Xqci extension: delete qc.flags CSR

Signed-off-by: Albert Yosher <[email protected]>

Author: ayosher

cfgs/qc_iu/arch_overlay/csr/Xqci/qc_flags.yaml

@@ -155,6 +155,7 @@ versions:
     - Rename qc.sllsat -> qc.shlusat
     - Add requirement to include Zca extension for Xqcisim since it has 16-bit instructions
     - Add requirement to include Zca extension for Xqcisync since it has 16-bit instructions
+    - Remove qc.flags CSR
   implies:
   - [Xqcia, "0.4.0"]
   - [Xqciac, "0.2.0"]
@@ -163,7 +164,7 @@ versions:
   - [Xqcicli, "0.2.0"]
   - [Xqcicm, "0.2.0"]
   - [Xqcics, "0.2.0"]
-  - [Xqcicsr, "0.2.0"]
+  - [Xqcicsr, "0.3.0"]
   - [Xqciint, "0.2.0"]
   - [Xqcilb, "0.2.0"]
   - [Xqcili, "0.2.0"]

cfgs/qc_iu/arch_overlay/ext/Xqci.yaml

@@ -28,6 +28,18 @@ versions:
     email: [email protected]
   changes:
     - Add information about instruction formats of each instruction
+- version: "0.3.0"
+  state: frozen
+  ratification_date: null
+  contributors:
+  - name: Albert Yosher
+    company: Qualcomm Technologies, Inc.
+    email: [email protected]
+  - name: Derek Hower
+    company: Qualcomm Technologies, Inc.
+    email: [email protected]
+  changes:
+    - Remove qc.flags CSR
 description: |
   The Xqcicsr extension contains two instructions to read/write CSR which index is in register and not immediate.
 

cfgs/qc_iu/arch_overlay/ext/Xqcicsr.yaml

@@ -25,7 +25,7 @@ operation(): |
   XReg mepc_val = CSR[mepc].sw_read();
   XReg mnepc_val = CSR[qc_mnepc].sw_read();
   XReg mcause_val = CSR[mcause].sw_read();
-  XReg flags_val = CSR[qc_flags].sw_read();
+  XReg reserved_val = 0;
   if (CSR[mcause].NMI != 1'b1) {
     write_memory<32>(virtual_address -  4, mepc_val, $encoding);
   } else {
@@ -34,7 +34,7 @@ operation(): |
   write_memory<32>(virtual_address -  8, X[ 8][31:0], $encoding);
   write_memory<32>(virtual_address - 12, mcause_val, $encoding);
   write_memory<32>(virtual_address - 16, X[ 1][31:0], $encoding);
-  write_memory<32>(virtual_address - 20, flags_val, $encoding);
+  write_memory<32>(virtual_address - 20, reserved_val, $encoding);
   write_memory<32>(virtual_address - 24, X[ 5][31:0], $encoding);
   write_memory<32>(virtual_address - 28, X[ 6][31:0], $encoding);
   write_memory<32>(virtual_address - 32, X[ 7][31:0], $encoding);

cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mienter.nest.yaml

@@ -27,7 +27,7 @@ operation(): |
   XReg mepc_val = CSR[mepc].sw_read();
   XReg mnepc_val = CSR[qc_mnepc].sw_read();
   XReg mcause_val = CSR[mcause].sw_read();
-  XReg flags_val = CSR[qc_flags].sw_read();
+  XReg reserved_val = 0;
   if (CSR[mcause].NMI != 1'b1) {
     write_memory<32>(virtual_address -  4, mepc_val, $encoding);
   } else {
@@ -36,7 +36,7 @@ operation(): |
   write_memory<32>(virtual_address -  8, X[ 8][31:0], $encoding);
   write_memory<32>(virtual_address - 12, mcause_val, $encoding);
   write_memory<32>(virtual_address - 16, X[ 1][31:0], $encoding);
-  write_memory<32>(virtual_address - 20, flags_val, $encoding);
+  write_memory<32>(virtual_address - 20, reserved_val, $encoding);
   write_memory<32>(virtual_address - 24, X[ 5][31:0], $encoding);
   write_memory<32>(virtual_address - 28, X[ 6][31:0], $encoding);
   write_memory<32>(virtual_address - 32, X[ 7][31:0], $encoding);

cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mienter.yaml

@@ -33,7 +33,6 @@ operation(): |
   X[ 8] = read_memory<32>(virtual_address -  8, $encoding);
   CSR[mcause].sw_write(read_memory<32>(virtual_address - 12, $encoding));
   X[ 1] = read_memory<32>(virtual_address - 16, $encoding);
-  CSR[qc_flags].sw_write(read_memory<32>(virtual_address - 20, $encoding));
   X[ 5] = read_memory<32>(virtual_address - 24, $encoding);
   X[ 6] = read_memory<32>(virtual_address - 28, $encoding);
   X[ 7] = read_memory<32>(virtual_address - 32, $encoding);