Xqci (Xqcibm) extension: Fix IDL code and description increasing shift to 6 bit for all dual-register bitfield extraction instructions, where shift and width of bitfield are in register

Signed-off-by: Albert Yosher <[email protected]>

Author: ayosher

arch_overlay/qc_iu/ext/Xqci.yaml

@@ -282,6 +282,9 @@ versions:
     - Fix IDL code sign extension logic for qc.e.lb and qc.e.lh instructions
     - Fix IDL code sign extension logic for qc.ext and qc.extd instructions
     - Fix IDL code sign extension logic for qc.extdpr, qc.extdprh and qc.extdr instructions
+    - Fix IDL code and description increasing shift to 6 bit for qc.extdr and qc.extdur instructions
+    - Fix IDL code and description increasing shift to 6 bit for qc.extdpr and qc.extdprh instructions
+    - Fix IDL code and description increasing shift to 6 bit for qc.extdupr and qc.extduprh instructions
     - Fix IDL code sign extension logic for qc.lieq instruction
   implies:
   - { name: Xqcia, version: "0.5.0" }

arch_overlay/qc_iu/ext/Xqcibm.yaml

@@ -101,6 +101,9 @@ versions:
   changes:
     - Fix IDL code sign extension logic for qc.ext and qc.extd instructions
     - Fix IDL code sign extension logic for qc.extdpr, qc.extdprh and qc.extdr instructions
+    - Fix IDL code and description increasing shift to 6 bit for qc.extdr and qc.extdur instructions
+    - Fix IDL code and description increasing shift to 6 bit for qc.extdpr and qc.extdprh instructions
+    - Fix IDL code and description increasing shift to 6 bit for qc.extdupr and qc.extduprh instructions
   requires: { name: Zca, version: ">= 1.0.0" }
 description: |
   The Xqcibm extension includes thirty eight instructions that perform bit manipulation,

arch_overlay/qc_iu/inst/Xqci/qc.extdpr.yaml

@@ -7,7 +7,7 @@ long_name: Extract bits from pair signed, packed descriptor (Register)
 description: |
   Extract a subset of bits from the register pair [`rs1`, `rs1`+1] into `rd`, and sign extend the result.
   The width of the subset is determined by `rs2` bits [13:8] (0..32),
-  and the offset of the subset is determined by `rs2` bits [4:0].
+  and the offset of the subset is determined by `rs2` bits [5:0] (0..63).
   In case when `rs2` bit [13] == 1 width is enforced to 32.
   In case when width == 0, to the destination register written 0.
   Instruction encoded in R instruction format.
@@ -38,7 +38,7 @@ operation(): |
   Bits<{1'b0, XLEN}*2> pair = {X[rs1 + 1], X[rs1]};
   XReg width_bits = X[rs2][13:8];
   XReg width = (width_bits > 32) ? 32 : width_bits;
-  XReg shamt = X[rs2][4:0];
+  XReg shamt = X[rs2][5:0];
   if (width > 0) {
     X[rd] = sext((pair >> shamt) & ((1 << width) - 1), width);
   } else {

arch_overlay/qc_iu/inst/Xqci/qc.extdprh.yaml

@@ -7,7 +7,7 @@ long_name: Extract bits from pair signed, packed descriptor high part (Register)
 description: |
   Extract a subset of bits from the register pair [`rs1`, `rs1`+1] into `rd`, and sign extend the result.
   The width of the subset is determined by `rs2` bits [29:24] (0..32),
-  and the offset of the subset is determined by `rs2` bits [20:16].
+  and the offset of the subset is determined by `rs2` bits [21:16] (0..63).
   In case when `rs2` bit [29] == 1 width is enforced to 32.
   In case when width == 0, to the destination register written 0.
   Instruction encoded in R instruction format.
@@ -38,7 +38,7 @@ operation(): |
   Bits<{1'b0, XLEN}*2> pair = {X[rs1 + 1], X[rs1]};
   XReg width_bits = X[rs2][29:24];
   XReg width = (width_bits > 32) ? 32 : width_bits;
-  XReg shamt = X[rs2][20:16];
+  XReg shamt = X[rs2][21:16];
   if (width > 0) {
     X[rd] = sext((pair >> shamt) & ((1 << width) - 1), width);
   } else {

arch_overlay/qc_iu/inst/Xqci/qc.extdr.yaml

@@ -7,7 +7,7 @@ long_name: Extract bits from pair signed (Register)
 description: |
   Extract a subset of bits from the register pair [`rs1`, `rs1`+1] into `rd`, and sign extend the result.
   The width of the subset is determined by `rs2` bits [21:16] (0..32),
-  and the offset of the subset is determined by `rs2` bits [4:0].
+  and the offset of the subset is determined by `rs2` bits [5:0] (0..63).
   In case when `rs2` bit [21] == 1 width is enforced to 32.
   In case when width == 0, to the destination register written 0.
   Instruction encoded in R instruction format.
@@ -38,7 +38,7 @@ operation(): |
   Bits<{1'b0, XLEN}*2> pair = {X[rs1 + 1], X[rs1]};
   XReg width_bits = X[rs2][21:16];
   XReg width = (width_bits > 32) ? 32 : width_bits;
-  XReg shamt = X[rs2][4:0];
+  XReg shamt = X[rs2][5:0];
   if (width > 0) {
     X[rd] = sext((pair >> shamt) & ((1 << width) - 1), width);
   } else {

arch_overlay/qc_iu/inst/Xqci/qc.extdupr.yaml

@@ -7,7 +7,7 @@ long_name: Extract bits from pair unsigned, packed descriptor (Register)
 description: |
   Extract a subset of bits from the register pair [`rs1`, `rs1`+1] into `rd`.
   The width of the subset is determined by `rs2` bits [13:8] (0..32),
-  and the offset of the subset is determined by `rs2` bits [4:0].
+  and the offset of the subset is determined by `rs2` bits [5:0] (0..63).
   In case when `rs2` bit [13] == 1 width is enforced to 32.
   In case when width == 0, to the destination register written 0.
   Instruction encoded in R instruction format.
@@ -38,7 +38,7 @@ operation(): |
   Bits<{1'b0, XLEN}*2> pair = {X[rs1 + 1], X[rs1]};
   XReg width_bits = X[rs2][13:8];
   XReg width = (width_bits > 32) ? 32 : width_bits;
-  XReg shamt = X[rs2][4:0];
+  XReg shamt = X[rs2][5:0];
   if (width > 0) {
     X[rd] = (pair >> shamt) & ((1 << width) - 1);
   } else {

arch_overlay/qc_iu/inst/Xqci/qc.extduprh.yaml

@@ -7,7 +7,7 @@ long_name: Extract bits from pair unsigned, packed descriptor high part (Registe
 description: |
   Extract a subset of bits from the register pair [`rs1`, `rs1`+1] into `rd`.
   The width of the subset is determined by `rs2` bits [29:24] (0..32),
-  and the offset of the subset is determined by `rs2` bits [20:16].
+  and the offset of the subset is determined by `rs2` bits [21:16] (0..63).
   In case when `rs2` bit [29] == 1 width is enforced to 32.
   In case when width == 0, to the destination register written 0.
   Instruction encoded in R instruction format.
@@ -38,7 +38,7 @@ operation(): |
   Bits<{1'b0, XLEN}*2> pair = {X[rs1 + 1], X[rs1]};
   XReg width_bits = X[rs2][29:24];
   XReg width = (width_bits > 32) ? 32 : width_bits;
-  XReg shamt = X[rs2][20:16];
+  XReg shamt = X[rs2][21:16];
   if (width > 0) {
     X[rd] = (pair >> shamt) & ((1 << width) - 1);
   } else {

arch_overlay/qc_iu/inst/Xqci/qc.extdur.yaml

@@ -7,7 +7,7 @@ long_name: Extract bits from pair unsigned (Register)
 description: |
   Extract a subset of bits from the register pair [`rs1`, `rs1`+1] into `rd`.
   The width of the subset is determined by `rs2` bits [21:16] (0..32),
-  and the offset of the subset is determined by `rs2` bits [4:0].
+  and the offset of the subset is determined by `rs2` bits [5:0] (0..63).
   In case when `rs2` bit [21] == 1 width is enforced to 32.
   In case when width == 0, to the destination register written 0.
   Instruction encoded in R instruction format.
@@ -38,7 +38,7 @@ operation(): |
   Bits<{1'b0, XLEN}*2> pair = {X[rs1 + 1], X[rs1]};
   XReg width_bits = X[rs2][21:16];
   XReg width = (width_bits > 32) ? 32 : width_bits;
-  XReg shamt = X[rs2][4:0];
+  XReg shamt = X[rs2][5:0];
   if (width > 0) {
     X[rd] = (pair >> shamt) & ((1 << width) - 1);
   } else {