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Additional fixes for Xqci v0.11.0 (#729)
changes: - Fix IDL code of qc.shlusat instruction (should use zero-extension and not sign-extension) - Fix IDL code of qc.shlusat and qc.shlsat instructions (should compare values of xlen()*2 bits) - Fix IDL code of qc.shlusat and qc.shlsat instructions because change in IDL operators (width adjustment) - Fix IDL code of qc.subsat, qc.addusat and qc.addsat instructions because change in IDL operators (width adjustment) - Fix IDL code for qc.c.mileaveret, qc.c.mnret and qc.c.mret instructions because change in IDL '<<' operator - Fix IDL code for qc.c.clrint, qc.c.setint, qc.clrinti and qc.setinti instructions because change in IDL '<<' operator - Fix IDL code for qc.c.di, qc.c.dir, qc.c.ei, qc.c.eir and qc.c.mienter.nest instructions because change in IDL '<<' operator - Fix IDL code for qc.c.sync, qc.c.syncr, qc.c.syncwf and qc.c.syncwl instructions because change in IDL '<<' operator - Fix IDL code for qc.c.bseti, qc.c.extu, qc.ext and qc.extu instructions because change in IDL '<<' operator - Fix IDL code for qc.extd, qc.extdu, qc.extdr and qc.extdur instructions because change in IDL '<<' operator - Fix IDL code for qc.extdpr, qc.extdprh, qc.extdupr and qc.extduprh instructions because change in IDL '<<' operator - Fix IDL code for qc.insb, qc.insbi, qc.insbr and qc.insbri instructions because change in IDL '<<' operator - Fix IDL code for qc.insbh, qc.insbhr, qc.insbpr and qc.insbprh instructions because change in IDL '<<' operator --------- Signed-off-by: Albert Yosher <[email protected]>
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‎arch_overlay/qc_iu/ext/Xqci.yaml‎

Lines changed: 14 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -358,11 +358,23 @@ versions:
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email: [email protected]
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changes:
360360
- Fix IDL code of qc.shlusat instruction (should use zero-extension and not sign-extension)
361+
- Fix IDL code of qc.shlusat and qc.shlsat instructions (should compare values of xlen()*2 bits)
362+
- Fix IDL code of qc.shlusat and qc.shlsat instructions because change in IDL operators (width adjustment)
363+
- Fix IDL code of qc.subsat, qc.addusat and qc.addsat instructions because change in IDL operators (width adjustment)
364+
- Fix IDL code for qc.c.mileaveret, qc.c.mnret and qc.c.mret instructions because change in IDL '<<' operator
365+
- Fix IDL code for qc.c.clrint, qc.c.setint, qc.clrinti and qc.setinti instructions because change in IDL '<<' operator
366+
- Fix IDL code for qc.c.di, qc.c.dir, qc.c.ei, qc.c.eir and qc.c.mienter.nest instructions because change in IDL '<<' operator
367+
- Fix IDL code for qc.c.sync, qc.c.syncr, qc.c.syncwf and qc.c.syncwl instructions because change in IDL '<<' operator
368+
- Fix IDL code for qc.c.bseti, qc.c.extu, qc.ext and qc.extu instructions because change in IDL '<<' operator
369+
- Fix IDL code for qc.extd, qc.extdu, qc.extdr and qc.extdur instructions because change in IDL '<<' operator
370+
- Fix IDL code for qc.extdpr, qc.extdprh, qc.extdupr and qc.extduprh instructions because change in IDL '<<' operator
371+
- Fix IDL code for qc.insb, qc.insbi, qc.insbr and qc.insbri instructions because change in IDL '<<' operator
372+
- Fix IDL code for qc.insbh, qc.insbhr, qc.insbpr and qc.insbprh instructions because change in IDL '<<' operator
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implies:
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- { name: Xqcia, version: "0.7.0" }
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- { name: Xqciac, version: "0.3.0" }
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- { name: Xqcibi, version: "0.2.0" }
365-
- { name: Xqcibm, version: "0.7.0" }
377+
- { name: Xqcibm, version: "0.8.0" }
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- { name: Xqcicli, version: "0.3.0" }
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- { name: Xqcicm, version: "0.2.0" }
368380
- { name: Xqcics, version: "0.2.0" }
@@ -376,7 +388,7 @@ versions:
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- { name: Xqcilsm, version: "0.5.0" }
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- { name: Xqcisim, version: "0.2.0" }
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- { name: Xqcisls, version: "0.2.0" }
379-
- { name: Xqcisync, version: "0.2.0" }
391+
- { name: Xqcisync, version: "0.3.0" }
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requires:
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name: Zca
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version: ">= 1.0.0"

‎arch_overlay/qc_iu/ext/Xqcia.yaml‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -92,6 +92,9 @@ versions:
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email: [email protected]
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changes:
9494
- Fix IDL code of qc.shlusat instruction (should use zero-extension and not sign-extension)
95+
- Fix IDL code of qc.shlusat and qc.shlsat instructions (should compare values of xlen()*2 bits)
96+
- Fix IDL code of qc.shlusat and qc.shlsat instructions because change in IDL operators (width adjustment)
97+
- Fix IDL code of qc.subsat, qc.addusat and qc.addsat instructions because change in IDL operators (width adjustment)
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description: |
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The Xqcia extension includes eleven instructions to perform integer arithmetic.
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‎arch_overlay/qc_iu/ext/Xqcibm.yaml‎

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Original file line numberDiff line numberDiff line change
@@ -105,6 +105,23 @@ versions:
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- Fix IDL code and description increasing shift to 6 bit for qc.extdpr and qc.extdprh instructions
106106
- Fix IDL code and description increasing shift to 6 bit for qc.extdupr and qc.extduprh instructions
107107
requires: { name: Zca, version: ">= 1.0.0" }
108+
- version: "0.8.0"
109+
state: frozen
110+
ratification_date: null
111+
contributors:
112+
- name: Albert Yosher
113+
company: Qualcomm Technologies, Inc.
114+
email: [email protected]
115+
- name: Derek Hower
116+
company: Qualcomm Technologies, Inc.
117+
email: [email protected]
118+
changes:
119+
- Fix IDL code for qc.c.bseti, qc.c.extu, qc.ext and qc.extu instructions because change in IDL '<<' operator
120+
- Fix IDL code for qc.extd, qc.extdu, qc.extdr and qc.extdur instructions because change in IDL '<<' operator
121+
- Fix IDL code for qc.extdpr, qc.extdprh, qc.extdupr and qc.extduprh instructions because change in IDL '<<' operator
122+
- Fix IDL code for qc.insb, qc.insbi, qc.insbr and qc.insbri instructions because change in IDL '<<' operator
123+
- Fix IDL code for qc.insbh, qc.insbhr, qc.insbpr and qc.insbprh instructions because change in IDL '<<' operator
124+
requires: { name: Zca, version: ">= 1.0.0" }
108125
description: |
109126
The Xqcibm extension includes thirty eight instructions that perform bit manipulation,
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include insertion and extraction.

‎arch_overlay/qc_iu/ext/Xqciint.yaml‎

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -106,6 +106,21 @@ versions:
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changes:
107107
- Fix IDL code for Smdbltrp and Smrnmi spec compatibility for qc.c.mileaveret instruction
108108
requires: { name: Zca, version: ">= 1.0.0" }
109+
- version: "0.8.0"
110+
state: frozen
111+
ratification_date: null
112+
contributors:
113+
- name: Albert Yosher
114+
company: Qualcomm Technologies, Inc.
115+
email: [email protected]
116+
- name: Derek Hower
117+
company: Qualcomm Technologies, Inc.
118+
email: [email protected]
119+
changes:
120+
- Fix IDL code for qc.c.mileaveret, qc.c.mnret and qc.c.mret instructions because change in IDL '<<' operator
121+
- Fix IDL code for qc.c.clrint, qc.c.setint, qc.clrinti and qc.setinti instructions because change in IDL '<<' operator
122+
- Fix IDL code for qc.c.di, qc.c.dir, qc.c.ei, qc.c.eir and qc.c.mienter.nest instructions because change in IDL '<<' operator
123+
requires: { name: Zca, version: ">= 1.0.0" }
109124
description: |
110125
The Xqciint extension includes eleven instructions to accelerate interrupt
111126
servicing by performing common actions during ISR prologue/epilogue.

‎arch_overlay/qc_iu/ext/Xqcisync.yaml‎

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -30,6 +30,19 @@ versions:
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- Fix decoding of qc.c.delay instruction (state that immediate cannot be 0)
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- Add requirement to include Zca extension since has 16-bit instructions
3232
requires: { name: Zca, version: ">= 1.0.0" }
33+
- version: "0.3.0"
34+
state: frozen
35+
ratification_date: null
36+
contributors:
37+
- name: Albert Yosher
38+
company: Qualcomm Technologies, Inc.
39+
email: [email protected]
40+
- name: Derek Hower
41+
company: Qualcomm Technologies, Inc.
42+
email: [email protected]
43+
changes:
44+
- Fix IDL code for qc.c.sync, qc.c.syncr, qc.c.syncwf and qc.c.syncwl instructions because change in IDL '<<' operator
45+
requires: { name: Zca, version: ">= 1.0.0" }
3346
description: |
3447
The Xqcisync extension includes nine instructions, eight for non-memory-mapped devices synchronization and delay instruction.
3548
Synchronization instructions are kind of IO fences that work with special devices synchronization signals.

‎arch_overlay/qc_iu/inst/Xqci/qc.addsat.yaml‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -31,9 +31,9 @@ access:
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vs: always
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vu: always
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operation(): |
34-
XReg sum = X[rs1] + X[rs2];
35-
XReg most_negative_number = 1 << (xlen() - 1);
36-
XReg most_positive_number = (1 << (xlen() - 1)) - 1;
34+
Bits<xlen()+1> sum = X[rs1] `+ X[rs2];
35+
Bits<xlen()+1> most_negative_number = {2'b11,{(xlen()-1){1'b0}}};
36+
Bits<xlen()+1> most_positive_number = {2'b00,{(xlen()-1){1'b1}}};
3737
# overflow occurs if the operands are the same sign and the result is a different sign
3838
if (X[rs1][xlen()-1] == X[rs2][xlen()-1]) {
3939
if (sum[xlen()-1] != X[rs1][xlen()-1]) {
@@ -45,4 +45,4 @@ operation(): |
4545
}
4646
}
4747
# otherwise, overflow did not occur
48-
X[rd] = sum;
48+
X[rd] = sum[(xlen() - 1):0];

‎arch_overlay/qc_iu/inst/Xqci/qc.addusat.yaml‎

Lines changed: 6 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -31,14 +31,11 @@ access:
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vs: always
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vu: always
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operation(): |
34-
XReg sum = X[rs1] + X[rs2];
34+
Bits<xlen()+1> sum = X[rs1] `+ X[rs2];
35+
Bits<xlen()+1> largest_unsigned_value = {1'b0, {xlen(){1'b1}}};
3536
36-
# overflow occurs if the msb of at least one operand is 1 and the msb of the sum is not
37-
if ((X[rs1][xlen()-1] == 1) || (X[rs2][xlen()-1] == 1)) {
38-
if (sum[xlen()-1] == 0) {
39-
sum = ~{MXLEN{1'b0}}; # return largest number
40-
}
37+
if (sum > largest_unsigned_value) {
38+
X[rd] = largest_unsigned_value[(xlen() - 1):0];
39+
} else {
40+
X[rd] = sum[(xlen() - 1):0];
4141
}
42-
43-
# otherwise, overflow did not occur
44-
X[rd] = sum;

‎arch_overlay/qc_iu/inst/Xqci/qc.c.bseti.yaml‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -30,4 +30,4 @@ access:
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operation(): |
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XReg index = shamt & (xlen() - 1);
3232
XReg reg = creg2reg(rd);
33-
X[reg] = X[reg] | (1 << index);
33+
X[reg] = X[reg] | (MXLEN'b1 << index);

‎arch_overlay/qc_iu/inst/Xqci/qc.c.clrint.yaml‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -30,4 +30,4 @@ operation(): |
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XReg idx = rs1 / 32;
3131
XReg bit = rs1 % 32;
3232
Csr pre_csr = direct_csr_lookup(MCLICIP0_ADDR + idx);
33-
csr_sw_write(pre_csr, csr_sw_read(pre_csr) & ~(1 << bit));
33+
csr_sw_write(pre_csr, csr_sw_read(pre_csr) & ~(32'b1 << bit));

‎arch_overlay/qc_iu/inst/Xqci/qc.c.di.yaml‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -24,4 +24,4 @@ access:
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operation(): |
2525
CSR[mstatus].MIE = 0;
2626
XReg pre_qc_mcause = CSR[qc.mcause].sw_read();
27-
CSR[qc.mcause].sw_write(pre_qc_mcause & ~(1<<26));
27+
CSR[qc.mcause].sw_write(pre_qc_mcause & ~(32'b1<<26));

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