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ShehrozkashifShehrozkashif
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fix(ci): update golden instructions appendix to fix failing test
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‎backends/instructions_appendix/all_instructions.golden.adoc‎

Lines changed: 113 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
= Instruction Appendix
22
:doctype: book
3-
:wavedrom: /workspace/riscv-unified-db/node_modules/.bin/wavedrom-cli
3+
:wavedrom: /workspaces/riscv-unified-db/node_modules/.bin/wavedrom-cli
44
// Now the document header is complete and the wavedrom attribute is active.
55

66

@@ -3996,25 +3996,48 @@ Synopsis::
39963996
Load double
39973997

39983998
Encoding::
3999+
[NOTE]
4000+
This instruction has different encodings in RV32 and RV64
4001+
4002+
RV32::
39994003
[wavedrom, ,svg,subs='attributes',width="100%"]
40004004
....
4001-
{"reg":[{"bits":2,"name": 0x0,"type":2},{"bits":3,"name": "rd","type":4},{"bits":2,"name": "imm[7:6]","type":4},{"bits":3,"name": "rs1","type":4},{"bits":3,"name": "imm[5:3]","type":4},{"bits":3,"name": 0x3,"type":2}]}
4005+
{"reg":[{"bits":2,"name": 0x0,"type":2},{"bits":3,"name": "xd != {1,3,5,7}","type":4},{"bits":2,"name": "imm[7:6]","type":4},{"bits":3,"name": "xs1","type":4},{"bits":3,"name": "imm[5:3]","type":4},{"bits":3,"name": 0x3,"type":2}]}
4006+
....
4007+
4008+
RV64::
4009+
[wavedrom, ,svg,subs='attributes',width="100%"]
4010+
....
4011+
{"reg":[{"bits":2,"name": 0x0,"type":2},{"bits":3,"name": "xd","type":4},{"bits":2,"name": "imm[7:6]","type":4},{"bits":3,"name": "xs1","type":4},{"bits":3,"name": "imm[5:3]","type":4},{"bits":3,"name": 0x3,"type":2}]}
40024012
....
40034013

40044014
Description::
4005-
Loads a 64-bit value from memory into register rd.
4015+
Loads a 64-bit value from memory into register xd.
40064016
It computes an effective address by adding the zero-extended offset, scaled by 8,
4007-
to the base address in register rs1.
4008-
It expands to xref:insts:ld.adoc#udb:doc:inst:ld[ld] `rd, offset(rs1)`.
4017+
to the base address in register xs1.
4018+
It expands to xref:insts:ld.adoc#udb:doc:inst:ld[ld] `xd, offset(xs1)`.
4019+
For RV32, if the Zclsd extension is enabled, this instruction loads a 64-bit value into registers xd and xd+1. It computes an effective address by adding the zero-extended imm, scaled by 8, to the base address in register xs1.
40094020

40104021

40114022
Decode Variables::
4023+
*RV32:*
4024+
40124025
[width="100%", cols="1,2", options="header"]
40134026
|===
40144027
|Variable Name |Location
40154028
|imm |{$encoding[6:5], $encoding[12:10], 3'd0}
4016-
|rd |$encoding[4:2]
4017-
|rs1 |$encoding[9:7]
4029+
|xd |$encoding[4:2]
4030+
|xs1 |$encoding[9:7]
4031+
|===
4032+
4033+
*RV64:*
4034+
4035+
[width="100%", cols="1,2", options="header"]
4036+
|===
4037+
|Variable Name |Location
4038+
|imm |{$encoding[6:5], $encoding[12:10], 3'd0}
4039+
|xd |$encoding[4:2]
4040+
|xs1 |$encoding[9:7]
40184041
|===
40194042

40204043
Included in::
@@ -4026,6 +4049,8 @@ Included in::
40264049

40274050
| *Zca* | ~> 1.0.0
40284051

4052+
| *Zclsd* | ~> 1.0
4053+
40294054
|===
40304055

40314056

@@ -4036,26 +4061,47 @@ Synopsis::
40364061
Load doubleword from stack pointer
40374062

40384063
Encoding::
4064+
[NOTE]
4065+
This instruction has different encodings in RV32 and RV64
4066+
4067+
RV32::
40394068
[wavedrom, ,svg,subs='attributes',width="100%"]
40404069
....
4041-
{"reg":[{"bits":2,"name": 0x2,"type":2},{"bits":5,"name": "imm[4:3|8:6]","type":4},{"bits":5,"name": "rd != 0","type":4},{"bits":1,"name": "imm[5]","type":4},{"bits":3,"name": 0x3,"type":2}]}
4070+
{"reg":[{"bits":2,"name": 0x2,"type":2},{"bits":5,"name": "imm[4:3|8:6]","type":4},{"bits":5,"name": "xd != {0,1,3,5,7}","type":4},{"bits":1,"name": "imm[5]","type":4},{"bits":3,"name": 0x3,"type":2}]}
4071+
....
4072+
4073+
RV64::
4074+
[wavedrom, ,svg,subs='attributes',width="100%"]
4075+
....
4076+
{"reg":[{"bits":2,"name": 0x2,"type":2},{"bits":5,"name": "imm[4:3|8:6]","type":4},{"bits":5,"name": "xd","type":4},{"bits":1,"name": "imm[5]","type":4},{"bits":3,"name": 0x3,"type":2}]}
40424077
....
40434078

40444079
Description::
40454080
C.LDSP is an RV64C/RV128C-only instruction that loads a 64-bit value from memory
4046-
into register rd.
4081+
into register xd.
40474082
It computes its effective address by adding the zero-extended offset, scaled by 8,
40484083
to the stack pointer, x2.
4049-
It expands to xref:insts:ld.adoc#udb:doc:inst:ld[ld] `rd, offset(x2)`.
4050-
C.LDSP is only valid when rd ≠ x0 the code points with rd=x0 are reserved.
4084+
It expands to `ld xd, offset(x2)`.
4085+
C.LDSP is only valid when xd ≠ x0; code points with xd=x0 are reserved.
40514086

40524087

40534088
Decode Variables::
4089+
*RV32:*
4090+
40544091
[width="100%", cols="1,2", options="header"]
40554092
|===
40564093
|Variable Name |Location
40574094
|imm |{$encoding[4:2], $encoding[12], $encoding[6:5], 3'd0}
4058-
|rd |$encoding[11:7]
4095+
|xd |$encoding[11:7]
4096+
|===
4097+
4098+
*RV64:*
4099+
4100+
[width="100%", cols="1,2", options="header"]
4101+
|===
4102+
|Variable Name |Location
4103+
|imm |{$encoding[4:2], $encoding[12], $encoding[6:5], 3'd0}
4104+
|xd |$encoding[11:7]
40594105
|===
40604106

40614107
Included in::
@@ -4561,25 +4607,47 @@ Synopsis::
45614607
Store double
45624608

45634609
Encoding::
4610+
[NOTE]
4611+
This instruction has different encodings in RV32 and RV64
4612+
4613+
RV32::
45644614
[wavedrom, ,svg,subs='attributes',width="100%"]
45654615
....
4566-
{"reg":[{"bits":2,"name": 0x0,"type":2},{"bits":3,"name": "rs2","type":4},{"bits":2,"name": "imm[7:6]","type":4},{"bits":3,"name": "rs1","type":4},{"bits":3,"name": "imm[5:3]","type":4},{"bits":3,"name": 0x7,"type":2}]}
4616+
{"reg":[{"bits":2,"name": 0x0,"type":2},{"bits":3,"name": "xs2 != {1,3,5,7}","type":4},{"bits":2,"name": "imm[7:6]","type":4},{"bits":3,"name": "xs1","type":4},{"bits":3,"name": "imm[5:3]","type":4},{"bits":3,"name": 0x7,"type":2}]}
4617+
....
4618+
4619+
RV64::
4620+
[wavedrom, ,svg,subs='attributes',width="100%"]
4621+
....
4622+
{"reg":[{"bits":2,"name": 0x0,"type":2},{"bits":3,"name": "xs2","type":4},{"bits":2,"name": "imm[7:6]","type":4},{"bits":3,"name": "xs1","type":4},{"bits":3,"name": "imm[5:3]","type":4},{"bits":3,"name": 0x7,"type":2}]}
45674623
....
45684624

45694625
Description::
4570-
Stores a 64-bit value in register rs2 to memory.
4626+
Stores a 64-bit value in register xs2 to memory.
45714627
It computes an effective address by adding the zero-extended offset, scaled by 8,
4572-
to the base address in register rs1.
4573-
It expands to xref:insts:sd.adoc#udb:doc:inst:sd[sd] `rs2, offset(rs1)`.
4628+
to the base address in register xs1.
4629+
It expands to xref:insts:sd.adoc#udb:doc:inst:sd[sd] `xs2, offset(xs1)`.
45744630

45754631

45764632
Decode Variables::
4633+
*RV32:*
4634+
45774635
[width="100%", cols="1,2", options="header"]
45784636
|===
45794637
|Variable Name |Location
45804638
|imm |{$encoding[6:5], $encoding[12:10], 3'd0}
4581-
|rs2 |$encoding[4:2]
4582-
|rs1 |$encoding[9:7]
4639+
|xs2 |$encoding[4:2]
4640+
|xs1 |$encoding[9:7]
4641+
|===
4642+
4643+
*RV64:*
4644+
4645+
[width="100%", cols="1,2", options="header"]
4646+
|===
4647+
|Variable Name |Location
4648+
|imm |{$encoding[6:5], $encoding[12:10], 3'd0}
4649+
|xs2 |$encoding[4:2]
4650+
|xs1 |$encoding[9:7]
45834651
|===
45844652

45854653
Included in::
@@ -4591,6 +4659,8 @@ Included in::
45914659

45924660
| *Zca* | ~> 1.0.0
45934661

4662+
| *Zclsd* | ~> 1.0
4663+
45944664
|===
45954665

45964666

@@ -4601,9 +4671,19 @@ Synopsis::
46014671
Store doubleword to stack
46024672

46034673
Encoding::
4674+
[NOTE]
4675+
This instruction has different encodings in RV32 and RV64
4676+
4677+
RV32::
46044678
[wavedrom, ,svg,subs='attributes',width="100%"]
46054679
....
4606-
{"reg":[{"bits":2,"name": 0x2,"type":2},{"bits":5,"name": "rs2","type":4},{"bits":6,"name": "imm[5:3|8:6]","type":4},{"bits":3,"name": 0x7,"type":2}]}
4680+
{"reg":[{"bits":2,"name": 0x2,"type":2},{"bits":5,"name": "xs2 != {1,3,5,7}","type":4},{"bits":6,"name": "imm[5:3|8:6]","type":4},{"bits":3,"name": 0x7,"type":2}]}
4681+
....
4682+
4683+
RV64::
4684+
[wavedrom, ,svg,subs='attributes',width="100%"]
4685+
....
4686+
{"reg":[{"bits":2,"name": 0x2,"type":2},{"bits":5,"name": "xs2","type":4},{"bits":6,"name": "imm[5:3|8:6]","type":4},{"bits":3,"name": 0x7,"type":2}]}
46074687
....
46084688

46094689
Description::
@@ -4614,11 +4694,22 @@ It expands to xref:insts:sd.adoc#udb:doc:inst:sd[sd] `rs2, offset(x2)`.
46144694

46154695

46164696
Decode Variables::
4697+
*RV32:*
4698+
46174699
[width="100%", cols="1,2", options="header"]
46184700
|===
46194701
|Variable Name |Location
4702+
|xs2 |$encoding[6:2]
4703+
|imm |{$encoding[9:7], $encoding[12:10], 3'd0}
4704+
|===
4705+
4706+
*RV64:*
4707+
4708+
[width="100%", cols="1,2", options="header"]
4709+
|===
4710+
|Variable Name |Location
4711+
|xs2 |$encoding[6:2]
46204712
|imm |{$encoding[9:7], $encoding[12:10], 3'd0}
4621-
|rs2 |$encoding[6:2]
46224713
|===
46234714

46244715
Included in::
@@ -4630,6 +4721,8 @@ Included in::
46304721

46314722
| *Zca* | ~> 1.0.0
46324723

4724+
| *Zclsd* | ~> 1.0
4725+
46334726
|===
46344727

46354728

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