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Merge pull request #333 from riscv-software-src/Zcb
Zcb spec support initial add
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‎arch/ext/Zcb.yaml‎

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# yaml-language-server: $schema=../../schemas/ext_schema.json
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$schema: "ext_schema.json#"
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kind: extension
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name: Zcb
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long_name: Simple code-size saving instructions
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description: |
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Zcb has simple code-size saving instructions which are easy to implement on all CPUs.
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All proposed encodings are currently reserved for all architectures, and have no conflicts with any existing extensions.
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The Zcb extension depends on the Zca extension.
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As shown on the individual instruction pages, many of the instructions in Zcb depend upon another extension being implemented.
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For example, c.mul is only implemented if M or Zmmul is implemented, and c.sext.b is only implemented if Zbb is implemented.
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type: unprivileged
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company:
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name: RISC-V International
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url: https://riscv.org
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versions:
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- version: "1.0.0"
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state: ratified
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ratification_date: 2023-04
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repositories:
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- url: https://github.com/riscv/riscv-code-size-reduction
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branch: main
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contributors:
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- name: Tariq Kurd
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- name: Ibrahim Abu Kharmeh
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- name: Torbjørn Viem Ness
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- name: Matteo Perotti
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- name: Nidal Faour
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- name: Bill Traynor
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- name: Rafael Sene
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- name: Xinlong Wu
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- name: sinan
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- name: Jeremy Bennett
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- name: Heda Chen
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- name: Alasdair Armstrong
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- name: Graeme Smecher
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- name: Nicolas Brunie
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- name: Jiawei

‎arch/inst/Zcb/c.lbu.yaml‎

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# yaml-language-server: $schema=../../../schemas/inst_schema.json
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$schema: "inst_schema.json#"
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kind: instruction
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name: c.lbu
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long_name: Load unsigned byte, 16-bit encoding
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description: |
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Loads a 8-bit value from memory into register rd.
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It computes an effective address by adding the zero-extended offset, to the base address in register rs1.
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It expands to `lbu` `rd, offset(rs1)`.
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definedBy:
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anyOf:
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- Zcb
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- Zce
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assembly: xd, imm(xs1)
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encoding:
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match: 100000--------00
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variables:
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- name: imm
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location: 5|6
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- name: rd
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location: 4-2
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- name: rs1
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location: 9-7
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access:
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s: always
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u: always
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vs: always
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vu: always
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operation(): |
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if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
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raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
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}
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XReg virtual_address = X[rs1+8] + imm;
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X[rd+8] = zext(read_memory<8>(virtual_address, $encoding), 8);
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sail(): |
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{
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let offset : xlenbits = zero_extend(imm);
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/* Get the address, X(rs1c) + offset.
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Some extensions perform additional checks on address validity. */
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match ext_data_get_addr(rs1c, offset, Read(Data), width) {
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Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL },
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Ext_DataAddr_OK(vaddr) =>
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if check_misaligned(vaddr, width)
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then { handle_mem_exception(vaddr, E_Load_Addr_Align()); RETIRE_FAIL }
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else match translateAddr(vaddr, Read(Data)) {
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TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },
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TR_Address(paddr, _) =>
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match (width) {
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BYTE =>
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process_load(rdc, vaddr, mem_read(Read(Data), paddr, 1, aq, rl, false), is_unsigned),
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HALF =>
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process_load(rdc, vaddr, mem_read(Read(Data), paddr, 2, aq, rl, false), is_unsigned),
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WORD =>
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process_load(rdc, vaddr, mem_read(Read(Data), paddr, 4, aq, rl, false), is_unsigned),
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DOUBLE if sizeof(xlen) >= 64 =>
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process_load(rdc, vaddr, mem_read(Read(Data), paddr, 8, aq, rl, false), is_unsigned),
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_ => report_invalid_width(__FILE__, __LINE__, width, "load")
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}
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}
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}
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}

‎arch/inst/Zcb/c.lh.yaml‎

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# yaml-language-server: $schema=../../../schemas/inst_schema.json
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$schema: "inst_schema.json#"
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kind: instruction
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name: c.lh
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long_name: Load signed halfword, 16-bit encoding
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description: |
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Loads a 16-bit value from memory into register rd.
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It computes an effective address by adding the zero-extended offset, to the base address in register rs1.
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It expands to `lh` `rd, offset(rs1)`.
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definedBy:
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anyOf:
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- Zcb
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- Zce
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assembly: xd, imm(xs1)
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encoding:
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match: 100001---1----00
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variables:
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- name: imm
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location: 5
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left_shift: 1
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- name: rd
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location: 4-2
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- name: rs1
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location: 9-7
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access:
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s: always
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u: always
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vs: always
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vu: always
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operation(): |
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if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
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raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
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}
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XReg virtual_address = X[rs1+8] + imm;
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X[rd+8] = sext(read_memory<16>(virtual_address, $encoding), 16);
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sail(): |
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{
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let offset : xlenbits = zero_extend(imm);
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/* Get the address, X(rs1c) + offset.
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Some extensions perform additional checks on address validity. */
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match ext_data_get_addr(rs1c, offset, Read(Data), width) {
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Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL },
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Ext_DataAddr_OK(vaddr) =>
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if check_misaligned(vaddr, width)
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then { handle_mem_exception(vaddr, E_Load_Addr_Align()); RETIRE_FAIL }
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else match translateAddr(vaddr, Read(Data)) {
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TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },
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TR_Address(paddr, _) =>
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match (width) {
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BYTE =>
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process_load(rdc, vaddr, mem_read(Read(Data), paddr, 1, aq, rl, false), is_unsigned),
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HALF =>
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process_load(rdc, vaddr, mem_read(Read(Data), paddr, 2, aq, rl, false), is_unsigned),
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WORD =>
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process_load(rdc, vaddr, mem_read(Read(Data), paddr, 4, aq, rl, false), is_unsigned),
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DOUBLE if sizeof(xlen) >= 64 =>
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process_load(rdc, vaddr, mem_read(Read(Data), paddr, 8, aq, rl, false), is_unsigned),
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_ => report_invalid_width(__FILE__, __LINE__, width, "load")
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}
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}
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}
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}

‎arch/inst/Zcb/c.lhu.yaml‎

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# yaml-language-server: $schema=../../../schemas/inst_schema.json
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$schema: "inst_schema.json#"
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kind: instruction
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name: c.lhu
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long_name: Load unsigned halfword, 16-bit encoding
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description: |
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Loads a 16-bit value from memory into register rd.
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It computes an effective address by adding the zero-extended offset, to the base address in register rs1.
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It expands to `lhu` `rd, offset(rs1)`.
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definedBy:
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anyOf:
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- Zcb
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- Zce
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assembly: xd, imm(xs1)
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encoding:
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match: 100001---0----00
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variables:
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- name: imm
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location: 5
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left_shift: 1
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- name: rd
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location: 4-2
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- name: rs1
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location: 9-7
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access:
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s: always
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u: always
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vs: always
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vu: always
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operation(): |
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if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
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raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
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}
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XReg virtual_address = X[rs1+8] + imm;
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X[rd+8] = zext(read_memory<16>(virtual_address, $encoding), 16);
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sail(): |
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{
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let offset : xlenbits = zero_extend(imm);
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/* Get the address, X(rs1c) + offset.
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Some extensions perform additional checks on address validity. */
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match ext_data_get_addr(rs1c, offset, Read(Data), width) {
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Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL },
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Ext_DataAddr_OK(vaddr) =>
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if check_misaligned(vaddr, width)
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then { handle_mem_exception(vaddr, E_Load_Addr_Align()); RETIRE_FAIL }
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else match translateAddr(vaddr, Read(Data)) {
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TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },
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TR_Address(paddr, _) =>
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match (width) {
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BYTE =>
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process_load(rdc, vaddr, mem_read(Read(Data), paddr, 1, aq, rl, false), is_unsigned),
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HALF =>
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process_load(rdc, vaddr, mem_read(Read(Data), paddr, 2, aq, rl, false), is_unsigned),
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WORD =>
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process_load(rdc, vaddr, mem_read(Read(Data), paddr, 4, aq, rl, false), is_unsigned),
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DOUBLE if sizeof(xlen) >= 64 =>
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process_load(rdc, vaddr, mem_read(Read(Data), paddr, 8, aq, rl, false), is_unsigned),
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_ => report_invalid_width(__FILE__, __LINE__, width, "load")
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}
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}
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}
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}

‎arch/inst/Zcb/c.mul.yaml‎

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# yaml-language-server: $schema=../../../schemas/inst_schema.json
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$schema: "inst_schema.json#"
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kind: instruction
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name: c.mul
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long_name: Multiply, 16-bit encoding
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description: |
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This instruction multiplies XLEN bits of the source operands from rsd' and rs2' and writes the lowest XLEN bits of the result to rsd'.
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definedBy:
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allOf:
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- Zcb
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- Zmmul
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assembly: xd, xs2
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encoding:
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match: 100111---10---01
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variables:
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- name: rd
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location: 9-7
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- name: rs2
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location: 4-2
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access:
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s: always
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u: always
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vs: always
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vu: always
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operation(): |
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if (implemented?(ExtensionName::M) && (CSR[misa].M == 1'b0)) {
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raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
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}
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if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
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raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
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}
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X[rd+8] = X[rd+8] * X[rs2+8];
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sail(): |
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{
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let result_wide = to_bits(2 * sizeof(xlen), signed(X(rsdc)) * signed(X(rs2c)));
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X(rsdc) = result_wide[(sizeof(xlen) - 1) .. 0];
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RETIRE_SUCCESS
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}
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‎arch/inst/Zcb/c.not.yaml‎

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# yaml-language-server: $schema=../../../schemas/inst_schema.json
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$schema: "inst_schema.json#"
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kind: instruction
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name: c.not
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long_name: Bitwise not, 16-bit encoding
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description: |
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This instruction takes a single source/destination operand.
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This instruction takes the one’s complement of rd'/rs1' and writes the result to the same register.
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definedBy:
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anyOf:
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- Zcb
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- Zce
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assembly: xd
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encoding:
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match: 100111---1110101
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variables:
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- name: rd
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location: 9-7
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access:
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s: always
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u: always
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vs: always
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vu: always
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operation(): |
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if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
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raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
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}
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X[rd+8] = ~X[rd+8];
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sail(): |
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{
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X(rsdc) = X(rsdc) XOR -1;
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RETIRE_SUCCESS
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}
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‎arch/inst/Zcb/c.sb.yaml‎

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# yaml-language-server: $schema=../../../schemas/inst_schema.json
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$schema: "inst_schema.json#"
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kind: instruction
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name: c.sb
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long_name: Store unsigned byte, 16-bit encoding
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description: |
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Stores a 8-bit value from register rs2 into memory.
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It computes an effective address by adding the zero-extended offset, to the base address in register rs1.
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It expands to `sb` `rs2, offset(rs1)`.
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definedBy:
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anyOf:
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- Zcb
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- Zce
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assembly: xs2, imm(xs1)
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encoding:
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match: 100010--------00
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variables:
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- name: imm
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location: 5|6
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- name: rs2
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location: 4-2
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- name: rs1
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location: 9-7
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access:
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s: always
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u: always
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vs: always
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vu: always
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operation(): |
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if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
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raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
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}
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XReg virtual_address = X[rs1+8] + imm;
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write_memory<8>(virtual_address, X[rs2+8][7:0], $encoding);

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