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‎spec/custom/non_isa/preface_demo.yaml‎

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Original file line numberDiff line numberDiff line change
@@ -8,15 +8,12 @@ name: preface
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long_name: Preface (Demo)
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version: 1.0.0
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ratification_date: "2025-08-08"
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description:
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- id: spec-preface-overview
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normative: false
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text: |
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This Programmer's Reference Manual (PRM) provides comprehensive documentation for a generic RISC-V processor implementation. It is intended for system designers, integrators, verification engineers, and software developers working with RISC-V-based systems.
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description: |
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This Programmer's Reference Manual (PRM) provides comprehensive documentation for a generic RISC-V processor implementation. It is intended for system designers, integrators, verification engineers, and software developers working with RISC-V-based systems.
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The manual covers the processor architecture, instruction set, control and status registers, memory management, debug and trace features, and other essential aspects. It aims to clarify both standard RISC-V features and implementation-defined options, supporting robust and portable software development.
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The manual covers the processor architecture, instruction set, control and status registers, memory management, debug and trace features, and other essential aspects. It aims to clarify both standard RISC-V features and implementation-defined options, supporting robust and portable software development.
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This document is suitable for public distribution and does not contain proprietary or vendor-specific content. All examples and descriptions are generic and based on open RISC-V standards.
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This document is suitable for public distribution and does not contain proprietary or vendor-specific content. All examples and descriptions are generic and based on open RISC-V standards.
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authors:
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- name: RISC-V Community
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organization:
@@ -28,85 +25,65 @@ license:
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url: https://spdx.org/licenses/CC0-1.0.html
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sections:
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- title: About This Manual
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content:
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- id: sec-preface-about
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normative: false
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text: |
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This manual is organized to guide users through the essential features of a RISC-V processor. It begins with an overview of the architecture and programming model, followed by chapters on the instruction set, privilege levels, memory subsystem, and system integration topics. Each chapter provides references to the official RISC-V specifications and highlights implementation-defined aspects where relevant.
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content: |
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This manual is organized to guide users through the essential features of a RISC-V processor. It begins with an overview of the architecture and programming model, followed by chapters on the instruction set, privilege levels, memory subsystem, and system integration topics. Each chapter provides references to the official RISC-V specifications and highlights implementation-defined aspects where relevant.
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The manual is designed to be accessible to both new and experienced users, with clear explanations, diagrams, and practical examples. It emphasizes portability, compliance with RISC-V standards, and best practices for system design and software development.
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The manual is designed to be accessible to both new and experienced users, with clear explanations, diagrams, and practical examples. It emphasizes portability, compliance with RISC-V standards, and best practices for system design and software development.
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- title: Audience
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content:
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- id: sec-preface-audience
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normative: false
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text: |
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This document is intended for:
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content: |
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This document is intended for:
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* System architects and designers
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* Hardware and software engineers
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* Verification and validation teams
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* Technical writers and educators
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* System architects and designers
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* Hardware and software engineers
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* Verification and validation teams
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* Technical writers and educators
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The manual assumes a basic familiarity with computer architecture and programming concepts, but provides background information and references for further study.
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- id: sec-preface-audience-conditional
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normative: false
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text: |
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This section is only included for educational distributions.
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when(): "distribution_type == 'educational'"
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The manual assumes a basic familiarity with computer architecture and programming concepts, but provides background information and references for further study.
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This section is only included for educational distributions.
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when(): "distribution_type == 'educational'"
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- title: Notation and Conventions
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content:
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- id: sec-preface-notation
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normative: false
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text: |
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The following conventions are used throughout this manual:
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content: |
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The following conventions are used throughout this manual:
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* Register and field names are shown in `monospace` font.
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* Bit values are indicated as 0 (read-only zero) or 1 (read-only one).
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* References to RISC-V specifications are provided for standard features.
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* Implementation-defined options are clearly marked and explained.
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* Register and field names are shown in `monospace` font.
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* Bit values are indicated as 0 (read-only zero) or 1 (read-only one).
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* References to RISC-V specifications are provided for standard features.
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* Implementation-defined options are clearly marked and explained.
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- title: Document Organization
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content:
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- id: sec-preface-organization
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normative: false
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text: |
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Chapters include:
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content: |
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Chapters include:
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* Architecture Overview
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* Instruction Set Architecture
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* Privileged Architecture
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* Interrupts and Exceptions
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* Memory Subsystem
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* Memory Management
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* Reliability, Availability, and Serviceability (RAS)
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* Floating Point Unit
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* Debug and Trace
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* Triggers and Watchpoints
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* Power Management
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* Performance Monitoring
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* Timers and Watchdog
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* Security Features
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* Control and Status Registers
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* Build and Configuration Options
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* Acronyms and Definitions
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* References
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* Architecture Overview
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* Instruction Set Architecture
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* Privileged Architecture
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* Interrupts and Exceptions
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* Memory Subsystem
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* Memory Management
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* Reliability, Availability, and Serviceability (RAS)
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* Floating Point Unit
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* Debug and Trace
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* Triggers and Watchpoints
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* Power Management
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* Performance Monitoring
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* Timers and Watchdog
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* Security Features
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* Control and Status Registers
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* Build and Configuration Options
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* Acronyms and Definitions
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* References
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Each chapter is self-contained and provides links to related topics and external resources.
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Each chapter is self-contained and provides links to related topics and external resources.
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- title: Web Resources
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content:
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- id: sec-preface-web
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normative: true
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text: |
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For more information on RISC-V standards and open-source resources, visit:
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content: |
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For more information on RISC-V standards and open-source resources, visit:
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* https://riscv.org
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* https://github.com/riscv/riscv-isa-manual
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* https://github.com/riscv/riscv-debug-spec
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* https://github.com/riscv-software-src
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* https://riscv.org
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* https://github.com/riscv/riscv-isa-manual
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* https://github.com/riscv/riscv-debug-spec
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* https://github.com/riscv-software-src
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Community forums, mailing lists, and technical documentation are available to support developers and users worldwide.
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Community forums, mailing lists, and technical documentation are available to support developers and users worldwide.
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- title: Revision History
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content:
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- id: sec-preface-history
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normative: true
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text: |
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Version 1.0.0 (2025-08-08): Initial public release of the demo Programmer's Reference Manual for RISC-V processors.
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content: |
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Version 1.0.0 (2025-08-08): Initial public release of the demo Programmer's Reference Manual for RISC-V processors.

‎spec/std/isa/csr/F/fflags.yaml‎

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@@ -9,22 +9,16 @@ name: fflags
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long_name: Floating-Point Accrued Exceptions
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address: 0x001
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writable: true
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description:
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- id: csr-fflags-purpose
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normative: true
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text: |
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The accrued exception flags indicate the exception conditions that have arisen on any floating-point arithmetic
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instruction since the field was last reset by software.
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- id: csr-fflags-fptrap
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normative: false
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text: The base RISC-V ISA does not support generating a trap on the setting of a floating-point exception flag.
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- id: csr-fflags-reasoning
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normative: false
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text: |
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As allowed by the standard, we do not support traps on floating-point exceptions in the F
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extension, but instead require explicit checks of the flags in software. We considered
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adding branches controlled directly by the contents of the floating-point accrued
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exception flags, but ultimately chose to omit these instructions to keep the ISA simple.
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description: |
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The accrued exception flags indicate the exception conditions that have arisen on any floating-point arithmetic
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instruction since the field was last reset by software.
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The base RISC-V ISA does not support generating a trap on the setting of a floating-point exception flag.
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As allowed by the standard, we do not support traps on floating-point exceptions in the F
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extension, but instead require explicit checks of the flags in software. We considered
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adding branches controlled directly by the contents of the floating-point accrued
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exception flags, but ultimately chose to omit these instructions to keep the ISA simple.
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priv_mode: U
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length: 32

‎spec/std/isa/csr/F/frm.yaml‎

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long_name: Floating-Point Dynamic Rounding Mode
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address: 0x002
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writable: true
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description:
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- id: csr-frm-encodings
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normative: false
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text: |
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Rounding modes are encoded as follows:
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description: |
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Rounding modes are encoded as follows:
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[[rm]]
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.Rounding mode encoding.
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[%autowidth,float="center",align="center",cols="^,^,<",options="header"]
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!===
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!Rounding Mode |Mnemonic |Meaning
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!000 !RNE !Round to Nearest, ties to Even
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!001 !RTZ !Round towards Zero
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!010 !RDN !Round Down (towards latexmath:[$-\infty$])
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!011 !RUP !Round Up (towards latexmath:[$+\infty$])
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!100 !RMM !Round to Nearest, ties to Max Magnitude
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!101 ! !_Reserved for future use._
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!110 ! !_Reserved for future use._
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!111 !DYN !In instruction's _rm_ field, selects dynamic rounding mode; In Rounding Mode register, _reserved_.
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!===
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- id: csr-frm-reserved
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normative: false
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text: |
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The behavior of floating-point instructions that depend on rounding mode when
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executed with a reserved rounding mode is _reserved_, including both static
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reserved rounding modes (101-110) and dynamic reserved rounding modes (101-111).
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- id: csr-frm-rmfield
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normative: false
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text: |
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Some instructions, including widening conversions, have the _rm_ field but are
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nevertheless mathematically unaffected by the rounding mode; software should set
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their _rm_ field to RNE (000) but implementations must treat the _rm_ field as
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usual (in particular, with regard to decoding legal vs. reserved encodings).
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[[rm]]
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.Rounding mode encoding.
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[%autowidth,float="center",align="center",cols="^,^,<",options="header"]
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!===
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!Rounding Mode |Mnemonic |Meaning
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!000 !RNE !Round to Nearest, ties to Even
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!001 !RTZ !Round towards Zero
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!010 !RDN !Round Down (towards latexmath:[$-\infty$])
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!011 !RUP !Round Up (towards latexmath:[$+\infty$])
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!100 !RMM !Round to Nearest, ties to Max Magnitude
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!101 ! !_Reserved for future use._
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!110 ! !_Reserved for future use._
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!111 !DYN !In instruction's _rm_ field, selects dynamic rounding mode; In Rounding Mode register, _reserved_.
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!===
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The behavior of floating-point instructions that depend on rounding mode when
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executed with a reserved rounding mode is _reserved_, including both static
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reserved rounding modes (101-110) and dynamic reserved rounding modes (101-111).
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Some instructions, including widening conversions, have the _rm_ field but are
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nevertheless mathematically unaffected by the rounding mode; software should set
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their _rm_ field to RNE (000) but implementations must treat the _rm_ field as
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usual (in particular, with regard to decoding legal vs. reserved encodings).
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priv_mode: U
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length: 32

‎spec/std/isa/csr/Smcsrind/mireg.yaml‎

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priv_mode: M
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length: MXLEN
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definedBy: Smcsrind
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description:
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- id: csr-mireg-purpose
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normative: true
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text: |
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The mireg machine indirect alias CSR is used to access another CSR's state
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indirectly upon a read or write, as determined by the value of miselect.
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- id: csr-mireg-unimplemented-miselect
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normative: true
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text: |
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The behavior upon accessing mireg from M-mode, while miselect holds a value
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that is not implemented, is UNSPECIFIED.
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- id: csr-mireg-unimplemented-miselect-note
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normative: false
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text: |
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It is expected that implementations will typically raise an illegal instruction exception for
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such accesses, so that, for example, they can be identified as software bugs. Platform
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specs, profile specs, and/or the Privileged ISA spec may place more restrictions on
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behavior for such accesses.
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- id: csr-mireg-implemented-miselect
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normative: true
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text: |
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Attempts to access mireg while miselect holds a number in an allocated and implemented range
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results in a specific behavior that, for each combination of miselect and mireg, is defined by the
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extension to which the miselect value is allocated.
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- id: csr-mireg-implemented-miselect-note
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normative: false
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text: |
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Ordinarily, mireg will access register state, access read-only 0 state, or raise an
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illegal instruction exception.
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- id: csr-mireg-rv32-64bit-access
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normative: false
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text: |
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For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is
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recommended that the lower 32 bits of the register are accessed through mireg,
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while the upper 32 bits are accessed through mireg4.
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description: |
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The mireg machine indirect alias CSR is used to access another CSR's state
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indirectly upon a read or write, as determined by the value of miselect.
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The behavior upon accessing mireg from M-mode, while miselect holds a value
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that is not implemented, is UNSPECIFIED.
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It is expected that implementations will typically raise an illegal instruction exception for
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such accesses, so that, for example, they can be identified as software bugs. Platform
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specs, profile specs, and/or the Privileged ISA spec may place more restrictions on
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behavior for such accesses.
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Attempts to access mireg while miselect holds a number in an allocated and implemented range
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results in a specific behavior that, for each combination of miselect and mireg, is defined by the
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extension to which the miselect value is allocated.
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Ordinarily, mireg will access register state, access read-only 0 state, or raise an
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illegal instruction exception.
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For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is
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recommended that the lower 32 bits of the register are accessed through mireg,
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while the upper 32 bits are accessed through mireg4.
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fields:
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VALUE:
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long_name: Indirectly Selected Register Value
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location_rv32: 31-0
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location_rv64: 63-0
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type: RW
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description:
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- id: csr-mireg-value-purpose
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normative: true
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text: Register state of the CSR selected by the current `miselect` value
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description: |
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Register state of the CSR selected by the current `miselect` value
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reset_value: UNDEFINED_LEGAL
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sw_write(csr_value): |
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Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 1);

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