Removed non UTF-8 characters (nice apostrophes) in Smdbltrp, Zce, and c.not descriptions causing conversion error in Ruby.

Author: james-ball-qualcomm

arch/ext/Smdbltrp.yaml

@@ -9,7 +9,7 @@ description: |
   When the `Smrnmi` extension is implemented, it enables invocation of the RNMI handler on a
   double trap in M-mode to handle the critical error.
   If the `Smrnmi` extension is not implemented or if a double trap occurs during the RNMI
-  handler’s execution, this extension helps transition the hart to a critical error state and
+  handler's execution, this extension helps transition the hart to a critical error state and
   enables signaling the critical error to the platform.
 
   To improve error diagnosis and resolution, this extension supports debugging harts in a critical

arch/ext/Zce.yaml

@@ -11,14 +11,13 @@ description: |
   * Specifying `Zce` on RV32 without `F` includes `Zca`, `Zcb`, `Zcmp`, `Zcmt`
   * Specifying `Zce` on RV32 with `F` includes `Zca`, `Zcb`, `Zcmp`, `Zcmt` and `Zcf`
   * Specifying `Zce` on RV64 always includes `Zca`, `Zcb`, `Zcmp`, `Zcmt`
-  * `Zcf` doesn’t exist for RV64
+  * `Zcf` doesn't exist for RV64
 
   Therefore common ISA strings can be updated as follows to include the relevant Zc extensions, for
   example:
 
   * RV32IMC becomes RV32IM_Zce
   * RV32IMCF becomes RV32IMF_Zce
-
 type: unprivileged
 company:
   name: RISC-V International

arch/inst/Zcb/c.not.yaml

@@ -6,7 +6,7 @@ name: c.not
 long_name: Bitwise not, 16-bit encoding
 description: |
   This instruction takes a single source/destination operand.
-  This instruction takes the one’s complement of rd'/rs1' and writes the result to the same register.
+  This instruction takes the one's complement of rd'/rs1' and writes the result to the same register.
 
 definedBy:
   anyOf:

backends/certificate_doc/tasks.rake

@@ -25,7 +25,8 @@ Dir.glob("#{$root}/arch/certificate_model/*.yaml") do |f|
     __FILE__
   ] do |t|
     # TODO: schema validation
-    base_cert_model = cfg_arch_for("rv#{base}").cert_model(cert_model_name)
+    base_cfg_arch = cfg_arch_for("rv#{base}")
+    base_cert_model = base_cfg_arch.cert_model(cert_model_name)
     raise "No certificate model named '#{cert_model_name}'" if base_cert_model.nil?
 
     # Ask base certification model to create an in-memory config arch for this model.

backends/certificate_doc/templates/certificate.adoc.erb

@@ -116,10 +116,10 @@ Where:
 | Term | Meaning
 
 | MANDATORY | You have to implement it to get a certificate and the certificate tests will cover it
-| OPTIONAL | It’s up to you if you implement or not. If you claim to implement it, certificate tests will cover it
+| OPTIONAL | It's up to you if you implement or not. If you claim to implement it, certificate tests will cover it
 | IN-SCOPE | Either MANDATORY or OPTIONAL
-| OUT-OF-SCOPE | It’s up to you if you implement or not. If you implement it, it won't be certified but make sure you don’t mess up anything we are certifying.
-| INCOMPATIBLE | If you implement it you won’t get a certificate
+| OUT-OF-SCOPE | It's up to you if you implement or not. If you implement it, it won't be certified but make sure you don't mess up anything we are certifying.
+| INCOMPATIBLE | If you implement it you won't get a certificate
 |===
 
 .Glossary
@@ -187,7 +187,7 @@ Where:
 
 The Priv ISA requires reads of WARL fields to return some implementation-dependent deterministic legal value
 after the field is written with an illegal value.
-Certifying such behaviors is expensive and provides low value for a certificate since software can’t rely
+Certifying such behaviors is expensive and provides low value for a certificate since software can't rely
 on a particular behavior from one implementation to another.
 
 Processor CRDs define writes to WARL fields of illegal values to be OUT-OF-SCOPE unless otherwise stated
@@ -200,7 +200,7 @@ The following special cases for WARL are supported when explicitly listed in the
 1. Probing for Field Width
 
 * Some WARL fields are variable length such as the ASID field in the virtual memory extension.
-* Here’s the algorithm recommended to discover the ASID width:
+* Here's the algorithm recommended to discover the ASID width:
 ** The number of implemented ASID bits, termed ASIDLEN, may be determined by writing one to every bit position in
    the ASID field, then reading back the value in the satp CSR to see which bit positions in the ASID field hold a one.
 * The RVCP-provided certification materials (certification tests, certification reference models) can map writes of
@@ -219,7 +219,7 @@ The following special cases for WARL are supported when explicitly listed in the
 
 The Priv ISA requires reads of WLRL fields to return some implementation-dependent deterministic arbitrary value
 after the field is written with an illegal value.
-Certifying such behaviors is expensive and provides low value for a certificate since software can’t rely
+Certifying such behaviors is expensive and provides low value for a certificate since software can't rely
 on a particular behavior.
 Processor CRDs define writes to WLRL fields of illegal values to be OUT-OF-SCOPE unless otherwise stated
 (i.e., certification tests will only ever write legal values to WLRL fields).
@@ -231,7 +231,7 @@ Such WPRI fields are always unimplemented by definition.
 Certification tests are aware of which fields in the CSRs are WPRI and normally write them with 0 but will
 also write them with ~0 (all ones) and ensure that reads return 0 in both cases.
 It is OUT-OF-SCOPE for certification tests to write all possible values of WPRI fields
-(especially if they are more than just a few bits) and certification tests aren’t designed to be comprehensive
+(especially if they are more than just a few bits) and certification tests aren't designed to be comprehensive
 verification test suites anyways.
 
 === Related Specifications