fix(data): correct c.addi4spn/c.addi16sp assembly syntax (#849)

riscv/sail-riscv#1045

Fixes #842

Author: ThinkOpenly

arch/inst/C/c.addi16sp.yaml

@@ -13,7 +13,7 @@ definedBy:
   anyOf:
     - C
     - Zca
-assembly: imm(sp)
+assembly: sp, imm
 encoding:
   match: 011-00010-----01
   variables:

arch/inst/C/c.addi4spn.yaml

@@ -13,15 +13,15 @@ definedBy:
   anyOf:
     - C
     - Zca
-assembly: xd, imm(sp)
+assembly: xd, sp, imm
 encoding:
   match: 000-----------00
   variables:
     - name: imm
       location: 10-7|12-11|5|6
       left_shift: 2
       not: 0
-    - name: rd
+    - name: xd
       location: 4-2
 access:
   s: always
@@ -33,4 +33,4 @@ operation(): |
     raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
   }
 
-  X[creg2reg(rd)] = X[2] + imm;
+  X[creg2reg(xd)] = X[2] + imm;

backends/instructions_appendix/all_instructions.golden.adoc

@@ -3223,7 +3223,7 @@ Add a zero-extended non-zero immediate, scaled by 4, to the stack pointer
 Encoding::
 [wavedrom, ,svg,subs='attributes',width="100%"]
 ....
-{"reg":[{"bits":2,"name": 0x0,"type":2},{"bits":3,"name": "rd","type":4},{"bits":8,"name": "imm != 0[5:4|9:6|2|3]","type":4},{"bits":3,"name": 0x0,"type":2}]}
+{"reg":[{"bits":2,"name": 0x0,"type":2},{"bits":3,"name": "xd","type":4},{"bits":8,"name": "imm != 0[5:4|9:6|2|3]","type":4},{"bits":3,"name": 0x0,"type":2}]}
 ....
 
 Description::
@@ -3238,7 +3238,7 @@ Decode Variables::
 |===
 |Variable Name |Location
 |imm |{$encoding[10:7], $encoding[12:11], $encoding[5], $encoding[6], 2'd0}
-|rd |$encoding[4:2]
+|xd |$encoding[4:2]
 |===
 
 Included in::