fix(data): update extension descriptions to better match spec (#1249)

Signed-off-by: Paul A. Clarke <[email protected]>

Author: ThinkOpenly

spec/std/isa/ext/B.yaml

@@ -7,7 +7,7 @@ $schema: "ext_schema.json#"
 kind: extension
 name: B
 type: unprivileged
-long_name: Bitmanipulation instructions
+long_name: Bit Manipulation
 company:
   name: RISC-V International
   url: https://riscv.org

spec/std/isa/ext/M.yaml

@@ -7,7 +7,7 @@ $schema: "ext_schema.json#"
 kind: extension
 name: M
 type: unprivileged
-long_name: Integer multiply and divide instructions
+long_name: Integer multiply and divide
 versions:
   - version: "2.0.0"
     state: ratified

spec/std/isa/ext/Sha.yaml

@@ -7,7 +7,7 @@ $schema: "ext_schema.json#"
 kind: extension
 name: Sha
 type: privileged
-long_name: The augmented hypervisor extension
+long_name: Augmented hypervisor
 description: |
   *Sha* comprises the following extensions:
 

spec/std/isa/ext/Shgatpa.yaml

@@ -6,7 +6,7 @@
 $schema: "ext_schema.json#"
 kind: extension
 name: Shgatpa
-long_name: hgtap profile requirements
+long_name: SvNNx4 mode supported for all modes supported by Supervisor Address Translation and Protection, as well as Bare
 description: |
   For each supported virtual memory scheme SvNN supported in
   `satp`, the corresponding hgatp SvNNx4 mode must be supported.  The

spec/std/isa/ext/Shtvala.yaml

@@ -6,7 +6,7 @@
 $schema: "ext_schema.json#"
 kind: extension
 name: Shtvala
-long_name: htval profile requirements
+long_name: Hypervisor Trap Value provides all needed values
 description: |
   htval must be written with the faulting virtual address
   for load, store, and instruction page-fault, access-fault, and

spec/std/isa/ext/Shvsatpa.yaml

@@ -6,7 +6,7 @@
 $schema: "ext_schema.json#"
 kind: extension
 name: Shvsatpa
-long_name: vstap translation mode requirements
+long_name: Virtual Supervisor Address Translation and Protection supports all modes supported by Supervisor Address Translation and Protection
 description: |
   All translation modes supported in the `satp` CSR must be supported in the `vsatp` CSR.
 

spec/std/isa/ext/Shvstvala.yaml

@@ -6,7 +6,7 @@
 $schema: "ext_schema.json#"
 kind: extension
 name: Shvstvala
-long_name: vstval profile requirements
+long_name: Virtual Supervisor Trap Value provides all needed values
 description: |
   vstval must be written with the faulting virtual address
   for load, store, and instruction page-fault, access-fault, and

spec/std/isa/ext/Shvstvecd.yaml

@@ -6,7 +6,7 @@
 $schema: "ext_schema.json#"
 kind: extension
 name: Shvstvecd
-long_name: vstvec profile requirements
+long_name: Virtual Supervisor Trap Vector Base Address supports Direct mode
 description: |
   `vstvec.MODE` must be capable of holding the value 0 (Direct).
   When `vstvec.MODE`=Direct, `vstvec.BASE` must be capable of holding

spec/std/isa/ext/Smcsrind.yaml

@@ -7,7 +7,7 @@ $schema: "ext_schema.json#"
 kind: extension
 name: Smcsrind
 type: privileged
-long_name: Machine Indirect CSR Access (Smcsrind)
+long_name: Machine-mode Indirect CSR Access
 description: |
   Smcsrind/Sscsrind is an ISA extension that extends the indirect CSR access mechanism originally defined as
   part of the Smaia/Ssaia extensions, in order to make it available for use by other extensions without creating

spec/std/isa/ext/Smdbltrp.yaml

@@ -6,7 +6,7 @@
 $schema: "ext_schema.json#"
 kind: extension
 name: Smdbltrp
-long_name: Double trap
+long_name: Double trap in M-mode
 description: |
   The `Smdbltrp` extension addresses a double trap in M-mode.
   When the `Smrnmi` extension is implemented, it enables invocation of the RNMI handler on a