Final fix definedBy allOf addition.

Signed-off-by: Afonso Oliveira <[email protected]>

Author: AFOliveira

arch/inst/Zfh/fcvt.h.s.yaml

@@ -5,7 +5,7 @@ kind: instruction
 name: fcvt.h.s
 long_name: Convert half-precision float to a single-precision float
 definedBy:
-  anyOf: [Zfh, Zfhmin]
+  allOf: [Zfh, Zfhmin]
 assembly: fd, xs1
 description: |
   Converts a half-precision number in floating-point register _fs1_ into a single-precision floating-point number in

arch/inst/Zfh/fcvt.s.h.yaml

@@ -5,7 +5,7 @@ kind: instruction
 name: fcvt.s.h
 long_name: Convert single-precision float to a half-precision float
 definedBy:
-  anyOf: [Zfh, Zfhmin]
+  allOf: [Zfh, Zfhmin]
 assembly: fd, xs1
 description: |
   Converts a single-precision number in floating-point register _fs1_ into a half-precision floating-point number in

arch/inst/Zfh/flh.yaml

@@ -12,7 +12,7 @@ description: |
   `flh` is only guaranteed to execute atomically if the effective address is naturally aligned.
 
 definedBy:
-  anyOf: [Zfh, Zfhmin]
+  allOf: [Zfh, Zfhmin]
 assembly: fd, imm(xs1)
 encoding:
   match: -----------------001-----0000111

arch/inst/Zfh/fmv.x.h.yaml

@@ -5,7 +5,7 @@ kind: instruction
 name: fmv.x.h
 long_name: Move half-precision value from floating-point to integer register
 definedBy:
-  anyOf: [Zfh, Zfhmin]
+  allOf: [Zfh, Zfhmin]
 assembly: rd, fs1
 description: |
   Moves the half-precision value in floating-point register rs1 represented in IEEE 754-2008

arch/inst/Zfh/fsh.yaml

@@ -15,7 +15,7 @@ description: |
   `fsh` is only guaranteed to execute atomically if the effective address is naturally aligned.
 
 definedBy:
-  anyOf: [Zfh, Zfhmin]
+  allOf: [Zfh, Zfhmin]
 assembly: fs2, imm(xs1)
 encoding:
   match: -----------------001-----0100111