Xqci (Xqciint) extension: Fix IDL code for Smdbltrp and Smrnmi spec compatibility for qc.c.mret and qc.c.mnret instructions

Signed-off-by: Albert Yosher <[email protected]>

Author: ayosher

arch_overlay/qc_iu/ext/Xqci.yaml

@@ -289,6 +289,7 @@ versions:
     - Fix wrong mantissa bit selection in qc.norm, qc.normu and qc.normeu instructions
     - Fix wrong exponent calculation in qc.normeu instruction
     - Fix IDL code and description of qc.setwm instruction to state that number of words written 0..31.
+    - Fix IDL code for Smdbltrp and Smrnmi spec compatibility for qc.c.mret and qc.c.mnret instructions
   implies:
   - { name: Xqcia, version: "0.6.0" }
   - { name: Xqciac, version: "0.3.0" }
@@ -298,7 +299,7 @@ versions:
   - { name: Xqcicm, version: "0.2.0" }
   - { name: Xqcics, version: "0.2.0" }
   - { name: Xqcicsr, version: "0.3.0" }
-  - { name: Xqciint, version: "0.5.0" }
+  - { name: Xqciint, version: "0.6.0" }
   - { name: Xqciio, version: "0.1.0" }
   - { name: Xqcilb, version: "0.2.0" }
   - { name: Xqcili, version: "0.2.0" }

arch_overlay/qc_iu/ext/Xqciint.yaml

@@ -80,6 +80,19 @@ versions:
   changes:
     - Add stack checks to qc.c.mienter, qc.c.mienter.nest, qc.c.mileaveret
   requires: { name: Zca, version: ">= 1.0.0" }
+- version: "0.6.0"
+  state: frozen
+  ratification_date: null
+  contributors:
+  - name: Albert Yosher
+    company: Qualcomm Technologies, Inc.
+    email: [email protected]
+  - name: Derek Hower
+    company: Qualcomm Technologies, Inc.
+    email: [email protected]
+  changes:
+    - Fix IDL code for Smdbltrp and Smrnmi spec compatibility for qc.c.mret and qc.c.mnret instructions
+  requires: { name: Zca, version: ">= 1.0.0" }
 description: |
   The Xqciint extension includes eleven instructions to accelerate interrupt
   servicing by performing common actions during ISR prologue/epilogue.

arch_overlay/qc_iu/inst/Xqci/qc.c.mnret.yaml

@@ -30,6 +30,12 @@ operation(): |
   CSR[qc.mcause].sw_write(qc_mcause_val_masked |
                           (1<<28) | (mnpie_val<<26) | (1<<30) |
                           (mnpil_val << 12) | (0xF << 20));
+  if (CSR[mnstatus].MNPP != 2'b11) {
+    CSR[mstatus].MPRV = 0;
+    if (implemented?(ExtensionName::Smdbltrp)) {
+      CSR[mstatush].MDT = 1'b0;
+    }
+  }
   if (CSR[mnstatus].MNPP == 2'b00) {
     set_mode(PrivilegeMode::U);
   } else if (CSR[mnstatus].MNPP == 2'b01) {

arch_overlay/qc_iu/inst/Xqci/qc.c.mret.yaml

@@ -28,11 +28,16 @@ operation(): |
   Bits<4> mpil_val = (qc_mcause_val >> 16) & 0xF;
   CSR[mstatus].MIE = mpie_val;
   CSR[mstatus].MPIE = 1'b1;
-  CSR[mstatush].MDT = mpdt_val;
+  if (implemented?(ExtensionName::Smdbltrp)) {
+    CSR[mstatush].MDT = mpdt_val;
+  }
   CSR[qc.mcause].sw_write(qc_mcause_val_masked |
                           (1<<27) | (mpie_val<<26) | (0<<29) |
                           (mpil_val << 12) | (0xF << 16));
   if (mpdt_val == 1'b0) {
+    if (CSR[mstatus].MPP != 2'b11) {
+      CSR[mstatus].MPRV = 0;
+    }
     if (CSR[mstatus].MPP == 2'b00) {
       set_mode(PrivilegeMode::U);
     } else if (CSR[mstatus].MPP == 2'b01) {