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read-only-zero when MISA_CSR_IMPLEMENTED=false
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‎spec/std/isa/csr/misa.yaml‎

Lines changed: 72 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -8,10 +8,14 @@ kind: csr
88
name: misa
99
long_name: Machine ISA Control
1010
address: 0x301
11+
# writable when misa CSR is implemented; read-only-0 otherwise
1112
writable: true
1213
priv_mode: M
1314
length: MXLEN
14-
description: Reports the XLEN and "major" extensions supported by the ISA.
15+
description: |
16+
Reports the XLEN and "major" extensions supported by the ISA.
17+
[when,"MISA_CSR_IMPLEMENTED == false"]
18+
This CSR is read-only-0 (all bits hardwired to zero) and cannot be written.
1519
definedBy: Sm
1620
fields:
1721
MXL:
@@ -20,7 +24,7 @@ fields:
2024
description: XLEN in M-mode.
2125
type: RO
2226
reset_value(): |
23-
return (MXLEN == 32) ? 2'b01 : 2'b10;
27+
return (!MISA_CSR_IMPLEMENTED) ? 0 : (MXLEN == 32) ? 2'b01 : 2'b10;
2428
A:
2529
location: 0
2630
description: |
@@ -29,9 +33,10 @@ fields:
2933
[when,"MUTABLE_MISA_A == true"]
3034
Writing 0 to this field will cause all atomic instructions to raise an `IllegalInstruction` exception.
3135
type(): |
32-
return (implemented?(ExtensionName::A) && MUTABLE_MISA_A) ? CsrFieldType::RW : CsrFieldType::RO;
36+
return (!MISA_CSR_IMPLEMENTED) ? CsrFieldType::RO :
37+
(implemented?(ExtensionName::A) && MUTABLE_MISA_A) ? CsrFieldType::RW : CsrFieldType::RO;
3338
reset_value(): |
34-
return implemented?(ExtensionName::A) ? 1 : 0;
39+
return (!MISA_CSR_IMPLEMENTED) ? 0 : implemented?(ExtensionName::A) ? 1 : 0;
3540
definedBy: A
3641
B:
3742
location: 1
@@ -41,9 +46,10 @@ fields:
4146
[when,"MUTABLE_MISA_B == true"]
4247
Writing 0 to this field will cause all bitmanip instructions to raise an `IllegalInstruction` exception.
4348
type(): |
44-
return (implemented?(ExtensionName::B) && MUTABLE_MISA_B) ? CsrFieldType::RW : CsrFieldType::RO;
49+
return (!MISA_CSR_IMPLEMENTED) ? CsrFieldType::RO :
50+
(implemented?(ExtensionName::B) && MUTABLE_MISA_B) ? CsrFieldType::RW : CsrFieldType::RO;
4551
reset_value(): |
46-
return implemented?(ExtensionName::B) ? 1 : 0;
52+
return (!MISA_CSR_IMPLEMENTED) ? 0 : implemented?(ExtensionName::B) ? 1 : 0;
4753
definedBy: B
4854
C:
4955
location: 2
@@ -54,9 +60,10 @@ fields:
5460
Writing 0 to this field will cause all compressed instructions to raise an `IllegalInstruction` exception.
5561
Additionally, IALIGN becomes 32.
5662
type(): |
57-
return (implemented?(ExtensionName::C) && MUTABLE_MISA_C) ? CsrFieldType::RW : CsrFieldType::RO;
63+
return (!MISA_CSR_IMPLEMENTED) ? CsrFieldType::RO :
64+
(implemented?(ExtensionName::C) && MUTABLE_MISA_C) ? CsrFieldType::RW : CsrFieldType::RO;
5865
reset_value(): |
59-
return implemented?(ExtensionName::C) ? 1 : 0;
66+
return (!MISA_CSR_IMPLEMENTED) ? 0 : implemented?(ExtensionName::C) ? 1 : 0;
6067
definedBy: C
6168
D:
6269
location: 3
@@ -70,9 +77,10 @@ fields:
7077
Additionally, the upper 32-bits of the f registers will read as zero.
7178
--
7279
type(): |
73-
return (implemented?(ExtensionName::D) && MUTABLE_MISA_D) ? CsrFieldType::RW : CsrFieldType::RO;
80+
return (!MISA_CSR_IMPLEMENTED) ? CsrFieldType::RO :
81+
(implemented?(ExtensionName::D) && MUTABLE_MISA_D) ? CsrFieldType::RW : CsrFieldType::RO;
7482
reset_value(): |
75-
return implemented?(ExtensionName::D) ? 1 : 0;
83+
return (!MISA_CSR_IMPLEMENTED) ? 0 : implemented?(ExtensionName::D) ? 1 : 0;
7684
definedBy: D
7785
F:
7886
location: 5
@@ -86,24 +94,34 @@ fields:
8694
Writing 0 to this field with `misa.D` set will result in UNDEFINED behavior.
8795
--
8896
type(): |
89-
return (implemented?(ExtensionName::F) && MUTABLE_MISA_F) ? CsrFieldType::RW : CsrFieldType::RO;
97+
return (!MISA_CSR_IMPLEMENTED) ? CsrFieldType::RO :
98+
(implemented?(ExtensionName::F) && MUTABLE_MISA_F) ? CsrFieldType::RW : CsrFieldType::RO;
9099
reset_value(): |
91-
return implemented?(ExtensionName::F) ? 1 : 0;
100+
return (!MISA_CSR_IMPLEMENTED) ? 0 : implemented?(ExtensionName::F) ? 1 : 0;
92101
definedBy: F
93102
sw_write(csr_value): |
103+
if (!MISA_CSR_IMPLEMENTED) {
104+
return 0;
105+
}
94106
if (csr_value.F == 0 && csr_value.D == 1) {
95107
return UNDEFINED_LEGAL_DETERMINISTIC;
96108
}
97109
98110
# fall-through; write the intended value
99111
return csr_value.F;
100112
legal?(csr_value): |
113+
if (!MISA_CSR_IMPLEMENTED) {
114+
return true;
115+
}
101116
return !(csr_value.F == 0 && csr_value.D == 1);
102117
G:
103118
location: 6
104119
description: |
105120
Indicates support for all of the following extensions: `I`, `A`, `M`, `F`, `D`.
106121
type(): |
122+
if (!MISA_CSR_IMPLEMENTED) {
123+
return CsrFieldType::RO;
124+
}
107125
if ((implemented?(ExtensionName::A) && MUTABLE_MISA_A) ||
108126
(implemented?(ExtensionName::M) && MUTABLE_MISA_M) ||
109127
(implemented?(ExtensionName::F) && MUTABLE_MISA_F) ||
@@ -113,6 +131,9 @@ fields:
113131
return CsrFieldType::RO;
114132
}
115133
reset_value(): |
134+
if (!MISA_CSR_IMPLEMENTED) {
135+
return 0;
136+
}
116137
return (
117138
implemented?(ExtensionName::A) &&
118139
implemented?(ExtensionName::M) &&
@@ -126,17 +147,19 @@ fields:
126147
[when,"MUTABLE_MISA_H == true"]
127148
Writing 0 to this field will cause all attempts to enter VS- or VU- mode, execute a hypervisor instruction, or access a hypervisor CSR to raise an `IllegalInstruction` fault.
128149
type(): |
129-
return (implemented?(ExtensionName::H) && MUTABLE_MISA_H) ? CsrFieldType::RW : CsrFieldType::RO;
150+
return (!MISA_CSR_IMPLEMENTED) ? CsrFieldType::RO :
151+
(implemented?(ExtensionName::H) && MUTABLE_MISA_H) ? CsrFieldType::RW : CsrFieldType::RO;
130152
definedBy: H
131153
reset_value(): |
132-
return implemented?(ExtensionName::H) ? 1 : 0;
154+
return (!MISA_CSR_IMPLEMENTED) ? 0 : implemented?(ExtensionName::H) ? 1 : 0;
133155
I:
134156
location: 8
135157
description: |
136158
Indicates support for the `I` (base) extension.
137159
type: RO
138160
definedBy: I
139-
reset_value: 1
161+
reset_value(): |
162+
return (!MISA_CSR_IMPLEMENTED) ? 0 : 1;
140163
M:
141164
location: 12
142165
description: |
@@ -145,9 +168,10 @@ fields:
145168
[when,"MUTABLE_MISA_M == true"]
146169
Writing 0 to this field will cause all attempts to execute an integer multiply or divide instruction to raise an `IllegalInstruction` exception.
147170
type(): |
148-
return (implemented?(ExtensionName::M) && MUTABLE_MISA_M) ? CsrFieldType::RW : CsrFieldType::RO;
171+
return (!MISA_CSR_IMPLEMENTED) ? CsrFieldType::RO :
172+
(implemented?(ExtensionName::M) && MUTABLE_MISA_M) ? CsrFieldType::RW : CsrFieldType::RO;
149173
reset_value(): |
150-
return implemented?(ExtensionName::M) ? 1 : 0;
174+
return (!MISA_CSR_IMPLEMENTED) ? 0 : implemented?(ExtensionName::M) ? 1 : 0;
151175
definedBy: M
152176
cert_normative_rules:
153177
- id: csr_field.misa.M.disabled
@@ -182,17 +206,25 @@ fields:
182206
Writing 0 to this field will cause all quad-precision floating point instructions to raise an `IllegalInstruction` exception.
183207
--
184208
type(): |
185-
return MUTABLE_MISA_Q ? CsrFieldType::RW : CsrFieldType::RO;
186-
reset_value: 1
209+
return (!MISA_CSR_IMPLEMENTED) ? CsrFieldType::RO :
210+
MUTABLE_MISA_Q ? CsrFieldType::RW : CsrFieldType::RO;
211+
reset_value(): |
212+
return (!MISA_CSR_IMPLEMENTED) ? 0 : 1;
187213
definedBy: Q
188214
sw_write(csr_value): |
215+
if (!MISA_CSR_IMPLEMENTED) {
216+
return 0;
217+
}
189218
if ((csr_value.F == 0 || csr_value.D == 0) && csr_value.Q == 1) {
190219
return UNDEFINED_LEGAL_DETERMINISTIC;
191220
}
192221
193222
# fall-through; write the intended value
194223
return csr_value.Q;
195224
legal?(csr_value): |
225+
if (!MISA_CSR_IMPLEMENTED) {
226+
return true;
227+
}
196228
return !(csr_value.Q == 1 && csr_value.D == 0);
197229
S:
198230
location: 18
@@ -202,9 +234,10 @@ fields:
202234
[when,"MUTABLE_MISA_S == true"]
203235
Writing 0 to this field will cause all attempts to enter S-mode or access S-mode state to raise an exception.
204236
type(): |
205-
return (implemented?(ExtensionName::S) && MUTABLE_MISA_S) ? CsrFieldType::RW : CsrFieldType::RO;
237+
return (!MISA_CSR_IMPLEMENTED) ? CsrFieldType::RO :
238+
(implemented?(ExtensionName::S) && MUTABLE_MISA_S) ? CsrFieldType::RW : CsrFieldType::RO;
206239
reset_value(): |
207-
return implemented?(ExtensionName::S) ? 1 : 0;
240+
return (!MISA_CSR_IMPLEMENTED) ? 0 : implemented?(ExtensionName::S) ? 1 : 0;
208241
definedBy: S
209242
U:
210243
location: 20
@@ -214,33 +247,41 @@ fields:
214247
[when,"MUTABLE_MISA_U == true"]
215248
Writing 0 to this field will cause all attempts to enter U-mode to raise an exception.
216249
type(): |
217-
return (implemented?(ExtensionName::U) && MUTABLE_MISA_U) ? CsrFieldType::RW : CsrFieldType::RO;
250+
return (!MISA_CSR_IMPLEMENTED) ? CsrFieldType::RO :
251+
(implemented?(ExtensionName::U) && MUTABLE_MISA_U) ? CsrFieldType::RW : CsrFieldType::RO;
218252
reset_value(): |
219-
return implemented?(ExtensionName::U) ? 1 : 0;
253+
return (!MISA_CSR_IMPLEMENTED) ? 0 : implemented?(ExtensionName::U) ? 1 : 0;
220254
definedBy: U
221255
V:
222256
location: 21
223257
description: |
224258
Indicates support for the `V` (vector) extension.
225259
226-
[when,"MUTABLE_MISA_V == true"]
260+
[when,"MUTABLE_MISA_V == true && MISA_CSR_IMPLEMENTED == true"]
227261
Writing 0 to this field will cause all attempts to execute a vector instruction to raise an `IllegalInstruction` trap.
262+
263+
[when,"MISA_CSR_IMPLEMENTED == false"]
264+
This field reads as 0 and cannot be modified.
228265
type(): |
229-
return (implemented?(ExtensionName::V) && MUTABLE_MISA_V) ? CsrFieldType::RW : CsrFieldType::RO;
266+
return (!MISA_CSR_IMPLEMENTED) ? CsrFieldType::RO :
267+
(implemented?(ExtensionName::V) && MUTABLE_MISA_V) ? CsrFieldType::RW : CsrFieldType::RO;
230268
reset_value(): |
231-
return implemented?(ExtensionName::V) ? 1 : 0;
269+
return (!MISA_CSR_IMPLEMENTED) ? 0 : implemented?(ExtensionName::V) ? 1 : 0;
232270
definedBy: V
233271
sw_read(): |
272+
if (!MISA_CSR_IMPLEMENTED) {
273+
return 0;
274+
}
234275
return (
235276
(CSR[misa].MXL << (xlen() - 2)) |
236277
(CSR[misa].V << 21) |
237278
(CSR[misa].U << 20) |
238279
(CSR[misa].S << 18) |
239280
(CSR[misa].M << 12) |
240-
(CSR[misa].I << 7) |
241-
(CSR[misa].H << 6) |
242-
((CSR[misa].A & CSR[misa].M & CSR[misa].F & CSR[misa].D) << 5) | # 'G'
243-
(CSR[misa].F << 4) |
281+
(CSR[misa].I << 8) |
282+
(CSR[misa].H << 7) |
283+
((CSR[misa].A & CSR[misa].M & CSR[misa].F & CSR[misa].D) << 6) | # 'G'
284+
(CSR[misa].F << 5) |
244285
(CSR[misa].D << 3) |
245286
(CSR[misa].C << 2) |
246287
(CSR[misa].B << 1) |
@@ -261,4 +302,4 @@ cert_test_procedures:
261302
. Loop
262303
.. Turn off each present bit invidually and try affected behaviors
263304
. Check
264-
.. Fail unless turning off bit disables extension as expected
305+
.. Fail unless turning off bit disables extension as expected

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