Xqci extension: fix qc.c.mnret and qc.c.mret instructions

Signed-off-by: Albert Yosher <[email protected]>

Author: ayosher

cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mncause.yaml

@@ -0,0 +1,65 @@
+$schema: csr_schema.json#
+kind: csr
+name: qc_mncause
+long_name: Machine NMI Cause
+address: 0x7c2
+base: 32
+priv_mode: M
+length: MXLEN
+description: |
+  Reports the cause of the latest non-maskable interrupt.
+definedBy:
+  anyOf:
+    - Xqci
+    - Xqciint
+fields:
+  INT:
+    type: RW-H
+    reset_value: 0
+    location: 31
+    description: Interrupt bit copied from mcause.INT at the moment of NMI
+  NMI:
+    type: RW-H
+    reset_value: 0
+    location: 30
+    description: If 1'b1, currently processing NMI.
+  MPP:
+    type: RW-H
+    reset_value: 3
+    location: 29-28
+    description: M-mode Previous Privilege.
+  MPIE:
+    type: RW-H
+    reset_value: 0
+    location: 27
+    description: M-mode Previous Interrupt Enable.
+  MIE:
+    type: RW-H
+    reset_value: 0
+    location: 26
+    description: M-mode Interrupt Enable.
+  EXCP:
+    type: RW-H
+    reset_value: 0
+    location: 25
+    description: Exception Pending Bit.
+  RESP:
+    type: RW-H
+    reset_value: 0
+    location: 24
+    description: Resume Pending Bit.
+  MPIL:
+    type: RW-H
+    reset_value: 0
+    location: 19-16
+    description: M-mode Previous Interrupt Level.
+  MIL:
+    type: RW-H
+    reset_value: 15
+    location: 15-12
+    description: M-mode Interrupt Level.
+  NMICODE:
+    type: RW-H
+    reset_value: 0
+    location: 11-0
+    description: NMI code ID.

cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mnret.yaml

@@ -8,7 +8,10 @@ description: |
   Returns from an NMI in M-mode.
   Instruction encoded in CI instruction format.
 assembly: ""
-definedBy: Xqciint
+definedBy:
+  anyOf:
+    - Xqci
+    - Xqciint
 access:
   s: never
   u: never
@@ -18,15 +21,18 @@ base: 32
 encoding:
   match: "0001100110010010"
 operation(): |
-  CSR[mncause].MIE = CSR[mncause].MPIE;
-  CSR[mncause].MPIE = 1;
-  if (CSR[mncause].MPP == 2'b00) {
+  if (implemented?(ExtensionName::S) && CSR[mstatus].MPP != 2'b11) {
+    CSR[mstatus].MPRV = 0;
+  }
+  CSR[mstatus].MIE = CSR[mstatus].MPIE;
+  CSR[mstatus].MPIE = 1;
+  if (CSR[mstatus].MPP == 2'b00) {
     set_mode(PrivilegeMode::U);
-  } else if (CSR[mncause].MPP == 2'b01) {
+  } else if (CSR[mstatus].MPP == 2'b01) {
     set_mode(PrivilegeMode::S);
-  } else if (CSR[mncause].MPP == 2'b11) {
+  } else if (CSR[mstatus].MPP == 2'b11) {
     set_mode(PrivilegeMode::M);
   }
-  CSR[mncause].MPP = implemented?(ExtensionName::U) ? 2'b00 : 2'b11;
+  CSR[mstatus].MPP = implemented?(ExtensionName::U) ? 2'b00 : 2'b11;
   CSR[mcause].NMI = 0;
   $pc = CSR[qc_mnepc].sw_read();

cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mret.yaml

@@ -8,7 +8,10 @@ description: |
   Returns from an exception in M-mode.
   Instruction encoded in CI instruction format.
 assembly: ""
-definedBy: Xqciint
+definedBy:
+  anyOf:
+    - Xqci
+    - Xqciint
 access:
   s: never
   u: never