Merge remote-tracking branch 'rvi/main' into 147-fix-typos-found-in-idl-documentation

Author: Derek Hower

arch/crd/MC-1.yaml

@@ -63,6 +63,12 @@ MC-1:
         MTVAL_WIDTH: {} # Unconstrained
         MTVEC_MODES: {} # Unconstrained
         PHYS_ADDR_WIDTH: {} # Unconstrained
+        MISALIGNED_LDST: {} # Unconstrained
+        MISALIGNED_LDST_EXCEPTION_PRIORITY : {} # Unconstrained
+        MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE: {} # Unconstrained
+        MISALIGNED_SPLIT_STRATEGY:
+          schema:
+            const: by_byte
         PRECISE_SYNCHRONOUS_EXCEPTIONS:
           schema:
             const: true
@@ -77,59 +83,4 @@ MC-1:
             const: little
         XLEN:
           schema:
-            const: 32
-  
-  requirement_groups:
-    - name: MC-Unpriv
-      description: |
-        The MC-Unpriv defines unprivileged ISA requirements.
-        Note that unprivileged ISA features are those that are usable in all privilege modes;
-        they aren't only usable in U-mode (User-mode).
-        It is unfortunate that both “Unprivileged” and “User” start with the letter “U” but they
-        aren't the same thing.
-
-      requirements:
-      - name: REQ-UINST-001
-        description: Should use little-endian byte order
-
-      - name: REQ-UCSR-001-a
-        description: Should raise an Illegal Instruction exception when writing to the `cycle` CSR
-
-      - name: REQ-UCSR-001-b
-        description: Should return the XLEN least-significant bits of the `mcycle` CSR when reading the `cycle` CSR
-        
-      - name: REQ-UCSR-002-a
-        description: Should raise an Illegal Instruction exception when writing to the `time` CSR
-
-      - name: REQ-UCSR-002-b
-        description: Should return the XLEN least-significant bits of the `mtime` CSR when reading the `time` CSR
-        when:
-          param:
-            TIME_CSR_IMPLEMENTED: true
-
-      - name: REQ-UCSR-002-c
-        description: Should raise an Illegal Instruction exception when reading the `time` CSR
-        when:
-          param:
-            TIME_CSR_IMPLEMENTED: false
-
-    - name: MC-Unpriv-32
-      when:
-        xlen: 32
-      description: |
-        The MC-Unpriv-32 defines unprivileged ISA requirements specific to 32-bit processors.
-      requirements:
-      - name: REQ-M32CSR-001-a
-        description: Should raise an illegal instruction trap when writing the 'cycleh' CSR
-      - name: REQ-M32CSR-001-b
-        description: Should return the most-significant 32-bits of the `mcycle` CSR when reading `cycleh`
-      - name: REQ-M32CSR-002
-        description: Should return the most-significant 32-bits of the `minstret` CSR when reading `instreth`
-
-    - name: MC-Priv
-      description: |
-        The MC-Priv defines Privileged ISA requirements.
-      requirements:
-      - name: REQ-PRIV-HARTID
-        description: | 
-          One hart in system has to have a HARTID of 0. Reading `mhartid` on other CSRs provides some value.
+            const: 32

arch/csr/medelegh.yaml

@@ -8,5 +8,7 @@ medelegh:
   base: 32
   description: |
     Alias of the upper 32 bits of `medeleg`.
-  definedBy: I
+  definedBy:
+    name: S
+    version: ">= 1.13"
   fields: {}

arch/csr/mip.yaml

@@ -5,7 +5,7 @@ mip:
   address: 0x344
   priv_mode: M
   description: Machine Interrupt Pending bits
-  length: 64
+  length: MXLEN
   definedBy: Sm
   fields:
     SSIP:

arch/csr/mscratch.yaml

@@ -4,12 +4,13 @@ mscratch:
   long_name: Machine Scratch Register
   address: 0x340
   priv_mode: M
-  length: 64
+  length: MXLEN
   description: Scratch register for software use. Bits are not interpreted by hardware.
-  definedBy: U # actually, defined by RV64, but must implement U-mode for this CSR to exist
+  definedBy: Sm
   fields:
     SCRATCH:
-      location: 63-0
+      location_rv32: 31-0
+      location_rv64: 63-0
       description: Scratch value
       type: RW
       reset_value: 0

arch/csr/mseccfg.yaml

@@ -8,6 +8,6 @@ mseccfg:
   description: Machine Security Configuration
   definedBy:
     name: Sm
-    version: ">=1.12"
+    version: ">= 1.12"
   fields: {}
 

arch/csr/mseccfgh.yaml

@@ -8,6 +8,6 @@ mseccfgh:
   description: Machine Security Configuration
   definedBy:
     name: Sm
-    version: ">=1.12"
+    version: ">= 1.12"
   fields: {}
 

arch/csr/mstatush.yaml

@@ -7,7 +7,9 @@ mstatush:
   base: 32
   length: 32
   description: The mstatus register tracks and controls the hart's current operating state.
-  definedBy: Sm
+  definedBy:
+    name: Sm
+    version: ">= 1.12"
   fields:
     MPV:
       location: 7

arch/csr/mtval.yaml

@@ -5,11 +5,12 @@ mtval:
   address: 0x343
   description: Holds trap-specific information
   priv_mode: M
-  length: 64
+  length: MXLEN
   definedBy: Sm
   fields:
     VALUE:
-      location: 63-0
+      location_rv32: 31-0
+      location_rv64: 63-0
       description: |
         Written with trap-specific information when a trap is taken into M-mode.
 

arch/csr/mtvec.yaml

@@ -4,14 +4,15 @@ mtvec:
   long_name: Machine Trap Vector Control
   address: 0x305
   priv_mode: M
-  length: 64
+  length: MXLEN
   description: Controls where traps jump.
   definedBy: Sm
   fields:
     BASE:
-      location: 63-2
+      location_rv64: 63-2
+      location_rv32: 31-2
       description: |
-        Bits [63:2] of the exception vector physical address for any trap taken in M-mode.
+        Bits [MXLEN-1:2] of the exception vector physical address for any trap taken in M-mode.
 
         The implementation physical memory map may resitrict which values are legal in this field.
       type: RW-R

arch/ext/Sm.yaml

@@ -231,7 +231,7 @@ Sm:
       description: |
         Does the implementation perform non-atomic misaligned loads and stores to main memory 
         (does *not* affect misaligned support to device memory)? 
-        If not, the implementation throws a misaligned exception.
+        If not, the implementation always throws a misaligned exception.
       schema:
         type: boolean
     MISALIGNED_LDST_EXCEPTION_PRIORITY:
@@ -247,21 +247,21 @@ Sm:
         ! high ! Misaligned load/store/AMO exceptions are always higher priority than load/store/AMO page-fault and access-fault exceptions.
         !===
 
-        MISALIGNED_LDST_EXCEPTION_PRIORITY cannot be "high" when MAX_MISALIGNED_ATOMICITY_GRANULE_SIZE
+        MISALIGNED_LDST_EXCEPTION_PRIORITY cannot be "high" when MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE
         is non-zero, since the atomicity of an access cannot be determined in that case until after
         address translation.
       schema:
         type: string
         enum: ["low", "high"]
         extra_validation: |
-          assert (MISALIGNED_LDST_EXCEPTION_PRIORITY == "low") if MAX_MISALIGNED_ATOMICITY_GRANULE_SIZE.positive?
-    MAX_MISALIGNED_ATOMICITY_GRANULE_SIZE:
+          assert (MISALIGNED_LDST_EXCEPTION_PRIORITY == "low") if MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE.positive?
+    MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE:
       description: |
         The maximum granule size, in bytes, that the hart can atomically perform a
-        misaligned load/store/AMO without raising a Misaligned exception. When MAX_MISALIGNED_ATOMICITY_GRANULE_SIZE is 0, the hart
+        misaligned load/store/AMO without raising a Misaligned exception. When MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE is 0, the hart
         cannot atomically perform a misaligned load/store/AMO. When a power of two, the hart can
         atomically load/store/AMO a misaligned access that is fully contained in a
-        MAX_MISALIGNED_ATOMICITY_GRANULE_SIZE-aligned region.
+        MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE-aligned region.
 
         [NOTE]
         Even if the hart is capable of performing a misaligned load/store/AMO atomically,