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This pull request adds support for generating a SystemVerilog package
containing RISC-V instruction and CSR definitions, and enhances the
instruction encoding logic to support a new schema format. The changes
include introducing a new generator script, updating the encoding
extraction logic to handle new formats, and integrating the
SystemVerilog generation into the build process.
**SystemVerilog Generation:**
- Added a new script `sverilog_generator.py` that generates a
SystemVerilog package (`riscv_decode_package.svh`) with instruction and
CSR encodings, including formatting and argument parsing for flexible
generation.
- Integrated a new Rake task (`gen:sverilog`) to invoke the
SystemVerilog generator, with options for configuration and output
directory.
- Created the `gen/sverilog` output directory as part of the build
process.
**Instruction Encoding Enhancements:**
- Added `build_match_from_format` function to extract encoding match
strings from the new `format` field in instruction definitions,
supporting opcodes with specific bit fields.
- Updated instruction loading logic to use the new
`build_match_from_format` when the legacy `encoding` field is missing,
improving compatibility with new schema definitions.
- Improved handling of RV32/RV64 instruction encodings to ensure both
variants are processed and named correctly.
**CSR Handling:**
- Simplified CSR naming logic by always using the uppercase name without
`.RV32` suffix, regardless of architecture.
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Signed-off-by: Afonso Oliveira <[email protected]>
Signed-off-by: Alieldin Alaa <[email protected]>
Co-authored-by: Afonso Oliveira <[email protected]>
Co-authored-by: Jordan Carlin <[email protected]>
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