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Merge branch 'main' into trap_on_reserved
2 parents 813908e + e83c4bc commit cc9a968

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‎arch/csr/fcsr.yaml‎ renamed to ‎arch/csr/F/fcsr.yaml‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
# yaml-language-server: $schema=../../schemas/csr_schema.json
1+
# yaml-language-server: $schema=../../../schemas/csr_schema.json
22

33
fcsr:
44
long_name: Floating-point control and status register (`frm` + `fflags`)
@@ -93,7 +93,7 @@ fcsr:
9393
length: 32
9494
definedBy: F
9595
fields:
96-
RMODE:
96+
FRM:
9797
location: 7-5
9898
description: |
9999
Rounding modes are encoded as follows:
@@ -179,4 +179,4 @@ fcsr:
179179
Set by hardware when a floating point operation is inexact and stays set until explicitly
180180
cleared by software.
181181
type: RW-H
182-
reset_value: UNDEFINED_LEGAL
182+
reset_value: UNDEFINED_LEGAL

‎arch/csr/hstatus.yaml‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -133,10 +133,10 @@ hstatus:
133133
When `hstatus.VGEIN` != 0, it selects which bit of `hgeip` is currently active in VS-mode.
134134
135135
type(): |
136-
# if NUM_EXTERNAL_GUEST_INTERRUPTS+1 is a power of two (beacuse indexing in `hgeip` starts at 1),
136+
# if NUM_EXTERNAL_GUEST_INTERRUPTS+1 is 63 (beacuse indexing in `hgeip` starts at 1),
137137
# then the field accepts any value.
138138
# Otherwise, it accepts a restricted set of values
139-
if (power_of_2?<6>(NUM_EXTERNAL_GUEST_INTERRUPTS + 1)) {
139+
if (NUM_EXTERNAL_GUEST_INTERRUPTS == 63) {
140140
return CsrFieldType::RW;
141141
} else {
142142
return CsrFieldType::RWR;

‎arch/ext/F.yaml‎

Lines changed: 18 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -239,6 +239,20 @@ F:
239239
Indicates whether or not the `F` extension can be disabled with the `misa.F` bit.
240240
schema:
241241
type: boolean
242+
HW_MSTATUS_FS_DIRTY_UPDATE:
243+
description: |
244+
Indicates whether or not hardware will write to `mstatus.FS`
245+
246+
Values are:
247+
[separator="!"]
248+
!===
249+
h! none ! Hardware never writes `mstatus.FS`
250+
h! precise ! Hardware writes `mstatus.FS` to the Dirty (3) state precisely when F registers are modified
251+
h! imprecise ! Hardware writes `mstatus.FS` imprecisely. This will result in a call to unpredictable() on any attempt to read `mstatus` or write FP state.
252+
!===
253+
schema:
254+
type: string
255+
enum: ["none", "precise", "imprecise"]
242256
MSTATUS_FS_LEGAL_VALUES:
243257
description: |
244258
The set of values that mstatus.FS will accept from a software write.
@@ -251,4 +265,7 @@ F:
251265
uniqueItems: true
252266
also_defined_in: S
253267
extra_validation: |
254-
assert MSTATUS_FS_LEGAL_VALUES.include?(0) && MSTATUS_FS_LEGAL_VALUES.include?(3) if ext?(:F)
268+
assert MSTATUS_FS_LEGAL_VALUES.include?(0) && MSTATUS_FS_LEGAL_VALUES.include?(3) if ext?(:F)
269+
270+
# if HW is writing FS, then Dirty (3) better be a supported value
271+
assert MSTATUS_FS_LEGAL_VALUES.include?(3) if ext?(:F) && (HW_MSTATUS_FS_DIRTY_UPDATE != "none")

‎arch/inst/F/fadd.s.yaml‎

Lines changed: 27 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,27 @@
1+
# yaml-language-server: $schema=../../../schemas/inst_schema.json
2+
3+
fadd.s:
4+
long_name: No synopsis available.
5+
description: |
6+
No description available.
7+
definedBy: F
8+
assembly: fd, fs1, fs2, rm
9+
encoding:
10+
match: 0000000------------------1010011
11+
variables:
12+
- name: fs2
13+
location: 24-20
14+
- name: fs1
15+
location: 19-15
16+
- name: rm
17+
location: 14-12
18+
- name: fd
19+
location: 11-7
20+
access:
21+
s: always
22+
u: always
23+
vs: always
24+
vu: always
25+
data_independent_timing: true
26+
operation(): |
27+

‎arch/inst/F/fclass.s.yaml‎

Lines changed: 73 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,73 @@
1+
# yaml-language-server: $schema=../../../schemas/inst_schema.json
2+
3+
fclass.s:
4+
long_name: Single-precision floating-point classify.
5+
description: |
6+
The `fclass.s` instruction examines the value in floating-point register
7+
_fs1_ and writes to integer register _rd_ a 10-bit mask that indicates
8+
the class of the floating-point number.
9+
The format of the mask is described in the table below.
10+
The corresponding bit in _rd_ will be set if the property is true and
11+
clear otherwise.
12+
All other bits in _rd_ are cleared.
13+
Note that exactly one bit in rd will be set.
14+
`fclass.s` does not set the floating-point exception flags.
15+
16+
.Format of result of `fclass` instruction.
17+
[%autowidth,float="center",align="center",cols="^,<",options="header",]
18+
|===
19+
|_rd_ bit |Meaning
20+
|0 |_rs1_ is latexmath:[$-\infty$].
21+
|1 |_rs1_ is a negative normal number.
22+
|2 |_rs1_ is a negative subnormal number.
23+
|3 |_rs1_ is latexmath:[$-0$].
24+
|4 |_rs1_ is latexmath:[$+0$].
25+
|5 |_rs1_ is a positive subnormal number.
26+
|6 |_rs1_ is a positive normal number.
27+
|7 |_rs1_ is latexmath:[$+\infty$].
28+
|8 |_rs1_ is a signaling NaN.
29+
|9 |_rs1_ is a quiet NaN.
30+
|===
31+
32+
definedBy: F
33+
assembly: xd, fs1
34+
encoding:
35+
match: 111000000000-----001-----1010011
36+
variables:
37+
- name: fs1
38+
location: 19-15
39+
- name: rd
40+
location: 11-7
41+
access:
42+
s: always
43+
u: always
44+
vs: always
45+
vu: always
46+
data_independent_timing: false
47+
operation(): |
48+
check_f_ok($encoding);
49+
50+
Bits<32> sp_value = f[fs1][31:0];
51+
52+
if (is_sp_neg_inf?(sp_value)) {
53+
X[rd] = 1 << 0;
54+
} else if (is_sp_neg_norm?(sp_value)) {
55+
X[rd] = 1 << 1;
56+
} else if (is_sp_neg_subnorm?(sp_value)) {
57+
X[rd] = 1 << 2;
58+
} else if (is_sp_neg_zero?(sp_value)) {
59+
X[rd] = 1 << 3;
60+
} else if (is_sp_pos_zero?(sp_value)) {
61+
X[rd] = 1 << 4;
62+
} else if (is_sp_pos_subnorm?(sp_value)) {
63+
X[rd] = 1 << 5;
64+
} else if (is_sp_pos_norm?(sp_value)) {
65+
X[rd] = 1 << 6;
66+
} else if (is_sp_pos_inf?(sp_value)) {
67+
X[rd] = 1 << 7;
68+
} else if (is_sp_signaling_nan?(sp_value)) {
69+
X[rd] = 1 << 8;
70+
} else {
71+
assert(is_sp_quiet_nan?(sp_value), "Unexpected SP value");
72+
X[rd] = 1 << 9;
73+
}

‎arch/inst/F/fcvt.l.s.yaml‎

Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
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1+
# yaml-language-server: $schema=../../../schemas/inst_schema.json
2+
3+
fcvt.l.s:
4+
long_name: No synopsis available.
5+
description: |
6+
No description available.
7+
definedBy: F
8+
base: 64
9+
assembly: xd, fs1, rm
10+
encoding:
11+
match: 110000000010-------------1010011
12+
variables:
13+
- name: fs1
14+
location: 19-15
15+
- name: rm
16+
location: 14-12
17+
- name: rd
18+
location: 11-7
19+
access:
20+
s: always
21+
u: always
22+
vs: always
23+
vu: always
24+
data_independent_timing: true
25+
operation(): |
26+

‎arch/inst/F/fcvt.lu.s.yaml‎

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Original file line numberDiff line numberDiff line change
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1+
# yaml-language-server: $schema=../../../schemas/inst_schema.json
2+
3+
fcvt.lu.s:
4+
long_name: No synopsis available.
5+
description: |
6+
No description available.
7+
definedBy: F
8+
base: 64
9+
assembly: xd, fs1, rm
10+
encoding:
11+
match: 110000000011-------------1010011
12+
variables:
13+
- name: fs1
14+
location: 19-15
15+
- name: rm
16+
location: 14-12
17+
- name: rd
18+
location: 11-7
19+
access:
20+
s: always
21+
u: always
22+
vs: always
23+
vu: always
24+
data_independent_timing: true
25+
operation(): |
26+

‎arch/inst/F/fcvt.s.l.yaml‎

Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,26 @@
1+
# yaml-language-server: $schema=../../../schemas/inst_schema.json
2+
3+
fcvt.s.l:
4+
long_name: No synopsis available.
5+
description: |
6+
No description available.
7+
definedBy: F
8+
base: 64
9+
assembly: fd, xs1, rm
10+
encoding:
11+
match: 110100000010-------------1010011
12+
variables:
13+
- name: rs1
14+
location: 19-15
15+
- name: rm
16+
location: 14-12
17+
- name: fd
18+
location: 11-7
19+
access:
20+
s: always
21+
u: always
22+
vs: always
23+
vu: always
24+
data_independent_timing: true
25+
operation(): |
26+

‎arch/inst/F/fcvt.s.lu.yaml‎

Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,26 @@
1+
# yaml-language-server: $schema=../../../schemas/inst_schema.json
2+
3+
fcvt.s.lu:
4+
long_name: No synopsis available.
5+
description: |
6+
No description available.
7+
definedBy: F
8+
base: 64
9+
assembly: fd, xs1, rm
10+
encoding:
11+
match: 110100000011-------------1010011
12+
variables:
13+
- name: rs1
14+
location: 19-15
15+
- name: rm
16+
location: 14-12
17+
- name: fd
18+
location: 11-7
19+
access:
20+
s: always
21+
u: always
22+
vs: always
23+
vu: always
24+
data_independent_timing: true
25+
operation(): |
26+

‎arch/inst/F/fcvt.s.w.yaml‎

Lines changed: 50 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,50 @@
1+
# yaml-language-server: $schema=../../../schemas/inst_schema.json
2+
3+
fcvt.s.w:
4+
long_name: Convert signed 32-bit integer to single-precision float
5+
description: |
6+
Converts a 32-bit signed integer in integer register _rs1_ into a floating-point number in
7+
floating-point register _fd_.
8+
9+
All floating-point to integer and integer to floating-point conversion instructions round
10+
according to the _rm_ field.
11+
A floating-point register can be initialized to floating-point positive zero using
12+
`fcvt.s.w rd, x0`, which will never set any exception flags.
13+
14+
All floating-point conversion instructions set the Inexact exception flag if the rounded
15+
result differs from the operand value and the Invalid exception flag is not set.
16+
definedBy: F
17+
assembly: fd, xs1
18+
encoding:
19+
match: 110100000000-------------1010011
20+
variables:
21+
- name: rs1
22+
location: 19-15
23+
- name: rm
24+
location: 14-12
25+
- name: fd
26+
location: 11-7
27+
access:
28+
s: always
29+
u: always
30+
vs: always
31+
vu: always
32+
data_independent_timing: false
33+
operation(): |
34+
check_f_ok($encoding);
35+
36+
Bits<32> int_value = X[rs1];
37+
38+
Bits<1> sign = int_value[31];
39+
40+
RoundingMode rounding_mode = rm_to_mode(rm, $encoding);
41+
42+
if ((int_value & 32'h7fff_ffff) == 0) {
43+
X[fd] = (sign == 1) ? packToF32UI(1, 0x9E, 0) : 0;
44+
} else {
45+
Bits<32> absA = (sign == 1) ? -int_value : int_value;
46+
X[fd] = softfloat_normRoundPackToF32( sign, 0x9C, absA, rounding_mode );
47+
}
48+
49+
mark_f_state_dirty();
50+

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