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hansfbaierHans Baier
hansfbaier
and
Hans Baier
authored
fix inconsistent destination register naming in compressed shift instructions (#1023)
In all the other instructions the destination register is named xd, not rd, except the shift instructions. Furthermore in the assembly attribute of the shift instructions the destination register is designated as xd, not rd, thus causing code generators to generate incorrect code. Signed-off-by: Hans Baier <[email protected]> Co-authored-by: Hans Baier <[email protected]>
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‎backends/instructions_appendix/all_instructions.golden.adoc‎

Lines changed: 20 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -5206,18 +5206,18 @@ This instruction has different encodings in RV32 and RV64
52065206
RV32::
52075207
[wavedrom, ,svg,subs='attributes',width="100%"]
52085208
....
5209-
{"reg":[{"bits":2,"name": 0x2,"type":2},{"bits":5,"name": "shamt != 0","type":4},{"bits":5,"name": "rd","type":4},{"bits":4,"name": 0x0,"type":2}]}
5209+
{"reg":[{"bits":2,"name": 0x2,"type":2},{"bits":5,"name": "shamt != 0","type":4},{"bits":5,"name": "xd","type":4},{"bits":4,"name": 0x0,"type":2}]}
52105210
....
52115211

52125212
RV64::
52135213
[wavedrom, ,svg,subs='attributes',width="100%"]
52145214
....
5215-
{"reg":[{"bits":2,"name": 0x2,"type":2},{"bits":5,"name": "shamt != 0[4:0]","type":4},{"bits":5,"name": "rd","type":4},{"bits":1,"name": "shamt != 0[5]","type":4},{"bits":3,"name": 0x0,"type":2}]}
5215+
{"reg":[{"bits":2,"name": 0x2,"type":2},{"bits":5,"name": "shamt != 0[4:0]","type":4},{"bits":5,"name": "xd","type":4},{"bits":1,"name": "shamt != 0[5]","type":4},{"bits":3,"name": 0x0,"type":2}]}
52165216
....
52175217

52185218
Description::
5219-
Shift the value in rd left by shamt, and store the result back in rd.
5220-
C.SLLI expands into `slli rd, rd, shamt`.
5219+
Shift the value in xd left by shamt, and store the result back in xd.
5220+
C.SLLI expands into `slli xd, xd, shamt`.
52215221

52225222

52235223
Decode Variables::
@@ -5227,7 +5227,7 @@ Decode Variables::
52275227
|===
52285228
|Variable Name |Location
52295229
|shamt |$encoding[6:2]
5230-
|rd |$encoding[11:7]
5230+
|xd |$encoding[11:7]
52315231
|===
52325232

52335233
*RV64:*
@@ -5236,7 +5236,7 @@ Decode Variables::
52365236
|===
52375237
|Variable Name |Location
52385238
|shamt |{$encoding[12], $encoding[6:2]}
5239-
|rd |$encoding[11:7]
5239+
|xd |$encoding[11:7]
52405240
|===
52415241

52425242
Included in::
@@ -5267,19 +5267,19 @@ This instruction has different encodings in RV32 and RV64
52675267
RV32::
52685268
[wavedrom, ,svg,subs='attributes',width="100%"]
52695269
....
5270-
{"reg":[{"bits":2,"name": 0x1,"type":2},{"bits":5,"name": "shamt != 0","type":4},{"bits":3,"name": "rd","type":4},{"bits":6,"name": 0x21,"type":2}]}
5270+
{"reg":[{"bits":2,"name": 0x1,"type":2},{"bits":5,"name": "shamt != 0","type":4},{"bits":3,"name": "xd","type":4},{"bits":6,"name": 0x21,"type":2}]}
52715271
....
52725272

52735273
RV64::
52745274
[wavedrom, ,svg,subs='attributes',width="100%"]
52755275
....
5276-
{"reg":[{"bits":2,"name": 0x1,"type":2},{"bits":5,"name": "shamt != 0[4:0]","type":4},{"bits":3,"name": "rd","type":4},{"bits":2,"name": 0x1,"type":2},{"bits":1,"name": "shamt != 0[5]","type":4},{"bits":3,"name": 0x4,"type":2}]}
5276+
{"reg":[{"bits":2,"name": 0x1,"type":2},{"bits":5,"name": "shamt != 0[4:0]","type":4},{"bits":3,"name": "xd","type":4},{"bits":2,"name": 0x1,"type":2},{"bits":1,"name": "shamt != 0[5]","type":4},{"bits":3,"name": 0x4,"type":2}]}
52775277
....
52785278

52795279
Description::
5280-
Arithmetic shift (the original sign bit is copied into the vacated upper bits) the value in rd right by shamt, and store the result in rd.
5281-
The rd register index should be used as rd+8 (registers x8-x15).
5282-
C.SRAI expands into `srai rd, rd, shamt`.
5280+
Arithmetic shift (the original sign bit is copied into the vacated upper bits) the value in xd right by shamt, and store the result in xd.
5281+
The xd register index should be used as xd+8 (registers x8-x15).
5282+
C.SRAI expands into `srai xd, xd, shamt`.
52835283

52845284

52855285
Decode Variables::
@@ -5289,7 +5289,7 @@ Decode Variables::
52895289
|===
52905290
|Variable Name |Location
52915291
|shamt |$encoding[6:2]
5292-
|rd |$encoding[9:7]
5292+
|xd |$encoding[9:7]
52935293
|===
52945294

52955295
*RV64:*
@@ -5298,7 +5298,7 @@ Decode Variables::
52985298
|===
52995299
|Variable Name |Location
53005300
|shamt |{$encoding[12], $encoding[6:2]}
5301-
|rd |$encoding[9:7]
5301+
|xd |$encoding[9:7]
53025302
|===
53035303

53045304
Included in::
@@ -5329,19 +5329,19 @@ This instruction has different encodings in RV32 and RV64
53295329
RV32::
53305330
[wavedrom, ,svg,subs='attributes',width="100%"]
53315331
....
5332-
{"reg":[{"bits":2,"name": 0x1,"type":2},{"bits":5,"name": "shamt != 0","type":4},{"bits":3,"name": "rd","type":4},{"bits":6,"name": 0x20,"type":2}]}
5332+
{"reg":[{"bits":2,"name": 0x1,"type":2},{"bits":5,"name": "shamt != 0","type":4},{"bits":3,"name": "xd","type":4},{"bits":6,"name": 0x20,"type":2}]}
53335333
....
53345334

53355335
RV64::
53365336
[wavedrom, ,svg,subs='attributes',width="100%"]
53375337
....
5338-
{"reg":[{"bits":2,"name": 0x1,"type":2},{"bits":5,"name": "shamt != 0[4:0]","type":4},{"bits":3,"name": "rd","type":4},{"bits":2,"name": 0x0,"type":2},{"bits":1,"name": "shamt != 0[5]","type":4},{"bits":3,"name": 0x4,"type":2}]}
5338+
{"reg":[{"bits":2,"name": 0x1,"type":2},{"bits":5,"name": "shamt != 0[4:0]","type":4},{"bits":3,"name": "xd","type":4},{"bits":2,"name": 0x0,"type":2},{"bits":1,"name": "shamt != 0[5]","type":4},{"bits":3,"name": 0x4,"type":2}]}
53395339
....
53405340

53415341
Description::
5342-
Shift the value in rd right by shamt, and store the result back in rd.
5343-
The rd register index should be used as rd+8 (registers x8-x15).
5344-
C.SRLI expands into `srli rd, rd, shamt`.
5342+
Shift the value in xd right by shamt, and store the result back in xd.
5343+
The xd register index should be used as xd+8 (registers x8-x15).
5344+
C.SRLI expands into `srli xd, xd, shamt`.
53455345

53465346

53475347
Decode Variables::
@@ -5351,7 +5351,7 @@ Decode Variables::
53515351
|===
53525352
|Variable Name |Location
53535353
|shamt |$encoding[6:2]
5354-
|rd |$encoding[9:7]
5354+
|xd |$encoding[9:7]
53555355
|===
53565356

53575357
*RV64:*
@@ -5360,7 +5360,7 @@ Decode Variables::
53605360
|===
53615361
|Variable Name |Location
53625362
|shamt |{$encoding[12], $encoding[6:2]}
5363-
|rd |$encoding[9:7]
5363+
|xd |$encoding[9:7]
53645364
|===
53655365

53665366
Included in::

‎spec/std/isa/inst/C/c.slli.yaml‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -8,8 +8,8 @@ kind: instruction
88
name: c.slli
99
long_name: Shift left logical immediate
1010
description: |
11-
Shift the value in rd left by shamt, and store the result back in rd.
12-
C.SLLI expands into `slli rd, rd, shamt`.
11+
Shift the value in xd left by shamt, and store the result back in xd.
12+
C.SLLI expands into `slli xd, xd, shamt`.
1313
definedBy:
1414
anyOf:
1515
- C
@@ -22,15 +22,15 @@ encoding:
2222
- name: shamt
2323
location: 6-2
2424
not: 0
25-
- name: rd
25+
- name: xd
2626
location: 11-7
2727
RV64:
2828
match: 000-----------10
2929
variables:
3030
- name: shamt
3131
location: 12|6-2
3232
not: 0
33-
- name: rd
33+
- name: xd
3434
location: 11-7
3535
access:
3636
s: always
@@ -39,7 +39,7 @@ access:
3939
vu: always
4040
operation(): |
4141
# shamt is between 0-63
42-
X[rd] = X[rd] << shamt;
42+
X[xd] = X[xd] << shamt;
4343
4444
# SPDX-SnippetBegin
4545
# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

‎spec/std/isa/inst/C/c.srai.yaml‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -8,9 +8,9 @@ kind: instruction
88
name: c.srai
99
long_name: Shift right arithmetical immediate
1010
description: |
11-
Arithmetic shift (the original sign bit is copied into the vacated upper bits) the value in rd right by shamt, and store the result in rd.
12-
The rd register index should be used as rd+8 (registers x8-x15).
13-
C.SRAI expands into `srai rd, rd, shamt`.
11+
Arithmetic shift (the original sign bit is copied into the vacated upper bits) the value in xd right by shamt, and store the result in xd.
12+
The xd register index should be used as xd+8 (registers x8-x15).
13+
C.SRAI expands into `srai xd, xd, shamt`.
1414
definedBy:
1515
anyOf:
1616
- C
@@ -23,15 +23,15 @@ encoding:
2323
- name: shamt
2424
location: 6-2
2525
not: 0
26-
- name: rd
26+
- name: xd
2727
location: 9-7
2828
RV64:
2929
match: 100-01--------01
3030
variables:
3131
- name: shamt
3232
location: 12|6-2
3333
not: 0
34-
- name: rd
34+
- name: xd
3535
location: 9-7
3636
access:
3737
s: always
@@ -40,7 +40,7 @@ access:
4040
vu: always
4141
operation(): |
4242
# shamt is between 0-63
43-
X[creg2reg(rd)] = X[creg2reg(rd)] >>> shamt;
43+
X[creg2reg(xd)] = X[creg2reg(xd)] >>> shamt;
4444
4545
# SPDX-SnippetBegin
4646
# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

‎spec/std/isa/inst/C/c.srli.yaml‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -8,9 +8,9 @@ kind: instruction
88
name: c.srli
99
long_name: Shift right logical immediate
1010
description: |
11-
Shift the value in rd right by shamt, and store the result back in rd.
12-
The rd register index should be used as rd+8 (registers x8-x15).
13-
C.SRLI expands into `srli rd, rd, shamt`.
11+
Shift the value in xd right by shamt, and store the result back in xd.
12+
The xd register index should be used as xd+8 (registers x8-x15).
13+
C.SRLI expands into `srli xd, xd, shamt`.
1414
definedBy:
1515
anyOf:
1616
- C
@@ -23,15 +23,15 @@ encoding:
2323
- name: shamt
2424
location: 6-2
2525
not: 0
26-
- name: rd
26+
- name: xd
2727
location: 9-7
2828
RV64:
2929
match: 100-00--------01
3030
variables:
3131
- name: shamt
3232
location: 12|6-2
3333
not: 0
34-
- name: rd
34+
- name: xd
3535
location: 9-7
3636
access:
3737
s: always
@@ -40,7 +40,7 @@ access:
4040
vu: always
4141
operation(): |
4242
# shamt is between 0-63
43-
X[creg2reg(rd)] = X[creg2reg(rd)] >> shamt;
43+
X[creg2reg(xd)] = X[creg2reg(xd)] >> shamt;
4444
4545
# SPDX-SnippetBegin
4646
# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

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