Commit d595041
Bumps
[ext/riscv-tests](https://github.com/riscv-software-src/riscv-tests)
from `0494f95` to `355f1fb`.
<details>
<summary>Commits</summary>
<ul>
<li><a
href="https://github.com/riscv-software-src/riscv-tests/commit/355f1fb9b8a7142bee718e4123fea0aa8f49c319"><code>355f1fb</code></a>
CI: Bump GitHub actions to latest versions (<a
href="https://redirect.github.com/riscv-software-src/riscv-tests/issues/619">#619</a>)</li>
<li><a
href="https://github.com/riscv-software-src/riscv-tests/commit/b6941920e88c5c751b03f9a3b88c01f7309a35af"><code>b694192</code></a>
Fix rv32ud-p-fcvt_w and -recoding being redundant with rv32uf</li>
<li><a
href="https://github.com/riscv-software-src/riscv-tests/commit/4bbcf2e7def4c0b37e893baaa5ddaf31e1144e33"><code>4bbcf2e</code></a>
configure: do autoupdate</li>
<li><a
href="https://github.com/riscv-software-src/riscv-tests/commit/8d1e1ca3861bee1e3e26e4e62ec4fe4cdd8503d6"><code>8d1e1ca</code></a>
Remove use of qNaN/sNaN in a different way to fix LLVM build (<a
href="https://redirect.github.com/riscv-software-src/riscv-tests/issues/613">#613</a>)</li>
<li><a
href="https://github.com/riscv-software-src/riscv-tests/commit/40f07e2916d928b265a54fbbe0fc4a6e7b239596"><code>40f07e2</code></a>
Fix rv64ua-amomaxu_w and rv64ua-amominu_w testcases for rv32 (<a
href="https://redirect.github.com/riscv-software-src/riscv-tests/issues/611">#611</a>)</li>
<li><a
href="https://github.com/riscv-software-src/riscv-tests/commit/8b9bd7b8d2df5e126351ff5cec51915bde1e9e5f"><code>8b9bd7b</code></a>
Remove use of qNaN/sNaN to fix LLVM build (<a
href="https://redirect.github.com/riscv-software-src/riscv-tests/issues/612">#612</a>)</li>
<li><a
href="https://github.com/riscv-software-src/riscv-tests/commit/7785754f8f2811e691ec7c1e8f3683e1ed386006"><code>7785754</code></a>
Add test for pmpaddr[G-1] edge cases (<a
href="https://redirect.github.com/riscv-software-src/riscv-tests/issues/609">#609</a>)</li>
<li><a
href="https://github.com/riscv-software-src/riscv-tests/commit/162d3e7b61559dc47d001c6a42bb6c14982b7866"><code>162d3e7</code></a>
Add instret_overflow test</li>
<li><a
href="https://github.com/riscv-software-src/riscv-tests/commit/8edbedf776b4d7b9af1061058a816a9a2a44e9ca"><code>8edbedf</code></a>
Moving env forward (<a
href="https://redirect.github.com/riscv-software-src/riscv-tests/issues/607">#607</a>)</li>
<li><a
href="https://github.com/riscv-software-src/riscv-tests/commit/799d6e807fa1e5b71cc4dace9d75f264c4ff224c"><code>799d6e8</code></a>
Removed irrelevant test (<a
href="https://redirect.github.com/riscv-software-src/riscv-tests/issues/605">#605</a>)</li>
<li>Additional commits viewable in <a
href="https://github.com/riscv-software-src/riscv-tests/compare/0494f954a3d8d2ca9e4972da7a01e94b6a909bce...355f1fb9b8a7142bee718e4123fea0aa8f49c319">compare
view</a></li>
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1 parent c4cae76 commit d595041
1 file changed
+1
-1
lines changedSubmodule riscv-tests updated 31 files
- .github/workflows/debug.yml+1-1
- .github/workflows/spike-openocd-tests.yml+10-10
- benchmarks/Makefile+11-4
- configure.ac+4-4
- env+1-1
- isa/macros/scalar/test_macros.h+111-50
- isa/rv32mi/Makefrag+2
- isa/rv32mi/instret_overflow.S+8
- isa/rv32mi/pmpaddr.S+8
- isa/rv32ud/fcvt_w.S+5-1
- isa/rv32ud/recoding.S+1-1
- isa/rv32ui/Makefrag+2-2
- isa/rv32ui/ld_st.S+7
- isa/rv32ui/st_ld.S+7
- isa/rv64mi/Makefrag+2-1
- isa/rv64mi/access.S-70
- isa/rv64mi/instret_overflow.S+42
- isa/rv64mi/pmpaddr.S+154
- isa/rv64ua/amomaxu_w.S+4
- isa/rv64ua/amominu_w.S+4
- isa/rv64ud/fadd.S+3-1
- isa/rv64ud/fcmp.S+5-3
- isa/rv64ud/fmin.S+4-2
- isa/rv64uf/fadd.S+1-1
- isa/rv64uf/fcmp.S+3-3
- isa/rv64uf/fmin.S+2-2
- isa/rv64ui/Makefrag+2-2
- isa/rv64ui/ld_st.S+130
- isa/rv64ui/st_ld.S+130
- isa/rv64uzfh/fadd.S+1-1
- isa/rv64uzfh/fmin.S+3-3
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