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Xqci Extension v0.9 (#582)
* Xqci(Xqcibm,Xqcicli,Xqcilo) extensions: fix sext() IDL function calls for several instructions: qc.e.lb,qc.e.lh,qc.ext,qc.extd,qc.extdpr,qc.extdprh,qc.extdr,qc.lieq Signed-off-by: Albert Yosher <[email protected]> * Xqci (Xqcibm) extension: Fix IDL code and description increasing shift to 6 bit for all dual-register bitfield extraction instructions, where shift and width of bitfield are in register Signed-off-by: Albert Yosher <[email protected]> * Xqci (Xqcia) extension: fix wrong mantissa bit selection for qc.norm, qc.normu and qc.normeu instructions Signed-off-by: Albert Yosher <[email protected]> * Xqci (Xqcia) extension: fix wrong exponent calculation for qc.normeu instructions Signed-off-by: Albert Yosher <[email protected]> * Xqci (Xqcilsm) extension: Fix IDL code and description of qc.setwm instruction to state that number of words written 0..31. Signed-off-by: Albert Yosher <[email protected]> * Xqci (Xqciint) extension: Fix IDL code for Smdbltrp and Smrnmi spec compatibility for qc.c.mret and qc.c.mnret instructions Signed-off-by: Albert Yosher <[email protected]> --------- Signed-off-by: Albert Yosher <[email protected]>
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‎arch_overlay/qc_iu/ext/Xqci.yaml‎

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requires:
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name: Zca
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version: ">= 1.0.0"
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- version: "0.9.0"
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state: frozen
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ratification_date: null
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contributors:
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- name: Albert Yosher
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company: Qualcomm Technologies, Inc.
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email: [email protected]
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- name: Derek Hower
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company: Qualcomm Technologies, Inc.
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email: [email protected]
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changes:
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- Fix IDL code sign extension logic for qc.e.lb and qc.e.lh instructions
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- Fix IDL code sign extension logic for qc.ext and qc.extd instructions
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- Fix IDL code sign extension logic for qc.extdpr, qc.extdprh and qc.extdr instructions
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- Fix IDL code and description increasing shift to 6 bit for qc.extdr and qc.extdur instructions
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- Fix IDL code and description increasing shift to 6 bit for qc.extdpr and qc.extdprh instructions
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- Fix IDL code and description increasing shift to 6 bit for qc.extdupr and qc.extduprh instructions
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- Fix IDL code sign extension logic for qc.lieq instruction
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- Fix wrong mantissa bit selection in qc.norm, qc.normu and qc.normeu instructions
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- Fix wrong exponent calculation in qc.normeu instruction
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- Fix IDL code and description of qc.setwm instruction to state that number of words written 0..31.
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- Fix IDL code for Smdbltrp and Smrnmi spec compatibility for qc.c.mret and qc.c.mnret instructions
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implies:
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- { name: Xqcia, version: "0.6.0" }
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- { name: Xqciac, version: "0.3.0" }
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- { name: Xqcibi, version: "0.2.0" }
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- { name: Xqcibm, version: "0.7.0" }
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- { name: Xqcicli, version: "0.3.0" }
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- { name: Xqcicm, version: "0.2.0" }
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- { name: Xqcics, version: "0.2.0" }
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- { name: Xqcicsr, version: "0.3.0" }
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- { name: Xqciint, version: "0.6.0" }
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- { name: Xqciio, version: "0.1.0" }
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- { name: Xqcilb, version: "0.2.0" }
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- { name: Xqcili, version: "0.2.0" }
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- { name: Xqcilia, version: "0.2.0" }
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- { name: Xqcilo, version: "0.3.0" }
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- { name: Xqcilsm, version: "0.5.0" }
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- { name: Xqcisim, version: "0.2.0" }
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- { name: Xqcisls, version: "0.2.0" }
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- { name: Xqcisync, version: "0.2.0" }
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requires:
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name: Zca
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version: ">= 1.0.0"
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description: |
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The Xqci extension includes a set of instructions that improve RISC-V code density and
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performance in microontrollers. It fills several gaps:

‎arch_overlay/qc_iu/ext/Xqcia.yaml‎

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- Fix typos in description of qc.shlsat and qc.shlusat instructions
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- Fix bug in qc.shlsat that caused wrong IDL code result
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- Fix clobbering of saturation results in [add|addu|sub]sat instructions
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- version: "0.6.0"
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state: frozen
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ratification_date: null
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contributors:
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- name: Albert Yosher
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company: Qualcomm Technologies, Inc.
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email: [email protected]
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- name: Derek Hower
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company: Qualcomm Technologies, Inc.
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email: [email protected]
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changes:
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- Fix wrong mantissa bit selection in qc.norm, qc.normu and qc.normeu instructions
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- Fix wrong exponent calculation in qc.normeu instruction
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description: |
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The Xqcia extension includes eleven instructions to perform integer arithmetic.
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‎arch_overlay/qc_iu/ext/Xqcibm.yaml‎

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- Fix IDL code and description to look correct in PDF for qc.insbhr and qc.insbh instructions
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- Fix IDL code to to match description for qc.insbr instruction
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requires: { name: Zca, version: ">= 1.0.0" }
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- version: "0.7.0"
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state: frozen
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ratification_date: null
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contributors:
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- name: Albert Yosher
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company: Qualcomm Technologies, Inc.
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email: [email protected]
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- name: Derek Hower
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company: Qualcomm Technologies, Inc.
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email: [email protected]
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changes:
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- Fix IDL code sign extension logic for qc.ext and qc.extd instructions
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- Fix IDL code sign extension logic for qc.extdpr, qc.extdprh and qc.extdr instructions
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- Fix IDL code and description increasing shift to 6 bit for qc.extdr and qc.extdur instructions
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- Fix IDL code and description increasing shift to 6 bit for qc.extdpr and qc.extdprh instructions
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- Fix IDL code and description increasing shift to 6 bit for qc.extdupr and qc.extduprh instructions
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requires: { name: Zca, version: ">= 1.0.0" }
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description: |
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The Xqcibm extension includes thirty eight instructions that perform bit manipulation,
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include insertion and extraction.

‎arch_overlay/qc_iu/ext/Xqcicli.yaml‎

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email: [email protected]
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changes:
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- Add information about instruction formats of each instruction
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- version: "0.3.0"
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state: frozen
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ratification_date: null
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contributors:
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- name: Albert Yosher
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company: Qualcomm Technologies, Inc.
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email: [email protected]
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- name: Derek Hower
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company: Qualcomm Technologies, Inc.
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email: [email protected]
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changes:
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- Fix IDL code sign extension logic for qc.lieq instruction
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description: |
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The Xqcicli extension includes twelve instructions that conditionally
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load an immediate value.

‎arch_overlay/qc_iu/ext/Xqciint.yaml‎

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changes:
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- Add stack checks to qc.c.mienter, qc.c.mienter.nest, qc.c.mileaveret
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requires: { name: Zca, version: ">= 1.0.0" }
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- version: "0.6.0"
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state: frozen
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ratification_date: null
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contributors:
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- name: Albert Yosher
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company: Qualcomm Technologies, Inc.
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email: [email protected]
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- name: Derek Hower
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company: Qualcomm Technologies, Inc.
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email: [email protected]
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changes:
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- Fix IDL code for Smdbltrp and Smrnmi spec compatibility for qc.c.mret and qc.c.mnret instructions
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requires: { name: Zca, version: ">= 1.0.0" }
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description: |
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The Xqciint extension includes eleven instructions to accelerate interrupt
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servicing by performing common actions during ISR prologue/epilogue.

‎arch_overlay/qc_iu/ext/Xqcilo.yaml‎

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changes:
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- Add information about instruction formats of each instruction
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requires: { name: Zca, version: ">= 1.0.0" }
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- version: "0.3.0"
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state: frozen
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ratification_date: null
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contributors:
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- name: Albert Yosher
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company: Qualcomm Technologies, Inc.
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email: [email protected]
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- name: Derek Hower
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company: Qualcomm Technologies, Inc.
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email: [email protected]
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changes:
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- Fix IDL code sign extension logic for qc.e.lb and qc.e.lh instructions
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description: |
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The Xqcilo extension includes eight 48-bit load/stores instructions that use an offset
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larger than can be found in the base RISC-V ISA.

‎arch_overlay/qc_iu/ext/Xqcilsm.yaml‎

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email: [email protected]
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changes:
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- Fix encoding of qc.swmi
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- version: "0.5.0"
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state: frozen
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ratification_date: null
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contributors:
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- name: Albert Yosher
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company: Qualcomm Technologies, Inc.
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email: [email protected]
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- name: Derek Hower
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company: Qualcomm Technologies, Inc.
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email: [email protected]
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changes:
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- Fix IDL code and description of qc.setwm instruction to state that number of words written 0..31.
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description: |
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The Xqcilsm extension includes six instructions that transfer multiple values
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between registers and memory.

‎arch_overlay/qc_iu/inst/Xqci/qc.c.mnret.yaml‎

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CSR[qc.mcause].sw_write(qc_mcause_val_masked |
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(1<<28) | (mnpie_val<<26) | (1<<30) |
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(mnpil_val << 12) | (0xF << 20));
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if (CSR[mnstatus].MNPP != 2'b11) {
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CSR[mstatus].MPRV = 0;
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if (implemented?(ExtensionName::Smdbltrp)) {
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CSR[mstatush].MDT = 1'b0;
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}
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}
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if (CSR[mnstatus].MNPP == 2'b00) {
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set_mode(PrivilegeMode::U);
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} else if (CSR[mnstatus].MNPP == 2'b01) {

‎arch_overlay/qc_iu/inst/Xqci/qc.c.mret.yaml‎

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Bits<4> mpil_val = (qc_mcause_val >> 16) & 0xF;
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CSR[mstatus].MIE = mpie_val;
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CSR[mstatus].MPIE = 1'b1;
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CSR[mstatush].MDT = mpdt_val;
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if (implemented?(ExtensionName::Smdbltrp)) {
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CSR[mstatush].MDT = mpdt_val;
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}
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CSR[qc.mcause].sw_write(qc_mcause_val_masked |
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(1<<27) | (mpie_val<<26) | (0<<29) |
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(mpil_val << 12) | (0xF << 16));
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if (mpdt_val == 1'b0) {
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if (CSR[mstatus].MPP != 2'b11) {
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CSR[mstatus].MPRV = 0;
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}
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if (CSR[mstatus].MPP == 2'b00) {
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set_mode(PrivilegeMode::U);
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} else if (CSR[mstatus].MPP == 2'b01) {

‎arch_overlay/qc_iu/inst/Xqci/qc.e.lb.yaml‎

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vu: always
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operation(): |
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XReg virtual_address = X[rs1] + imm;
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X[rd] = sext(read_memory<8>(virtual_address, $encoding), 7);
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X[rd] = sext(read_memory<8>(virtual_address, $encoding), 8);

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