Changed profile YAML to add "presence" to extensions instead of having separate mandatory and optional lists. Did this to better match CRD and work towards having multiple optional types in RVA23/RVB23.

Author: james-ball-qualcomm

arch/crd/MC-1.yaml

@@ -31,24 +31,24 @@ MC-1:
   extensions:
   - name: I
     version: "~> 2.1"
-    status: mandatory
+    presence: mandatory
   - name: C
     version: "~> 2.2"
-    status: mandatory
+    presence: mandatory
   - name: M
     version: "~> 2.0"
-    status: mandatory
+    presence: mandatory
   - name: Zicsr
     version: "~> 2.0"
-    status: mandatory
+    presence: mandatory
   - name: Zicntr
     version: "~> 2.0"
-    status: mandatory
+    presence: mandatory
     parameters:
         TIME_CSR_IMPLEMENTED: {} # Unconstrained
   - name: Sm
     version: "~> 1.11"
-    status: mandatory
+    presence: mandatory
     parameters:
         MTVEC_BASE_ALIGNMENT_DIRECT: {} # Unconstrained
         MTVEC_BASE_ALIGNMENT_VECTORED: {} # Unconstrained

arch/crd/MockCRD-1.yaml

@@ -24,7 +24,7 @@ MockCRD-1:
 # XXX - Remove version information since specifying priv/unpriv ISA manual should imply this.
   extensions:
   - name: MockExt
-    status: mandatory
+    presence: mandatory
     parameters:
       MOCK_ENUM_2_INTS: {}
       MOCK_ENUM_2_STRINGS: {}
@@ -46,11 +46,11 @@ MockCRD-1:
           contains: { const : DEF }
   - name: I
     version: "~> 2.1"
-    status: mandatory
+    presence: mandatory
     note: Here's a note for the I extension.
   - name: C
     version: "~> 2.2"
-    status: mandatory
+    presence: mandatory
     parameters:
         MUTABLE_MISA_C:
           schema:
@@ -59,19 +59,19 @@ MockCRD-1:
       Here's a multi-line note +
       for the C extension.
   - name: M
-    status: mandatory
+    presence: mandatory
     version: "~> 2.0"
   - name: Zicsr
     version: "~> 2.0"
-    status: mandatory
+    presence: mandatory
   - name: Zicntr
     version: "~> 2.0"
-    status: mandatory
+    presence: mandatory
     parameters:
         TIME_CSR_IMPLEMENTED: {} # Unconstrained
   - name: Sm
     version: "~> 1.11"
-    status: mandatory
+    presence: mandatory
     parameters:
         MTVEC_BASE_ALIGNMENT_DIRECT: {} # Unconstrained
         MTVEC_BASE_ALIGNMENT_VECTORED: {} # Unconstrained
@@ -120,22 +120,34 @@ MockCRD-1:
           schema:
             const: 0
   - name: Zifencei
-    status: optional
+    presence: optional
     note: "Here's a note for Zifencei"
   - name: Zicbop
-    status: optional
+    presence: optional
     note: "Testing CACHE_BLOCK_SIZE parameter which is also defined by Zicbom."
     parameters:
         CACHE_BLOCK_SIZE:
           schema:
             const: 64
   - name: Zicbom
-    status: optional
+    presence: optional
     note: "Testing CACHE_BLOCK_SIZE parameter which is also defined by Zicbop."
     parameters:
         CACHE_BLOCK_SIZE:
           schema:
             const: 64
+  - name: Zba
+    presence: mandatory
+    version: "~> 1.0"
+    note: "Added these as mandatory to see if bug in profiles not listing instructions in appendix is here in CRD too."
+  - name: Zbb
+    presence: mandatory
+    version: "~> 1.0"
+    note: "Added these as mandatory to see if bug in profiles not listing instructions in appendix is here in CRD too."
+  - name: Zbs
+    presence: mandatory
+    version: "~> 1.0"
+    note: "Added these as mandatory to see if bug in profiles not listing instructions in appendix is here in CRD too."
 
   requirement_groups:
     - name: Req-Grp-Any-XLEN

arch/profile/rva20s64.yaml

@@ -15,47 +15,56 @@ rva20s64:
     email: [email protected]
     company: SiFive
   extensions:
-    mandatory:
-    - name: S
-      version: "= 1.11"
-    - name: Zifencei
-      version: "= 2.0"
-      note: |
-        Zifencei is mandated as it is the only standard way to support
-        instruction-cache coherence in RVA20 application processors.  A new
-        instruction-cache coherence mechanism is under development which might
-        be added as an option in the future.
-    - name: Svbare
-      version: "= 1.0"
-      note: |
-        Svbare is a new extension name introduced with RVA20.
-    - name: Sv39
-      version: "= 1.11"
-    - name: Svade
-      version: "~> 1.0"
-      note: |
-        Svbare is a new extension name introduced with RVA20.
+  - name: S
+    presence: mandatory
+    version: "= 1.11"
+  - name: Zifencei
+    presence: mandatory
+    version: "= 2.0"
+    note: |
+      Zifencei is mandated as it is the only standard way to support
+      instruction-cache coherence in RVA20 application processors.  A new
+      instruction-cache coherence mechanism is under development which might
+      be added as an option in the future.
+  - name: Svbare
+    presence: mandatory
+    version: "= 1.0"
+    note: |
+      Svbare is a new extension name introduced with RVA20.
+  - name: Sv39
+    presence: mandatory
+    version: "= 1.11"
+  - name: Svade
+    presence: mandatory
+    version: "~> 1.0"
+    note: |
+      Svbare is a new extension name introduced with RVA20.
 
-        It is subsequently defined in more detail with the ratification of
-        `Svadu`.
-    - name: Ssccptr
-      version: "= 1.0"
-      note: |
-        Ssccptr is a new extension name introduced with RVA20.
-    - name: Sstvecd
-      version: "= 1.0"
-      note: |
-        Sstvecd is a new extension name introduced with RVA20.
-    - name: Sstvala
-      version: "= 1.0"
-      note: |
-        Sstvala is a new extension name introduced with RVA20.
-    optional:
-    - name: Zihpm
-      version: "= 2.0"
-    - name: Sv48
-      version: "= 1.11"
-    - name: Ssu64xl
-      version: "= 1.0"
-      note: |
-        Ssu64xl is a new extension name introduced with RVA20.
+      It is subsequently defined in more detail with the ratification of
+      `Svadu`.
+  - name: Ssccptr
+    presence: mandatory
+    version: "= 1.0"
+    note: |
+      Ssccptr is a new extension name introduced with RVA20.
+  - name: Sstvecd
+    presence: mandatory
+    version: "= 1.0"
+    note: |
+      Sstvecd is a new extension name introduced with RVA20.
+  - name: Sstvala
+    presence: mandatory
+    version: "= 1.0"
+    note: |
+      Sstvala is a new extension name introduced with RVA20.
+  - name: Zihpm
+    presence: optional
+    version: "= 2.0"
+  - name: Sv48
+    presence: optional
+    version: "= 1.11"
+  - name: Ssu64xl
+    presence: optional
+    version: "= 1.0"
+    note: |
+      Ssu64xl is a new extension name introduced with RVA20.