Xqci extension: add Xqciio and Xqcisim sub-extensions, initial spec addition

Signed-off-by: Albert Yosher <[email protected]>

Author: ayosher

cfgs/qc_iu/arch_overlay/ext/Xqci.yaml

@@ -103,6 +103,8 @@ versions:
     company: Qualcomm Technologies, Inc.
     email: [email protected]
   changes:
+    - Added Xqciio sub-extension
+    - Added Xqcisim sub-extension
     - Fix description of qc.shladd instruction
     - Fix description and functionality of qc.c.extu instruction
     - Fix description and functionality of qc.wrapi instruction
@@ -119,11 +121,13 @@ versions:
   - [Xqcics, "0.2.0"]
   - [Xqcicsr, "0.2.0"]
   - [Xqciint, "0.3.0"]
+  - [Xqciio, "0.1.0"]
   - [Xqcilb, "0.2.0"]
   - [Xqcili, "0.2.0"]
   - [Xqcilia, "0.2.0"]
   - [Xqcilo, "0.2.0"]
   - [Xqcilsm, "0.3.0"]
+  - [Xqcisim, "0.1.0"]
   - [Xqcisls, "0.2.0"]
   requires:
     name: Zca

cfgs/qc_iu/arch_overlay/ext/Xqciio.yaml

@@ -0,0 +1,27 @@
+# yaml-language-server: $schema=../../../../schemas/ext_schema.json
+
+$schema: ext_schema.json#
+kind: extension
+name: Xqciio
+type: privileged
+long_name: Qualcomm Input/Output device support
+versions:
+- version: "0.1.0"
+  state: frozen
+  ratification_date: null
+  contributors:
+  - name: Albert Yosher
+    company: Qualcomm Technologies, Inc.
+    email: [email protected]
+  - name: Derek Hower
+    company: Qualcomm Technologies, Inc.
+    email: [email protected]
+description: |
+  The Xqciio extension includes two instructions to access external non-memory-mapped devices for input and output
+
+doc_license:
+  name: Creative Commons Attribution 4.0 International License
+  url: https://creativecommons.org/licenses/by/4.0/
+company:
+  name: Qualcomm Technologies, Inc.
+  url: https://qualcomm.com

cfgs/qc_iu/arch_overlay/ext/Xqcisim.yaml

@@ -0,0 +1,28 @@
+# yaml-language-server: $schema=../../../../schemas/ext_schema.json
+
+$schema: ext_schema.json#
+kind: extension
+name: Xqcisim
+type: unprivileged
+long_name: Qualcomm simulator support hints
+versions:
+- version: "0.1.0"
+  state: frozen
+  ratification_date: null
+  contributors:
+  - name: Albert Yosher
+    company: Qualcomm Technologies, Inc.
+    email: [email protected]
+  - name: Derek Hower
+    company: Qualcomm Technologies, Inc.
+    email: [email protected]
+description: |
+  The Xqcisim extension includes ten hint instructions to interface simulation environment.
+  On real target any instruction from this extension executed as "no-operation" and have no effect.
+
+doc_license:
+  name: Creative Commons Attribution 4.0 International License
+  url: https://creativecommons.org/licenses/by/4.0/
+company:
+  name: Qualcomm Technologies, Inc.
+  url: https://qualcomm.com

cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.ptrace.yaml

@@ -0,0 +1,28 @@
+# yaml-language-server: $schema=../../../schemas/inst_schema.json
+
+$schema: inst_schema.json#
+kind: instruction
+name: qc.c.ptrace
+long_name: Tracing pseudo-instruction (hint) working only in simulation environment
+description: |
+  The tracing instruction have no explicit arguments.
+  Implicit arguments defined by simulation environment implementation.
+  Instruction is used to signal simulator to collect some tracing information.
+  Instruction encoded in CI instruction format.
+definedBy:
+  anyOf:
+    - Xqci
+    - Xqcisim
+assembly: ""
+base: 32
+encoding:
+  match: "0000000000000010"
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  XReg func = 9;
+  XReg arg = 0;
+  iss_syscall(func,arg);

cfgs/qc_iu/arch_overlay/inst/Xqci/qc.inw.yaml

@@ -0,0 +1,35 @@
+# yaml-language-server: $schema=../../../schemas/inst_schema.json
+
+$schema: inst_schema.json#
+kind: instruction
+name: qc.inw
+long_name: Input word from non-memory-mapped device
+description: |
+  Input 32 bits of data into register `rd` from a non-memory-mapped device.
+  Such devices have own address space, unrelated to memory map.
+  Device space address formed by adding `rs1` to  to a unsigned offset `imm`.
+  Instruction encoded in I instruction format.
+definedBy:
+  anyOf:
+    - Xqci
+    - Xqciio
+assembly: xd, imm(xs1)
+base: 32
+encoding:
+  match: -----------------101-----0001011
+  variables:
+    - name: imm
+      location: 31-20
+      left_shift: 2
+    - name: rs1
+      location: 19-15
+    - name: rd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  XReg device_address = X[rs1] + imm;
+  X[rd] = read_device<32>(device_address);

cfgs/qc_iu/arch_overlay/inst/Xqci/qc.outw.yaml

@@ -0,0 +1,35 @@
+# yaml-language-server: $schema=../../../schemas/inst_schema.json
+
+$schema: inst_schema.json#
+kind: instruction
+name: qc.outw
+long_name: Output word to non-memory-mapped device
+description: |
+  Output 32 bits of data from register `rs2` to a non-memory-mapped device.
+  Such devices have own address space, unrelated to memory map.
+  Device space address formed by adding `rs1` to  to a unsigned offset `imm`.
+  Instruction encoded in I instruction format.
+definedBy:
+  anyOf:
+    - Xqci
+    - Xqciio
+assembly: xs2, imm(xs1)
+base: 32
+encoding:
+  match: -----------------100-----0001011
+  variables:
+    - name: imm
+      location: 31-20
+      left_shift: 2
+    - name: rs1
+      location: 19-15
+    - name: rs2
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  XReg device_address = X[rs1] + imm;
+  write_device<32>(device_address, X[rs2]);

cfgs/qc_iu/arch_overlay/inst/Xqci/qc.pcoredump.yaml

@@ -0,0 +1,29 @@
+# yaml-language-server: $schema=../../../schemas/inst_schema.json
+
+$schema: inst_schema.json#
+kind: instruction
+name: qc.pcoredump
+long_name: Print core dump pseudo-instruction (hint) working only in simulation environment
+description: |
+  The print core dump instruction calls simulation environment with no explicit arguments.
+  Implicit arguments are all general purpose registers and CSRs.
+  Simulation environment expected to print the core dump on its console or standard output.
+  The core dump format and content are defined by simulation environment.
+  Instruction encoded in I instruction format.
+definedBy:
+  anyOf:
+    - Xqci
+    - Xqcisim
+assembly: ""
+base: 32
+encoding:
+  match: "01100000000000000010000000010011"
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  XReg func = 8;
+  XReg arg = 0;
+  iss_syscall(func,arg);

cfgs/qc_iu/arch_overlay/inst/Xqci/qc.pexit.yaml

@@ -0,0 +1,30 @@
+# yaml-language-server: $schema=../../../schemas/inst_schema.json
+
+$schema: inst_schema.json#
+kind: instruction
+name: qc.pexit
+long_name: Exit call with register argument pseudo-instruction (hint) working only in simulation environment
+description: |
+  The Exit call instruction calls simulation environment with unsigned `rs1` explicit argument.
+  Simulation environment is expected to complete its execution and return to the system with exit code provided in `rs1`.
+  Instruction encoded in I instruction format.
+definedBy:
+  anyOf:
+    - Xqci
+    - Xqcisim
+assembly: " xs1"
+base: 32
+encoding:
+  match: 101100000000-----010000000010011
+  variables:
+    - name: rs1
+      location: 19-15
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  XReg func = 12;
+  XReg arg = X[rs1];
+  iss_syscall(func,arg);

cfgs/qc_iu/arch_overlay/inst/Xqci/qc.ppreg.yaml

@@ -0,0 +1,30 @@
+# yaml-language-server: $schema=../../../schemas/inst_schema.json
+
+$schema: inst_schema.json#
+kind: instruction
+name: qc.ppreg
+long_name: Print register pseudo-instruction (hint) working only in simulation environment
+description: |
+  The print register instruction calls simulation environment with `rs1` explicit argument.
+  Simulation environment expected to print the register value on its console or standard output.
+  Instruction encoded in I instruction format.
+definedBy:
+  anyOf:
+    - Xqci
+    - Xqcisim
+assembly: " xs1"
+base: 32
+encoding:
+  match: 100000000000-----010000000010011
+  variables:
+    - name: rs1
+      location: 19-15
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  XReg func = 2;
+  XReg arg = X[rs1];
+  iss_syscall(func,arg);

cfgs/qc_iu/arch_overlay/inst/Xqci/qc.ppregs.yaml

@@ -0,0 +1,28 @@
+# yaml-language-server: $schema=../../../schemas/inst_schema.json
+
+$schema: inst_schema.json#
+kind: instruction
+name: qc.ppregs
+long_name: Print all registers pseudo-instruction (hint) working only in simulation environment
+description: |
+  The print registers instruction calls simulation environment with no explicit arguments.
+  Implicit arguments are all general purpose registers.
+  Simulation environment expected to print the all registers value on its console or standard output.
+  Instruction encoded in I instruction format.
+definedBy:
+  anyOf:
+    - Xqci
+    - Xqcisim
+assembly: ""
+base: 32
+encoding:
+  match: "01110000000000000010000000010011"
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  XReg func = 3;
+  XReg arg = 0;
+  iss_syscall(func,arg);