fix(data): use '0' instead of 'zero'

"zero" is not a constant in IDL.

Also, add a comment to "fence" pseudoinstruction, since it maps
to "fence" instruction with "iorw,iorw" operands.

Author: ThinkOpenly

arch/inst/I/addi.yaml

@@ -23,7 +23,7 @@ access:
   vu: always
 data_independent_timing: true
 pseudoinstructions:
-  - when: (xd == zero && xs1 == zero && imm == 0)
+  - when: (xd == 0 && xs1 == 0 && imm == 0)
     to: nop
   - when: imm == 0
     to: mv xd,xs1

arch/inst/I/addiw.yaml

@@ -24,7 +24,7 @@ access:
   vu: always
 data_independent_timing: true
 pseudoinstructions:
-  - when: imm == zero
+  - when: imm == 0
     to: sext.w xd,xs1
 operation(): |
   XReg operand = sext(X[xs1], 31);

arch/inst/I/beq.yaml

@@ -27,7 +27,7 @@ access:
   vs: always
   vu: always
 pseudoinstructions:
-  - when: xs2 == zero
+  - when: xs2 == 0
     to: beqz xs1,imm
 operation(): |
   XReg lhs = X[xs1];

arch/inst/I/bge.yaml

@@ -27,9 +27,9 @@ access:
   vs: always
   vu: always
 pseudoinstructions:
-  - when: xs1 == zero
+  - when: xs1 == 0
     to: blez xs2,imm
-  - when: xs2 == zero
+  - when: xs2 == 0
     to: blez xs1,imm
 operation(): |
   XReg lhs = X[xs1];

arch/inst/I/blt.yaml

@@ -27,9 +27,9 @@ access:
   vs: always
   vu: always
 pseudoinstructions:
-  - when: xs2 == zero
+  - when: xs2 == 0
     to: bltz xs1,imm
-  - when: xs1 == zero
+  - when: xs1 == 0
     to: bgtz xs2,imm
 operation(): |
   XReg lhs = X[xs1];

arch/inst/I/bne.yaml

@@ -27,7 +27,7 @@ access:
   vs: always
   vu: always
 pseudoinstructions:
-  - when: xs2 == zero
+  - when: xs2 == 0
     to: bnez xs1,imm
 operation(): |
   XReg lhs = X[xs1];

arch/inst/I/fence.yaml

@@ -199,7 +199,7 @@ pseudoinstructions:
   - when: (pred == 1) && (succ == 0) && (xd == 0) && (xs1 == 0)
     to: pause
   - when: (pred == 4'b1111) && (succ == 4'b1111)
-    to: fence
+    to: fence # fence => fence iorw,iorw
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

arch/inst/I/jalr.yaml

@@ -26,9 +26,9 @@ access:
   vs: always
   vu: always
 pseudoinstructions:
-  - when: xd == zero
+  - when: xd == 0
     to: jr imm(xs1)
-  - when: (rd == zero && xs1 == x1 && imm == 0)
+  - when: (rd == 0 && xs1 == x1 && imm == 0)
     to: ret
 operation(): |
   XReg returnaddr;

arch/inst/I/slt.yaml

@@ -25,9 +25,9 @@ access:
   vu: always
 data_independent_timing: true
 pseudoinstructions:
-  - when: xs2 == zero
+  - when: xs2 == 0
     to: sltz xd,xs1
-  - when: xs1 == zero
+  - when: xs1 == 0
     to: sgtz xd,xs2
 operation(): |
   XReg src1 = X[xs1];

arch/inst/I/sltu.yaml

@@ -25,7 +25,7 @@ access:
   vu: always
 data_independent_timing: true
 pseudoinstructions:
-  - when: xs1 == zero
+  - when: xs1 == 0
     to: snez xd,xs2
 
 operation(): |