fix(data): make descriptions consistent with the RISC-V style guidelines (#1084)

sudo-apt-abdullah · web-flow · commit effa6b4b166f · 2025-09-18T13:57:48.000Z
...and fix a few spelling mistakes. Closes #1082
diff --git a/backends/instructions_appendix/all_instructions.golden.adoc b/backends/instructions_appendix/all_instructions.golden.adoc
diff --git a/spec/std/isa/inst/D/fadd.d.yaml b/spec/std/isa/inst/D/fadd.d.yaml
@@ -11,8 +11,8 @@ description:
   - id: inst-fadd.d-behaviour
     normative: false
     text: |
-      `FADD.D` is analogous to `FADD.S` and performs double-precision floating-point addition between
-      _fs1_ and _fs2_ and writes the final result to _fd_.
+      The `fadd.d` instruction is analogous to `fadd.s` and performs double-precision floating-point addition between
+      `fs1` and `fs2` and writes the final result to `fd`.
 definedBy: D
 assembly: fd, fs1, fs2, rm
 encoding:
diff --git a/spec/std/isa/inst/D/fclass.d.yaml b/spec/std/isa/inst/D/fclass.d.yaml
@@ -11,12 +11,12 @@ description:
   - id: inst-fclass.d-behaviour
     normative: false
     text: |
-      `FCLASS.D` is defined analogously to its single-precision counterpart, but operates on double-precision operands.
-      It examines the value in floating-point register _fs1_ and writes to integer register _xd_ a 10-bit mask that
+      The `fclass.d` instruction is defined analogously to its single-precision counterpart, but operates on double-precision
+      operands. It examines the value in floating-point register `fs1` and writes to integer register `xd` a 10-bit mask that
       indicates the class of the floating point number.
 
-      The format of the mask is described in the table below. The corresponding bit in _xd_ will be set if the property
-      is true and clear otherwise. All other bits in _xd_ are cleared. Note that exactly one bit in xd will be set.
+      The format of the mask is described in the table below. The corresponding bit in `xd` will be set if the property
+      is true and clear otherwise. All other bits in `xd` are cleared. Note that exactly one bit in `xd` will be set.
 
       .Format of result of `fclass` instruction.
       [%autowidth,float="center",align="center",cols="^,<",options="header",]
diff --git a/spec/std/isa/inst/D/fcvt.d.l.yaml b/spec/std/isa/inst/D/fcvt.d.l.yaml
@@ -11,8 +11,8 @@ description:
   - id: inst-fcvt.d.l-behaviour
     normative: false
     text: |
-      `FCVT.D.L` converts a 64-bit signed integer, in integer register _xs1_ into a double-precision
-      floating-point number in floating-point register _fd_.
+      The `fcvt.d.l` instruction converts a 64-bit signed integer, in integer register `xs1` into a double-precision
+      floating-point number in floating-point register `fd`.
 definedBy: D
 assembly: fd, xs1, rm
 encoding:
diff --git a/spec/std/isa/inst/D/fcvt.d.lu.yaml b/spec/std/isa/inst/D/fcvt.d.lu.yaml
@@ -11,8 +11,8 @@ description:
   - id: inst-fcvt.d.lu-behaviour
     normative: false
     text: |
-      `FCVT.D.LU` converts to or from a 64-bit unsigned integer, _xs1_ into a double-precision
-      floating-point number in floating-point register _fd_.
+      The `fcvt.d.lu` instruction converts to or from a 64-bit unsigned integer, `xs1` into a double-precision
+      floating-point number in floating-point register `fd`.
 definedBy: D
 assembly: fd, xs1, rm
 encoding:
diff --git a/spec/std/isa/inst/D/fcvt.d.s.yaml b/spec/std/isa/inst/D/fcvt.d.s.yaml
@@ -11,10 +11,10 @@ description:
   - id: inst-fcvt.d.s-behaviour
     normative: false
     text: |
-      The single-precision to double-precision conversion instruction, `FCVT.D.S` is encoded in the OP-FP
+      The single-precision to double-precision conversion instruction, `fcvt.d.s` is encoded in the OP-FP
       major opcode space and both the source and destination are floating-point registers. The `xs2` field
       encodes the datatype of the source, and the `fmt` field encodes the datatype of the destination.
-      `FCVT.D.S` will never round.
+      `fcvt.d.s` will never round.
 definedBy: D
 assembly: fd, fs1, rm
 encoding:
diff --git a/spec/std/isa/inst/D/fcvt.d.w.yaml b/spec/std/isa/inst/D/fcvt.d.w.yaml
@@ -11,9 +11,9 @@ description:
   - id: inst-fcvt.d.w-behaviour
     normative: false
     text: |
-      `FCVT.D.W` converts a 32-bit signed integer, in integer register _xs1_ into a double-precision
-      floating-point number in floating-point register _fd_. Note `FCVT.D.W` always produces an exact
-      result and is unaffected by rounding mode.
+      The `fcvt.d.w` instruction converts a 32-bit signed integer, in integer register `xs1` into a double-precision
+      floating-point number in floating-point register `fd`. Note `fcvt.d.w` always produces an exact result and is
+      unaffected by rounding mode.
 definedBy: D
 assembly: fd, xs1, rm
 encoding:
diff --git a/spec/std/isa/inst/D/fcvt.d.wu.yaml b/spec/std/isa/inst/D/fcvt.d.wu.yaml
@@ -11,9 +11,9 @@ description:
   - id: inst-fcvt.d.wu-behaviour
     normative: false
     text: |
-      `FCVT.D.WU` converts a 32-bit unsigned integer in integer register _xs1_ into a double-precision
-      floating-point number in floating-point register _fd_. Note `FCVT.D.WU` always produces an exact
-      result and is unaffected by rounding mode.
+      The `fcvt.d.wu` instruction converts a 32-bit unsigned integer in integer register `xs1` into a double-precision
+      floating-point number in floating-point register `fd`. Note `fcvt.d.wu` always produces an exact result and is
+      unaffected by rounding mode.
 definedBy: D
 assembly: fd, xs1, rm
 encoding:
diff --git a/spec/std/isa/inst/D/fcvt.l.d.yaml b/spec/std/isa/inst/D/fcvt.l.d.yaml
@@ -11,8 +11,8 @@ description:
   - id: inst-fcvt.l.d-behaviour
     normative: false
     text: |
-      `FCVT.L.D` converts a double-precision floating-point number in floating-point register _fs1_
-      to a signed 64-bit integer, in integer register _xd_.
+      The `fcvt.l.d` instruction converts a double-precision floating-point number in floating-point register `fs1`
+      to a signed 64-bit integer, in integer register `xd`.
 definedBy: D
 assembly: xd, fs1, rm
 encoding:
diff --git a/spec/std/isa/inst/D/fcvt.lu.d.yaml b/spec/std/isa/inst/D/fcvt.lu.d.yaml
@@ -11,8 +11,8 @@ description:
   - id: inst-fcvt.lu.d-behaviour
     normative: false
     text: |
-      `FCVT.LU.D` converts a double-precision floating-point number in floating-point register _fs1_
-      to an unsigned 64-bit integer, in integer register _xd_.
+      The `fcvt.lu.d` instruction converts a double-precision floating-point number in floating-point register `fs1`
+      to an unsigned 64-bit integer, in integer register `xd`.
 definedBy: D
 assembly: xd, fs1, rm
 encoding:
diff --git a/spec/std/isa/inst/D/fcvt.s.d.yaml b/spec/std/isa/inst/D/fcvt.s.d.yaml
@@ -11,10 +11,10 @@ description:
   - id: inst-fcvt.s.d-behaviour
     normative: false
     text: |
-      `FCVT.S.D` converts a double-precision floating-point number to a single-precision floating-point number.
-       This is encoded in the OP-FP major opcode space and both the source and destination are floating-point
-       registers. The `xs2` field encodes the datatype of the source, and the `fmt` field encodes the datatype
-       of the destination. `FCVT.S.D` rounds according to the RM field.
+      The `fcvt.s.d` instruction converts a double-precision floating-point number to a single-precision floating-point
+      number. This is encoded in the OP-FP major opcode space and both the source and destination are floating-point
+      registers. The `xs2` field encodes the datatype of the source, and the `fmt` field encodes the datatype of the
+      destination. `fcvt.s.d` rounds according to the `rm` field.
 definedBy: D
 assembly: fd, fs1, rm
 encoding:
diff --git a/spec/std/isa/inst/D/fcvt.w.d.yaml b/spec/std/isa/inst/D/fcvt.w.d.yaml
@@ -11,8 +11,8 @@ description:
   - id: inst-fcvt.w.d-behaviour
     normative: false
     text: |
-      `FCVT.W.D` converts a double-precision floating-point number in floating-point register _fs1_ to a
-      signed 32-bit integer, in integer register _xd_.
+      The `fcvt.w.d` instruction converts a double-precision floating-point number in floating-point register `fs1` to a
+      signed 32-bit integer, in integer register `xd`.
 definedBy: D
 assembly: xd, fs1, rm
 encoding:
diff --git a/spec/std/isa/inst/D/fcvt.wu.d.yaml b/spec/std/isa/inst/D/fcvt.wu.d.yaml
@@ -11,8 +11,8 @@ description:
   - id: inst-fcvt.wu.d-behaviour
     normative: false
     text: |
-      `FCVT.WU.D.d` converts a double-precision floating-point number in floating-point register _fs1_ to an
-      unsigned 32-bit integer, in integer register _xd_.
+      The `fcvt.wu.d` instruction converts a double-precision floating-point number in floating-point register `fs1` to an
+      unsigned 32-bit integer, in integer register `xd`.
 definedBy: D
 assembly: xd, fs1, rm
 encoding:
diff --git a/spec/std/isa/inst/D/fcvtmod.w.d.yaml b/spec/std/isa/inst/D/fcvtmod.w.d.yaml
@@ -11,14 +11,14 @@ description:
   - id: inst-fcvtmod.w.d-behaviour
     normative: false
     text: |
-      `FCVTMOD.W.D` always rounds towards zero. Bits 31:0 are taken from the rounded, unbounded two's
-      complement result, then sign-extended to XLEN bits and written to integer register _xd_. ±∞ and
+      The `fcvtmod.w.d` instruction always rounds towards zero. Bits 31:0 are taken from the rounded, unbounded
+      two's complement result, then sign-extended to XLEN bits and written to integer register `xd`. ±∞ and
       NaN are converted to zero.
 
-      Floating-point exception flags are raised the same as they would be for `FCVT.W.D` with the same input
+      Floating-point exception flags are raised the same as they would be for `fcvt.w.d` with the same input
       operand.
 
-      This instruction is only provided if the D extension is implemented. It is encoded like `FCVT.W.D`, but
+      This instruction is only provided if the D extension is implemented. It is encoded like `fcvt.w.d`, but
       with the `xs2` field set to 8 and the `rm` field set to 1 (RTZ). Other `rm` values are reserved.
 definedBy:
   allOf: [D, Zfa]
diff --git a/spec/std/isa/inst/D/fdiv.d.yaml b/spec/std/isa/inst/D/fdiv.d.yaml
@@ -11,9 +11,8 @@ description:
   - id: inst-fdiv.d-behaviour
     normative: false
     text: |
-      `FDIV.D` performs the double-precision floating-point division of _fs1_ by _fs2_. It is defined analogously
-       to its single-precision counterpart, but operates on double-precision operands and produces double-precision
-       results.
+      The `fdiv.d` instruction performs the double-precision floating-point division of `fs1` by `fs2`. It is defined analogously
+      to its single-precision counterpart, but operates on double-precision operands and produces double-precision results.
 definedBy: D
 assembly: fd, fs1, fs2, rm
 encoding:
diff --git a/spec/std/isa/inst/D/feq.d.yaml b/spec/std/isa/inst/D/feq.d.yaml
@@ -11,7 +11,7 @@ description:
   - id: inst-feq.d-behaviour
     normative: false
     text: |
-      `FEQ.D` writes 1 to _xd_ if _fs1_ and _fs2_ are equal, and 0 otherwise. It is defined analogously to its
+      The `feq.d` instruction writes 1 to `xd` if `fs1` and `fs2` are equal, and 0 otherwise. It is defined analogously to its
       single-precision counterpart, but operates on double-precision operands.
 definedBy: D
 assembly: xd, fs1, fs2
diff --git a/spec/std/isa/inst/D/fld.yaml b/spec/std/isa/inst/D/fld.yaml
@@ -11,8 +11,8 @@ description:
   - id: inst-fld-behaviour
     normative: false
     text: |
-      `FLD` instruction loads a double-precision floating-point value from memory into floating-point
-      register _fd_. It is guaranteed to execute atomically if the effective address is naturally aligned
+      The `fld` instruction loads a double-precision floating-point value from memory into floating-point
+      register `fd`. It is guaranteed to execute atomically if the effective address is naturally aligned
       and XLEN≥64. It doesn't modify the bits being transferred; in particular, the payloads of non-canonical
       NaNs are preserved.
 definedBy: D
diff --git a/spec/std/isa/inst/D/fle.d.yaml b/spec/std/isa/inst/D/fle.d.yaml
@@ -11,7 +11,7 @@ description:
   - id: inst-fle.d-behaviour
     normative: false
     text: |
-      `FLE.D` writes 1 to _xd_ if _fs1_ is less than or equal to _fs2_, and 0 otherwise. It is defined
+      The `fle.d` instruction writes 1 to `xd` if `fs1` is less than or equal to `fs2`, and 0 otherwise. It is defined
       analogously to its single-precision counterpart, but operates on double-precision operands.
 definedBy: D
 assembly: xd, fs1, fs2
diff --git a/spec/std/isa/inst/D/fleq.d.yaml b/spec/std/isa/inst/D/fleq.d.yaml
@@ -11,7 +11,7 @@ description:
   - id: inst-fleq.d-behaviour
     normative: false
     text: |
-      `FLEQ.D` is defined like the `FLE.D` instruction, except that quiet NaN inputs do not cause
+      The `fleq.d` instruction is defined like the `fle.d` instruction, except that quiet NaN inputs do not cause
       the invalid operation exception flag to be set.
 definedBy:
   allOf: [D, Zfa]
diff --git a/spec/std/isa/inst/D/fli.d.yaml b/spec/std/isa/inst/D/fli.d.yaml
@@ -11,8 +11,8 @@ description:
   - id: inst-fli.d-behaviour
     normative: false
     text: |
-      `FLI.D` instruction loads one of 32 double-precision floating-point constants, encoded in the `xs1`
-      field, into floating-point register _fd_. `FLI.D` is encoded like `FLI.S`, but with fmt=D.
+      The `fli.d` instruction instruction loads one of 32 double-precision floating-point constants, encoded in the `xs1`
+      field, into floating-point register `fd`. `fli.d` is encoded like `fli.s`, but with `fmt` set to D.
 definedBy:
   allOf: [D, Zfa]
 assembly: fd, xs1
diff --git a/spec/std/isa/inst/D/flt.d.yaml b/spec/std/isa/inst/D/flt.d.yaml
@@ -11,8 +11,8 @@ description:
   - id: inst-flt.d-behaviour
     normative: false
     text: |
-      `FLT.D` writes 1 to _xd_ if _fs1_ is less than _fs2_, and 0 otherwise. It is defined analogously to its
-      single-precision counterpart, but operate on double-precision operands.
+      The `flt.d` instruction writes 1 to `xd` if `fs1` is less than `fs2`, and 0 otherwise. It is defined analogously to its
+      single-precision counterpart, but operates on double-precision operands.
 definedBy: D
 assembly: xd, fs1, fs2
 encoding:
diff --git a/spec/std/isa/inst/D/fltq.d.yaml b/spec/std/isa/inst/D/fltq.d.yaml
@@ -11,7 +11,7 @@ description:
   - id: inst-fltq.d-behaviour
     normative: false
     text: |
-      `FLTQ.D` is defined like the `FLT.D` instruction, except that quiet NaN inputs do not cause
+      The `fltq.d` instruction is defined like the `flt.d` instruction, except that quiet NaN inputs do not cause
       the invalid operation exception flag to be set.
 definedBy:
   allOf: [D, Zfa]
diff --git a/spec/std/isa/inst/D/fmadd.d.yaml b/spec/std/isa/inst/D/fmadd.d.yaml
@@ -11,7 +11,7 @@ description:
   - id: inst-fmadd.d-behaviour
     normative: false
     text: |
-      `FMADD.D` multiplies the values in _fs1_ and _fs2_, adds the value in _fs3_, and writes the final result to _fd_.
+      The `fmadd.d` instruction multiplies the values in `fs1` and `fs2`, adds the value in `fs3`, and writes the final result to `fd`.
 definedBy: D
 assembly: fd, fs1, fs2, fs3, rm
 encoding:
diff --git a/spec/std/isa/inst/D/fmax.d.yaml b/spec/std/isa/inst/D/fmax.d.yaml
@@ -11,9 +11,9 @@ description:
   - id: inst-fmax.d-behaviour
     normative: false
     text: |
-      `FMAX.D` writes larger of _fs1_ and _fs2_ to _fd_. For the purposes of this instruction, the value
-      `-0.0` is considered to be less than the value `+0.0`. If both inputs are NaNs, the result is the
-      canonical NaN. If only one operand is a NaN, the result is the non-NaN operand. Signaling NaN inputs
+      The `fmax.d` instruction writes larger of `fs1` and `fs2` to `fd`. For the purposes of this instruction,
+      the value `-0.0` is considered to be less than the value `+0.0`. If both inputs are NaNs, the result is
+      the canonical NaN. If only one operand is a NaN, the result is the non-NaN operand. Signaling NaN inputs
       set the invalid operation exception flag, even when the result is not NaN.
 definedBy: D
 assembly: fd, fs1, fs2
diff --git a/spec/std/isa/inst/D/fmaxm.d.yaml b/spec/std/isa/inst/D/fmaxm.d.yaml
@@ -11,7 +11,7 @@ description:
   - id: inst-fmaxm.d-behaviour
     normative: false
     text: |
-      `FMAXM.D` writes larger of _fs1_ and _fs2_ to _fd_. It is defined like `FMAX.D` instruction, except
+      The `fmaxm.d` instruction writes larger of `fs1` and `fs2` to `fd`. It is defined like `fmax.d` instruction, except
       that if either input is NaN, the result is the canonical NaN.
 definedBy:
   allOf: [D, Zfa]
diff --git a/spec/std/isa/inst/D/fmin.d.yaml b/spec/std/isa/inst/D/fmin.d.yaml
@@ -11,9 +11,9 @@ description:
   - id: inst-fmin.d-behaviour
     normative: false
     text: |
-      `FMIN.D` writes smaller of _fs1_ and _fs2_ to _fd_. For the purposes of this instruction, the value
-      `-0.0` is considered to be less than the value `+0.0`. If both inputs are NaNs, the result is the
-      canonical NaN. If only one operand is a NaN, the result is the non-NaN operand. Signaling NaN inputs
+      The `fmin.d` instruction writes smaller of `fs1` and `fs2` to `fd`. For the purposes of this instruction,
+      the value `-0.0` is considered to be less than the value `+0.0`. If both inputs are NaNs, the result is
+      the canonical NaN. If only one operand is a NaN, the result is the non-NaN operand. Signaling NaN inputs
       set the invalid operation exception flag, even when the result is not NaN.
 definedBy: D
 assembly: fd, fs1, fs2
diff --git a/spec/std/isa/inst/D/fminm.d.yaml b/spec/std/isa/inst/D/fminm.d.yaml
@@ -11,7 +11,7 @@ description:
   - id: inst-fminm.d-behaviour
     normative: false
     text: |
-      `FMINM.D` writes smaller of _fs1_ and _fs2_ to _fd_. It is defined like `FMIN.D` instruction, except
+      The `fminm.d` instruction writes smaller of `fs1` and `fs2` to `fd`. It is defined like `fmin.d` instruction, except
       that if either input is NaN, the result is the canonical NaN.
 definedBy:
   allOf: [D, Zfa]
diff --git a/spec/std/isa/inst/D/fmsub.d.yaml b/spec/std/isa/inst/D/fmsub.d.yaml
@@ -11,7 +11,7 @@ description:
   - id: inst-fmsub.d-behaviour
     normative: false
     text: |
-      `FMSUB.D` multiplies the values in _fs1_ and _fs2_, subtracts the value in _fs3_, and writes the final result to _fd_.
+      The `fmsub.d` instruction multiplies the values in `fs1` and `fs2`, subtracts the value in `fs3`, and writes the final result to `fd`.
 definedBy: D
 assembly: fd, fs1, fs2, fs3, rm
 encoding:
diff --git a/spec/std/isa/inst/D/fmul.d.yaml b/spec/std/isa/inst/D/fmul.d.yaml
@@ -11,9 +11,9 @@ description:
   - id: inst-fmul.d-behaviour
     normative: false
     text: |
-      `FMUL.D` performs the double-precision floating-point multiplication between _fs1_ and _fs2_. It is defined
-      analogously to its single-precision counterpart, but operates on double-precision operands and produces
-      double-precision results.
+      The `fmul.d` instruction performs the double-precision floating-point multiplication between `fs1` and `fs2`.
+      It is defined analogously to its single-precision counterpart, but operates on double-precision operands and
+      produces double-precision results.
 definedBy: D
 assembly: fd, fs1, fs2, rm
 encoding:
diff --git a/spec/std/isa/inst/D/fmv.d.x.yaml b/spec/std/isa/inst/D/fmv.d.x.yaml
@@ -11,8 +11,8 @@ description:
   - id: inst-fmv.d.x-behaviour
     normative: false
     text: |
-      `FMV.D.X` moves the double-precision value encoded in `IEEE 754-2008` standard encoding from the integer
-      register _xs1_ to the floating-point register _fd_.
+      The `fmv.d.x` instruction moves the double-precision value encoded in `IEEE 754-2008` standard encoding from the integer
+      register `xs1` to the floating-point register `fd`.
 definedBy: D
 assembly: fd, xs1
 encoding:
diff --git a/spec/std/isa/inst/D/fmv.x.d.yaml b/spec/std/isa/inst/D/fmv.x.d.yaml
@@ -11,8 +11,8 @@ description:
   - id: inst-fmv.x.d-behaviour
     normative: false
     text: |
-      `FMV.X.D` moves the double-precision value in floating-point register _fs1_ to a representation in
-      `IEEE 754-2008` standard encoding in integer register _xd_.
+      The `fmv.x.d` instruction moves the double-precision value in floating-point register `fs1` to a representation in
+      `IEEE 754-2008` standard encoding in integer register `xd`.
 definedBy: D
 assembly: xd, fs1
 encoding:
diff --git a/spec/std/isa/inst/D/fmvh.x.d.yaml b/spec/std/isa/inst/D/fmvh.x.d.yaml
@@ -11,8 +11,8 @@ description:
   - id: inst-fmvh.x.d-behaviour
     normative: false
     text: |
-      `FMVH.X.D` moves bits 63:32 of floating-point register _fs1_ into integer register _xd_. `FMVH.X.D` is used
-      in conjunction with the existing `FMV.X.W` instruction to move a double-precision floating-point number to a
+      The `fmvh.x.d` instruction moves bits 63:32 of floating-point register `fs1` into integer register `xd`. `fmvh.x.d`
+      is used in conjunction with the existing `fmv.x.w` instruction to move a double-precision floating-point number to a
       pair of integer-registers.
 definedBy:
   allOf: [D, Zfa]
diff --git a/spec/std/isa/inst/D/fmvp.d.x.yaml b/spec/std/isa/inst/D/fmvp.d.x.yaml
@@ -11,9 +11,9 @@ description:
   - id: inst-fmvp.d.x-behaviour
     normative: false
     text: |
-      `FMVP.D.X` moves a double-precision number from a pair of integer registers into a floating-point
-      register. Integer registers _xs1_ and _xs2_ supply bits 31:0 and 63:32, respectively; the result
-      is written to floating-point register _fd_.
+      The `fmvp.d.x` instruction moves a double-precision number from a pair of integer registers into a floating-point
+      register. Integer registers `xs1` and `xs2` supply bits 31:0 and 63:32, respectively; the result is written to
+      floating-point register `fd`.
 definedBy:
   allOf: [D, Zfa]
 assembly: fd, xs1, xs2
diff --git a/spec/std/isa/inst/D/fnmadd.d.yaml b/spec/std/isa/inst/D/fnmadd.d.yaml
@@ -11,8 +11,8 @@ description:
   - id: inst-fnmadd.d-behaviour
     normative: false
     text: |
-      `FNMADD.D` multiplies the values in _fs1_ and _fs2_, negates the product, subtracts the value in _fs3_, and
-      writes the final result to _fd_.
+      The `fnmadd.d` instruction multiplies the values in `fs1` and `fs2`, negates the product, subtracts the value in `fs3`, and
+      writes the final result to `fd`.
 definedBy: D
 assembly: fd, fs1, fs2, fs3, rm
 encoding:
diff --git a/spec/std/isa/inst/D/fnmsub.d.yaml b/spec/std/isa/inst/D/fnmsub.d.yaml
diff --git a/spec/std/isa/inst/D/fround.d.yaml b/spec/std/isa/inst/D/fround.d.yaml
diff --git a/spec/std/isa/inst/D/froundnx.d.yaml b/spec/std/isa/inst/D/froundnx.d.yaml
diff --git a/spec/std/isa/inst/D/fsd.yaml b/spec/std/isa/inst/D/fsd.yaml
diff --git a/spec/std/isa/inst/D/fsgnj.d.yaml b/spec/std/isa/inst/D/fsgnj.d.yaml
diff --git a/spec/std/isa/inst/D/fsgnjn.d.yaml b/spec/std/isa/inst/D/fsgnjn.d.yaml
diff --git a/spec/std/isa/inst/D/fsgnjx.d.yaml b/spec/std/isa/inst/D/fsgnjx.d.yaml
diff --git a/spec/std/isa/inst/D/fsqrt.d.yaml b/spec/std/isa/inst/D/fsqrt.d.yaml
diff --git a/spec/std/isa/inst/D/fsub.d.yaml b/spec/std/isa/inst/D/fsub.d.yaml
