fix(data): CBO instructions need parentheses around address register (#805)

Author: ThinkOpenly

arch/inst/Zicbom/cbo.clean.yaml

@@ -36,11 +36,11 @@ description: |
   CBO operations never raise a misaligned address fault.
 
 definedBy: Zicbom
-assembly: xs1
+assembly: (xs1)
 encoding:
   match: 000000000001-----010000000001111
   variables:
-    - name: rs1
+    - name: xs1
       location: 19-15
 access:
   m: always
@@ -67,6 +67,6 @@ access_detail: |
   !===
 
 # operation(): |
-#   let cache_block_address = X[rs1] & ~(CACHE_BLOCK_SIZE-1);
+#   let cache_block_address = X[xs1] & ~(CACHE_BLOCK_SIZE-1);
 
 #   CACHE_BLOCK_CLEAN(cache_block_address);

arch/inst/Zicbom/cbo.flush.yaml

@@ -29,11 +29,11 @@ description: |
 
   CBO operations never raise a misaligned address fault.
 definedBy: Zicbom
-assembly: xs1
+assembly: (xs1)
 encoding:
   match: 000000000010-----010000000001111
   variables:
-    - name: rs1
+    - name: xs1
       location: 19-15
 access:
   m: always
@@ -60,7 +60,7 @@ access_detail: |
   !===
 
 # operation(): |
-#   XReg cache_block_address = X[rs1] & ~(CACHE_BLOCK_SIZE-1);
+#   XReg cache_block_address = X[xs1] & ~(CACHE_BLOCK_SIZE-1);
 #   Boolean has_fault?;
 #   ExceptionCode code;
 

arch/inst/Zicbom/cbo.inval.yaml

@@ -68,11 +68,11 @@ description: |
 
   CBO operations never raise a misaligned address fault.
 definedBy: Zicbom
-assembly: xs1
+assembly: (xs1)
 encoding:
   match: 000000000000-----010000000001111
   variables:
-    - name: rs1
+    - name: xs1
       location: 19-15
 access:
   m: always
@@ -103,7 +103,7 @@ access_detail: |
   !===
 
 # operation(): |
-#   let cache_block_address = X[RS1] & ~(CACHE_BLOCK_SIZE-1);
+#   let cache_block_address = X[xs1] & ~(CACHE_BLOCK_SIZE-1);
 
 #   // zeroing operation can occur in any number of independent stores
 #   for (i=0; i<CACHE_BLOCK_SIZE; i++) {

arch/inst/Zicboz/cbo.zero.yaml

@@ -31,11 +31,11 @@ description: |
 
   CBO operations never raise a misaligned address fault.
 definedBy: Zicboz
-assembly: xs1
+assembly: (xs1)
 encoding:
   match: 000000000100-----010000000001111
   variables:
-    - name: rs1
+    - name: xs1
       location: 19-15
 access:
   m: always
@@ -70,7 +70,7 @@ operation(): |
     raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
   } else {
     XReg mask = CACHE_BLOCK_SIZE - 1;
-    XReg cache_block_vaddr = X[rs1] & ~mask;
+    XReg cache_block_vaddr = X[xs1] & ~mask;
 
     TranslationResult result;
     result = translate(cache_block_vaddr, MemoryOperation::Write, effective_ldst_mode(), $encoding);

backends/instructions_appendix/all_instructions.golden.adoc

@@ -5234,7 +5234,7 @@ Cache Block Clean
 Encoding::
 [wavedrom, ,svg,subs='attributes',width="100%"]
 ....
-{"reg":[{"bits":15,"name": 0x200f,"type":2},{"bits":5,"name": "rs1","type":4},{"bits":12,"name": 0x1,"type":2}]}
+{"reg":[{"bits":15,"name": 0x200f,"type":2},{"bits":5,"name": "xs1","type":4},{"bits":12,"name": 0x1,"type":2}]}
 ....
 
 Description::
@@ -5273,7 +5273,7 @@ Decode Variables::
 [width="100%", cols="1,2", options="header"]
 |===
 |Variable Name |Location
-|rs1 |$encoding[19:15]
+|xs1 |$encoding[19:15]
 |===
 
 Included in::
@@ -5295,7 +5295,7 @@ Cache Block Flush
 Encoding::
 [wavedrom, ,svg,subs='attributes',width="100%"]
 ....
-{"reg":[{"bits":15,"name": 0x200f,"type":2},{"bits":5,"name": "rs1","type":4},{"bits":12,"name": 0x2,"type":2}]}
+{"reg":[{"bits":15,"name": 0x200f,"type":2},{"bits":5,"name": "xs1","type":4},{"bits":12,"name": 0x2,"type":2}]}
 ....
 
 Description::
@@ -5328,7 +5328,7 @@ Decode Variables::
 [width="100%", cols="1,2", options="header"]
 |===
 |Variable Name |Location
-|rs1 |$encoding[19:15]
+|xs1 |$encoding[19:15]
 |===
 
 Included in::
@@ -5350,7 +5350,7 @@ Cache Block Invalidate
 Encoding::
 [wavedrom, ,svg,subs='attributes',width="100%"]
 ....
-{"reg":[{"bits":15,"name": 0x200f,"type":2},{"bits":5,"name": "rs1","type":4},{"bits":12,"name": 0x0,"type":2}]}
+{"reg":[{"bits":15,"name": 0x200f,"type":2},{"bits":5,"name": "xs1","type":4},{"bits":12,"name": 0x0,"type":2}]}
 ....
 
 Description::
@@ -5422,7 +5422,7 @@ Decode Variables::
 [width="100%", cols="1,2", options="header"]
 |===
 |Variable Name |Location
-|rs1 |$encoding[19:15]
+|xs1 |$encoding[19:15]
 |===
 
 Included in::
@@ -5444,7 +5444,7 @@ Cache Block Zero
 Encoding::
 [wavedrom, ,svg,subs='attributes',width="100%"]
 ....
-{"reg":[{"bits":15,"name": 0x200f,"type":2},{"bits":5,"name": "rs1","type":4},{"bits":12,"name": 0x4,"type":2}]}
+{"reg":[{"bits":15,"name": 0x200f,"type":2},{"bits":5,"name": "xs1","type":4},{"bits":12,"name": 0x4,"type":2}]}
 ....
 
 Description::
@@ -5479,7 +5479,7 @@ Decode Variables::
 [width="100%", cols="1,2", options="header"]
 |===
 |Variable Name |Location
-|rs1 |$encoding[19:15]
+|xs1 |$encoding[19:15]
 |===
 
 Included in::