Xqci(Xqcibm,Xqcicli,Xqcilo) extensions: fix sext() IDL function calls for several instructions: qc.e.lb,qc.e.lh,qc.ext,qc.extd,qc.extdpr,qc.extdprh,qc.extdr,qc.lieq

Signed-off-by: Albert Yosher <[email protected]>

Author: ayosher

arch_overlay/qc_iu/ext/Xqci.yaml

@@ -268,6 +268,43 @@ versions:
   requires:
     name: Zca
     version: ">= 1.0.0"
+- version: "0.9.0"
+  state: frozen
+  ratification_date: null
+  contributors:
+  - name: Albert Yosher
+    company: Qualcomm Technologies, Inc.
+    email: [email protected]
+  - name: Derek Hower
+    company: Qualcomm Technologies, Inc.
+    email: [email protected]
+  changes:
+    - Fix IDL code sign extension logic for qc.e.lb and qc.e.lh instructions
+    - Fix IDL code sign extension logic for qc.ext and qc.extd instructions
+    - Fix IDL code sign extension logic for qc.extdpr, qc.extdprh and qc.extdr instructions
+    - Fix IDL code sign extension logic for qc.lieq instruction
+  implies:
+  - { name: Xqcia, version: "0.5.0" }
+  - { name: Xqciac, version: "0.3.0" }
+  - { name: Xqcibi, version: "0.2.0" }
+  - { name: Xqcibm, version: "0.7.0" }
+  - { name: Xqcicli, version: "0.3.0" }
+  - { name: Xqcicm, version: "0.2.0" }
+  - { name: Xqcics, version: "0.2.0" }
+  - { name: Xqcicsr, version: "0.3.0" }
+  - { name: Xqciint, version: "0.5.0" }
+  - { name: Xqciio, version: "0.1.0" }
+  - { name: Xqcilb, version: "0.2.0" }
+  - { name: Xqcili, version: "0.2.0" }
+  - { name: Xqcilia, version: "0.2.0" }
+  - { name: Xqcilo, version: "0.3.0" }
+  - { name: Xqcilsm, version: "0.4.0" }
+  - { name: Xqcisim, version: "0.2.0" }
+  - { name: Xqcisls, version: "0.2.0" }
+  - { name: Xqcisync, version: "0.2.0" }
+  requires:
+    name: Zca
+    version: ">= 1.0.0"
 description: |
   The Xqci extension includes a set of instructions that improve RISC-V code density and
   performance in microontrollers. It fills several gaps:

arch_overlay/qc_iu/ext/Xqcibm.yaml

@@ -88,6 +88,20 @@ versions:
     - Fix IDL code and description to look correct in PDF for qc.insbhr and qc.insbh instructions
     - Fix IDL code to to match description for qc.insbr instruction
   requires: { name: Zca, version: ">= 1.0.0" }
+- version: "0.7.0"
+  state: frozen
+  ratification_date: null
+  contributors:
+  - name: Albert Yosher
+    company: Qualcomm Technologies, Inc.
+    email: [email protected]
+  - name: Derek Hower
+    company: Qualcomm Technologies, Inc.
+    email: [email protected]
+  changes:
+    - Fix IDL code sign extension logic for qc.ext and qc.extd instructions
+    - Fix IDL code sign extension logic for qc.extdpr, qc.extdprh and qc.extdr instructions
+  requires: { name: Zca, version: ">= 1.0.0" }
 description: |
   The Xqcibm extension includes thirty eight instructions that perform bit manipulation,
   include insertion and extraction.

arch_overlay/qc_iu/ext/Xqcicli.yaml

@@ -28,6 +28,18 @@ versions:
     email: [email protected]
   changes:
     - Add information about instruction formats of each instruction
+- version: "0.3.0"
+  state: frozen
+  ratification_date: null
+  contributors:
+  - name: Albert Yosher
+    company: Qualcomm Technologies, Inc.
+    email: [email protected]
+  - name: Derek Hower
+    company: Qualcomm Technologies, Inc.
+    email: [email protected]
+  changes:
+    - Fix IDL code sign extension logic for qc.lieq instruction
 description: |
   The Xqcicli extension includes twelve instructions that conditionally
   load an immediate value.

arch_overlay/qc_iu/ext/Xqcilo.yaml

@@ -29,6 +29,18 @@ versions:
   changes:
     - Add information about instruction formats of each instruction
   requires: { name: Zca, version: ">= 1.0.0" }
+- version: "0.3.0"
+  state: frozen
+  ratification_date: null
+  contributors:
+  - name: Albert Yosher
+    company: Qualcomm Technologies, Inc.
+    email: [email protected]
+  - name: Derek Hower
+    company: Qualcomm Technologies, Inc.
+    email: [email protected]
+  changes:
+    - Fix IDL code sign extension logic for qc.e.lb and qc.e.lh instructions
 description: |
   The Xqcilo extension includes eight 48-bit load/stores instructions that use an offset
   larger than can be found in the base RISC-V ISA.

arch_overlay/qc_iu/inst/Xqci/qc.e.lb.yaml

@@ -31,4 +31,4 @@ access:
   vu: always
 operation(): |
   XReg virtual_address = X[rs1] + imm;
-  X[rd] = sext(read_memory<8>(virtual_address, $encoding), 7);
+  X[rd] = sext(read_memory<8>(virtual_address, $encoding), 8);

arch_overlay/qc_iu/inst/Xqci/qc.e.lh.yaml

@@ -31,4 +31,4 @@ access:
   vu: always
 operation(): |
   XReg virtual_address = X[rs1] + imm;
-  X[rd] = sext(read_memory<16>(virtual_address, $encoding), 15);
+  X[rd] = sext(read_memory<16>(virtual_address, $encoding), 16);

arch_overlay/qc_iu/inst/Xqci/qc.ext.yaml

@@ -36,4 +36,4 @@ access:
 operation(): |
   XReg width = width_minus1 + 1;
   XReg unsigned_extraction = (X[rs1] >> shamt) & ((1 << width) - 1);
-  X[rd] = sext(unsigned_extraction, width_minus1);
+  X[rd] = sext(unsigned_extraction, width);

arch_overlay/qc_iu/inst/Xqci/qc.extd.yaml

@@ -36,4 +36,4 @@ access:
 operation(): |
   Bits<{1'b0, XLEN}*2> pair = {X[rs1 + 1], X[rs1]};
   XReg width = width_minus1 + 1;
-  X[rd] = sext((pair >> shamt) & ((1 << width) - 1), width_minus1);
+  X[rd] = sext((pair >> shamt) & ((1 << width) - 1), width);

arch_overlay/qc_iu/inst/Xqci/qc.extdpr.yaml

@@ -40,7 +40,7 @@ operation(): |
   XReg width = (width_bits > 32) ? 32 : width_bits;
   XReg shamt = X[rs2][4:0];
   if (width > 0) {
-    X[rd] = sext((pair >> shamt) & ((1 << width) - 1), width - 1);
+    X[rd] = sext((pair >> shamt) & ((1 << width) - 1), width);
   } else {
     X[rd] = 0;
   }

arch_overlay/qc_iu/inst/Xqci/qc.extdprh.yaml

@@ -40,7 +40,7 @@ operation(): |
   XReg width = (width_bits > 32) ? 32 : width_bits;
   XReg shamt = X[rs2][20:16];
   if (width > 0) {
-    X[rd] = sext((pair >> shamt) & ((1 << width) - 1), width - 1);
+    X[rd] = sext((pair >> shamt) & ((1 << width) - 1), width);
   } else {
     X[rd] = 0;
   }