feat(schema): add new instruction schema for types/subtypes (#686)

### Add instruction “type” schema & link sub‐types (closes #676)

- **inst_schema.json**:  
- Introduce `type` object under `encoding` with a `$ref` to external
`inst_type/...#.yaml` files
- **inst_type_schema.json**:  
- Import of encoding schema for defining RV32/RV64 encodings for
instruction types
- Lays groundwork for sub‐types in R/I/B/S/U formats as discussed in
#655

---------

Signed-off-by: Afonso Oliveira <[email protected]>
Co-authored-by: Derek Hower <[email protected]>

Author: AFOliveira

arch/inst/Zba/add.uw.yaml

@@ -10,15 +10,17 @@ description: |
   zero-extended least-significant word of rs1.
 definedBy: Zba
 assembly: xd, xs1, xs2
-encoding:
-  match: 0000100----------000-----0111011
-  variables:
-    - name: rs2
-      location: 24-20
-    - name: rs1
-      location: 19-15
-    - name: rd
-      location: 11-7
+format:
+  $inherits:
+    - inst_subtype/R/R-x.yaml#/data
+  opcodes:
+    funct7:
+      display_name: ADD.UW
+      value: 0b0000100
+    funct3:
+      display_name: ADD.UW
+      value: 0b000
+    opcode: { $inherits: inst_opcode/OP-32.yaml#/data }
 access:
   s: always
   u: always
@@ -32,7 +34,7 @@ operation(): |
     raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
   }
 
-  X[rd] = X[rs2] + X[rs1][31:0];
+  X[xd] = X[xs2] + X[xs1][31:0];
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

arch/inst_opcode/OP-32.yaml

@@ -0,0 +1,9 @@
+# yaml-language-server: $schema=../../schemas/inst_opcode_schema.json#
+
+$schema: inst_opcode_schema.json#
+kind: instruction_opcode
+name: OP-32
+
+data:
+  display_name: OP-32
+  value: 0b0111011

arch/inst_subtype/R/R-x.yaml

@@ -0,0 +1,18 @@
+# yaml-language-server: $schema=../../../schemas/inst_subtype_schema.json
+
+$schema: inst_subtype_schema.json#
+kind: instruction_subtype
+name: R-x
+
+data:
+  type: { "$ref": "inst_type/R.yaml#" }
+  subtype: { "$ref": "inst_subtype/R/R-x.yaml#" }
+  opcodes:
+    $inherits: inst_type/R.yaml#/opcodes
+  variables:
+    xs2:
+      $inherits: inst_var/xs2.yaml#/data
+    xs1:
+      $inherits: inst_var/xs1.yaml#/data
+    xd:
+      $inherits: inst_var/xd.yaml#/data

arch/inst_type/R.yaml

@@ -0,0 +1,21 @@
+# yaml-language-server: $schema=../../schemas/inst_type_schema.json#
+
+$schema: inst_type_schema.json#
+kind: instruction_type
+name: R
+description: R-type instructions usually have two source registers and one destination registers
+length: 32
+opcodes:
+  funct7:
+    location: 31-25
+  funct3:
+    location: 14-12
+  opcode:
+    location: 6-0
+variables:
+  rs2:
+    location: 24-20
+  rs1:
+    location: 19-15
+  rd:
+    location: 11-7

arch/inst_var/xd.yaml

@@ -0,0 +1,9 @@
+# yaml-language-server: $schema=../../schemas/inst_var_schema.json#
+
+$schema: inst_var_schema.json#
+kind: instruction_variable
+name: xd
+
+data:
+  $inherits: inst_type/R.yaml#/variables/rd
+  type: { "$ref": "inst_var_type/x_dst_reg.yaml#" }

arch/inst_var/xs1.yaml

@@ -0,0 +1,9 @@
+# yaml-language-server: $schema=../../schemas/inst_var_schema.json#
+
+$schema: inst_var_schema.json#
+kind: instruction_variable
+name: xs1
+
+data:
+  $inherits: inst_type/R.yaml#/variables/rs1
+  type: { "$ref": "inst_var_type/x_src_reg.yaml#" }

arch/inst_var/xs2.yaml

@@ -0,0 +1,9 @@
+# yaml-language-server: $schema=../../schemas/inst_var_schema.json#
+
+$schema: inst_var_schema.json#
+kind: instruction_variable
+name: xs2
+
+data:
+  $inherits: inst_type/R.yaml#/variables/rs2
+  type: { "$ref": "inst_var_type/x_src_reg.yaml#" }

arch/inst_var_type/x_dst_reg.yaml

@@ -0,0 +1,8 @@
+# yaml-language-server: $schema=../../schemas/inst_var_type_schema.json#
+
+$schema: inst_var_type_schema.json#
+kind: instruction_variable_type
+name: x_dst_reg
+type: register_reference
+register_file: X
+access: W

arch/inst_var_type/x_src_reg.yaml

@@ -0,0 +1,8 @@
+# yaml-language-server: $schema=../../schemas/inst_var_type_schema.json#
+
+$schema: inst_var_type_schema.json#
+kind: instruction_variable_type
+name: x_src_reg
+type: register_reference
+register_file: X
+access: R

backends/cfg_html_doc/templates/inst.adoc.erb

@@ -33,7 +33,7 @@ RV64::
 <%- else -%>
 [wavedrom, ,svg,subs='attributes',width="100%"]
 ....
-<%= JSON.dump inst.wavedrom_desc(cfg_arch.param_values["MXLEN"]) %>
+<%= JSON.dump inst.wavedrom_desc(inst.base.nil? ? cfg_arch.param_values["MXLEN"] : inst.base) %>
 ....
 <%- end -%>
 
@@ -89,7 +89,7 @@ RV64::
 <%- else -%>
 [source,idl]
 ----
-<%- inst.decode_variables(cfg_arch.param_values["MXLEN"]).each do |d| -%>
+<%- inst.decode_variables(inst.base.nil? ? cfg_arch.param_values["MXLEN"] : inst.base).each do |d| -%>
 <%= d.sext? ? 'signed ' : '' %>Bits<<%= d.size %>> <%= d.name %> = <%= d.extract %>;
 <%- end -%>
 ----
@@ -120,7 +120,7 @@ Original::
 ====
 <%- end -%>
 
-<%- exception_list = inst.reachable_exceptions_str() -%>
+<%- exception_list = inst.reachable_exceptions_str(inst.base.nil? ? cfg_arch.param_values["MXLEN"] : inst.base) -%>
 <%- unless exception_list.empty? -%>
 == Exceptions