fix: correct "writeable" to "writable" (#728)

Both are used in places. While "writeable" is generally defined as "an
alternative spelling of 'writable'", the latter seems to be generally
accepted as correct/preferred. The RISC-V ISA specification uses
"writable".

BREAKING CHANGE: Change spelling of "writeable" to "writeable"
everywhere

The spelling of "writeable" is corrected to "writable" everywhere,
including CSR schema and configuration parameters.

Author: ThinkOpenly

arch/csr/F/fcsr.yaml

@@ -5,7 +5,7 @@ kind: csr
 name: fcsr
 long_name: Floating-point control and status register (`frm` + `fflags`)
 address: 0x003
-writeable: true
+writable: true
 description: |
   The floating-point control and status register, `fcsr`, is a RISC-V
   control and status register (CSR). It is a 32-bit read/write register

arch/csr/H/henvcfg.yaml

@@ -4,7 +4,7 @@ $schema: "csr_schema.json#"
 kind: csr
 name: henvcfg
 address: 0x60A
-writeable: true
+writable: true
 long_name: Hypervisor Environment Configuration
 description: |
   The henvcfg CSR is a 64-bit read/write register that controls certain characteristics of the

arch/csr/H/henvcfgh.yaml

@@ -4,7 +4,7 @@ $schema: "csr_schema.json#"
 kind: csr
 name: henvcfgh
 address: 0x61A
-writeable: true
+writable: true
 base: 32
 long_name: most-significant 32 bits of Hypervisor Environment Configuration
 description: |

arch/csr/H/hgatp.yaml

@@ -102,7 +102,7 @@ description: |
   HFENCE.GVMA instruction (see <<hfence.vma>>) before or
   after writing `hgatp`.
 address: 0x680
-writeable: true
+writable: true
 priv_mode: S
 definedBy: H
 length: SXLEN

arch/csr/H/htimedelta.yaml

@@ -15,7 +15,7 @@ description: |
   `htimedelta` may be used to represent negative time offsets.
 
 address: 0x605
-writeable: true
+writable: true
 priv_mode: S
 definedBy: H
 length: 64

arch/csr/H/htimedeltah.yaml

@@ -8,7 +8,7 @@ description: |
   Upper half of the `htimedelta` CSR.
 
 address: 0x615
-writeable: true
+writable: true
 priv_mode: S
 definedBy: H
 length: 32

arch/csr/H/htinst.yaml

@@ -4,7 +4,7 @@ $schema: "csr_schema.json#"
 kind: csr
 name: htinst
 address: 0x64a
-writeable: true
+writable: true
 long_name: Hypervisor Trap Instruction Register
 description: |
   When a trap is taken into HS-mode, mtinst is written with a value that, if nonzero,

arch/csr/H/htval.yaml

@@ -4,7 +4,7 @@ $schema: "csr_schema.json#"
 kind: csr
 name: htval
 address: 0x643
-writeable: true
+writable: true
 long_name: Hypervisor Trap Value Register
 description: |
   When a trap is taken into HS-mode, htval is written with additional exception-specific information, alongside stval, to assist software in handling the trap.

arch/csr/H/mtinst.yaml

@@ -4,7 +4,7 @@ $schema: "csr_schema.json#"
 kind: csr
 name: mtinst
 address: 0x34a
-writeable: true
+writable: true
 long_name: Machine Trap Instruction Register
 description: |
   When a trap is taken into M-mode, mtinst is written with a value that, if nonzero,

arch/csr/H/mtval2.yaml

@@ -4,7 +4,7 @@ $schema: "csr_schema.json#"
 kind: csr
 name: mtval2
 address: 0x34b
-writeable: true
+writable: true
 long_name: Machine Second Trap Value Register
 description: |
   When a trap is taken into M-mode from a virtual mode, mtval2 is written with additional exception-specific information,