Support projects using encoding.h through C Header Generator

[cmd05]

Several projects utilize encoding.h header provided by riscv-opcodes. These projects can benefit from using the header provided from UDB containing up to date information. These projects include:

OpenOCD: https://github.com/openocd-org/openocd/blob/master/src/target/riscv/encoding.h
Spike: https://github.com/riscv-software-src/riscv-isa-sim/blob/master/riscv/encoding.h

The header can be generated using the command ./do gen:c_header. Summary of the following information:

• Hardcoded information present as a seperate header in riscv-opcodes
• Missing causes in DECLARE_CAUSE or have slightly different naming. Ex: CAUSE_DOUBLE_TRAP is not present in current generator
• Missing CSRs. Ex: DECLARE_CSR(dscratch0, CSR_DSCRATCH0) is not present
• Missing instruction declarations. Ex: DECLARE_INSN(add_uw, ...)

By filling these gaps, the C header generator is a viable option for the above mentioned projects and possibly others. @AFOliveira

List of Missing Information

Missing CSR entries

• Many CSRs are directly present in the header encoding.h in riscv-opcodes, which are not part of the generated header.
• The 'High' bit CSRs are present with _RV32 suffix, so there is a naming difference to the ones present in riscv-opcodes. Ex: CSR_MHPMCOUNTER10H is present as CSR_MHPMCOUNTER10H_RV32.
• Excluding the ones in encoding.h, the following are missing:

List

• CSR_DSCRATCH0
• CSR_DSCRATCH1
• CSR_HGEIE
• CSR_HGEIP
• CSR_HIDELEG
• CSR_HIDELEGH
• CSR_HIE
• CSR_HIP
• CSR_MCTRCTL
• CSR_HVICTL
• CSR_HVIEN
• CSR_HVIENH
• CSR_HVIP
• CSR_HVIPH
• CSR_HVIPRIO1
• CSR_HVIPRIO1H
• CSR_HVIPRIO2
• CSR_HVIPRIO2H

• The following CSRs are missing and in the form MASK_* or MATCH_*:

List

• MASK_ADD_UW
• MASK_ANDN
• MASK_BEQI
• MASK_BNEI
• MASK_CLMUL
• MASK_CLMULH
• MASK_CM_JALT
• MASK_C_MOP_1
• MASK_C_MOP_11
• MASK_C_MOP_13
• MASK_C_MOP_15
• MASK_C_MOP_3
• MASK_C_MOP_5
• MASK_C_MOP_7
• MASK_C_MOP_9
• MASK_C_SSPOPCHK_X5
• MASK_C_SSPUSH_X1
• MASK_GORCI
• MASK_GREVI
• MASK_MOP_RR_0
• MASK_MOP_RR_1
• MASK_MOP_RR_2
• MASK_MOP_RR_3
• MASK_MOP_RR_4
• MASK_MOP_RR_5
• MASK_MOP_RR_6
• MASK_MOP_RR_7
• MASK_MOP_R_0
• MASK_MOP_R_1
• MASK_MOP_R_10
• MASK_MOP_R_11
• MASK_MOP_R_12
• MASK_MOP_R_13
• MASK_MOP_R_14
• MASK_MOP_R_15
• MASK_MOP_R_16
• MASK_MOP_R_17
• MASK_MOP_R_18
• MASK_MOP_R_19
• MASK_MOP_R_2
• MASK_MOP_R_20
• MASK_MOP_R_21
• MASK_MOP_R_22
• MASK_MOP_R_23
• MASK_MOP_R_24
• MASK_MOP_R_25
• MASK_MOP_R_26
• MASK_MOP_R_27
• MASK_MOP_R_28
• MASK_MOP_R_29
• MASK_MOP_R_3
• MASK_MOP_R_30
• MASK_MOP_R_31
• MASK_MOP_R_4
• MASK_MOP_R_5
• MASK_MOP_R_6
• MASK_MOP_R_7
• MASK_MOP_R_8
• MASK_MOP_R_9
• MASK_ORN
• MASK_PAUSE
• MASK_PREFETCH_I
• MASK_PREFETCH_R
• MASK_PREFETCH_W
• MASK_ROL
• MASK_ROLW
• MASK_ROR
• MASK_RORW
• MASK_SHFLI
• MASK_UNSHFLI
• MASK_VFBDOT_VV
• MASK_VFEXT_VF2
• MASK_VFNCVTBF16_SAT_F_F_W
• MASK_VFNCVT_F_F_Q
• MASK_VFNCVT_SAT_F_F_Q
• MASK_VFQBDOT_ALT_VV
• MASK_VFQBDOT_VV
• MASK_VFQLDOT_ALT_VV
• MASK_VFQLDOT_VV
• MASK_VFWBDOT_VV
• MASK_VFWLDOT_VV
• MASK_VQBDOTS_VV
• MASK_VQBDOTU_VV
• MASK_VQDOTSU_VV
• MASK_VQDOTSU_VX
• MASK_VQDOTUS_VX
• MASK_VQDOTU_VV
• MASK_VQDOTU_VX
• MASK_VQDOT_VV
• MASK_VQDOT_VX
• MASK_VQLDOTS_VV
• MASK_VQLDOTU_VV
• MASK_XNOR
• MASK_XPERM16
• MASK_XPERM32
• MATCH_ADD_UW
• MATCH_ANDN
• MATCH_BEQI
• MATCH_BNEI
• MATCH_CLMUL
• MATCH_CLMULH
• MATCH_CM_JALT
• MATCH_C_MOP_1
• MATCH_C_MOP_11
• MATCH_C_MOP_13
• MATCH_C_MOP_15
• MATCH_C_MOP_3
• MATCH_C_MOP_5
• MATCH_C_MOP_7
• MATCH_C_MOP_9
• MATCH_C_SSPOPCHK_X5
• MATCH_C_SSPUSH_X1
• MATCH_GORCI
• MATCH_GREVI
• MATCH_MOP_RR_0
• MATCH_MOP_RR_1
• MATCH_MOP_RR_2
• MATCH_MOP_RR_3
• MATCH_MOP_RR_4
• MATCH_MOP_RR_5
• MATCH_MOP_RR_6
• MATCH_MOP_RR_7
• MATCH_MOP_R_0
• MATCH_MOP_R_1
• MATCH_MOP_R_10
• MATCH_MOP_R_11
• MATCH_MOP_R_12
• MATCH_MOP_R_13
• MATCH_MOP_R_14
• MATCH_MOP_R_15
• MATCH_MOP_R_16
• MATCH_MOP_R_17
• MATCH_MOP_R_18
• MATCH_MOP_R_19
• MATCH_MOP_R_2
• MATCH_MOP_R_20
• MATCH_MOP_R_21
• MATCH_MOP_R_22
• MATCH_MOP_R_23
• MATCH_MOP_R_24
• MATCH_MOP_R_25
• MATCH_MOP_R_26
• MATCH_MOP_R_27
• MATCH_MOP_R_28
• MATCH_MOP_R_29
• MATCH_MOP_R_3
• MATCH_MOP_R_30
• MATCH_MOP_R_31
• MATCH_MOP_R_4
• MATCH_MOP_R_5
• MATCH_MOP_R_6
• MATCH_MOP_R_7
• MATCH_MOP_R_8
• MATCH_MOP_R_9
• MATCH_ORN
• MATCH_PAUSE

Missing INSN_FIELD entries

Currently the generator only creates 18 INSN_FIELD entries. The following are missing:

List

• INSN_FIELD_AMOOP
• INSN_FIELD_AQ
• INSN_FIELD_AQRL
• INSN_FIELD_BIMM12HI
• INSN_FIELD_BIMM12LO
• INSN_FIELD_BS
• INSN_FIELD_C_BIMM9HI
• INSN_FIELD_C_BIMM9LO
• INSN_FIELD_C_IMM12
• INSN_FIELD_C_IMM6HI
• INSN_FIELD_C_IMM6LO
• INSN_FIELD_C_INDEX
• INSN_FIELD_C_MOP_T
• INSN_FIELD_C_NZIMM10HI
• INSN_FIELD_C_NZIMM10LO
• INSN_FIELD_C_NZIMM18HI
• INSN_FIELD_C_NZIMM18LO
• INSN_FIELD_C_NZIMM6HI
• INSN_FIELD_C_NZIMM6LO
• INSN_FIELD_C_NZUIMM10
• INSN_FIELD_C_NZUIMM5
• INSN_FIELD_C_NZUIMM6HI
• INSN_FIELD_C_NZUIMM6LO
• INSN_FIELD_C_RLIST
• INSN_FIELD_C_RS1_N0
• INSN_FIELD_C_RS2
• INSN_FIELD_C_RS2_E
• INSN_FIELD_C_RS2_N0
• INSN_FIELD_C_SPIMM
• INSN_FIELD_C_SREG1
• INSN_FIELD_C_SREG2
• INSN_FIELD_C_UIMM1
• INSN_FIELD_C_UIMM10SPHI
• INSN_FIELD_C_UIMM10SPLO
• INSN_FIELD_C_UIMM10SP_S
• INSN_FIELD_C_UIMM2
• INSN_FIELD_C_UIMM7HI
• INSN_FIELD_C_UIMM7LO
• INSN_FIELD_C_UIMM8HI
• INSN_FIELD_C_UIMM8LO
• INSN_FIELD_C_UIMM8SPHI
• INSN_FIELD_C_UIMM8SPLO
• INSN_FIELD_C_UIMM8SP_S
• INSN_FIELD_C_UIMM9HI
• INSN_FIELD_C_UIMM9LO
• INSN_FIELD_C_UIMM9SPHI
• INSN_FIELD_C_UIMM9SPLO
• INSN_FIELD_C_UIMM9SP_S
• INSN_FIELD_FM
• INSN_FIELD_FUNCT2
• INSN_FIELD_IMM12
• INSN_FIELD_IMM12HI
• INSN_FIELD_IMM12LO
• INSN_FIELD_IMM2
• INSN_FIELD_IMM20
• INSN_FIELD_IMM3
• INSN_FIELD_IMM4
• INSN_FIELD_IMM5
• INSN_FIELD_IMM6
• INSN_FIELD_JIMM20
• INSN_FIELD_MOP_RR_T_27_26
• INSN_FIELD_MOP_RR_T_30
• INSN_FIELD_MOP_R_T_21_20
• INSN_FIELD_MOP_R_T_27_26
• INSN_FIELD_MOP_R_T_30
• INSN_FIELD_NF
• INSN_FIELD_RC
• INSN_FIELD_RD_E
• INSN_FIELD_RD_N0
• INSN_FIELD_RD_N0_E
• INSN_FIELD_RD_N2
• INSN_FIELD_RD_P
• INSN_FIELD_RD_P_E
• INSN_FIELD_RD_RS1
• INSN_FIELD_RD_RS1_N0
• INSN_FIELD_RD_RS1_P
• INSN_FIELD_RL
• INSN_FIELD_RNUM
• INSN_FIELD_RS1_N0
• INSN_FIELD_RS1_P
• INSN_FIELD_RS2_E
• INSN_FIELD_RS2_EQ_RS1
• INSN_FIELD_RS2_P
• INSN_FIELD_RS2_P_E
• INSN_FIELD_RT
• INSN_FIELD_SHAMTD
• INSN_FIELD_SHAMTQ
• INSN_FIELD_SHAMTW
• INSN_FIELD_SHAMTW4
• INSN_FIELD_SIMM5
• INSN_FIELD_VD
• INSN_FIELD_VM
• INSN_FIELD_VS1
• INSN_FIELD_VS2
• INSN_FIELD_VS3
• INSN_FIELD_WD
• INSN_FIELD_ZIMM10
• INSN_FIELD_ZIMM11
• INSN_FIELD_ZIMM5
• INSN_FIELD_ZIMM6HI
• INSN_FIELD_ZIMM6LO

Missing DECLARE_INSN entries

Missing instructions in generated header:

List

• add_uw
• andn
• beqi
• bnei
• c_mop_1
• c_mop_11
• c_mop_13
• c_mop_15
• c_mop_3
• c_mop_5
• c_mop_7
• c_mop_9
• c_mop_N
• c_sspopchk_x5
• c_sspush_x1
• clmul
• clmulh
• cm_jalt
• gorci
• grevi
• mop_r_0
• mop_r_1
• mop_r_10
• mop_r_11
• mop_r_12
• mop_r_13
• mop_r_14
• mop_r_15
• mop_r_16
• mop_r_17
• mop_r_18
• mop_r_19
• mop_r_2
• mop_r_20
• mop_r_21
• mop_r_22
• mop_r_23
• mop_r_24
• mop_r_25
• mop_r_26
• mop_r_27
• mop_r_28
• mop_r_29
• mop_r_3
• mop_r_30
• mop_r_31
• mop_r_4
• mop_r_5
• mop_r_6
• mop_r_7
• mop_r_8
• mop_r_9
• mop_r_N
• mop_rr_0
• mop_rr_1
• mop_rr_2
• mop_rr_3
• mop_rr_4
• mop_rr_5
• mop_rr_6
• mop_rr_7
• mop_rr_N
• orn
• pause
• prefetch_i
• prefetch_r
• prefetch_w
• rol
• rolw
• ror
• rorw
• shfli
• unshfli
• vfbdot_vv
• vfext_vf2
• vfncvt_f_f_q
• vfncvt_sat_f_f_q
• vfncvtbf16_sat_f_f_w
• vfqbdot_alt_vv
• vfqbdot_vv
• vfqldot_alt_vv
• vfqldot_vv
• vfwbdot_vv
• vfwldot_vv
• vqbdots_vv
• vqbdotu_vv
• vqdot_vv
• vqdot_vx
• vqdotsu_vv
• vqdotsu_vx
• vqdotu_vv
• vqdotu_vx
• vqdotus_vx
• vqldots_vv
• vqldotu_vv
• xnor
• xperm16
• xperm32

Missing DECLARE_CAUSE entries

There are 22 DECLARE_CAUSE entries in the riscv-opcodes encoding header and 20 in the one generated by the UDB generator. Some of the names are different in UDB but refer to the same cause, so it is better to check these manually.

[AFOliveira]

Hi thanks for the summary!

Can you please find all missing declarations and list them here?

[cmd05]

@AFOliveira I have added the missing information in the issue description. Could you check.

[AFOliveira]

@cmd05 I think some of this Instructions are already in the UDB, can you check why they are not getting loaded into the output?

Moreover, can you please add to the list if these are in UDB or not. So that we can understand what to do to move forward, either add more info or modify the script (or most likely do both).

[ThinkOpenly]

One nit, you said:

The following CSRs are missing and in the form MASK_* or MATCH_*

That list is actually instructions (not CSRs).

There is a lot of information here.

Some of the CSRs are buried in old PRs, like #617 and #991, but some are definitely missing. What information is required for those missing CSRs to complete the content for encoding.h? It might be easy to add the basics, and go back and add the rest later.

Some of the instructions are missing because they are using a different encoding schema, for example, ADD_UW, but I thought we had modified the generation script to account for that... see PR #1092 (merged).

The MOP instructions are all there, so we need to understand why they are appearing on the "missing" list. They use "layouts", so maybe that's causing an issue. Are you basing your generation on the "raw" YAML (in spec/std/isa) or the resolved architecture YAML (in gen/resolved_arch/...)?

SSPUSH and SSPOPCHK are weird and broken at the moment, so those aren't surprising.

...skipping ahead...

The INSN_FIELD data is probably related to some of the subtype work, which is ongoing. This might be a fair bit of effort.

The list for DECLARE_INSN seems to match the list for MASK/MATCH, which is good. Solving it for one will likely solve it for the other.

This is good work. Let's keep iterating on finding and fixing issues, and gradually whittle down the list. Keep updating status here, perhaps in new comments, so we can compare new and old if needed. If you get stuck, yell for help. :-)

[jordancarlin]

The MOP instructions are all there, so we need to understand why they are appearing on the "missing" list. They use "layouts", so maybe that's causing an issue. Are you basing your generation on the "raw" YAML (in spec/std/isa) or the resolved architecture YAML (in gen/resolved_arch/...)?

I suspect this is the same as #1178