diff --git a/.vscode/launch.json b/.vscode/launch.json
index 7163deb3fa..a5aebc6bd5 100644
--- a/.vscode/launch.json
+++ b/.vscode/launch.json
@@ -6,7 +6,7 @@
       "type": "cppdbg",
       "request": "launch",
       "program": "${workspaceFolder}/gen/cpp_hart_gen/rv32_Debug/build/iss",
-      "args": ["-m", "rv32", "-c", "${workspaceFolder}/cfgs/rv32-riscv-tests.yaml", "${workspaceFolder}/ext/riscv-tests/isa/rv32ui-p-addi"],
+      "args": ["-m", "rv32", "-c", "${workspaceFolder}/cfgs/mc100-32-riscv-tests.yaml", "${workspaceFolder}/ext/riscv-tests/isa/rv32ui-p-addi"],
       "stopAtEntry": true,
       "cwd": "${workspaceFolder}",
       "environment": [],
diff --git a/backends/cpp_hart_gen/cpp/include/udb/bitfield.hpp b/backends/cpp_hart_gen/cpp/include/udb/bitfield.hpp
index 710131d554..91477ab60c 100644
--- a/backends/cpp_hart_gen/cpp/include/udb/bitfield.hpp
+++ b/backends/cpp_hart_gen/cpp/include/udb/bitfield.hpp
@@ -167,7 +167,7 @@ namespace udb {
   template <template <unsigned, bool> class BitsClass, unsigned N, bool Signed>
     requires ((N >= Size) && (BitsClass<N, Signed>::IsABits))
   BitfieldMember<ParentSize, Start, Size>::template operator BitsClass<N, Signed>() const {
-    return BitsClass<N, Signed> {(static_cast<BitsType<ParentSize>>(m_parent) >> Bits<ParentSize>(Start)) & MaximumValue};
+    return BitsClass<N, Signed> {static_cast<BitsType<ParentSize>>(m_parent) >> Bits<Size>(Start) & MaximumValue};
   }
 
   template <unsigned ParentSize, unsigned Start, unsigned Size>
@@ -185,7 +185,7 @@ namespace udb {
       &BitfieldMember<ParentSize, Start, Size>::template operator=(
           const BitfieldMember<ParentSize, Start, Size> &other) {
     m_parent = (static_cast<BitsType<ParentSize>>(m_parent) & ~Mask) |
-               ((static_cast<BitsType<Size>>(other).template widening_sll<Start>()) & Mask);
+               ((static_cast<BitsType<Size>>(other).template widening_sll<Size>()) & Mask);
     return *this;
   }
 
diff --git a/backends/cpp_hart_gen/cpp/include/udb/bits.hpp b/backends/cpp_hart_gen/cpp/include/udb/bits.hpp
index 6f6b71aebd..a1ef141b97 100644
--- a/backends/cpp_hart_gen/cpp/include/udb/bits.hpp
+++ b/backends/cpp_hart_gen/cpp/include/udb/bits.hpp
@@ -2801,14 +2801,12 @@ namespace udb {
       template <unsigned, bool> class MsbType, unsigned MsbN,
       template <unsigned, bool> class LsbType, unsigned LsbN
     >
-    constexpr _PossiblyUnknownRuntimeBits<constmax_v<MsbN, LsbN>, false> extract(const MsbType<MsbN, false>& msb, const LsbType<LsbN, false>& lsb) const {
+    constexpr _PossiblyUnknownBits<N, false> extract(const MsbType<MsbN, false>& msb, const LsbType<LsbN, false>& lsb) const {
       udb_assert(msb >= lsb, "Negative range is not allowed");
       udb_assert(lsb.get() <= width(), "Extract out of range");
 
-      return _PossiblyUnknownRuntimeBits<constmax_v<MsbN, LsbN>, false>(
-        WidthArg(msb.get() - lsb.get() + 1),
-        ValueArg(_PossiblyUnknownBits<constmax_v<MsbN, LsbN>, false>(m_val.extract(msb, lsb), m_unknown_mask.extract(msb, lsb)))
-      );
+      _Bits<N, false> mask = (_Bits<N, false>{1} << (msb - lsb)) - _Bits<N, false>{1};
+      return _PossiblyUnknownBits<N, false>{m_val.extract(msb, lsb), m_unknown_mask.extract(msb, lsb)};
     }
 
     template <unsigned Pos>
@@ -3020,8 +3018,8 @@ namespace udb {
 
     constexpr explicit _PossiblyUnknownRuntimeBits(unsigned width) : m_width(width) {}
     constexpr explicit _PossiblyUnknownRuntimeBits(const WidthArg& width) : m_width(width.width) {}
-    constexpr explicit _PossiblyUnknownRuntimeBits(const ValueArg<_PossiblyUnknownBits<MaxN, Signed>> val, const WidthArg& width)  : m_val(val.value), m_width(width.width) {}
-    constexpr explicit _PossiblyUnknownRuntimeBits(const WidthArg& width, const ValueArg<_PossiblyUnknownBits<MaxN, Signed>> val)  : m_val(val.value), m_width(width.width) {}
+    constexpr explicit _PossiblyUnknownRuntimeBits(const ValueArg<StorageType> val, const WidthArg& width)  : m_val(val.value), m_width(width.width) {}
+    constexpr explicit _PossiblyUnknownRuntimeBits(const WidthArg& width, const ValueArg<StorageType> val)  : m_val(val.value), m_width(width.width) {}
 
     // template <std::integral T>
     // constexpr _PossiblyUnknownRuntimeBits(const T &initial_value, unsigned width)
diff --git a/backends/cpp_hart_gen/tasks.rake b/backends/cpp_hart_gen/tasks.rake
index 1143c39d3d..970a675798 100644
--- a/backends/cpp_hart_gen/tasks.rake
+++ b/backends/cpp_hart_gen/tasks.rake
@@ -397,32 +397,17 @@ namespace :test do
 
   task riscv_tests: ["build_riscv_tests", "build:cpp_hart"] do
     configs_name, build_name = configs_build_name
-    rv32uiTests = ["simple", "add", "addi", "and",
-      "andi", "auipc", "beq", "bge", "bgeu", "blt",
-      "bltu", "bne", "fence_i", "jal", "jalr",
-      "lb", "lbu", "lh", "lhu", "lw", "ld_st",
-      "lui", "ma_data", "or", "ori", "sb", "sh",
-      "sw", "st_ld", "sll", "slli", "slt", "slti",
-      "sltiu", "sltu", "sra", "srai", "srl",
-      "srli", "sub", "xor", "xori"]
-
-    rv32uiTests.each do |t|
-      sh "#{CPP_HART_GEN_DST}/#{build_name}/build/iss -m rv32 -c #{$root}/cfgs/rv32-riscv-tests.yaml ext/riscv-tests/isa/rv32ui-p-#{t}"
-    end
-
-    rv32umTests = [ "div", "divu", "mul", "mulh", "mulhsu", "mulhu", "rem", "remu" ]
-    rv32umTests.each do |t|
-      sh "#{CPP_HART_GEN_DST}/#{build_name}/build/iss -m rv32 -c #{$root}/cfgs/rv32-riscv-tests.yaml ext/riscv-tests/isa/rv32um-p-#{t}"
-    end
-
-    rv32ucTests = [ "rvc" ]
-    rv32ucTests.each do |t|
-      sh "#{CPP_HART_GEN_DST}/#{build_name}/build/iss -m rv32 -c #{$root}/cfgs/rv32-riscv-tests.yaml ext/riscv-tests/isa/rv32uc-p-#{t}"
-    end
-
-    rv32siTests = ["csr", "dirty", "ma_fetch", "scall", "sbreak"]
-    rv32siTests.each do |t|
-      sh "#{CPP_HART_GEN_DST}/#{build_name}/build/iss -m rv32 -c #{$root}/cfgs/rv32-riscv-tests.yaml ext/riscv-tests/isa/rv32si-p-#{t}"
+    tests = ["simple", "add", "addi", "and",
+    "andi", "auipc", "beq", "bge", "bgeu", "blt",
+    "bltu", "bne", "fence_i", "jal", "jalr",
+     "lb", "lbu", "lh", "lhu", "lw", "ld_st",
+     "lui", "ma_data", "or", "ori", "sb", "sh",
+     "sw", "st_ld", "sll", "slli", "slt", "slti",
+     "sltiu", "sltu", "sra", "srai", "srl",
+     "srli", "sub", "xor", "xori"]
+
+     tests.each do |t|
+      sh "#{CPP_HART_GEN_DST}/#{build_name}/build/iss -m rv32 -c #{$root}/cfgs/mc100-32-riscv-tests.yaml ext/riscv-tests/isa/rv32ui-p-#{t}"
     end
   end
 end
diff --git a/backends/cpp_hart_gen/templates/enum.hxx.erb b/backends/cpp_hart_gen/templates/enum.hxx.erb
index dc95642b53..41b51067d2 100644
--- a/backends/cpp_hart_gen/templates/enum.hxx.erb
+++ b/backends/cpp_hart_gen/templates/enum.hxx.erb
@@ -56,7 +56,7 @@ namespace udb {
     }
 
     constexpr bool operator!=(const <%= enum.name %>& rhs) const {
-      return m_value != rhs.m_value;
+      return m_value == rhs.m_value;
     }
 
     constexpr bool operator<(const <%= enum.name %>& rhs) const {
diff --git a/backends/cpp_hart_gen/templates/hart_impl.hxx.erb b/backends/cpp_hart_gen/templates/hart_impl.hxx.erb
index 915e1c8e84..70a2aa64fc 100644
--- a/backends/cpp_hart_gen/templates/hart_impl.hxx.erb
+++ b/backends/cpp_hart_gen/templates/hart_impl.hxx.erb
@@ -138,20 +138,11 @@ namespace udb {
         for (unsigned b = 0; b < bb_size; b++) {
           inst = current_bb->pop();
 
-          fmt::print("PC {:x} {}\n", m_pc, inst->disassemble());
-          for (auto r : inst->srcRegs()) {
-            fmt::print("R {} {:x}\n", r.to_string(), _xreg(r.get_num()));
-          }
-
           // set the fall-through next pc
           m_next_pc = m_pc + Bits<MXLEN>{inst->enc_len()};
 
           inst->execute();
 
-          for (auto r : inst->dstRegs()) {
-            fmt::print("R= {} {:x}\n", r.to_string(), _xreg(r.get_num()));
-          }
-
           advance_pc();
           if (this->m_exit_requested) {
             this->m_exit_requested = false;  // reset the request
diff --git a/backends/generators/generator.py b/backends/generators/generator.py
index 13d29ae819..053cfab59b 100755
--- a/backends/generators/generator.py
+++ b/backends/generators/generator.py
@@ -17,105 +17,6 @@ def check_requirement(req, exts):
     return False
 
 
-def build_match_from_format(format_field):
-    """
-    Build a match string from the format field in the new schema.
-    """
-    if not format_field or "opcodes" not in format_field:
-        return None
-
-    # Determine instruction width by finding maximum bit position
-    valid_locations = []
-
-    opcodes = format_field["opcodes"]
-    # Check opcodes
-    for field_data in opcodes.values():
-        if isinstance(field_data, dict) and "location" in field_data:
-            if isinstance(field_data["location"], str):
-                try:
-                    location = field_data["location"]
-                    split_location = location.split("|")
-                    high = max(
-                        (
-                            int(location.split("-")[0])
-                            if "-" in location
-                            else int(location)
-                        )
-                        for location in split_location
-                    )
-                    valid_locations.append(high)
-                except (ValueError, IndexError):
-                    raise ValueError(
-                        f"Invalid location format: {field_data['location']}"
-                    )
-            elif isinstance(field_data["location"], int):
-                try:
-                    valid_locations.append(field_data["location"])
-                except (ValueError, IndexError):
-                    raise ValueError(
-                        f"Invalid location format: {field_data['location']}"
-                    )
-            else:
-                raise ValueError(f"Unknown location format: {field_data['location']}")
-
-    if "variables" in format_field:
-        variables = format_field["variables"]
-        # Check variables
-        for var_data in variables.values():
-            if isinstance(var_data, dict) and "location" in var_data:
-                if isinstance(var_data["location"], str):
-                    try:
-                        location = var_data["location"]
-                        if "-" in location:
-                            high = int(location.split("-")[0])
-                        else:
-                            high = int(location)
-                        valid_locations.append(high)
-                    except (ValueError, IndexError):
-                        raise ValueError(
-                            f"Invalid location format: {var_data['location']}"
-                        )
-                elif isinstance(var_data["location"], int):
-                    try:
-                        valid_locations.append(var_data["location"])
-                    except (ValueError, IndexError):
-                        raise ValueError(
-                            f"Invalid location format: {var_data['location']}"
-                        )
-                else:
-                    raise ValueError(f"Invalid location format: {var_data['location']}")
-
-    if not valid_locations:
-        raise ValueError("No valid bit locations found in format field")
-
-    max_bit = max(valid_locations)
-
-    # Set instruction width based on maximum bit position
-    width = max_bit + 1
-    match_bits = ["-"] * width
-
-    # Populate match string with opcode bits
-    for field_data in opcodes.values():
-        if isinstance(field_data, dict):
-            try:
-                location = field_data["location"]
-                if isinstance(location, str) and "-" in location:
-                    high, low = map(int, location.split("-"))
-                else:
-                    high = low = int(location)
-
-                if high < low or high >= width:
-                    logging.warning(f"Invalid bit range: {location}")
-                    continue  # Skip invalid bit ranges
-
-                binary_value = format(field_data["value"], f"0{high - low + 1}b")
-                match_bits[width - high - 1 : width - low] = binary_value
-            except (ValueError, IndexError):
-                raise ValueError(f"Error processing opcode field: {field_data}")
-
-    return "".join(match_bits)
-
-
 def parse_extension_requirements(extensions_spec):
     """
     Parse the extension requirements from the definedBy field.
@@ -276,27 +177,11 @@ def load_instructions(
 
             encoding = data.get("encoding", {})
             if not encoding:
-                # Check if this instruction uses the new schema with a 'format' field
-                format_field = data.get("format")
-                if not format_field:
-                    logging.error(
-                        f"Missing 'encoding' field in instruction {name} in {path}"
-                    )
-                    encoding_filtered += 1
-                    continue
-
-                # Try to build a match string from the format field
-                match_string = build_match_from_format(format_field)
-                if not match_string:
-                    logging.error(
-                        f"Could not build encoding from format field in instruction {name} in {path}"
-                    )
-                    encoding_filtered += 1
-                    continue
-
-                # Create a synthetic encoding compatible with existing logic
-                encoding = {"match": match_string, "variables": []}
-                logging.debug(f"Built encoding from format field for {name}")
+                logging.error(
+                    f"Missing 'encoding' field in instruction {name} in {path}"
+                )
+                encoding_filtered += 1
+                continue
 
             # Check if the instruction specifies a base architecture constraint
             base = data.get("base")
diff --git a/backends/instructions_appendix/all_instructions.golden.adoc b/backends/instructions_appendix/all_instructions.golden.adoc
index 52dcc7a163..61196f3b53 100644
--- a/backends/instructions_appendix/all_instructions.golden.adoc
+++ b/backends/instructions_appendix/all_instructions.golden.adoc
@@ -569,8 +569,6 @@ Encoding::
 Description::
 This instruction implements the rotation, SubBytes and Round Constant addition steps of the AES
 block cipher Key Schedule.
-
-
 `rnum` must be in the range `0x0..0xA`. The values `0xB..0xF` are reserved.
 
 
@@ -7268,7 +7266,7 @@ Encoding::
 ....
 
 Description::
-The xref:insts:fadd_d.adoc#udb:doc:inst:fadd_d[fadd.d] instruction is analogous to xref:insts:fadd_s.adoc#udb:doc:inst:fadd_s[fadd.s] and performs double-precision floating-point addition between
+The xref:insts:fadd_d.adoc#udb:doc:inst:fadd_d[fadd.d] instruction is analogous to xref:insts:fadd_s.adoc#udb:doc:inst:fadd_s[fadd.s] and performs double-precision floating-point addition of
 `fs1` and `fs2` and writes the final result to `fd`.
 
 
@@ -7387,7 +7385,7 @@ Encoding::
 ....
 
 Description::
-The xref:insts:fadd_s.adoc#udb:doc:inst:fadd_s[fadd.s] instruction performs single-precision floating-point addition of `xs1` and `xs2`
+The xref:insts:fadd_s.adoc#udb:doc:inst:fadd_s[fadd.s] instruction performs single-precision floating-point addition of `fs1` and `fs2`
 and writes the final result to `fd`.
 
 
@@ -10622,8 +10620,7 @@ Encoding::
 ....
 
 Description::
-The
-The xref:insts:fli_q.adoc#udb:doc:inst:fli_q[fli.q] instruction loads one of 32 quad-precision floating-point constants, encoded in the `rs1`
+The xref:insts:fli_q.adoc#udb:doc:inst:fli_q[fli.q] instruction loads one of 32 quad-precision floating-point constants, encoded in the `xs1`
 field, into floating-point register `rd`.
 xref:insts:fli_q.adoc#udb:doc:inst:fli_q[fli.q] is encoded like xref:insts:fmv_w_x.adoc#udb:doc:inst:fmv_w_x[fmv.w.x], but with _fmt_ = Q.
 
@@ -12246,7 +12243,7 @@ Included in::
 == fmv.d.x
 
 Synopsis::
-Floating-Point Move from Integer Register to Double-Precision Register
+Floating-Point Move Double-Precision from Integer Register
 
 Assembly::
 fmv.d.x fd, xs1
@@ -12365,7 +12362,7 @@ Included in::
 == fmv.x.d
 
 Synopsis::
-Floating-Point Move from Double-Precision Register to Integer Register
+Floating-Point Move Double-Precision to Integer Register
 
 Assembly::
 fmv.x.d xd, fs1
@@ -12631,7 +12628,7 @@ Encoding::
 Description::
 The xref:insts:fmvp_q_x.adoc#udb:doc:inst:fmvp_q_x[fmvp.q.x] instruction moves a double-precision number from a pair of integer registers into
 a floating-point register.
-Integer registers xs1 and xs2 supply bits 63:0 and 127:64, respectively; the result is written to
+Integer registers `xs1` and `xs2` supply bits 63:0 and 127:64, respectively; the result is written to
 floating-point register `fd`.
 xref:insts:fmvp_q_x.adoc#udb:doc:inst:fmvp_q_x[fmvp.q.x] is encoded in the OP-FP major opcode with _funct3_=0 and _funct7_=1011011.
 
diff --git a/cfgs/rv32-riscv-tests.yaml b/cfgs/mc100-32-riscv-tests.yaml
similarity index 96%
rename from cfgs/rv32-riscv-tests.yaml
rename to cfgs/mc100-32-riscv-tests.yaml
index a7eac07de2..856fb1d39b 100644
--- a/cfgs/rv32-riscv-tests.yaml
+++ b/cfgs/mc100-32-riscv-tests.yaml
@@ -3,8 +3,8 @@
 $schema: https://riscv.org/udb/schemas/config_schema-0.1.0.json
 kind: architecture configuration
 type: fully configured
-name: rv32-riscv-tests
-description: A compliant full config for rv32 riscv-tests
+name: MC100-32-riscv-tests
+description: An example MC100-32-compliant full config for riscv-tests
 implemented_extensions:
   - [Sm, "1.11.0"]
   - [I, "2.1"]
@@ -17,7 +17,6 @@ implemented_extensions:
   - [Smpmp, "1.11.0"]
   - [U, "1.0.0"]
   - [Zifencei, "2.0.0"]
-  - [Sv32, "1.11.0"]
 
 params:
   MXLEN: 32
@@ -109,7 +108,7 @@ params:
       false,
       false,
     ]
-  STVEC_MODE_DIRECT: true
+  STVEC_MODE_DIRECT: false
   STVEC_MODE_VECTORED: true
   SATP_MODE_BARE: true
   TRAP_ON_ECALL_FROM_S: true
diff --git a/spec/custom/non_isa/preface_demo.yaml b/spec/custom/non_isa/preface_demo.yaml
index e9a12ef6b2..39ce04f232 100644
--- a/spec/custom/non_isa/preface_demo.yaml
+++ b/spec/custom/non_isa/preface_demo.yaml
@@ -8,15 +8,12 @@ name: preface
 long_name: Preface (Demo)
 version: 1.0.0
 ratification_date: "2025-08-08"
-description:
-  - id: spec-preface-overview
-    normative: false
-    text: |
-      This Programmer's Reference Manual (PRM) provides comprehensive documentation for a generic RISC-V processor implementation. It is intended for system designers, integrators, verification engineers, and software developers working with RISC-V-based systems.
+description: |
+  This Programmer's Reference Manual (PRM) provides comprehensive documentation for a generic RISC-V processor implementation. It is intended for system designers, integrators, verification engineers, and software developers working with RISC-V-based systems.
 
-      The manual covers the processor architecture, instruction set, control and status registers, memory management, debug and trace features, and other essential aspects. It aims to clarify both standard RISC-V features and implementation-defined options, supporting robust and portable software development.
+  The manual covers the processor architecture, instruction set, control and status registers, memory management, debug and trace features, and other essential aspects. It aims to clarify both standard RISC-V features and implementation-defined options, supporting robust and portable software development.
 
-      This document is suitable for public distribution and does not contain proprietary or vendor-specific content. All examples and descriptions are generic and based on open RISC-V standards.
+  This document is suitable for public distribution and does not contain proprietary or vendor-specific content. All examples and descriptions are generic and based on open RISC-V standards.
 authors:
   - name: RISC-V Community
     organization:
@@ -28,85 +25,64 @@ license:
   url: https://spdx.org/licenses/CC0-1.0.html
 sections:
   - title: About This Manual
-    content:
-      - id: sec-preface-about
-        normative: false
-        text: |
-          This manual is organized to guide users through the essential features of a RISC-V processor. It begins with an overview of the architecture and programming model, followed by chapters on the instruction set, privilege levels, memory subsystem, and system integration topics. Each chapter provides references to the official RISC-V specifications and highlights implementation-defined aspects where relevant.
+    content: |
+      This manual is organized to guide users through the essential features of a RISC-V processor. It begins with an overview of the architecture and programming model, followed by chapters on the instruction set, privilege levels, memory subsystem, and system integration topics. Each chapter provides references to the official RISC-V specifications and highlights implementation-defined aspects where relevant.
 
-          The manual is designed to be accessible to both new and experienced users, with clear explanations, diagrams, and practical examples. It emphasizes portability, compliance with RISC-V standards, and best practices for system design and software development.
+      The manual is designed to be accessible to both new and experienced users, with clear explanations, diagrams, and practical examples. It emphasizes portability, compliance with RISC-V standards, and best practices for system design and software development.
   - title: Audience
-    content:
-      - id: sec-preface-audience
-        normative: false
-        text: |
-          This document is intended for:
+    content: |
+      This document is intended for:
 
-          * System architects and designers
-          * Hardware and software engineers
-          * Verification and validation teams
-          * Technical writers and educators
+      * System architects and designers
+      * Hardware and software engineers
+      * Verification and validation teams
+      * Technical writers and educators
 
-          The manual assumes a basic familiarity with computer architecture and programming concepts, but provides background information and references for further study.
-      - id: sec-preface-audience-conditional
-        normative: false
-        text: |
-          This section is only included for educational distributions.
-        when(): "distribution_type == 'educational'"
+      The manual assumes a basic familiarity with computer architecture and programming concepts, but provides background information and references for further study.
+
+      This section is only included for educational distributions.
   - title: Notation and Conventions
-    content:
-      - id: sec-preface-notation
-        normative: false
-        text: |
-          The following conventions are used throughout this manual:
+    content: |
+      The following conventions are used throughout this manual:
 
-          * Register and field names are shown in `monospace` font.
-          * Bit values are indicated as 0 (read-only zero) or 1 (read-only one).
-          * References to RISC-V specifications are provided for standard features.
-          * Implementation-defined options are clearly marked and explained.
+      * Register and field names are shown in `monospace` font.
+      * Bit values are indicated as 0 (read-only zero) or 1 (read-only one).
+      * References to RISC-V specifications are provided for standard features.
+      * Implementation-defined options are clearly marked and explained.
   - title: Document Organization
-    content:
-      - id: sec-preface-organization
-        normative: false
-        text: |
-          Chapters include:
+    content: |
+      Chapters include:
 
-          * Architecture Overview
-          * Instruction Set Architecture
-          * Privileged Architecture
-          * Interrupts and Exceptions
-          * Memory Subsystem
-          * Memory Management
-          * Reliability, Availability, and Serviceability (RAS)
-          * Floating Point Unit
-          * Debug and Trace
-          * Triggers and Watchpoints
-          * Power Management
-          * Performance Monitoring
-          * Timers and Watchdog
-          * Security Features
-          * Control and Status Registers
-          * Build and Configuration Options
-          * Acronyms and Definitions
-          * References
+      * Architecture Overview
+      * Instruction Set Architecture
+      * Privileged Architecture
+      * Interrupts and Exceptions
+      * Memory Subsystem
+      * Memory Management
+      * Reliability, Availability, and Serviceability (RAS)
+      * Floating Point Unit
+      * Debug and Trace
+      * Triggers and Watchpoints
+      * Power Management
+      * Performance Monitoring
+      * Timers and Watchdog
+      * Security Features
+      * Control and Status Registers
+      * Build and Configuration Options
+      * Acronyms and Definitions
+      * References
 
-          Each chapter is self-contained and provides links to related topics and external resources.
+      Each chapter is self-contained and provides links to related topics and external resources.
   - title: Web Resources
-    content:
-      - id: sec-preface-web
-        normative: true
-        text: |
-          For more information on RISC-V standards and open-source resources, visit:
+    content: |
+      For more information on RISC-V standards and open-source resources, visit:
 
-          * https://riscv.org
-          * https://github.com/riscv/riscv-isa-manual
-          * https://github.com/riscv/riscv-debug-spec
-          * https://github.com/riscv-software-src
+      * https://riscv.org
+      * https://github.com/riscv/riscv-isa-manual
+      * https://github.com/riscv/riscv-debug-spec
+      * https://github.com/riscv-software-src
 
-          Community forums, mailing lists, and technical documentation are available to support developers and users worldwide.
+      Community forums, mailing lists, and technical documentation are available to support developers and users worldwide.
   - title: Revision History
-    content:
-      - id: sec-preface-history
-        normative: true
-        text: |
-          Version 1.0.0 (2025-08-08): Initial public release of the demo Programmer's Reference Manual for RISC-V processors.
+    content: |
+      Version 1.0.0 (2025-08-08): Initial public release of the demo Programmer's Reference Manual for RISC-V processors.
diff --git a/spec/schemas/schema_defs.json b/spec/schemas/schema_defs.json
index 3b2ed7d73b..35c30eae11 100644
--- a/spec/schemas/schema_defs.json
+++ b/spec/schemas/schema_defs.json
@@ -102,26 +102,19 @@
         {
           "type": "array",
           "items": {
-            "$ref": "#/$defs/tagged_text"
+            "$ref": "#/$defs/conditional_text"
           }
         }
       ]
     },
-    "tagged_text": {
+    "conditional_text": {
       "type": "object",
-      "required": ["id", "text", "normative"],
+      "required": ["text"],
       "properties": {
-        "id": {
-          "type": "string",
-          "description": "Unique identifier for the statement"
-        },
         "text": {
           "type": "string",
           "description": "Asciidoctor source"
         },
-        "normative": {
-          "type": "boolean"
-        },
         "when()": {
           "type": "string",
           "description": "IDL boolean expression. When true, the text applies"
diff --git a/spec/std/isa/csr/F/fflags.yaml b/spec/std/isa/csr/F/fflags.yaml
index 66fabeb4b5..7e62a65b02 100644
--- a/spec/std/isa/csr/F/fflags.yaml
+++ b/spec/std/isa/csr/F/fflags.yaml
@@ -9,22 +9,16 @@ name: fflags
 long_name: Floating-Point Accrued Exceptions
 address: 0x001
 writable: true
-description:
-  - id: csr-fflags-purpose
-    normative: true
-    text: |
-      The accrued exception flags indicate the exception conditions that have arisen on any floating-point arithmetic
-      instruction since the field was last reset by software.
-  - id: csr-fflags-fptrap
-    normative: false
-    text: The base RISC-V ISA does not support generating a trap on the setting of a floating-point exception flag.
-  - id: csr-fflags-reasoning
-    normative: false
-    text: |
-      As allowed by the standard, we do not support traps on floating-point exceptions in the F
-      extension, but instead require explicit checks of the flags in software. We considered
-      adding branches controlled directly by the contents of the floating-point accrued
-      exception flags, but ultimately chose to omit these instructions to keep the ISA simple.
+description: |
+  The accrued exception flags indicate the exception conditions that have arisen on any floating-point arithmetic
+  instruction since the field was last reset by software.
+
+  The base RISC-V ISA does not support generating a trap on the setting of a floating-point exception flag.
+
+  As allowed by the standard, we do not support traps on floating-point exceptions in the F
+  extension, but instead require explicit checks of the flags in software. We considered
+  adding branches controlled directly by the contents of the floating-point accrued
+  exception flags, but ultimately chose to omit these instructions to keep the ISA simple.
 
 priv_mode: U
 length: 32
diff --git a/spec/std/isa/csr/F/frm.yaml b/spec/std/isa/csr/F/frm.yaml
index ce9e881779..31fa89e3b0 100644
--- a/spec/std/isa/csr/F/frm.yaml
+++ b/spec/std/isa/csr/F/frm.yaml
@@ -9,39 +9,32 @@ name: frm
 long_name: Floating-Point Dynamic Rounding Mode
 address: 0x002
 writable: true
-description:
-  - id: csr-frm-encodings
-    normative: false
-    text: |
-      Rounding modes are encoded as follows:
+description: |
+  Rounding modes are encoded as follows:
 
-      [[rm]]
-      .Rounding mode encoding.
-      [%autowidth,float="center",align="center",cols="^,^,<",options="header"]
-      !===
-      !Rounding Mode |Mnemonic |Meaning
-      !000 !RNE !Round to Nearest, ties to Even
-      !001 !RTZ !Round towards Zero
-      !010 !RDN !Round Down (towards latexmath:[$-\infty$])
-      !011 !RUP !Round Up (towards latexmath:[$+\infty$])
-      !100 !RMM !Round to Nearest, ties to Max Magnitude
-      !101 ! !_Reserved for future use._
-      !110 ! !_Reserved for future use._
-      !111 !DYN !In instruction's _rm_ field, selects dynamic rounding mode; In Rounding Mode register, _reserved_.
-      !===
-  - id: csr-frm-reserved
-    normative: false
-    text: |
-      The behavior of floating-point instructions that depend on rounding mode when
-      executed with a reserved rounding mode is _reserved_, including both static
-      reserved rounding modes (101-110) and dynamic reserved rounding modes (101-111).
-  - id: csr-frm-rmfield
-    normative: false
-    text: |
-      Some instructions, including widening conversions, have the _rm_ field but are
-      nevertheless mathematically unaffected by the rounding mode; software should set
-      their _rm_ field to RNE (000) but implementations must treat the _rm_ field as
-      usual (in particular, with regard to decoding legal vs. reserved encodings).
+  [[rm]]
+  .Rounding mode encoding.
+  [%autowidth,float="center",align="center",cols="^,^,<",options="header"]
+  !===
+  !Rounding Mode |Mnemonic |Meaning
+  !000 !RNE !Round to Nearest, ties to Even
+  !001 !RTZ !Round towards Zero
+  !010 !RDN !Round Down (towards latexmath:[$-\infty$])
+  !011 !RUP !Round Up (towards latexmath:[$+\infty$])
+  !100 !RMM !Round to Nearest, ties to Max Magnitude
+  !101 ! !_Reserved for future use._
+  !110 ! !_Reserved for future use._
+  !111 !DYN !In instruction's _rm_ field, selects dynamic rounding mode; In Rounding Mode register, _reserved_.
+  !===
+
+  The behavior of floating-point instructions that depend on rounding mode when
+  executed with a reserved rounding mode is _reserved_, including both static
+  reserved rounding modes (101-110) and dynamic reserved rounding modes (101-111).
+
+  Some instructions, including widening conversions, have the _rm_ field but are
+  nevertheless mathematically unaffected by the rounding mode; software should set
+  their _rm_ field to RNE (000) but implementations must treat the _rm_ field as
+  usual (in particular, with regard to decoding legal vs. reserved encodings).
 
 priv_mode: U
 length: 32
diff --git a/spec/std/isa/csr/Smcsrind/mireg.yaml b/spec/std/isa/csr/Smcsrind/mireg.yaml
index 1dc878a51e..a5f9f7693b 100644
--- a/spec/std/isa/csr/Smcsrind/mireg.yaml
+++ b/spec/std/isa/csr/Smcsrind/mireg.yaml
@@ -11,51 +11,36 @@ writable: true
 priv_mode: M
 length: MXLEN
 definedBy: Smcsrind
-description:
-  - id: csr-mireg-purpose
-    normative: true
-    text: |
-      The mireg machine indirect alias CSR is used to access another CSR's state
-      indirectly upon a read or write, as determined by the value of miselect.
-  - id: csr-mireg-unimplemented-miselect
-    normative: true
-    text: |
-      The behavior upon accessing mireg from M-mode, while miselect holds a value
-      that is not implemented, is UNSPECIFIED.
-  - id: csr-mireg-unimplemented-miselect-note
-    normative: false
-    text: |
-      It is expected that implementations will typically raise an illegal instruction exception for
-      such accesses, so that, for example, they can be identified as software bugs. Platform
-      specs, profile specs, and/or the Privileged ISA spec may place more restrictions on
-      behavior for such accesses.
-  - id: csr-mireg-implemented-miselect
-    normative: true
-    text: |
-      Attempts to access mireg while miselect holds a number in an allocated and implemented range
-      results in a specific behavior that, for each combination of miselect and mireg, is defined by the
-      extension to which the miselect value is allocated.
-  - id: csr-mireg-implemented-miselect-note
-    normative: false
-    text: |
-      Ordinarily, mireg will access register state, access read-only 0 state, or raise an
-      illegal instruction exception.
-  - id: csr-mireg-rv32-64bit-access
-    normative: false
-    text: |
-      For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is
-      recommended that the lower 32 bits of the register are accessed through mireg,
-      while the upper 32 bits are accessed through mireg4.
+description: |
+  The mireg machine indirect alias CSR is used to access another CSR's state
+  indirectly upon a read or write, as determined by the value of miselect.
+
+  The behavior upon accessing mireg from M-mode, while miselect holds a value
+  that is not implemented, is UNSPECIFIED.
+
+  It is expected that implementations will typically raise an illegal instruction exception for
+  such accesses, so that, for example, they can be identified as software bugs. Platform
+  specs, profile specs, and/or the Privileged ISA spec may place more restrictions on
+  behavior for such accesses.
+
+  Attempts to access mireg while miselect holds a number in an allocated and implemented range
+  results in a specific behavior that, for each combination of miselect and mireg, is defined by the
+  extension to which the miselect value is allocated.
+
+  Ordinarily, mireg will access register state, access read-only 0 state, or raise an
+  illegal instruction exception.
+
+  For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is
+  recommended that the lower 32 bits of the register are accessed through mireg,
+  while the upper 32 bits are accessed through mireg4.
 fields:
   VALUE:
     long_name: Indirectly Selected Register Value
     location_rv32: 31-0
     location_rv64: 63-0
     type: RW
-    description:
-      - id: csr-mireg-value-purpose
-        normative: true
-        text: Register state of the CSR selected by the current `miselect` value
+    description: |
+      Register state of the CSR selected by the current `miselect` value
     reset_value: UNDEFINED_LEGAL
     sw_write(csr_value): |
       Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 1);
diff --git a/spec/std/isa/csr/Smcsrind/mireg2.yaml b/spec/std/isa/csr/Smcsrind/mireg2.yaml
index e88f834c13..c6d27cbaf6 100644
--- a/spec/std/isa/csr/Smcsrind/mireg2.yaml
+++ b/spec/std/isa/csr/Smcsrind/mireg2.yaml
@@ -11,46 +11,28 @@ writable: true
 priv_mode: M
 length: MXLEN
 definedBy: Smcsrind
-description:
-  - id: csr-mireg2-purpose
-    normative: true
-    text: |
-      The `mireg2` machine indirect alias CSR is used to access register state indirectly
-      upon a read or write, as determined by the value of `miselect`.
+description: |
+  The `mireg2` machine indirect alias CSR is used to access register state indirectly
+  upon a read or write, as determined by the value of `miselect`.
 
-  - id: csr-mireg2-unimplemented-miselect
-    normative: true
-    text: |
-      The behavior upon accessing `mireg2` from M-mode, while `miselect` holds a value
-      that is not implemented, is UNSPECIFIED.
+  The behavior upon accessing `mireg2` from M-mode, while `miselect` holds a value
+  that is not implemented, is UNSPECIFIED.
 
-  - id: csr-mireg2-unimplemented-miselect-typical
-    normative: false
-    text: |
-      It is expected that implementations will typically raise an illegal instruction exception for
-      such accesses, so that, for example, they can be identified as software bugs. Platform
-      specs, profile specs, and/or the Privileged ISA spec may place more restrictions on
-      behavior for such accesses.
+  It is expected that implementations will typically raise an illegal instruction exception for
+  such accesses, so that, for example, they can be identified as software bugs. Platform
+  specs, profile specs, and/or the Privileged ISA spec may place more restrictions on
+  behavior for such accesses.
 
-  - id: csr-mireg2-implemented-miselect
-    normative: true
-    text: |
-      Attempts to access `mireg2` while `miselect` holds a number in an allocated and implemented
-      range results in a specific behavior that, for each combination of `miselect` and `mireg2`, is
-      defined by the extension to which the `miselect` value is allocated.
+  Attempts to access `mireg2` while `miselect` holds a number in an allocated and implemented
+  range results in a specific behavior that, for each combination of `miselect` and `mireg2`, is
+  defined by the extension to which the `miselect` value is allocated.
 
-  - id: csr-mireg2-behavior-typical
-    normative: false
-    text: |
-      Ordinarily, `mireg2` will access register state, access read-only 0 state, or raise an
-      illegal instruction exception.
+  Ordinarily, `mireg2` will access register state, access read-only 0 state, or raise an
+  illegal instruction exception.
 
-  - id: csr-mireg2-rv32-64bit-access
-    normative: false
-    text: |
-      For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is
-      recommended that the lower 32 bits of the register are accessed through `mireg2`,
-      while the upper 32 bits are accessed through `mireg5`.
+  For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is
+  recommended that the lower 32 bits of the register are accessed through `mireg2`,
+  while the upper 32 bits are accessed through `mireg5`.
 
 fields:
   VALUE:
@@ -58,10 +40,8 @@ fields:
     location_rv32: 31-0
     location_rv64: 63-0
     type: RW
-    description:
-      - id: csr-mireg2-value-purpose
-        normative: true
-        text: Register state of the CSR selected by the current `miselect` value
+    description: |
+      Register state of the CSR selected by the current `miselect` value
     reset_value: UNDEFINED_LEGAL
     sw_write(csr_value): |
       Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 2);
diff --git a/spec/std/isa/csr/Smcsrind/mireg3.yaml b/spec/std/isa/csr/Smcsrind/mireg3.yaml
index a3282664dc..750605dc98 100644
--- a/spec/std/isa/csr/Smcsrind/mireg3.yaml
+++ b/spec/std/isa/csr/Smcsrind/mireg3.yaml
@@ -11,46 +11,28 @@ writable: true
 priv_mode: M
 length: MXLEN
 definedBy: Smcsrind
-description:
-  - id: csr-mireg3-purpose
-    normative: true
-    text: |
-      The `mireg3` machine indirect alias CSR is used to access register state indirectly
-      upon a read or write, as determined by the value of `miselect`.
+description: |
+  The `mireg3` machine indirect alias CSR is used to access register state indirectly
+  upon a read or write, as determined by the value of `miselect`.
 
-  - id: csr-mireg3-unimplemented-miselect
-    normative: true
-    text: |
-      The behavior upon accessing `mireg3` from M-mode, while `miselect` holds a value
-      that is not implemented, is UNSPECIFIED.
+  The behavior upon accessing `mireg3` from M-mode, while `miselect` holds a value
+  that is not implemented, is UNSPECIFIED.
 
-  - id: csr-mireg3-unimplemented-miselect-note
-    normative: false
-    text: |
-      It is expected that implementations will typically raise an illegal instruction exception for
-      such accesses, so that, for example, they can be identified as software bugs. Platform
-      specs, profile specs, and/or the Privileged ISA spec may place more restrictions on
-      behavior for such accesses.
+  It is expected that implementations will typically raise an illegal instruction exception for
+  such accesses, so that, for example, they can be identified as software bugs. Platform
+  specs, profile specs, and/or the Privileged ISA spec may place more restrictions on
+  behavior for such accesses.
 
-  - id: csr-mireg3-implemented-miselect
-    normative: true
-    text: |
-      Attempts to access `mireg3` while `miselect` holds a number in an allocated and implemented
-      range results in a specific behavior that, for each combination of `miselect` and `mireg3`, is
-      defined by the extension to which the `miselect` value is allocated.
+  Attempts to access `mireg3` while `miselect` holds a number in an allocated and implemented
+  range results in a specific behavior that, for each combination of `miselect` and `mireg3`, is
+  defined by the extension to which the `miselect` value is allocated.
 
-  - id: csr-mireg3-implemented-miselect-note
-    normative: false
-    text: |
-      Ordinarily, `mireg3` will access register state, access read-only 0 state, or raise an
-      illegal instruction exception.
+  Ordinarily, `mireg3` will access register state, access read-only 0 state, or raise an
+  illegal instruction exception.
 
-  - id: csr-mireg3-rv32-64bit-access
-    normative: false
-    text: |
-      For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is
-      recommended that the lower 32 bits of the register are accessed through `mireg3`,
-      while the upper 32 bits are accessed through `mireg6`.
+  For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is
+  recommended that the lower 32 bits of the register are accessed through `mireg3`,
+  while the upper 32 bits are accessed through `mireg6`.
 
 fields:
   VALUE:
@@ -58,10 +40,8 @@ fields:
     location_rv32: 31-0
     location_rv64: 63-0
     type: RW
-    description:
-      - id: csr-mireg3-value-purpose
-        normative: true
-        text: Register state of the CSR selected by the current `miselect` value
+    description: |
+      Register state of the CSR selected by the current `miselect` value
     reset_value: UNDEFINED_LEGAL
     sw_write(csr_value): |
       Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 3);
diff --git a/spec/std/isa/csr/Smcsrind/mireg4.yaml b/spec/std/isa/csr/Smcsrind/mireg4.yaml
index 9fc214b1cd..b1d47b8f79 100644
--- a/spec/std/isa/csr/Smcsrind/mireg4.yaml
+++ b/spec/std/isa/csr/Smcsrind/mireg4.yaml
@@ -11,46 +11,28 @@ writable: true
 priv_mode: M
 length: MXLEN
 definedBy: Smcsrind
-description:
-  - id: csr-mireg4-purpose
-    normative: true
-    text: |
-      The `mireg4` machine indirect alias CSR is used to access register state indirectly
-      upon a read or write, as determined by the value of `miselect`.
+description: |
+  The `mireg4` machine indirect alias CSR is used to access register state indirectly
+  upon a read or write, as determined by the value of `miselect`.
 
-  - id: csr-mireg4-unimplemented-miselect
-    normative: true
-    text: |
-      The behavior upon accessing `mireg4` from M-mode, while `miselect` holds a value
-      that is not implemented, is UNSPECIFIED.
+  The behavior upon accessing `mireg4` from M-mode, while `miselect` holds a value
+  that is not implemented, is UNSPECIFIED.
 
-  - id: csr-mireg4-unimplemented-miselect-note
-    normative: false
-    text: |
-      It is expected that implementations will typically raise an illegal instruction exception for
-      such accesses, so that, for example, they can be identified as software bugs. Platform
-      specs, profile specs, and/or the Privileged ISA spec may place more restrictions on
-      behavior for such accesses.
+  It is expected that implementations will typically raise an illegal instruction exception for
+  such accesses, so that, for example, they can be identified as software bugs. Platform
+  specs, profile specs, and/or the Privileged ISA spec may place more restrictions on
+  behavior for such accesses.
 
-  - id: csr-mireg4-implemented-miselect
-    normative: true
-    text: |
-      Attempts to access `mireg4` while `miselect` holds a number in an allocated and implemented
-      range results in a specific behavior that, for each combination of `miselect` and `mireg4`, is
-      defined by the extension to which the `miselect` value is allocated.
+  Attempts to access `mireg4` while `miselect` holds a number in an allocated and implemented
+  range results in a specific behavior that, for each combination of `miselect` and `mireg4`, is
+  defined by the extension to which the `miselect` value is allocated.
 
-  - id: csr-mireg4-implemented-miselect-note
-    normative: false
-    text: |
-      Ordinarily, `mireg4` will access register state, access read-only 0 state, or raise an
-      illegal instruction exception.
+  Ordinarily, `mireg4` will access register state, access read-only 0 state, or raise an
+  illegal instruction exception.
 
-  - id: csr-mireg4-rv32-64bit-access
-    normative: false
-    text: |
-      For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is
-      recommended that the upper 32 bits of the register are accessed through `mireg4`,
-      while the lower 32 bits are accessed through `mireg`, `mireg2`, or `mireg3`.
+  For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is
+  recommended that the upper 32 bits of the register are accessed through `mireg4`,
+  while the lower 32 bits are accessed through `mireg`, `mireg2`, or `mireg3`.
 
 fields:
   VALUE:
@@ -58,10 +40,8 @@ fields:
     location_rv32: 31-0
     location_rv64: 63-0
     type: RW
-    description:
-      - id: csr-mireg4-value-purpose
-        normative: true
-        text: Register state of the CSR selected by the current `miselect` value
+    description: |
+      Register state of the CSR selected by the current `miselect` value
     reset_value: UNDEFINED_LEGAL
     sw_write(csr_value): |
       Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 4);
diff --git a/spec/std/isa/csr/Smcsrind/mireg5.yaml b/spec/std/isa/csr/Smcsrind/mireg5.yaml
index b45ee56bdd..b926387402 100644
--- a/spec/std/isa/csr/Smcsrind/mireg5.yaml
+++ b/spec/std/isa/csr/Smcsrind/mireg5.yaml
@@ -11,46 +11,28 @@ writable: true
 priv_mode: M
 length: MXLEN
 definedBy: Smcsrind
-description:
-  - id: csr-mireg5-purpose
-    normative: true
-    text: |
-      The `mireg5` machine indirect alias CSR is used to access register state indirectly
-      upon a read or write, as determined by the value of `miselect`.
+description: |
+  The `mireg5` machine indirect alias CSR is used to access register state indirectly
+  upon a read or write, as determined by the value of `miselect`.
 
-  - id: csr-mireg5-unimplemented-miselect
-    normative: true
-    text: |
-      The behavior upon accessing `mireg5` from M-mode, while `miselect` holds a value
-      that is not implemented, is UNSPECIFIED.
+  The behavior upon accessing `mireg5` from M-mode, while `miselect` holds a value
+  that is not implemented, is UNSPECIFIED.
 
-  - id: csr-mireg5-unimplemented-miselect-note
-    normative: false
-    text: |
-      It is expected that implementations will typically raise an illegal instruction exception for
-      such accesses, so that, for example, they can be identified as software bugs. Platform
-      specs, profile specs, and/or the Privileged ISA spec may place more restrictions on
-      behavior for such accesses.
+  It is expected that implementations will typically raise an illegal instruction exception for
+  such accesses, so that, for example, they can be identified as software bugs. Platform
+  specs, profile specs, and/or the Privileged ISA spec may place more restrictions on
+  behavior for such accesses.
 
-  - id: csr-mireg5-implemented-miselect
-    normative: true
-    text: |
-      Attempts to access `mireg5` while `miselect` holds a number in an allocated and implemented
-      range results in a specific behavior that, for each combination of `miselect` and `mireg5`, is
-      defined by the extension to which the `miselect` value is allocated.
+  Attempts to access `mireg5` while `miselect` holds a number in an allocated and implemented
+  range results in a specific behavior that, for each combination of `miselect` and `mireg5`, is
+  defined by the extension to which the `miselect` value is allocated.
 
-  - id: csr-mireg5-implemented-miselect-note
-    normative: false
-    text: |
-      Ordinarily, `mireg5` will access register state, access read-only 0 state, or raise an
-      illegal instruction exception.
+  Ordinarily, `mireg5` will access register state, access read-only 0 state, or raise an
+  illegal instruction exception.
 
-  - id: csr-mireg5-rv32-64bit-access
-    normative: false
-    text: |
-      For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is
-      recommended that the upper 32 bits of the register are accessed through `mireg5`,
-      while the lower 32 bits are accessed through `mireg2`.
+  For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is
+  recommended that the upper 32 bits of the register are accessed through `mireg5`,
+  while the lower 32 bits are accessed through `mireg2`.
 
 fields:
   VALUE:
@@ -58,10 +40,8 @@ fields:
     location_rv32: 31-0
     location_rv64: 63-0
     type: RW
-    description:
-      - id: csr-mireg5-value-purpose
-        normative: true
-        text: Register state of the CSR selected by the current `miselect` value
+    description: |
+      Register state of the CSR selected by the current `miselect` value
     reset_value: UNDEFINED_LEGAL
     sw_write(csr_value): |
       Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 5);
diff --git a/spec/std/isa/csr/Smcsrind/mireg6.yaml b/spec/std/isa/csr/Smcsrind/mireg6.yaml
index b983675c8a..8211ec3081 100644
--- a/spec/std/isa/csr/Smcsrind/mireg6.yaml
+++ b/spec/std/isa/csr/Smcsrind/mireg6.yaml
@@ -11,46 +11,28 @@ writable: true
 priv_mode: M
 length: MXLEN
 definedBy: Smcsrind
-description:
-  - id: csr-mireg6-purpose
-    normative: true
-    text: |
-      The `mireg6` machine indirect alias CSR is used to access register state indirectly
-      upon a read or write, as determined by the value of `miselect`.
+description: |
+  The `mireg6` machine indirect alias CSR is used to access register state indirectly
+  upon a read or write, as determined by the value of `miselect`.
 
-  - id: csr-mireg6-unimplemented-miselect
-    normative: true
-    text: |
-      The behavior upon accessing `mireg6` from M-mode, while `miselect` holds a value
-      that is not implemented, is UNSPECIFIED.
+  The behavior upon accessing `mireg6` from M-mode, while `miselect` holds a value
+  that is not implemented, is UNSPECIFIED.
 
-  - id: csr-mireg6-unimplemented-miselect-note
-    normative: false
-    text: |
-      It is expected that implementations will typically raise an illegal instruction exception for
-      such accesses, so that, for example, they can be identified as software bugs. Platform
-      specs, profile specs, and/or the Privileged ISA spec may place more restrictions on
-      behavior for such accesses.
+  It is expected that implementations will typically raise an illegal instruction exception for
+  such accesses, so that, for example, they can be identified as software bugs. Platform
+  specs, profile specs, and/or the Privileged ISA spec may place more restrictions on
+  behavior for such accesses.
 
-  - id: csr-mireg6-implemented-miselect
-    normative: true
-    text: |
-      Attempts to access `mireg6` while `miselect` holds a number in an allocated and implemented
-      range results in a specific behavior that, for each combination of `miselect` and `mireg6`, is
-      defined by the extension to which the `miselect` value is allocated.
+  Attempts to access `mireg6` while `miselect` holds a number in an allocated and implemented
+  range results in a specific behavior that, for each combination of `miselect` and `mireg6`, is
+  defined by the extension to which the `miselect` value is allocated.
 
-  - id: csr-mireg6-implemented-miselect-note
-    normative: false
-    text: |
-      Ordinarily, `mireg6` will access register state, access read-only 0 state, or raise an
-      illegal instruction exception.
+  Ordinarily, `mireg6` will access register state, access read-only 0 state, or raise an
+  illegal instruction exception.
 
-  - id: csr-mireg6-rv32-64bit-access
-    normative: false
-    text: |
-      For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is
-      recommended that the upper 32 bits of the register are accessed through `mireg6`,
-      while the lower 32 bits are accessed through `mireg3`.
+  For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is
+  recommended that the upper 32 bits of the register are accessed through `mireg6`,
+  while the lower 32 bits are accessed through `mireg3`.
 
 fields:
   VALUE:
@@ -58,10 +40,8 @@ fields:
     location_rv32: 31-0
     location_rv64: 63-0
     type: RW
-    description:
-      - id: csr-mireg6-value-purpose
-        normative: true
-        text: Register state of the CSR selected by the current `miselect` value
+    description: |
+      Register state of the CSR selected by the current `miselect` value
     reset_value: UNDEFINED_LEGAL
     sw_write(csr_value): |
       Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 6);
diff --git a/spec/std/isa/csr/Smcsrind/miselect.yaml b/spec/std/isa/csr/Smcsrind/miselect.yaml
index 93eaccc64b..23cfb9b3f2 100644
--- a/spec/std/isa/csr/Smcsrind/miselect.yaml
+++ b/spec/std/isa/csr/Smcsrind/miselect.yaml
@@ -11,42 +11,27 @@ writable: true
 priv_mode: M
 length: MXLEN
 definedBy: Smcsrind
-description:
-  - id: csr-miselect-purpose
-    normative: true
-    text: |
-      The CSRs listed in the table above provide a window for accessing register state indirectly.
-      The value of `miselect` determines which register is accessed upon read or write of each of
-      the machine indirect alias CSRs (`mireg*`). `miselect` value ranges are allocated to dependent
-      extensions, which specify the register state accessible via each `miregi` register, for each
-      `miselect` value. `miselect` is a WARL register.
+description: |
+  The CSRs listed in the table above provide a window for accessing register state indirectly.
+  The value of `miselect` determines which register is accessed upon read or write of each of
+  the machine indirect alias CSRs (`mireg*`). `miselect` value ranges are allocated to dependent
+  extensions, which specify the register state accessible via each `miregi` register, for each
+  `miselect` value. `miselect` is a WARL register.
 
-  - id: csr-miselect-implemented-bits
-    normative: true
-    text: |
-      The `miselect` register implements at least enough bits to support all implemented `miselect`
-      values (corresponding to the implemented extensions that utilize `miselect`/`mireg*` to
-      indirectly access register state). The `miselect` register may be read-only zero if there are
-      no extensions implemented that utilize it.
+  The `miselect` register implements at least enough bits to support all implemented `miselect`
+  values (corresponding to the implemented extensions that utilize `miselect`/`mireg*` to
+  indirectly access register state). The `miselect` register may be read-only zero if there are
+  no extensions implemented that utilize it.
 
-  - id: csr-miselect-custom-standard-bit
-    normative: true
-    text: |
-      Values of `miselect` with the most-significant bit set (bit XLEN - 1 = 1) are designated only for
-      custom use, presumably for accessing custom registers through the alias CSRs. Values of
-      `miselect` with the most-significant bit clear are designated only for standard use and are
-      reserved until allocated to a standard architecture extension.
+  Values of `miselect` with the most-significant bit set (bit XLEN - 1 = 1) are designated only for
+  custom use, presumably for accessing custom registers through the alias CSRs. Values of
+  `miselect` with the most-significant bit clear are designated only for standard use and are
+  reserved until allocated to a standard architecture extension.
 
-  - id: csr-miselect-msb-stability
-    normative: true
-    text: |
-      If XLEN is changed, the most-significant bit of `miselect` moves to the new position,
-      retaining its value from before.
+  If XLEN is changed, the most-significant bit of `miselect` moves to the new position,
+  retaining its value from before.
 
-  - id: csr-miselect-no-custom-support
-    normative: false
-    text: |
-      An implementation is not required to support any custom values for `miselect`.
+  An implementation is not required to support any custom values for `miselect`.
 
 fields:
   VALUE:
@@ -54,9 +39,7 @@ fields:
     location_rv32: 31-0
     location_rv64: 63-0
     type: RW
-    description:
-      - id: csr-miselect-value-purpose
-        normative: true
-        text: Selects which indirect register is accessed via `mireg*`.
+    description: |
+      Selects which indirect register is accessed via `mireg*`.
     reset_value: UNDEFINED_LEGAL
 sw_read(): |
diff --git a/spec/std/isa/csr/Smcsrind/sireg.yaml b/spec/std/isa/csr/Smcsrind/sireg.yaml
index 91e57259d5..06216636c7 100644
--- a/spec/std/isa/csr/Smcsrind/sireg.yaml
+++ b/spec/std/isa/csr/Smcsrind/sireg.yaml
@@ -11,46 +11,28 @@ writable: true
 priv_mode: S
 length: SXLEN
 definedBy: Sscsrind
-description:
-  - id: csr-sireg-behavior-implemented
-    normative: true
-    text: |
-      Access to `sireg` from M-mode or S-mode while `siselect` holds a number in a
-      standard-defined and implemented range results in specific behavior that, for each combination of
-      `siselect` and `sireg`, is defined by the extension to which the `siselect` value is allocated.
+description: |
+  Access to `sireg` from M-mode or S-mode while `siselect` holds a number in a
+  standard-defined and implemented range results in specific behavior that, for each combination of
+  `siselect` and `sireg`, is defined by the extension to which the `siselect` value is allocated.
 
-  - id: csr-sireg-typical-behavior-note
-    normative: false
-    text: |
-      Ordinarily, `sireg` will access register state, access read-only 0 state, or, unless
-      executing in a virtual machine (covered in the next section), raise an illegal instruction
-      exception.
+  Ordinarily, `sireg` will access register state, access read-only 0 state, or, unless
+  executing in a virtual machine (covered in the next section), raise an illegal instruction
+  exception.
 
-  - id: csr-sireg-xlens
-    normative: true
-    text: |
-      Note that the widths of `siselect` and `sireg` are always the current XLEN rather than SXLEN. Hence,
-      for example, if MXLEN = 64 and SXLEN = 32, then this register is 64 bits when the current
-      privilege mode is M (running RV64 code) but 32 bits when the privilege mode is S (RV32 code).
+  Note that the widths of `siselect` and `sireg` are always the current XLEN rather than SXLEN. Hence,
+  for example, if MXLEN = 64 and SXLEN = 32, then this register is 64 bits when the current
+  privilege mode is M (running RV64 code) but 32 bits when the privilege mode is S (RV32 code).
 
-  - id: csr-sireg-unimplemented
-    normative: true
-    text: |
-      The behavior upon accessing `sireg` from M-mode or S-mode, while `siselect` holds a value that is
-      not implemented at supervisor level, is UNSPECIFIED.
+  The behavior upon accessing `sireg` from M-mode or S-mode, while `siselect` holds a value that is
+  not implemented at supervisor level, is UNSPECIFIED.
 
-  - id: csr-sireg-unimplemented-recommendation
-    normative: false
-    text: |
-      It is recommended that implementations raise an illegal instruction exception for such
-      accesses, to facilitate possible emulation (by M-mode) of these accesses.
+  It is recommended that implementations raise an illegal instruction exception for such
+  accesses, to facilitate possible emulation (by M-mode) of these accesses.
 
-  - id: csr-sireg-extension-disabled
-    normative: false
-    text: |
-      An extension is considered not to be implemented at supervisor level if machine level has
-      disabled the extension for S-mode, such as by the settings of certain fields in CSR
-      `menvcfg`, for example.
+  An extension is considered not to be implemented at supervisor level if machine level has
+  disabled the extension for S-mode, such as by the settings of certain fields in CSR
+  `menvcfg`, for example.
 
 fields:
   VALUE:
@@ -58,10 +40,8 @@ fields:
     location_rv32: 31-0
     location_rv64: 63-0
     type: RW
-    description:
-      - id: csr-sireg-value-desc
-        normative: true
-        text: The data read from or written to the register selected by the current `siselect` value.
+    description: |
+      The data read from or written to the register selected by the current `siselect` value.
     reset_value: UNDEFINED_LEGAL
     sw_write(csr_value): |
       Csr handle = indirect_csr_lookup(CSR[siselect].VALUE, 1);
diff --git a/spec/std/isa/csr/Smcsrind/sireg2.yaml b/spec/std/isa/csr/Smcsrind/sireg2.yaml
index 9f36c46d4b..f02928d64f 100644
--- a/spec/std/isa/csr/Smcsrind/sireg2.yaml
+++ b/spec/std/isa/csr/Smcsrind/sireg2.yaml
@@ -11,46 +11,28 @@ writable: true
 priv_mode: S
 length: SXLEN
 definedBy: Sscsrind
-description:
-  - id: csr-sireg2-behavior-implemented
-    normative: true
-    text: |
-      Access to `sireg2` from M-mode or S-mode while `siselect` holds a number in a
-      standard-defined and implemented range results in specific behavior that, for each combination of
-      `siselect` and `sireg2`, is defined by the extension to which the `siselect` value is allocated.
+description: |
+  Access to `sireg2` from M-mode or S-mode while `siselect` holds a number in a
+  standard-defined and implemented range results in specific behavior that, for each combination of
+  `siselect` and `sireg2`, is defined by the extension to which the `siselect` value is allocated.
 
-  - id: csr-sireg2-typical-behavior-note
-    normative: false
-    text: |
-      Ordinarily, `sireg2` will access register state, access read-only 0 state, or, unless
-      executing in a virtual machine (covered in the next section), raise an illegal instruction
-      exception.
+  Ordinarily, `sireg2` will access register state, access read-only 0 state, or, unless
+  executing in a virtual machine (covered in the next section), raise an illegal instruction
+  exception.
 
-  - id: csr-sireg2-xlens
-    normative: true
-    text: |
-      Note that the widths of `siselect` and `sireg2` are always the current XLEN rather than SXLEN. Hence,
-      for example, if MXLEN = 64 and SXLEN = 32, then this register is 64 bits when the current
-      privilege mode is M (running RV64 code) but 32 bits when the privilege mode is S (RV32 code).
+  Note that the widths of `siselect` and `sireg2` are always the current XLEN rather than SXLEN. Hence,
+  for example, if MXLEN = 64 and SXLEN = 32, then this register is 64 bits when the current
+  privilege mode is M (running RV64 code) but 32 bits when the privilege mode is S (RV32 code).
 
-  - id: csr-sireg2-unimplemented
-    normative: true
-    text: |
-      The behavior upon accessing `sireg2` from M-mode or S-mode, while `siselect` holds a value that is
-      not implemented at supervisor level, is UNSPECIFIED.
+  The behavior upon accessing `sireg2` from M-mode or S-mode, while `siselect` holds a value that is
+  not implemented at supervisor level, is UNSPECIFIED.
 
-  - id: csr-sireg2-unimplemented-recommendation
-    normative: false
-    text: |
-      It is recommended that implementations raise an illegal instruction exception for such
-      accesses, to facilitate possible emulation (by M-mode) of these accesses.
+  It is recommended that implementations raise an illegal instruction exception for such
+  accesses, to facilitate possible emulation (by M-mode) of these accesses.
 
-  - id: csr-sireg2-extension-disabled
-    normative: false
-    text: |
-      An extension is considered not to be implemented at supervisor level if machine level has
-      disabled the extension for S-mode, such as by the settings of certain fields in CSR
-      `menvcfg`, for example.
+  An extension is considered not to be implemented at supervisor level if machine level has
+  disabled the extension for S-mode, such as by the settings of certain fields in CSR
+  `menvcfg`, for example.
 
 fields:
   VALUE:
@@ -58,10 +40,8 @@ fields:
     location_rv32: 31-0
     location_rv64: 63-0
     type: RW
-    description:
-      - id: csr-sireg2-value-desc
-        normative: true
-        text: The data read from or written to the register selected by the current `siselect` value.
+    description: |
+      The data read from or written to the register selected by the current `siselect` value.
     reset_value: UNDEFINED_LEGAL
     sw_write(csr_value): |
       Csr handle = indirect_csr_lookup(CSR[siselect].VALUE, 2);
diff --git a/spec/std/isa/csr/Smcsrind/sireg3.yaml b/spec/std/isa/csr/Smcsrind/sireg3.yaml
index 80260854a8..607881c8a8 100644
--- a/spec/std/isa/csr/Smcsrind/sireg3.yaml
+++ b/spec/std/isa/csr/Smcsrind/sireg3.yaml
@@ -11,46 +11,28 @@ writable: true
 priv_mode: S
 length: SXLEN
 definedBy: Sscsrind
-description:
-  - id: csr-sireg3-behavior-implemented
-    normative: true
-    text: |
-      Access to `sireg3` from M-mode or S-mode while `siselect` holds a number in a
-      standard-defined and implemented range results in specific behavior that, for each combination of
-      `siselect` and `sireg3`, is defined by the extension to which the `siselect` value is allocated.
+description: |
+  Access to `sireg3` from M-mode or S-mode while `siselect` holds a number in a
+  standard-defined and implemented range results in specific behavior that, for each combination of
+  `siselect` and `sireg3`, is defined by the extension to which the `siselect` value is allocated.
 
-  - id: csr-sireg3-typical-behavior-note
-    normative: false
-    text: |
-      Ordinarily, `sireg3` will access register state, access read-only 0 state, or, unless
-      executing in a virtual machine (covered in the next section), raise an illegal instruction
-      exception.
+  Ordinarily, `sireg3` will access register state, access read-only 0 state, or, unless
+  executing in a virtual machine (covered in the next section), raise an illegal instruction
+  exception.
 
-  - id: csr-sireg3-xlens
-    normative: true
-    text: |
-      Note that the widths of `siselect` and `sireg3` are always the current XLEN rather than SXLEN. Hence,
-      for example, if MXLEN = 64 and SXLEN = 32, then this register is 64 bits when the current
-      privilege mode is M (running RV64 code) but 32 bits when the privilege mode is S (RV32 code).
+  Note that the widths of `siselect` and `sireg3` are always the current XLEN rather than SXLEN. Hence,
+  for example, if MXLEN = 64 and SXLEN = 32, then this register is 64 bits when the current
+  privilege mode is M (running RV64 code) but 32 bits when the privilege mode is S (RV32 code).
 
-  - id: csr-sireg3-unimplemented
-    normative: true
-    text: |
-      The behavior upon accessing `sireg3` from M-mode or S-mode, while `siselect` holds a value that is
-      not implemented at supervisor level, is UNSPECIFIED.
+  The behavior upon accessing `sireg3` from M-mode or S-mode, while `siselect` holds a value that is
+  not implemented at supervisor level, is UNSPECIFIED.
 
-  - id: csr-sireg3-unimplemented-recommendation
-    normative: false
-    text: |
-      It is recommended that implementations raise an illegal instruction exception for such
-      accesses, to facilitate possible emulation (by M-mode) of these accesses.
+  It is recommended that implementations raise an illegal instruction exception for such
+  accesses, to facilitate possible emulation (by M-mode) of these accesses.
 
-  - id: csr-sireg3-extension-disabled
-    normative: false
-    text: |
-      An extension is considered not to be implemented at supervisor level if machine level has
-      disabled the extension for S-mode, such as by the settings of certain fields in CSR
-      `menvcfg`, for example.
+  An extension is considered not to be implemented at supervisor level if machine level has
+  disabled the extension for S-mode, such as by the settings of certain fields in CSR
+  `menvcfg`, for example.
 
 fields:
   VALUE:
@@ -58,10 +40,8 @@ fields:
     location_rv32: 31-0
     location_rv64: 63-0
     type: RW
-    description:
-      - id: csr-sireg3-value-desc
-        normative: true
-        text: The data read from or written to the register selected by the current `siselect` value.
+    description: |
+      The data read from or written to the register selected by the current `siselect` value.
     reset_value: UNDEFINED_LEGAL
     sw_write(csr_value): |
       Csr handle = indirect_csr_lookup(CSR[siselect].VALUE, 3);
diff --git a/spec/std/isa/csr/Smcsrind/sireg4.yaml b/spec/std/isa/csr/Smcsrind/sireg4.yaml
index ec6de98888..236ae039cf 100644
--- a/spec/std/isa/csr/Smcsrind/sireg4.yaml
+++ b/spec/std/isa/csr/Smcsrind/sireg4.yaml
@@ -11,46 +11,28 @@ writable: true
 priv_mode: S
 length: SXLEN
 definedBy: Sscsrind
-description:
-  - id: csr-sireg4-behavior-implemented
-    normative: true
-    text: |
-      Access to `sireg4` from M-mode or S-mode while `siselect` holds a number in a
-      standard-defined and implemented range results in specific behavior that, for each combination of
-      `siselect` and `sireg4`, is defined by the extension to which the `siselect` value is allocated.
+description: |
+  Access to `sireg4` from M-mode or S-mode while `siselect` holds a number in a
+  standard-defined and implemented range results in specific behavior that, for each combination of
+  `siselect` and `sireg4`, is defined by the extension to which the `siselect` value is allocated.
 
-  - id: csr-sireg4-typical-behavior-note
-    normative: false
-    text: |
-      Ordinarily, `sireg4` will access register state, access read-only 0 state, or, unless
-      executing in a virtual machine (covered in the next section), raise an illegal instruction
-      exception.
+  Ordinarily, `sireg4` will access register state, access read-only 0 state, or, unless
+  executing in a virtual machine (covered in the next section), raise an illegal instruction
+  exception.
 
-  - id: csr-sireg4-xlens
-    normative: true
-    text: |
-      Note that the widths of `siselect` and `sireg4` are always the current XLEN rather than SXLEN. Hence,
-      for example, if MXLEN = 64 and SXLEN = 32, then this register is 64 bits when the current
-      privilege mode is M (running RV64 code) but 32 bits when the privilege mode is S (RV32 code).
+  Note that the widths of `siselect` and `sireg4` are always the current XLEN rather than SXLEN. Hence,
+  for example, if MXLEN = 64 and SXLEN = 32, then this register is 64 bits when the current
+  privilege mode is M (running RV64 code) but 32 bits when the privilege mode is S (RV32 code).
 
-  - id: csr-sireg4-unimplemented
-    normative: true
-    text: |
-      The behavior upon accessing `sireg4` from M-mode or S-mode, while `siselect` holds a value that is
-      not implemented at supervisor level, is UNSPECIFIED.
+  The behavior upon accessing `sireg4` from M-mode or S-mode, while `siselect` holds a value that is
+  not implemented at supervisor level, is UNSPECIFIED.
 
-  - id: csr-sireg4-unimplemented-recommendation
-    normative: false
-    text: |
-      It is recommended that implementations raise an illegal instruction exception for such
-      accesses, to facilitate possible emulation (by M-mode) of these accesses.
+  It is recommended that implementations raise an illegal instruction exception for such
+  accesses, to facilitate possible emulation (by M-mode) of these accesses.
 
-  - id: csr-sireg4-extension-disabled
-    normative: false
-    text: |
-      An extension is considered not to be implemented at supervisor level if machine level has
-      disabled the extension for S-mode, such as by the settings of certain fields in CSR
-      `menvcfg`, for example.
+  An extension is considered not to be implemented at supervisor level if machine level has
+  disabled the extension for S-mode, such as by the settings of certain fields in CSR
+  `menvcfg`, for example.
 
 fields:
   VALUE:
@@ -58,10 +40,8 @@ fields:
     location_rv32: 31-0
     location_rv64: 63-0
     type: RW
-    description:
-      - id: csr-sireg4-value-desc
-        normative: true
-        text: The data read from or written to the register selected by the current `siselect` value.
+    description: |
+      The data read from or written to the register selected by the current `siselect` value.
     reset_value: UNDEFINED_LEGAL
     sw_write(csr_value): |
       Csr handle = indirect_csr_lookup(CSR[siselect].VALUE, 4);
diff --git a/spec/std/isa/csr/Smcsrind/sireg5.yaml b/spec/std/isa/csr/Smcsrind/sireg5.yaml
index d71114e582..b640737633 100644
--- a/spec/std/isa/csr/Smcsrind/sireg5.yaml
+++ b/spec/std/isa/csr/Smcsrind/sireg5.yaml
@@ -11,46 +11,28 @@ writable: true
 priv_mode: S
 length: SXLEN
 definedBy: Sscsrind
-description:
-  - id: csr-sireg5-behavior-implemented
-    normative: true
-    text: |
-      Access to `sireg5` from M-mode or S-mode while `siselect` holds a number in a
-      standard-defined and implemented range results in specific behavior that, for each combination of
-      `siselect` and `sireg5`, is defined by the extension to which the `siselect` value is allocated.
+description: |
+  Access to `sireg5` from M-mode or S-mode while `siselect` holds a number in a
+  standard-defined and implemented range results in specific behavior that, for each combination of
+  `siselect` and `sireg5`, is defined by the extension to which the `siselect` value is allocated.
 
-  - id: csr-sireg5-typical-behavior-note
-    normative: false
-    text: |
-      Ordinarily, `sireg5` will access register state, access read-only 0 state, or, unless
-      executing in a virtual machine (covered in the next section), raise an illegal instruction
-      exception.
+  Ordinarily, `sireg5` will access register state, access read-only 0 state, or, unless
+  executing in a virtual machine (covered in the next section), raise an illegal instruction
+  exception.
 
-  - id: csr-sireg5-xlens
-    normative: true
-    text: |
-      Note that the widths of `siselect` and `sireg5` are always the current XLEN rather than SXLEN. Hence,
-      for example, if MXLEN = 64 and SXLEN = 32, then this register is 64 bits when the current
-      privilege mode is M (running RV64 code) but 32 bits when the privilege mode is S (RV32 code).
+  Note that the widths of `siselect` and `sireg5` are always the current XLEN rather than SXLEN. Hence,
+  for example, if MXLEN = 64 and SXLEN = 32, then this register is 64 bits when the current
+  privilege mode is M (running RV64 code) but 32 bits when the privilege mode is S (RV32 code).
 
-  - id: csr-sireg5-unimplemented
-    normative: true
-    text: |
-      The behavior upon accessing `sireg5` from M-mode or S-mode, while `siselect` holds a value that is
-      not implemented at supervisor level, is UNSPECIFIED.
+  The behavior upon accessing `sireg5` from M-mode or S-mode, while `siselect` holds a value that is
+  not implemented at supervisor level, is UNSPECIFIED.
 
-  - id: csr-sireg5-unimplemented-recommendation
-    normative: false
-    text: |
-      It is recommended that implementations raise an illegal instruction exception for such
-      accesses, to facilitate possible emulation (by M-mode) of these accesses.
+  It is recommended that implementations raise an illegal instruction exception for such
+  accesses, to facilitate possible emulation (by M-mode) of these accesses.
 
-  - id: csr-sireg5-extension-disabled
-    normative: false
-    text: |
-      An extension is considered not to be implemented at supervisor level if machine level has
-      disabled the extension for S-mode, such as by the settings of certain fields in CSR
-      `menvcfg`, for example.
+  An extension is considered not to be implemented at supervisor level if machine level has
+  disabled the extension for S-mode, such as by the settings of certain fields in CSR
+  `menvcfg`, for example.
 
 fields:
   VALUE:
@@ -58,10 +40,8 @@ fields:
     location_rv32: 31-0
     location_rv64: 63-0
     type: RW
-    description:
-      - id: csr-sireg5-value-desc
-        normative: true
-        text: The data read from or written to the register selected by the current `siselect` value.
+    description: |
+      The data read from or written to the register selected by the current `siselect` value.
     reset_value: UNDEFINED_LEGAL
     sw_write(csr_value): |
       Csr handle = indirect_csr_lookup(CSR[siselect].VALUE, 5);
diff --git a/spec/std/isa/csr/Smcsrind/sireg6.yaml b/spec/std/isa/csr/Smcsrind/sireg6.yaml
index 4cdeb131a9..b8b9ecc771 100644
--- a/spec/std/isa/csr/Smcsrind/sireg6.yaml
+++ b/spec/std/isa/csr/Smcsrind/sireg6.yaml
@@ -11,46 +11,28 @@ writable: true
 priv_mode: S
 length: SXLEN
 definedBy: Sscsrind
-description:
-  - id: csr-sireg6-behavior-implemented
-    normative: true
-    text: |
-      Access to `sireg6` from M-mode or S-mode while `siselect` holds a number in a
-      standard-defined and implemented range results in specific behavior that, for each combination of
-      `siselect` and `sireg6`, is defined by the extension to which the `siselect` value is allocated.
+description: |
+  Access to `sireg6` from M-mode or S-mode while `siselect` holds a number in a
+  standard-defined and implemented range results in specific behavior that, for each combination of
+  `siselect` and `sireg6`, is defined by the extension to which the `siselect` value is allocated.
 
-  - id: csr-sireg6-typical-behavior-note
-    normative: false
-    text: |
-      Ordinarily, `sireg6` will access register state, access read-only 0 state, or, unless
-      executing in a virtual machine (covered in the next section), raise an illegal instruction
-      exception.
+  Ordinarily, `sireg6` will access register state, access read-only 0 state, or, unless
+  executing in a virtual machine (covered in the next section), raise an illegal instruction
+  exception.
 
-  - id: csr-sireg6-xlens
-    normative: true
-    text: |
-      Note that the widths of `siselect` and `sireg6` are always the current XLEN rather than SXLEN. Hence,
-      for example, if MXLEN = 64 and SXLEN = 32, then this register is 64 bits when the current
-      privilege mode is M (running RV64 code) but 32 bits when the privilege mode is S (RV32 code).
+  Note that the widths of `siselect` and `sireg6` are always the current XLEN rather than SXLEN. Hence,
+  for example, if MXLEN = 64 and SXLEN = 32, then this register is 64 bits when the current
+  privilege mode is M (running RV64 code) but 32 bits when the privilege mode is S (RV32 code).
 
-  - id: csr-sireg6-unimplemented
-    normative: true
-    text: |
-      The behavior upon accessing `sireg6` from M-mode or S-mode, while `siselect` holds a value that is
-      not implemented at supervisor level, is UNSPECIFIED.
+  The behavior upon accessing `sireg6` from M-mode or S-mode, while `siselect` holds a value that is
+  not implemented at supervisor level, is UNSPECIFIED.
 
-  - id: csr-sireg6-unimplemented-recommendation
-    normative: false
-    text: |
-      It is recommended that implementations raise an illegal instruction exception for such
-      accesses, to facilitate possible emulation (by M-mode) of these accesses.
+  It is recommended that implementations raise an illegal instruction exception for such
+  accesses, to facilitate possible emulation (by M-mode) of these accesses.
 
-  - id: csr-sireg6-extension-disabled
-    normative: false
-    text: |
-      An extension is considered not to be implemented at supervisor level if machine level has
-      disabled the extension for S-mode, such as by the settings of certain fields in CSR
-      `menvcfg`, for example.
+  An extension is considered not to be implemented at supervisor level if machine level has
+  disabled the extension for S-mode, such as by the settings of certain fields in CSR
+  `menvcfg`, for example.
 
 fields:
   VALUE:
@@ -58,10 +40,8 @@ fields:
     location_rv32: 31-0
     location_rv64: 63-0
     type: RW
-    description:
-      - id: csr-sireg6-value-desc
-        normative: true
-        text: The data read from or written to the register selected by the current `siselect` value.
+    description: |
+      The data read from or written to the register selected by the current `siselect` value.
     reset_value: UNDEFINED_LEGAL
     sw_write(csr_value): |
       Csr handle = indirect_csr_lookup(CSR[siselect].VALUE, 6);
diff --git a/spec/std/isa/csr/Smcsrind/siselect.yaml b/spec/std/isa/csr/Smcsrind/siselect.yaml
index ff93f28831..b4ed44f6b2 100644
--- a/spec/std/isa/csr/Smcsrind/siselect.yaml
+++ b/spec/std/isa/csr/Smcsrind/siselect.yaml
@@ -11,29 +11,20 @@ writable: true
 priv_mode: S
 length: SXLEN
 definedBy: Sscsrind
-description:
-  - id: csr-siselect-value-range
-    normative: true
-    text: |
-      The `siselect` register will support the value range 0..0xFFF at a minimum. A future extension may
-      define a value range outside of this minimum range. Only if such an extension is implemented will
-      `siselect` be required to support larger values.
+description: |
+  The `siselect` register will support the value range 0..0xFFF at a minimum. A future extension may
+  define a value range outside of this minimum range. Only if such an extension is implemented will
+  `siselect` be required to support larger values.
 
-  - id: csr-siselect-emulation
-    normative: false
-    text: |
-      Requiring a range of 0-0xFFF for `siselect`, even though most or all of the space may be reserved or
-      inaccessible, permits M-mode to emulate indirectly accessed registers in this implemented range,
-      including registers that may be standardized in the future.
+  Requiring a range of 0-0xFFF for `siselect`, even though most or all of the space may be reserved or
+  inaccessible, permits M-mode to emulate indirectly accessed registers in this implemented range,
+  including registers that may be standardized in the future.
 
-  - id: csr-siselect-msb
-    normative: true
-    text: |
-      Values of `siselect` with the most-significant bit set (bit XLEN - 1 = 1) are designated only for
-      custom use, presumably for accessing custom registers through the alias CSRs. Values of `siselect`
-      with the most-significant bit clear are designated only for standard use and are reserved until
-      allocated to a standard architecture extension. If XLEN is changed, the most-significant bit of
-      `siselect` moves to the new position, retaining its value from before.
+  Values of `siselect` with the most-significant bit set (bit XLEN - 1 = 1) are designated only for
+  custom use, presumably for accessing custom registers through the alias CSRs. Values of `siselect`
+  with the most-significant bit clear are designated only for standard use and are reserved until
+  allocated to a standard architecture extension. If XLEN is changed, the most-significant bit of
+  `siselect` moves to the new position, retaining its value from before.
 
 fields:
   VALUE:
@@ -41,11 +32,8 @@ fields:
     location_rv32: 31-0
     location_rv64: 63-0
     type: RW
-    description:
-      - id: csr-siselect-value-desc
-        normative: true
-        text: |
-          Value ranges are allocated to dependent extensions, which specify the
-          register state accessible via each `sireg*` register, for each `siselect` value.
+    description: |
+      Value ranges are allocated to dependent extensions, which specify the
+      register state accessible via each `sireg*` register, for each `siselect` value.
     reset_value: UNDEFINED_LEGAL
 sw_read(): |
diff --git a/spec/std/isa/csr/Smcsrind/vsireg.yaml b/spec/std/isa/csr/Smcsrind/vsireg.yaml
index 9ea709e347..face94c56c 100644
--- a/spec/std/isa/csr/Smcsrind/vsireg.yaml
+++ b/spec/std/isa/csr/Smcsrind/vsireg.yaml
@@ -12,47 +12,26 @@ writable: true
 priv_mode: VS
 length: VSXLEN
 definedBy: Smcsrind
-description:
-  - id: csr-vsireg-purpose
-    normative: true
-    text: |
-      The `vsireg` CSR is one of several alias registers used to indirectly access
-      virtual supervisor-level CSRs in VS-mode or VU-mode.
+description: |
+  The `vsireg` CSR is one of several alias registers used to indirectly access
+  virtual supervisor-level CSRs in VS-mode or VU-mode.
 
-  - id: csr-vsireg-selection-mechanism
-    normative: true
-    text: |
-      The register addressed by `vsireg` is selected by the current value of the `vsiselect` CSR.
+  The register addressed by `vsireg` is selected by the current value of the `vsiselect` CSR.
 
-  - id: csr-vsireg-indirect-access-benefit
-    normative: false
-    text: |
-      The alias mechanism allows indirect CSR access, which helps in virtualization and future extensibility.
+  The alias mechanism allows indirect CSR access, which helps in virtualization and future extensibility.
 
-  - id: csr-vsireg-access-exception
-    normative: true
-    text: |
-      A virtual instruction exception is raised for attempts from VS-mode or VU-mode
-      to directly access `vsiselect` or `vsireg`, or from VU-mode to access `siselect` or `sireg`.
+  A virtual instruction exception is raised for attempts from VS-mode or VU-mode
+  to directly access `vsiselect` or `vsireg`, or from VU-mode to access `siselect` or `sireg`.
 
-  - id: csr-vsireg-unimplemented-target
-    normative: true
-    text: |
-      The behavior of accesses to `vsireg` when `vsiselect` holds a value that is
-      not implemented at the HS level is UNSPECIFIED.
+  The behavior of accesses to `vsireg` when `vsiselect` holds a value that is
+  not implemented at the HS level is UNSPECIFIED.
 
-  - id: csr-vsireg-unimplemented-target-recommendation
-    normative: false
-    text: |
-      Implementations are recommended to raise an illegal instruction exception for
-      accesses to unimplemented targets via `vsireg`.
+  Implementations are recommended to raise an illegal instruction exception for
+  accesses to unimplemented targets via `vsireg`.
 
-  - id: csr-vsireg-width
-    normative: true
-    text: |
-      The width of `vsireg` is always the current `XLEN`, not `VSXLEN`.
-      For example, if `HSXLEN = 64` and `VSXLEN = 32`, then `vsireg` is 64 bits wide
-      when accessed from HS-mode (RV64), but 32 bits when accessed from VS-mode (RV32).
+  The width of `vsireg` is always the current `XLEN`, not `VSXLEN`.
+  For example, if `HSXLEN = 64` and `VSXLEN = 32`, then `vsireg` is 64 bits wide
+  when accessed from HS-mode (RV64), but 32 bits when accessed from VS-mode (RV32).
 
 fields:
   VALUE:
@@ -61,11 +40,8 @@ fields:
     location_rv64: 63-0
     type: RW
     description:
-      - id: csr-vsireg-value-indirect-data
-        normative: true
-        text: |
-          The data read from or written to the register selected by the current
-          value of the `vsiselect` CSR.
+      The data read from or written to the register selected by the current
+      value of the `vsiselect` CSR.
     reset_value: UNDEFINED_LEGAL
     sw_write(csr_value): |
       Csr handle = indirect_csr_lookup(CSR[vsiselect].VALUE, 1);
diff --git a/spec/std/isa/csr/Smcsrind/vsireg2.yaml b/spec/std/isa/csr/Smcsrind/vsireg2.yaml
index 5db742ccec..b880a1cd59 100644
--- a/spec/std/isa/csr/Smcsrind/vsireg2.yaml
+++ b/spec/std/isa/csr/Smcsrind/vsireg2.yaml
@@ -12,47 +12,26 @@ writable: true
 priv_mode: VS
 length: VSXLEN
 definedBy: Smcsrind
-description:
-  - id: csr-vsireg2-purpose
-    normative: true
-    text: |
-      The `vsireg2` CSR is one of several alias registers used to indirectly access
-      virtual supervisor-level CSRs in VS-mode or VU-mode.
+description: |
+  The `vsireg2` CSR is one of several alias registers used to indirectly access
+  virtual supervisor-level CSRs in VS-mode or VU-mode.
 
-  - id: csr-vsireg2-selection-mechanism
-    normative: true
-    text: |
-      The register addressed by `vsireg2` is selected by the current value of the `vsiselect` CSR.
+  The register addressed by `vsireg2` is selected by the current value of the `vsiselect` CSR.
 
-  - id: csr-vsireg2-indirect-access-benefit
-    normative: false
-    text: |
-      The alias mechanism allows indirect CSR access, which helps in virtualization and future extensibility.
+  The alias mechanism allows indirect CSR access, which helps in virtualization and future extensibility.
 
-  - id: csr-vsireg2-access-exception
-    normative: true
-    text: |
-      A virtual instruction exception is raised for attempts from VS-mode or VU-mode
-      to directly access `vsiselect` or `vsireg2`, or from VU-mode to access `siselect` or `siregX`.
+  A virtual instruction exception is raised for attempts from VS-mode or VU-mode
+  to directly access `vsiselect` or `vsireg2`, or from VU-mode to access `siselect` or `siregX`.
 
-  - id: csr-vsireg2-unimplemented-target
-    normative: true
-    text: |
-      The behavior of accesses to `vsireg2` when `vsiselect` holds a value that is
-      not implemented at the HS level is UNSPECIFIED.
+  The behavior of accesses to `vsireg2` when `vsiselect` holds a value that is
+  not implemented at the HS level is UNSPECIFIED.
 
-  - id: csr-vsireg2-unimplemented-target-recommendation
-    normative: false
-    text: |
-      Implementations are recommended to raise an illegal instruction exception for
-      accesses to unimplemented targets via `vsireg2`.
+  Implementations are recommended to raise an illegal instruction exception for
+  accesses to unimplemented targets via `vsireg2`.
 
-  - id: csr-vsireg2-width
-    normative: true
-    text: |
-      The width of `vsireg2` is always the current `XLEN`, not `VSXLEN`.
-      For example, if `HSXLEN = 64` and `VSXLEN = 32`, then `vsireg2` is 64 bits wide
-      when accessed from HS-mode (RV64), but 32 bits when accessed from VS-mode (RV32).
+  The width of `vsireg2` is always the current `XLEN`, not `VSXLEN`.
+  For example, if `HSXLEN = 64` and `VSXLEN = 32`, then `vsireg2` is 64 bits wide
+  when accessed from HS-mode (RV64), but 32 bits when accessed from VS-mode (RV32).
 
 fields:
   VALUE:
@@ -60,11 +39,8 @@ fields:
     location_rv32: 31-0
     location_rv64: 63-0
     type: RW
-    description:
-      - id: csr-vsireg2-value-indirect-data
-        normative: true
-        text: |
-          Data read or written based on the currently selected `vsiselect` value.
+    description: |
+      Data read or written based on the currently selected `vsiselect` value.
     reset_value: UNDEFINED_LEGAL
     sw_write(csr_value): |
       Csr handle = indirect_csr_lookup(CSR[vsiselect].VALUE, 2);
diff --git a/spec/std/isa/csr/Smcsrind/vsireg3.yaml b/spec/std/isa/csr/Smcsrind/vsireg3.yaml
index 93b32212e1..dc31fbcf63 100644
--- a/spec/std/isa/csr/Smcsrind/vsireg3.yaml
+++ b/spec/std/isa/csr/Smcsrind/vsireg3.yaml
@@ -12,47 +12,26 @@ writable: true
 priv_mode: VS
 length: VSXLEN
 definedBy: Smcsrind
-description:
-  - id: csr-vsireg3-purpose
-    normative: true
-    text: |
-      The `vsireg3` CSR is one of several alias registers used to indirectly access
-      virtual supervisor-level CSRs in VS-mode or VU-mode.
+description: |
+  The `vsireg3` CSR is one of several alias registers used to indirectly access
+  virtual supervisor-level CSRs in VS-mode or VU-mode.
 
-  - id: csr-vsireg3-selection-mechanism
-    normative: true
-    text: |
-      The register addressed by `vsireg3` is selected by the current value of the `vsiselect` CSR.
+  The register addressed by `vsireg3` is selected by the current value of the `vsiselect` CSR.
 
-  - id: csr-vsireg3-indirect-access-benefit
-    normative: false
-    text: |
-      The alias mechanism allows indirect CSR access, which helps in virtualization and future extensibility.
+  The alias mechanism allows indirect CSR access, which helps in virtualization and future extensibility.
 
-  - id: csr-vsireg3-access-exception
-    normative: true
-    text: |
-      A virtual instruction exception is raised for attempts from VS-mode or VU-mode
-      to directly access `vsiselect` or `vsireg3`, or from VU-mode to access `siselect` or `siregX`.
+  A virtual instruction exception is raised for attempts from VS-mode or VU-mode
+  to directly access `vsiselect` or `vsireg3`, or from VU-mode to access `siselect` or `siregX`.
 
-  - id: csr-vsireg3-unimplemented-target
-    normative: true
-    text: |
-      The behavior of accesses to `vsireg3` when `vsiselect` holds a value that is
-      not implemented at the HS level is UNSPECIFIED.
+  The behavior of accesses to `vsireg3` when `vsiselect` holds a value that is
+  not implemented at the HS level is UNSPECIFIED.
 
-  - id: csr-vsireg3-unimplemented-target-recommendation
-    normative: false
-    text: |
-      Implementations are recommended to raise an illegal instruction exception for
-      accesses to unimplemented targets via `vsireg3`.
+  Implementations are recommended to raise an illegal instruction exception for
+  accesses to unimplemented targets via `vsireg3`.
 
-  - id: csr-vsireg3-width
-    normative: true
-    text: |
-      The width of `vsireg3` is always the current `XLEN`, not `VSXLEN`.
-      For example, if `HSXLEN = 64` and `VSXLEN = 32`, then `vsireg3` is 64 bits wide
-      when accessed from HS-mode (RV64), but 32 bits when accessed from VS-mode (RV32).
+  The width of `vsireg3` is always the current `XLEN`, not `VSXLEN`.
+  For example, if `HSXLEN = 64` and `VSXLEN = 32`, then `vsireg3` is 64 bits wide
+  when accessed from HS-mode (RV64), but 32 bits when accessed from VS-mode (RV32).
 
 fields:
   VALUE:
@@ -60,11 +39,7 @@ fields:
     location_rv32: 31-0
     location_rv64: 63-0
     type: RW
-    description:
-      - id: csr-vsireg3-value-indirect-data
-        normative: true
-        text: |
-          The data read or written based on the currently selected `vsiselect` value.
+    description: The data read or written based on the currently selected `vsiselect` value.
     reset_value: UNDEFINED_LEGAL
     sw_write(csr_value): |
       Csr handle = indirect_csr_lookup(CSR[vsiselect].VALUE, 3);
diff --git a/spec/std/isa/csr/Smcsrind/vsireg4.yaml b/spec/std/isa/csr/Smcsrind/vsireg4.yaml
index 7da8145364..f827c456c9 100644
--- a/spec/std/isa/csr/Smcsrind/vsireg4.yaml
+++ b/spec/std/isa/csr/Smcsrind/vsireg4.yaml
@@ -12,47 +12,26 @@ writable: true
 priv_mode: VS
 length: VSXLEN
 definedBy: Smcsrind
-description:
-  - id: csr-vsireg4-purpose
-    normative: true
-    text: |
-      The `vsireg4` CSR is one of several alias registers used to indirectly access
-      virtual supervisor-level CSRs in VS-mode or VU-mode.
+description: |
+  The `vsireg4` CSR is one of several alias registers used to indirectly access
+  virtual supervisor-level CSRs in VS-mode or VU-mode.
 
-  - id: csr-vsireg4-selection-mechanism
-    normative: true
-    text: |
-      The register addressed by `vsireg4` is selected by the current value of the `vsiselect` CSR.
+  The register addressed by `vsireg4` is selected by the current value of the `vsiselect` CSR.
 
-  - id: csr-vsireg4-indirect-access-benefit
-    normative: false
-    text: |
-      The alias mechanism allows indirect CSR access, which helps in virtualization and future extensibility.
+  The alias mechanism allows indirect CSR access, which helps in virtualization and future extensibility.
 
-  - id: csr-vsireg4-access-exception
-    normative: true
-    text: |
-      A virtual instruction exception is raised for attempts from VS-mode or VU-mode
-      to directly access `vsiselect` or `vsireg4`, or from VU-mode to access `siselect` or `siregX`.
+  A virtual instruction exception is raised for attempts from VS-mode or VU-mode
+  to directly access `vsiselect` or `vsireg4`, or from VU-mode to access `siselect` or `siregX`.
 
-  - id: csr-vsireg4-unimplemented-target
-    normative: true
-    text: |
-      The behavior of accesses to `vsireg4` when `vsiselect` holds a value that is
-      not implemented at the HS level is UNSPECIFIED.
+  The behavior of accesses to `vsireg4` when `vsiselect` holds a value that is
+  not implemented at the HS level is UNSPECIFIED.
 
-  - id: csr-vsireg4-unimplemented-target-recommendation
-    normative: false
-    text: |
-      Implementations are recommended to raise an illegal instruction exception for
-      accesses to unimplemented targets via `vsireg4`.
+  Implementations are recommended to raise an illegal instruction exception for
+  accesses to unimplemented targets via `vsireg4`.
 
-  - id: csr-vsireg4-width
-    normative: true
-    text: |
-      The width of `vsireg4` is always the current `XLEN`, not `VSXLEN`.
-      For example, if `HSXLEN = 64` and `VSXLEN = 32`, then `vsireg4` is 64 bits wide
-      when accessed from HS-mode (RV64), but 32 bits when accessed from VS-mode (RV32).
+  The width of `vsireg4` is always the current `XLEN`, not `VSXLEN`.
+  For example, if `HSXLEN = 64` and `VSXLEN = 32`, then `vsireg4` is 64 bits wide
+  when accessed from HS-mode (RV64), but 32 bits when accessed from VS-mode (RV32).
 
 fields:
   VALUE:
@@ -60,11 +39,7 @@ fields:
     location_rv32: 31-0
     location_rv64: 63-0
     type: RW
-    description:
-      - id: csr-vsireg4-value-indirect-data
-        normative: true
-        text: |
-          The data read or written based on the currently selected `vsiselect` value.
+    description: The data read or written based on the currently selected `vsiselect` value.
     reset_value: UNDEFINED_LEGAL
     sw_write(csr_value): |
       Csr handle = indirect_csr_lookup(CSR[vsiselect].VALUE, 4);
diff --git a/spec/std/isa/csr/Smcsrind/vsireg5.yaml b/spec/std/isa/csr/Smcsrind/vsireg5.yaml
index 1e003f7935..e540c1c3d3 100644
--- a/spec/std/isa/csr/Smcsrind/vsireg5.yaml
+++ b/spec/std/isa/csr/Smcsrind/vsireg5.yaml
@@ -12,47 +12,26 @@ writable: true
 priv_mode: VS
 length: VSXLEN
 definedBy: Smcsrind
-description:
-  - id: csr-vsireg5-purpose
-    normative: true
-    text: |
-      The `vsireg5` CSR is one of several alias registers used to indirectly access
-      virtual supervisor-level CSRs in VS-mode or VU-mode.
+description: |
+  The `vsireg5` CSR is one of several alias registers used to indirectly access
+  virtual supervisor-level CSRs in VS-mode or VU-mode.
 
-  - id: csr-vsireg5-selection
-    normative: true
-    text: |
-      The register addressed by `vsireg5` is selected by the current value of the `vsiselect` CSR.
+  The register addressed by `vsireg5` is selected by the current value of the `vsiselect` CSR.
 
-  - id: csr-vsireg5-benefits
-    normative: false
-    text: |
-      The alias mechanism allows indirect CSR access, which helps in virtualization and future extensibility.
+  The alias mechanism allows indirect CSR access, which helps in virtualization and future extensibility.
 
-  - id: csr-vsireg5-access-traps
-    normative: true
-    text: |
-      A virtual instruction exception is raised for attempts from VS-mode or VU-mode
-      to directly access `vsiselect` or `vsireg5`, or from VU-mode to access `siselect` or `siregX`.
+  A virtual instruction exception is raised for attempts from VS-mode or VU-mode
+  to directly access `vsiselect` or `vsireg5`, or from VU-mode to access `siselect` or `siregX`.
 
-  - id: csr-vsireg5-unimplemented
-    normative: true
-    text: |
-      The behavior of accesses to `vsireg5` when `vsiselect` holds a value that is
-      not implemented at the HS level is UNSPECIFIED.
+  The behavior of accesses to `vsireg5` when `vsiselect` holds a value that is
+  not implemented at the HS level is UNSPECIFIED.
 
-  - id: csr-vsireg5-recommendation
-    normative: false
-    text: |
-      Implementations are recommended to raise an illegal instruction exception for
-      such accesses to unimplemented targets.
+  Implementations are recommended to raise an illegal instruction exception for
+  such accesses to unimplemented targets.
 
-  - id: csr-vsireg5-width
-    normative: true
-    text: |
-      The width of `vsireg5` is always the current `XLEN`, not `VSXLEN`.
-      For example, if `HSXLEN = 64` and `VSXLEN = 32`, then `vsireg5` is 64 bits wide
-      when accessed from HS-mode (RV64), but 32 bits when accessed from VS-mode (RV32).
+  The width of `vsireg5` is always the current `XLEN`, not `VSXLEN`.
+  For example, if `HSXLEN = 64` and `VSXLEN = 32`, then `vsireg5` is 64 bits wide
+  when accessed from HS-mode (RV64), but 32 bits when accessed from VS-mode (RV32).
 
 fields:
   VALUE:
@@ -60,11 +39,8 @@ fields:
     location_rv32: 31-0
     location_rv64: 63-0
     type: RW
-    description:
-      - id: csr-vsireg5-value
-        normative: true
-        text: |
-          The data read or written from the register selected by the value in `vsiselect`.
+    description: |
+      The data read or written from the register selected by the value in `vsiselect`.
     reset_value: UNDEFINED_LEGAL
     sw_write(csr_value): |
       Csr handle = indirect_csr_lookup(CSR[vsiselect].VALUE, 5);
diff --git a/spec/std/isa/csr/Smcsrind/vsireg6.yaml b/spec/std/isa/csr/Smcsrind/vsireg6.yaml
index 4d9c9e2f0a..cc17a0e63d 100644
--- a/spec/std/isa/csr/Smcsrind/vsireg6.yaml
+++ b/spec/std/isa/csr/Smcsrind/vsireg6.yaml
@@ -12,47 +12,26 @@ writable: true
 priv_mode: VS
 length: VSXLEN
 definedBy: Smcsrind
-description:
-  - id: csr-vsireg6-purpose
-    normative: true
-    text: |
-      The `vsireg6` CSR is one of several alias registers used to indirectly access
-      virtual supervisor-level CSRs in VS-mode or VU-mode.
+description: |
+  The `vsireg6` CSR is one of several alias registers used to indirectly access
+  virtual supervisor-level CSRs in VS-mode or VU-mode.
 
-  - id: csr-vsireg6-selection
-    normative: true
-    text: |
-      The register addressed by `vsireg6` is selected by the current value of the `vsiselect` CSR.
+  The register addressed by `vsireg6` is selected by the current value of the `vsiselect` CSR.
 
-  - id: csr-vsireg6-benefits
-    normative: false
-    text: |
-      The alias mechanism allows indirect CSR access, which helps in virtualization and future extensibility.
+  The alias mechanism allows indirect CSR access, which helps in virtualization and future extensibility.
 
-  - id: csr-vsireg6-access-traps
-    normative: true
-    text: |
-      A virtual instruction exception is raised for attempts from VS-mode or VU-mode
-      to directly access `vsiselect` or `vsireg6`, or from VU-mode to access `siselect` or `siregX`.
+  A virtual instruction exception is raised for attempts from VS-mode or VU-mode
+  to directly access `vsiselect` or `vsireg6`, or from VU-mode to access `siselect` or `siregX`.
 
-  - id: csr-vsireg6-unimplemented
-    normative: true
-    text: |
-      The behavior of accesses to `vsireg6` when `vsiselect` holds a value that is
-      not implemented at the HS level is UNSPECIFIED.
+  The behavior of accesses to `vsireg6` when `vsiselect` holds a value that is
+  not implemented at the HS level is UNSPECIFIED.
 
-  - id: csr-vsireg6-recommendation
-    normative: false
-    text: |
-      Implementations are recommended to raise an illegal instruction exception for
-      such accesses to unimplemented targets.
+  Implementations are recommended to raise an illegal instruction exception for
+  such accesses to unimplemented targets.
 
-  - id: csr-vsireg6-width
-    normative: true
-    text: |
-      The width of `vsireg6` is always the current `XLEN`, not `VSXLEN`.
-      For example, if `HSXLEN = 64` and `VSXLEN = 32`, then `vsireg6` is 64 bits wide
-      when accessed from HS-mode (RV64), but 32 bits when accessed from VS-mode (RV32).
+  The width of `vsireg6` is always the current `XLEN`, not `VSXLEN`.
+  For example, if `HSXLEN = 64` and `VSXLEN = 32`, then `vsireg6` is 64 bits wide
+  when accessed from HS-mode (RV64), but 32 bits when accessed from VS-mode (RV32).
 
 fields:
   VALUE:
@@ -60,11 +39,8 @@ fields:
     location_rv32: 31-0
     location_rv64: 63-0
     type: RW
-    description:
-      - id: csr-vsireg6-value
-        normative: true
-        text: |
-          The data read or written from the register selected by the current value of `vsiselect`.
+    description: |
+      The data read or written from the register selected by the current value of `vsiselect`.
     reset_value: UNDEFINED_LEGAL
     sw_write(csr_value): |
       Csr handle = indirect_csr_lookup(CSR[vsiselect].VALUE, 6);
diff --git a/spec/std/isa/csr/Smcsrind/vsiselect.yaml b/spec/std/isa/csr/Smcsrind/vsiselect.yaml
index 40f48af448..ae63b53376 100644
--- a/spec/std/isa/csr/Smcsrind/vsiselect.yaml
+++ b/spec/std/isa/csr/Smcsrind/vsiselect.yaml
@@ -12,40 +12,25 @@ writable: true
 priv_mode: VS
 length: VSXLEN
 definedBy: Smcsrind
-description:
-  - id: csr-vsiselect-range-minimum
-    normative: true
-    text: |
-      The `vsiselect` register will support the value range 0..0xFFF at a minimum.
-      A future extension may define a value range outside of this minimum range.
-      Only if such an extension is implemented will `vsiselect` be required to support larger values.
+description: |
+  The `vsiselect` register will support the value range 0..0xFFF at a minimum.
+  A future extension may define a value range outside of this minimum range.
+  Only if such an extension is implemented will `vsiselect` be required to support larger values.
 
-  - id: csr-vsiselect-hypervisor-emulation
-    normative: true
-    text: |
-      Requiring a range of 0-0xFFF for `vsiselect`, even though most or all of the space may be reserved
-      or inaccessible, permits a hypervisor to emulate indirectly accessed registers in this implemented
-      range, including registers that may be standardized in the future.
+  Requiring a range of 0-0xFFF for `vsiselect`, even though most or all of the space may be reserved
+  or inaccessible, permits a hypervisor to emulate indirectly accessed registers in this implemented
+  range, including registers that may be standardized in the future.
 
-  - id: csr-vsiselect-siselect-width-matching
-    normative: false
-    text: |
-      It is recommended that `vsiselect` and `siselect` be implemented with the same number of bits.
-      This avoids the creation of a virtualization hole due to observable differences between their widths.
+  It is recommended that `vsiselect` and `siselect` be implemented with the same number of bits.
+  This avoids the creation of a virtualization hole due to observable differences between their widths.
 
-  - id: csr-vsiselect-msb-custom-vs-standard
-    normative: true
-    text: |
-      Values of `vsiselect` with the most-significant bit set (bit XLEN - 1 = 1) are designated only for
-      custom use, presumably for accessing custom registers through the alias CSRs.
-      Values with the most-significant bit clear are designated only for standard use and are reserved
-      until allocated to a standard architecture extension.
+  Values of `vsiselect` with the most-significant bit set (bit XLEN - 1 = 1) are designated only for
+  custom use, presumably for accessing custom registers through the alias CSRs.
+  Values with the most-significant bit clear are designated only for standard use and are reserved
+  until allocated to a standard architecture extension.
 
-  - id: csr-vsiselect-msb-behavior-xlen-change
-    normative: true
-    text: |
-      If XLEN is changed, the most-significant bit of `vsiselect` moves to the new position,
-      retaining its value from before.
+  If XLEN is changed, the most-significant bit of `vsiselect` moves to the new position,
+  retaining its value from before.
 
 fields:
   VALUE:
@@ -53,11 +38,8 @@ fields:
     location_rv32: 31-0
     location_rv64: 63-0
     type: RW
-    description:
-      - id: csr-vsiselect-value-indirect-access
-        normative: true
-        text: |
-          The index value selecting the register accessed through the `vsireg*` alias registers.
+    description: |
+      The index value selecting the register accessed through the `vsireg*` alias registers.
     reset_value: UNDEFINED_LEGAL
 
 sw_read(): |
diff --git a/spec/std/isa/csr/Ssqosid/srmcfg.yaml b/spec/std/isa/csr/Ssqosid/srmcfg.yaml
index bb51612f60..2da0b3eba1 100644
--- a/spec/std/isa/csr/Ssqosid/srmcfg.yaml
+++ b/spec/std/isa/csr/Ssqosid/srmcfg.yaml
@@ -11,89 +11,47 @@ writable: true
 priv_mode: S
 length: SXLEN
 definedBy: Ssqosid
-description:
-  - id: csr-srmcfg-purpose
-    normative: true
-    text: |
-      The `srmcfg` register is used to configure a Resource Control ID (`RCID`) and a Monitoring Counter ID (`MCID`).
-      Both `RCID` and `MCID` are WARL fields.
-
-  - id: csr-`srmcfg`-field-usage
-    normative: true
-    text: |
-      The `RCID` and `MCID` accompany each request made by the hart to shared resource controllers.
-      The `RCID` is used to determine the resource allocations (e.g., cache occupancy limits, memory bandwidth limits, etc.) to enforce.
-      The `MCID` is used to identify a counter to monitor resource usage.
+description: |
+  The `srmcfg` register is used to configure a Resource Control ID (`RCID`) and a Monitoring Counter ID (`MCID`).
+  Both `RCID` and `MCID` are WARL fields.
+
+  The `RCID` and `MCID` accompany each request made by the hart to shared resource controllers.
+  The `RCID` is used to determine the resource allocations (e.g., cache occupancy limits, memory bandwidth limits, etc.) to enforce.
+  The `MCID` is used to identify a counter to monitor resource usage.
+
+  The `RCID` and `MCID` configured in the `srmcfg` CSR apply to all privilege modes of software execution on that hart by default,
+  but this behavior may be overridden by future extensions.
+
+  If extension `Smstateen` is implemented together with `Ssqosid`, then `Ssqosid` also requires the `SRMCFG` bit in `mstateen0` to be implemented.
+  If `mstateen0.SRMCFG` is `0`, attempts to access `srmcfg` in privilege modes less privileged than M-mode raise an illegal-instruction exception.
+
+  If `mstateen0.SRMCFG` is `1` or if extension `Smstateen` is not implemented, attempts to access `srmcfg` when `V=1` raise a virtual-instruction exception.
+
+  A reset value of `0` is suggested for the `RCID` field, matching resource controllers' default behavior of associating all capacity with `RCID=0`.
+
+  The `MCID` reset value does not affect functionality and may be implementation-defined.
+
+  Typically, fewer bits are allocated for `RCID` (e.g., to support tens of `RCID`s) than for `MCID` (e.g., to support hundreds of `MCID`s).
+
+  A common `RCID` is usually used to group apps or VMs, pooling resource allocations to meet collective SLAs.
+
+  If an SLA breach occurs, unique `MCID`s enable granular monitoring, aiding decisions on resource adjustment,
+  associating a different `RCID` with a subset of members, or migrating members to other machines.
+  The larger pool of `MCID`s speeds up this analysis.
+
+  The `RCID` and `MCID` in `srmcfg` apply across all privilege levels on the hart.
+  Typically, higher-privilege modes don't modify `srmcfg`, as they often serve lower-privileged tasks.
+  If differentiation is needed, higher privilege code can update `srmcfg` and restore it before returning to a lower privilege level.
+
+  In VM environments, hypervisors usually manage resource allocations, keeping the Guest OS out of QoS flows.
+  If needed, the hypervisor can virtualize the `srmcfg` CSR for a VM using the virtual-instruction exceptions triggered upon Guest access.
+
+  If the direct selection of `RCID` and `MCID` by the VM becomes common and emulation overhead is an issue,
+  future extensions may allow VS-mode to use a selector for a hypervisor-configured set of CSRs holding `RCID` and `MCID` values designated for that Guest OS use.
 
-  - id: csr-srmcfg-default-scope
-    normative: true
-    text: |
-      The `RCID` and `MCID` configured in the `srmcfg` CSR apply to all privilege modes of software execution on that hart by default,
-      but this behavior may be overridden by future extensions.
-
-  - id: csr-srmcfg-smstateen-interaction
-    normative: true
-    text: |
-      If extension `Smstateen` is implemented together with `Ssqosid`, then `Ssqosid` also requires the `SRMCFG` bit in `mstateen0` to be implemented.
-      If `mstateen0.SRMCFG` is `0`, attempts to access `srmcfg` in privilege modes less privileged than M-mode raise an illegal-instruction exception.
-
-  - id: csr-srmcfg-vsmode-exception
-    normative: true
-    text: |
-      If `mstateen0.SRMCFG` is `1` or if extension `Smstateen` is not implemented, attempts to access `srmcfg` when `V=1` raise a virtual-instruction exception.
-
-  - id: csr-srmcfg-rcid-reset
-    normative: false
-    text: |
-      A reset value of `0` is suggested for the `RCID` field, matching resource controllers' default behavior of associating all capacity with `RCID=0`.
-
-  - id: csr-srmcfg-mcid-reset
-    normative: false
-    text: |
-      The `MCID` reset value does not affect functionality and may be implementation-defined.
-
-  - id: csr-srmcfg-id-bit-allocation
-    normative: false
-    text: |
-      Typically, fewer bits are allocated for `RCID` (e.g., to support tens of `RCID`s) than for `MCID` (e.g., to support hundreds of `MCID`s).
-
-  - id: csr-srmcfg-rcid-grouping
-    normative: false
-    text: |
-      A common `RCID` is usually used to group apps or VMs, pooling resource allocations to meet collective SLAs.
-
-  - id: csr-srmcfg-mcid-granularity
-    normative: false
-    text: |
-      If an SLA breach occurs, unique `MCID`s enable granular monitoring, aiding decisions on resource adjustment,
-      associating a different `RCID` with a subset of members, or migrating members to other machines.
-      The larger pool of `MCID`s speeds up this analysis.
-
-  - id: csr-srmcfg-privilege-behavior
-    normative: false
-    text: |
-      The `RCID` and `MCID` in `srmcfg` apply across all privilege levels on the hart.
-      Typically, higher-privilege modes don't modify `srmcfg`, as they often serve lower-privileged tasks.
-      If differentiation is needed, higher privilege code can update `srmcfg` and restore it before returning to a lower privilege level.
-
-  - id: csr-srmcfg-vm-virtualization
-    normative: false
-    text: |
-      In VM environments, hypervisors usually manage resource allocations, keeping the Guest OS out of QoS flows.
-      If needed, the hypervisor can virtualize the `srmcfg` CSR for a VM using the virtual-instruction exceptions triggered upon Guest access.
-
-  - id: csr-srmcfg-vs-mode-future
-    normative: false
-    text: |
-      If the direct selection of `RCID` and `MCID` by the VM becomes common and emulation overhead is an issue,
-      future extensions may allow VS-mode to use a selector for a hypervisor-configured set of CSRs holding `RCID` and `MCID` values designated for that Guest OS use.
-
-  - id: csr-srmcfg-context-switch
-    normative: false
-    text: |
-      During context switches, the supervisor may choose to execute with the `srmcfg` of the outgoing context to attribute the execution to it.
-      Prior to restoring the new context, it switches to the new VM’s `srmcfg`.
-      The supervisor can also use a separate configuration for execution not to be attributed to either context.
+  During context switches, the supervisor may choose to execute with the `srmcfg` of the outgoing context to attribute the execution to it.
+  Prior to restoring the new context, it switches to the new VM’s `srmcfg`.
+  The supervisor can also use a separate configuration for execution not to be attributed to either context.
 fields:
   RCID:
     location: 11-0
diff --git a/spec/std/isa/csr/hstateen0.yaml b/spec/std/isa/csr/hstateen0.yaml
index dfa590dd26..7d61e74c00 100644
--- a/spec/std/isa/csr/hstateen0.yaml
+++ b/spec/std/isa/csr/hstateen0.yaml
@@ -11,51 +11,36 @@ address: 0x60C
 priv_mode: S
 length: 64
 writable: true
-description:
-  - id: csr-hstateen0-purpose
-    normative: true
-    text: |
-      Each bit of a `stateen` CSR controls less-privileged access to an extension’s state,
-      for an extension that was not deemed "worthy" of a full XS field in `sstatus` like the
-      FS and VS fields for the F and V extensions.
-  - id: csr-hstateen0-num-justification
-    normative: false
-    text: |
-      The number of registers provided at each level is four because it is believed that
-      4 * 64 = 256 bits for machine and hypervisor levels, and 4 * 32 = 128 bits for
-      supervisor level, will be adequate for many years to come, perhaps for as long as
-      the RISC-V ISA is in use.
-      The exact number four is an attempted compromise between providing too few bits on
-      the one hand and going overboard with CSRs that will never be used on the other.
-  - id: csr-hstateen0-scope
-    normative: true
-    text: |
-      The `stateen` registers at each level control access to state at all less-privileged
-      levels, but not at its own level.
-  - id: csr-hstateen0-effect
-    normative: true
-    text: |
-      When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute
-      in that privilege mode an instruction that implicitly updates the state without reading
-      it may or may not raise an illegal instruction or virtual instruction exception.
-      Such cases must be disambiguated by being explicitly specified one way or the other.
-      In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the
-      ISA extensions that introduce the controlled state.
-  - id: csr-hstateen0-encodings
-    normative: true
-    text: |
-      With the hypervisor extension, the `hstateen` CSRs have identical encodings to the `mstateen` CSRs,
-      except controlling accesses for a virtual machine (from VS and VU modes).
-  - id: csr-hstateen0-zero
-    normative: true
-    text: |
-      For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero),
-      the same bit appears as read-only zero in `sstateen` when accessed in VS-mode.
-  - id: csr-hstateen0-read-only
-    normative: true
-    text: |
-      A bit in an `hstateen` CSR cannot be read-only one unless the same bit is read-only one
-      in the matching `mstateen` CSR.
+description: |
+  Each bit of a `stateen` CSR controls less-privileged access to an extension’s state,
+  for an extension that was not deemed "worthy" of a full XS field in `sstatus` like the
+  FS and VS fields for the F and V extensions.
+
+  The number of registers provided at each level is four because it is believed that
+  4 * 64 = 256 bits for machine and hypervisor levels, and 4 * 32 = 128 bits for
+  supervisor level, will be adequate for many years to come, perhaps for as long as
+  the RISC-V ISA is in use.
+  The exact number four is an attempted compromise between providing too few bits on
+  the one hand and going overboard with CSRs that will never be used on the other.
+
+  The `stateen` registers at each level control access to state at all less-privileged
+  levels, but not at its own level.
+
+  When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute
+  in that privilege mode an instruction that implicitly updates the state without reading
+  it may or may not raise an illegal instruction or virtual instruction exception.
+  Such cases must be disambiguated by being explicitly specified one way or the other.
+  In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the
+  ISA extensions that introduce the controlled state.
+
+  With the hypervisor extension, the `hstateen` CSRs have identical encodings to the `mstateen` CSRs,
+  except controlling accesses for a virtual machine (from VS and VU modes).
+
+  For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero),
+  the same bit appears as read-only zero in `sstateen` when accessed in VS-mode.
+
+  A bit in an `hstateen` CSR cannot be read-only one unless the same bit is read-only one
+  in the matching `mstateen` CSR.
 
 definedBy:
   allOf:
diff --git a/spec/std/isa/csr/hstateen0h.yaml b/spec/std/isa/csr/hstateen0h.yaml
index e1a780dbbe..7f1090cd2b 100644
--- a/spec/std/isa/csr/hstateen0h.yaml
+++ b/spec/std/isa/csr/hstateen0h.yaml
@@ -12,18 +12,15 @@ priv_mode: S
 length: 32
 base: 32
 writable: true
-description:
-  - id: csr-hstateen0h-purpose
-    normative: true
-    text: |
-      For RV64 harts, the Smstateen/Ssstateen extension adds four new 64-bit CSRs at machine level: `mstateen0` (Machine State Enable 0),
-      `mstateen1`, `mstateen2`, and `mstateen3`. If supervisor mode is implemented, another four CSRs are defined at
-      supervisor level: `sstateen0`, `sstateen1`, `sstateen2`, and `sstateen3`. And if the hypervisor extension is implemented,
-      another set of CSRs is added: `hstateen0`, `hstateen1`, `hstateen2`, and `hstateen3`.
+description: |
+  For RV64 harts, the Smstateen/Ssstateen extension adds four new 64-bit CSRs at machine level: `mstateen0` (Machine State Enable 0),
+  `mstateen1`, `mstateen2`, and `mstateen3`. If supervisor mode is implemented, another four CSRs are defined at
+  supervisor level: `sstateen0`, `sstateen1`, `sstateen2`, and `sstateen3`. And if the hypervisor extension is implemented,
+  another set of CSRs is added: `hstateen0`, `hstateen1`, `hstateen2`, and `hstateen3`.
 
-      For RV32, the registers listed above are 32-bit, and for the machine-level and hypervisor CSRs there is a corresponding
-      set of high-half CSRs for the upper 32 bits of each register: `mstateen0h`, `mstateen1h`, `mstateen2h`, `mstateen3h`, `hstateen0h`,
-      `hstateen1h`, `hstateen2h`, and `hstateen3h`.
+  For RV32, the registers listed above are 32-bit, and for the machine-level and hypervisor CSRs there is a corresponding
+  set of high-half CSRs for the upper 32 bits of each register: `mstateen0h`, `mstateen1h`, `mstateen2h`, `mstateen3h`, `hstateen0h`,
+  `hstateen1h`, `hstateen2h`, and `hstateen3h`.
 
 definedBy:
   allOf:
diff --git a/spec/std/isa/csr/hstateen1.yaml b/spec/std/isa/csr/hstateen1.yaml
index a5e211dff6..83a395acc7 100644
--- a/spec/std/isa/csr/hstateen1.yaml
+++ b/spec/std/isa/csr/hstateen1.yaml
@@ -11,51 +11,36 @@ address: 0x60D
 priv_mode: S
 length: 64
 writable: true
-description:
-  - id: csr-hstateen1-purpose
-    normative: true
-    text: |
-      Each bit of a `stateen` CSR controls less-privileged access to an extension’s state,
-      for an extension that was not deemed "worthy" of a full XS field in `sstatus` like the
-      FS and VS fields for the F and V extensions.
-  - id: csr-hstateen1-num-justification
-    normative: false
-    text: |
-      The number of registers provided at each level is four because it is believed that
-      4 * 64 = 256 bits for machine and hypervisor levels, and 4 * 32 = 128 bits for
-      supervisor level, will be adequate for many years to come, perhaps for as long as
-      the RISC-V ISA is in use.
-      The exact number four is an attempted compromise between providing too few bits on
-      the one hand and going overboard with CSRs that will never be used on the other.
-  - id: csr-hstateen1-scope
-    normative: true
-    text: |
-      The `stateen` registers at each level control access to state at all less-privileged
-      levels, but not at its own level.
-  - id: csr-hstateen1-effect
-    normative: true
-    text: |
-      When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute
-      in that privilege mode an instruction that implicitly updates the state without reading
-      it may or may not raise an illegal instruction or virtual instruction exception.
-      Such cases must be disambiguated by being explicitly specified one way or the other.
-      In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the
-      ISA extensions that introduce the controlled state.
-  - id: csr-hstateen1-encodings
-    normative: true
-    text: |
-      With the hypervisor extension, the `hstateen` CSRs have identical encodings to the `mstateen` CSRs,
-      except controlling accesses for a virtual machine (from VS and VU modes).
-  - id: csr-hstateen1-zero
-    normative: true
-    text: |
-      For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero),
-      the same bit appears as read-only zero in `sstateen` when accessed in VS-mode.
-  - id: csr-hstateen1-read-only
-    normative: true
-    text: |
-      A bit in an `hstateen` CSR cannot be read-only one unless the same bit is read-only one
-      in the matching `mstateen` CSR.
+description: |
+  Each bit of a `stateen` CSR controls less-privileged access to an extension’s state,
+  for an extension that was not deemed "worthy" of a full XS field in `sstatus` like the
+  FS and VS fields for the F and V extensions.
+
+  The number of registers provided at each level is four because it is believed that
+  4 * 64 = 256 bits for machine and hypervisor levels, and 4 * 32 = 128 bits for
+  supervisor level, will be adequate for many years to come, perhaps for as long as
+  the RISC-V ISA is in use.
+  The exact number four is an attempted compromise between providing too few bits on
+  the one hand and going overboard with CSRs that will never be used on the other.
+
+  The `stateen` registers at each level control access to state at all less-privileged
+  levels, but not at its own level.
+
+  When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute
+  in that privilege mode an instruction that implicitly updates the state without reading
+  it may or may not raise an illegal instruction or virtual instruction exception.
+  Such cases must be disambiguated by being explicitly specified one way or the other.
+  In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the
+  ISA extensions that introduce the controlled state.
+
+  With the hypervisor extension, the `hstateen` CSRs have identical encodings to the `mstateen` CSRs,
+  except controlling accesses for a virtual machine (from VS and VU modes).
+
+  For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero),
+  the same bit appears as read-only zero in `sstateen` when accessed in VS-mode.
+
+  A bit in an `hstateen` CSR cannot be read-only one unless the same bit is read-only one
+  in the matching `mstateen` CSR.
 
 definedBy:
   allOf:
diff --git a/spec/std/isa/csr/hstateen1h.yaml b/spec/std/isa/csr/hstateen1h.yaml
index 7a59a65633..870f27b1f2 100644
--- a/spec/std/isa/csr/hstateen1h.yaml
+++ b/spec/std/isa/csr/hstateen1h.yaml
@@ -12,18 +12,15 @@ priv_mode: S
 length: 32
 base: 32
 writable: true
-description:
-  - id: csr-hstateen0h-purpose
-    normative: true
-    text: |
-      For RV64 harts, the Smstateen/Ssstateen extension adds four new 64-bit CSRs at machine level: `mstateen0` (Machine State Enable 0),
-      `mstateen1`, `mstateen2`, and `mstateen3`. If supervisor mode is implemented, another four CSRs are defined at
-      supervisor level: `sstateen0`, `sstateen1`, `sstateen2`, and `sstateen3`. And if the hypervisor extension is implemented,
-      another set of CSRs is added: `hstateen0`, `hstateen1`, `hstateen2`, and `hstateen3`.
+description: |
+  For RV64 harts, the Smstateen/Ssstateen extension adds four new 64-bit CSRs at machine level: `mstateen0` (Machine State Enable 0),
+  `mstateen1`, `mstateen2`, and `mstateen3`. If supervisor mode is implemented, another four CSRs are defined at
+  supervisor level: `sstateen0`, `sstateen1`, `sstateen2`, and `sstateen3`. And if the hypervisor extension is implemented,
+  another set of CSRs is added: `hstateen0`, `hstateen1`, `hstateen2`, and `hstateen3`.
 
-      For RV32, the registers listed above are 32-bit, and for the machine-level and hypervisor CSRs there is a corresponding
-      set of high-half CSRs for the upper 32 bits of each register: `mstateen0h`, `mstateen1h`, `mstateen2h`, `mstateen3h`, `hstateen0h`,
-      `hstateen1h`, `hstateen2h`, and `hstateen3h`.
+  For RV32, the registers listed above are 32-bit, and for the machine-level and hypervisor CSRs there is a corresponding
+  set of high-half CSRs for the upper 32 bits of each register: `mstateen0h`, `mstateen1h`, `mstateen2h`, `mstateen3h`, `hstateen0h`,
+  `hstateen1h`, `hstateen2h`, and `hstateen3h`.
 
 definedBy:
   allOf:
diff --git a/spec/std/isa/csr/hstateen2.yaml b/spec/std/isa/csr/hstateen2.yaml
index 1d848eacc7..c556e770c1 100644
--- a/spec/std/isa/csr/hstateen2.yaml
+++ b/spec/std/isa/csr/hstateen2.yaml
@@ -11,51 +11,36 @@ address: 0x60E
 priv_mode: S
 length: 64
 writable: true
-description:
-  - id: csr-hstateen2-purpose
-    normative: true
-    text: |
-      Each bit of a `stateen` CSR controls less-privileged access to an extension’s state,
-      for an extension that was not deemed "worthy" of a full XS field in `sstatus` like the
-      FS and VS fields for the F and V extensions.
-  - id: csr-hstateen2-num-justification
-    normative: false
-    text: |
-      The number of registers provided at each level is four because it is believed that
-      4 * 64 = 256 bits for machine and hypervisor levels, and 4 * 32 = 128 bits for
-      supervisor level, will be adequate for many years to come, perhaps for as long as
-      the RISC-V ISA is in use.
-      The exact number four is an attempted compromise between providing too few bits on
-      the one hand and going overboard with CSRs that will never be used on the other.
-  - id: csr-hstateen2-scope
-    normative: true
-    text: |
-      The `stateen` registers at each level control access to state at all less-privileged
-      levels, but not at its own level.
-  - id: csr-hstateen2-effect
-    normative: true
-    text: |
-      When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute
-      in that privilege mode an instruction that implicitly updates the state without reading
-      it may or may not raise an illegal instruction or virtual instruction exception.
-      Such cases must be disambiguated by being explicitly specified one way or the other.
-      In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the
-      ISA extensions that introduce the controlled state.
-  - id: csr-hstateen2-encodings
-    normative: true
-    text: |
-      With the hypervisor extension, the `hstateen` CSRs have identical encodings to the `mstateen` CSRs,
-      except controlling accesses for a virtual machine (from VS and VU modes).
-  - id: csr-hstateen2-zero
-    normative: true
-    text: |
-      For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero),
-      the same bit appears as read-only zero in `sstateen` when accessed in VS-mode.
-  - id: csr-hstateen2-read-only
-    normative: true
-    text: |
-      A bit in an `hstateen` CSR cannot be read-only one unless the same bit is read-only one
-      in the matching `mstateen` CSR.
+description: |
+  Each bit of a `stateen` CSR controls less-privileged access to an extension’s state,
+  for an extension that was not deemed "worthy" of a full XS field in `sstatus` like the
+  FS and VS fields for the F and V extensions.
+
+  The number of registers provided at each level is four because it is believed that
+  4 * 64 = 256 bits for machine and hypervisor levels, and 4 * 32 = 128 bits for
+  supervisor level, will be adequate for many years to come, perhaps for as long as
+  the RISC-V ISA is in use.
+  The exact number four is an attempted compromise between providing too few bits on
+  the one hand and going overboard with CSRs that will never be used on the other.
+
+  The `stateen` registers at each level control access to state at all less-privileged
+  levels, but not at its own level.
+
+  When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute
+  in that privilege mode an instruction that implicitly updates the state without reading
+  it may or may not raise an illegal instruction or virtual instruction exception.
+  Such cases must be disambiguated by being explicitly specified one way or the other.
+  In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the
+  ISA extensions that introduce the controlled state.
+
+  With the hypervisor extension, the `hstateen` CSRs have identical encodings to the `mstateen` CSRs,
+  except controlling accesses for a virtual machine (from VS and VU modes).
+
+  For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero),
+  the same bit appears as read-only zero in `sstateen` when accessed in VS-mode.
+
+  A bit in an `hstateen` CSR cannot be read-only one unless the same bit is read-only one
+  in the matching `mstateen` CSR.
 
 definedBy:
   allOf:
diff --git a/spec/std/isa/csr/hstateen2h.yaml b/spec/std/isa/csr/hstateen2h.yaml
index e3d1f6d458..1d8c596099 100644
--- a/spec/std/isa/csr/hstateen2h.yaml
+++ b/spec/std/isa/csr/hstateen2h.yaml
@@ -12,18 +12,15 @@ priv_mode: S
 length: 32
 base: 32
 writable: true
-description:
-  - id: csr-hstateen0h-purpose
-    normative: true
-    text: |
-      For RV64 harts, the Smstateen/Ssstateen extension adds four new 64-bit CSRs at machine level: `mstateen0` (Machine State Enable 0),
-      `mstateen1`, `mstateen2`, and `mstateen3`. If supervisor mode is implemented, another four CSRs are defined at
-      supervisor level: `sstateen0`, `sstateen1`, `sstateen2`, and `sstateen3`. And if the hypervisor extension is implemented,
-      another set of CSRs is added: `hstateen0`, `hstateen1`, `hstateen2`, and `hstateen3`.
+description: |
+  For RV64 harts, the Smstateen/Ssstateen extension adds four new 64-bit CSRs at machine level: `mstateen0` (Machine State Enable 0),
+  `mstateen1`, `mstateen2`, and `mstateen3`. If supervisor mode is implemented, another four CSRs are defined at
+  supervisor level: `sstateen0`, `sstateen1`, `sstateen2`, and `sstateen3`. And if the hypervisor extension is implemented,
+  another set of CSRs is added: `hstateen0`, `hstateen1`, `hstateen2`, and `hstateen3`.
 
-      For RV32, the registers listed above are 32-bit, and for the machine-level and hypervisor CSRs there is a corresponding
-      set of high-half CSRs for the upper 32 bits of each register: `mstateen0h`, `mstateen1h`, `mstateen2h`, `mstateen3h`, `hstateen0h`,
-      `hstateen1h`, `hstateen2h`, and `hstateen3h`.
+  For RV32, the registers listed above are 32-bit, and for the machine-level and hypervisor CSRs there is a corresponding
+  set of high-half CSRs for the upper 32 bits of each register: `mstateen0h`, `mstateen1h`, `mstateen2h`, `mstateen3h`, `hstateen0h`,
+  `hstateen1h`, `hstateen2h`, and `hstateen3h`.
 
 definedBy:
   allOf:
diff --git a/spec/std/isa/csr/hstateen3.yaml b/spec/std/isa/csr/hstateen3.yaml
index 90304c3f01..0285af6b9c 100644
--- a/spec/std/isa/csr/hstateen3.yaml
+++ b/spec/std/isa/csr/hstateen3.yaml
@@ -11,51 +11,36 @@ address: 0x60F
 priv_mode: S
 length: 64
 writable: true
-description:
-  - id: csr-hstateen3-purpose
-    normative: true
-    text: |
-      Each bit of a `stateen` CSR controls less-privileged access to an extension’s state,
-      for an extension that was not deemed "worthy" of a full XS field in `sstatus` like the
-      FS and VS fields for the F and V extensions.
-  - id: csr-hstateen3-num-justification
-    normative: false
-    text: |
-      The number of registers provided at each level is four because it is believed that
-      4 * 64 = 256 bits for machine and hypervisor levels, and 4 * 32 = 128 bits for
-      supervisor level, will be adequate for many years to come, perhaps for as long as
-      the RISC-V ISA is in use.
-      The exact number four is an attempted compromise between providing too few bits on
-      the one hand and going overboard with CSRs that will never be used on the other.
-  - id: csr-hstateen3-scope
-    normative: true
-    text: |
-      The `stateen` registers at each level control access to state at all less-privileged
-      levels, but not at its own level.
-  - id: csr-hstateen3-effect
-    normative: true
-    text: |
-      When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute
-      in that privilege mode an instruction that implicitly updates the state without reading
-      it may or may not raise an illegal instruction or virtual instruction exception.
-      Such cases must be disambiguated by being explicitly specified one way or the other.
-      In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the
-      ISA extensions that introduce the controlled state.
-  - id: csr-hstateen3-encodings
-    normative: true
-    text: |
-      With the hypervisor extension, the `hstateen` CSRs have identical encodings to the `mstateen` CSRs,
-      except controlling accesses for a virtual machine (from VS and VU modes).
-  - id: csr-hstateen3-zero
-    normative: true
-    text: |
-      For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero),
-      the same bit appears as read-only zero in `sstateen` when accessed in VS-mode.
-  - id: csr-hstateen3-read-only
-    normative: true
-    text: |
-      A bit in an `hstateen` CSR cannot be read-only one unless the same bit is read-only one
-      in the matching `mstateen` CSR.
+description: |
+  Each bit of a `stateen` CSR controls less-privileged access to an extension’s state,
+  for an extension that was not deemed "worthy" of a full XS field in `sstatus` like the
+  FS and VS fields for the F and V extensions.
+
+  The number of registers provided at each level is four because it is believed that
+  4 * 64 = 256 bits for machine and hypervisor levels, and 4 * 32 = 128 bits for
+  supervisor level, will be adequate for many years to come, perhaps for as long as
+  the RISC-V ISA is in use.
+  The exact number four is an attempted compromise between providing too few bits on
+  the one hand and going overboard with CSRs that will never be used on the other.
+
+  The `stateen` registers at each level control access to state at all less-privileged
+  levels, but not at its own level.
+
+  When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute
+  in that privilege mode an instruction that implicitly updates the state without reading
+  it may or may not raise an illegal instruction or virtual instruction exception.
+  Such cases must be disambiguated by being explicitly specified one way or the other.
+  In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the
+  ISA extensions that introduce the controlled state.
+
+  With the hypervisor extension, the `hstateen` CSRs have identical encodings to the `mstateen` CSRs,
+  except controlling accesses for a virtual machine (from VS and VU modes).
+
+  For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero),
+  the same bit appears as read-only zero in `sstateen` when accessed in VS-mode.
+
+  A bit in an `hstateen` CSR cannot be read-only one unless the same bit is read-only one
+  in the matching `mstateen` CSR.
 
 definedBy:
   allOf:
diff --git a/spec/std/isa/csr/hstateen3h.yaml b/spec/std/isa/csr/hstateen3h.yaml
index 3659c1c99f..41865f5fa0 100644
--- a/spec/std/isa/csr/hstateen3h.yaml
+++ b/spec/std/isa/csr/hstateen3h.yaml
@@ -12,18 +12,15 @@ priv_mode: S
 length: 32
 base: 32
 writable: true
-description:
-  - id: csr-hstateen0h-purpose
-    normative: true
-    text: |
-      For RV64 harts, the Smstateen/Ssstateen extension adds four new 64-bit CSRs at machine level: `mstateen0` (Machine State Enable 0),
-      `mstateen1`, `mstateen2`, and `mstateen3`. If supervisor mode is implemented, another four CSRs are defined at
-      supervisor level: `sstateen0`, `sstateen1`, `sstateen2`, and `sstateen3`. And if the hypervisor extension is implemented,
-      another set of CSRs is added: `hstateen0`, `hstateen1`, `hstateen2`, and `hstateen3`.
+description: |
+  For RV64 harts, the Smstateen/Ssstateen extension adds four new 64-bit CSRs at machine level: `mstateen0` (Machine State Enable 0),
+  `mstateen1`, `mstateen2`, and `mstateen3`. If supervisor mode is implemented, another four CSRs are defined at
+  supervisor level: `sstateen0`, `sstateen1`, `sstateen2`, and `sstateen3`. And if the hypervisor extension is implemented,
+  another set of CSRs is added: `hstateen0`, `hstateen1`, `hstateen2`, and `hstateen3`.
 
-      For RV32, the registers listed above are 32-bit, and for the machine-level and hypervisor CSRs there is a corresponding
-      set of high-half CSRs for the upper 32 bits of each register: `mstateen0h`, `mstateen1h`, `mstateen2h`, `mstateen3h`, `hstateen0h`,
-      `hstateen1h`, `hstateen2h`, and `hstateen3h`.
+  For RV32, the registers listed above are 32-bit, and for the machine-level and hypervisor CSRs there is a corresponding
+  set of high-half CSRs for the upper 32 bits of each register: `mstateen0h`, `mstateen1h`, `mstateen2h`, `mstateen3h`, `hstateen0h`,
+  `hstateen1h`, `hstateen2h`, and `hstateen3h`.
 
 definedBy:
   allOf:
diff --git a/spec/std/isa/csr/hstatus.yaml b/spec/std/isa/csr/hstatus.yaml
index b65947ad8d..9ea2b391dd 100644
--- a/spec/std/isa/csr/hstatus.yaml
+++ b/spec/std/isa/csr/hstatus.yaml
@@ -23,9 +23,7 @@ fields:
     location: 33-32
     base: 64
     description:
-      - id: csr-hstatus-vsxl-values
-        normative: false
-        text: |
+      - text: |
           Determines the effective XLEN in VS-mode. Valid values are:
 
           [separator="!"]
@@ -36,14 +34,12 @@ fields:
           ! 1     ! 64
           !===
         when(): return VSXLEN == 3264;
-      - id: csr-hstatus-vsxl-rv32
-        normative: false
-        text: |
+
+      - text: |
           Because the implementation only supports a single VSXLEN == 32, this field is read-only-0.
         when(): return VSXLEN == 32;
-      - id: csr-hstatus-vsxl-rv64
-        normative: false
-        text: |
+
+      - text: |
           Because the implementation only supports a single VSXLEN == 64, this field is read-only-1.
         when(): return VSXLEN == 64;
 
@@ -77,76 +73,64 @@ fields:
   VTSR:
     location: 22
     long_name: Virtual Trap SRET
-    description:
-      - id: csr-hstatus-vtsr-behavior
-        normative: false
-        text: |
-          When `hstatus.VTSR` is set, executing the `sret` instruction in VS-mode
-          raises a `Virtual Instruction` exception.
-
-          When `hstatus.VTSR` is clear, an `sret` instruction in VS-mode returns control
-          to the mode stored in `vsstatus.SPP`.
+    description: |
+      When `hstatus.VTSR` is set, executing the `sret` instruction in VS-mode
+      raises a `Virtual Instruction` exception.
+
+      When `hstatus.VTSR` is clear, an `sret` instruction in VS-mode returns control
+      to the mode stored in `vsstatus.SPP`.
     type: RW
     reset_value: UNDEFINED_LEGAL
   VTW:
     location: 21
     long_name: Virtual Trap WFI
-    description:
-      - id: csr-hstatus-vtw-behavior
-        normative: false
-        text: |
-          When `hstatus.VTW` is set, a `wfi` instruction executed in VS-mode raises
-          a `Virtual Instruction` exception after waiting an implementation-defined
-          amount of time (which can be 0).
+    description: |
+      When `hstatus.VTW` is set, a `wfi` instruction executed in VS-mode raises
+      a `Virtual Instruction` exception after waiting an implementation-defined
+      amount of time (which can be 0).
 
-          When both `hstatus.VTW` and `mstatus.TW` are clear, a `wfi` instruction
-          executes in VS-mode without a timeout period.
+      When both `hstatus.VTW` and `mstatus.TW` are clear, a `wfi` instruction
+      executes in VS-mode without a timeout period.
 
-          The `wfi` instruction is also affected by `mstatus.TW`, as shown below:
+      The `wfi` instruction is also affected by `mstatus.TW`, as shown below:
 
-          [separator="!",%autowidth,%footer]
-          !===
-          .2+! [.rotate]#`mstatus.TW`# .2+! [.rotate]#`hstatus.VTW`# 4+^.>! `wfi` behavior
-          h! HS-mode h! U-mode h! VS-mode h! VU-mode
+      [separator="!",%autowidth,%footer]
+      !===
+      .2+! [.rotate]#`mstatus.TW`# .2+! [.rotate]#`hstatus.VTW`# 4+^.>! `wfi` behavior
+      h! HS-mode h! U-mode h! VS-mode h! VU-mode
 
-          ! 0 ! 0 ! Wait ! Trap (I) ! Wait ! Trap (V)
-          ! 0 ! 1 ! Wait ! Trap (I) ! Trap (V) ! Trap (V)
-          ! 1 ! - ! Trap (I) ! Trap (I) ! Trap (I) ! Trap (I)
+      ! 0 ! 0 ! Wait ! Trap (I) ! Wait ! Trap (V)
+      ! 0 ! 1 ! Wait ! Trap (I) ! Trap (V) ! Trap (V)
+      ! 1 ! - ! Trap (I) ! Trap (I) ! Trap (I) ! Trap (I)
 
-          6+! Trap (I) - Trap with `Illegal Instruction` code +
-          Trap (V) - Trap with `Virtual Instruction` code
-          !===
+      6+! Trap (I) - Trap with `Illegal Instruction` code +
+      Trap (V) - Trap with `Virtual Instruction` code
+      !===
     type: RW
     reset_value: UNDEFINED_LEGAL
   VTVM:
     location: 20
     long_name: Virtual Trap Virtual Memory
-    description:
-      - id: csr-hstatus-vtvm-behavior
-        normative: false
-        text: |
-          When set, a 'Virtual Instruction` trap occurs when executing an `sfence.vma`, `sinval.vma`,
-          or an explicit CSR access of the `satp` (really `vsatp`) register when in VS-mode.
+    description: |
+      When set, a 'Virtual Instruction` trap occurs when executing an `sfence.vma`, `sinval.vma`,
+      or an explicit CSR access of the `satp` (really `vsatp`) register when in VS-mode.
 
-          When clear, the instructions execute as normal in VS-mode.
+      When clear, the instructions execute as normal in VS-mode.
 
-          Notably, `hstatus.VTVM` does *not* cause `hfence.vvma`, `sfence.w.inval`, or `sfence.inval.ir` to trap.
+      Notably, `hstatus.VTVM` does *not* cause `hfence.vvma`, `sfence.w.inval`, or `sfence.inval.ir` to trap.
 
-          `mstatus.TVM` does not affect the VS-mode instructions controlled by `hstatus.TVTM`.
+      `mstatus.TVM` does not affect the VS-mode instructions controlled by `hstatus.TVTM`.
     type: RW
     reset_value: UNDEFINED_LEGAL
   VGEIN:
     location: 17-12
     long_name: Virtual Guest External Interrupt Number
-    description:
-      - id: csr-hstatus-vgein-behavior
-        normative: false
-        text: |
-          Selects the guest external interrupt source for VS-level external interrupts.
+    description: |
+      Selects the guest external interrupt source for VS-level external interrupts.
 
-          When `hstatus.VGEIN` == 0, no external interrupt source is selected.
+      When `hstatus.VGEIN` == 0, no external interrupt source is selected.
 
-          When `hstatus.VGEIN` != 0, it selects which bit of `hgeip` is currently active in VS-mode.
+      When `hstatus.VGEIN` != 0, it selects which bit of `hgeip` is currently active in VS-mode.
 
     type(): |
       # if NUM_EXTERNAL_GUEST_INTERRUPTS+1 is 63 (because indexing in `hgeip` starts at 1),
@@ -169,92 +153,75 @@ fields:
   HU:
     location: 9
     long_name: Hypervisor in U-mode
-    description:
-      - id: csr-hstatus-hu-behavior
-        normative: false
-        text: |
-          When set, the hypervisor load/store instructions (`hlv`, `hlvx`, and `hsv`) can be
-          executed in U-mode.
+    description: |
+      When set, the hypervisor load/store instructions (`hlv`, `hlvx`, and `hsv`) can be
+      executed in U-mode.
 
-          When clear, the hypervisor load/store instructions cause an `Illegal Instruction` trap.
+      When clear, the hypervisor load/store instructions cause an `Illegal Instruction` trap.
     type: RW
     reset_value: UNDEFINED_LEGAL
   SPVP:
     location: 8
     long_name: Supervisor Previous Virtual Privilege
-    description:
-      - id: csr-hstatus-spvp-behavior
-        normative: false
-        text: |
-          Written by hardware:
+    description: |
+      Written by hardware:
 
-          * When taking a trap into HS-mode from VS-mode or VU-mode, `hstatus.SPVP` is written with the nominal privilege mode
+      * When taking a trap into HS-mode from VS-mode or VU-mode, `hstatus.SPVP` is written with the nominal privilege mode
 
-          Notably, unlike its analog `mstatus.SPP`, `hstatus.SPVP` is *not* cleared when returning from a trap.
+      Notably, unlike its analog `mstatus.SPP`, `hstatus.SPVP` is *not* cleared when returning from a trap.
 
-          Can also be written by software without immediate side-effect.
+      Can also be written by software without immediate side-effect.
 
-          Affects execution by:
+      Affects execution by:
 
-          * Controls the effective privilege level applied to the hypervisor load/store instructions, `hlv`, `hlvx`, and `hsv`.
+      * Controls the effective privilege level applied to the hypervisor load/store instructions, `hlv`, `hlvx`, and `hsv`.
     type: RW
     reset_value: UNDEFINED_LEGAL
   SPV:
     location: 7
     long_name: Supervisor Previous Virtualization Mode
-    description:
-      - id: csr-hstatus-spv-behavior
-        normative: false
-        text: |
-          Written by hardware:
+    description: |
+      Written by hardware:
 
-          * On a trap into HS-mode, hardware writes 1 when the prior mode was VS-mode or VU-mode, and 0 otherwise.
+      * On a trap into HS-mode, hardware writes 1 when the prior mode was VS-mode or VU-mode, and 0 otherwise.
 
-          Can also be written by software without immediate side-effect.
+      Can also be written by software without immediate side-effect.
 
-          Affects execution by:
+      Affects execution by:
 
-          * When an `sret` instruction in executed in HS-mode or M-mode,
-            control returns to VS-mode or VU-mode (as selected by `mstatus.SPP`) when
-            `hstatus.SPV` is 1 and to HS-mode or U-mode otherwise.
+      * When an `sret` instruction in executed in HS-mode or M-mode,
+        control returns to VS-mode or VU-mode (as selected by `mstatus.SPP`) when
+        `hstatus.SPV` is 1 and to HS-mode or U-mode otherwise.
     type: RW
     reset_value: UNDEFINED_LEGAL
   GVA:
     location: 6
     long_name: Guest Virtual Address
-    description:
-      - id: csr-hstatus-gva-behavior
-        normative: false
-        text: |
-          Written by hardware whenever a trap is taken into HS-mode:
+    description: |
+      Written by hardware whenever a trap is taken into HS-mode:
 
-          * Writes 1 when a trap causes a guest virtual address to be written into `stval` (`Breakpoint`, `* Address Misaligned`, `* Access Fault`, `* Page Fault`, or `* Guest-Page Fault`).
-          * Writes 0 otherwise
+      * Writes 1 when a trap causes a guest virtual address to be written into `stval` (`Breakpoint`, `* Address Misaligned`, `* Access Fault`, `* Page Fault`, or `* Guest-Page Fault`).
+      * Writes 0 otherwise
 
-          Does not affect execution.
+      Does not affect execution.
     type: RW
     reset_value: UNDEFINED_LEGAL
   VSBE:
     location: 5
     long_name: VS-mode Big Endian
     description:
-      - id: csr-hstatus-vgein-behavior
-        normative: false
-        text: |
+      - text: |
           Controls the endianness of data VS-mode (0 = little, 1 = big).
           Instructions are always little endian, regardless of the data setting.
 
-      - id: csr-hstatus-vgein-little-endian
-        normative: false
-        text: |
+      - text: |
           Since the CPU does not support big endian in VS-mode, this is hardwired to 0.
         when(): return VS_MODE_ENDIANNESS == "little";
 
-      - id: csr-hstatus-vgein-big-endian
-        normative: false
-        text: |
+      - text: |
           Since the CPU does not support little endian in VS-mode, this is hardwired to 1.
         when(): return VS_MODE_ENDIANNESS == "big";
+
     type(): |
       if (VS_MODE_ENDIANNESS == "dynamic") {
         # mode is mutable
diff --git a/spec/std/isa/csr/jvt.yaml b/spec/std/isa/csr/jvt.yaml
index 890bdfc06e..ad78377b18 100644
--- a/spec/std/isa/csr/jvt.yaml
+++ b/spec/std/isa/csr/jvt.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) Katherine Hsu
 # SPDX-License-Identifier: BSD-3-Clause-Clear
 
-# yaml-language-server: $schema=../../schemas/csr_schema.json
+# yaml-language-server: $schema=../../../schemas/csr_schema.json
 
 $schema: "csr_schema.json#"
 kind: csr
@@ -9,17 +9,12 @@ name: jvt
 long_name: Table Jump Base Vector and Control Register
 address: 0x017
 writable: true
-description:
-  - id: csr-jvt-purpose
-    normative: true
-    text: |
-      The `jvt` register is an XLEN-bit WARL read/write register that holds the jump table configuration,
-      consisting of the jump table base address (BASE) and the jump table mode (MODE).
-  - id: csr-jvt-architectural
-    normative: false
-    text: |
-      `jvt` CSR adds architectural state to the system software context (such as an OS process), therefore
-      must be saved/restored on context switches.
+description: |
+  The `jvt` register is an XLEN-bit WARL read/write register that holds the jump table configuration,
+  consisting of the jump table base address (BASE) and the jump table mode (MODE).
+
+  `jvt` CSR adds architectural state to the system software context (such as an OS process), therefore
+  must be saved/restored on context switches.
 priv_mode: U
 length: XLEN
 definedBy: Zcmt
diff --git a/spec/std/isa/csr/mstateen0.yaml b/spec/std/isa/csr/mstateen0.yaml
index e9fe5ba3df..d2c89d8fa0 100644
--- a/spec/std/isa/csr/mstateen0.yaml
+++ b/spec/std/isa/csr/mstateen0.yaml
@@ -11,61 +11,46 @@ address: 0x30C
 priv_mode: M
 length: 64
 writable: true
-description:
-  - id: csr-mstateen0-purpose
-    normative: true
-    text: |
-      Each bit of a `stateen` CSR controls less-privileged access to an extension’s state,
-      or an extension that was not deemed "worthy" of a full XS field in `sstatus` like the
-      FS and VS fields for the F and V extensions.
-  - id: csr-mstateen0-num-justification
-    normative: false
-    text: |
-      The number of registers provided at each level is four because it is believed that
-      4 * 64 = 256 bits for machine and hypervisor levels, and 4 * 32 = 128 bits for
-      supervisor level, will be adequate for many years to come, perhaps for as long as
-      the RISC-V ISA is in use.
-      The exact number four is an attempted compromise between providing too few bits on
-      the one hand and going overboard with CSRs that will never be used on the other.
-  - id: csr-mstateen0-scope
-    normative: true
-    text: |
-      The `stateen` registers at each level control access to state at all less-privileged
-      levels, but not at its own level.
-  - id: csr-mstateen0-effect
-    normative: true
-    text: |
-      When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute
-      in that privilege mode an instruction that implicitly updates the state without reading
-      it may or may not raise an illegal instruction or virtual instruction exception.
-      Such cases must be disambiguated by being explicitly specified one way or the other.
-      In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the
-      ISA extensions that introduce the controlled state.
-  - id: csr-mstateen0-bit-allocation
-    normative: true
-    text: |
-      For every bit with a defined purpose in an `sstateen` CSR, the same bit is defined in the matching
-      `mstateen` CSR to control access below machine level to the same state. The upper 32 bits of an
-      `mstateen` CSR (or for RV32, the corresponding high-half CSR) control access to state that is inherently
-      inaccessible to user level, so no corresponding enable bits in the supervisor-level `sstateen` CSR are
-      applicable. The intention is to allocate bits for this purpose starting at the most-significant end, bit 63,
-      through to bit 32, and then on to the next-higher `mstateen` CSR. If the rate that bits are being allocated
-      from the least-significant end for `sstateen` CSRs is sufficiently low, allocation from the most-significant
-      end of `mstateen` CSRs may be allowed to encroach on the lower 32 bits before jumping to the next-higher
-      `mstateen` CSR. In that case, the bit positions of "encroaching" bits will remain forever read-only zeros in
-      the matching `sstateen` CSRs.
-  - id: csr-mstateen0-zero
-    normative: true
-    text: |
-      For every bit in an `mstateen` CSR that is zero (whether read-only zero or set to zero),
-      the same bit appears as read-only zero in the matching `hstateen` and `sstateen` CSRs.
-  - id: csr-mstateen0-read-only
-    normative: true
-    text: |
-      A bit in a supervisor-level `sstateen` CSR cannot be read-only one unless the same bit is read-only one in the matching
-      `mstateen` CSR and, if it exists, in the matching `hstateen` CSR. A bit in an `hstateen` CSR cannot be read-only one unless
-      the same bit is read-only one in the matching `mstateen` CSR. Bit 63 of each `mstateen` CSR may be read-only zero only if
-      the hypervisor extension is not implemented and the matching supervisor-level `sstateen` CSR is all read-only zeros.
+description: |
+  Each bit of a `stateen` CSR controls less-privileged access to an extension’s state,
+  or an extension that was not deemed "worthy" of a full XS field in `sstatus` like the
+  FS and VS fields for the F and V extensions.
+
+  The number of registers provided at each level is four because it is believed that
+  4 * 64 = 256 bits for machine and hypervisor levels, and 4 * 32 = 128 bits for
+  supervisor level, will be adequate for many years to come, perhaps for as long as
+  the RISC-V ISA is in use.
+  The exact number four is an attempted compromise between providing too few bits on
+  the one hand and going overboard with CSRs that will never be used on the other.
+
+  The `stateen` registers at each level control access to state at all less-privileged
+  levels, but not at its own level.
+
+  When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute
+  in that privilege mode an instruction that implicitly updates the state without reading
+  it may or may not raise an illegal instruction or virtual instruction exception.
+  Such cases must be disambiguated by being explicitly specified one way or the other.
+  In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the
+  ISA extensions that introduce the controlled state.
+
+  For every bit with a defined purpose in an `sstateen` CSR, the same bit is defined in the matching
+  `mstateen` CSR to control access below machine level to the same state. The upper 32 bits of an
+  `mstateen` CSR (or for RV32, the corresponding high-half CSR) control access to state that is inherently
+  inaccessible to user level, so no corresponding enable bits in the supervisor-level `sstateen` CSR are
+  applicable. The intention is to allocate bits for this purpose starting at the most-significant end, bit 63,
+  through to bit 32, and then on to the next-higher `mstateen` CSR. If the rate that bits are being allocated
+  from the least-significant end for `sstateen` CSRs is sufficiently low, allocation from the most-significant
+  end of `mstateen` CSRs may be allowed to encroach on the lower 32 bits before jumping to the next-higher
+  `mstateen` CSR. In that case, the bit positions of "encroaching" bits will remain forever read-only zeros in
+  the matching `sstateen` CSRs.
+
+  For every bit in an `mstateen` CSR that is zero (whether read-only zero or set to zero),
+  the same bit appears as read-only zero in the matching `hstateen` and `sstateen` CSRs.
+
+  A bit in a supervisor-level `sstateen` CSR cannot be read-only one unless the same bit is read-only one in the matching
+  `mstateen` CSR and, if it exists, in the matching `hstateen` CSR. A bit in an `hstateen` CSR cannot be read-only one unless
+  the same bit is read-only one in the matching `mstateen` CSR. Bit 63 of each `mstateen` CSR may be read-only zero only if
+  the hypervisor extension is not implemented and the matching supervisor-level `sstateen` CSR is all read-only zeros.
 
 definedBy: Smstateen
 fields:
diff --git a/spec/std/isa/csr/mstateen0h.yaml b/spec/std/isa/csr/mstateen0h.yaml
index 1906a7f5c8..dbb96b7065 100644
--- a/spec/std/isa/csr/mstateen0h.yaml
+++ b/spec/std/isa/csr/mstateen0h.yaml
@@ -12,14 +12,11 @@ priv_mode: M
 length: 32
 base: 32
 writable: true
-description:
-  - id: csr-mstateen0h-purpose
-    normative: true
-    text: |
-      For RV64 harts, the Smstateen extension adds four new 64-bit CSRs at machine level: `mstateen0` (Machine State
-      Enable 0), `mstateen1`, `mstateen2`, and `mstateen3`. For RV32, the registers listed above are 32-bit, and for the
-      machine-level CSRs there is a corresponding set of high-half CSRs for the upper 32 bits of each register:
-      `mstateen0h`, `mstateen1h`, `mstateen2h`, `mstateen3h`.
+description: |
+  For RV64 harts, the Smstateen extension adds four new 64-bit CSRs at machine level: `mstateen0` (Machine State
+  Enable 0), `mstateen1`, `mstateen2`, and `mstateen3`. For RV32, the registers listed above are 32-bit, and for the
+  machine-level CSRs there is a corresponding set of high-half CSRs for the upper 32 bits of each register:
+  `mstateen0h`, `mstateen1h`, `mstateen2h`, `mstateen3h`.
 
 definedBy: Smstateen
 fields:
diff --git a/spec/std/isa/csr/mstateen1.yaml b/spec/std/isa/csr/mstateen1.yaml
index e83dfc9198..23745f136a 100644
--- a/spec/std/isa/csr/mstateen1.yaml
+++ b/spec/std/isa/csr/mstateen1.yaml
@@ -11,61 +11,46 @@ address: 0x30D
 priv_mode: M
 length: 64
 writable: true
-description:
-  - id: csr-mstateen1-purpose
-    normative: true
-    text: |
-      Each bit of a `stateen` CSR controls less-privileged access to an extension’s state,
-      or an extension that was not deemed "worthy" of a full XS field in `sstatus` like the
-      FS and VS fields for the F and V extensions.
-  - id: csr-mstateen1-num-justification
-    normative: false
-    text: |
-      The number of registers provided at each level is four because it is believed that
-      4 * 64 = 256 bits for machine and hypervisor levels, and 4 * 32 = 128 bits for
-      supervisor level, will be adequate for many years to come, perhaps for as long as
-      the RISC-V ISA is in use.
-      The exact number four is an attempted compromise between providing too few bits on
-      the one hand and going overboard with CSRs that will never be used on the other.
-  - id: csr-mstateen1-scope
-    normative: true
-    text: |
-      The `stateen` registers at each level control access to state at all less-privileged
-      levels, but not at its own level.
-  - id: csr-mstateen1-effect
-    normative: true
-    text: |
-      When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute
-      in that privilege mode an instruction that implicitly updates the state without reading
-      it may or may not raise an illegal instruction or virtual instruction exception.
-      Such cases must be disambiguated by being explicitly specified one way or the other.
-      In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the
-      ISA extensions that introduce the controlled state.
-  - id: csr-mstateen1-bit-allocation
-    normative: true
-    text: |
-      For every bit with a defined purpose in an `sstateen` CSR, the same bit is defined in the matching
-      `mstateen` CSR to control access below machine level to the same state. The upper 32 bits of an
-      `mstateen` CSR (or for RV32, the corresponding high-half CSR) control access to state that is inherently
-      inaccessible to user level, so no corresponding enable bits in the supervisor-level `sstateen` CSR are
-      applicable. The intention is to allocate bits for this purpose starting at the most-significant end, bit 63,
-      through to bit 32, and then on to the next-higher `mstateen` CSR. If the rate that bits are being allocated
-      from the least-significant end for `sstateen` CSRs is sufficiently low, allocation from the most-significant
-      end of `mstateen` CSRs may be allowed to encroach on the lower 32 bits before jumping to the next-higher
-      `mstateen` CSR. In that case, the bit positions of "encroaching" bits will remain forever read-only zeros in
-      the matching `sstateen` CSRs.
-  - id: csr-mstateen1-zero
-    normative: true
-    text: |
-      For every bit in an `mstateen` CSR that is zero (whether read-only zero or set to zero),
-      the same bit appears as read-only zero in the matching `hstateen` and `sstateen` CSRs.
-  - id: csr-mstateen1-read-only
-    normative: true
-    text: |
-      A bit in a supervisor-level `sstateen` CSR cannot be read-only one unless the same bit is read-only one in the matching
-      `mstateen` CSR and, if it exists, in the matching `hstateen` CSR. A bit in an `hstateen` CSR cannot be read-only one unless
-      the same bit is read-only one in the matching `mstateen` CSR. Bit 63 of each `mstateen` CSR may be read-only zero only if
-      the hypervisor extension is not implemented and the matching supervisor-level `sstateen` CSR is all read-only zeros.
+description: |
+  Each bit of a `stateen` CSR controls less-privileged access to an extension’s state,
+  or an extension that was not deemed "worthy" of a full XS field in `sstatus` like the
+  FS and VS fields for the F and V extensions.
+
+  The number of registers provided at each level is four because it is believed that
+  4 * 64 = 256 bits for machine and hypervisor levels, and 4 * 32 = 128 bits for
+  supervisor level, will be adequate for many years to come, perhaps for as long as
+  the RISC-V ISA is in use.
+  The exact number four is an attempted compromise between providing too few bits on
+  the one hand and going overboard with CSRs that will never be used on the other.
+
+  The `stateen` registers at each level control access to state at all less-privileged
+  levels, but not at its own level.
+
+  When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute
+  in that privilege mode an instruction that implicitly updates the state without reading
+  it may or may not raise an illegal instruction or virtual instruction exception.
+  Such cases must be disambiguated by being explicitly specified one way or the other.
+  In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the
+  ISA extensions that introduce the controlled state.
+
+  For every bit with a defined purpose in an `sstateen` CSR, the same bit is defined in the matching
+  `mstateen` CSR to control access below machine level to the same state. The upper 32 bits of an
+  `mstateen` CSR (or for RV32, the corresponding high-half CSR) control access to state that is inherently
+  inaccessible to user level, so no corresponding enable bits in the supervisor-level `sstateen` CSR are
+  applicable. The intention is to allocate bits for this purpose starting at the most-significant end, bit 63,
+  through to bit 32, and then on to the next-higher `mstateen` CSR. If the rate that bits are being allocated
+  from the least-significant end for `sstateen` CSRs is sufficiently low, allocation from the most-significant
+  end of `mstateen` CSRs may be allowed to encroach on the lower 32 bits before jumping to the next-higher
+  `mstateen` CSR. In that case, the bit positions of "encroaching" bits will remain forever read-only zeros in
+  the matching `sstateen` CSRs.
+
+  For every bit in an `mstateen` CSR that is zero (whether read-only zero or set to zero),
+  the same bit appears as read-only zero in the matching `hstateen` and `sstateen` CSRs.
+
+  A bit in a supervisor-level `sstateen` CSR cannot be read-only one unless the same bit is read-only one in the matching
+  `mstateen` CSR and, if it exists, in the matching `hstateen` CSR. A bit in an `hstateen` CSR cannot be read-only one unless
+  the same bit is read-only one in the matching `mstateen` CSR. Bit 63 of each `mstateen` CSR may be read-only zero only if
+  the hypervisor extension is not implemented and the matching supervisor-level `sstateen` CSR is all read-only zeros.
 
 definedBy: Smstateen
 fields:
diff --git a/spec/std/isa/csr/mstateen1h.yaml b/spec/std/isa/csr/mstateen1h.yaml
index ee82fcd9c4..acdf81b2e8 100644
--- a/spec/std/isa/csr/mstateen1h.yaml
+++ b/spec/std/isa/csr/mstateen1h.yaml
@@ -12,14 +12,11 @@ priv_mode: M
 length: 32
 base: 32
 writable: true
-description:
-  - id: csr-mstateen1h-purpose
-    normative: true
-    text: |
-      For RV64 harts, the Smstateen extension adds four new 64-bit CSRs at machine level: `mstateen0` (Machine State
-      Enable 0), `mstateen1`, `mstateen2`, and `mstateen3`. For RV32, the registers listed above are 32-bit, and for the
-      machine-level CSRs there is a corresponding set of high-half CSRs for the upper 32 bits of each register:
-      `mstateen0h`, `mstateen1h`, `mstateen2h`, `mstateen3h`.
+description: |
+  For RV64 harts, the Smstateen extension adds four new 64-bit CSRs at machine level: `mstateen0` (Machine State
+  Enable 0), `mstateen1`, `mstateen2`, and `mstateen3`. For RV32, the registers listed above are 32-bit, and for the
+  machine-level CSRs there is a corresponding set of high-half CSRs for the upper 32 bits of each register:
+  `mstateen0h`, `mstateen1h`, `mstateen2h`, `mstateen3h`.
 
 definedBy: Smstateen
 fields:
diff --git a/spec/std/isa/csr/mstateen2.yaml b/spec/std/isa/csr/mstateen2.yaml
index 4f34a31c40..4f08f74b05 100644
--- a/spec/std/isa/csr/mstateen2.yaml
+++ b/spec/std/isa/csr/mstateen2.yaml
@@ -11,61 +11,46 @@ address: 0x30E
 priv_mode: M
 length: 64
 writable: true
-description:
-  - id: csr-mstateen2-purpose
-    normative: true
-    text: |
-      Each bit of a `stateen` CSR controls less-privileged access to an extension’s state,
-      or an extension that was not deemed "worthy" of a full XS field in `sstatus` like the
-      FS and VS fields for the F and V extensions.
-  - id: csr-mstateen2-num-justification
-    normative: false
-    text: |
-      The number of registers provided at each level is four because it is believed that
-      4 * 64 = 256 bits for machine and hypervisor levels, and 4 * 32 = 128 bits for
-      supervisor level, will be adequate for many years to come, perhaps for as long as
-      the RISC-V ISA is in use.
-      The exact number four is an attempted compromise between providing too few bits on
-      the one hand and going overboard with CSRs that will never be used on the other.
-  - id: csr-mstateen2-scope
-    normative: true
-    text: |
-      The `stateen` registers at each level control access to state at all less-privileged
-      levels, but not at its own level.
-  - id: csr-mstateen2-effect
-    normative: true
-    text: |
-      When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute
-      in that privilege mode an instruction that implicitly updates the state without reading
-      it may or may not raise an illegal instruction or virtual instruction exception.
-      Such cases must be disambiguated by being explicitly specified one way or the other.
-      In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the
-      ISA extensions that introduce the controlled state.
-  - id: csr-mstateen2-bit-allocation
-    normative: true
-    text: |
-      For every bit with a defined purpose in an `sstateen` CSR, the same bit is defined in the matching
-      `mstateen` CSR to control access below machine level to the same state. The upper 32 bits of an
-      `mstateen` CSR (or for RV32, the corresponding high-half CSR) control access to state that is inherently
-      inaccessible to user level, so no corresponding enable bits in the supervisor-level `sstateen` CSR are
-      applicable. The intention is to allocate bits for this purpose starting at the most-significant end, bit 63,
-      through to bit 32, and then on to the next-higher `mstateen` CSR. If the rate that bits are being allocated
-      from the least-significant end for `sstateen` CSRs is sufficiently low, allocation from the most-significant
-      end of `mstateen` CSRs may be allowed to encroach on the lower 32 bits before jumping to the next-higher
-      `mstateen` CSR. In that case, the bit positions of "encroaching" bits will remain forever read-only zeros in
-      the matching `sstateen` CSRs.
-  - id: csr-mstateen2-zero
-    normative: true
-    text: |
-      For every bit in an `mstateen` CSR that is zero (whether read-only zero or set to zero),
-      the same bit appears as read-only zero in the matching `hstateen` and `sstateen` CSRs.
-  - id: csr-mstateen2-read-only
-    normative: true
-    text: |
-      A bit in a supervisor-level `sstateen` CSR cannot be read-only one unless the same bit is read-only one in the matching
-      `mstateen` CSR and, if it exists, in the matching `hstateen` CSR. A bit in an `hstateen` CSR cannot be read-only one unless
-      the same bit is read-only one in the matching `mstateen` CSR. Bit 63 of each `mstateen` CSR may be read-only zero only if
-      the hypervisor extension is not implemented and the matching supervisor-level `sstateen` CSR is all read-only zeros.
+description: |
+  Each bit of a `stateen` CSR controls less-privileged access to an extension’s state,
+  or an extension that was not deemed "worthy" of a full XS field in `sstatus` like the
+  FS and VS fields for the F and V extensions.
+
+  The number of registers provided at each level is four because it is believed that
+  4 * 64 = 256 bits for machine and hypervisor levels, and 4 * 32 = 128 bits for
+  supervisor level, will be adequate for many years to come, perhaps for as long as
+  the RISC-V ISA is in use.
+  The exact number four is an attempted compromise between providing too few bits on
+  the one hand and going overboard with CSRs that will never be used on the other.
+
+  The `stateen` registers at each level control access to state at all less-privileged
+  levels, but not at its own level.
+
+  When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute
+  in that privilege mode an instruction that implicitly updates the state without reading
+  it may or may not raise an illegal instruction or virtual instruction exception.
+  Such cases must be disambiguated by being explicitly specified one way or the other.
+  In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the
+  ISA extensions that introduce the controlled state.
+
+  For every bit with a defined purpose in an `sstateen` CSR, the same bit is defined in the matching
+  `mstateen` CSR to control access below machine level to the same state. The upper 32 bits of an
+  `mstateen` CSR (or for RV32, the corresponding high-half CSR) control access to state that is inherently
+  inaccessible to user level, so no corresponding enable bits in the supervisor-level `sstateen` CSR are
+  applicable. The intention is to allocate bits for this purpose starting at the most-significant end, bit 63,
+  through to bit 32, and then on to the next-higher `mstateen` CSR. If the rate that bits are being allocated
+  from the least-significant end for `sstateen` CSRs is sufficiently low, allocation from the most-significant
+  end of `mstateen` CSRs may be allowed to encroach on the lower 32 bits before jumping to the next-higher
+  `mstateen` CSR. In that case, the bit positions of "encroaching" bits will remain forever read-only zeros in
+  the matching `sstateen` CSRs.
+
+  For every bit in an `mstateen` CSR that is zero (whether read-only zero or set to zero),
+  the same bit appears as read-only zero in the matching `hstateen` and `sstateen` CSRs.
+
+  A bit in a supervisor-level `sstateen` CSR cannot be read-only one unless the same bit is read-only one in the matching
+  `mstateen` CSR and, if it exists, in the matching `hstateen` CSR. A bit in an `hstateen` CSR cannot be read-only one unless
+  the same bit is read-only one in the matching `mstateen` CSR. Bit 63 of each `mstateen` CSR may be read-only zero only if
+  the hypervisor extension is not implemented and the matching supervisor-level `sstateen` CSR is all read-only zeros.
 
 definedBy: Smstateen
 fields:
diff --git a/spec/std/isa/csr/mstateen2h.yaml b/spec/std/isa/csr/mstateen2h.yaml
index 906434ff00..cd9d020edb 100644
--- a/spec/std/isa/csr/mstateen2h.yaml
+++ b/spec/std/isa/csr/mstateen2h.yaml
@@ -12,14 +12,11 @@ priv_mode: M
 length: 32
 base: 32
 writable: true
-description:
-  - id: csr-mstateen2h-purpose
-    normative: true
-    text: |
-      For RV64 harts, the Smstateen extension adds four new 64-bit CSRs at machine level: `mstateen0` (Machine State
-      Enable 0), `mstateen1`, `mstateen2`, and `mstateen3`. For RV32, the registers listed above are 32-bit, and for the
-      machine-level CSRs there is a corresponding set of high-half CSRs for the upper 32 bits of each register:
-      `mstateen0h`, `mstateen1h`, `mstateen2h`, `mstateen3h`.
+description: |
+  For RV64 harts, the Smstateen extension adds four new 64-bit CSRs at machine level: `mstateen0` (Machine State
+  Enable 0), `mstateen1`, `mstateen2`, and `mstateen3`. For RV32, the registers listed above are 32-bit, and for the
+  machine-level CSRs there is a corresponding set of high-half CSRs for the upper 32 bits of each register:
+  `mstateen0h`, `mstateen1h`, `mstateen2h`, `mstateen3h`.
 
 definedBy: Smstateen
 fields:
diff --git a/spec/std/isa/csr/mstateen3.yaml b/spec/std/isa/csr/mstateen3.yaml
index 824b9c517a..eb4170d496 100644
--- a/spec/std/isa/csr/mstateen3.yaml
+++ b/spec/std/isa/csr/mstateen3.yaml
@@ -11,61 +11,46 @@ address: 0x30F
 priv_mode: M
 length: 64
 writable: true
-description:
-  - id: csr-mstateen3-purpose
-    normative: true
-    text: |
-      Each bit of a `stateen` CSR controls less-privileged access to an extension’s state,
-      or an extension that was not deemed "worthy" of a full XS field in `sstatus` like the
-      FS and VS fields for the F and V extensions.
-  - id: csr-mstateen3-num-justification
-    normative: false
-    text: |
-      The number of registers provided at each level is four because it is believed that
-      4 * 64 = 256 bits for machine and hypervisor levels, and 4 * 32 = 128 bits for
-      supervisor level, will be adequate for many years to come, perhaps for as long as
-      the RISC-V ISA is in use.
-      The exact number four is an attempted compromise between providing too few bits on
-      the one hand and going overboard with CSRs that will never be used on the other.
-  - id: csr-mstateen3-scope
-    normative: true
-    text: |
-      The `stateen` registers at each level control access to state at all less-privileged
-      levels, but not at its own level.
-  - id: csr-mstateen3-effect
-    normative: true
-    text: |
-      When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute
-      in that privilege mode an instruction that implicitly updates the state without reading
-      it may or may not raise an illegal instruction or virtual instruction exception.
-      Such cases must be disambiguated by being explicitly specified one way or the other.
-      In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the
-      ISA extensions that introduce the controlled state.
-  - id: csr-mstateen3-bit-allocation
-    normative: true
-    text: |
-      For every bit with a defined purpose in an `sstateen` CSR, the same bit is defined in the matching
-      `mstateen` CSR to control access below machine level to the same state. The upper 32 bits of an
-      `mstateen` CSR (or for RV32, the corresponding high-half CSR) control access to state that is inherently
-      inaccessible to user level, so no corresponding enable bits in the supervisor-level `sstateen` CSR are
-      applicable. The intention is to allocate bits for this purpose starting at the most-significant end, bit 63,
-      through to bit 32, and then on to the next-higher `mstateen` CSR. If the rate that bits are being allocated
-      from the least-significant end for `sstateen` CSRs is sufficiently low, allocation from the most-significant
-      end of `mstateen` CSRs may be allowed to encroach on the lower 32 bits before jumping to the next-higher
-      `mstateen` CSR. In that case, the bit positions of "encroaching" bits will remain forever read-only zeros in
-      the matching `sstateen` CSRs.
-  - id: csr-mstateen3-zero
-    normative: true
-    text: |
-      For every bit in an `mstateen` CSR that is zero (whether read-only zero or set to zero),
-      the same bit appears as read-only zero in the matching `hstateen` and `sstateen` CSRs.
-  - id: csr-mstateen3-read-only
-    normative: true
-    text: |
-      A bit in a supervisor-level `sstateen` CSR cannot be read-only one unless the same bit is read-only one in the matching
-      `mstateen` CSR and, if it exists, in the matching `hstateen` CSR. A bit in an `hstateen` CSR cannot be read-only one unless
-      the same bit is read-only one in the matching `mstateen` CSR. Bit 63 of each `mstateen` CSR may be read-only zero only if
-      the hypervisor extension is not implemented and the matching supervisor-level `sstateen` CSR is all read-only zeros.
+description: |
+  Each bit of a `stateen` CSR controls less-privileged access to an extension’s state,
+  or an extension that was not deemed "worthy" of a full XS field in `sstatus` like the
+  FS and VS fields for the F and V extensions.
+
+  The number of registers provided at each level is four because it is believed that
+  4 * 64 = 256 bits for machine and hypervisor levels, and 4 * 32 = 128 bits for
+  supervisor level, will be adequate for many years to come, perhaps for as long as
+  the RISC-V ISA is in use.
+  The exact number four is an attempted compromise between providing too few bits on
+  the one hand and going overboard with CSRs that will never be used on the other.
+
+  The `stateen` registers at each level control access to state at all less-privileged
+  levels, but not at its own level.
+
+  When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute
+  in that privilege mode an instruction that implicitly updates the state without reading
+  it may or may not raise an illegal instruction or virtual instruction exception.
+  Such cases must be disambiguated by being explicitly specified one way or the other.
+  In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the
+  ISA extensions that introduce the controlled state.
+
+  For every bit with a defined purpose in an `sstateen` CSR, the same bit is defined in the matching
+  `mstateen` CSR to control access below machine level to the same state. The upper 32 bits of an
+  `mstateen` CSR (or for RV32, the corresponding high-half CSR) control access to state that is inherently
+  inaccessible to user level, so no corresponding enable bits in the supervisor-level `sstateen` CSR are
+  applicable. The intention is to allocate bits for this purpose starting at the most-significant end, bit 63,
+  through to bit 32, and then on to the next-higher `mstateen` CSR. If the rate that bits are being allocated
+  from the least-significant end for `sstateen` CSRs is sufficiently low, allocation from the most-significant
+  end of `mstateen` CSRs may be allowed to encroach on the lower 32 bits before jumping to the next-higher
+  `mstateen` CSR. In that case, the bit positions of "encroaching" bits will remain forever read-only zeros in
+  the matching `sstateen` CSRs.
+
+  For every bit in an `mstateen` CSR that is zero (whether read-only zero or set to zero),
+  the same bit appears as read-only zero in the matching `hstateen` and `sstateen` CSRs.
+
+  A bit in a supervisor-level `sstateen` CSR cannot be read-only one unless the same bit is read-only one in the matching
+  `mstateen` CSR and, if it exists, in the matching `hstateen` CSR. A bit in an `hstateen` CSR cannot be read-only one unless
+  the same bit is read-only one in the matching `mstateen` CSR. Bit 63 of each `mstateen` CSR may be read-only zero only if
+  the hypervisor extension is not implemented and the matching supervisor-level `sstateen` CSR is all read-only zeros.
 
 definedBy: Smstateen
 fields:
diff --git a/spec/std/isa/csr/mstateen3h.yaml b/spec/std/isa/csr/mstateen3h.yaml
index 13c5bfa087..09c4e3d222 100644
--- a/spec/std/isa/csr/mstateen3h.yaml
+++ b/spec/std/isa/csr/mstateen3h.yaml
@@ -12,14 +12,11 @@ priv_mode: M
 length: 32
 base: 32
 writable: true
-description:
-  - id: csr-mstateen3h-purpose
-    normative: true
-    text: |
-      For RV64 harts, the Smstateen extension adds four new 64-bit CSRs at machine level: `mstateen0` (Machine State
-      Enable 0), `mstateen1`, `mstateen2`, and `mstateen3`. For RV32, the registers listed above are 32-bit, and for the
-      machine-level CSRs there is a corresponding set of high-half CSRs for the upper 32 bits of each register:
-      `mstateen0h`, `mstateen1h`, `mstateen2h`, `mstateen3h`.
+description: |
+  For RV64 harts, the Smstateen extension adds four new 64-bit CSRs at machine level: `mstateen0` (Machine State
+  Enable 0), `mstateen1`, `mstateen2`, and `mstateen3`. For RV32, the registers listed above are 32-bit, and for the
+  machine-level CSRs there is a corresponding set of high-half CSRs for the upper 32 bits of each register:
+  `mstateen0h`, `mstateen1h`, `mstateen2h`, `mstateen3h`.
 
 definedBy: Smstateen
 fields:
diff --git a/spec/std/isa/csr/satp.yaml b/spec/std/isa/csr/satp.yaml
index 66518f558b..39bf6cd726 100644
--- a/spec/std/isa/csr/satp.yaml
+++ b/spec/std/isa/csr/satp.yaml
@@ -45,39 +45,28 @@ fields:
     reset_value(): |
       return 0;
     sw_write(csr_value): |
-      if (SATP_MODE_BARE && (csr_value.MODE == 0)) {
-        # In Bare, ASID and PPN must be zero, else the entire write is ignored
-        if (csr_value.ASID == 0 && csr_value.PPN == 0) {
-          if (CSR[satp].MODE != 0) {
-            # changes *to* Bare mode take effect immediately without needing sfence.vma
-            # thus, an implicit sfence.vma occurs now
-            VmaOrderType order_type;
-            order_type.global = true;
-            order_pgtbl_writes_before_vmafence(order_type);
-
-            invalidate_translations(order_type);
-
-            order_pgtbl_reads_after_vmafence(order_type);
+      if (SATP_MODE_BARE) {
+        if (csr_value.MODE == 0) {
+          # In Bare, ASID and PPN must be zero, else the entire write is ignored
+          if (csr_value.ASID == 0 && csr_value.PPN == 0) {
+            if (CSR[satp].MODE != 0) {
+              # changes *to* Bare mode take effect immediately without needing sfence.vma
+              # thus, an implicit sfence.vma occurs now
+              VmaOrderType order_type;
+              order_type.global = true;
+              order_pgtbl_writes_before_vmafence(order_type);
+
+              invalidate_translations(order_type);
+
+              order_pgtbl_reads_after_vmafence(order_type);
+            }
+            return csr_value.MODE;
+          } else {
+            return UNDEFINED_LEGAL_DETERMINISTIC;
           }
-          return csr_value.MODE;
-        } else {
-          return UNDEFINED_LEGAL_DETERMINISTIC;
         }
       }
-      else if (implemented?(ExtensionName::Sv32) && csr_value.MODE == 1) {
-        if (CSR[satp].MODE == 0) {
-          # changes *from* Bare mode take effect immediately without needing sfence.vma
-          # thus, an implicit sfence.vma occurs now
-          VmaOrderType order_type;
-          order_type.global = true;
-          order_pgtbl_writes_before_vmafence(order_type);
-
-          invalidate_translations(order_type);
-
-          order_pgtbl_reads_after_vmafence(order_type);
-        }
-        return csr_value.MODE;
-      }else if (implemented?(ExtensionName::Sv39) && csr_value.MODE == 8) {
+      else if (implemented?(ExtensionName::Sv39) && csr_value.MODE == 8) {
         if (CSR[satp].MODE == 0) {
           # changes *from* Bare mode take effect immediately without needing sfence.vma
           # thus, an implicit sfence.vma occurs now
diff --git a/spec/std/isa/csr/sstateen0.yaml b/spec/std/isa/csr/sstateen0.yaml
index b9639bc1f0..fc606c9016 100644
--- a/spec/std/isa/csr/sstateen0.yaml
+++ b/spec/std/isa/csr/sstateen0.yaml
@@ -11,62 +11,47 @@ address: 0x10C
 priv_mode: S
 length: MXLEN
 writable: true
-description:
-  - id: csr-sstateen0-purpose
-    normative: true
-    text: |
-      Each bit of a `stateen` CSR controls less-privileged access to an extension’s state,
-      for an extension that was not deemed "worthy" of a full XS field in `sstatus` like the
-      FS and VS fields for the F and V extensions.
-  - id: csr-sstateen0-num-justification
-    normative: false
-    text: |
-      The number of registers provided at each level is four because it is believed that
-      4 * 64 = 256 bits for machine and hypervisor levels, and 4 * 32 = 128 bits for
-      supervisor level, will be adequate for many years to come, perhaps for as long as
-      the RISC-V ISA is in use.
-      The exact number four is an attempted compromise between providing too few bits on
-      the one hand and going overboard with CSRs that will never be used on the other.
-  - id: csr-sstateen0-scope
-    normative: true
-    text: |
-      The `stateen` registers at each level control access to state at all less-privileged
-      levels, but not at its own level.
-  - id: csr-sstateen0-effect
-    normative: true
-    text: |
-      When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute
-      in that privilege mode an instruction that implicitly updates the state without reading
-      it may or may not raise an illegal instruction or virtual instruction exception.
-      Such cases must be disambiguated by being explicitly specified one way or the other.
-      In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the
-      ISA extensions that introduce the controlled state.
-  - id: csr-sstateen0-bit-allocation
-    normative: true
-    text: |
-      For every bit with a defined purpose in an `sstateen` CSR, the same bit is defined in the matching
-      `mstateen` CSR to control access below machine level to the same state. The upper 32 bits of an
-      `mstateen` CSR (or for RV32, the corresponding high-half CSR) control access to state that is inherently
-      inaccessible to user level, so no corresponding enable bits in the supervisor-level `sstateen` CSR are
-      applicable. The intention is to allocate bits for this purpose starting at the most-significant end, bit 63,
-      through to bit 32, and then on to the next-higher `mstateen` CSR. If the rate that bits are being allocated
-      from the least-significant end for `sstateen` CSRs is sufficiently low, allocation from the most-significant
-      end of `mstateen` CSRs may be allowed to encroach on the lower 32 bits before jumping to the next-higher
-      `mstateen` CSR. In that case, the bit positions of "encroaching" bits will remain forever read-only zeros in
-      the matching `sstateen` CSRs.
-  - id: csr-sstateen0-zero
-    normative: true
-    text: |
-      For every bit in an `mstateen` CSR that is zero (whether read-only zero or set to zero),
-      the same bit appears as read-only zero in the matching `hstateen` and `sstateen` CSRs.
-      For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero),
-      the same bit appears as read-only zero in `sstateen` when accessed in VS-mode.
-  - id: csr-sstateen0-read-only
-    normative: true
-    text: |
-      A bit in a supervisor-level `sstateen` CSR cannot be read-only one unless the same bit is read-only one in the matching
-      `mstateen` CSR and, if it exists, in the matching `hstateen` CSR. Bit 63 of each `mstateen` CSR may be read-only zero
-      only if the hypervisor extension is not implemented and the matching supervisor-level `sstateen` CSR is all read-only zeros.
+description: |
+  Each bit of a `stateen` CSR controls less-privileged access to an extension’s state,
+  for an extension that was not deemed "worthy" of a full XS field in `sstatus` like the
+  FS and VS fields for the F and V extensions.
+
+  The number of registers provided at each level is four because it is believed that
+  4 * 64 = 256 bits for machine and hypervisor levels, and 4 * 32 = 128 bits for
+  supervisor level, will be adequate for many years to come, perhaps for as long as
+  the RISC-V ISA is in use.
+  The exact number four is an attempted compromise between providing too few bits on
+  the one hand and going overboard with CSRs that will never be used on the other.
+
+  The `stateen` registers at each level control access to state at all less-privileged
+  levels, but not at its own level.
+
+  When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute
+  in that privilege mode an instruction that implicitly updates the state without reading
+  it may or may not raise an illegal instruction or virtual instruction exception.
+  Such cases must be disambiguated by being explicitly specified one way or the other.
+  In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the
+  ISA extensions that introduce the controlled state.
+
+  For every bit with a defined purpose in an `sstateen` CSR, the same bit is defined in the matching
+  `mstateen` CSR to control access below machine level to the same state. The upper 32 bits of an
+  `mstateen` CSR (or for RV32, the corresponding high-half CSR) control access to state that is inherently
+  inaccessible to user level, so no corresponding enable bits in the supervisor-level `sstateen` CSR are
+  applicable. The intention is to allocate bits for this purpose starting at the most-significant end, bit 63,
+  through to bit 32, and then on to the next-higher `mstateen` CSR. If the rate that bits are being allocated
+  from the least-significant end for `sstateen` CSRs is sufficiently low, allocation from the most-significant
+  end of `mstateen` CSRs may be allowed to encroach on the lower 32 bits before jumping to the next-higher
+  `mstateen` CSR. In that case, the bit positions of "encroaching" bits will remain forever read-only zeros in
+  the matching `sstateen` CSRs.
+
+  For every bit in an `mstateen` CSR that is zero (whether read-only zero or set to zero),
+  the same bit appears as read-only zero in the matching `hstateen` and `sstateen` CSRs.
+  For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero),
+  the same bit appears as read-only zero in `sstateen` when accessed in VS-mode.
+
+  A bit in a supervisor-level `sstateen` CSR cannot be read-only one unless the same bit is read-only one in the matching
+  `mstateen` CSR and, if it exists, in the matching `hstateen` CSR. Bit 63 of each `mstateen` CSR may be read-only zero
+  only if the hypervisor extension is not implemented and the matching supervisor-level `sstateen` CSR is all read-only zeros.
 
 definedBy:
   allOf:
diff --git a/spec/std/isa/csr/sstateen1.yaml b/spec/std/isa/csr/sstateen1.yaml
index df26666abc..34c2347ff9 100644
--- a/spec/std/isa/csr/sstateen1.yaml
+++ b/spec/std/isa/csr/sstateen1.yaml
@@ -11,62 +11,47 @@ address: 0x10D
 priv_mode: S
 length: MXLEN
 writable: true
-description:
-  - id: csr-sstateen1-purpose
-    normative: true
-    text: |
-      Each bit of a `stateen` CSR controls less-privileged access to an extension’s state,
-      for an extension that was not deemed "worthy" of a full XS field in `sstatus` like the
-      FS and VS fields for the F and V extensions.
-  - id: csr-sstateen1-num-justification
-    normative: false
-    text: |
-      The number of registers provided at each level is four because it is believed that
-      4 * 64 = 256 bits for machine and hypervisor levels, and 4 * 32 = 128 bits for
-      supervisor level, will be adequate for many years to come, perhaps for as long as
-      the RISC-V ISA is in use.
-      The exact number four is an attempted compromise between providing too few bits on
-      the one hand and going overboard with CSRs that will never be used on the other.
-  - id: csr-sstateen1-scope
-    normative: true
-    text: |
-      The `stateen` registers at each level control access to state at all less-privileged
-      levels, but not at its own level.
-  - id: csr-sstateen1-effect
-    normative: true
-    text: |
-      When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute
-      in that privilege mode an instruction that implicitly updates the state without reading
-      it may or may not raise an illegal instruction or virtual instruction exception.
-      Such cases must be disambiguated by being explicitly specified one way or the other.
-      In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the
-      ISA extensions that introduce the controlled state.
-  - id: csr-sstateen1-bit-allocation
-    normative: true
-    text: |
-      For every bit with a defined purpose in an `sstateen` CSR, the same bit is defined in the matching
-      `mstateen` CSR to control access below machine level to the same state. The upper 32 bits of an
-      `mstateen` CSR (or for RV32, the corresponding high-half CSR) control access to state that is inherently
-      inaccessible to user level, so no corresponding enable bits in the supervisor-level `sstateen` CSR are
-      applicable. The intention is to allocate bits for this purpose starting at the most-significant end, bit 63,
-      through to bit 32, and then on to the next-higher `mstateen` CSR. If the rate that bits are being allocated
-      from the least-significant end for `sstateen` CSRs is sufficiently low, allocation from the most-significant
-      end of `mstateen` CSRs may be allowed to encroach on the lower 32 bits before jumping to the next-higher
-      `mstateen` CSR. In that case, the bit positions of "encroaching" bits will remain forever read-only zeros in
-      the matching `sstateen` CSRs.
-  - id: csr-sstateen1-zero
-    normative: true
-    text: |
-      For every bit in an `mstateen` CSR that is zero (whether read-only zero or set to zero),
-      the same bit appears as read-only zero in the matching `hstateen` and `sstateen` CSRs.
-      For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero),
-      the same bit appears as read-only zero in `sstateen` when accessed in VS-mode.
-  - id: csr-sstateen1-read-only
-    normative: true
-    text: |
-      A bit in a supervisor-level `sstateen` CSR cannot be read-only one unless the same bit is read-only one in the matching
-      `mstateen` CSR and, if it exists, in the matching `hstateen` CSR. Bit 63 of each `mstateen` CSR may be read-only zero
-      only if the hypervisor extension is not implemented and the matching supervisor-level `sstateen` CSR is all read-only zeros.
+description: |
+  Each bit of a `stateen` CSR controls less-privileged access to an extension’s state,
+  for an extension that was not deemed "worthy" of a full XS field in `sstatus` like the
+  FS and VS fields for the F and V extensions.
+
+  The number of registers provided at each level is four because it is believed that
+  4 * 64 = 256 bits for machine and hypervisor levels, and 4 * 32 = 128 bits for
+  supervisor level, will be adequate for many years to come, perhaps for as long as
+  the RISC-V ISA is in use.
+  The exact number four is an attempted compromise between providing too few bits on
+  the one hand and going overboard with CSRs that will never be used on the other.
+
+  The `stateen` registers at each level control access to state at all less-privileged
+  levels, but not at its own level.
+
+  When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute
+  in that privilege mode an instruction that implicitly updates the state without reading
+  it may or may not raise an illegal instruction or virtual instruction exception.
+  Such cases must be disambiguated by being explicitly specified one way or the other.
+  In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the
+  ISA extensions that introduce the controlled state.
+
+  For every bit with a defined purpose in an `sstateen` CSR, the same bit is defined in the matching
+  `mstateen` CSR to control access below machine level to the same state. The upper 32 bits of an
+  `mstateen` CSR (or for RV32, the corresponding high-half CSR) control access to state that is inherently
+  inaccessible to user level, so no corresponding enable bits in the supervisor-level `sstateen` CSR are
+  applicable. The intention is to allocate bits for this purpose starting at the most-significant end, bit 63,
+  through to bit 32, and then on to the next-higher `mstateen` CSR. If the rate that bits are being allocated
+  from the least-significant end for `sstateen` CSRs is sufficiently low, allocation from the most-significant
+  end of `mstateen` CSRs may be allowed to encroach on the lower 32 bits before jumping to the next-higher
+  `mstateen` CSR. In that case, the bit positions of "encroaching" bits will remain forever read-only zeros in
+  the matching `sstateen` CSRs.
+
+  For every bit in an `mstateen` CSR that is zero (whether read-only zero or set to zero),
+  the same bit appears as read-only zero in the matching `hstateen` and `sstateen` CSRs.
+  For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero),
+  the same bit appears as read-only zero in `sstateen` when accessed in VS-mode.
+
+  A bit in a supervisor-level `sstateen` CSR cannot be read-only one unless the same bit is read-only one in the matching
+  `mstateen` CSR and, if it exists, in the matching `hstateen` CSR. Bit 63 of each `mstateen` CSR may be read-only zero
+  only if the hypervisor extension is not implemented and the matching supervisor-level `sstateen` CSR is all read-only zeros.
 
 definedBy:
   allOf:
diff --git a/spec/std/isa/csr/sstateen2.yaml b/spec/std/isa/csr/sstateen2.yaml
index a362131eea..66b189a9d2 100644
--- a/spec/std/isa/csr/sstateen2.yaml
+++ b/spec/std/isa/csr/sstateen2.yaml
@@ -11,62 +11,47 @@ address: 0x10E
 priv_mode: S
 length: MXLEN
 writable: true
-description:
-  - id: csr-sstateen2-purpose
-    normative: true
-    text: |
-      Each bit of a `stateen` CSR controls less-privileged access to an extension’s state,
-      for an extension that was not deemed "worthy" of a full XS field in `sstatus` like the
-      FS and VS fields for the F and V extensions.
-  - id: csr-sstateen2-num-justification
-    normative: false
-    text: |
-      The number of registers provided at each level is four because it is believed that
-      4 * 64 = 256 bits for machine and hypervisor levels, and 4 * 32 = 128 bits for
-      supervisor level, will be adequate for many years to come, perhaps for as long as
-      the RISC-V ISA is in use.
-      The exact number four is an attempted compromise between providing too few bits on
-      the one hand and going overboard with CSRs that will never be used on the other.
-  - id: csr-sstateen2-scope
-    normative: true
-    text: |
-      The `stateen` registers at each level control access to state at all less-privileged
-      levels, but not at its own level.
-  - id: csr-sstateen2-effect
-    normative: true
-    text: |
-      When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute
-      in that privilege mode an instruction that implicitly updates the state without reading
-      it may or may not raise an illegal instruction or virtual instruction exception.
-      Such cases must be disambiguated by being explicitly specified one way or the other.
-      In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the
-      ISA extensions that introduce the controlled state.
-  - id: csr-sstateen2-bit-allocation
-    normative: true
-    text: |
-      For every bit with a defined purpose in an `sstateen` CSR, the same bit is defined in the matching
-      `mstateen` CSR to control access below machine level to the same state. The upper 32 bits of an
-      `mstateen` CSR (or for RV32, the corresponding high-half CSR) control access to state that is inherently
-      inaccessible to user level, so no corresponding enable bits in the supervisor-level `sstateen` CSR are
-      applicable. The intention is to allocate bits for this purpose starting at the most-significant end, bit 63,
-      through to bit 32, and then on to the next-higher `mstateen` CSR. If the rate that bits are being allocated
-      from the least-significant end for `sstateen` CSRs is sufficiently low, allocation from the most-significant
-      end of `mstateen` CSRs may be allowed to encroach on the lower 32 bits before jumping to the next-higher
-      `mstateen` CSR. In that case, the bit positions of "encroaching" bits will remain forever read-only zeros in
-      the matching `sstateen` CSRs.
-  - id: csr-sstateen2-zero
-    normative: true
-    text: |
-      For every bit in an `mstateen` CSR that is zero (whether read-only zero or set to zero),
-      the same bit appears as read-only zero in the matching `hstateen` and `sstateen` CSRs.
-      For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero),
-      the same bit appears as read-only zero in `sstateen` when accessed in VS-mode.
-  - id: csr-sstateen2-read-only
-    normative: true
-    text: |
-      A bit in a supervisor-level `sstateen` CSR cannot be read-only one unless the same bit is read-only one in the matching
-      `mstateen` CSR and, if it exists, in the matching `hstateen` CSR. Bit 63 of each `mstateen` CSR may be read-only zero
-      only if the hypervisor extension is not implemented and the matching supervisor-level `sstateen` CSR is all read-only zeros.
+description: |
+  Each bit of a `stateen` CSR controls less-privileged access to an extension’s state,
+  for an extension that was not deemed "worthy" of a full XS field in `sstatus` like the
+  FS and VS fields for the F and V extensions.
+
+  The number of registers provided at each level is four because it is believed that
+  4 * 64 = 256 bits for machine and hypervisor levels, and 4 * 32 = 128 bits for
+  supervisor level, will be adequate for many years to come, perhaps for as long as
+  the RISC-V ISA is in use.
+  The exact number four is an attempted compromise between providing too few bits on
+  the one hand and going overboard with CSRs that will never be used on the other.
+
+  The `stateen` registers at each level control access to state at all less-privileged
+  levels, but not at its own level.
+
+  When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute
+  in that privilege mode an instruction that implicitly updates the state without reading
+  it may or may not raise an illegal instruction or virtual instruction exception.
+  Such cases must be disambiguated by being explicitly specified one way or the other.
+  In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the
+  ISA extensions that introduce the controlled state.
+
+  For every bit with a defined purpose in an `sstateen` CSR, the same bit is defined in the matching
+  `mstateen` CSR to control access below machine level to the same state. The upper 32 bits of an
+  `mstateen` CSR (or for RV32, the corresponding high-half CSR) control access to state that is inherently
+  inaccessible to user level, so no corresponding enable bits in the supervisor-level `sstateen` CSR are
+  applicable. The intention is to allocate bits for this purpose starting at the most-significant end, bit 63,
+  through to bit 32, and then on to the next-higher `mstateen` CSR. If the rate that bits are being allocated
+  from the least-significant end for `sstateen` CSRs is sufficiently low, allocation from the most-significant
+  end of `mstateen` CSRs may be allowed to encroach on the lower 32 bits before jumping to the next-higher
+  `mstateen` CSR. In that case, the bit positions of "encroaching" bits will remain forever read-only zeros in
+  the matching `sstateen` CSRs.
+
+  For every bit in an `mstateen` CSR that is zero (whether read-only zero or set to zero),
+  the same bit appears as read-only zero in the matching `hstateen` and `sstateen` CSRs.
+  For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero),
+  the same bit appears as read-only zero in `sstateen` when accessed in VS-mode.
+
+  A bit in a supervisor-level `sstateen` CSR cannot be read-only one unless the same bit is read-only one in the matching
+  `mstateen` CSR and, if it exists, in the matching `hstateen` CSR. Bit 63 of each `mstateen` CSR may be read-only zero
+  only if the hypervisor extension is not implemented and the matching supervisor-level `sstateen` CSR is all read-only zeros.
 
 definedBy:
   allOf:
diff --git a/spec/std/isa/csr/sstateen3.yaml b/spec/std/isa/csr/sstateen3.yaml
index 963016ef56..4f5834b068 100644
--- a/spec/std/isa/csr/sstateen3.yaml
+++ b/spec/std/isa/csr/sstateen3.yaml
@@ -11,62 +11,47 @@ address: 0x10F
 priv_mode: S
 length: MXLEN
 writable: true
-description:
-  - id: csr-sstateen3-purpose
-    normative: true
-    text: |
-      Each bit of a `stateen` CSR controls less-privileged access to an extension’s state,
-      for an extension that was not deemed "worthy" of a full XS field in `sstatus` like the
-      FS and VS fields for the F and V extensions.
-  - id: csr-sstateen3-num-justification
-    normative: false
-    text: |
-      The number of registers provided at each level is four because it is believed that
-      4 * 64 = 256 bits for machine and hypervisor levels, and 4 * 32 = 128 bits for
-      supervisor level, will be adequate for many years to come, perhaps for as long as
-      the RISC-V ISA is in use.
-      The exact number four is an attempted compromise between providing too few bits on
-      the one hand and going overboard with CSRs that will never be used on the other.
-  - id: csr-sstateen3-scope
-    normative: true
-    text: |
-      The `stateen` registers at each level control access to state at all less-privileged
-      levels, but not at its own level.
-  - id: csr-sstateen3-effect
-    normative: true
-    text: |
-      When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute
-      in that privilege mode an instruction that implicitly updates the state without reading
-      it may or may not raise an illegal instruction or virtual instruction exception.
-      Such cases must be disambiguated by being explicitly specified one way or the other.
-      In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the
-      ISA extensions that introduce the controlled state.
-  - id: csr-sstateen3-bit-allocation
-    normative: true
-    text: |
-      For every bit with a defined purpose in an `sstateen` CSR, the same bit is defined in the matching
-      `mstateen` CSR to control access below machine level to the same state. The upper 32 bits of an
-      `mstateen` CSR (or for RV32, the corresponding high-half CSR) control access to state that is inherently
-      inaccessible to user level, so no corresponding enable bits in the supervisor-level `sstateen` CSR are
-      applicable. The intention is to allocate bits for this purpose starting at the most-significant end, bit 63,
-      through to bit 32, and then on to the next-higher `mstateen` CSR. If the rate that bits are being allocated
-      from the least-significant end for `sstateen` CSRs is sufficiently low, allocation from the most-significant
-      end of `mstateen` CSRs may be allowed to encroach on the lower 32 bits before jumping to the next-higher
-      `mstateen` CSR. In that case, the bit positions of "encroaching" bits will remain forever read-only zeros in
-      the matching `sstateen` CSRs.
-  - id: csr-sstateen3-zero
-    normative: true
-    text: |
-      For every bit in an `mstateen` CSR that is zero (whether read-only zero or set to zero),
-      the same bit appears as read-only zero in the matching `hstateen` and `sstateen` CSRs.
-      For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero),
-      the same bit appears as read-only zero in `sstateen` when accessed in VS-mode.
-  - id: csr-sstateen3-read-only
-    normative: true
-    text: |
-      A bit in a supervisor-level `sstateen` CSR cannot be read-only one unless the same bit is read-only one in the matching
-      `mstateen` CSR and, if it exists, in the matching `hstateen` CSR. Bit 63 of each `mstateen` CSR may be read-only zero
-      only if the hypervisor extension is not implemented and the matching supervisor-level `sstateen` CSR is all read-only zeros.
+description: |
+  Each bit of a `stateen` CSR controls less-privileged access to an extension’s state,
+  for an extension that was not deemed "worthy" of a full XS field in `sstatus` like the
+  FS and VS fields for the F and V extensions.
+
+  The number of registers provided at each level is four because it is believed that
+  4 * 64 = 256 bits for machine and hypervisor levels, and 4 * 32 = 128 bits for
+  supervisor level, will be adequate for many years to come, perhaps for as long as
+  the RISC-V ISA is in use.
+  The exact number four is an attempted compromise between providing too few bits on
+  the one hand and going overboard with CSRs that will never be used on the other.
+
+  The `stateen` registers at each level control access to state at all less-privileged
+  levels, but not at its own level.
+
+  When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute
+  in that privilege mode an instruction that implicitly updates the state without reading
+  it may or may not raise an illegal instruction or virtual instruction exception.
+  Such cases must be disambiguated by being explicitly specified one way or the other.
+  In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the
+  ISA extensions that introduce the controlled state.
+
+  For every bit with a defined purpose in an `sstateen` CSR, the same bit is defined in the matching
+  `mstateen` CSR to control access below machine level to the same state. The upper 32 bits of an
+  `mstateen` CSR (or for RV32, the corresponding high-half CSR) control access to state that is inherently
+  inaccessible to user level, so no corresponding enable bits in the supervisor-level `sstateen` CSR are
+  applicable. The intention is to allocate bits for this purpose starting at the most-significant end, bit 63,
+  through to bit 32, and then on to the next-higher `mstateen` CSR. If the rate that bits are being allocated
+  from the least-significant end for `sstateen` CSRs is sufficiently low, allocation from the most-significant
+  end of `mstateen` CSRs may be allowed to encroach on the lower 32 bits before jumping to the next-higher
+  `mstateen` CSR. In that case, the bit positions of "encroaching" bits will remain forever read-only zeros in
+  the matching `sstateen` CSRs.
+
+  For every bit in an `mstateen` CSR that is zero (whether read-only zero or set to zero),
+  the same bit appears as read-only zero in the matching `hstateen` and `sstateen` CSRs.
+  For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero),
+  the same bit appears as read-only zero in `sstateen` when accessed in VS-mode.
+
+  A bit in a supervisor-level `sstateen` CSR cannot be read-only one unless the same bit is read-only one in the matching
+  `mstateen` CSR and, if it exists, in the matching `hstateen` CSR. Bit 63 of each `mstateen` CSR may be read-only zero
+  only if the hypervisor extension is not implemented and the matching supervisor-level `sstateen` CSR is all read-only zeros.
 
 definedBy:
   allOf:
diff --git a/spec/std/isa/ext/Svrsw60t59b.yaml b/spec/std/isa/ext/Svrsw60t59b.yaml
deleted file mode 100644
index 6224525abd..0000000000
--- a/spec/std/isa/ext/Svrsw60t59b.yaml
+++ /dev/null
@@ -1,38 +0,0 @@
-# Copyright (c) Jordan Carlin, Harvey Mudd College.
-# SPDX-License-Identifier: BSD-3-Clause-Clear
-
-# yaml-language-server: $schema=../../../schemas/ext_schema.json
-
-$schema: "ext_schema.json#"
-kind: extension
-name: Svrsw60t59b
-long_name: PTE Reserved-for-Software Bits 60-59
-type: privileged
-description: |
-  == "Svrsw60t59b" Extension for PTE Reserved-for-Software Bits 60-59, Version 1.0
-
-  If the Svrsw60t59b extension is implemented, then bits 60-59 of the page table
-  entries (PTEs) are reserved for use by supervisor software and are ignored by
-  the implementation.
-
-  If the Hypervisor (H) extension is also implemented, then bits 60-59 of the
-  G-stage PTEs are reserved for use by supervisor software and are ignored by the
-  implementation.
-
-  The Svrsw60t59b extension depends on Sv39.
-
-  [NOTE]
-  ====
-  Operating systems frequently use reserved bits within PTEs to store metadata for
-  advanced memory management features. Embedding these metadata bits directly within
-  the PTEs allows for fast access with minimal overhead, avoiding costly lookups in
-  auxiliary data structures. By default, Sv39 and Sv39x4 require a page fault and
-  a guest-page fault exception, respectively, to be raised if bits 60-59 are not
-  zero.
-  ====
-versions:
-  - version: "1.0.0"
-    state: ratified
-    ratification_date: 2025-08
-    requires:
-      name: Sv39
diff --git a/spec/std/isa/inst/D/fadd.d.yaml b/spec/std/isa/inst/D/fadd.d.yaml
index ec0e4615da..1c3e2f276f 100644
--- a/spec/std/isa/inst/D/fadd.d.yaml
+++ b/spec/std/isa/inst/D/fadd.d.yaml
@@ -7,12 +7,9 @@ $schema: inst_schema.json#
 kind: instruction
 name: fadd.d
 long_name: Floating-Point Add Double-Precision
-description:
-  - id: inst-fadd.d-behaviour
-    normative: false
-    text: |
-      The `fadd.d` instruction is analogous to `fadd.s` and performs double-precision floating-point addition between
-      `fs1` and `fs2` and writes the final result to `fd`.
+description: |
+  The `fadd.d` instruction is analogous to `fadd.s` and performs double-precision floating-point addition of
+  `fs1` and `fs2` and writes the final result to `fd`.
 definedBy: D
 assembly: fd, fs1, fs2, rm
 encoding:
diff --git a/spec/std/isa/inst/D/fclass.d.yaml b/spec/std/isa/inst/D/fclass.d.yaml
index 4c77620aa7..9c012c60b1 100644
--- a/spec/std/isa/inst/D/fclass.d.yaml
+++ b/spec/std/isa/inst/D/fclass.d.yaml
@@ -7,32 +7,29 @@ $schema: inst_schema.json#
 kind: instruction
 name: fclass.d
 long_name: Floating-Point Classify Double-Precision
-description:
-  - id: inst-fclass.d-behaviour
-    normative: false
-    text: |
-      The `fclass.d` instruction is defined analogously to its single-precision counterpart, but operates on double-precision
-      operands. It examines the value in floating-point register `fs1` and writes to integer register `xd` a 10-bit mask that
-      indicates the class of the floating point number.
+description: |
+  The `fclass.d` instruction is defined analogously to its single-precision counterpart, but operates on double-precision
+  operands. It examines the value in floating-point register `fs1` and writes to integer register `xd` a 10-bit mask that
+  indicates the class of the floating point number.
 
-      The format of the mask is described in the table below. The corresponding bit in `xd` will be set if the property
-      is true and clear otherwise. All other bits in `xd` are cleared. Note that exactly one bit in `xd` will be set.
+  The format of the mask is described in the table below. The corresponding bit in `xd` will be set if the property
+  is true and clear otherwise. All other bits in `xd` are cleared. Note that exactly one bit in `xd` will be set.
 
-      .Format of result of `fclass` instruction.
-      [%autowidth,float="center",align="center",cols="^,<",options="header",]
-      |===
-      |_xd_ bit |Meaning
-      |0 |_fs1_ is latexmath:[$-\infty$].
-      |1 |_fs1_ is a negative normal number.
-      |2 |_fs1_ is a negative subnormal number.
-      |3 |_fs1_ is latexmath:[$-0$].
-      |4 |_fs1_ is latexmath:[$+0$].
-      |5 |_fs1_ is a positive subnormal number.
-      |6 |_fs1_ is a positive normal number.
-      |7 |_fs1_ is latexmath:[$+\infty$].
-      |8 |_fs1_ is a signaling NaN.
-      |9 |_fs1_ is a quiet NaN.
-      |===
+  .Format of result of `fclass` instruction.
+  [%autowidth,float="center",align="center",cols="^,<",options="header",]
+  |===
+  |_xd_ bit |Meaning
+  |0 |_fs1_ is latexmath:[$-\infty$].
+  |1 |_fs1_ is a negative normal number.
+  |2 |_fs1_ is a negative subnormal number.
+  |3 |_fs1_ is latexmath:[$-0$].
+  |4 |_fs1_ is latexmath:[$+0$].
+  |5 |_fs1_ is a positive subnormal number.
+  |6 |_fs1_ is a positive normal number.
+  |7 |_fs1_ is latexmath:[$+\infty$].
+  |8 |_fs1_ is a signaling NaN.
+  |9 |_fs1_ is a quiet NaN.
+  |===
 definedBy: D
 assembly: xd, fs1
 encoding:
diff --git a/spec/std/isa/inst/D/fcvt.d.l.yaml b/spec/std/isa/inst/D/fcvt.d.l.yaml
index 19973aa894..5ac2404224 100644
--- a/spec/std/isa/inst/D/fcvt.d.l.yaml
+++ b/spec/std/isa/inst/D/fcvt.d.l.yaml
@@ -7,12 +7,9 @@ $schema: inst_schema.json#
 kind: instruction
 name: fcvt.d.l
 long_name: Floating-Point Convert Long to Double-Precision
-description:
-  - id: inst-fcvt.d.l-behaviour
-    normative: false
-    text: |
-      The `fcvt.d.l` instruction converts a 64-bit signed integer, in integer register `xs1` into a double-precision
-      floating-point number in floating-point register `fd`.
+description: |
+  The `fcvt.d.l` instruction converts a 64-bit signed integer, in integer register `xs1` into a double-precision
+  floating-point number in floating-point register `fd`.
 definedBy: D
 assembly: fd, xs1, rm
 encoding:
diff --git a/spec/std/isa/inst/D/fcvt.d.lu.yaml b/spec/std/isa/inst/D/fcvt.d.lu.yaml
index 4b08546acd..f4389f8af0 100644
--- a/spec/std/isa/inst/D/fcvt.d.lu.yaml
+++ b/spec/std/isa/inst/D/fcvt.d.lu.yaml
@@ -7,12 +7,9 @@ $schema: inst_schema.json#
 kind: instruction
 name: fcvt.d.lu
 long_name: Floating-Point Convert Unsigned Long to Double-Precision
-description:
-  - id: inst-fcvt.d.lu-behaviour
-    normative: false
-    text: |
-      The `fcvt.d.lu` instruction converts to or from a 64-bit unsigned integer, `xs1` into a double-precision
-      floating-point number in floating-point register `fd`.
+description: |
+  The `fcvt.d.lu` instruction converts to or from a 64-bit unsigned integer, `xs1` into a double-precision
+  floating-point number in floating-point register `fd`.
 definedBy: D
 assembly: fd, xs1, rm
 encoding:
diff --git a/spec/std/isa/inst/D/fcvt.d.s.yaml b/spec/std/isa/inst/D/fcvt.d.s.yaml
index 7e54b7d1ea..1085247689 100644
--- a/spec/std/isa/inst/D/fcvt.d.s.yaml
+++ b/spec/std/isa/inst/D/fcvt.d.s.yaml
@@ -7,14 +7,11 @@ $schema: inst_schema.json#
 kind: instruction
 name: fcvt.d.s
 long_name: Floating-Point Convert Single-Precision to Double-Precision
-description:
-  - id: inst-fcvt.d.s-behaviour
-    normative: false
-    text: |
-      The single-precision to double-precision conversion instruction, `fcvt.d.s` is encoded in the OP-FP
-      major opcode space and both the source and destination are floating-point registers. The `xs2` field
-      encodes the datatype of the source, and the `fmt` field encodes the datatype of the destination.
-      `fcvt.d.s` will never round.
+description: |
+  The single-precision to double-precision conversion instruction, `fcvt.d.s` is encoded in the OP-FP
+  major opcode space and both the source and destination are floating-point registers. The `xs2` field
+  encodes the datatype of the source, and the `fmt` field encodes the datatype of the destination.
+  `fcvt.d.s` will never round.
 definedBy: D
 assembly: fd, fs1, rm
 encoding:
diff --git a/spec/std/isa/inst/D/fcvt.d.w.yaml b/spec/std/isa/inst/D/fcvt.d.w.yaml
index 6f952bbf6a..112bed2756 100644
--- a/spec/std/isa/inst/D/fcvt.d.w.yaml
+++ b/spec/std/isa/inst/D/fcvt.d.w.yaml
@@ -7,13 +7,10 @@ $schema: inst_schema.json#
 kind: instruction
 name: fcvt.d.w
 long_name: Floating-Point Convert Word to Double-Precision
-description:
-  - id: inst-fcvt.d.w-behaviour
-    normative: false
-    text: |
-      The `fcvt.d.w` instruction converts a 32-bit signed integer, in integer register `xs1` into a double-precision
-      floating-point number in floating-point register `fd`. Note `fcvt.d.w` always produces an exact result and is
-      unaffected by rounding mode.
+description: |
+  The `fcvt.d.w` instruction converts a 32-bit signed integer, in integer register `xs1` into a double-precision
+  floating-point number in floating-point register `fd`. Note `fcvt.d.w` always produces an exact result and is
+  unaffected by rounding mode.
 definedBy: D
 assembly: fd, xs1, rm
 encoding:
diff --git a/spec/std/isa/inst/D/fcvt.d.wu.yaml b/spec/std/isa/inst/D/fcvt.d.wu.yaml
index e072aad2da..4ebb1d00bb 100644
--- a/spec/std/isa/inst/D/fcvt.d.wu.yaml
+++ b/spec/std/isa/inst/D/fcvt.d.wu.yaml
@@ -7,13 +7,10 @@ $schema: inst_schema.json#
 kind: instruction
 name: fcvt.d.wu
 long_name: Floating-Point Convert Unsigned Word to Double-Precision
-description:
-  - id: inst-fcvt.d.wu-behaviour
-    normative: false
-    text: |
-      The `fcvt.d.wu` instruction converts a 32-bit unsigned integer in integer register `xs1` into a double-precision
-      floating-point number in floating-point register `fd`. Note `fcvt.d.wu` always produces an exact result and is
-      unaffected by rounding mode.
+description: |
+  The `fcvt.d.wu` instruction converts a 32-bit unsigned integer in integer register `xs1` into a double-precision
+  floating-point number in floating-point register `fd`. Note `fcvt.d.wu` always produces an exact result and is
+  unaffected by rounding mode.
 definedBy: D
 assembly: fd, xs1, rm
 encoding:
diff --git a/spec/std/isa/inst/D/fcvt.l.d.yaml b/spec/std/isa/inst/D/fcvt.l.d.yaml
index b7abd8e8dc..a6db94c76f 100644
--- a/spec/std/isa/inst/D/fcvt.l.d.yaml
+++ b/spec/std/isa/inst/D/fcvt.l.d.yaml
@@ -7,12 +7,9 @@ $schema: inst_schema.json#
 kind: instruction
 name: fcvt.l.d
 long_name: Floating-Point Convert Double-Precision to Long
-description:
-  - id: inst-fcvt.l.d-behaviour
-    normative: false
-    text: |
-      The `fcvt.l.d` instruction converts a double-precision floating-point number in floating-point register `fs1`
-      to a signed 64-bit integer, in integer register `xd`.
+description: |
+  The `fcvt.l.d` instruction converts a double-precision floating-point number in floating-point register `fs1`
+  to a signed 64-bit integer, in integer register `xd`.
 definedBy: D
 assembly: xd, fs1, rm
 encoding:
diff --git a/spec/std/isa/inst/D/fcvt.lu.d.yaml b/spec/std/isa/inst/D/fcvt.lu.d.yaml
index 402e791adf..412fe85ef2 100644
--- a/spec/std/isa/inst/D/fcvt.lu.d.yaml
+++ b/spec/std/isa/inst/D/fcvt.lu.d.yaml
@@ -7,12 +7,9 @@ $schema: inst_schema.json#
 kind: instruction
 name: fcvt.lu.d
 long_name: Floating-Point Convert Double-Precision to Unsigned Long
-description:
-  - id: inst-fcvt.lu.d-behaviour
-    normative: false
-    text: |
-      The `fcvt.lu.d` instruction converts a double-precision floating-point number in floating-point register `fs1`
-      to an unsigned 64-bit integer, in integer register `xd`.
+description: |
+  The `fcvt.lu.d` instruction converts a double-precision floating-point number in floating-point register `fs1`
+  to an unsigned 64-bit integer, in integer register `xd`.
 definedBy: D
 assembly: xd, fs1, rm
 encoding:
diff --git a/spec/std/isa/inst/D/fcvt.s.d.yaml b/spec/std/isa/inst/D/fcvt.s.d.yaml
index e29f4945ed..8dee843e27 100644
--- a/spec/std/isa/inst/D/fcvt.s.d.yaml
+++ b/spec/std/isa/inst/D/fcvt.s.d.yaml
@@ -7,14 +7,11 @@ $schema: inst_schema.json#
 kind: instruction
 name: fcvt.s.d
 long_name: Floating-Point Convert Double-Precision to Single-Precision
-description:
-  - id: inst-fcvt.s.d-behaviour
-    normative: false
-    text: |
-      The `fcvt.s.d` instruction converts a double-precision floating-point number to a single-precision floating-point
-      number. This is encoded in the OP-FP major opcode space and both the source and destination are floating-point
-      registers. The `xs2` field encodes the datatype of the source, and the `fmt` field encodes the datatype of the
-      destination. `fcvt.s.d` rounds according to the `rm` field.
+description: |
+  The `fcvt.s.d` instruction converts a double-precision floating-point number to a single-precision floating-point
+  number. This is encoded in the OP-FP major opcode space and both the source and destination are floating-point
+  registers. The `xs2` field encodes the datatype of the source, and the `fmt` field encodes the datatype of the
+  destination. `fcvt.s.d` rounds according to the `rm` field.
 definedBy: D
 assembly: fd, fs1, rm
 encoding:
diff --git a/spec/std/isa/inst/D/fcvt.w.d.yaml b/spec/std/isa/inst/D/fcvt.w.d.yaml
index 085b52604b..cc68d18a3a 100644
--- a/spec/std/isa/inst/D/fcvt.w.d.yaml
+++ b/spec/std/isa/inst/D/fcvt.w.d.yaml
@@ -7,12 +7,9 @@ $schema: inst_schema.json#
 kind: instruction
 name: fcvt.w.d
 long_name: Floating-Point Convert Double-Precision to Word
-description:
-  - id: inst-fcvt.w.d-behaviour
-    normative: false
-    text: |
-      The `fcvt.w.d` instruction converts a double-precision floating-point number in floating-point register `fs1` to a
-      signed 32-bit integer, in integer register `xd`.
+description: |
+  The `fcvt.w.d` instruction converts a double-precision floating-point number in floating-point register `fs1` to a
+  signed 32-bit integer, in integer register `xd`.
 definedBy: D
 assembly: xd, fs1, rm
 encoding:
diff --git a/spec/std/isa/inst/D/fcvt.wu.d.yaml b/spec/std/isa/inst/D/fcvt.wu.d.yaml
index 5b5df5d708..68bb6ca868 100644
--- a/spec/std/isa/inst/D/fcvt.wu.d.yaml
+++ b/spec/std/isa/inst/D/fcvt.wu.d.yaml
@@ -7,12 +7,9 @@ $schema: inst_schema.json#
 kind: instruction
 name: fcvt.wu.d
 long_name: Floating-Point Convert Double-Precision to Unsigned Word
-description:
-  - id: inst-fcvt.wu.d-behaviour
-    normative: false
-    text: |
-      The `fcvt.wu.d` instruction converts a double-precision floating-point number in floating-point register `fs1` to an
-      unsigned 32-bit integer, in integer register `xd`.
+description: |
+  The `fcvt.wu.d` instruction converts a double-precision floating-point number in floating-point register `fs1` to an
+  unsigned 32-bit integer, in integer register `xd`.
 definedBy: D
 assembly: xd, fs1, rm
 encoding:
diff --git a/spec/std/isa/inst/D/fcvtmod.w.d.yaml b/spec/std/isa/inst/D/fcvtmod.w.d.yaml
index 256c6edc90..58112b2152 100644
--- a/spec/std/isa/inst/D/fcvtmod.w.d.yaml
+++ b/spec/std/isa/inst/D/fcvtmod.w.d.yaml
@@ -7,19 +7,16 @@ $schema: inst_schema.json#
 kind: instruction
 name: fcvtmod.w.d
 long_name: Floating-Point Convert Double-Precision to Word with Modulo
-description:
-  - id: inst-fcvtmod.w.d-behaviour
-    normative: false
-    text: |
-      The `fcvtmod.w.d` instruction always rounds towards zero. Bits 31:0 are taken from the rounded, unbounded
-      two's complement result, then sign-extended to XLEN bits and written to integer register `xd`. ±∞ and
-      NaN are converted to zero.
+description: |
+  The `fcvtmod.w.d` instruction always rounds towards zero. Bits 31:0 are taken from the rounded, unbounded
+  two's complement result, then sign-extended to XLEN bits and written to integer register `xd`. ±∞ and
+  NaN are converted to zero.
 
-      Floating-point exception flags are raised the same as they would be for `fcvt.w.d` with the same input
-      operand.
+  Floating-point exception flags are raised the same as they would be for `fcvt.w.d` with the same input
+  operand.
 
-      This instruction is only provided if the D extension is implemented. It is encoded like `fcvt.w.d`, but
-      with the `xs2` field set to 8 and the `rm` field set to 1 (RTZ). Other `rm` values are reserved.
+  This instruction is only provided if the D extension is implemented. It is encoded like `fcvt.w.d`, but
+  with the `xs2` field set to 8 and the `rm` field set to 1 (RTZ). Other `rm` values are reserved.
 definedBy:
   allOf: [D, Zfa]
 assembly: xd, fs1, rm
diff --git a/spec/std/isa/inst/D/fdiv.d.yaml b/spec/std/isa/inst/D/fdiv.d.yaml
index 1b9d8213ac..b0072abd94 100644
--- a/spec/std/isa/inst/D/fdiv.d.yaml
+++ b/spec/std/isa/inst/D/fdiv.d.yaml
@@ -7,12 +7,9 @@ $schema: inst_schema.json#
 kind: instruction
 name: fdiv.d
 long_name: Floating-Point Divide Double-Precision
-description:
-  - id: inst-fdiv.d-behaviour
-    normative: false
-    text: |
-      The `fdiv.d` instruction performs the double-precision floating-point division of `fs1` by `fs2`. It is defined analogously
-      to its single-precision counterpart, but operates on double-precision operands and produces double-precision results.
+description: |
+  The `fdiv.d` instruction performs the double-precision floating-point division of `fs1` by `fs2`. It is defined analogously
+  to its single-precision counterpart, but operates on double-precision operands and produces double-precision results.
 definedBy: D
 assembly: fd, fs1, fs2, rm
 encoding:
diff --git a/spec/std/isa/inst/D/feq.d.yaml b/spec/std/isa/inst/D/feq.d.yaml
index 7cb3b61319..fb0c0c95c0 100644
--- a/spec/std/isa/inst/D/feq.d.yaml
+++ b/spec/std/isa/inst/D/feq.d.yaml
@@ -7,12 +7,9 @@ $schema: inst_schema.json#
 kind: instruction
 name: feq.d
 long_name: Floating-Point Equal Double-Precision
-description:
-  - id: inst-feq.d-behaviour
-    normative: false
-    text: |
-      The `feq.d` instruction writes 1 to `xd` if `fs1` and `fs2` are equal, and 0 otherwise. It is defined analogously to its
-      single-precision counterpart, but operates on double-precision operands.
+description: |
+  The `feq.d` instruction writes 1 to `xd` if `fs1` and `fs2` are equal, and 0 otherwise. It is defined analogously to its
+  single-precision counterpart, but operates on double-precision operands.
 definedBy: D
 assembly: xd, fs1, fs2
 encoding:
diff --git a/spec/std/isa/inst/D/fld.yaml b/spec/std/isa/inst/D/fld.yaml
index 0414132419..b75d1905e5 100644
--- a/spec/std/isa/inst/D/fld.yaml
+++ b/spec/std/isa/inst/D/fld.yaml
@@ -7,14 +7,11 @@ $schema: inst_schema.json#
 kind: instruction
 name: fld
 long_name: Floating-Point Load Double-Precision
-description:
-  - id: inst-fld-behaviour
-    normative: false
-    text: |
-      The `fld` instruction loads a double-precision floating-point value from memory into floating-point
-      register `fd`. It is guaranteed to execute atomically if the effective address is naturally aligned
-      and XLEN≥64. It doesn't modify the bits being transferred; in particular, the payloads of non-canonical
-      NaNs are preserved.
+description: |
+  The `fld` instruction loads a double-precision floating-point value from memory into floating-point
+  register `fd`. It is guaranteed to execute atomically if the effective address is naturally aligned
+  and XLEN≥64. It doesn't modify the bits being transferred; in particular, the payloads of non-canonical
+  NaNs are preserved.
 definedBy: D
 assembly: fd, imm(xs1)
 encoding:
diff --git a/spec/std/isa/inst/D/fle.d.yaml b/spec/std/isa/inst/D/fle.d.yaml
index 280f5cc5ca..a5c854e7e1 100644
--- a/spec/std/isa/inst/D/fle.d.yaml
+++ b/spec/std/isa/inst/D/fle.d.yaml
@@ -7,12 +7,9 @@ $schema: inst_schema.json#
 kind: instruction
 name: fle.d
 long_name: Floating-Point Less Than or Equal Double-Precision
-description:
-  - id: inst-fle.d-behaviour
-    normative: false
-    text: |
-      The `fle.d` instruction writes 1 to `xd` if `fs1` is less than or equal to `fs2`, and 0 otherwise. It is defined
-      analogously to its single-precision counterpart, but operates on double-precision operands.
+description: |
+  The `fle.d` instruction writes 1 to `xd` if `fs1` is less than or equal to `fs2`, and 0 otherwise. It is defined
+  analogously to its single-precision counterpart, but operates on double-precision operands.
 definedBy: D
 assembly: xd, fs1, fs2
 encoding:
diff --git a/spec/std/isa/inst/D/fleq.d.yaml b/spec/std/isa/inst/D/fleq.d.yaml
index 5ed7e6a91e..04f37bc83c 100644
--- a/spec/std/isa/inst/D/fleq.d.yaml
+++ b/spec/std/isa/inst/D/fleq.d.yaml
@@ -7,12 +7,9 @@ $schema: inst_schema.json#
 kind: instruction
 name: fleq.d
 long_name: Floating-Point Less Than or Equal Quiet Double-Precision
-description:
-  - id: inst-fleq.d-behaviour
-    normative: false
-    text: |
-      The `fleq.d` instruction is defined like the `fle.d` instruction, except that quiet NaN inputs do not cause
-      the invalid operation exception flag to be set.
+description: |
+  The `fleq.d` instruction is defined like the `fle.d` instruction, except that quiet NaN inputs do not cause
+  the invalid operation exception flag to be set.
 definedBy:
   allOf: [D, Zfa]
 assembly: xd, fs1, fs2
diff --git a/spec/std/isa/inst/D/fli.d.yaml b/spec/std/isa/inst/D/fli.d.yaml
index 662a10aa03..034a13ac31 100644
--- a/spec/std/isa/inst/D/fli.d.yaml
+++ b/spec/std/isa/inst/D/fli.d.yaml
@@ -7,12 +7,9 @@ $schema: inst_schema.json#
 kind: instruction
 name: fli.d
 long_name: Floating-Point Load Immediate Double-Precision
-description:
-  - id: inst-fli.d-behaviour
-    normative: false
-    text: |
-      The `fli.d` instruction instruction loads one of 32 double-precision floating-point constants, encoded in the `xs1`
-      field, into floating-point register `fd`. `fli.d` is encoded like `fli.s`, but with `fmt` set to D.
+description: |
+  The `fli.d` instruction instruction loads one of 32 double-precision floating-point constants, encoded in the `xs1`
+  field, into floating-point register `fd`. `fli.d` is encoded like `fli.s`, but with `fmt` set to D.
 definedBy:
   allOf: [D, Zfa]
 assembly: fd, xs1
diff --git a/spec/std/isa/inst/D/flt.d.yaml b/spec/std/isa/inst/D/flt.d.yaml
index 6ff12eff47..df7bef19ce 100644
--- a/spec/std/isa/inst/D/flt.d.yaml
+++ b/spec/std/isa/inst/D/flt.d.yaml
@@ -7,12 +7,9 @@ $schema: inst_schema.json#
 kind: instruction
 name: flt.d
 long_name: Floating-Point Less Than Double-Precision
-description:
-  - id: inst-flt.d-behaviour
-    normative: false
-    text: |
-      The `flt.d` instruction writes 1 to `xd` if `fs1` is less than `fs2`, and 0 otherwise. It is defined analogously to its
-      single-precision counterpart, but operates on double-precision operands.
+description: |
+  The `flt.d` instruction writes 1 to `xd` if `fs1` is less than `fs2`, and 0 otherwise. It is defined analogously to its
+  single-precision counterpart, but operates on double-precision operands.
 definedBy: D
 assembly: xd, fs1, fs2
 encoding:
diff --git a/spec/std/isa/inst/D/fltq.d.yaml b/spec/std/isa/inst/D/fltq.d.yaml
index d39714c1ec..5d05ee19ef 100644
--- a/spec/std/isa/inst/D/fltq.d.yaml
+++ b/spec/std/isa/inst/D/fltq.d.yaml
@@ -7,12 +7,9 @@ $schema: inst_schema.json#
 kind: instruction
 name: fltq.d
 long_name: Floating-Point Less Than Quiet Double-Precision
-description:
-  - id: inst-fltq.d-behaviour
-    normative: false
-    text: |
-      The `fltq.d` instruction is defined like the `flt.d` instruction, except that quiet NaN inputs do not cause
-      the invalid operation exception flag to be set.
+description: |
+  The `fltq.d` instruction is defined like the `flt.d` instruction, except that quiet NaN inputs do not cause
+  the invalid operation exception flag to be set.
 definedBy:
   allOf: [D, Zfa]
 assembly: xd, fs1, fs2
diff --git a/spec/std/isa/inst/D/fmadd.d.yaml b/spec/std/isa/inst/D/fmadd.d.yaml
index c939d8b7a9..e85c304abd 100644
--- a/spec/std/isa/inst/D/fmadd.d.yaml
+++ b/spec/std/isa/inst/D/fmadd.d.yaml
@@ -7,11 +7,8 @@ $schema: inst_schema.json#
 kind: instruction
 name: fmadd.d
 long_name: Floating-Point Multiply-Add Double-Precision
-description:
-  - id: inst-fmadd.d-behaviour
-    normative: false
-    text: |
-      The `fmadd.d` instruction multiplies the values in `fs1` and `fs2`, adds the value in `fs3`, and writes the final result to `fd`.
+description: |
+  The `fmadd.d` instruction multiplies the values in `fs1` and `fs2`, adds the value in `fs3`, and writes the final result to `fd`.
 definedBy: D
 assembly: fd, fs1, fs2, fs3, rm
 encoding:
diff --git a/spec/std/isa/inst/D/fmax.d.yaml b/spec/std/isa/inst/D/fmax.d.yaml
index f76c6898d3..0d5545eb68 100644
--- a/spec/std/isa/inst/D/fmax.d.yaml
+++ b/spec/std/isa/inst/D/fmax.d.yaml
@@ -7,14 +7,11 @@ $schema: inst_schema.json#
 kind: instruction
 name: fmax.d
 long_name: Floating-Point Maximum-Number Double-Precision
-description:
-  - id: inst-fmax.d-behaviour
-    normative: false
-    text: |
-      The `fmax.d` instruction writes larger of `fs1` and `fs2` to `fd`. For the purposes of this instruction,
-      the value `-0.0` is considered to be less than the value `+0.0`. If both inputs are NaNs, the result is
-      the canonical NaN. If only one operand is a NaN, the result is the non-NaN operand. Signaling NaN inputs
-      set the invalid operation exception flag, even when the result is not NaN.
+description: |
+  The `fmax.d` instruction writes larger of `fs1` and `fs2` to `fd`. For the purposes of this instruction,
+  the value `-0.0` is considered to be less than the value `+0.0`. If both inputs are NaNs, the result is
+  the canonical NaN. If only one operand is a NaN, the result is the non-NaN operand. Signaling NaN inputs
+  set the invalid operation exception flag, even when the result is not NaN.
 definedBy: D
 assembly: fd, fs1, fs2
 encoding:
diff --git a/spec/std/isa/inst/D/fmaxm.d.yaml b/spec/std/isa/inst/D/fmaxm.d.yaml
index a652ba663c..1f54bab95b 100644
--- a/spec/std/isa/inst/D/fmaxm.d.yaml
+++ b/spec/std/isa/inst/D/fmaxm.d.yaml
@@ -7,12 +7,9 @@ $schema: inst_schema.json#
 kind: instruction
 name: fmaxm.d
 long_name: Floating-Point Maximum-Number NaN Double-Precision
-description:
-  - id: inst-fmaxm.d-behaviour
-    normative: false
-    text: |
-      The `fmaxm.d` instruction writes larger of `fs1` and `fs2` to `fd`. It is defined like `fmax.d` instruction, except
-      that if either input is NaN, the result is the canonical NaN.
+description: |
+  The `fmaxm.d` instruction writes larger of `fs1` and `fs2` to `fd`. It is defined like `fmax.d` instruction, except
+  that if either input is NaN, the result is the canonical NaN.
 definedBy:
   allOf: [D, Zfa]
 assembly: fd, fs1, fs2
diff --git a/spec/std/isa/inst/D/fmin.d.yaml b/spec/std/isa/inst/D/fmin.d.yaml
index 88bda4a593..f85f780b48 100644
--- a/spec/std/isa/inst/D/fmin.d.yaml
+++ b/spec/std/isa/inst/D/fmin.d.yaml
@@ -7,14 +7,11 @@ $schema: inst_schema.json#
 kind: instruction
 name: fmin.d
 long_name: Floating-Point Minimum-Number Double-Precision
-description:
-  - id: inst-fmin.d-behaviour
-    normative: false
-    text: |
-      The `fmin.d` instruction writes smaller of `fs1` and `fs2` to `fd`. For the purposes of this instruction,
-      the value `-0.0` is considered to be less than the value `+0.0`. If both inputs are NaNs, the result is
-      the canonical NaN. If only one operand is a NaN, the result is the non-NaN operand. Signaling NaN inputs
-      set the invalid operation exception flag, even when the result is not NaN.
+description: |
+  The `fmin.d` instruction writes smaller of `fs1` and `fs2` to `fd`. For the purposes of this instruction,
+  the value `-0.0` is considered to be less than the value `+0.0`. If both inputs are NaNs, the result is
+  the canonical NaN. If only one operand is a NaN, the result is the non-NaN operand. Signaling NaN inputs
+  set the invalid operation exception flag, even when the result is not NaN.
 definedBy: D
 assembly: fd, fs1, fs2
 encoding:
diff --git a/spec/std/isa/inst/D/fminm.d.yaml b/spec/std/isa/inst/D/fminm.d.yaml
index 38fb7293be..bb884b85fa 100644
--- a/spec/std/isa/inst/D/fminm.d.yaml
+++ b/spec/std/isa/inst/D/fminm.d.yaml
@@ -7,12 +7,9 @@ $schema: inst_schema.json#
 kind: instruction
 name: fminm.d
 long_name: Floating-Point Minimum-Number NaN Double-Precision
-description:
-  - id: inst-fminm.d-behaviour
-    normative: false
-    text: |
-      The `fminm.d` instruction writes smaller of `fs1` and `fs2` to `fd`. It is defined like `fmin.d` instruction, except
-      that if either input is NaN, the result is the canonical NaN.
+description: |
+  The `fminm.d` instruction writes smaller of `fs1` and `fs2` to `fd`. It is defined like `fmin.d` instruction, except
+  that if either input is NaN, the result is the canonical NaN.
 definedBy:
   allOf: [D, Zfa]
 assembly: fd, fs1, fs2
diff --git a/spec/std/isa/inst/D/fmsub.d.yaml b/spec/std/isa/inst/D/fmsub.d.yaml
index b1798d41a8..1391ab4c43 100644
--- a/spec/std/isa/inst/D/fmsub.d.yaml
+++ b/spec/std/isa/inst/D/fmsub.d.yaml
@@ -7,11 +7,8 @@ $schema: inst_schema.json#
 kind: instruction
 name: fmsub.d
 long_name: Floating-Point Multiply-Subtract Double-Precision
-description:
-  - id: inst-fmsub.d-behaviour
-    normative: false
-    text: |
-      The `fmsub.d` instruction multiplies the values in `fs1` and `fs2`, subtracts the value in `fs3`, and writes the final result to `fd`.
+description: |
+  The `fmsub.d` instruction multiplies the values in `fs1` and `fs2`, subtracts the value in `fs3`, and writes the final result to `fd`.
 definedBy: D
 assembly: fd, fs1, fs2, fs3, rm
 encoding:
diff --git a/spec/std/isa/inst/D/fmul.d.yaml b/spec/std/isa/inst/D/fmul.d.yaml
index 928014f411..b735430c30 100644
--- a/spec/std/isa/inst/D/fmul.d.yaml
+++ b/spec/std/isa/inst/D/fmul.d.yaml
@@ -7,13 +7,10 @@ $schema: inst_schema.json#
 kind: instruction
 name: fmul.d
 long_name: Floating-Point Multiply Double-Precision
-description:
-  - id: inst-fmul.d-behaviour
-    normative: false
-    text: |
-      The `fmul.d` instruction performs the double-precision floating-point multiplication between `fs1` and `fs2`.
-      It is defined analogously to its single-precision counterpart, but operates on double-precision operands and
-      produces double-precision results.
+description: |
+  The `fmul.d` instruction performs the double-precision floating-point multiplication between `fs1` and `fs2`.
+  It is defined analogously to its single-precision counterpart, but operates on double-precision operands and
+  produces double-precision results.
 definedBy: D
 assembly: fd, fs1, fs2, rm
 encoding:
diff --git a/spec/std/isa/inst/D/fmv.d.x.yaml b/spec/std/isa/inst/D/fmv.d.x.yaml
index c3f0b0a898..e7d1c49d82 100644
--- a/spec/std/isa/inst/D/fmv.d.x.yaml
+++ b/spec/std/isa/inst/D/fmv.d.x.yaml
@@ -6,13 +6,10 @@
 $schema: inst_schema.json#
 kind: instruction
 name: fmv.d.x
-long_name: Floating-Point Move from Integer Register to Double-Precision Register
-description:
-  - id: inst-fmv.d.x-behaviour
-    normative: false
-    text: |
-      The `fmv.d.x` instruction moves the double-precision value encoded in `IEEE 754-2008` standard encoding from the integer
-      register `xs1` to the floating-point register `fd`.
+long_name: Floating-Point Move Double-Precision from Integer Register
+description: |
+  The `fmv.d.x` instruction moves the double-precision value encoded in `IEEE 754-2008` standard encoding from the integer
+  register `xs1` to the floating-point register `fd`.
 definedBy: D
 assembly: fd, xs1
 encoding:
diff --git a/spec/std/isa/inst/D/fmv.x.d.yaml b/spec/std/isa/inst/D/fmv.x.d.yaml
index 678d6b7d2f..6a31add7ac 100644
--- a/spec/std/isa/inst/D/fmv.x.d.yaml
+++ b/spec/std/isa/inst/D/fmv.x.d.yaml
@@ -6,13 +6,10 @@
 $schema: inst_schema.json#
 kind: instruction
 name: fmv.x.d
-long_name: Floating-Point Move from Double-Precision Register to Integer Register
-description:
-  - id: inst-fmv.x.d-behaviour
-    normative: false
-    text: |
-      The `fmv.x.d` instruction moves the double-precision value in floating-point register `fs1` to a representation in
-      `IEEE 754-2008` standard encoding in integer register `xd`.
+long_name: Floating-Point Move Double-Precision to Integer Register
+description: |
+  The `fmv.x.d` instruction moves the double-precision value in floating-point register `fs1` to a representation in
+  `IEEE 754-2008` standard encoding in integer register `xd`.
 definedBy: D
 assembly: xd, fs1
 encoding:
diff --git a/spec/std/isa/inst/D/fmvh.x.d.yaml b/spec/std/isa/inst/D/fmvh.x.d.yaml
index a61c1a3c6a..40df278a13 100644
--- a/spec/std/isa/inst/D/fmvh.x.d.yaml
+++ b/spec/std/isa/inst/D/fmvh.x.d.yaml
@@ -7,13 +7,10 @@ $schema: inst_schema.json#
 kind: instruction
 name: fmvh.x.d
 long_name: Floating-Point Move High Half from Double-Precision Register to Integer Register
-description:
-  - id: inst-fmvh.x.d-behaviour
-    normative: false
-    text: |
-      The `fmvh.x.d` instruction moves bits 63:32 of floating-point register `fs1` into integer register `xd`. `fmvh.x.d`
-      is used in conjunction with the existing `fmv.x.w` instruction to move a double-precision floating-point number to a
-      pair of integer-registers.
+description: |
+  The `fmvh.x.d` instruction moves bits 63:32 of floating-point register `fs1` into integer register `xd`. `fmvh.x.d`
+  is used in conjunction with the existing `fmv.x.w` instruction to move a double-precision floating-point number to a
+  pair of integer-registers.
 definedBy:
   allOf: [D, Zfa]
 assembly: xd, fs1
diff --git a/spec/std/isa/inst/D/fmvp.d.x.yaml b/spec/std/isa/inst/D/fmvp.d.x.yaml
index b9afa30b26..c8d44bc3cc 100644
--- a/spec/std/isa/inst/D/fmvp.d.x.yaml
+++ b/spec/std/isa/inst/D/fmvp.d.x.yaml
@@ -7,13 +7,10 @@ $schema: inst_schema.json#
 kind: instruction
 name: fmvp.d.x
 long_name: Floating-Point Move Pair from Integer Registers to Double-Precision Register
-description:
-  - id: inst-fmvp.d.x-behaviour
-    normative: false
-    text: |
-      The `fmvp.d.x` instruction moves a double-precision number from a pair of integer registers into a floating-point
-      register. Integer registers `xs1` and `xs2` supply bits 31:0 and 63:32, respectively; the result is written to
-      floating-point register `fd`.
+description: |
+  The `fmvp.d.x` instruction moves a double-precision number from a pair of integer registers into a floating-point
+  register. Integer registers `xs1` and `xs2` supply bits 31:0 and 63:32, respectively; the result is written to
+  floating-point register `fd`.
 definedBy:
   allOf: [D, Zfa]
 assembly: fd, xs1, xs2
diff --git a/spec/std/isa/inst/D/fnmadd.d.yaml b/spec/std/isa/inst/D/fnmadd.d.yaml
index 9fe296a8a2..214d7c06cb 100644
--- a/spec/std/isa/inst/D/fnmadd.d.yaml
+++ b/spec/std/isa/inst/D/fnmadd.d.yaml
@@ -7,12 +7,9 @@ $schema: inst_schema.json#
 kind: instruction
 name: fnmadd.d
 long_name: Floating-Point Negate-Multiply-Add Double-Precision
-description:
-  - id: inst-fnmadd.d-behaviour
-    normative: false
-    text: |
-      The `fnmadd.d` instruction multiplies the values in `fs1` and `fs2`, negates the product, subtracts the value in `fs3`, and
-      writes the final result to `fd`.
+description: |
+  The `fnmadd.d` instruction multiplies the values in `fs1` and `fs2`, negates the product, subtracts the value in `fs3`, and
+  writes the final result to `fd`.
 definedBy: D
 assembly: fd, fs1, fs2, fs3, rm
 encoding:
diff --git a/spec/std/isa/inst/D/fnmsub.d.yaml b/spec/std/isa/inst/D/fnmsub.d.yaml
index 46e08f9995..66df972bfe 100644
--- a/spec/std/isa/inst/D/fnmsub.d.yaml
+++ b/spec/std/isa/inst/D/fnmsub.d.yaml
@@ -7,12 +7,9 @@ $schema: inst_schema.json#
 kind: instruction
 name: fnmsub.d
 long_name: Floating-Point Negate-Multiply-Subtract Double-Precision
-description:
-  - id: inst-fnmsub.d-behaviour
-    normative: false
-    text: |
-      The `fnmsub.d` instruction multiplies the values in `fs1` and `fs2`, negates the product, adds the value in `fs3`, and
-      writes the final result to `fd`.
+description: |
+  The `fnmsub.d` instruction multiplies the values in `fs1` and `fs2`, negates the product, adds the value in `fs3`, and
+  writes the final result to `fd`.
 definedBy: D
 assembly: fd, fs1, fs2, fs3, rm
 encoding:
diff --git a/spec/std/isa/inst/D/fround.d.yaml b/spec/std/isa/inst/D/fround.d.yaml
index 2a4cd58bf1..d0192ce1f1 100644
--- a/spec/std/isa/inst/D/fround.d.yaml
+++ b/spec/std/isa/inst/D/fround.d.yaml
@@ -7,16 +7,13 @@ $schema: inst_schema.json#
 kind: instruction
 name: fround.d
 long_name: Floating-Point Round Double-Precision
-description:
-  - id: inst-fround.d-behaviour
-    normative: false
-    text: |
-      The `fround.d` instruction rounds the double-precision floating-point number in floating-point register
-      `fs1` to an integer, according to the rounding mode specified in the instruction's `rm` field. It then writes
-      that integer, represented as a double-precision floating-point number, to floating-point register `fd`. Zero
-      and infinite inputs are copied to `fd` unmodified. Signaling NaN inputs cause the invalid operation
-      exception flag to be set; no other exception flags are set. `fround.d` is encoded like `fcvt.d.s`, but with
-      `xs2` set to 4.
+description: |
+  The `fround.d` instruction rounds the double-precision floating-point number in floating-point register
+  `fs1` to an integer, according to the rounding mode specified in the instruction's `rm` field. It then writes
+  that integer, represented as a double-precision floating-point number, to floating-point register `fd`. Zero
+  and infinite inputs are copied to `fd` unmodified. Signaling NaN inputs cause the invalid operation
+  exception flag to be set; no other exception flags are set. `fround.d` is encoded like `fcvt.d.s`, but with
+  `xs2` set to 4.
 definedBy:
   allOf: [D, Zfa]
 assembly: fd, fs1, rm
diff --git a/spec/std/isa/inst/D/froundnx.d.yaml b/spec/std/isa/inst/D/froundnx.d.yaml
index ada36186d6..f72b2e2698 100644
--- a/spec/std/isa/inst/D/froundnx.d.yaml
+++ b/spec/std/isa/inst/D/froundnx.d.yaml
@@ -7,12 +7,9 @@ $schema: inst_schema.json#
 kind: instruction
 name: froundnx.d
 long_name: Floating-Point Round-to-Integer Inexact Double-Precision
-description:
-  - id: inst-froundnx.d-behaviour
-    normative: false
-    text: |
-      The `froundnx.d` instruction is defined in the same way as `fround.d`, but it also sets the inexact exception flag if the input
-      differs from the rounded result and is not NaN. `froundnx.d` is encoded like `fcvt.d.s`, but with `xs2` set to 5.
+description: |
+  The `froundnx.d` instruction is defined in the same way as `fround.d`, but it also sets the inexact exception flag if the input
+  differs from the rounded result and is not NaN. `froundnx.d` is encoded like `fcvt.d.s`, but with `xs2` set to 5.
 definedBy:
   allOf: [D, Zfa]
 assembly: fd, fs1, rm
diff --git a/spec/std/isa/inst/D/fsd.yaml b/spec/std/isa/inst/D/fsd.yaml
index 92568540df..7f1aa9a424 100644
--- a/spec/std/isa/inst/D/fsd.yaml
+++ b/spec/std/isa/inst/D/fsd.yaml
@@ -7,13 +7,10 @@ $schema: inst_schema.json#
 kind: instruction
 name: fsd
 long_name: Floating-Point Store Double-Precision
-description:
-  - id: inst-fsd-behaviour
-    normative: false
-    text: |
-      The `fsd` instruction stores a double-precision value from the floating-point registers to memory. It is guaranteed to execute
-      atomically if the effective address is naturally aligned and XLEN≥64. It doesn't modify the bits being transferred; in particular,
-      the payloads of non-canonical NaNs are preserved.
+description: |
+  The `fsd` instruction stores a double-precision value from the floating-point registers to memory. It is guaranteed to execute
+  atomically if the effective address is naturally aligned and XLEN≥64. It doesn't modify the bits being transferred; in particular,
+  the payloads of non-canonical NaNs are preserved.
 definedBy: D
 assembly: fs2, imm(xs1)
 encoding:
diff --git a/spec/std/isa/inst/D/fsgnj.d.yaml b/spec/std/isa/inst/D/fsgnj.d.yaml
index 338723a399..a98802795c 100644
--- a/spec/std/isa/inst/D/fsgnj.d.yaml
+++ b/spec/std/isa/inst/D/fsgnj.d.yaml
@@ -7,14 +7,11 @@ $schema: inst_schema.json#
 kind: instruction
 name: fsgnj.d
 long_name: Floating-Point Sign-Inject Double-Precision
-description:
-  - id: inst-fsgnj.d-behaviour
-    normative: false
-    text: |
-      The `fsgnj.d` instruction produces a result that takes all bits except the sign bit from `fs1`.
-      The result's sign bit is taken from `fs2`'s sign bit, and the result is written to the destination
-      register `fd`. Sign-injection instructions do not set floating-point exception flags, nor do they
-      canonicalize NaNs.
+description: |
+  The `fsgnj.d` instruction produces a result that takes all bits except the sign bit from `fs1`.
+  The result's sign bit is taken from `fs2`'s sign bit, and the result is written to the destination
+  register `fd`. Sign-injection instructions do not set floating-point exception flags, nor do they
+  canonicalize NaNs.
 definedBy: D
 assembly: fd, fs1, fs2
 encoding:
diff --git a/spec/std/isa/inst/D/fsgnjn.d.yaml b/spec/std/isa/inst/D/fsgnjn.d.yaml
index 1f69aff7e1..17e8012020 100644
--- a/spec/std/isa/inst/D/fsgnjn.d.yaml
+++ b/spec/std/isa/inst/D/fsgnjn.d.yaml
@@ -7,14 +7,11 @@ $schema: inst_schema.json#
 kind: instruction
 name: fsgnjn.d
 long_name: Floating-Point Sign-Inject Negate Double-Precision
-description:
-  - id: inst-fsgnjn.d-behaviour
-    normative: false
-    text: |
-      The `fsgnjn.d` instruction produces a result that takes all bits except the sign bit from `fs1`.
-      The result's sign bit is opposite of `fs2`'s sign bit, and the result is written to the destination
-      register `fd`. Sign-injection instructions do not set floating-point exception flags, nor do they
-      canonicalize NaNs.
+description: |
+  The `fsgnjn.d` instruction produces a result that takes all bits except the sign bit from `fs1`.
+  The result's sign bit is opposite of `fs2`'s sign bit, and the result is written to the destination
+  register `fd`. Sign-injection instructions do not set floating-point exception flags, nor do they
+  canonicalize NaNs.
 definedBy: D
 assembly: fd, fs1, fs2
 encoding:
diff --git a/spec/std/isa/inst/D/fsgnjx.d.yaml b/spec/std/isa/inst/D/fsgnjx.d.yaml
index 0b5375a5c6..f2fb896096 100644
--- a/spec/std/isa/inst/D/fsgnjx.d.yaml
+++ b/spec/std/isa/inst/D/fsgnjx.d.yaml
@@ -7,14 +7,11 @@ $schema: inst_schema.json#
 kind: instruction
 name: fsgnjx.d
 long_name: Floating-Point Sign-Inject XOR Double-Precision
-description:
-  - id: inst-fsgnjx.d-behaviour
-    normative: false
-    text: |
-      The `fsgnjx.d` instruction produces a result that takes all bits except the sign bit from `fs1`.
-      The result's sign bit is the XOR of sign bits of `fs1` and `fs2`, and the result is written to
-      the destination register `fd`. Sign-injection instructions do not set floating-point exception
-      flags, nor do they canonicalize NaNs.
+description: |
+  The `fsgnjx.d` instruction produces a result that takes all bits except the sign bit from `fs1`.
+  The result's sign bit is the XOR of sign bits of `fs1` and `fs2`, and the result is written to
+  the destination register `fd`. Sign-injection instructions do not set floating-point exception
+  flags, nor do they canonicalize NaNs.
 definedBy: D
 assembly: fd, fs1, fs2
 encoding:
diff --git a/spec/std/isa/inst/D/fsqrt.d.yaml b/spec/std/isa/inst/D/fsqrt.d.yaml
index c8d01d43b2..0d946e6e60 100644
--- a/spec/std/isa/inst/D/fsqrt.d.yaml
+++ b/spec/std/isa/inst/D/fsqrt.d.yaml
@@ -7,13 +7,10 @@ $schema: inst_schema.json#
 kind: instruction
 name: fsqrt.d
 long_name: Floating-Point Square Root Double-Precision
-description:
-  - id: inst-fsqrt.d-behaviour
-    normative: false
-    text: |
-      The `fsqrt.d` instruction computes the square root of `fs1` and result is written in `fd`. It is defined
-      analogously to its single-precision counterpart, but operates on double-precision operands and produces
-      double-precision results.
+description: |
+  The `fsqrt.d` instruction computes the square root of `fs1` and result is written in `fd`. It is defined
+  analogously to its single-precision counterpart, but operates on double-precision operands and produces
+  double-precision results.
 definedBy: D
 assembly: fd, fs1, rm
 encoding:
diff --git a/spec/std/isa/inst/D/fsub.d.yaml b/spec/std/isa/inst/D/fsub.d.yaml
index 872574ac04..e7ccade27d 100644
--- a/spec/std/isa/inst/D/fsub.d.yaml
+++ b/spec/std/isa/inst/D/fsub.d.yaml
@@ -7,12 +7,9 @@ $schema: inst_schema.json#
 kind: instruction
 name: fsub.d
 long_name: Floating-Point Subtract Double-Precision
-description:
-  - id: inst-fsub.d-behaviour
-    normative: false
-    text: |
-      The `fsub.d` instruction is analogous to `fsub.s` and performs double-precision floating-point subtraction between
-      `fs1` and `fs2` and writes the final result to `fd`.
+description: |
+  The `fsub.d` instruction is analogous to `fsub.s` and performs double-precision floating-point subtraction between
+  `fs1` and `fs2` and writes the final result to `fd`.
 definedBy: D
 assembly: fd, fs1, fs2, rm
 encoding:
diff --git a/spec/std/isa/inst/F/fadd.s.yaml b/spec/std/isa/inst/F/fadd.s.yaml
index 1d30723c62..a2205538c1 100644
--- a/spec/std/isa/inst/F/fadd.s.yaml
+++ b/spec/std/isa/inst/F/fadd.s.yaml
@@ -8,7 +8,7 @@ kind: instruction
 name: fadd.s
 long_name: Floating-Point Add Single-Precision
 description: |
-  The `fadd.s` instruction performs single-precision floating-point addition of `xs1` and `xs2`
+  The `fadd.s` instruction performs single-precision floating-point addition of `fs1` and `fs2`
   and writes the final result to `fd`.
 definedBy: F
 assembly: fd, fs1, fs2, rm
diff --git a/spec/std/isa/inst/Q/fadd.q.yaml b/spec/std/isa/inst/Q/fadd.q.yaml
index 7d656e7cde..16fcd07c7c 100644
--- a/spec/std/isa/inst/Q/fadd.q.yaml
+++ b/spec/std/isa/inst/Q/fadd.q.yaml
@@ -7,12 +7,9 @@ $schema: "inst_schema.json#"
 kind: instruction
 name: fadd.q
 long_name: Floating-point Add Quad-Precision
-description:
-  - id: inst-fadd.q-behaviour
-    normative: false
-    text: |
-      `fadd.q` is analogous to `fadd.d` and performs double-precision floating-point addition between
-      `qs1` and `qs2` and writes the final result to `qd`.
+description: |
+  `fadd.q` is analogous to `fadd.d` and performs double-precision floating-point addition between
+  `qs1` and `qs2` and writes the final result to `qd`.
 definedBy: Q
 assembly: fd, fs1, fs2, rm
 encoding:
diff --git a/spec/std/isa/inst/Q/fclass.q.yaml b/spec/std/isa/inst/Q/fclass.q.yaml
index f90689ffeb..46c83c0df2 100644
--- a/spec/std/isa/inst/Q/fclass.q.yaml
+++ b/spec/std/isa/inst/Q/fclass.q.yaml
@@ -7,34 +7,31 @@ $schema: "inst_schema.json#"
 kind: instruction
 name: fclass.q
 long_name: Floating-Point Classify Quad-Precision
-description:
-  - id: inst-fclass.q-behaviour
-    normative: false
-    text: |
-      The `fclass.q` instruction examines the value in floating-point register `rs1` and writes to integer
-      register `rd` a 10-bit mask that indicates the class of the floating-point number.
+description: |
+  The `fclass.q` instruction examines the value in floating-point register `rs1` and writes to integer
+  register `rd` a 10-bit mask that indicates the class of the floating-point number.
 
-      The format of the mask is described in table given below. The corresponding bit in `rd`
-      will be set if the property is true and clear otherwise. All other bits in `rd` are cleared.
+  The format of the mask is described in table given below. The corresponding bit in `rd`
+  will be set if the property is true and clear otherwise. All other bits in `rd` are cleared.
 
-      Note that exactly one bit in `rd` will be set. `fclass.q` does not set the floating-point
-      exception flags.
+  Note that exactly one bit in `rd` will be set. `fclass.q` does not set the floating-point
+  exception flags.
 
-      .Format of result of `fclass` instruction.
-      [%autowidth,float="center",align="center",cols="^,<",options="header",]
-      |===
-      |_xd_ bit |Meaning
-      |0 |_fs1_ is latexmath:[$-\infty$].
-      |1 |_fs1_ is a negative normal number.
-      |2 |_fs1_ is a negative subnormal number.
-      |3 |_fs1_ is latexmath:[$-0$].
-      |4 |_fs1_ is latexmath:[$+0$].
-      |5 |_fs1_ is a positive subnormal number.
-      |6 |_fs1_ is a positive normal number.
-      |7 |_fs1_ is latexmath:[$+\infty$].
-      |8 |_fs1_ is a signaling NaN.
-      |9 |_fs1_ is a quiet NaN.
-      |===
+  .Format of result of `fclass` instruction.
+  [%autowidth,float="center",align="center",cols="^,<",options="header",]
+  |===
+  |_xd_ bit |Meaning
+  |0 |_fs1_ is latexmath:[$-\infty$].
+  |1 |_fs1_ is a negative normal number.
+  |2 |_fs1_ is a negative subnormal number.
+  |3 |_fs1_ is latexmath:[$-0$].
+  |4 |_fs1_ is latexmath:[$+0$].
+  |5 |_fs1_ is a positive subnormal number.
+  |6 |_fs1_ is a positive normal number.
+  |7 |_fs1_ is latexmath:[$+\infty$].
+  |8 |_fs1_ is a signaling NaN.
+  |9 |_fs1_ is a quiet NaN.
+  |===
 definedBy: Q
 assembly: xd, fs1
 encoding:
diff --git a/spec/std/isa/inst/Q/fcvt.d.q.yaml b/spec/std/isa/inst/Q/fcvt.d.q.yaml
index dce4d2d3c8..faab1fbdda 100644
--- a/spec/std/isa/inst/Q/fcvt.d.q.yaml
+++ b/spec/std/isa/inst/Q/fcvt.d.q.yaml
@@ -7,11 +7,8 @@ $schema: "inst_schema.json#"
 kind: instruction
 name: fcvt.d.q
 long_name: Floating-Point Convert Quad-Precision to Double-Precision
-description:
-  - id: inst-fcvt.d.q-behaviour
-    normative: false
-    text: |
-      `fcvt.d.q` converts a quad-precision floating-point number to a double-precision floating-point number.
+description: |
+  `fcvt.d.q` converts a quad-precision floating-point number to a double-precision floating-point number.
 definedBy: Q
 assembly: fd, fs1, rm
 encoding:
diff --git a/spec/std/isa/inst/Q/fcvt.h.q.yaml b/spec/std/isa/inst/Q/fcvt.h.q.yaml
index 4db0843108..09378db905 100644
--- a/spec/std/isa/inst/Q/fcvt.h.q.yaml
+++ b/spec/std/isa/inst/Q/fcvt.h.q.yaml
@@ -7,11 +7,8 @@ $schema: "inst_schema.json#"
 kind: instruction
 name: fcvt.h.q
 long_name: Floating-point Convert Quad-precision to Half-precision
-description:
-  - id: inst-fcvt.h.q-behaviour
-    normative: false
-    text: |
-      `fcvt.h.q` converts a Quad-precision Floating-point number to a Half-precision Floating-point number.
+description: |
+  `fcvt.h.q` converts a Quad-precision Floating-point number to a Half-precision Floating-point number.
 definedBy:
   allOf: [Q, Zfh]
 assembly: fd, fs1, rm
diff --git a/spec/std/isa/inst/Q/fcvt.l.q.yaml b/spec/std/isa/inst/Q/fcvt.l.q.yaml
index ebc357bf93..d9dd08585b 100644
--- a/spec/std/isa/inst/Q/fcvt.l.q.yaml
+++ b/spec/std/isa/inst/Q/fcvt.l.q.yaml
@@ -7,11 +7,8 @@ $schema: "inst_schema.json#"
 kind: instruction
 name: fcvt.l.q
 long_name: Floating-Point Convert Quad-Precision to Long
-description:
-  - id: inst-fcvt.l.q-behaviour
-    normative: false
-    text: |
-      `fcvt.l.q` converts a quad-precision floating-point number to a signed 64-bit integer.
+description: |
+  `fcvt.l.q` converts a quad-precision floating-point number to a signed 64-bit integer.
 definedBy: Q
 base: 64
 assembly: xd, fs1, rm
diff --git a/spec/std/isa/inst/Q/fcvt.lu.q.yaml b/spec/std/isa/inst/Q/fcvt.lu.q.yaml
index 6932832d11..9028a2fde2 100644
--- a/spec/std/isa/inst/Q/fcvt.lu.q.yaml
+++ b/spec/std/isa/inst/Q/fcvt.lu.q.yaml
@@ -7,11 +7,8 @@ $schema: "inst_schema.json#"
 kind: instruction
 name: fcvt.lu.q
 long_name: Floating-Point Convert Quad-Precision to Unsigned Long
-description:
-  - id: inst-fcvt.lu.q-behaviour
-    normative: false
-    text: |
-      `fcvt.lu.q` converts a quad-precision floating-point number to an unsigned 64-bit integer.
+description: |
+  `fcvt.lu.q` converts a quad-precision floating-point number to an unsigned 64-bit integer.
 definedBy: Q
 base: 64
 assembly: xd, fs1, rm
diff --git a/spec/std/isa/inst/Q/fcvt.q.d.yaml b/spec/std/isa/inst/Q/fcvt.q.d.yaml
index 09dfd8d5ec..b6784feaa8 100644
--- a/spec/std/isa/inst/Q/fcvt.q.d.yaml
+++ b/spec/std/isa/inst/Q/fcvt.q.d.yaml
@@ -7,11 +7,8 @@ $schema: "inst_schema.json#"
 kind: instruction
 name: fcvt.q.d
 long_name: Floating-Point Convert Double-Precision to Quad-Precision
-description:
-  - id: inst-fcvt.q.d-behaviour
-    normative: false
-    text: |
-      `fcvt.d.q` converts a double-precision floating-point number to a quad-precision floating-point number.
+description: |
+  `fcvt.d.q` converts a double-precision floating-point number to a quad-precision floating-point number.
 definedBy: Q
 assembly: fd, fs1, rm
 encoding:
diff --git a/spec/std/isa/inst/Q/fcvt.q.h.yaml b/spec/std/isa/inst/Q/fcvt.q.h.yaml
index 9f13280fa4..4a163817a3 100644
--- a/spec/std/isa/inst/Q/fcvt.q.h.yaml
+++ b/spec/std/isa/inst/Q/fcvt.q.h.yaml
@@ -7,11 +7,8 @@ $schema: "inst_schema.json#"
 kind: instruction
 name: fcvt.q.h
 long_name: Floating-point Convert Half-precision to Quad-precision
-description:
-  - id: inst-fcvt.q.h-behaviour
-    normative: false
-    text: |
-      `fcvt.q.h` converts a half-precision floating-point number to a quad-precision floating-point number.
+description: |
+  `fcvt.q.h` converts a half-precision floating-point number to a quad-precision floating-point number.
 definedBy:
   allOf: [Q, Zfh]
 assembly: fd, fs1, rm
diff --git a/spec/std/isa/inst/Q/fcvt.q.l.yaml b/spec/std/isa/inst/Q/fcvt.q.l.yaml
index 73892d4283..6721c46455 100644
--- a/spec/std/isa/inst/Q/fcvt.q.l.yaml
+++ b/spec/std/isa/inst/Q/fcvt.q.l.yaml
@@ -7,11 +7,8 @@ $schema: "inst_schema.json#"
 kind: instruction
 name: fcvt.q.l
 long_name: Floating-Point Convert Long to Quad-Precision
-description:
-  - id: inst-fcvt.q.l-behaviour
-    normative: false
-    text: |
-      `fcvt.q.l` converts a 64-bit signed integer, into a quad-precision floating-point number.
+description: |
+  `fcvt.q.l` converts a 64-bit signed integer, into a quad-precision floating-point number.
 definedBy: Q
 base: 64
 assembly: fd, xs1, rm
diff --git a/spec/std/isa/inst/Q/fcvt.q.lu.yaml b/spec/std/isa/inst/Q/fcvt.q.lu.yaml
index 9b33f969f6..21350ae05e 100644
--- a/spec/std/isa/inst/Q/fcvt.q.lu.yaml
+++ b/spec/std/isa/inst/Q/fcvt.q.lu.yaml
@@ -7,11 +7,8 @@ $schema: "inst_schema.json#"
 kind: instruction
 name: fcvt.q.lu
 long_name: Floating-Point Convert Unsigned Long to Quad-Precision
-description:
-  - id: inst-fcvt.q.lu-behaviour
-    normative: false
-    text: |
-      `fcvt.q.lu` converts a 64-bit unsigned integer, into a quad-precision floating-point number.
+description: |
+  `fcvt.q.lu` converts a 64-bit unsigned integer, into a quad-precision floating-point number.
 definedBy: Q
 base: 64
 assembly: fd, xs1, rm
diff --git a/spec/std/isa/inst/Q/fcvt.q.s.yaml b/spec/std/isa/inst/Q/fcvt.q.s.yaml
index bd0d3ad6c8..19cc2487f6 100644
--- a/spec/std/isa/inst/Q/fcvt.q.s.yaml
+++ b/spec/std/isa/inst/Q/fcvt.q.s.yaml
@@ -7,11 +7,8 @@ $schema: "inst_schema.json#"
 kind: instruction
 name: fcvt.q.s
 long_name: Floating-Point Convert Single-Precision to Quad-Precision
-description:
-  - id: inst-fcvt.q.s-behaviour
-    normative: false
-    text: |
-      `fcvt.q.s` converts a single-precision floating-point number to a quad-precision floating-point number.
+description: |
+  `fcvt.q.s` converts a single-precision floating-point number to a quad-precision floating-point number.
 definedBy: Q
 assembly: fd, fs1, rm
 encoding:
diff --git a/spec/std/isa/inst/Q/fcvt.q.w.yaml b/spec/std/isa/inst/Q/fcvt.q.w.yaml
index fb21ed17dd..e8e0bf817d 100644
--- a/spec/std/isa/inst/Q/fcvt.q.w.yaml
+++ b/spec/std/isa/inst/Q/fcvt.q.w.yaml
@@ -7,11 +7,8 @@ $schema: "inst_schema.json#"
 kind: instruction
 name: fcvt.q.w
 long_name: Floating-Point Convert Word to Quad-Precision
-description:
-  - id: inst-fcvt.q.w-behaviour
-    normative: false
-    text: |
-      `fcvt.q.w` converts a 32-bit signed integer into a quad-precision floating-point number.
+description: |
+  `fcvt.q.w` converts a 32-bit signed integer into a quad-precision floating-point number.
 definedBy: Q
 assembly: fd, xs1, rm
 encoding:
diff --git a/spec/std/isa/inst/Q/fcvt.q.wu.yaml b/spec/std/isa/inst/Q/fcvt.q.wu.yaml
index 910afefd81..0d3483a324 100644
--- a/spec/std/isa/inst/Q/fcvt.q.wu.yaml
+++ b/spec/std/isa/inst/Q/fcvt.q.wu.yaml
@@ -7,11 +7,8 @@ $schema: "inst_schema.json#"
 kind: instruction
 name: fcvt.q.wu
 long_name: Floating-Point Convert Unsigned Word to Quad-Precision
-description:
-  - id: inst-fcvt.q.wu-behaviour
-    normative: false
-    text: |
-      `fcvt.q.wu` converts a 32-bit unsigned integer into a quad-precision floating-point number.
+description: |
+  `fcvt.q.wu` converts a 32-bit unsigned integer into a quad-precision floating-point number.
 definedBy: Q
 assembly: fd, xs1, rm
 encoding:
diff --git a/spec/std/isa/inst/Q/fcvt.s.q.yaml b/spec/std/isa/inst/Q/fcvt.s.q.yaml
index 7c9f2d05fb..fc04f4b0e1 100644
--- a/spec/std/isa/inst/Q/fcvt.s.q.yaml
+++ b/spec/std/isa/inst/Q/fcvt.s.q.yaml
@@ -7,11 +7,8 @@ $schema: "inst_schema.json#"
 kind: instruction
 name: fcvt.s.q
 long_name: Floating-Point Convert Quad-Precision to Single-Precision
-description:
-  - id: inst-fcvt.s.q-behaviour
-    normative: false
-    text: |
-      `fcvt.s.q` converts a quad-precision floating-point number to a single-precision floating-point number.
+description: |
+  `fcvt.s.q` converts a quad-precision floating-point number to a single-precision floating-point number.
 definedBy: Q
 assembly: fd, fs1, rm
 encoding:
diff --git a/spec/std/isa/inst/Q/fcvt.w.q.yaml b/spec/std/isa/inst/Q/fcvt.w.q.yaml
index 6d93deef8b..c50c6f9a84 100644
--- a/spec/std/isa/inst/Q/fcvt.w.q.yaml
+++ b/spec/std/isa/inst/Q/fcvt.w.q.yaml
@@ -7,11 +7,8 @@ $schema: "inst_schema.json#"
 kind: instruction
 name: fcvt.w.q
 long_name: Floating-point Convert Quad-precision to Word
-description:
-  - id: inst-fcvt.w.q-behaviour
-    normative: false
-    text: |
-      `fcvt.w.q` converts a quad-precision floating-point number to a 32-bit signed integer.
+description: |
+  `fcvt.w.q` converts a quad-precision floating-point number to a 32-bit signed integer.
 definedBy: Q
 assembly: xd, fs1, rm
 encoding:
diff --git a/spec/std/isa/inst/Q/fcvt.wu.q.yaml b/spec/std/isa/inst/Q/fcvt.wu.q.yaml
index f0c958c834..278b9de9e3 100644
--- a/spec/std/isa/inst/Q/fcvt.wu.q.yaml
+++ b/spec/std/isa/inst/Q/fcvt.wu.q.yaml
@@ -7,11 +7,8 @@ $schema: "inst_schema.json#"
 kind: instruction
 name: fcvt.wu.q
 long_name: Floating-Point Convert Unsigned Quad-Precision to Word
-description:
-  - id: inst-fcvt.wu.q-behaviour
-    normative: false
-    text: |
-      `fcvt.wu.q` converts a quad-precision floating-point number to a 32-bit unsigned integer.
+description: |
+  `fcvt.wu.q` converts a quad-precision floating-point number to a 32-bit unsigned integer.
 definedBy: Q
 assembly: xd, fs1, rm
 encoding:
diff --git a/spec/std/isa/inst/Q/fdiv.q.yaml b/spec/std/isa/inst/Q/fdiv.q.yaml
index a174ae529c..aebb5af299 100644
--- a/spec/std/isa/inst/Q/fdiv.q.yaml
+++ b/spec/std/isa/inst/Q/fdiv.q.yaml
@@ -7,18 +7,15 @@ $schema: "inst_schema.json#"
 kind: instruction
 name: fdiv.q
 long_name: Floating-Point Divide Quad-Precision
-description:
-  - id: inst-fdiv.q-behaviour
-    normative: false
-    text: |
-      The `fdiv.q` performs the quad-precision floating-point division of `fs1` by `fs2` and writes
-      the result to floating-point register `fd`.`
-      The rounding mode is specified by the value in the floating-point Control and Status register (FCSR)
-      or by the value in the `rm` field of the instruction.
+description: |
+  The `fdiv.q` performs the quad-precision floating-point division of `fs1` by `fs2` and writes
+  the result to floating-point register `fd`.`
+  The rounding mode is specified by the value in the floating-point Control and Status register (FCSR)
+  or by the value in the `rm` field of the instruction.
 
-      The operation is performed according to the IEEE 754-2008 standard for quad-precision floating-point arithmetic.
+  The operation is performed according to the IEEE 754-2008 standard for quad-precision floating-point arithmetic.
 
-      The instruction sets the floating-point exception flags according to the result of the operation.
+  The instruction sets the floating-point exception flags according to the result of the operation.
 definedBy: Q
 assembly: fd, fs1, fs2, rm
 encoding:
diff --git a/spec/std/isa/inst/Q/feq.q.yaml b/spec/std/isa/inst/Q/feq.q.yaml
index 62b073256a..d81586003f 100644
--- a/spec/std/isa/inst/Q/feq.q.yaml
+++ b/spec/std/isa/inst/Q/feq.q.yaml
@@ -7,16 +7,13 @@ $schema: "inst_schema.json#"
 kind: instruction
 name: feq.q
 long_name: Floating-Point Equal Quad-Precision
-description:
-  - id: inst-feq.q-behaviour
-    normative: false
-    text: |
-      The `feq.q` performs the specified comparison between floating-point registers `fs1` and `fs2`,
-      and writes 1 to integer register `xd` if the conditon hold, and 0 otherwise.
+description: |
+  The `feq.q` performs the specified comparison between floating-point registers `fs1` and `fs2`,
+  and writes 1 to integer register `xd` if the conditon hold, and 0 otherwise.
 
-      `feq.q` performs a quiet comparison:
-      it only sets the invalid operation exception flag if either input is a signaling _NaN_.
-      The result is 0 if either operand is _NaN_.
+  `feq.q` performs a quiet comparison:
+  it only sets the invalid operation exception flag if either input is a signaling _NaN_.
+  The result is 0 if either operand is _NaN_.
 definedBy: Q
 assembly: xd, fs1, fs2
 encoding:
diff --git a/spec/std/isa/inst/Q/fle.q.yaml b/spec/std/isa/inst/Q/fle.q.yaml
index cbeb2867b1..771eb79e1f 100644
--- a/spec/std/isa/inst/Q/fle.q.yaml
+++ b/spec/std/isa/inst/Q/fle.q.yaml
@@ -7,16 +7,13 @@ $schema: "inst_schema.json#"
 kind: instruction
 name: fle.q
 long_name: Floating-Point Less Than or Equal Quad-Precision
-description:
-  - id: inst-fle.q-behaviour
-    normative: false
-    text: |
-      The `fle.q` performs the specified comparison between floating-point registers `fs1` and `fs2`,
-      and writes 1 to integer register `xd` if the condition holds, and 0 otherwise.
+description: |
+  The `fle.q` performs the specified comparison between floating-point registers `fs1` and `fs2`,
+  and writes 1 to integer register `xd` if the condition holds, and 0 otherwise.
 
-      `fle.q` performs what the IEEE 754-2008 standard refers to as signaling comparisons: that is,
-      they set the invalid operation exception flag if either input is _NaN_.
-      The result is 0 if either operand is _NaN_.
+  `fle.q` performs what the IEEE 754-2008 standard refers to as signaling comparisons: that is,
+  they set the invalid operation exception flag if either input is _NaN_.
+  The result is 0 if either operand is _NaN_.
 definedBy: Q
 assembly: xd, fs1, fs2
 encoding:
diff --git a/spec/std/isa/inst/Q/fleq.q.yaml b/spec/std/isa/inst/Q/fleq.q.yaml
index 6d2ccb449c..03da207245 100644
--- a/spec/std/isa/inst/Q/fleq.q.yaml
+++ b/spec/std/isa/inst/Q/fleq.q.yaml
@@ -7,16 +7,13 @@ $schema: "inst_schema.json#"
 kind: instruction
 name: fleq.q
 long_name: Floating-Point Less Than or Equal Quiet Quad-Precision
-description:
-  - id: inst-fleq.q-behaviour
-    normative: false
-    text: |
-      The `fleq.q` performs the specified comparison between floating-point registers `fs1` and `fs2`,
-      and writes 1 to integer register `xd` if the condition holds, and 0 otherwise.
+description: |
+  The `fleq.q` performs the specified comparison between floating-point registers `fs1` and `fs2`,
+  and writes 1 to integer register `xd` if the condition holds, and 0 otherwise.
 
-      `fleq.q` is defined like `fle.q`, except that quiet _NaN_ inputs do not cause the invalid
-      operation exception flag to be set.
-      This instruction is encoded like its `flt` counterpart, but with instruction bit 14 set to 1.
+  `fleq.q` is defined like `fle.q`, except that quiet _NaN_ inputs do not cause the invalid
+  operation exception flag to be set.
+  This instruction is encoded like its `flt` counterpart, but with instruction bit 14 set to 1.
 definedBy:
   allOf: [Q, Zfa]
 assembly: xd, fs1, fs2
diff --git a/spec/std/isa/inst/Q/fli.q.yaml b/spec/std/isa/inst/Q/fli.q.yaml
index adf922203f..168551d1ed 100644
--- a/spec/std/isa/inst/Q/fli.q.yaml
+++ b/spec/std/isa/inst/Q/fli.q.yaml
@@ -7,14 +7,10 @@ $schema: "inst_schema.json#"
 kind: instruction
 name: fli.q
 long_name: Floating-Point Load Immediate Quad-Precision
-description:
-  - id: inst-fli.q-behaviour
-    normative: false
-    text: |
-      The
-      The `fli.q` instruction loads one of 32 quad-precision floating-point constants, encoded in the `rs1`
-      field, into floating-point register `rd`.
-      `fli.q` is encoded like `fmv.w.x`, but with _fmt_ = Q.
+description: |
+  The `fli.q` instruction loads one of 32 quad-precision floating-point constants, encoded in the `xs1`
+  field, into floating-point register `rd`.
+  `fli.q` is encoded like `fmv.w.x`, but with _fmt_ = Q.
 definedBy:
   allOf: [Q, Zfa]
 assembly: fd, xs1
diff --git a/spec/std/isa/inst/Q/flq.yaml b/spec/std/isa/inst/Q/flq.yaml
index ea18a17d69..964b46d1be 100644
--- a/spec/std/isa/inst/Q/flq.yaml
+++ b/spec/std/isa/inst/Q/flq.yaml
@@ -7,16 +7,13 @@ $schema: "inst_schema.json#"
 kind: instruction
 name: flq
 long_name: Floating-Point Load Quad-Precision
-description:
-  - id: inst-flq-behaviour
-    normative: false
-    text: |
-      The `flq` is the new variant of LOAD-FP, encoded with a new value for the `funct3`.
+description: |
+  The `flq` is the new variant of LOAD-FP, encoded with a new value for the `funct3`.
 
-      `flq` is only guaranteed to execute atomically if the effective address is naturally aligned XLEN=128.
+  `flq` is only guaranteed to execute atomically if the effective address is naturally aligned XLEN=128.
 
-      `flq` does not modify the bits being transferred; in particular, the payloads of non-canonical
-      _NaNs_ are preserved.
+  `flq` does not modify the bits being transferred; in particular, the payloads of non-canonical
+  _NaNs_ are preserved.
 definedBy: Q
 assembly: fd, xs1, imm
 encoding:
diff --git a/spec/std/isa/inst/Q/flt.q.yaml b/spec/std/isa/inst/Q/flt.q.yaml
index 1eb4dea6a7..c4f4cec73d 100644
--- a/spec/std/isa/inst/Q/flt.q.yaml
+++ b/spec/std/isa/inst/Q/flt.q.yaml
@@ -7,16 +7,13 @@ $schema: "inst_schema.json#"
 kind: instruction
 name: flt.q
 long_name: Floating-Point Less Than Quad-Precision
-description:
-  - id: inst-flt.q-behaviour
-    normative: false
-    text: |
-      The `flt.q` performs the specified comparison between floating-point registers `fs1` and `fs2`,
-      and writes 1 to integer register `xd` if the conditon hold, and 0 otherwise.
+description: |
+  The `flt.q` performs the specified comparison between floating-point registers `fs1` and `fs2`,
+  and writes 1 to integer register `xd` if the conditon hold, and 0 otherwise.
 
-      `flt.q` performs what the IEEE 754-2008 standard refers to as signaling comparisons: that is,
-      they set the invalid operation exception flag if either input is _NaN_.
-      The result is 0 if either operand is _NaN_.
+  `flt.q` performs what the IEEE 754-2008 standard refers to as signaling comparisons: that is,
+  they set the invalid operation exception flag if either input is _NaN_.
+  The result is 0 if either operand is _NaN_.
 definedBy: Q
 assembly: xd, fs1, fs2
 encoding:
diff --git a/spec/std/isa/inst/Q/fltq.q.yaml b/spec/std/isa/inst/Q/fltq.q.yaml
index ad9a6ccca6..8e9b6d4650 100644
--- a/spec/std/isa/inst/Q/fltq.q.yaml
+++ b/spec/std/isa/inst/Q/fltq.q.yaml
@@ -7,16 +7,13 @@ $schema: "inst_schema.json#"
 kind: instruction
 name: fltq.q
 long_name: Floating-Point Less Than Quiet Quad-Precision
-description:
-  - id: inst-fltq.q-behaviour
-    normative: false
-    text: |
-      The `fltq.q` performs the specified comparison between floating-point registers `fs1` and `fs2`,
-      and writes 1 to integer register `xd` if the condition holds, and 0 otherwise.
+description: |
+  The `fltq.q` performs the specified comparison between floating-point registers `fs1` and `fs2`,
+  and writes 1 to integer register `xd` if the condition holds, and 0 otherwise.
 
-      `fltq.q` is defined like `flt.q`, except that quiet _NaN_ inputs do not cause the invalid
-      operation exception flag to be set.
-      This instruction is encoded like its `fle` counterpart, but with instruction bit 14 set to 1.
+  `fltq.q` is defined like `flt.q`, except that quiet _NaN_ inputs do not cause the invalid
+  operation exception flag to be set.
+  This instruction is encoded like its `fle` counterpart, but with instruction bit 14 set to 1.
 definedBy:
   allOf: [Q, Zfa]
 assembly: fd, fs1, fs2
diff --git a/spec/std/isa/inst/Q/fmadd.q.yaml b/spec/std/isa/inst/Q/fmadd.q.yaml
index fb56f7969c..ddf78562b0 100644
--- a/spec/std/isa/inst/Q/fmadd.q.yaml
+++ b/spec/std/isa/inst/Q/fmadd.q.yaml
@@ -7,15 +7,12 @@ $schema: "inst_schema.json#"
 kind: instruction
 name: fmadd.q
 long_name: Floating-Point Multiply-Add Quad-Precision
-description:
-  - id: inst-fmadd.q-behaviour
-    normative: true
-    text: |
-      The `fmadd.q` instruction performs a floating-point multiply-add operation on the values in registers `fs1`, `fs2`, and `fs3`.
-      It computes the result as `(fs1 * fs2) + fs3` and writes the result to the destination register `fd`.
+description: |
+  The `fmadd.q` instruction performs a floating-point multiply-add operation on the values in registers `fs1`, `fs2`, and `fs3`.
+  It computes the result as `(fs1 * fs2) + fs3` and writes the result to the destination register `fd`.
 
-      The fused multiply-add instructions must set the invalid operation exception flag when the
-      multiplicands are latexmath:[$\infty$] and zero, even when the addend is a quiet _NaN_.
+  The fused multiply-add instructions must set the invalid operation exception flag when the
+  multiplicands are latexmath:[$\infty$] and zero, even when the addend is a quiet _NaN_.
 definedBy: Q
 assembly: fd, fs1, fs2, fs3, rm
 encoding:
diff --git a/spec/std/isa/inst/Q/fmax.q.yaml b/spec/std/isa/inst/Q/fmax.q.yaml
index 0a4b0e46c2..cd69c92048 100644
--- a/spec/std/isa/inst/Q/fmax.q.yaml
+++ b/spec/std/isa/inst/Q/fmax.q.yaml
@@ -7,15 +7,12 @@ $schema: "inst_schema.json#"
 kind: instruction
 name: fmax.q
 long_name: Floating-Point Maximum-Number Quad-Precision
-description:
-  - id: inst-fmax.q-behaviour
-    normative: false
-    text: |
-      The `fmax.q` instruction writes the larger/maximum of `fs1` and `fs2` to `fd`.
-      The value `-0.0` is considered to be less than the value `+0.0`.
-      If both inputs are _NaN_s, the result is the canonical _NaN_.
-      If only one operand is a _NaN_, the result is the non-_NaN_ operand.
-      Signaling _NaN_ inputs set the invalid operation exception flag, even when the result is not _NaN_.
+description: |
+  The `fmax.q` instruction writes the larger/maximum of `fs1` and `fs2` to `fd`.
+  The value `-0.0` is considered to be less than the value `+0.0`.
+  If both inputs are _NaN_s, the result is the canonical _NaN_.
+  If only one operand is a _NaN_, the result is the non-_NaN_ operand.
+  Signaling _NaN_ inputs set the invalid operation exception flag, even when the result is not _NaN_.
 definedBy: Q
 assembly: fd, fs1, fs2
 encoding:
diff --git a/spec/std/isa/inst/Q/fmaxm.q.yaml b/spec/std/isa/inst/Q/fmaxm.q.yaml
index cb45a01486..ae5d490e72 100644
--- a/spec/std/isa/inst/Q/fmaxm.q.yaml
+++ b/spec/std/isa/inst/Q/fmaxm.q.yaml
@@ -7,16 +7,13 @@ $schema: "inst_schema.json#"
 kind: instruction
 name: fmaxm.q
 long_name: Floating-Point Maximum-Number NaN Quad-Precision
-description:
-  - id: inst-fmaxm.q-behaviour
-    normative: false
-    text: |
-      The `fmaxm.q` instruction, defined like `fmax.q`, writes the larger/maximum of `fs1` and `fs2` to `fd`.
-      The value `-0.0` is considered to be less than the value `+0.0`.
-      If both inputs are _NaN_s, the result is the canonical _NaN_.
-      If either input is _NaN_, the result is the canonical _NaN_.
-      Signaling _NaN_ inputs set the invalid operation exception flag, even when the result is not _NaN_.
-      This instruction is encoded like its `fminm.q` counterpart, but with instruction bit 14 set to 1.
+description: |
+  The `fmaxm.q` instruction, defined like `fmax.q`, writes the larger/maximum of `fs1` and `fs2` to `fd`.
+  The value `-0.0` is considered to be less than the value `+0.0`.
+  If both inputs are _NaN_s, the result is the canonical _NaN_.
+  If either input is _NaN_, the result is the canonical _NaN_.
+  Signaling _NaN_ inputs set the invalid operation exception flag, even when the result is not _NaN_.
+  This instruction is encoded like its `fminm.q` counterpart, but with instruction bit 14 set to 1.
 definedBy:
   allOf: [Q, Zfa]
 assembly: fd, fs1, fs2
diff --git a/spec/std/isa/inst/Q/fmin.q.yaml b/spec/std/isa/inst/Q/fmin.q.yaml
index dc5ccfbd18..f91262a691 100644
--- a/spec/std/isa/inst/Q/fmin.q.yaml
+++ b/spec/std/isa/inst/Q/fmin.q.yaml
@@ -7,15 +7,12 @@ $schema: "inst_schema.json#"
 kind: instruction
 name: fmin.q
 long_name: Floating-Point Minimum-Number Quad-Precision
-description:
-  - id: inst-fmin.q-behaviour
-    normative: false
-    text: |
-      The `fmin.q` instruction writes the smaller/minimum of `fs1` and `fs2` to `fd`.
-      The value `-0.0` is considered to be less than the value `+0.0`.
-      If both inputs are _NaN_s, the result is the canonical _NaN_.
-      If only one operand is a _NaN_, the result is the non-_NaN_ operand.
-      Signaling _NaN_ inputs set the invalid operation exception flag, even when the result is not _NaN_.
+description: |
+  The `fmin.q` instruction writes the smaller/minimum of `fs1` and `fs2` to `fd`.
+  The value `-0.0` is considered to be less than the value `+0.0`.
+  If both inputs are _NaN_s, the result is the canonical _NaN_.
+  If only one operand is a _NaN_, the result is the non-_NaN_ operand.
+  Signaling _NaN_ inputs set the invalid operation exception flag, even when the result is not _NaN_.
 definedBy: Q
 assembly: fd, fs1, fs2
 encoding:
diff --git a/spec/std/isa/inst/Q/fminm.q.yaml b/spec/std/isa/inst/Q/fminm.q.yaml
index efa3448f3d..c945d38a30 100644
--- a/spec/std/isa/inst/Q/fminm.q.yaml
+++ b/spec/std/isa/inst/Q/fminm.q.yaml
@@ -7,16 +7,13 @@ $schema: "inst_schema.json#"
 kind: instruction
 name: fminm.q
 long_name: Floating-Point Minimum-Number NaN Quad-Precision
-description:
-  - id: inst-fminm.q-behaviour
-    normative: false
-    text: |
-      The `fminm.q` instruction, defined like `fmin.q`, writes the smaller/minimum of `fs1` and `fs2` to `fd`.
-      The value `-0.0` is considered to be less than the value `+0.0`.
-      If both inputs are _NaN_s, the result is the canonical _NaN_.
-      If either input is _NaN_, the result is the canonical _NaN_.
-      Signaling _NaN_ inputs set the invalid operation exception flag, even when the result is not _NaN_.
-      This instruction is encoded like its `fminm.q` counterpart, but with instruction bit 14 set to 1.
+description: |
+  The `fminm.q` instruction, defined like `fmin.q`, writes the smaller/minimum of `fs1` and `fs2` to `fd`.
+  The value `-0.0` is considered to be less than the value `+0.0`.
+  If both inputs are _NaN_s, the result is the canonical _NaN_.
+  If either input is _NaN_, the result is the canonical _NaN_.
+  Signaling _NaN_ inputs set the invalid operation exception flag, even when the result is not _NaN_.
+  This instruction is encoded like its `fminm.q` counterpart, but with instruction bit 14 set to 1.
 definedBy:
   allOf: [Q, Zfa]
 assembly: fd, fs1, fs2
diff --git a/spec/std/isa/inst/Q/fmsub.q.yaml b/spec/std/isa/inst/Q/fmsub.q.yaml
index 041b236373..fe9318a108 100644
--- a/spec/std/isa/inst/Q/fmsub.q.yaml
+++ b/spec/std/isa/inst/Q/fmsub.q.yaml
@@ -7,12 +7,9 @@ $schema: "inst_schema.json#"
 kind: instruction
 name: fmsub.q
 long_name: Floating-Point Multiply-Subtract Quad-Precision
-description:
-  - id: inst-fmsub.q-behaviour
-    normative: false
-    text: |
-      The `fmsub.q` instruction performs a floating-point multiply-subtract operation on the values in registers `fs1`, `fs2`, and `fs3`.
-      It computes the result as `(fs1 * fs2) - fs3` and writes the result to the destination register `fd`.
+description: |
+  The `fmsub.q` instruction performs a floating-point multiply-subtract operation on the values in registers `fs1`, `fs2`, and `fs3`.
+  It computes the result as `(fs1 * fs2) - fs3` and writes the result to the destination register `fd`.
 definedBy: Q
 assembly: fd, fs1, fs2, fs3, rm
 encoding:
diff --git a/spec/std/isa/inst/Q/fmul.q.yaml b/spec/std/isa/inst/Q/fmul.q.yaml
index 1943582f50..e3b8c33381 100644
--- a/spec/std/isa/inst/Q/fmul.q.yaml
+++ b/spec/std/isa/inst/Q/fmul.q.yaml
@@ -7,11 +7,8 @@ $schema: "inst_schema.json#"
 kind: instruction
 name: fmul.q
 long_name: Floating-point Multiply Quad-Precision
-description:
-  - id: inst-fmul.q-behaviour
-    normative: false
-    text: |
-      `fmul.q` performs quad-precision floating-point multiplication, between `fs1` and `fs2`.
+description: |
+  `fmul.q` performs quad-precision floating-point multiplication, between `fs1` and `fs2`.
 definedBy: Q
 assembly: fd, fs1, fs2, rm
 encoding:
diff --git a/spec/std/isa/inst/Q/fmvh.x.q.yaml b/spec/std/isa/inst/Q/fmvh.x.q.yaml
index 04608ba93f..92cdaadefc 100644
--- a/spec/std/isa/inst/Q/fmvh.x.q.yaml
+++ b/spec/std/isa/inst/Q/fmvh.x.q.yaml
@@ -7,15 +7,12 @@ $schema: "inst_schema.json#"
 kind: instruction
 name: fmvh.x.q
 long_name: Floating-Point Move High Half to Integer from Quad-Precision
-description:
-  - id: inst-fmvh.x.q-behaviour
-    normative: false
-    text: |
-      The `fmvh.x.q` instruction moves bits `127:64` of floating-point register `fs1` into integer register `xd`.
-      It is encoded in the OP-FP major opcode with _funct3_=0, _rs2_=1, and _funct7_=1110011.
+description: |
+  The `fmvh.x.q` instruction moves bits `127:64` of floating-point register `fs1` into integer register `xd`.
+  It is encoded in the OP-FP major opcode with _funct3_=0, _rs2_=1, and _funct7_=1110011.
 
-      `fmvh.x.q` is used in conjunction with the existing `fmv.x.d` instruction to move a quad-precision floating-point
-      number to a pair of x-registers.
+  `fmvh.x.q` is used in conjunction with the existing `fmv.x.d` instruction to move a quad-precision floating-point
+  number to a pair of x-registers.
 definedBy:
   allOf: [Q, Zfa]
 base: 64
diff --git a/spec/std/isa/inst/Q/fmvp.q.x.yaml b/spec/std/isa/inst/Q/fmvp.q.x.yaml
index a86f9ca4ad..7b0987ac1e 100644
--- a/spec/std/isa/inst/Q/fmvp.q.x.yaml
+++ b/spec/std/isa/inst/Q/fmvp.q.x.yaml
@@ -7,15 +7,12 @@ $schema: "inst_schema.json#"
 kind: instruction
 name: fmvp.q.x
 long_name: Floating-Point Move Pair from Integer Registers to Quad-Precision Register
-description:
-  - id: inst-fmvp.q.x-behaviour
-    normative: false
-    text: |
-      The `fmvp.q.x` instruction moves a double-precision number from a pair of integer registers into
-      a floating-point register.
-      Integer registers xs1 and xs2 supply bits 63:0 and 127:64, respectively; the result is written to
-      floating-point register `fd`.
-      `fmvp.q.x` is encoded in the OP-FP major opcode with _funct3_=0 and _funct7_=1011011.
+description: |
+  The `fmvp.q.x` instruction moves a double-precision number from a pair of integer registers into
+  a floating-point register.
+  Integer registers `xs1` and `xs2` supply bits 63:0 and 127:64, respectively; the result is written to
+  floating-point register `fd`.
+  `fmvp.q.x` is encoded in the OP-FP major opcode with _funct3_=0 and _funct7_=1011011.
 definedBy:
   allOf: [Q, Zfa]
 base: 64
diff --git a/spec/std/isa/inst/Q/fnmadd.q.yaml b/spec/std/isa/inst/Q/fnmadd.q.yaml
index 0886d79469..acde0cefb6 100644
--- a/spec/std/isa/inst/Q/fnmadd.q.yaml
+++ b/spec/std/isa/inst/Q/fnmadd.q.yaml
@@ -7,13 +7,10 @@ $schema: "inst_schema.json#"
 kind: instruction
 name: fnmadd.q
 long_name: Floating-Point Negate-Multiply-Add Quad-Precision
-description:
-  - id: inst-fnmadd.q-behaviour
-    normative: true
-    text: |
-      The `fnmadd.q` instruction multiplies the values in `fs1` and `fs2`, negates the product, adds the
-      value in `fs3`, and writes the final result to `fd`.
-      `fnmadd.q` computes `-(fs1 * fs2) + fs3`.
+description: |
+  The `fnmadd.q` instruction multiplies the values in `fs1` and `fs2`, negates the product, adds the
+  value in `fs3`, and writes the final result to `fd`.
+  `fnmadd.q` computes `-(fs1 * fs2) + fs3`.
 definedBy: Q
 assembly: fd, fs1, fs2, fs3, rm
 encoding:
diff --git a/spec/std/isa/inst/Q/fnmsub.q.yaml b/spec/std/isa/inst/Q/fnmsub.q.yaml
index bf666684f4..ffcfdc3f33 100644
--- a/spec/std/isa/inst/Q/fnmsub.q.yaml
+++ b/spec/std/isa/inst/Q/fnmsub.q.yaml
@@ -7,13 +7,10 @@ $schema: "inst_schema.json#"
 kind: instruction
 name: fnmsub.q
 long_name: Floating-Point Negate-Multiply-Subtract Quad-Precision
-description:
-  - id: inst-fnmsub.q-behaviour
-    normative: true
-    text: |
-      The `fnmsub.q` instruction multiplies the values in `fs1` and `fs2`, negates the product, subtracts the
-      value in `fs3`, and writes the final result to `fd`.
-      `fnmsub.q` computes `-(fs1 * fs2) - fs3`.
+description: |
+  The `fnmsub.q` instruction multiplies the values in `fs1` and `fs2`, negates the product, subtracts the
+  value in `fs3`, and writes the final result to `fd`.
+  `fnmsub.q` computes `-(fs1 * fs2) - fs3`.
 definedBy: Q
 assembly: fd, fs1, fs2, fs3, rm
 encoding:
diff --git a/spec/std/isa/inst/Q/fround.q.yaml b/spec/std/isa/inst/Q/fround.q.yaml
index ee3a3494b8..10ec271813 100644
--- a/spec/std/isa/inst/Q/fround.q.yaml
+++ b/spec/std/isa/inst/Q/fround.q.yaml
@@ -7,16 +7,13 @@ $schema: "inst_schema.json#"
 kind: instruction
 name: fround.q
 long_name: Floating-Point Round Quad-Precision
-description:
-  - id: inst-fround.q-behaviour
-    normative: false
-    text: |
-      The `fround.q` instruction rounds the quad-precision floating-point number in floating-point register
-      `fs1` to an integer, according to the rounding mode specified in the instruction's `rm` field. It then writes
-      that integer, represented as a quad-precision floating-point number, to floating-point register `fd`. Zero
-      and infinite inputs are copied to `fd` unmodified. Signaling _NaN_ inputs cause the invalid operation
-      exception flag to be set; no other exception flags are set. `fround.q` is encoded like `fcvt.q.s`, but with
-      `rs2`=4.
+description: |
+  The `fround.q` instruction rounds the quad-precision floating-point number in floating-point register
+  `fs1` to an integer, according to the rounding mode specified in the instruction's `rm` field. It then writes
+  that integer, represented as a quad-precision floating-point number, to floating-point register `fd`. Zero
+  and infinite inputs are copied to `fd` unmodified. Signaling _NaN_ inputs cause the invalid operation
+  exception flag to be set; no other exception flags are set. `fround.q` is encoded like `fcvt.q.s`, but with
+  `rs2`=4.
 definedBy:
   allOf: [Q, Zfa]
 assembly: fd, fs1, rm
diff --git a/spec/std/isa/inst/Q/froundnx.q.yaml b/spec/std/isa/inst/Q/froundnx.q.yaml
index a0ff34bbf7..2b03b9e38d 100644
--- a/spec/std/isa/inst/Q/froundnx.q.yaml
+++ b/spec/std/isa/inst/Q/froundnx.q.yaml
@@ -7,12 +7,9 @@ $schema: "inst_schema.json#"
 kind: instruction
 name: froundnx.q
 long_name: Floating-Point Round-to-Integer Inexact Quad-Precision
-description:
-  - id: inst-froundnx.q-behaviour
-    normative: false
-    text: |
-      The `froundnx.q` instruction is encoded like `fround.q` but with `rs2`=5 and it also sets the
-      inexact exception flag if the input differs from the rounded result and is not _NaN_.
+description: |
+  The `froundnx.q` instruction is encoded like `fround.q` but with `rs2`=5 and it also sets the
+  inexact exception flag if the input differs from the rounded result and is not _NaN_.
 definedBy:
   allOf: [Q, Zfa]
 assembly: fd, fs1, rm
diff --git a/spec/std/isa/inst/Q/fsgnj.q.yaml b/spec/std/isa/inst/Q/fsgnj.q.yaml
index d5199aa572..e01935eafc 100644
--- a/spec/std/isa/inst/Q/fsgnj.q.yaml
+++ b/spec/std/isa/inst/Q/fsgnj.q.yaml
@@ -7,13 +7,10 @@ $schema: "inst_schema.json#"
 kind: instruction
 name: fsgnj.q
 long_name: Floating-Point Sign-Inject Quad-Precision
-description:
-  - id: inst-fsgnj.q-behaviour
-    normative: false
-    text: |
-      The `fsgnj.q` instruction produces a result that takes all bits except the sign bit from `fs1`.
-      The result's sign bit is taken from `fs2`'s sign bit, and the result is written to the destination register `fd`.
-      `fsgnj.q` does not set floating-point exception flags, nor do they canonicalize _NaN_s.
+description: |
+  The `fsgnj.q` instruction produces a result that takes all bits except the sign bit from `fs1`.
+  The result's sign bit is taken from `fs2`'s sign bit, and the result is written to the destination register `fd`.
+  `fsgnj.q` does not set floating-point exception flags, nor do they canonicalize _NaN_s.
 definedBy: Q
 assembly: fd, fs1, fs2
 encoding:
diff --git a/spec/std/isa/inst/Q/fsgnjn.q.yaml b/spec/std/isa/inst/Q/fsgnjn.q.yaml
index 001eea8683..1609c07abc 100644
--- a/spec/std/isa/inst/Q/fsgnjn.q.yaml
+++ b/spec/std/isa/inst/Q/fsgnjn.q.yaml
@@ -7,13 +7,10 @@ $schema: "inst_schema.json#"
 kind: instruction
 name: fsgnjn.q
 long_name: Floating-Point Sign-Inject Negate Quad-Precision
-description:
-  - id: inst-fsgnjn.q-behaviour
-    normative: false
-    text: |
-      The `fsgnjn.q` instruction produces a result that takes all bits except the sign bit from `fs1`.
-      The result's sign bit is opposite of `fs2`'s sign bit, and the result is written to the destination register `fd`.
-      `fsgnjn.q` does not set floating-point exception flags, nor do they canonicalize _NaN_s.
+description: |
+  The `fsgnjn.q` instruction produces a result that takes all bits except the sign bit from `fs1`.
+  The result's sign bit is opposite of `fs2`'s sign bit, and the result is written to the destination register `fd`.
+  `fsgnjn.q` does not set floating-point exception flags, nor do they canonicalize _NaN_s.
 definedBy: Q
 assembly: fd, fs1, fs2
 encoding:
diff --git a/spec/std/isa/inst/Q/fsgnjx.q.yaml b/spec/std/isa/inst/Q/fsgnjx.q.yaml
index 4ed0142c78..468455157a 100644
--- a/spec/std/isa/inst/Q/fsgnjx.q.yaml
+++ b/spec/std/isa/inst/Q/fsgnjx.q.yaml
@@ -7,13 +7,10 @@ $schema: "inst_schema.json#"
 kind: instruction
 name: fsgnjx.q
 long_name: Floating-Point Sign-Inject XOR Quad-Precision
-description:
-  - id: inst-fsgnjx.q-behaviour
-    normative: false
-    text: |
-      The `fsgnjx.q` instruction produces a result that takes all bits except the sign bit from `fs1`.
-      The result's sign bit is the XOR of sign bits of `fs1` and `fs2`, and the result is written to the destination register `fd`.
-      `fsgnjx.q` does not set floating-point exception flags, nor do they canonicalize _NaN_s.
+description: |
+  The `fsgnjx.q` instruction produces a result that takes all bits except the sign bit from `fs1`.
+  The result's sign bit is the XOR of sign bits of `fs1` and `fs2`, and the result is written to the destination register `fd`.
+  `fsgnjx.q` does not set floating-point exception flags, nor do they canonicalize _NaN_s.
 definedBy: Q
 assembly: fd, fs1, fs2
 encoding:
diff --git a/spec/std/isa/inst/Q/fsq.yaml b/spec/std/isa/inst/Q/fsq.yaml
index e860ee335c..8c2938a84a 100644
--- a/spec/std/isa/inst/Q/fsq.yaml
+++ b/spec/std/isa/inst/Q/fsq.yaml
@@ -7,16 +7,13 @@ $schema: "inst_schema.json#"
 kind: instruction
 name: fsq
 long_name: Floating-Point Store Quad-Precision
-description:
-  - id: inst-fsq-behaviour
-    normative: false
-    text: |
-      The `fsq` is the new variant of LOAD-FP, encoded with a new value for the `funct3`.
+description: |
+  The `fsq` is the new variant of LOAD-FP, encoded with a new value for the `funct3`.
 
-      `fsq` is only guaranteed to execute atomically if the effective address is naturally aligned XLEN=128.
+  `fsq` is only guaranteed to execute atomically if the effective address is naturally aligned XLEN=128.
 
-      `fsq` does not modify the bits being transferred; in particular, the payloads of non-canonical
-      _NaNs_ are preserved.
+  `fsq` does not modify the bits being transferred; in particular, the payloads of non-canonical
+  _NaNs_ are preserved.
 definedBy: Q
 assembly: fs2, imm(xs1)
 encoding:
diff --git a/spec/std/isa/inst/Q/fsqrt.q.yaml b/spec/std/isa/inst/Q/fsqrt.q.yaml
index 7c7da52332..fe64ed980e 100644
--- a/spec/std/isa/inst/Q/fsqrt.q.yaml
+++ b/spec/std/isa/inst/Q/fsqrt.q.yaml
@@ -7,11 +7,8 @@ $schema: "inst_schema.json#"
 kind: instruction
 name: fsqrt.q
 long_name: Floating-Point Square Root Quad-Precision
-description:
-  - id: inst-fsqrt.q-behaviour
-    normative: false
-    text: |
-      The `fsqrt.q` instruction computes the square root of the value in `fs1` and writes the result to `fd`.
+description: |
+  The `fsqrt.q` instruction computes the square root of the value in `fs1` and writes the result to `fd`.
 definedBy: Q
 assembly: fd, fs1, rm
 encoding:
diff --git a/spec/std/isa/inst/Q/fsub.q.yaml b/spec/std/isa/inst/Q/fsub.q.yaml
index f2bc6dc0f0..3e0d50f6c3 100644
--- a/spec/std/isa/inst/Q/fsub.q.yaml
+++ b/spec/std/isa/inst/Q/fsub.q.yaml
@@ -7,12 +7,9 @@ $schema: "inst_schema.json#"
 kind: instruction
 name: fsub.q
 long_name: Floating-Point Subtract Quad-Precision
-description:
-  - id: inst-fsub.q-behaviour
-    normative: false
-    text: |
-      The `fsub.q` instruction performs the quad-precision floating-point subtraction of `fs2` from `fs1`.
-      It computes the result as `fs1 - fs2` and writes the result to the destination register `fd`.
+description: |
+  The `fsub.q` instruction performs the quad-precision floating-point subtraction of `fs2` from `fs1`.
+  It computes the result as `fs1 - fs2` and writes the result to the destination register `fd`.
 definedBy: Q
 assembly: fd, fs1, fs2, rm
 encoding:
diff --git a/spec/std/isa/inst/S/sret.yaml b/spec/std/isa/inst/S/sret.yaml
index 6583fa911b..b6e115103e 100644
--- a/spec/std/isa/inst/S/sret.yaml
+++ b/spec/std/isa/inst/S/sret.yaml
@@ -98,7 +98,7 @@ operation(): |
       }
     }
   } else {
-    if (mode() == PrivilegeMode::U) {
+    if (mode() != PrivilegeMode::U) {
       raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
     }
   }
@@ -107,25 +107,13 @@ operation(): |
   if (!virtual_mode?()) {
     if (implemented?(ExtensionName::H)) {
       if (CSR[hstatus].SPV == 1'b1) {
-        if (CSR[mstatus].SPP == 1'b1) {
+        if (CSR[mstatus].SPP == 2'b01) {
           set_mode(PrivilegeMode::VS);
-        } else {
+        } else if (CSR[mstatus].SPP == 2'b00) {
           set_mode(PrivilegeMode::VU);
         }
-      } else {
-        if (CSR[mstatus].SPP == 1'b1) {
-          set_mode(PrivilegeMode::S);
-        } else {
-          set_mode(PrivilegeMode::U);
-        }
       }
       CSR[hstatus].SPV = 0;
-    } else {
-      if (CSR[mstatus].SPP == 1'b1) {
-        set_mode(PrivilegeMode::S);
-      } else {
-        set_mode(PrivilegeMode::U);
-      }
     }
     CSR[mstatus].SIE = CSR[mstatus].SPIE;
     CSR[mstatus].SPIE = 1;
diff --git a/spec/std/isa/inst/Zfh/fcvt.h.d.yaml b/spec/std/isa/inst/Zfh/fcvt.h.d.yaml
index 59c69a45cc..96b39b400d 100644
--- a/spec/std/isa/inst/Zfh/fcvt.h.d.yaml
+++ b/spec/std/isa/inst/Zfh/fcvt.h.d.yaml
@@ -7,11 +7,8 @@ $schema: inst_schema.json#
 kind: instruction
 name: fcvt.h.d
 long_name: Floating-point Convert Double-precision to Half-precision
-description:
-  - id: inst-fcvt.h.d-behaviour
-    normative: false
-    text: |
-      `fcvt.h.d` converts a Double-precision Floating-point number to a Half-precision floating-point number.
+description: |
+  `fcvt.h.d` converts a Double-precision Floating-point number to a Half-precision floating-point number.
 definedBy:
   allOf: [D, Zfh]
 assembly: fd, fs1, rm
diff --git a/spec/std/isa/inst/Zfh/fcvt.h.l.yaml b/spec/std/isa/inst/Zfh/fcvt.h.l.yaml
index 51aa580097..492789a372 100644
--- a/spec/std/isa/inst/Zfh/fcvt.h.l.yaml
+++ b/spec/std/isa/inst/Zfh/fcvt.h.l.yaml
@@ -7,11 +7,8 @@ $schema: inst_schema.json#
 kind: instruction
 name: fcvt.h.l
 long_name: Floating-point Convert Long to Half-precision
-description:
-  - id: inst-fcvt.h.l-behaviour
-    normative: false
-    text: |
-      `fcvt.h.l` converts a 64-bit signed integer to a half-precision floating-point number.
+description: |
+  `fcvt.h.l` converts a 64-bit signed integer to a half-precision floating-point number.
 definedBy: Zfh
 assembly: fd, xs1, rm
 encoding:
diff --git a/spec/std/isa/inst/Zfh/fcvt.h.lu.yaml b/spec/std/isa/inst/Zfh/fcvt.h.lu.yaml
index cd5eb7da63..f90491fc98 100644
--- a/spec/std/isa/inst/Zfh/fcvt.h.lu.yaml
+++ b/spec/std/isa/inst/Zfh/fcvt.h.lu.yaml
@@ -7,11 +7,8 @@ $schema: inst_schema.json#
 kind: instruction
 name: fcvt.h.lu
 long_name: Floating-point Convert Unsigned Long to Half-precision
-description:
-  - id: inst-fcvt.h.lu-behaviour
-    normative: false
-    text: |
-      `fcvt.h.lu` converts a 64-bit unsigned integer to a half-precision floating-point number.
+description: |
+  `fcvt.h.lu` converts a 64-bit unsigned integer to a half-precision floating-point number.
 definedBy: Zfh
 assembly: fd, xs1, rm
 encoding:
diff --git a/spec/std/isa/inst/Zfh/fcvt.h.w.yaml b/spec/std/isa/inst/Zfh/fcvt.h.w.yaml
index 77fec6d33c..aa918e04e8 100644
--- a/spec/std/isa/inst/Zfh/fcvt.h.w.yaml
+++ b/spec/std/isa/inst/Zfh/fcvt.h.w.yaml
@@ -7,11 +7,8 @@ $schema: inst_schema.json#
 kind: instruction
 name: fcvt.h.w
 long_name: Floating-point Convert Word to Half-precision
-description:
-  - id: inst-fcvt.h.w-behaviour
-    normative: false
-    text: |
-      `fcvt.h.w` converts a 32-bit signed integer to a half-precision floating-point number.
+description: |
+  `fcvt.h.w` converts a 32-bit signed integer to a half-precision floating-point number.
 definedBy: Zfh
 assembly: fd, xs1, rm
 encoding:
diff --git a/spec/std/isa/inst/Zfh/fcvt.h.wu.yaml b/spec/std/isa/inst/Zfh/fcvt.h.wu.yaml
index 46c6244522..5552620800 100644
--- a/spec/std/isa/inst/Zfh/fcvt.h.wu.yaml
+++ b/spec/std/isa/inst/Zfh/fcvt.h.wu.yaml
@@ -7,11 +7,8 @@ $schema: inst_schema.json#
 kind: instruction
 name: fcvt.h.wu
 long_name: Floating-point Convert Unsigned Word to Half-precision
-description:
-  - id: inst-fcvt.h.wu-behaviour
-    normative: false
-    text: |
-      `fcvt.h.wu` converts a 32-bit unsigned integer to a half-precision floating-point number.
+description: |
+  `fcvt.h.wu` converts a 32-bit unsigned integer to a half-precision floating-point number.
 definedBy: Zfh
 assembly: fd, xs1, rm
 encoding:
diff --git a/spec/std/isa/inst/Zfh/fcvt.l.h.yaml b/spec/std/isa/inst/Zfh/fcvt.l.h.yaml
index c33d1e6b25..12e730e49a 100644
--- a/spec/std/isa/inst/Zfh/fcvt.l.h.yaml
+++ b/spec/std/isa/inst/Zfh/fcvt.l.h.yaml
@@ -7,11 +7,8 @@ $schema: inst_schema.json#
 kind: instruction
 name: fcvt.l.h
 long_name: Floating-point Convert Half-precision to Long
-description:
-  - id: inst-fcvt.l.h-behaviour
-    normative: false
-    text: |
-      `fcvt.l.h` converts a half-precision floating-point number to a signed 64-bit integer.
+description: |
+  `fcvt.l.h` converts a half-precision floating-point number to a signed 64-bit integer.
 definedBy: Zfh
 assembly: xd, fs1, rm
 encoding:
diff --git a/spec/std/isa/inst/Zfh/fcvt.lu.h.yaml b/spec/std/isa/inst/Zfh/fcvt.lu.h.yaml
index 129e54acdb..6e3d1b25d7 100644
--- a/spec/std/isa/inst/Zfh/fcvt.lu.h.yaml
+++ b/spec/std/isa/inst/Zfh/fcvt.lu.h.yaml
@@ -7,11 +7,8 @@ $schema: inst_schema.json#
 kind: instruction
 name: fcvt.lu.h
 long_name: Floating-point Convert Half-precision to Unsigned Long
-description:
-  - id: inst-fcvt.lu.h-behaviour
-    normative: false
-    text: |
-      `fcvt.lu.h` converts a half-precision floating-point number to an unsigned 64-bit integer.
+description: |
+  `fcvt.lu.h` converts a half-precision floating-point number to an unsigned 64-bit integer.
 definedBy: Zfh
 assembly: xd, fs1, rm
 encoding:
diff --git a/spec/std/isa/inst/Zfh/fcvt.w.h.yaml b/spec/std/isa/inst/Zfh/fcvt.w.h.yaml
index add4781f67..8fcdfbeb27 100644
--- a/spec/std/isa/inst/Zfh/fcvt.w.h.yaml
+++ b/spec/std/isa/inst/Zfh/fcvt.w.h.yaml
@@ -7,11 +7,8 @@ $schema: inst_schema.json#
 kind: instruction
 name: fcvt.w.h
 long_name: Floating-point Convert Half-precision to Word
-description:
-  - id: inst-fcvt.w.h-behaviour
-    normative: false
-    text: |
-      `fcvt.w.h` converts a half-precision floating-point number to a signed 32-bit integer.
+description: |
+  `fcvt.w.h` converts a half-precision floating-point number to a signed 32-bit integer.
 definedBy: Zfh
 assembly: xd, fs1, rm
 encoding:
diff --git a/spec/std/isa/inst/Zfh/fcvt.wu.h.yaml b/spec/std/isa/inst/Zfh/fcvt.wu.h.yaml
index 4a9ab907f6..71e9d131ee 100644
--- a/spec/std/isa/inst/Zfh/fcvt.wu.h.yaml
+++ b/spec/std/isa/inst/Zfh/fcvt.wu.h.yaml
@@ -7,11 +7,8 @@ $schema: inst_schema.json#
 kind: instruction
 name: fcvt.wu.h
 long_name: Floating-point Convert Half-precision to Word
-description:
-  - id: inst-fcvt.wu.h-behaviour
-    normative: false
-    text: |
-      `fcvt.wu.h` converts a half-precision floating-point number to an unsigned 32-bit integer.
+description: |
+  `fcvt.wu.h` converts a half-precision floating-point number to an unsigned 32-bit integer.
 definedBy: Zfh
 assembly: xd, fs1, rm
 encoding:
diff --git a/spec/std/isa/inst/Zkn/aes64ks1i.yaml b/spec/std/isa/inst/Zkn/aes64ks1i.yaml
index 11459a458d..5c18992710 100644
--- a/spec/std/isa/inst/Zkn/aes64ks1i.yaml
+++ b/spec/std/isa/inst/Zkn/aes64ks1i.yaml
@@ -7,16 +7,10 @@ $schema: "inst_schema.json#"
 kind: instruction
 name: aes64ks1i
 long_name: AES Key Schedule Instruction 1
-description:
-  - id: inst-aes64ks1i-behavior
-    normative: true
-    text: |
-      This instruction implements the rotation, SubBytes and Round Constant addition steps of the AES
-      block cipher Key Schedule.
-  - id: inst-aes64ks1i-range
-    normative: true
-    text: |
-      `rnum` must be in the range `0x0..0xA`. The values `0xB..0xF` are reserved.
+description: |
+  This instruction implements the rotation, SubBytes and Round Constant addition steps of the AES
+  block cipher Key Schedule.
+  `rnum` must be in the range `0x0..0xA`. The values `0xB..0xF` are reserved.
 definedBy:
   anyOf: [Zknd, Zkne]
 base: 64
diff --git a/spec/std/isa/inst/Zkn/aes64ks2.yaml b/spec/std/isa/inst/Zkn/aes64ks2.yaml
index 6434ab2306..24832fab56 100644
--- a/spec/std/isa/inst/Zkn/aes64ks2.yaml
+++ b/spec/std/isa/inst/Zkn/aes64ks2.yaml
@@ -7,12 +7,9 @@ $schema: "inst_schema.json#"
 kind: instruction
 name: aes64ks2
 long_name: AES Key Schedule Instruction 2
-description:
-  - id: instr-aes64ks2-behavior
-    normative: true
-    text: |
-      This instruction implements the additional XOR'ing of key words as part of the AES block cipher
-      Key Schedule.
+description: |
+  This instruction implements the additional XOR'ing of key words as part of the AES block cipher
+  Key Schedule.
 definedBy:
   anyOf: [Zknd, Zkne]
 base: 64
diff --git a/spec/std/isa/inst/Zknd/aes64ds.yaml b/spec/std/isa/inst/Zknd/aes64ds.yaml
index c785ba4059..9a922b3b75 100644
--- a/spec/std/isa/inst/Zknd/aes64ds.yaml
+++ b/spec/std/isa/inst/Zknd/aes64ds.yaml
@@ -7,12 +7,9 @@ $schema: "inst_schema.json#"
 kind: instruction
 name: aes64ds
 long_name: AES decrypt final round
-description:
-  - id: inst-aes64ds-behavior
-    normative: true
-    text: |
-      Uses the two 64-bit source registers to represent the entire AES state, and produces _half_ of the next
-      round output, applying the Inverse ShiftRows and SubBytes steps.
+description: |
+  Uses the two 64-bit source registers to represent the entire AES state, and produces _half_ of the next
+  round output, applying the Inverse ShiftRows and SubBytes steps.
 definedBy: Zknd
 base: 64
 assembly: xd, xs1, xs2
diff --git a/spec/std/isa/inst/Zknd/aes64dsm.yaml b/spec/std/isa/inst/Zknd/aes64dsm.yaml
index f7cf769937..410c437b36 100644
--- a/spec/std/isa/inst/Zknd/aes64dsm.yaml
+++ b/spec/std/isa/inst/Zknd/aes64dsm.yaml
@@ -7,12 +7,9 @@ $schema: "inst_schema.json#"
 kind: instruction
 name: aes64dsm
 long_name: AES decrypt middle round
-description:
-  - id: inst-aes64dsm-behavior
-    normative: true
-    text: |
-      Uses the two 64-bit source registers to represent the entire AES state, and produces _half_ of the next
-      round output, applying the Inverse ShiftRows, SubBytes and MixColumns steps.
+description: |
+  Uses the two 64-bit source registers to represent the entire AES state, and produces _half_ of the next
+  round output, applying the Inverse ShiftRows, SubBytes and MixColumns steps.
 definedBy: Zknd
 base: 64
 assembly: xd, xs1, xs2
diff --git a/spec/std/isa/inst/Zknd/aes64im.yaml b/spec/std/isa/inst/Zknd/aes64im.yaml
index 58f4b3b61d..22c6ab54f0 100644
--- a/spec/std/isa/inst/Zknd/aes64im.yaml
+++ b/spec/std/isa/inst/Zknd/aes64im.yaml
@@ -7,13 +7,10 @@ $schema: "inst_schema.json#"
 kind: instruction
 name: aes64im
 long_name: AES Decrypt KeySchedule MixColumns
-description:
-  - id: inst-aes64im-behavior
-    normative: true
-    text: |
-      The instruction applies the inverse MixColumns transformation to two columns of the state array,
-      packed into a single 64-bit register. It is used to create the inverse cipher KeySchedule, according to
-      the equivalent inverse cipher construction in (NIST, 2001) (Page 23, Section 5.3.5).
+description: |
+  The instruction applies the inverse MixColumns transformation to two columns of the state array,
+  packed into a single 64-bit register. It is used to create the inverse cipher KeySchedule, according to
+  the equivalent inverse cipher construction in (NIST, 2001) (Page 23, Section 5.3.5).
 definedBy: Zknd
 base: 64
 assembly: xd, xs1
diff --git a/spec/std/isa/inst/Zkne/aes64es.yaml b/spec/std/isa/inst/Zkne/aes64es.yaml
index 63802b0e6a..08d4be82f8 100644
--- a/spec/std/isa/inst/Zkne/aes64es.yaml
+++ b/spec/std/isa/inst/Zkne/aes64es.yaml
@@ -7,12 +7,9 @@ $schema: "inst_schema.json#"
 kind: instruction
 name: aes64es
 long_name: AES encrypt final round
-description:
-  - id: inst-aes64es-behavior
-    normative: true
-    text: |
-      Uses the two 64-bit source registers to represent the entire AES state, and produces _half_ of the next
-      round output, applying the ShiftRows and SubBytes steps.
+description: |
+  Uses the two 64-bit source registers to represent the entire AES state, and produces _half_ of the next
+  round output, applying the ShiftRows and SubBytes steps.
 definedBy: Zkne
 base: 64
 assembly: xd, xs1, xs2
diff --git a/spec/std/isa/inst/Zkne/aes64esm.yaml b/spec/std/isa/inst/Zkne/aes64esm.yaml
index c6d74f838c..d6aca828f9 100644
--- a/spec/std/isa/inst/Zkne/aes64esm.yaml
+++ b/spec/std/isa/inst/Zkne/aes64esm.yaml
@@ -7,12 +7,9 @@ $schema: "inst_schema.json#"
 kind: instruction
 name: aes64esm
 long_name: AES encrypt middle round
-description:
-  - id: inst-aes64esm-behavior
-    normative: true
-    text: |
-      Uses the two 64-bit source registers to represent the entire AES state, and produces _half_ of the next
-      round output, applying the Inverse ShiftRows, SubBytes and MixColumns steps.
+description: |
+  Uses the two 64-bit source registers to represent the entire AES state, and produces _half_ of the next
+  round output, applying the Inverse ShiftRows, SubBytes and MixColumns steps.
 definedBy: Zkne
 base: 64
 assembly: xd, xs1, xs2
diff --git a/spec/std/isa/isa/globals.isa b/spec/std/isa/isa/globals.isa
index 9afd483a5c..47a4e271a7 100644
--- a/spec/std/isa/isa/globals.isa
+++ b/spec/std/isa/isa/globals.isa
@@ -200,9 +200,9 @@ struct VmaOrderType {
   Boolean gstage;  # include gstage (hgatp-based) mappings?
 
   Boolean single_vmid;    # Only order a single VMID?
-  Bits<14> vmid;          # when single_vmid is true, the VMID to order
+  Bits<VMID_WIDTH> vmid;  # when single_vmid is true, the VMID to order
   Boolean single_asid;    # Only order a single ASID?
-  Bits<16> asid;          # when single_asid is true, the ASID to order
+  Bits<ASID_WIDTH> asid;  # when single_asid is true, the ASID to order
   Boolean single_vaddr;   # Only order a single virtual address?
   XReg vaddr;             # when single_vaddr is true, the virtual address to order
   Boolean single_gpaddr;  # Only order a single guest physical address?
@@ -236,9 +236,9 @@ function mode {
     Returns the current active privilege mode.
   }
   body {
-    if ((!implemented?(ExtensionName::S)) &&
-        (!implemented?(ExtensionName::U)) &&
-        (!implemented?(ExtensionName::H))) {
+    if (!implemented?(ExtensionName::S) &&
+        !implemented?(ExtensionName::U) &&
+        !implemented?(ExtensionName::H)) {
       return PrivilegeMode::M;
     } else {
       return current_mode;
@@ -1076,19 +1076,19 @@ function pmp_match_32 {
 
       # set up the default range limits, which will result in NoMatch when
       # compared to the access
-      Bits<PHYS_ADDR_WIDTH> range_base = 0;
-      Bits<PHYS_ADDR_WIDTH> range_limit = 0;
+      Bits<PHYS_ADDR_WIDTH> range_hi = 0;
+      Bits<PHYS_ADDR_WIDTH> range_lo = 0;
 
       if (cfg.A == $bits(PmpCfg_A::TOR)) {
         if (i == 0) {
           # when entry zero is TOR, zero is the lower address bound
-          range_base = 0;
+          range_lo = 0;
         } else {
           # otherwise, it's the address in the next lowest pmpaddr register
           Csr tor_pmpaddr_csr = direct_csr_lookup(pmpaddr_idx - 1);
-          range_base = csr_sw_read(tor_pmpaddr_csr)[PHYS_ADDR_WIDTH-1:0];
+          range_lo = (csr_sw_read(tor_pmpaddr_csr) << 2)[PHYS_ADDR_WIDTH-1:0];
         }
-        range_limit = (pmpaddr_csr_value)[PHYS_ADDR_WIDTH-1:0] - 1;
+        range_hi = (pmpaddr_csr_value << 2)[PHYS_ADDR_WIDTH-1:0];
 
       } else if (cfg.A == $bits(PmpCfg_A::NAPOT)) {
         # Example pmpaddr: 0b00010101111
@@ -1097,20 +1097,21 @@ function pmp_match_32 {
         # mask:            0b00000011111
         # ~mask:           0b11111100000
         # len = mask + 1:  0b00000100000
-        Bits<PHYS_ADDR_WIDTH-1> pmpaddr_value = pmpaddr_csr_value[PHYS_ADDR_WIDTH-3:0];
-        Bits<PHYS_ADDR_WIDTH-1> mask = pmpaddr_value ^ (pmpaddr_value + 1);
-        range_base = pmpaddr_value & ~mask;
-        range_limit = range_base + mask;
+        Bits<PHYS_ADDR_WIDTH-2> pmpaddr_value = pmpaddr_csr_value[PHYS_ADDR_WIDTH-3:0];
+        Bits<PHYS_ADDR_WIDTH-2> mask = pmpaddr_value ^ (pmpaddr_value + 1);
+        range_lo = (pmpaddr_value & ~mask) << 2;
+        Bits<PHYS_ADDR_WIDTH-2> len = mask + 1;
+        range_hi = ((pmpaddr_value & ~mask) + len) << 2;
 
       } else if (cfg.A == $bits(PmpCfg_A::NA4)) {
-        range_base = pmpaddr_csr_value[PHYS_ADDR_WIDTH-1:0];
-        range_limit = range_base + 3;
+        range_lo = (pmpaddr_csr_value << 2)[PHYS_ADDR_WIDTH-1:0];
+        range_hi = range_lo + 4;
       }
 
-      if (((paddr >> 2) >= range_base) && (((paddr + (access_size/8) - 1) >> 2) <= range_limit)) {
+      if ((paddr >= range_lo) && ((paddr + (access_size/8)) < range_hi)) {
         # full match
         return PmpMatchResult::FullMatch, cfg;
-      } else if (!(((paddr + (access_size/8) - 1) < range_base) || (paddr >= range_limit))) {
+      } else if (!(((paddr + (access_size/8) - 1) < range_lo) || (paddr >= range_hi))) {
         # this is a partial match. By definition, the access must fail, regardless
         # of the pmp cfg settings
         return PmpMatchResult::PartialMatch, -;
@@ -1317,9 +1318,7 @@ function current_translation_mode {
     if (CSR[misa].H == 1'b1) {
       if (effective_mode == PrivilegeMode::VS || effective_mode == PrivilegeMode::VU) {
         Bits<4> mode_val = CSR[vsatp].MODE;
-        if (mode_val == $bits(SatpMode::Bare)) {
-          return SatpMode::Bare;
-        } else if (mode_val == $bits(SatpMode::Sv32)) {
+        if (mode_val == $bits(SatpMode::Sv32)) {
           # Sv32 is only defined when XLEN == 32
           if (MXLEN == 64) {
             if ((effective_mode == PrivilegeMode::VS) && (CSR[hstatus].VSXL != $bits(XRegWidth::XLEN32))) {
@@ -1392,17 +1391,13 @@ function current_translation_mode {
         } else {
           return SatpMode::Reserved;
         }
-      } else {
-        return SatpMode::Reserved;
       }
     } else if (CSR[misa].S == 1'b1) {
 
       # if we reach here, then the effective mode is S or U
       assert(effective_mode == PrivilegeMode::S || effective_mode == PrivilegeMode::U, "unexpected priv mode");
       Bits<4> mode_val = CSR[satp].MODE;
-      if (mode_val == $bits(SatpMode::Bare)) {
-        return SatpMode::Bare;
-      } else if (mode_val == $bits(SatpMode::Sv32)) {
+      if (mode_val == $bits(SatpMode::Sv32)) {
         # Sv32 is only defined when XLEN == 32
         if (MXLEN == 64) {
           if (effective_mode == PrivilegeMode::S && CSR[mstatus].SXL != $bits(XRegWidth::XLEN32)) {
@@ -1418,8 +1413,6 @@ function current_translation_mode {
           # not supported in this configuration
           return SatpMode::Reserved;
         }
-        # OK
-        return SatpMode::Sv32;
       } else if ((MXLEN == 64) && (mode_val == $bits(SatpMode::Sv39))) {
         # Sv39 is only defined when XLEN == 64
         if (effective_mode == PrivilegeMode::S && CSR[mstatus].SXL != $bits(XRegWidth::XLEN64)) {
@@ -1471,8 +1464,6 @@ function current_translation_mode {
       } else {
         return SatpMode::Reserved;
       }
-    } else {
-      return SatpMode::Reserved;
     }
   }
 }
@@ -1843,16 +1834,10 @@ function gstage_page_walk {
       PteFlags pte_flags = pte[9:0];
 
       # check if any reserved bits are set
-      # Sv32 has no reserved bits, and Sv39/48/57 all have reserved bits at 58:54
-      if ((VA_SIZE != 32) && (pte[58:54] != 0)) {
+      # Sv32 has no reserved bits, and Sv39/48/57 all have reserved bits at 60:54
+      if ((VA_SIZE != 32) && (pte[60:54] != 0)) {
         raise_guest_page_fault(op, gpaddr, vaddr, tinst, effective_mode);
       }
-      if (!implemented?(ExtensionName::Svrsw60t59b)) {
-        if ((PTESIZE >= 64) && pte[60:59] != 0) {
-          # 60:59 are reserved if Svrsw60t59b is not supported
-          raise_guest_page_fault(op, gpaddr, vaddr, tinst, effective_mode);
-        }
-      }
       if (!implemented?(ExtensionName::Svnapot)) {
         if ((PTESIZE >= 64) && pte[63] != 0) {
           # N is reserved if Svnapot is not supported
@@ -1903,7 +1888,7 @@ function gstage_page_walk {
         }
 
         # ensure remaining PPN bits are zero, otherwise there is a misaligned super page
-        if ((i > 0) && (pte[(i-1)*VPN_SIZE:0] != 0)) {
+        if ((i > 0) && (pte[(i-1)*VPN_SIZE:10] != 0)) {
           raise_guest_page_fault(op, gpaddr, vaddr, tinst, effective_mode);
         }
 
@@ -2083,10 +2068,8 @@ function stage1_page_walk {
       # HS-level sstatus.MXR makes execute-only pages readable for both stages of address translation
       # (VS-stage and G-stage), whereas vsstatus.MXR affects only the first translation stage (VS-stage)
       mxr = (CSR[mstatus].MXR == 1) || (CSR[vsstatus].MXR == 1);
-      ppn = CSR[vsatp].PPN;
     } else {
       mxr = CSR[mstatus].MXR == 1;
-      ppn = CSR[satp].PPN;
     }
 
     # Supervisor access user page?
@@ -2097,11 +2080,13 @@ function stage1_page_walk {
       sum = CSR[mstatus].SUM == 1;
     }
 
+    ppn = CSR[vsatp].PPN;
+
     if ((VA_SIZE < xlen()) && (vaddr[xlen()-1:VA_SIZE] != {xlen()-VA_SIZE{vaddr[VA_SIZE - 1]}})) {
       # non-canonical virtual address raises a page fault
       # note that if pointer masking is enabled,
       # vaddr has already been transformed before reaching here
-      raise (page_fault_code, mode(), vaddr);
+      raise (page_fault_code, effective_mode, vaddr);
     }
 
     for (U32 i = (LEVELS - 1); i >= 0; i--) {
@@ -2120,7 +2105,7 @@ function stage1_page_walk {
 
       # check hw page table access permission
       if (!pma_applies?(PmaAttribute::HardwarePageTableRead, pte_phys.paddr, PTESIZE)) {
-        raise (access_fault_code, mode(), vaddr);
+        raise (access_fault_code, effective_mode, vaddr);
       }
 
       # perform access check on the physical address of pte before it's used
@@ -2133,46 +2118,39 @@ function stage1_page_walk {
       Boolean ss_page = (pte_flags.R == 0) && (pte_flags.W == 1) && (pte_flags.X == 0);
 
       # check if any reserved bits are set
-      # Sv32 has no reserved bits, and Sv39/48/57 all have reserved bits at 58:54
-      if ((VA_SIZE != 32) && (pte[58:54] != 0)) {
-        raise(page_fault_code, mode(), vaddr);
+      # Sv32 has no reserved bits, and Sv39/48/57 all have reserved bits at 60:54
+      if ((VA_SIZE != 32) && (pte[60:54] != 0)) {
+        raise(page_fault_code, effective_mode, vaddr);
       }
 
       if (pte_flags.V == 0) {
         # invalid entry
-        raise (page_fault_code, mode(), vaddr);
+        raise (page_fault_code, effective_mode, vaddr);
       }
 
       if (!sse) {
         if ((pte_flags.R == 0) && (pte_flags.W == 1)) {
           # write permission must also have read permission
-          raise (page_fault_code, mode(), vaddr);
+          raise (page_fault_code, effective_mode, vaddr);
         }
       }
 
       if (pbmte) {
         # PBMT == 3 is reserved
         if (pte[62:61] == 3) {
-          raise (page_fault_code, mode(), vaddr);
+          raise (page_fault_code, effective_mode, vaddr);
         }
       } else {
         # PBMT is reserved if Svpbmt is not supported)
         if ((PTESIZE >= 64) && (pte[62:61] != 0)) {
-          raise (page_fault_code, mode(), vaddr);
-        }
-      }
-
-      if (!implemented?(ExtensionName::Svrsw60t59b)) {
-        if ((PTESIZE >= 64) && pte[60:59] != 0) {
-          # 60:59 are reserved if Svrsw60t59b is not supported
-          raise (page_fault_code, mode(), vaddr);
+          raise (page_fault_code, effective_mode, vaddr);
         }
       }
 
       if (!implemented?(ExtensionName::Svnapot)) {
         if ((PTESIZE >= 64) && (pte[63] != 0)) {
           # N is reserved if Svnapot is not supported
-          raise (page_fault_code, mode(), vaddr);
+          raise (page_fault_code, effective_mode, vaddr);
         }
       }
 
@@ -2184,37 +2162,37 @@ function stage1_page_walk {
           if (((!mxr) && (pte_flags.R == 0))
               || ((mxr) && (pte_flags.X == 0 && pte_flags.R == 0))) {
             # no read permission
-            raise (page_fault_code, mode(), vaddr);
+            raise (page_fault_code, effective_mode, vaddr);
           }
 
           if (effective_mode == PrivilegeMode::U && pte_flags.U == 0) {
             # U-mode can never access supervisor page
-            raise (page_fault_code, mode(), vaddr);
+            raise (page_fault_code, effective_mode, vaddr);
           } else if (CSR[misa].H == 1 && effective_mode == PrivilegeMode::VU && pte_flags.U == 0) {
             # VU-mode can never access supervisor page
-            raise (page_fault_code, mode(), vaddr);
+            raise (page_fault_code, effective_mode, vaddr);
           } else if (effective_mode == PrivilegeMode::S && pte_flags.U == 1 && !sum) {
             # S-mode cannot access User page unless mstatus.SUM == 1
-            raise (page_fault_code, mode(), vaddr);
+            raise (page_fault_code, effective_mode, vaddr);
           } else if (effective_mode == PrivilegeMode::VS && pte_flags.U == 1 && !sum) {
             # VS-mode cannot access User page unless vsstatus.SUM == 1
-            raise (page_fault_code, mode(), vaddr);
+            raise (page_fault_code, effective_mode, vaddr);
           }
         }
         if (((op == MemoryOperation::Write) || (op == MemoryOperation::ReadModifyWrite))
              && (pte_flags.W == 0)) {
           # no write permission
-          raise (page_fault_code, mode(), vaddr);
+          raise (page_fault_code, effective_mode, vaddr);
         } else if ((op == MemoryOperation::Fetch) && (pte_flags.X == 0)) {
           # no execute permission
-          raise (page_fault_code, mode(), vaddr);
+          raise (page_fault_code, effective_mode, vaddr);
         } else if ((op == MemoryOperation::Fetch) && ss_page) {
           # fetch from Shadow Stack never allowed
-          raise (page_fault_code, mode(), vaddr);
+          raise (page_fault_code, effective_mode, vaddr);
         }
 
         # ensure remaining PPN bits are zero, otherwise there is a misaligned super page
-        raise (page_fault_code, mode(), vaddr) if ((i > 0) && (pte[i*VPN_SIZE + 10:10] != 0));
+        raise (page_fault_code, effective_mode, vaddr) if ((i > 0) && (pte[(i-1)*VPN_SIZE:10] != 0));
 
         # check access and dirty bits
         if ((pte_flags.A == 0)         # access is clear
@@ -2272,7 +2250,7 @@ function stage1_page_walk {
               # successful translation and update
               TranslationResult pte_phys =
                 translate_gstage(
-                  {pte[PA_SIZE-3:i*VPN_SIZE + 10], vaddr[i*VPN_SIZE + 11:0]},
+                  {(pte[PA_SIZE-3:(i*VPN_SIZE) + 10] << 2), vaddr[11:0]},
                   vaddr,
                   op,
                   effective_mode,
@@ -2285,14 +2263,14 @@ function stage1_page_walk {
             }
           } else {
             # A or D bit needs updated
-            raise(page_fault_code, mode(), vaddr);
+            raise(page_fault_code, effective_mode, vaddr);
           }
         }
 
         # translation succeeded
         TranslationResult pte_phys =
           translate_gstage(
-            {pte[PA_SIZE-3:i*VPN_SIZE + 10], vaddr[i*VPN_SIZE + 11:0]},
+            {(pte[PA_SIZE-3:(i*VPN_SIZE) + 10] << 2), vaddr[11:0]},
             vaddr,
             op,
             effective_mode,
@@ -2309,22 +2287,22 @@ function stage1_page_walk {
 
         if (i == 0) {
           # a pointer can't exist on the last level
-          raise (page_fault_code, mode(), vaddr);
+          raise (page_fault_code, effective_mode, vaddr);
         }
 
         if (pte_flags.D == 1 || pte_flags.A == 1 || pte_flags.U == 1) {
           # D, A, and U are reserved in non-leaf PTEs
-          raise (page_fault_code, mode(), vaddr);
+          raise (page_fault_code, effective_mode, vaddr);
         }
 
         if ((VA_SIZE != 32) && (pte[62:61] != 0)) {
           # PBMT must be zero in a pointer PTE
-          raise (page_fault_code, mode(), vaddr);
+          raise (page_fault_code, effective_mode, vaddr);
         }
 
         if ((VA_SIZE != 32) && pte[63] != 0) {
           # N must be zero in a pointer PTE
-          raise (page_fault_code, mode(), vaddr);
+          raise (page_fault_code, effective_mode, vaddr);
         }
 
         # fall through to next level
@@ -2386,19 +2364,16 @@ function translate {
 
     if (translation_mode == SatpMode::Reserved) {
       if (op == MemoryOperation::Read) {
-        raise (ExceptionCode::LoadPageFault, mode(), vaddr);
+        raise (ExceptionCode::LoadPageFault, effective_mode, vaddr);
       } else if (op == MemoryOperation::Write || op == MemoryOperation::ReadModifyWrite) {
-        raise (ExceptionCode::StoreAmoPageFault, mode(), vaddr);
+        raise (ExceptionCode::StoreAmoPageFault, effective_mode, vaddr);
       } else {
         assert(op == MemoryOperation::Fetch, "Unexpected memory operation");
-        raise (ExceptionCode::InstructionPageFault, mode(), vaddr);
+        raise (ExceptionCode::InstructionPageFault, effective_mode, vaddr);
       }
     }
 
-
-    if (translation_mode == SatpMode::Bare) {
-      result.paddr = vaddr;
-    } else if (translation_mode == SatpMode::Sv32) {
+    if (translation_mode == SatpMode::Sv32) {
       # Sv32 page table walk
       result = stage1_page_walk<32, 34, 32, 2>(vaddr, op, effective_mode, encoding);
     } else if (translation_mode == SatpMode::Sv39) {
@@ -2592,7 +2567,7 @@ function read_memory {
           : virtual_address;
         access_check(physical_address, LEN, virtual_address, MemoryOperation::Read, ExceptionCode::LoadAccessFault, effective_ldst_mode());
       }
-      raise (ExceptionCode::LoadAddressMisaligned, mode(), virtual_address);
+      raise (ExceptionCode::LoadAddressMisaligned, effective_ldst_mode(), virtual_address);
     } else {
 
       # misaligned, must break into multiple reads
@@ -2751,7 +2726,7 @@ function load_reserved {
         : virtual_address;
 
     if (pma_applies?(PmaAttribute::RsrvNone, physical_address, N)) {
-      raise(ExceptionCode::LoadAccessFault, mode(), virtual_address);
+      raise(ExceptionCode::LoadAccessFault, effective_ldst_mode(), virtual_address);
     }
 
     if (aq == 1) {
@@ -2798,7 +2773,7 @@ function store_conditional {
         : virtual_address;
 
     if (pma_applies?(PmaAttribute::RsrvNone, physical_address, N)) {
-      raise(ExceptionCode::StoreAmoAccessFault, mode(), virtual_address);
+      raise(ExceptionCode::StoreAmoAccessFault, effective_ldst_mode(), virtual_address);
     }
 
     # failed SC still looks like a store to memory protection
@@ -2867,7 +2842,7 @@ function amo {
     Boolean aligned = is_naturally_aligned<N>(virtual_address);
 
     if (!aligned && MISALIGNED_LDST_EXCEPTION_PRIORITY == "high") {
-      raise(ExceptionCode::StoreAmoAddressMisaligned, mode(), virtual_address);
+      raise(ExceptionCode::StoreAmoAddressMisaligned, effective_ldst_mode(), virtual_address);
     }
 
     Bits<PHYS_ADDR_WIDTH> physical_address =
@@ -2877,13 +2852,13 @@ function amo {
 
     # PMA Atomicity checks
     if (pma_applies?(PmaAttribute::AmoNone, physical_address, N)) {
-      raise(ExceptionCode::StoreAmoAccessFault, mode(), virtual_address);
+      raise(ExceptionCode::StoreAmoAccessFault, effective_ldst_mode(), virtual_address);
     } else if (((op == AmoOperation::Add || op == AmoOperation::Max || op == AmoOperation::Maxu || op == AmoOperation::Min || op == AmoOperation::Minu)) &&
                !pma_applies?(PmaAttribute::AmoArithmetic, physical_address, N)) {
-      raise(ExceptionCode::StoreAmoAccessFault, mode(), virtual_address);
+      raise(ExceptionCode::StoreAmoAccessFault, effective_ldst_mode(), virtual_address);
     } else if (((op == AmoOperation::And || op == AmoOperation::Or || op == AmoOperation::Xor)) &&
                 !pma_applies?(PmaAttribute::AmoLogical, physical_address, N)) {
-      raise(ExceptionCode::StoreAmoAccessFault, mode(), virtual_address);
+      raise(ExceptionCode::StoreAmoAccessFault, effective_ldst_mode(), virtual_address);
     } else {
       assert(
         pma_applies?(PmaAttribute::AmoSwap, physical_address, N) &&
@@ -2895,7 +2870,7 @@ function amo {
     # pma alignment checks
     if (!aligned &&
          !misaligned_is_atomic?<N>(physical_address)) {
-      raise (ExceptionCode::StoreAmoAddressMisaligned, mode(), virtual_address);
+      raise (ExceptionCode::StoreAmoAddressMisaligned, effective_ldst_mode(), virtual_address);
     }
 
     if (N == 32) {
@@ -2980,7 +2955,7 @@ function write_memory {
           : virtual_address;
         access_check(physical_address, LEN, virtual_address, MemoryOperation::Write, ExceptionCode::StoreAmoAccessFault, effective_ldst_mode());
       }
-      raise (ExceptionCode::StoreAmoAddressMisaligned, mode(), virtual_address);
+      raise (ExceptionCode::StoreAmoAddressMisaligned, effective_ldst_mode(), virtual_address);
     } else {
       # misaligned, must break into multiple reads
       if (MISALIGNED_SPLIT_STRATEGY == "by_byte") {
diff --git a/tools/ruby-gems/udb/lib/udb/cli.rb b/tools/ruby-gems/udb/lib/udb/cli.rb
index e030451d4f..9ac13e2d4a 100644
--- a/tools/ruby-gems/udb/lib/udb/cli.rb
+++ b/tools/ruby-gems/udb/lib/udb/cli.rb
@@ -158,17 +158,9 @@ class List < SubCommandBase
       method_option :gen, type: :string, desc: "Path to folder used for generation", default: Udb.default_gen_path.to_s
       method_option :config, type: :string, required: true, desc: "Configuration name, or path to a config file", default: "_"
       method_option :config_dir, type: :string, desc: "Path to directory with config files", default: Udb.default_cfgs_path.to_s
-      method_option :output, aliases: "-o", type: :string, desc: "Output file, or '-' for stdout", default: "-"
       def extensions
         raise ArgumentError, "Arch directory does not exist: #{options[:arch]}" unless File.directory?(options[:arch])
 
-        out =
-          if options[:output] == "-"
-            $stdout
-          else
-            File.open(options[:output], "w")
-          end
-
         cfg_file =
           if File.file?(options[:config])
             Pathname.new(options[:config])
@@ -186,7 +178,7 @@ def extensions
           )
         cfg_arch = resolver.cfg_arch_for(cfg_file.realpath)
         cfg_arch.possible_extensions.each do |ext|
-          out.puts ext.name
+          puts ext.name
         end
       end