Merged F extension instructions. Some fields are not populated

arch/inst/F/fabs.s.yaml

@@ -0,0 +1,25 @@
+# yaml-language-server: $schema=../../../schemas/inst_schema.json
+
+fabs.s:
+  long_name: No synopsis available.
+  description: |
+      No description available.
+  definedBy: F
+  assembly: xd, xs1, xs2=xs1
+  encoding:
+    match: 0010000----------010-----1010011
+    variables:
+    - name: rs2=rs1
+      location: 24-20
+    - name: rs1
+      location: 19-15
+    - name: rd
+      location: 11-7
+  access:
+    s: always
+    u: always
+    vs: always
+    vu: always
+  data_independent_timing: true
+  operation(): |
+

arch/inst/F/fadd.s.yaml

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+# yaml-language-server: $schema=../../../schemas/inst_schema.json
+
+fadd.s:
+  long_name: No synopsis available.
+  description: |
+      No description available.
+  definedBy: F
+  assembly: xd, xs1, xs2, rm
+  encoding:
+    match: 0000000------------------1010011
+    variables:
+    - name: rs2
+      location: 24-20
+    - name: rs1
+      location: 19-15
+    - name: rm
+      location: 14-12
+    - name: rd
+      location: 11-7
+  access:
+    s: always
+    u: always
+    vs: always
+    vu: always
+  data_independent_timing: true
+  operation(): |
+

arch/inst/F/fclass.s.yaml

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+# yaml-language-server: $schema=../../../schemas/inst_schema.json
+
+fclass.s:
+  long_name: Single-precision floating-point classify.
+  description: |
+      The `fclass.s` instruction examines the value in floating-point register
+      _fs1_ and writes to integer register _rd_ a 10-bit mask that indicates
+      the class of the floating-point number.
+      The format of the mask is described in the table below.
+      The corresponding bit in _rd_ will be set if the property is true and
+      clear otherwise.
+      All other bits in _rd_ are cleared.
+      Note that exactly one bit in rd will be set.
+      `fclass.s` does not set the floating-point exception flags.
+
+      .Format of result of `fclass` instruction.
+      [%autowidth,float="center",align="center",cols="^,<",options="header",]
+      |===
+      |_rd_ bit |Meaning
+      |0 |_rs1_ is latexmath:[$-\infty$].
+      |1 |_rs1_ is a negative normal number.
+      |2 |_rs1_ is a negative subnormal number.
+      |3 |_rs1_ is latexmath:[$-0$].
+      |4 |_rs1_ is latexmath:[$+0$].
+      |5 |_rs1_ is a positive subnormal number.
+      |6 |_rs1_ is a positive normal number.
+      |7 |_rs1_ is latexmath:[$+\infty$].
+      |8 |_rs1_ is a signaling NaN.
+      |9 |_rs1_ is a quiet NaN.
+      |===
+
+  definedBy: F
+  assembly: xd, fs1
+  encoding:
+    match: 111000000000-----001-----1010011
+    variables:
+    - name: fs1
+      location: 19-15
+    - name: rd
+      location: 11-7
+  access:
+    s: always
+    u: always
+    vs: always
+    vu: always
+  data_independent_timing: false
+  operation(): |
+

arch/inst/F/fcvt.l.s.yaml

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+# yaml-language-server: $schema=../../../schemas/inst_schema.json
+
+fcvt.l.s:
+  long_name: No synopsis available.
+  description: |
+      No description available.
+  definedBy: F
+  base: 64
+  assembly: xd, xs1, rm
+  encoding:
+    match: 110000000010-------------1010011
+    variables:
+    - name: rs1
+      location: 19-15
+    - name: rm
+      location: 14-12
+    - name: rd
+      location: 11-7
+  access:
+    s: always
+    u: always
+    vs: always
+    vu: always
+  data_independent_timing: true
+  operation(): |
+

arch/inst/F/fcvt.lu.s.yaml

@@ -0,0 +1,26 @@
+# yaml-language-server: $schema=../../../schemas/inst_schema.json
+
+fcvt.lu.s:
+  long_name: No synopsis available.
+  description: |
+      No description available.
+  definedBy: F
+  base: 64
+  assembly: xd, xs1, rm
+  encoding:
+    match: 110000000011-------------1010011
+    variables:
+    - name: rs1
+      location: 19-15
+    - name: rm
+      location: 14-12
+    - name: rd
+      location: 11-7
+  access:
+    s: always
+    u: always
+    vs: always
+    vu: always
+  data_independent_timing: true
+  operation(): |
+

arch/inst/F/fcvt.s.l.yaml

@@ -0,0 +1,26 @@
+# yaml-language-server: $schema=../../../schemas/inst_schema.json
+
+fcvt.s.l:
+  long_name: No synopsis available.
+  description: |
+      No description available.
+  definedBy: F
+  base: 64
+  assembly: xd, xs1, rm
+  encoding:
+    match: 110100000010-------------1010011
+    variables:
+    - name: rs1
+      location: 19-15
+    - name: rm
+      location: 14-12
+    - name: rd
+      location: 11-7
+  access:
+    s: always
+    u: always
+    vs: always
+    vu: always
+  data_independent_timing: true
+  operation(): |
+

arch/inst/F/fcvt.s.lu.yaml

@@ -0,0 +1,26 @@
+# yaml-language-server: $schema=../../../schemas/inst_schema.json
+
+fcvt.s.lu:
+  long_name: No synopsis available.
+  description: |
+      No description available.
+  definedBy: F
+  base: 64
+  assembly: xd, xs1, rm
+  encoding:
+    match: 110100000011-------------1010011
+    variables:
+    - name: rs1
+      location: 19-15
+    - name: rm
+      location: 14-12
+    - name: rd
+      location: 11-7
+  access:
+    s: always
+    u: always
+    vs: always
+    vu: always
+  data_independent_timing: true
+  operation(): |
+

arch/inst/F/fcvt.s.w.yaml

@@ -0,0 +1,35 @@
+# yaml-language-server: $schema=../../../schemas/inst_schema.json
+
+fcvt.s.w:
+  long_name: Convert signed 32-bit integer to single-precision float
+  description: |
+    Converts a 32-bit signed integer in integer register _rs1_ into a floating-point number in
+    floating-point register _fd_.
+
+    All floating-point to integer and integer to floating-point conversion instructions round
+    according to the _rm_ field.
+    A floating-point register can be initialized to floating-point positive zero using
+    `fcvt.s.w rd, x0`, which will never set any exception flags.
+
+    All floating-point conversion instructions set the Inexact exception flag if the rounded
+    result differs from the operand value and the Invalid exception flag is not set.
+  definedBy: F
+  assembly: fd, xs1
+  encoding:
+    match: 110100000000-------------1010011
+    variables:
+    - name: rs1
+      location: 19-15
+    - name: rm
+      location: 14-12
+    - name: rd
+      location: 11-7
+  access:
+    s: always
+    u: always
+    vs: always
+    vu: always
+  data_independent_timing: false
+  operation(): |
+
+

arch/inst/F/fcvt.s.wu.yaml

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+# yaml-language-server: $schema=../../../schemas/inst_schema.json
+
+fcvt.s.wu:
+  long_name: No synopsis available.
+  description: |
+      No description available.
+  definedBy: F
+  assembly: xd, xs1, rm
+  encoding:
+    match: 110100000001-------------1010011
+    variables:
+    - name: rs1
+      location: 19-15
+    - name: rm
+      location: 14-12
+    - name: rd
+      location: 11-7
+  access:
+    s: always
+    u: always
+    vs: always
+    vu: always
+  data_independent_timing: true
+  operation(): |
+

arch/inst/F/fcvt.w.s.yaml

@@ -0,0 +1,54 @@
+# yaml-language-server: $schema=../../../schemas/inst_schema.json
+
+fcvt.w.s:
+  long_name: Convert single-precision float to integer word to signed 32-bit integer.
+  description: |
+          Converts a floating-point number in floating-point register _fs1_ to a signed 32-bit integer indicates
+          integer register _rd_.
+
+          For XLEN >32, `fcvt.w.s` sign-extends the 32-bit result to the destination register width.
+
+          If the rounded result is not representable as a 32-bit signed integer, it is clipped to the
+          nearest value and the invalid flag is set.
+
+          The range of valid inputs and behavior for invalid inputs are:
+
+          [separator="!"]
+          !===
+          ! ! Value
+
+          h! Minimum valid input (after rounding) ! `-2^31`
+          h! Maximum valid input (after rounding) ! `2^31 - 1`
+          h! Output for out-of-range negative input ! `-2^31`
+          h! Output for `-∞` ! `-2^31`
+          h! Output for out-of-range positive input ! `2^31 - 1`
+          h! Output for `+∞` for `NaN` ! `2^31 - 1`
+          !===
+
+          All floating-point to integer and integer to floating-point conversion instructions round
+          according to the _rm_ field.
+          A floating-point register can be initialized to floating-point positive zero using
+          `fcvt.s.w rd, x0`, which will never set any exception flags.
+
+          All floating-point conversion instructions set the Inexact exception flag if the rounded
+          result differs from the operand value and the Invalid exception flag is not set.
+
+  definedBy: F
+  assembly: xd, fs1
+  encoding:
+    match: 110000000000-------------1010011
+    variables:
+    - name: fs1
+      location: 19-15
+    - name: rm
+      location: 14-12
+    - name: rd
+      location: 11-7
+  access:
+    s: always
+    u: always
+    vs: always
+    vu: always
+  data_independent_timing: true
+  operation(): |
+

arch/inst/F/fcvt.wu.s.yaml

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+# yaml-language-server: $schema=../../../schemas/inst_schema.json
+
+fcvt.wu.s:
+  long_name: No synopsis available.
+  description: |
+      No description available.
+  definedBy: F
+  assembly: xd, xs1, rm
+  encoding:
+    match: 110000000001-------------1010011
+    variables:
+    - name: rs1
+      location: 19-15
+    - name: rm
+      location: 14-12
+    - name: rd
+      location: 11-7
+  access:
+    s: always
+    u: always
+    vs: always
+    vu: always
+  data_independent_timing: true
+  operation(): |
+

arch/inst/F/fdiv.s.yaml

@@ -0,0 +1,27 @@
+# yaml-language-server: $schema=../../../schemas/inst_schema.json
+
+fdiv.s:
+  long_name: No synopsis available.
+  description: |
+      No description available.
+  definedBy: F
+  assembly: xd, xs1, xs2, rm
+  encoding:
+    match: 0001100------------------1010011
+    variables:
+    - name: rs2
+      location: 24-20
+    - name: rs1
+      location: 19-15
+    - name: rm
+      location: 14-12
+    - name: rd
+      location: 11-7
+  access:
+    s: always
+    u: always
+    vs: always
+    vu: always
+  data_independent_timing: true
+  operation(): |
+