diff --git a/backends/instructions_appendix/all_instructions.golden.adoc b/backends/instructions_appendix/all_instructions.golden.adoc index 3477142770..531c0438fe 100644 --- a/backends/instructions_appendix/all_instructions.golden.adoc +++ b/backends/instructions_appendix/all_instructions.golden.adoc @@ -17765,7 +17765,7 @@ Included in:: == sctrclr Synopsis:: -No synopsis available +Supervisor Control Transfer Record (CTR) clear Encoding:: [wavedrom, ,svg,subs='attributes',width="100%"] @@ -17774,7 +17774,27 @@ Encoding:: .... Description:: -No description available. +When xref:csrs:mstateen0.adoc#udb:doc:csr_field:mstateen0:CTR[mstateen0.CTR]=1, the SCTRCLR instruction performs the following operations: + +* Zeroes all CTR Entry Registers, for all DEPTH values +* Reset to Zero the optional CTR cycle counter where implemented +** `ctrdata.CC` and `ctrdata.CCV` bit fields. + +Any read of `ctrsource`, `ctrtarget`, or `ctrdata` that follows SCTRCLR, such that it precedes the next +qualified control transfer, will return the value 0. + +Further, the first recorded transfer following SCTRCLR will have `ctrdata.CCV`=0. + +SCTRCLR execution causes an `IllegalInstruction` exception if: + +* xref:exts:Smctr.adoc#udb:doc:ext:Smctr[Smctr] is not implemented +* The instruction is executed in S/VS/VU-mode and xref:exts:Ssctr.adoc#udb:doc:ext:Ssctr[Ssctr] is not implemented, or xref:csrs:mstateen0.adoc#udb:doc:csr_field:mstateen0:CTR[mstateen0.CTR]=0 +* The instruction is executed in U-mode + +SCTRCLR execution causes a `VirtualInstruciton` exception if xref:csrs:mstateen0.adoc#udb:doc:csr_field:mstateen0:CTR[mstateen0.CTR]=1 and: + +* The instruction is executed in VS-mode and xref:csrs:hstateen0.adoc#udb:doc:csr_field:hstateen0:CTR[hstateen0.CTR]=0 +* The instruction is executed in VU-mode Decode Variables:: @@ -17785,7 +17805,9 @@ Included in:: |=== | Extension | Version -| *Smdbltrp* | ~> 1.0.0 +| *Smctr* | ~> 1.0.0 + +| *Ssctr* | ~> 1.0.0 |=== diff --git a/spec/std/isa/ext/Smctr.yaml b/spec/std/isa/ext/Smctr.yaml new file mode 100644 index 0000000000..9f3aab49fd --- /dev/null +++ b/spec/std/isa/ext/Smctr.yaml @@ -0,0 +1,58 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../schemas/ext_schema.json + +$schema: "ext_schema.json#" +kind: extension +name: Smctr +long_name: Control Transfer Records +description: | + A method for recording control flow transfer history is valuable not only for performance + profiling but also for debugging. + Control flow transfers refer to jump instructions (including function calls and returns), taken + branch instructions, traps, and trap returns. + Profiling tools, such as Linux perf, collect control transfer history when sampling software + execution, thereby enabling tools, like AutoFDO, to identify hot paths for optimization. + + Control flow trace capabilities offer very deep transfer history, but the volume of data produced + can result in significant performance overheads due to memory bandwidth consumption, buffer + management, and decoder overhead. + The Control Transfer Records (CTR) extension provides a method to record a limited history in + register-accessible internal chip storage, with the intent of dramatically reducing the + performance overhead and complexity of collecting transfer history. + + CTR defines a circular (FIFO) buffer. Each buffer entry holds a record for a single recorded + control flow transfer. + The number of records that can be held in the buffer depends upon both the implementation (the + maximum supported depth) and the CTR configuration (the software selected depth). + + Only qualified transfers are recorded. + Qualified transfers are those that meet the filtering criteria, which include the privilege mode + and the transfer type. + + Recorded transfers are inserted at the write pointer, which is then incremented, while older + recorded transfers may be overwritten once the buffer is full. + Or the user can enable RAS (Return Address Stack) emulation mode, where only function calls are + recorded, and function returns pop the last call record. + The source PC, target PC, and some optional metadata (transfer type, elapsed cycles) are stored + for each recorded transfer. + + The CTR buffer is accessible through an indirect CSR interface, such that software can specify + which logical entry in the buffer it wishes to read or write. + Logical entry 0 always corresponds to the youngest recorded transfer, followed by entry 1 as the + next youngest, and so on. +type: privileged +versions: + - version: "1.0.0" + state: ratified + ratification_date: 2024-11 + implies: + name: Ssctr + version: "1.0.0" + requires: + allOf: + - name: S + version: ~> 1.13 # The latest ratified version of S when Sscntr was ratified + - name: Smcsrind + version: ~> 1.0 diff --git a/spec/std/isa/ext/Ssctr.yaml b/spec/std/isa/ext/Ssctr.yaml new file mode 100644 index 0000000000..36a2e6d707 --- /dev/null +++ b/spec/std/isa/ext/Ssctr.yaml @@ -0,0 +1,22 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../schemas/ext_schema.json + +$schema: "ext_schema.json#" +kind: extension +name: Ssctr +long_name: Control Transfer Records +description: | + The supervisor view of `Smctr`. +type: privileged +versions: + - version: "1.0.0" + state: ratified + ratification_date: 2024-11 + requires: + allOf: + - name: S + version: ~> 1.13 # The latest ratified version of S when Sscntr was ratified + - name: Sscsrind + version: ~> 1.0 diff --git a/spec/std/isa/inst/Smdbltrp/sctrclr.yaml b/spec/std/isa/inst/Smdbltrp/sctrclr.yaml index 8dd49d276e..5224c70869 100644 --- a/spec/std/isa/inst/Smdbltrp/sctrclr.yaml +++ b/spec/std/isa/inst/Smdbltrp/sctrclr.yaml @@ -6,10 +6,31 @@ $schema: inst_schema.json# kind: instruction name: sctrclr -long_name: No synopsis available +long_name: Supervisor Control Transfer Record (CTR) clear description: | - No description available. -definedBy: Smdbltrp + When `mstateen0.CTR`=1, the SCTRCLR instruction performs the following operations: + + * Zeroes all CTR Entry Registers, for all DEPTH values + * Reset to Zero the optional CTR cycle counter where implemented + ** `ctrdata.CC` and `ctrdata.CCV` bit fields. + + Any read of `ctrsource`, `ctrtarget`, or `ctrdata` that follows SCTRCLR, such that it precedes the next + qualified control transfer, will return the value 0. + + Further, the first recorded transfer following SCTRCLR will have `ctrdata.CCV`=0. + + SCTRCLR execution causes an `IllegalInstruction` exception if: + + * `Smctr` is not implemented + * The instruction is executed in S/VS/VU-mode and `Ssctr` is not implemented, or `mstateen0.CTR`=0 + * The instruction is executed in U-mode + + SCTRCLR execution causes a `VirtualInstruciton` exception if `mstateen0.CTR`=1 and: + + * The instruction is executed in VS-mode and `hstateen0.CTR`=0 + * The instruction is executed in VU-mode +definedBy: + anyOf: [Smctr, Ssctr] assembly: "" encoding: match: "00010000010000000000000001110011"