feat: support CSR[name].reset_value() in IDL

.vscode/launch.json

@@ -5,8 +5,8 @@
       "name": "ISS debug Launch",
       "type": "cppdbg",
       "request": "launch",
-      "program": "${workspaceFolder}/gen/cpp_hart_gen/rv32_Debug/build/iss",
-      "args": ["-m", "rv32", "-c", "${workspaceFolder}/cfgs/rv32-riscv-tests.yaml", "${workspaceFolder}/ext/riscv-tests/isa/rv32ui-p-addi"],
+      "program": "${workspaceFolder}/gen/cpp_hart_gen/rv64_Debug/build/iss",
+      "args": ["-m", "rv64", "-c", "${workspaceFolder}/cfgs/rv64-riscv-tests.yaml", "${workspaceFolder}/ext/riscv-tests/isa/rv64ui-p-addi"],
       "stopAtEntry": true,
       "cwd": "${workspaceFolder}",
       "environment": [],

backends/cpp_hart_gen/cpp/include/udb/bits.hpp

@@ -694,6 +694,10 @@ namespace udb {
       }
     }
 
+    constexpr std::conditional_t<Signed, SignedStorageType, const StorageType &> get_ignore_unknown() const {
+      return m_val;
+    }
+
     constexpr const _Bits& to_defined() const { return *this; }
 
     // cast to other Bits types
@@ -3467,7 +3471,7 @@ struct fmt::formatter<BitsClass<N, Signed>>
     : formatter<typename BitsClass<N, Signed>::StorageType> {
   template <typename CONTEXT_TYPE>
   auto format(BitsClass<N, Signed> value, CONTEXT_TYPE &ctx) const {
-    return fmt::formatter<typename BitsClass<N, Signed>::StorageType>::format(value.get(), ctx);
+    return fmt::formatter<typename BitsClass<N, Signed>::StorageType>::format(value.get_ignore_unknown(), ctx);
   }
 };
 

backends/cpp_hart_gen/lib/gen_cpp.rb

@@ -270,6 +270,8 @@ def gen_cpp(symtab, indent = 2, indent_spaces: 2)
       if csr_obj.nil?
         if function_name == "sw_read"
           "#{' ' * indent}__UDB_CSR_BY_ADDR(#{csr.idx_expr.gen_cpp(symtab, 0, indent_spaces:)}).#{function_name}(__UDB_XLEN)"
+        elsif function_name == "reset_value"
+          "#{' ' * indent}__UDB_CSR_BY_ADDR(#{csr.idx_expr.gen_cpp(symtab, 0, indent_spaces:)})._#{function_name}()"
         else
           "#{' ' * indent}__UDB_CSR_BY_ADDR(#{csr.idx_expr.gen_cpp(symtab, 0, indent_spaces:)}).#{function_name.gsub('?', '_Q_')}(#{args_cpp.join(', ')})"
         end
@@ -280,6 +282,8 @@ def gen_cpp(symtab, indent = 2, indent_spaces: 2)
           else
             "#{' ' * indent}__UDB_CSR_BY_NAME(#{csr_obj.name})._#{function_name}()"
           end
+        elsif function_name == "reset_value"
+          "#{' ' * indent}__UDB_CSR_BY_NAME(#{csr_obj.name})._#{function_name}()"
         else
           "#{' ' * indent}__UDB_CSR_BY_NAME(#{csr_obj.name}).#{function_name.gsub('?', '_Q_')}(#{args_cpp.join(', ')})"
         end

backends/cpp_hart_gen/templates/csrs.hxx.erb

@@ -213,6 +213,17 @@ namespace udb {
     const std::string name() const override { return "<%= csr.name %>"; }
     PrivilegeMode mode() const override { return PrivilegeMode::<%= csr.priv_mode %>; }
     bool writable() const override { return <%= csr.writable %>; }
+    ValueType _reset_value() const {
+      if (defined()) {
+        return 0_b
+        <%- fields_for_xlen.each do |field| -%>
+        | (m_<%= field.name %>.reset_value() << _Bits<64, false>(m_<%= field.name %>.location().lsb))
+        <%- end -%>
+        ;
+      } else {
+        "x"_xb;
+      }
+    }
 
     bool defined() override {
       return <%= csr.defined_by_condition.to_cxx { |ext_name, ext_req|
@@ -254,7 +265,7 @@ namespace udb {
       } else {
         udb_assert(xlen == 64_b, "Bad xlen");
         <%-
-          field_cpp = fields_for_xlen32.map do |field|
+          field_cpp = fields_for_xlen64.map do |field|
             if field.dynamic_location?
               "((m_#{field.name}._hw_read() & 0x#{((1 << field.location(64).size) - 1).to_s(16)}_b).template widening_sll<#{field.location(64).begin}>())"
             else

backends/cpp_hart_gen/templates/hart.hxx.erb

@@ -402,12 +402,9 @@ namespace udb {
         _set_xreg(Bits<8>{num}, Bits<MXLEN>{value});
       }
 
-      template <
-        template <unsigned, bool> class IdxType, unsigned IdxN, bool IdxSigned,
-        template<unsigned, bool> class ValueType, unsigned ValueN, bool ValueSigned
-      >
-        requires (BitsType<IdxType<IdxN, IdxSigned>> && BitsType<ValueType<ValueN, ValueSigned>>)
-      void _set_xreg(const IdxType<IdxN, IdxSigned>& num, const ValueType<ValueN, ValueSigned>& value) {
+      template < template <unsigned, bool> class IdxType, unsigned IdxN, bool IdxSigned >
+        requires (BitsType<IdxType<IdxN, IdxSigned>>)
+      void _set_xreg(const IdxType<IdxN, IdxSigned>& num, const _PossiblyUnknownBits<MXLEN, false>& value) {
         if (num != 0_b) {
           m_xregs[static_cast<unsigned>(num.get())] = value;
         }

cfgs/rv64-riscv-tests.yaml

@@ -0,0 +1,128 @@
+# yaml-language-server: $schema=../schemas/config_schema.json
+---
+$schema: https://riscv.org/udb/schemas/config_schema-0.1.0.json
+kind: architecture configuration
+type: fully configured
+name: rv64-riscv-tests
+description: A compliant full config for rv64 riscv-tests
+implemented_extensions:
+  - [Sm, "1.11.0"]
+  - [I, "2.1"]
+  - [C, "2.0"]
+  - [M, "2.0"]
+  - [Zicsr, "2.0"]
+  - [Zicntr, "2.0"]
+  - [Smrnmi, "1.0"]
+  - [S, "1.11.0"]
+  - [Smpmp, "1.11.0"]
+  - [U, "1.0.0"]
+  - [Zifencei, "2.0.0"]
+  - [Sv32, "1.11.0"]
+
+params:
+  MXLEN: 64
+  ARCH_ID: 0
+  IMP_ID: 0
+  VENDOR_ID_BANK: 1
+  VENDOR_ID_OFFSET: 1
+  MISALIGNED_LDST: true
+  MISALIGNED_LDST_EXCEPTION_PRIORITY: low
+  MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE: 4
+  MISALIGNED_SPLIT_STRATEGY: by_byte
+  PRECISE_SYNCHRONOUS_EXCEPTIONS: true
+  TRAP_ON_ECALL_FROM_M: true
+  TRAP_ON_EBREAK: true
+  M_MODE_ENDIANNESS: little
+  TRAP_ON_ILLEGAL_WLRL: true
+  TRAP_ON_UNIMPLEMENTED_INSTRUCTION: true
+  TRAP_ON_RESERVED_INSTRUCTION: true
+  TRAP_ON_UNIMPLEMENTED_CSR: true
+  REPORT_VA_IN_MTVAL_ON_BREAKPOINT: true
+  REPORT_VA_IN_MTVAL_ON_LOAD_MISALIGNED: true
+  REPORT_VA_IN_MTVAL_ON_STORE_AMO_MISALIGNED: true
+  REPORT_VA_IN_MTVAL_ON_INSTRUCTION_MISALIGNED: true
+  REPORT_VA_IN_MTVAL_ON_LOAD_ACCESS_FAULT: true
+  REPORT_VA_IN_MTVAL_ON_STORE_AMO_ACCESS_FAULT: true
+  REPORT_VA_IN_MTVAL_ON_INSTRUCTION_ACCESS_FAULT: true
+  REPORT_ENCODING_IN_MTVAL_ON_ILLEGAL_INSTRUCTION: true
+  MTVAL_WIDTH: 32
+  PMA_GRANULARITY: 12
+  PHYS_ADDR_WIDTH: 57
+  MISA_CSR_IMPLEMENTED: true
+  MTVEC_MODES: [0, 1]
+  MTVEC_BASE_ALIGNMENT_DIRECT: 4
+  MTVEC_BASE_ALIGNMENT_VECTORED: 4
+  MUTABLE_MISA_C: false
+  MUTABLE_MISA_M: false
+  TIME_CSR_IMPLEMENTED: false
+  MUTABLE_MISA_S: false
+  ASID_WIDTH: 5
+  S_MODE_ENDIANNESS: little
+  SXLEN: 64
+  REPORT_VA_IN_MTVAL_ON_LOAD_PAGE_FAULT: true
+  REPORT_VA_IN_MTVAL_ON_STORE_AMO_PAGE_FAULT: true
+  REPORT_VA_IN_MTVAL_ON_INSTRUCTION_PAGE_FAULT: true
+  REPORT_VA_IN_STVAL_ON_BREAKPOINT: true
+  REPORT_VA_IN_STVAL_ON_LOAD_MISALIGNED: true
+  REPORT_VA_IN_STVAL_ON_STORE_AMO_MISALIGNED: true
+  REPORT_VA_IN_STVAL_ON_INSTRUCTION_MISALIGNED: true
+  REPORT_VA_IN_STVAL_ON_LOAD_ACCESS_FAULT: true
+  REPORT_VA_IN_STVAL_ON_STORE_AMO_ACCESS_FAULT: true
+  REPORT_VA_IN_STVAL_ON_INSTRUCTION_ACCESS_FAULT: true
+  REPORT_VA_IN_STVAL_ON_LOAD_PAGE_FAULT: true
+  REPORT_VA_IN_STVAL_ON_STORE_AMO_PAGE_FAULT: true
+  REPORT_VA_IN_STVAL_ON_INSTRUCTION_PAGE_FAULT: true
+  REPORT_ENCODING_IN_STVAL_ON_ILLEGAL_INSTRUCTION: true
+  STVAL_WIDTH: 32
+  SCOUNTENABLE_EN:
+    [
+      false,
+      false,
+      false,
+      false,
+      false,
+      false,
+      false,
+      false,
+      false,
+      false,
+      false,
+      false,
+      false,
+      false,
+      false,
+      false,
+      false,
+      false,
+      false,
+      false,
+      false,
+      false,
+      false,
+      false,
+      false,
+      false,
+      false,
+      false,
+      false,
+      false,
+      false,
+      false,
+    ]
+  STVEC_MODE_DIRECT: true
+  STVEC_MODE_VECTORED: true
+  SATP_MODE_BARE: true
+  TRAP_ON_ECALL_FROM_S: true
+  TRAP_ON_SFENCE_VMA_WHEN_SATP_MODE_IS_READ_ONLY: false
+  MSTATUS_FS_WRITABLE: false
+  MSTATUS_VS_WRITABLE: false
+  MSTATUS_VS_LEGAL_VALUES: [0]
+  MSTATUS_FS_LEGAL_VALUES: [0]
+  MSTATUS_TVM_IMPLEMENTED: false
+  NUM_PMP_ENTRIES: 16
+  PMP_GRANULARITY: 12
+  MUTABLE_MISA_U: false
+  U_MODE_ENDIANNESS: little
+  UXLEN: 64
+  MSTATEEN_ENVCFG_TYPE: rw
+  HSTATEEN_ENVCFG_TYPE: rw

spec/std/isa/csr/mstatus.yaml

@@ -143,13 +143,13 @@ fields:
     description: |
       *S-mode XLEN*
 
-      Sets the effective XLEN for S-mode (0 = 32-bit, 1 = 64-bit, 2 = 128-bit [reserved]).
+      Sets the effective XLEN for S-mode (1 = 32-bit, 2 = 64-bit, 3 = 128-bit [reserved]).
 
       [when,"SXLEN==32"]
-      Since the CPU only supports SXLEN==32, this is hardwired to 0.
+      Since the CPU only supports SXLEN==32, this is hardwired to 1.
 
-      [when,"SXLEN==32"]
-      Since the CPU only supports SXLEN==64, this is hardwired to 1.
+      [when,"SXLEN==64"]
+      Since the CPU only supports SXLEN==64, this is hardwired to 2.
 
       [when,"SXLEN=3264"]
       --
@@ -164,26 +164,34 @@ fields:
 
     legal?(csr_value): |
       if (SXLEN == 32) {
-        # SXLEN == 32 is encoded as 0
-        return csr_value.SXL == 0;
-      } else if (SXLEN == 64) {
-        # SXLEN == 64 is encoded as 1
+        # SXLEN == 32 is encoded as 1
         return csr_value.SXL == 1;
+      } else if (SXLEN == 64) {
+        # SXLEN == 64 is encoded as 2
+        return csr_value.SXL == 2;
       } else {
         # SXLEN could be 32 or 64
-        return csr_value.SXL <= 1;
+        return (csr_value.SXL >= 1 && csr_value.SXL <= 2);
       }
 
     sw_write(csr_value): |
       if (csr_value.SXL < csr_value.UXL) {
-        return UNDEFINED_LEGAL_DETERMINISTIC;
-      } else if (csr_value.SXL > 1) {
-        # SXL != [0, 1] is not defined (2 reserved for RV128, but that isn't ratified)
-        return UNDEFINED_LEGAL_DETERMINISTIC;
+        return CSR[mstatus].SXL;
+      } else if (csr_value.SXL < 1 || csr_value.SXL > 2) {
+        # SXL != [1, 2] is not defined (3 reserved for RV128, but that isn't ratified)
+        return CSR[mstatus].SXL;
       } else {
         return csr_value.SXL;
       }
-    reset_value: UNDEFINED_LEGAL
+
+    reset_value(): |
+      if (SXLEN == 32) {
+        return 1;
+      } else if (SXLEN == 64) {
+        return 2;
+      } else {
+        return 2;
+      }
 
   UXL:
     location: 33-32
@@ -192,13 +200,13 @@ fields:
     description: |
       U-mode XLEN.
 
-      Sets the effective XLEN for U-mode (0 = 32-bit, 1 = 64-bit, 2 = 128-bit [reserved]).
+      Sets the effective XLEN for U-mode (1 = 32-bit, 2 = 64-bit, 3 = 128-bit [reserved]).
 
       [when,"UXLEN == 32"]
-      Since the CPU only supports UXLEN==32, this is hardwired to 0.
+      Since the CPU only supports UXLEN==32, this is hardwired to 1.
 
       [when,"UXLEN == 64"]
-      Since the CPU only supports UXLEN==64, this is hardwired to 1.
+      Since the CPU only supports UXLEN==64, this is hardwired to 2.
 
 
       [when,"UXLEN == 3264"]
@@ -214,30 +222,30 @@ fields:
 
     sw_write(csr_value): |
       if (csr_value.SXL < csr_value.UXL) {
-        return UNDEFINED_LEGAL_DETERMINISTIC;
-      } else if (csr_value.UXL > 1) {
-        # UXL != [0, 1] is not defined (2 reserved for RV128, but that isn't ratified)
-        return UNDEFINED_LEGAL_DETERMINISTIC;
+        return CSR[mstatus].UXL;
+      } else if (csr_value.UXL < 1 || csr_value.UXL > 2) {
+        # UXL != [1, 2] is not defined (3 reserved for RV128, but that isn't ratified)
+        return CSR[mstatus].UXL;
       } else {
         return csr_value.UXL;
       }
 
     legal?(csr_value): |
       if (UXLEN == 32) {
-        return csr_value.UXL == 0;
-      } else if (UXLEN == 64) {
         return csr_value.UXL == 1;
+      } else if (UXLEN == 64) {
+        return csr_value.UXL == 2;
       } else {
-        return csr_value.UXL <= 1;
+        return (csr_value.UXL >= 1 && csr_value.UXL <= 2);
       }
 
     reset_value(): |
       if (UXLEN == 32) {
-        return 0;
-      } else if (UXLEN == 64) {
         return 1;
+      } else if (UXLEN == 64) {
+        return 2;
       } else {
-        return UNDEFINED_LEGAL;
+        return 2;
       }
 
   TSR:

spec/std/isa/csr/sstatus.yaml

@@ -28,12 +28,12 @@ fields:
       Alias of `mstatus.SD`.
 
     type: RO-H
-    reset_value: UNDEFINED_LEGAL
+    reset_value(): return CSR[mstatus].reset_value();
     affectedBy: [F, D, V]
   UXL:
     location: 33-32
     base: 64
-    alias: mstatus.MXR
+    alias: mstatus.UXL
     description: |
       *U-mode XLEN*
 

spec/std/isa/inst/C/c.addiw.yaml

@@ -36,4 +36,4 @@ operation(): |
     raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
   }
 
-  X[xd] = sext((X[xd] + imm), 32);
+  X[xd] = sext((X[xd] + sext(imm, 6)), 32);

spec/std/isa/inst/C/c.subw.yaml

@@ -32,7 +32,7 @@ access:
 operation(): |
   Bits<32> t0 = X[creg2reg(xd)][31:0];
   Bits<32> t1 = X[creg2reg(xs2)][31:0];
-  X[creg2reg(xd)] = sext(t0 - t1, 31);
+  X[creg2reg(xd)] = sext(t0 - t1, 32);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

spec/std/isa/inst/I/addiw.yaml

@@ -30,8 +30,7 @@ pseudoinstructions:
   - when: imm == 0
     to: sext.w xd,xs1
 operation(): |
-  XReg operand = sext(X[xs1], 31);
-  X[xd] = sext(operand + imm, 31);
+  X[xd] = $signed((X[xs1] + $signed(imm))[31:0]);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

spec/std/isa/inst/I/addw.yaml

@@ -29,9 +29,9 @@ access:
   vu: always
 data_independent_timing: true
 operation(): |
-  XReg operand1 = sext(X[xs1], 31);
-  XReg operand2 = sext(X[xs2], 31);
-  X[xd] = sext(operand1 + operand2, 31);
+  XReg operand1 = sext(X[xs1], 32);
+  XReg operand2 = sext(X[xs2], 32);
+  X[xd] = sext(operand1 + operand2, 32);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>