From 6d0ea1f2d414bf577d46220a242103ac9031ad1b Mon Sep 17 00:00:00 2001 From: jacassidy Date: Tue, 11 Nov 2025 15:27:14 -0800 Subject: [PATCH 01/14] first set of vector params --- spec/std/isa/ext/V.yaml | 120 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 120 insertions(+) diff --git a/spec/std/isa/ext/V.yaml b/spec/std/isa/ext/V.yaml index ae1422fa05..6a14c19590 100644 --- a/spec/std/isa/ext/V.yaml +++ b/spec/std/isa/ext/V.yaml @@ -15,6 +15,126 @@ versions: description: | TODO params: + ELEN: + description: | + The maximum size in bits of a vector element that any operation can produce or consume, _ELEN_ {ge} 8, which + must be a power of 2. + schema: + type: integer + enum: [8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536] + VLEN: + description: + The number of bits in a single vector register, _VLEN_ {ge} ELEN, which must be a power of 2, and must be no greater than 2^16^. + schema: + type: integer + enum: [8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536] + VILL_IMPLICIT_ENCODING: + description: | + A small implementation supporting ELEN=32 requires only seven bits of state in `vtype`: two bits for `ma` and `ta`, two bits for `vsew[1:0]` and three bits for `vlmul[2:0]`. The illegal value represented by `vill` can be internally encoded using the illegal 64-bit combination in `vsew[1:0]` without requiring an additional storage + bit to hold `vill`.: + schema: + type: boolean + MUTABLE_MISA_V: + description: Implementations may have a writable `misa.V` field. + schema: + type: boolean + HW_MSTATUS_VS_DIRTY_UPDATE: + description: | + Implementations may also change `mstatus.VS` or `vsstatus.VS` from Initial or + Clean to Dirty at any time, even when there is no change in vector state. + schema: + type: string + enum: ["never", "precise", "imprecise", "custom"] + MSTATUS_VS_EXISTS: + description: | + Analogous to the way in which the floating-point unit is handled, the `mstatus.VS` field may exist even if `misa.V` is clear. + schema: + type: boolean + RESERVED_VILL_SET: + description: | + When _rs1_=`x0` and _rd_=`x0`, the instructions operate as if the current vector length in `vl` is used as the AVL... + Use of the instructions with a new SEW/LMUL ratio that would result in a change of VLMAX is reserved. + Use of the instructions is also reserved if `vill` was 1 beforehand. Implementations may set `vill` in either case. + schema: + type: string + enum: ["never", "on_vlmax_change", "on_vill_set", "always", "custom"] + VECTOR_FF_PAST_TRAP: + description: + Similarly, fault-only-first load instructions may update active destination elements past the element that causes trimming + of the vector length (but not past the original vector length). The values of these spurious updates do not have to correspond + to the values in memory at the addressed memory locations. Non-idempotent memory locations can only be accessed when it is known + the corresponding element load operation will not be restarted due to a trap or vector-length trimming. + schema: + type: string + enum: ["update_none", "custom"] + VECTOR_FF_SEG_PARTIAL_ACCESS: + description: | + For fault-only-first segment loads, if an exception is detected partway + through accessing the zeroth segment, the trap is taken. + If an exception is detected partway through accessing a subsequent segment, + `vl` is reduced to the index of that segment. + In both cases, it is implementation-defined whether a subset of the segment is + loaded. + schema: + type: string + enum: ["no_subsegment_loaded", "custom"] + VECTOR_LS_MISSALIGNED_EXCEPTION: + description: | + If an element accessed by a vector memory instruction is not naturally + aligned to the size of the element, either the element is transferred + successfully or an address-misaligned exception is raised on that + element. + schema: + type: string + enum: ["element_loaded_no_exception", "address-misaligned_exception"] + VECTOR_LS_OVERWRITE_PAST_TRAP: + description: | + Load instructions may overwrite active destination vector register + group elements past the element index at which the trap is reported. + schema: + type: string + enum: ["preserve_inactive", "custom"] + VECTOR_LS_SEG_FF_OVERLOAD: + description: | + These instructions may overwrite destination vector register group + elements past the point at which a trap is reported or past the point + at which vector length is trimmed. + schema: + type: string + enum: ["no_overwrite", "custom"] + VECTOR_LS_SEG_PARTIAL_ACCESS: + description: | + If a trap occurs during + access to a segment, it is implementation-defined whether a subset + of the faulting segment's accesses are performed before the trap is taken. + schema: + type: string + enum: ["no_partial", "custom"] + LEGAL_VSTART: + description: | + Implementations are permitted to raise illegal-instruction exceptions when + attempting to execute a vector instruction with a value of `vstart` that the + implementation can never produce when executing that same instruction with + the same `vtype` setting. + schema: + type: string + enum: ["1_stride", "2_stride", "4_stride", "custom"] + VECTOR_LS_WHOLEREG_MISSALIGNED_EXCEPTION: + description: | + Implementations are allowed to raise a misaligned address exception on + whole register loads and stores if the base address is not naturally + aligned to the larger of the size of the encoded EEW in bytes (EEW/8) + or the implementation's smallest supported SEW size in bytes + (SEW~MIN~/8). + schema: + type: string + enum: ["misaligned_exception", "permitted"] + VSSTATUS_VS_EXISTS: + description: | + For implementations with a writable `misa.V` field, + the `vsstatus.VS` field may exist even if `misa.V` is clear. + schema: + type: boolean MUTABLE_MISA_V: description: | Indicates whether or not the `V` extension can be disabled with the `misa.V` bit. From ac9c774f6cb39fdf05a91feccc04c610715f36d7 Mon Sep 17 00:00:00 2001 From: jacassidy Date: Tue, 11 Nov 2025 17:17:45 -0800 Subject: [PATCH 02/14] first draft vector parameters --- spec/std/isa/ext/V.yaml | 88 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 87 insertions(+), 1 deletion(-) diff --git a/spec/std/isa/ext/V.yaml b/spec/std/isa/ext/V.yaml index 6a14c19590..27b2c7ffaf 100644 --- a/spec/std/isa/ext/V.yaml +++ b/spec/std/isa/ext/V.yaml @@ -23,11 +23,45 @@ params: type: integer enum: [8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536] VLEN: - description: + description: | The number of bits in a single vector register, _VLEN_ {ge} ELEN, which must be a power of 2, and must be no greater than 2^16^. schema: type: integer enum: [8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536] + SEWmin: + description: | + Implementations must provide fractional LMUL settings that allow the + narrowest supported type to occupy a fraction of a vector register + corresponding to the ratio of the narrowest supported type's width to + that of the largest supported type's width. In general, the + requirement is to support LMUL {ge} SEW~MIN~/ELEN, where SEW~MIN~ is + the narrowest supported SEW value and ELEN is the widest supported SEW + value. + schema: + type: integer + enum: [8, 16, 32, 64] + VECTOR_AGNOSTIC_BEHAVIOR: + description: + When a set is marked agnostic, the corresponding set of destination + elements in any vector destination operand can either retain the value + they previously held, or are overwritten with 1s. + schema: + type: string + enum: ["never_overwritten", "custom"] + SUPPORT_FRACTIONAL_LMUL_BEYOND_REQUIRED: + description: + For a given supported fractional LMUL setting, implementations must support + SEW settings between SEW~MIN~ and LMUL * ELEN, inclusive. + schema: + type: string + enum: ["no_unrequied_supported", "custom"] + VILL_SET_ON_RESERVED_VTYPE: + description: + The use of `vtype` encodings with LMUL < SEW~MIN~/ELEN is + __reserved__, but implementations can set `vill` if they do not + support these configurations. + schema: + type: boolean VILL_IMPLICIT_ENCODING: description: | A small implementation supporting ELEN=32 requires only seven bits of state in `vtype`: two bits for `ma` and `ta`, two bits for `vsew[1:0]` and three bits for `vlmul[2:0]`. The illegal value represented by `vill` can be internally encoded using the illegal 64-bit combination in `vsew[1:0]` without requiring an additional storage @@ -58,6 +92,13 @@ params: schema: type: string enum: ["never", "on_vlmax_change", "on_vill_set", "always", "custom"] + VECTOR_LS_INDEX_MAX_EEW: + description: + A profile may place an upper limit on the maximum supported index + EEW (e.g., only up to XLEN) smaller than ELEN. + schema: + type: integer + enum: [8, 16, 32, 64] VECTOR_FF_PAST_TRAP: description: Similarly, fault-only-first load instructions may update active destination elements past the element that causes trimming @@ -135,6 +176,51 @@ params: the `vsstatus.VS` field may exist even if `misa.V` is clear. schema: type: boolean + VECTOR_FF_NO_EXCEPTION_TRIM: + description: | + Even when an exception is not raised, implementations are permitted to process + fewer than `vl` elements and reduce `vl` accordingly, but if `vstart`=0 and + `vl`>0, then at least one element must be processed. + schema: + type: string + enum: ["no_trim", "custom"] + vfredosum_nan + VFREDOSUM_NAN: + description: | + As a consequence of this definition, implementations need not propagate + NaN payloads through the reduction tree when no elements are active. In + particular, if no elements are active and the scalar input is NaN, + implementations are permitted to canonicalize the NaN and, if the NaN is + signaling, set the invalid exception flag. Implementations are alternatively + permitted to pass through the original NaN and set no exception flags, as with + `vfredosum`. + schema: + type: string + enum: ["no_change", "custom"] + VSLIDE_OPTIMIZED_VALUES: + description: | + Implementations + may optimize certain OFFSET values for `vslideup` and `vslidedown`. + In particular, power-of-2 offsets may operate substantially faster + than other offsets. + schema: + type: string + enum: ["custom"] + IMPRECISE_VECTOR_TRAP_SETTABLE: + description: | + Some profiles may choose to provide a privileged mode bit to select between precise and imprecise vector traps. + schema: + type: boolean + FUSED_VSET_MICRO-OP: + description: + The primary motivation for the `vtype` CSR is to allow the + vector instruction set to fit into a 32-bit instruction encoding + space. A separate `vset{i}vl{i}` instruction can be used to set `vl` + and/or `vtype` fields before execution of a vector instruction, and + implementations may choose to fuse these two instructions into a single + internal vector microop. + schema: + type: boolean MUTABLE_MISA_V: description: | Indicates whether or not the `V` extension can be disabled with the `misa.V` bit. From 9edc04fc673af133eb0b2730d798eae067660205 Mon Sep 17 00:00:00 2001 From: jacassidy <47946874+jacassidy@users.noreply.github.com> Date: Wed, 12 Nov 2025 10:37:07 -0800 Subject: [PATCH 03/14] Update spec/std/isa/ext/V.yaml typo Co-authored-by: Paul Clarke Signed-off-by: jacassidy <47946874+jacassidy@users.noreply.github.com> --- spec/std/isa/ext/V.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/spec/std/isa/ext/V.yaml b/spec/std/isa/ext/V.yaml index 27b2c7ffaf..0b83e6bcf9 100644 --- a/spec/std/isa/ext/V.yaml +++ b/spec/std/isa/ext/V.yaml @@ -54,7 +54,7 @@ params: SEW settings between SEW~MIN~ and LMUL * ELEN, inclusive. schema: type: string - enum: ["no_unrequied_supported", "custom"] + enum: ["no_unrequired_supported", "custom"] VILL_SET_ON_RESERVED_VTYPE: description: The use of `vtype` encodings with LMUL < SEW~MIN~/ELEN is From b83601777b81e1515287505e4bc0ed9bd7d3fbc3 Mon Sep 17 00:00:00 2001 From: jacassidy <47946874+jacassidy@users.noreply.github.com> Date: Wed, 12 Nov 2025 10:39:13 -0800 Subject: [PATCH 04/14] Update spec/std/isa/ext/V.yaml Syntax for parameter names Co-authored-by: Paul Clarke Signed-off-by: jacassidy <47946874+jacassidy@users.noreply.github.com> --- spec/std/isa/ext/V.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/spec/std/isa/ext/V.yaml b/spec/std/isa/ext/V.yaml index 0b83e6bcf9..c4a6eda731 100644 --- a/spec/std/isa/ext/V.yaml +++ b/spec/std/isa/ext/V.yaml @@ -28,7 +28,7 @@ params: schema: type: integer enum: [8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536] - SEWmin: + SEW_MIN: description: | Implementations must provide fractional LMUL settings that allow the narrowest supported type to occupy a fraction of a vector register From e6c2e29970c2d60b4f47c612a97270a66d79e6b0 Mon Sep 17 00:00:00 2001 From: jacassidy <47946874+jacassidy@users.noreply.github.com> Date: Wed, 12 Nov 2025 10:42:14 -0800 Subject: [PATCH 05/14] Update spec/std/isa/ext/V.yaml Typo Co-authored-by: Paul Clarke Signed-off-by: jacassidy <47946874+jacassidy@users.noreply.github.com> --- spec/std/isa/ext/V.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/spec/std/isa/ext/V.yaml b/spec/std/isa/ext/V.yaml index c4a6eda731..1f1d2bf83f 100644 --- a/spec/std/isa/ext/V.yaml +++ b/spec/std/isa/ext/V.yaml @@ -185,7 +185,7 @@ params: type: string enum: ["no_trim", "custom"] vfredosum_nan - VFREDOSUM_NAN: + VFREDUSUM_NAN: description: | As a consequence of this definition, implementations need not propagate NaN payloads through the reduction tree when no elements are active. In From 58d2461ee586492a7242f7ad3489dcde38800f8f Mon Sep 17 00:00:00 2001 From: jacassidy <47946874+jacassidy@users.noreply.github.com> Date: Wed, 12 Nov 2025 10:42:43 -0800 Subject: [PATCH 06/14] Update spec/std/isa/ext/V.yaml punctuation Co-authored-by: Paul Clarke Signed-off-by: jacassidy <47946874+jacassidy@users.noreply.github.com> --- spec/std/isa/ext/V.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/spec/std/isa/ext/V.yaml b/spec/std/isa/ext/V.yaml index 1f1d2bf83f..c9d9d5637b 100644 --- a/spec/std/isa/ext/V.yaml +++ b/spec/std/isa/ext/V.yaml @@ -64,7 +64,7 @@ params: type: boolean VILL_IMPLICIT_ENCODING: description: | - A small implementation supporting ELEN=32 requires only seven bits of state in `vtype`: two bits for `ma` and `ta`, two bits for `vsew[1:0]` and three bits for `vlmul[2:0]`. The illegal value represented by `vill` can be internally encoded using the illegal 64-bit combination in `vsew[1:0]` without requiring an additional storage + A small implementation supporting ELEN=32 requires only seven bits of state in `vtype`: two bits for `ma` and `ta`, two bits for `vsew[1:0]` and three bits for `vlmul[2:0]`. The illegal value represented by `vill` can be internally encoded using the illegal 64-bit combination in `vsew[1:0]` without requiring an additional storage. bit to hold `vill`.: schema: type: boolean From 8d52853fd547779ef1420bbee4dbe9ee3242e644 Mon Sep 17 00:00:00 2001 From: jacassidy <47946874+jacassidy@users.noreply.github.com> Date: Wed, 12 Nov 2025 10:43:05 -0800 Subject: [PATCH 07/14] Update spec/std/isa/ext/V.yaml duplicate Co-authored-by: Paul Clarke Signed-off-by: jacassidy <47946874+jacassidy@users.noreply.github.com> --- spec/std/isa/ext/V.yaml | 4 ---- 1 file changed, 4 deletions(-) diff --git a/spec/std/isa/ext/V.yaml b/spec/std/isa/ext/V.yaml index c9d9d5637b..48eacebfd1 100644 --- a/spec/std/isa/ext/V.yaml +++ b/spec/std/isa/ext/V.yaml @@ -68,10 +68,6 @@ params: bit to hold `vill`.: schema: type: boolean - MUTABLE_MISA_V: - description: Implementations may have a writable `misa.V` field. - schema: - type: boolean HW_MSTATUS_VS_DIRTY_UPDATE: description: | Implementations may also change `mstatus.VS` or `vsstatus.VS` from Initial or From 6cc24a454720a1ed630d983fd59a5a8c9e6164a7 Mon Sep 17 00:00:00 2001 From: jacassidy <47946874+jacassidy@users.noreply.github.com> Date: Wed, 12 Nov 2025 10:48:50 -0800 Subject: [PATCH 08/14] Update spec/std/isa/ext/V.yaml Co-authored-by: Paul Clarke Signed-off-by: jacassidy <47946874+jacassidy@users.noreply.github.com> --- spec/std/isa/ext/V.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/spec/std/isa/ext/V.yaml b/spec/std/isa/ext/V.yaml index 48eacebfd1..771c73fb6d 100644 --- a/spec/std/isa/ext/V.yaml +++ b/spec/std/isa/ext/V.yaml @@ -95,7 +95,7 @@ params: schema: type: integer enum: [8, 16, 32, 64] - VECTOR_FF_PAST_TRAP: + VECTOR_FF_UPDATE_PAST_TRIM: description: Similarly, fault-only-first load instructions may update active destination elements past the element that causes trimming of the vector length (but not past the original vector length). The values of these spurious updates do not have to correspond From 2dd6085efda079c930a5aa2727a407e80954443a Mon Sep 17 00:00:00 2001 From: jacassidy <47946874+jacassidy@users.noreply.github.com> Date: Wed, 12 Nov 2025 10:49:34 -0800 Subject: [PATCH 09/14] Update spec/std/isa/ext/V.yaml Co-authored-by: Paul Clarke Signed-off-by: jacassidy <47946874+jacassidy@users.noreply.github.com> --- spec/std/isa/ext/V.yaml | 5 ----- 1 file changed, 5 deletions(-) diff --git a/spec/std/isa/ext/V.yaml b/spec/std/isa/ext/V.yaml index 771c73fb6d..602a21fe75 100644 --- a/spec/std/isa/ext/V.yaml +++ b/spec/std/isa/ext/V.yaml @@ -202,11 +202,6 @@ params: schema: type: string enum: ["custom"] - IMPRECISE_VECTOR_TRAP_SETTABLE: - description: | - Some profiles may choose to provide a privileged mode bit to select between precise and imprecise vector traps. - schema: - type: boolean FUSED_VSET_MICRO-OP: description: The primary motivation for the `vtype` CSR is to allow the From 071d63e1b3be8a25add5d73ecccc0bf6a872e34d Mon Sep 17 00:00:00 2001 From: jacassidy <47946874+jacassidy@users.noreply.github.com> Date: Wed, 12 Nov 2025 10:49:42 -0800 Subject: [PATCH 10/14] Update spec/std/isa/ext/V.yaml Co-authored-by: Paul Clarke Signed-off-by: jacassidy <47946874+jacassidy@users.noreply.github.com> --- spec/std/isa/ext/V.yaml | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/spec/std/isa/ext/V.yaml b/spec/std/isa/ext/V.yaml index 602a21fe75..92848404b9 100644 --- a/spec/std/isa/ext/V.yaml +++ b/spec/std/isa/ext/V.yaml @@ -202,16 +202,6 @@ params: schema: type: string enum: ["custom"] - FUSED_VSET_MICRO-OP: - description: - The primary motivation for the `vtype` CSR is to allow the - vector instruction set to fit into a 32-bit instruction encoding - space. A separate `vset{i}vl{i}` instruction can be used to set `vl` - and/or `vtype` fields before execution of a vector instruction, and - implementations may choose to fuse these two instructions into a single - internal vector microop. - schema: - type: boolean MUTABLE_MISA_V: description: | Indicates whether or not the `V` extension can be disabled with the `misa.V` bit. From 406e6d3adf061e9e6527958b13adb04ee463cf3f Mon Sep 17 00:00:00 2001 From: jacassidy <47946874+jacassidy@users.noreply.github.com> Date: Wed, 12 Nov 2025 10:52:42 -0800 Subject: [PATCH 11/14] Update spec/std/isa/ext/V.yaml Co-authored-by: Paul Clarke Signed-off-by: jacassidy <47946874+jacassidy@users.noreply.github.com> --- spec/std/isa/ext/V.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/spec/std/isa/ext/V.yaml b/spec/std/isa/ext/V.yaml index 92848404b9..f5cf11ef11 100644 --- a/spec/std/isa/ext/V.yaml +++ b/spec/std/isa/ext/V.yaml @@ -104,7 +104,7 @@ params: schema: type: string enum: ["update_none", "custom"] - VECTOR_FF_SEG_PARTIAL_ACCESS: + VECTOR_FF_SEG_EXCEPTION_PARTIAL_LOAD: description: | For fault-only-first segment loads, if an exception is detected partway through accessing the zeroth segment, the trap is taken. From ba209ced7477570cdd4475f52ef7fb10223371ee Mon Sep 17 00:00:00 2001 From: jacassidy <47946874+jacassidy@users.noreply.github.com> Date: Wed, 12 Nov 2025 10:53:16 -0800 Subject: [PATCH 12/14] Update spec/std/isa/ext/V.yaml Co-authored-by: Paul Clarke Signed-off-by: jacassidy <47946874+jacassidy@users.noreply.github.com> --- spec/std/isa/ext/V.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/spec/std/isa/ext/V.yaml b/spec/std/isa/ext/V.yaml index f5cf11ef11..b871defe88 100644 --- a/spec/std/isa/ext/V.yaml +++ b/spec/std/isa/ext/V.yaml @@ -124,7 +124,7 @@ params: schema: type: string enum: ["element_loaded_no_exception", "address-misaligned_exception"] - VECTOR_LS_OVERWRITE_PAST_TRAP: + VECTOR_LOAD_PAST_TRAP: description: | Load instructions may overwrite active destination vector register group elements past the element index at which the trap is reported. From 44e90e8c9262c986c156d1c7aa040302df4f8ff4 Mon Sep 17 00:00:00 2001 From: jacassidy <47946874+jacassidy@users.noreply.github.com> Date: Wed, 12 Nov 2025 11:35:29 -0800 Subject: [PATCH 13/14] Update spec/std/isa/ext/V.yaml better description Co-authored-by: Paul Clarke Signed-off-by: jacassidy <47946874+jacassidy@users.noreply.github.com> --- spec/std/isa/ext/V.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/spec/std/isa/ext/V.yaml b/spec/std/isa/ext/V.yaml index b871defe88..8ad1125a77 100644 --- a/spec/std/isa/ext/V.yaml +++ b/spec/std/isa/ext/V.yaml @@ -183,6 +183,7 @@ params: vfredosum_nan VFREDUSUM_NAN: description: | + The reduction tree structure must be deterministic for a given value in vtype and vl. As a consequence of this definition, implementations need not propagate NaN payloads through the reduction tree when no elements are active. In particular, if no elements are active and the scalar input is NaN, From 8d1733271da1f6d8887f6cb1a7b3b5faaeeb1a67 Mon Sep 17 00:00:00 2001 From: jacassidy Date: Wed, 12 Nov 2025 11:39:50 -0800 Subject: [PATCH 14/14] first round of comments --- spec/std/isa/ext/V.yaml | 61 ++++++++++++++--------------------------- 1 file changed, 21 insertions(+), 40 deletions(-) diff --git a/spec/std/isa/ext/V.yaml b/spec/std/isa/ext/V.yaml index 92848404b9..54604e4b1d 100644 --- a/spec/std/isa/ext/V.yaml +++ b/spec/std/isa/ext/V.yaml @@ -15,19 +15,21 @@ versions: description: | TODO params: - ELEN: + VLEN: description: | - The maximum size in bits of a vector element that any operation can produce or consume, _ELEN_ {ge} 8, which - must be a power of 2. + The number of bits in a single vector register, _VLEN_ {ge} ELEN, which must be a power of 2, and must be no greater than 2^16^. schema: type: integer enum: [8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536] - VLEN: + ELEN: description: | - The number of bits in a single vector register, _VLEN_ {ge} ELEN, which must be a power of 2, and must be no greater than 2^16^. + The maximum size in bits of a vector element that any operation can produce or consume, _ELEN_ {ge} 8, which + must be a power of 2. schema: type: integer enum: [8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536] + extra_validation: | + assert ELEN <= VLEN SEW_MIN: description: | Implementations must provide fractional LMUL settings that allow the @@ -40,6 +42,8 @@ params: schema: type: integer enum: [8, 16, 32, 64] + extra_validation: | + assert SEW_MIN <= ELEN VECTOR_AGNOSTIC_BEHAVIOR: description: When a set is marked agnostic, the corresponding set of destination @@ -62,24 +66,6 @@ params: support these configurations. schema: type: boolean - VILL_IMPLICIT_ENCODING: - description: | - A small implementation supporting ELEN=32 requires only seven bits of state in `vtype`: two bits for `ma` and `ta`, two bits for `vsew[1:0]` and three bits for `vlmul[2:0]`. The illegal value represented by `vill` can be internally encoded using the illegal 64-bit combination in `vsew[1:0]` without requiring an additional storage. - bit to hold `vill`.: - schema: - type: boolean - HW_MSTATUS_VS_DIRTY_UPDATE: - description: | - Implementations may also change `mstatus.VS` or `vsstatus.VS` from Initial or - Clean to Dirty at any time, even when there is no change in vector state. - schema: - type: string - enum: ["never", "precise", "imprecise", "custom"] - MSTATUS_VS_EXISTS: - description: | - Analogous to the way in which the floating-point unit is handled, the `mstatus.VS` field may exist even if `misa.V` is clear. - schema: - type: boolean RESERVED_VILL_SET: description: | When _rs1_=`x0` and _rd_=`x0`, the instructions operate as if the current vector length in `vl` is used as the AVL... @@ -95,6 +81,8 @@ params: schema: type: integer enum: [8, 16, 32, 64] + extra_validation: | + assert VECTOR_LS_INDEX_MAX_EEW <= ELEN VECTOR_FF_UPDATE_PAST_TRIM: description: Similarly, fault-only-first load instructions may update active destination elements past the element that causes trimming @@ -117,20 +105,19 @@ params: enum: ["no_subsegment_loaded", "custom"] VECTOR_LS_MISSALIGNED_EXCEPTION: description: | - If an element accessed by a vector memory instruction is not naturally - aligned to the size of the element, either the element is transferred - successfully or an address-misaligned exception is raised on that - element. + If an element accessed by a vector memory instruction is not naturally aligned to the size of the element, + either the element is transferred successfully or an address misaligned exception is raised on that element. + + Support for misaligned vector memory accesses is independent of an implementation’s support for misaligned scalar memory accesses. schema: - type: string - enum: ["element_loaded_no_exception", "address-misaligned_exception"] + type: boolean VECTOR_LS_OVERWRITE_PAST_TRAP: description: | Load instructions may overwrite active destination vector register group elements past the element index at which the trap is reported. schema: type: string - enum: ["preserve_inactive", "custom"] + enum: ["preserve_active", "custom"] VECTOR_LS_SEG_FF_OVERLOAD: description: | These instructions may overwrite destination vector register group @@ -164,8 +151,7 @@ params: or the implementation's smallest supported SEW size in bytes (SEW~MIN~/8). schema: - type: string - enum: ["misaligned_exception", "permitted"] + type: boolean VSSTATUS_VS_EXISTS: description: | For implementations with a writable `misa.V` field, @@ -180,7 +166,6 @@ params: schema: type: string enum: ["no_trim", "custom"] - vfredosum_nan VFREDUSUM_NAN: description: | As a consequence of this definition, implementations need not propagate @@ -193,15 +178,11 @@ params: schema: type: string enum: ["no_change", "custom"] - VSLIDE_OPTIMIZED_VALUES: + IMPRECISE_VECTOR_TRAP_SETTABLE: description: | - Implementations - may optimize certain OFFSET values for `vslideup` and `vslidedown`. - In particular, power-of-2 offsets may operate substantially faster - than other offsets. + Some profiles may choose to provide a privileged mode bit to select between precise and imprecise vector traps. schema: - type: string - enum: ["custom"] + type: boolean MUTABLE_MISA_V: description: | Indicates whether or not the `V` extension can be disabled with the `misa.V` bit.