diff --git a/spec/std/isa/ext/B.yaml b/spec/std/isa/ext/B.yaml index 1bb642ba0..d4ac0700f 100644 --- a/spec/std/isa/ext/B.yaml +++ b/spec/std/isa/ext/B.yaml @@ -7,7 +7,7 @@ $schema: "ext_schema.json#" kind: extension name: B type: unprivileged -long_name: Bitmanipulation instructions +long_name: Bit Manipulation company: name: RISC-V International url: https://riscv.org diff --git a/spec/std/isa/ext/M.yaml b/spec/std/isa/ext/M.yaml index 2791f4a46..f10aa3ff5 100644 --- a/spec/std/isa/ext/M.yaml +++ b/spec/std/isa/ext/M.yaml @@ -7,7 +7,7 @@ $schema: "ext_schema.json#" kind: extension name: M type: unprivileged -long_name: Integer multiply and divide instructions +long_name: Integer multiply and divide versions: - version: "2.0.0" state: ratified diff --git a/spec/std/isa/ext/Sha.yaml b/spec/std/isa/ext/Sha.yaml index 3d6a18811..9cc84408a 100644 --- a/spec/std/isa/ext/Sha.yaml +++ b/spec/std/isa/ext/Sha.yaml @@ -7,7 +7,7 @@ $schema: "ext_schema.json#" kind: extension name: Sha type: privileged -long_name: The augmented hypervisor extension +long_name: Augmented hypervisor description: | *Sha* comprises the following extensions: diff --git a/spec/std/isa/ext/Shgatpa.yaml b/spec/std/isa/ext/Shgatpa.yaml index c7dc68a0e..cfa41eafb 100644 --- a/spec/std/isa/ext/Shgatpa.yaml +++ b/spec/std/isa/ext/Shgatpa.yaml @@ -6,7 +6,7 @@ $schema: "ext_schema.json#" kind: extension name: Shgatpa -long_name: hgtap profile requirements +long_name: SvNNx4 mode supported for all modes supported by Supervisor Address Translation and Protection, as well as Bare description: | For each supported virtual memory scheme SvNN supported in `satp`, the corresponding hgatp SvNNx4 mode must be supported. The diff --git a/spec/std/isa/ext/Shtvala.yaml b/spec/std/isa/ext/Shtvala.yaml index 4adab8834..b0e7a7be1 100644 --- a/spec/std/isa/ext/Shtvala.yaml +++ b/spec/std/isa/ext/Shtvala.yaml @@ -6,7 +6,7 @@ $schema: "ext_schema.json#" kind: extension name: Shtvala -long_name: htval profile requirements +long_name: Hypervisor Trap Value provides all needed values description: | htval must be written with the faulting virtual address for load, store, and instruction page-fault, access-fault, and diff --git a/spec/std/isa/ext/Shvsatpa.yaml b/spec/std/isa/ext/Shvsatpa.yaml index 9c7e428f9..2c1843742 100644 --- a/spec/std/isa/ext/Shvsatpa.yaml +++ b/spec/std/isa/ext/Shvsatpa.yaml @@ -6,7 +6,7 @@ $schema: "ext_schema.json#" kind: extension name: Shvsatpa -long_name: vstap translation mode requirements +long_name: Virtual Supervisor Address Translation and Protection supports all modes supported by Supervisor Address Translation and Protection description: | All translation modes supported in the `satp` CSR must be supported in the `vsatp` CSR. diff --git a/spec/std/isa/ext/Shvstvala.yaml b/spec/std/isa/ext/Shvstvala.yaml index d4b71dc49..ab18af7af 100644 --- a/spec/std/isa/ext/Shvstvala.yaml +++ b/spec/std/isa/ext/Shvstvala.yaml @@ -6,7 +6,7 @@ $schema: "ext_schema.json#" kind: extension name: Shvstvala -long_name: vstval profile requirements +long_name: Virtual Supervisor Trap Value provides all needed values description: | vstval must be written with the faulting virtual address for load, store, and instruction page-fault, access-fault, and diff --git a/spec/std/isa/ext/Shvstvecd.yaml b/spec/std/isa/ext/Shvstvecd.yaml index a60eac9f4..6125e3142 100644 --- a/spec/std/isa/ext/Shvstvecd.yaml +++ b/spec/std/isa/ext/Shvstvecd.yaml @@ -6,7 +6,7 @@ $schema: "ext_schema.json#" kind: extension name: Shvstvecd -long_name: vstvec profile requirements +long_name: Virtual Supervisor Trap Vector Base Address supports Direct mode description: | `vstvec.MODE` must be capable of holding the value 0 (Direct). When `vstvec.MODE`=Direct, `vstvec.BASE` must be capable of holding diff --git a/spec/std/isa/ext/Smcsrind.yaml b/spec/std/isa/ext/Smcsrind.yaml index 35d112dde..86cefa1a5 100644 --- a/spec/std/isa/ext/Smcsrind.yaml +++ b/spec/std/isa/ext/Smcsrind.yaml @@ -7,7 +7,7 @@ $schema: "ext_schema.json#" kind: extension name: Smcsrind type: privileged -long_name: Machine Indirect CSR Access (Smcsrind) +long_name: Machine-mode Indirect CSR Access description: | Smcsrind/Sscsrind is an ISA extension that extends the indirect CSR access mechanism originally defined as part of the Smaia/Ssaia extensions, in order to make it available for use by other extensions without creating diff --git a/spec/std/isa/ext/Smdbltrp.yaml b/spec/std/isa/ext/Smdbltrp.yaml index 00948a307..ebc638869 100644 --- a/spec/std/isa/ext/Smdbltrp.yaml +++ b/spec/std/isa/ext/Smdbltrp.yaml @@ -6,7 +6,7 @@ $schema: "ext_schema.json#" kind: extension name: Smdbltrp -long_name: Double trap +long_name: Double trap in M-mode description: | The `Smdbltrp` extension addresses a double trap in M-mode. When the `Smrnmi` extension is implemented, it enables invocation of the RNMI handler on a diff --git a/spec/std/isa/ext/Sscounterenw.yaml b/spec/std/isa/ext/Sscounterenw.yaml index 8b8c5e73c..a267d721f 100644 --- a/spec/std/isa/ext/Sscounterenw.yaml +++ b/spec/std/isa/ext/Sscounterenw.yaml @@ -6,7 +6,7 @@ $schema: "ext_schema.json#" kind: extension name: Sscounterenw -long_name: Supervisor counter enable +long_name: Support writeable enables for any supported counter description: | For any hpmcounter that is not read-only zero, the corresponding bit in `scounteren` must be writable. diff --git a/spec/std/isa/ext/Sscsrind.yaml b/spec/std/isa/ext/Sscsrind.yaml index 4d40069a1..0705e6165 100644 --- a/spec/std/isa/ext/Sscsrind.yaml +++ b/spec/std/isa/ext/Sscsrind.yaml @@ -7,7 +7,7 @@ $schema: "ext_schema.json#" kind: extension name: Sscsrind type: privileged -long_name: Supervisor Indirect CSR Access (Sscsrind) +long_name: Supervisor-mode Indirect CSR Access description: | Smcsrind/Sscsrind is an ISA extension that extends the indirect CSR access mechanism originally defined as part of the Smaia/Ssaia extensions, in order to make it available for use by other extensions without creating diff --git a/spec/std/isa/ext/Ssstrict.yaml b/spec/std/isa/ext/Ssstrict.yaml index 717c452ff..dd7b55dbd 100644 --- a/spec/std/isa/ext/Ssstrict.yaml +++ b/spec/std/isa/ext/Ssstrict.yaml @@ -6,7 +6,7 @@ $schema: "ext_schema.json#" kind: extension name: Ssstrict -long_name: Unimplemented reserved encodings trap and no no-conforming extensions +long_name: Unimplemented reserved encodings trap and no non-conforming extensions type: privileged description: | No non-conforming extensions are present. Attempts to diff --git a/spec/std/isa/ext/Sstvala.yaml b/spec/std/isa/ext/Sstvala.yaml index cddcd652b..f14968f9c 100644 --- a/spec/std/isa/ext/Sstvala.yaml +++ b/spec/std/isa/ext/Sstvala.yaml @@ -6,7 +6,7 @@ $schema: "ext_schema.json#" kind: extension name: Sstvala -long_name: "`stval` requirements for RVA profiles" +long_name: "Supervisor Trap Value provides all needed values" description: | `stval` must be written with the faulting virtual address for load, store, and instruction page-fault, access-fault, and misaligned exceptions, diff --git a/spec/std/isa/ext/Svnapot.yaml b/spec/std/isa/ext/Svnapot.yaml index c26dd044a..5dba21168 100644 --- a/spec/std/isa/ext/Svnapot.yaml +++ b/spec/std/isa/ext/Svnapot.yaml @@ -6,7 +6,7 @@ $schema: "ext_schema.json#" kind: extension name: Svnapot -long_name: Naturally-aligned Power of Two Translation Contiguity +long_name: Naturally Aligned Power-of-Two Translation Contiguity type: privileged description: | In Sv39, Sv48, and Sv57, when a PTE has N=1, the PTE represents a diff --git a/spec/std/isa/ext/Svvptc.yaml b/spec/std/isa/ext/Svvptc.yaml index a466720af..1805c7cd8 100644 --- a/spec/std/isa/ext/Svvptc.yaml +++ b/spec/std/isa/ext/Svvptc.yaml @@ -6,7 +6,7 @@ $schema: "ext_schema.json#" kind: extension name: Svvptc -long_name: Guarantees visibility of PTE transitions from invalid to valid +long_name: Guarantee visibility of PTE transitions from invalid to valid description: | When the Svvptc extension is implemented, explicit stores by a hart that update the Valid bit of leaf and/or non-leaf PTEs from 0 to 1 and are visible to a hart diff --git a/spec/std/isa/ext/V.yaml b/spec/std/isa/ext/V.yaml index ae1422fa0..1034002a6 100644 --- a/spec/std/isa/ext/V.yaml +++ b/spec/std/isa/ext/V.yaml @@ -7,13 +7,13 @@ $schema: "ext_schema.json#" kind: extension name: V type: unprivileged -long_name: Variable-length vector +long_name: Vector Operations versions: - version: "1.0.0" state: ratified ratification_date: null description: | - TODO + General support for data-parallel execution. params: MUTABLE_MISA_V: description: | diff --git a/spec/std/isa/ext/Za128rs.yaml b/spec/std/isa/ext/Za128rs.yaml index d7a8edbb6..de0eabb2a 100644 --- a/spec/std/isa/ext/Za128rs.yaml +++ b/spec/std/isa/ext/Za128rs.yaml @@ -6,7 +6,7 @@ $schema: "ext_schema.json#" kind: extension name: Za128rs -long_name: Reservation set requirement for RVA profiles +long_name: Reservation set size of at most 128 bytes type: unprivileged description: | Reservation sets must be contiguous, naturally aligned, and at most 128 bytes in size. diff --git a/spec/std/isa/ext/Za64rs.yaml b/spec/std/isa/ext/Za64rs.yaml index abf4f1d42..24764d375 100644 --- a/spec/std/isa/ext/Za64rs.yaml +++ b/spec/std/isa/ext/Za64rs.yaml @@ -6,7 +6,7 @@ $schema: "ext_schema.json#" kind: extension name: Za64rs -long_name: Reservation set requirement for RVA profiles +long_name: Reservation set size of at most 64 bytes type: unprivileged description: | Reservation sets must be contiguous, naturally aligned, and at most 64 bytes in size. diff --git a/spec/std/isa/ext/Zalasr.yaml b/spec/std/isa/ext/Zalasr.yaml index 72b94a2d3..f2b512908 100644 --- a/spec/std/isa/ext/Zalasr.yaml +++ b/spec/std/isa/ext/Zalasr.yaml @@ -6,7 +6,7 @@ $schema: "ext_schema.json#" kind: extension name: Zalasr -long_name: Atomic, Load-Acquire Store-Release +long_name: Atomic Load-Acquire and Store-Release description: | load-acquire and store-release instructions. type: unprivileged diff --git a/spec/std/isa/ext/Zalrsc.yaml b/spec/std/isa/ext/Zalrsc.yaml index ff7267535..25189c6b7 100644 --- a/spec/std/isa/ext/Zalrsc.yaml +++ b/spec/std/isa/ext/Zalrsc.yaml @@ -6,7 +6,7 @@ $schema: "ext_schema.json#" kind: extension name: Zalrsc -long_name: Atomic read-modify-write instructions +long_name: Load-Reserved/Store-Conditional Instructions type: unprivileged versions: - version: "1.0.0" diff --git a/spec/std/isa/ext/Zama16b.yaml b/spec/std/isa/ext/Zama16b.yaml index 9ee7e0b0d..097565858 100644 --- a/spec/std/isa/ext/Zama16b.yaml +++ b/spec/std/isa/ext/Zama16b.yaml @@ -6,7 +6,7 @@ $schema: "ext_schema.json#" kind: extension name: Zama16b -long_name: Misaligned load/store/AMO within aligned 16-byte address are atomic +long_name: Misaligned load/store/AMO within aligned 16-byte boundaries are atomic type: unprivileged description: | Misaligned loads, stores, and AMOs to main memory regions that do not cross a diff --git a/spec/std/isa/ext/Zba.yaml b/spec/std/isa/ext/Zba.yaml index 4489a5cdc..943202f56 100644 --- a/spec/std/isa/ext/Zba.yaml +++ b/spec/std/isa/ext/Zba.yaml @@ -6,7 +6,7 @@ $schema: "ext_schema.json#" kind: extension name: Zba -long_name: Address generation instructions +long_name: Address generation description: | The Zba instructions can be used to accelerate the generation of addresses that index into arrays of basic types (halfword, word, doubleword) using both unsigned word-sized and diff --git a/spec/std/isa/ext/Zbb.yaml b/spec/std/isa/ext/Zbb.yaml index 73e98edbb..8e59e85a2 100644 --- a/spec/std/isa/ext/Zbb.yaml +++ b/spec/std/isa/ext/Zbb.yaml @@ -6,9 +6,9 @@ $schema: "ext_schema.json#" kind: extension name: Zbb -long_name: Basic bit manipulation +long_name: Basic bit-manipulation description: | - Basic bit manipulation + Basic bit-manipulation type: unprivileged company: name: RISC-V International diff --git a/spec/std/isa/ext/Zbc.yaml b/spec/std/isa/ext/Zbc.yaml index 38d2b193b..4944ac1fe 100644 --- a/spec/std/isa/ext/Zbc.yaml +++ b/spec/std/isa/ext/Zbc.yaml @@ -6,7 +6,7 @@ $schema: "ext_schema.json#" kind: extension name: Zbc -long_name: Carry-less multiplication scalar instructions +long_name: Carry-less multiplication description: | Carry-less multiplication is the multiplication in the polynomial ring over GF(2). type: unprivileged diff --git a/spec/std/isa/ext/Zca.yaml b/spec/std/isa/ext/Zca.yaml index ebbd0c332..6471e9ad0 100644 --- a/spec/std/isa/ext/Zca.yaml +++ b/spec/std/isa/ext/Zca.yaml @@ -6,7 +6,7 @@ $schema: "ext_schema.json#" kind: extension name: Zca -long_name: C instructions excluding floating-point +long_name: C instructions excluding floating-point loads/stores description: | The Zca extension is added as way to refer to instructions in the `C` extension that do not include the floating-point loads and stores. diff --git a/spec/std/isa/ext/Zcd.yaml b/spec/std/isa/ext/Zcd.yaml index ebbfa4291..ab3998c66 100644 --- a/spec/std/isa/ext/Zcd.yaml +++ b/spec/std/isa/ext/Zcd.yaml @@ -6,7 +6,7 @@ $schema: "ext_schema.json#" kind: extension name: Zcd -long_name: Compressed instructions for double precision floating point +long_name: Compressed double-precision floating-point loads/stores description: | Zcd is the existing set of compressed double precision floating point loads and stores: `c.fld`, `c.fldsp`, `c.fsd`, `c.fsdsp`. diff --git a/spec/std/isa/ext/Zcf.yaml b/spec/std/isa/ext/Zcf.yaml index 1fa8d0da9..316f36aef 100644 --- a/spec/std/isa/ext/Zcf.yaml +++ b/spec/std/isa/ext/Zcf.yaml @@ -6,7 +6,7 @@ $schema: "ext_schema.json#" kind: extension name: Zcf -long_name: Compressed instructions for single precision floating point +long_name: Compressed single-precision floating-point loads/stores description: | Zcf is the existing set of compressed single precision floating point loads and stores (RV32 only): `c.flw`, `c.flwsp`, `c.fsw`, `c.fswsp`. diff --git a/spec/std/isa/ext/Zcmop.yaml b/spec/std/isa/ext/Zcmop.yaml index 5c0a28f0b..680787148 100644 --- a/spec/std/isa/ext/Zcmop.yaml +++ b/spec/std/isa/ext/Zcmop.yaml @@ -6,7 +6,7 @@ $schema: "ext_schema.json#" kind: extension name: Zcmop -long_name: 16-bit May-be Operations +long_name: Compressed May-Be-Operations description: | The "Zcmop" extension, which defines eight 16-bit MOP instructions named C.MOP.__n__, where __n__ is an odd integer between 1 and diff --git a/spec/std/isa/ext/Zcmp.yaml b/spec/std/isa/ext/Zcmp.yaml index cd1c93912..49dab8459 100644 --- a/spec/std/isa/ext/Zcmp.yaml +++ b/spec/std/isa/ext/Zcmp.yaml @@ -6,7 +6,7 @@ $schema: "ext_schema.json#" kind: extension name: Zcmp -long_name: 16-bit Push/Pop instructions +long_name: Complex PUSH/POP and Double Move description: | The Zcmp extension is a set of instructions which may be executed as a series of existing 32-bit RISC-V instructions. diff --git a/spec/std/isa/ext/Zcmt.yaml b/spec/std/isa/ext/Zcmt.yaml index a9d506065..6a77a97e2 100644 --- a/spec/std/isa/ext/Zcmt.yaml +++ b/spec/std/isa/ext/Zcmt.yaml @@ -6,7 +6,7 @@ $schema: "ext_schema.json#" kind: extension name: Zcmt -long_name: 16-bit Table Jump +long_name: Table Jump description: | Zcmt adds the table jump instructions and also adds the jvt CSR. The jvt CSR requires a state enable if Smstateen is implemented. See <> for details. diff --git a/spec/std/isa/ext/Zfa.yaml b/spec/std/isa/ext/Zfa.yaml index dce9b9c34..911a838b7 100644 --- a/spec/std/isa/ext/Zfa.yaml +++ b/spec/std/isa/ext/Zfa.yaml @@ -6,7 +6,7 @@ $schema: "ext_schema.json#" kind: extension name: Zfa -long_name: Extension for Additional Floating-Point Instructions +long_name: Additional Floating-Point Instructions description: | `Zfa` adds instructions for immediate loads, IEEE 754-2019 minimum and maximum operations, round-to-integer operations, and quiet floating-point comparisons. diff --git a/spec/std/isa/ext/Zfhmin.yaml b/spec/std/isa/ext/Zfhmin.yaml index 60ea0516b..6871aa2e6 100644 --- a/spec/std/isa/ext/Zfhmin.yaml +++ b/spec/std/isa/ext/Zfhmin.yaml @@ -6,7 +6,7 @@ $schema: "ext_schema.json#" kind: extension name: Zfhmin -long_name: Minimal half-precision Floating-point +long_name: Minimal half-precision floating-point description: | `Zfhmin` provides minimal support for 16-bit half-precision binary floating-point diff --git a/spec/std/isa/ext/Zicbom.yaml b/spec/std/isa/ext/Zicbom.yaml index a19d9fabb..721f63bc8 100644 --- a/spec/std/isa/ext/Zicbom.yaml +++ b/spec/std/isa/ext/Zicbom.yaml @@ -6,8 +6,8 @@ $schema: "ext_schema.json#" kind: extension name: Zicbom -long_name: Cache block management instructions -description: Cache block management instructions +long_name: Cache-block management instructions +description: Cache-block management instructions type: unprivileged versions: - version: "1.0.0" diff --git a/spec/std/isa/ext/Zicbop.yaml b/spec/std/isa/ext/Zicbop.yaml index dedeeb514..601eff80f 100644 --- a/spec/std/isa/ext/Zicbop.yaml +++ b/spec/std/isa/ext/Zicbop.yaml @@ -6,8 +6,8 @@ $schema: "ext_schema.json#" kind: extension name: Zicbop -long_name: Cache block prefetch -description: Cache block prefetch instruction +long_name: Cache-block prefetch +description: Cache-block prefetch instructions type: unprivileged versions: - version: "1.0.0" diff --git a/spec/std/isa/ext/Zicboz.yaml b/spec/std/isa/ext/Zicboz.yaml index 0cbeae3ae..13fd925a8 100644 --- a/spec/std/isa/ext/Zicboz.yaml +++ b/spec/std/isa/ext/Zicboz.yaml @@ -6,8 +6,8 @@ $schema: "ext_schema.json#" kind: extension name: Zicboz -long_name: Cache block zero instruction -description: Cache block zero instruction +long_name: Cache-block zero instruction +description: Cache-block zero instruction type: unprivileged versions: - version: "1.0.0" diff --git a/spec/std/isa/ext/Ziccamoa.yaml b/spec/std/isa/ext/Ziccamoa.yaml index 2e777b802..460ad6793 100644 --- a/spec/std/isa/ext/Ziccamoa.yaml +++ b/spec/std/isa/ext/Ziccamoa.yaml @@ -6,7 +6,7 @@ $schema: "ext_schema.json#" kind: extension name: Ziccamoa -long_name: Main memory atomicity requirement for RVA profiles +long_name: Main memory supports all atomics in A extension type: unprivileged description: | Main memory regions with both the cacheability and coherence PMAs must support AMOArithmetic. diff --git a/spec/std/isa/ext/Ziccif.yaml b/spec/std/isa/ext/Ziccif.yaml index cad8e2046..a3be3d168 100644 --- a/spec/std/isa/ext/Ziccif.yaml +++ b/spec/std/isa/ext/Ziccif.yaml @@ -6,7 +6,7 @@ $schema: "ext_schema.json#" kind: extension name: Ziccif -long_name: Main memory fetch requirement for RVA profiles +long_name: Main memory supports instruction fetch with atomicity requirement type: unprivileged description: | Main memory regions with both the cacheability and coherence PMAs must support instruction diff --git a/spec/std/isa/ext/Zicclsm.yaml b/spec/std/isa/ext/Zicclsm.yaml index 8dbce5385..0435d5245 100644 --- a/spec/std/isa/ext/Zicclsm.yaml +++ b/spec/std/isa/ext/Zicclsm.yaml @@ -6,7 +6,7 @@ $schema: "ext_schema.json#" kind: extension name: Zicclsm -long_name: Main memory misaligned requirement for RVA profiles +long_name: "Main memory supports misaligned loads/stores" type: unprivileged description: | Misaligned loads and stores to main memory regions with both the cacheability and coherence diff --git a/spec/std/isa/ext/Ziccrse.yaml b/spec/std/isa/ext/Ziccrse.yaml index 5ff2d2907..e362c2ef5 100644 --- a/spec/std/isa/ext/Ziccrse.yaml +++ b/spec/std/isa/ext/Ziccrse.yaml @@ -6,7 +6,7 @@ $schema: "ext_schema.json#" kind: extension name: Ziccrse -long_name: Main memory reservability requirement for RVA profiles +long_name: Main memory supports forward progress on LR/SC sequences type: unprivileged description: | Main memory regions with both the cacheability and coherence PMAs must support RsrvEventual. diff --git a/spec/std/isa/ext/Zicfilp.yaml b/spec/std/isa/ext/Zicfilp.yaml index 6be6f6d7d..e908a34e1 100644 --- a/spec/std/isa/ext/Zicfilp.yaml +++ b/spec/std/isa/ext/Zicfilp.yaml @@ -6,7 +6,7 @@ $schema: "ext_schema.json#" kind: extension name: Zicfilp -long_name: Landing Pads +long_name: Landing Pad description: | TODO type: unprivileged diff --git a/spec/std/isa/ext/Zicntr.yaml b/spec/std/isa/ext/Zicntr.yaml index 33155f812..bbb024065 100644 --- a/spec/std/isa/ext/Zicntr.yaml +++ b/spec/std/isa/ext/Zicntr.yaml @@ -6,8 +6,10 @@ $schema: "ext_schema.json#" kind: extension name: Zicntr -long_name: Architectural performance counters -description: Architectural performance counters +long_name: Base Counters and Timers +description: | + The CYCLE, TIME, and INSTRET counters, which have dedicated functions + (cycle count, real-time clock, and instructions retired, respectively). type: unprivileged versions: - version: "2.0.0" diff --git a/spec/std/isa/ext/Zicsr.yaml b/spec/std/isa/ext/Zicsr.yaml index 9d375ea32..8620a37e5 100644 --- a/spec/std/isa/ext/Zicsr.yaml +++ b/spec/std/isa/ext/Zicsr.yaml @@ -6,8 +6,8 @@ $schema: "ext_schema.json#" kind: extension name: Zicsr -long_name: Control and status registers -description: Control and status registers +long_name: Control and status register instructions +description: Control and status register instructions type: unprivileged versions: - version: "2.0.0" diff --git a/spec/std/isa/ext/Zihintntl.yaml b/spec/std/isa/ext/Zihintntl.yaml index f350413a1..d2e9143b1 100644 --- a/spec/std/isa/ext/Zihintntl.yaml +++ b/spec/std/isa/ext/Zihintntl.yaml @@ -6,7 +6,7 @@ $schema: "ext_schema.json#" kind: extension name: Zihintntl -long_name: NTL Non-Temporal Locality Hint Instructions +long_name: Non-Temporal Locality Hints description: | The NTL instructions are HINTs that indicate that the explicit memory accesses of the immediately subsequent instruction (henceforth "target diff --git a/spec/std/isa/ext/Zihintpause.yaml b/spec/std/isa/ext/Zihintpause.yaml index df87e9193..af6a282a6 100644 --- a/spec/std/isa/ext/Zihintpause.yaml +++ b/spec/std/isa/ext/Zihintpause.yaml @@ -6,7 +6,7 @@ $schema: "ext_schema.json#" kind: extension name: Zihintpause -long_name: PAUSE instruction +long_name: Pause Hint description: | The PAUSE instruction is a HINT that indicates the current hart's rate of instruction retirement should be temporarily reduced or paused. The diff --git a/spec/std/isa/ext/Zihpm.yaml b/spec/std/isa/ext/Zihpm.yaml index 06c1db12d..b193a89b7 100644 --- a/spec/std/isa/ext/Zihpm.yaml +++ b/spec/std/isa/ext/Zihpm.yaml @@ -6,8 +6,8 @@ $schema: "ext_schema.json#" kind: extension name: Zihpm -long_name: Programmable hardware performance counters -description: Programmable hardware performance counters +long_name: Hardware Performance Counters +description: Hardware performance counters type: unprivileged versions: - version: "2.0.0" diff --git a/spec/std/isa/ext/Zimop.yaml b/spec/std/isa/ext/Zimop.yaml index 25a0fe252..33a88469c 100644 --- a/spec/std/isa/ext/Zimop.yaml +++ b/spec/std/isa/ext/Zimop.yaml @@ -6,7 +6,7 @@ $schema: "ext_schema.json#" kind: extension name: Zimop -long_name: May-be Operations +long_name: May-Be-Operations description: | The "Zimop" extension introduces the concept of instructions that _may be operations_ (MOPs). MOPs are initially defined to diff --git a/spec/std/isa/ext/Zknh.yaml b/spec/std/isa/ext/Zknh.yaml index 709f91486..0c2102dbe 100644 --- a/spec/std/isa/ext/Zknh.yaml +++ b/spec/std/isa/ext/Zknh.yaml @@ -6,7 +6,7 @@ $schema: "ext_schema.json#" kind: extension name: Zknh -long_name: "NIST Suite: Hash Function Instructions" +long_name: "NIST Suite: SHA2 Hashing" description: | Instructions for accelerating the SHA2 family of cryptographic hash functions. type: unprivileged diff --git a/spec/std/isa/ext/Zmmul.yaml b/spec/std/isa/ext/Zmmul.yaml index 2b1b3a068..ffb9f8ad0 100644 --- a/spec/std/isa/ext/Zmmul.yaml +++ b/spec/std/isa/ext/Zmmul.yaml @@ -6,7 +6,7 @@ $schema: "ext_schema.json#" kind: extension name: Zmmul -long_name: Integer multiplication instructions +long_name: Integer multiplication description: | The `Zmmul` extension implements the multiplication subset of the `M` extension. It adds `MUL`, `MULH`, `MULHU`, `MULHSU`, and (for RV64 only) `MULW`.