From d335aae7b54fb4cc5ba72f01044f2af0d313c1b0 Mon Sep 17 00:00:00 2001 From: Derek Hower Date: Mon, 4 Nov 2024 10:54:04 -0800 Subject: [PATCH 1/5] Add render() to TemplateHelpers --- lib/template_helpers.rb | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/lib/template_helpers.rb b/lib/template_helpers.rb index 7ae4e8930d..be11d0deed 100644 --- a/lib/template_helpers.rb +++ b/lib/template_helpers.rb @@ -1,6 +1,12 @@ +# frozen_string_literal: true + # At this point, we insert a placeholder since it will be up # to the backend to create a specific link. +require "erb" +require "pathname" + +# collection of functions that can be used inside ERB templates module TemplateHelpers # Insert a hyperlink to an extension. # @param name [#to_s] Name of the extension @@ -65,4 +71,12 @@ def anchor_for_csr(name) def anchor_for_csr_field(csr_name, field_name) "[[csr_field-#{csr_name.gsub(".", "_")}-#{field_name.gsub(".", "_")}-def]]" end -end \ No newline at end of file + + def render(template_path, locals = {}) + template_path = Pathname.new(template_path) + erb = ERB.new(template) + erb.filename = template_path.realpath + + erb.result(OpenStruct.new(locals).instance_eval { binding }) + end +end From f46651e73737f4c143bd5ee054b22846b74f8689 Mon Sep 17 00:00:00 2001 From: James Ball Date: Fri, 8 Nov 2024 11:31:42 -0800 Subject: [PATCH 2/5] Using $mref to inherit from RVI20 to RVA20 to RVA22 and from the mock profile into the mock certificate. --- Rakefile | 53 ++- arch/certificate_model/MC100.yaml | 104 ++-- .../MockCertificateModel.yaml | 278 +++++------ arch/profile_release/MockProfileRelease.yaml | 108 +++-- arch/profile_release/RVA20.yaml | 345 ++++++-------- arch/profile_release/RVA22.yaml | 450 +++++++++--------- arch/profile_release/RVI20.yaml | 202 +++----- .../templates/certificate.adoc.erb | 4 +- backends/profile_doc/tasks.rake | 2 +- lib/arch_def.rb | 3 +- lib/arch_obj_models/portfolio.rb | 64 +-- lib/arch_obj_models/profile.rb | 2 - lib/yaml_loader.rb | 16 +- 13 files changed, 793 insertions(+), 838 deletions(-) diff --git a/Rakefile b/Rakefile index 0aad8141b7..0b2a9f9a58 100644 --- a/Rakefile +++ b/Rakefile @@ -287,13 +287,54 @@ task :regress do ENV["VERSIONS"] = "all" Rake::Task["gen:html_manual"].invoke Rake::Task["gen:html"].invoke("generic_rv64") - Rake::Task["gen:cert_model_pdf"].invoke("MockCertificateModel") - Rake::Task["gen:cert_model_pdf"].invoke("MC100") - Rake::Task["gen:profile"].invoke("MockProfileRelease") - Rake::Task["gen:profile"].invoke("RVA20") - Rake::Task["gen:profile"].invoke("RVA22") - Rake::Task["gen:profile"].invoke("RVI20") + Rake::Task["#{$root}/gen/certificate_doc/pdf/MockCertificateModel.pdf"].invoke + Rake::Task["#{$root}/gen/certificate_doc/pdf/MC100.pdf"].invoke + Rake::Task["#{$root}/gen/profile_doc/pdf/MockProfileRelease.pdf"].invoke + Rake::Task["#{$root}/gen/profile_doc/pdf/RVA20.pdf"].invoke + Rake::Task["#{$root}/gen/profile_doc/pdf/RVA22.pdf"].invoke + Rake::Task["#{$root}/gen/profile_doc/pdf/RVI20.pdf"].invoke puts puts "Regression test PASSED" end + +desc <<~DESC + Generate all certificates and profile PDFs. +DESC +task :cert_profile_pdfs do + puts "===================================" + puts "cert_profile_pdfs: Generating MC100" + puts " 1st target" + puts "===================================" + Rake::Task["#{$root}/gen/certificate_doc/pdf/MC100.pdf"].invoke + + puts "==================================================" + puts "cert_profile_pdfs: Generating MockCertificateModel" + puts " 2nd target" + puts "==================================================" + Rake::Task["#{$root}/gen/certificate_doc/pdf/MockCertificateModel.pdf"].invoke + + puts "===================================" + puts "cert_profile_pdfs: Generating RVA20" + puts " 3rd target" + puts "===================================" + Rake::Task["#{$root}/gen/profile_doc/pdf/RVA20.pdf"].invoke + + puts "===================================" + puts "cert_profile_pdfs: Generating RVA22" + puts " 4th target" + puts "===================================" + Rake::Task["#{$root}/gen/profile_doc/pdf/RVA22.pdf"].invoke + + puts "===================================" + puts "cert_profile_pdfs: Generating RVI20" + puts " 5th target" + puts "===================================" + Rake::Task["#{$root}/gen/profile_doc/pdf/RVI20.pdf"].invoke + + puts "===================================" + puts "cert_profile_pdfs: Generating MockProfileRelease" + puts " 6th target" + puts "===================================" + Rake::Task["#{$root}/gen/profile_doc/pdf/MockProfileRelease.pdf"].invoke +end \ No newline at end of file diff --git a/arch/certificate_model/MC100.yaml b/arch/certificate_model/MC100.yaml index f92f61e6cf..48a4ecf405 100644 --- a/arch/certificate_model/MC100.yaml +++ b/arch/certificate_model/MC100.yaml @@ -87,55 +87,55 @@ MC100: # XXX - Remove version information since specifying priv/unpriv ISA manual should imply this. extensions: - - name: I - version: "~> 2.1" - presence: mandatory - - name: C - version: "~> 2.2" - presence: mandatory - - name: M - version: "~> 2.0" - presence: mandatory - - name: Zicsr - version: "~> 2.0" - presence: mandatory - - name: Zicntr - version: "~> 2.0" - presence: mandatory - parameters: - TIME_CSR_IMPLEMENTED: {} # Unconstrained - - name: Sm - version: "~> 1.11.0" - presence: mandatory - parameters: - MTVEC_BASE_ALIGNMENT_DIRECT: {} # Unconstrained - MTVEC_BASE_ALIGNMENT_VECTORED: {} # Unconstrained - ARCH_ID: {} # Unconstrained - IMP_ID: {} # Unconstrained - VENDOR_ID_BANK: {} # Unconstrained - VENDOR_ID_OFFSET: {} # Unconstrained - MISA_CSR_IMPLEMENTED: {} # Unconstrained - MTVAL_WIDTH: {} # Unconstrained - MTVEC_MODES: {} # Unconstrained - PHYS_ADDR_WIDTH: {} # Unconstrained - MISALIGNED_LDST: {} # Unconstrained - MISALIGNED_LDST_EXCEPTION_PRIORITY : {} # Unconstrained - MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE: {} # Unconstrained - MISALIGNED_SPLIT_STRATEGY: - schema: - const: by_byte - PRECISE_SYNCHRONOUS_EXCEPTIONS: - schema: - const: true - TRAP_ON_ECALL_FROM_M: - schema: - const: true - TRAP_ON_EBREAK: - schema: - const: true - M_MODE_ENDIANESS: - schema: - const: little - XLEN: - schema: - const: 32 \ No newline at end of file + I: + version: "~> 2.1" + presence: mandatory + C: + version: "~> 2.2" + presence: mandatory + M: + version: "~> 2.0" + presence: mandatory + Zicsr: + version: "~> 2.0" + presence: mandatory + Zicntr: + version: "~> 2.0" + presence: mandatory + parameters: + TIME_CSR_IMPLEMENTED: {} # Unconstrained + Sm: + version: "~> 1.11.0" + presence: mandatory + parameters: + MTVEC_BASE_ALIGNMENT_DIRECT: {} # Unconstrained + MTVEC_BASE_ALIGNMENT_VECTORED: {} # Unconstrained + ARCH_ID: {} # Unconstrained + IMP_ID: {} # Unconstrained + VENDOR_ID_BANK: {} # Unconstrained + VENDOR_ID_OFFSET: {} # Unconstrained + MISA_CSR_IMPLEMENTED: {} # Unconstrained + MTVAL_WIDTH: {} # Unconstrained + MTVEC_MODES: {} # Unconstrained + PHYS_ADDR_WIDTH: {} # Unconstrained + MISALIGNED_LDST: {} # Unconstrained + MISALIGNED_LDST_EXCEPTION_PRIORITY : {} # Unconstrained + MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE: {} # Unconstrained + MISALIGNED_SPLIT_STRATEGY: + schema: + const: by_byte + PRECISE_SYNCHRONOUS_EXCEPTIONS: + schema: + const: true + TRAP_ON_ECALL_FROM_M: + schema: + const: true + TRAP_ON_EBREAK: + schema: + const: true + M_MODE_ENDIANESS: + schema: + const: little + XLEN: + schema: + const: 32 \ No newline at end of file diff --git a/arch/certificate_model/MockCertificateModel.yaml b/arch/certificate_model/MockCertificateModel.yaml index dc421c5426..d1eab989fb 100644 --- a/arch/certificate_model/MockCertificateModel.yaml +++ b/arch/certificate_model/MockCertificateModel.yaml @@ -38,151 +38,151 @@ MockCertificateModel: # XXX - Remove version information since specifying priv/unpriv ISA manual should imply this. extensions: - - name: MockExt - presence: mandatory - parameters: - MOCK_ENUM_2_INTS: {} - MOCK_ENUM_2_STRINGS: {} - MOCK_BOOL_1: {} - MOCK_BOOL_2: - schema: - const: true - MOCK_1_BIT_INT: {} - MOCK_2_BIT_INT: {} - MOCK_25_BIT_INT: {} - MOCK_32_BIT_INT: - schema: - const: 0xdeadbeef - MOCK_64_BIT_INT: {} - MOCK_INT_RANGE_0_TO_127: {} - MOCK_INT_RANGE_0_TO_128: {} - MOCK_INT_RANGE_1_TO_128: {} - MOCK_INT_RANGE_0_TO_999: {} - MOCK_INT_RANGE_0_TO_1023: {} - MOCK_INT_RANGE_1000_TO_2048: {} - MOCK_ARRAY_INT_ENUM: {} - MOCK_ARRAY_BOOL_ARRAY_OF_8_FIRST_2_FALSE: {} - MOCK_ARRAY_STRING_ENUM1: - schema: - const : DEF - MOCK_ARRAY_STRING_ENUM2: - schema: - contains: { const : DEF } - - name: I - version: "~> 2.1" - presence: mandatory - note: Here's a note for the I extension. - - name: C - version: "~> 2.2" - presence: mandatory - parameters: - MUTABLE_MISA_C: - schema: - const: false - note: | - Here's a multi-line note + - for the C extension. - - name: M - presence: mandatory - version: "~> 2.0" - - name: Zicsr - version: "~> 2.0" - presence: mandatory - - name: Zicntr - version: "~> 2.0" - presence: mandatory - parameters: - TIME_CSR_IMPLEMENTED: {} # Unconstrained - - name: Sm - version: "~> 1.11" - presence: mandatory - parameters: - MTVEC_BASE_ALIGNMENT_DIRECT: {} # Unconstrained - MTVEC_BASE_ALIGNMENT_VECTORED: {} # Unconstrained - ARCH_ID: {} # Unconstrained - IMP_ID: {} # Unconstrained - VENDOR_ID_BANK: {} # Unconstrained - VENDOR_ID_OFFSET: {} # Unconstrained - MISA_CSR_IMPLEMENTED: {} # Unconstrained - MTVAL_WIDTH: {} # Unconstrained - MTVEC_MODES: - note: Here's a note for MTVEC_MODES parameter. - schema: - contains: { const : 0 } - PHYS_ADDR_WIDTH: {} # Unconstrained - PRECISE_SYNCHRONOUS_EXCEPTIONS: - schema: - const: true - TRAP_ON_ECALL_FROM_M: - schema: - const: true - TRAP_ON_EBREAK: - schema: - const: true - REPORT_VA_IN_MTVAL_ON_BREAKPOINT: - schema: - const: true - REPORT_VA_IN_MTVAL_ON_INSTRUCTION_ACCESS_FAULT: - schema: - const: true - REPORT_VA_IN_MTVAL_ON_LOAD_ACCESS_FAULT: - schema: - const: true - REPORT_VA_IN_MTVAL_ON_STORE_AMO_ACCESS_FAULT: + $mref: + - "../profile_release/MockProfileRelease.yaml#/MockProfileRelease/profiles/MP-U-64/extensions" + - "../profile_release/MockProfileRelease.yaml#/MockProfileRelease/profiles/MP-S-64/extensions" + I: + presence: optional + version: "=2.1.0" + note: Changed inherited I extension from mandatory to optional and version is =2.1.0 instead of ~>2.1 + MockExt: + presence: mandatory + parameters: + MOCK_ENUM_2_INTS: {} + MOCK_ENUM_2_STRINGS: {} + MOCK_BOOL_1: {} + MOCK_BOOL_2: schema: const: true - REPORT_ENCODING_IN_MTVAL_ON_ILLEGAL_INSTRUCTION: - schema: - const: true - M_MODE_ENDIANESS: - schema: - const: little - # XXX Uncomment when GitHub issue #XXX is fixed. - #schema: - #- when: - # version: "=1.0.0" - # then: - # const: little - #- when: - # version: "=1.1.0" - # then: - # enum: [little, big] - XLEN: - schema: - const: 64 - CONFIG_PTR_ADDRESS: + MOCK_1_BIT_INT: {} + MOCK_2_BIT_INT: {} + MOCK_25_BIT_INT: {} + MOCK_32_BIT_INT: schema: const: 0xdeadbeef - note: "This parameter and its associated CSR shouldn't be here. See GitHub issue #53." - - name: Zifencei - presence: optional - note: "Here's a note for Zifencei" - - name: Zicbop - presence: optional - note: "Testing CACHE_BLOCK_SIZE parameter which is also defined by Zicbom." - parameters: - CACHE_BLOCK_SIZE: + MOCK_64_BIT_INT: {} + MOCK_INT_RANGE_0_TO_127: {} + MOCK_INT_RANGE_0_TO_128: {} + MOCK_INT_RANGE_1_TO_128: {} + MOCK_INT_RANGE_0_TO_999: {} + MOCK_INT_RANGE_0_TO_1023: {} + MOCK_INT_RANGE_1000_TO_2048: {} + MOCK_ARRAY_INT_ENUM: {} + MOCK_ARRAY_BOOL_ARRAY_OF_8_FIRST_2_FALSE: {} + MOCK_ARRAY_STRING_ENUM1: schema: - const: 64 - - name: Zicbom - presence: optional - note: "Testing CACHE_BLOCK_SIZE parameter which is also defined by Zicbop." - parameters: - CACHE_BLOCK_SIZE: + const : DEF + MOCK_ARRAY_STRING_ENUM2: schema: - const: 64 - - name: Zba - presence: mandatory - version: "~> 1.0" - note: "Added these as mandatory to see if bug in profiles not listing instructions in appendix is here in CRD too." - - name: Zbb - presence: mandatory - version: "~> 1.0" - note: "Added these as mandatory to see if bug in profiles not listing instructions in appendix is here in CRD too." - - name: Zbs - presence: mandatory - version: "~> 1.0" - note: "Added these as mandatory to see if bug in profiles not listing instructions in appendix is here in CRD too." + contains: { const : DEF } + C: + version: "~> 2.2" + presence: mandatory + parameters: + MUTABLE_MISA_C: + schema: + const: false + note: | + Here's a multi-line note + + for the C extension. + Zicsr: + version: "~> 2.0" + presence: mandatory + Zicntr: + version: "~> 2.0" + presence: mandatory + parameters: + TIME_CSR_IMPLEMENTED: {} # Unconstrained + Sm: + version: "~> 1.11" + presence: mandatory + parameters: + MTVEC_BASE_ALIGNMENT_DIRECT: {} # Unconstrained + MTVEC_BASE_ALIGNMENT_VECTORED: {} # Unconstrained + ARCH_ID: {} # Unconstrained + IMP_ID: {} # Unconstrained + VENDOR_ID_BANK: {} # Unconstrained + VENDOR_ID_OFFSET: {} # Unconstrained + MISA_CSR_IMPLEMENTED: {} # Unconstrained + MTVAL_WIDTH: {} # Unconstrained + MTVEC_MODES: + note: Here's a note for MTVEC_MODES parameter. + schema: + contains: { const : 0 } + PHYS_ADDR_WIDTH: {} # Unconstrained + PRECISE_SYNCHRONOUS_EXCEPTIONS: + schema: + const: true + TRAP_ON_ECALL_FROM_M: + schema: + const: true + TRAP_ON_EBREAK: + schema: + const: true + REPORT_VA_IN_MTVAL_ON_BREAKPOINT: + schema: + const: true + REPORT_VA_IN_MTVAL_ON_INSTRUCTION_ACCESS_FAULT: + schema: + const: true + REPORT_VA_IN_MTVAL_ON_LOAD_ACCESS_FAULT: + schema: + const: true + REPORT_VA_IN_MTVAL_ON_STORE_AMO_ACCESS_FAULT: + schema: + const: true + REPORT_ENCODING_IN_MTVAL_ON_ILLEGAL_INSTRUCTION: + schema: + const: true + M_MODE_ENDIANESS: + schema: + const: little + # XXX Uncomment when GitHub issue #XXX is fixed. + #schema: + #- when: + # version: "=1.0.0" + # then: + # const: little + #- when: + # version: "=1.1.0" + # then: + # enum: [little, big] + XLEN: + schema: + const: 64 + CONFIG_PTR_ADDRESS: + schema: + const: 0xdeadbeef + note: "This parameter and its associated CSR shouldn't be here. See GitHub issue #53." + Zifencei: + presence: optional + note: "Here's a note for Zifencei" + Zicbop: + presence: optional + note: "Testing CACHE_BLOCK_SIZE parameter which is also defined by Zicbom." + parameters: + CACHE_BLOCK_SIZE: + schema: + const: 64 + Zicbom: + presence: optional + note: "Testing CACHE_BLOCK_SIZE parameter which is also defined by Zicbop." + parameters: + CACHE_BLOCK_SIZE: + schema: + const: 64 + Zba: + presence: mandatory + version: "~> 1.0" + note: "Added these as mandatory to see if bug in profiles not listing instructions in appendix is here in CRD too." + Zbb: + presence: mandatory + version: "~> 1.0" + note: "Added these as mandatory to see if bug in profiles not listing instructions in appendix is here in CRD too." + Zbs: + presence: mandatory + version: "~> 1.0" + note: "Added these as mandatory to see if bug in profiles not listing instructions in appendix is here in CRD too." requirement_groups: - name: Req-Grp-Any-XLEN diff --git a/arch/profile_release/MockProfileRelease.yaml b/arch/profile_release/MockProfileRelease.yaml index 21bbd9e1e5..0b1ed4d5f9 100644 --- a/arch/profile_release/MockProfileRelease.yaml +++ b/arch/profile_release/MockProfileRelease.yaml @@ -19,54 +19,60 @@ MockProfileRelease: email: jane.doe@gmail.com company: Universal Imports profiles: - - name: MockProfileUnpriv - marketing_name: MPUnpriv64 - mode: Unpriv - base: 64 - release: MockProfileRelease - extensions: - - name: I - presence: mandatory - version: "~> 2.1" - - name: MockProfileSuper - marketing_name: MPS64 - description: This is the Mock Profile Supervisor Mode description. - mode: S - base: 64 - release: MockProfileRelease - contributors: - - name: Micky Mouse - email: micky@disney.com - company: Disneyk - extensions: - - name: S - presence: mandatory - version: "= 1.11" - - name: Zifencei - presence: mandatory - version: "= 2.0" - note: | - Zifencei is mandated as it is the only standard way to support - instruction-cache coherence in RVA20 application processors. A new - instruction-cache coherence mechanism is under development which might - be added as an option in the future. - - name: Zihpm - presence: optional - version: "= 2.0" - - name: Sv48 - presence: optional - version: "= 1.11" - extra_notes: - - presence: optional - text: Here's the first extra note for the optional extensions section. - - presence: mandatory - text: | - Here's the first extra note for the mandatory extensions section. - This note is multiple lines. - - presence: optional - text: Here's the second extra note for the optional extensions section. - recommendations: - - text: | - Implementations are strongly recommended to raise illegal-instruction - exceptions on attempts to execute unimplemented opcodes. - - text: Micky should give Pluto an extra treat \ No newline at end of file + MP-U-64: + marketing_name: MockProfile 64-bit Unpriv + mode: Unpriv + base: 64 + release: MockProfileRelease + extensions: + A: + presence: optional + version: "= 2.1" + I: + presence: mandatory + version: "~> 2.1" + MP-S-64: + marketing_name: MockProfile 64-bit S-mode + description: This is the Mock Profile Supervisor Mode description. + mode: S + base: 64 + release: MockProfileRelease + contributors: + - name: Micky Mouse + email: micky@disney.com + company: Disney + extensions: + $mref: "#/MockProfileRelease/profiles/MP-U-64/extensions" + A: + presence: mandatory + S: + presence: mandatory + version: "= 1.11" + Zifencei: + presence: mandatory + version: "= 2.0" + note: | + Zifencei is mandated as it is the only standard way to support + instruction-cache coherence in RVA20 application processors. A new + instruction-cache coherence mechanism is under development which might + be added as an option in the future. + Zihpm: + presence: optional + version: "= 2.0" + Sv48: + presence: optional + version: "= 1.11" + extra_notes: + - presence: optional + text: Here's the first extra note for the optional extensions section. + - presence: mandatory + text: | + Here's the first extra note for the mandatory extensions section. + This note is multiple lines. + - presence: optional + text: Here's the second extra note for the optional extensions section. + recommendations: + - text: | + Implementations are strongly recommended to raise illegal-instruction + exceptions on attempts to execute unimplemented opcodes. + - text: Micky should give Pluto an extra treat \ No newline at end of file diff --git a/arch/profile_release/RVA20.yaml b/arch/profile_release/RVA20.yaml index 5bf1c063f2..0abdd9f7bd 100644 --- a/arch/profile_release/RVA20.yaml +++ b/arch/profile_release/RVA20.yaml @@ -32,190 +32,161 @@ RVA20: email: krste@sifive.com company: SiFive profiles: - - name: RVA20U64 - marketing_name: RVA20U64 - mode: Unpriv - base: 64 - release: RVA20 - introduction: | - The RVA20U64 profile specifies the ISA features available to user-mode - execution environments in 64-bit applications processors. This is the - most important profile within application processors in - terms of the amount of software that targets this profile. - extensions: - - name: I - presence: mandatory - version: "~> 2.1" - note: | - RVI is the mandatory base ISA for RVA, and is little-endian. - - As per the unprivileged architecture specification, the `ecall` - instruction causes a requested trap to the execution environment. - - The `fence.tso` instruction is mandatory. - - NOTE: The `fence.tso` instruction was incorrectly described as - optional in the 2019 ratified specifications. However, `fence.tso` is - encoded within the standard `fence` encoding such that implementations - must treat it as a simple global fence if they do not natively support - TSO-ordering optimizations. As software can always assume without any - penalty that `fence.tso` is being exploited by a hardware - implementation, there is no advantage to making the instruction a - profile option. Later versions of the unprivileged ISA - specifications correctly indicate that `fence.tso` is mandatory. - - name: A - presence: mandatory - version: "= 2.1" - - name: C - presence: mandatory - version: "= 2.2" - - name: D - presence: mandatory - version: "= 2.2" - - name: F - presence: mandatory - version: "= 2.2" - - name: M - presence: mandatory - version: "= 2.0" - - name: U - presence: mandatory - version: "~> 2.0" - param_constraints: - U_MODE_ENDIANESS: - schema: - const: little - - name: Zicntr - presence: mandatory - version: " = 2.0" - - name: Ziccif - presence: mandatory - version: "= 1.0" - note: | - Ziccif is a new extension name introduced with RVA20. - The fetch atomicity requirement facilitates runtime patching - of aligned instructions. - - name: Ziccrse - presence: mandatory - version: "= 1.0" - note: | - Ziccrse is a new extension name introduced with RVA20. - - name: Ziccamoa - presence: mandatory - version: "= 1.0" - note: | - Ziccamo is a new extension name introduced with RVA20. - - name: Za128rs - presence: mandatory - version: "= 1.0" - note: | - Za128rs is a new extension name introduced with RVA20. - The minimum reservation set size is effectively determined by the - size of atomic accesses in the `A` extension. - - name: Zicclsm - presence: mandatory - version: "= 1.0" - note: | - Zicclsm is a new extension name introduced with RVA20. - This requires misaligned support for all regular load and store - instructions (including scalar and vector) but not AMOs or other - specialized forms of memory access. Even though mandated, misaligned - loads and stores might execute extremely slowly. Standard software - distributions should assume their existence only for correctness, not - for performance. - - name: Zihpm - presence: optional - version: "= 2.0" - note: | - The number of counters is platform-specific. - extra_notes: - - presence: optional - text: | - The rationale to not make Q an optional extension is that - quad-precision floating-point is unlikely to be implemented in - hardware, and so we do not require or expect A-profile software to - expend effort optimizing use of Q instructions in case they are - present. - - presence: optional - text: | - Zifencei is not classed as a supported option in the user-mode - profile because it is not sufficient by itself to produce the desired - effect in a multiprogrammed multiprocessor environment without OS - support, and so the instruction cache flush should always be performed - using an OS call rather than using the `fence.i` instruction. - `fence.i` semantics can be expensive to implement for some hardware - memory hierarchy designs, and so alternative non-standard - instruction-cache coherence mechanisms can be used behind the OS - abstraction. A separate extension is being developed for more general - and efficient instruction cache coherence. - - presence: optional - text: | - The execution environment must provide a means to synchronize writes to - instruction memory with instruction fetches, the implementation of which - likely relies on the Zifencei extension. - For example, RISC-V Linux supplies the `__riscv_flush_icache` system call and - a corresponding vDSO call. - recommendations: - - text: | - Implementations are strongly recommended to raise illegal-instruction - exceptions on attempts to execute unimplemented opcodes. - - name: RVA20S64 - marketing_name: RVA20S64 - mode: S - base: 64 - release: RVA20 - introduction: | - The RVA20S64 profile specifies the ISA features available to a - supervisor-mode execution environment in 64-bit applications - processors. RVA20S64 is based on privileged architecture version 1.11. - extensions: - - name: S - presence: mandatory - version: "= 1.11" - - name: Zifencei - presence: mandatory - version: "= 2.0" - note: | - Zifencei is mandated as it is the only standard way to support - instruction-cache coherence in RVA20 application processors. A new - instruction-cache coherence mechanism is under development which might - be added as an option in the future. - - name: Svbare - presence: mandatory - version: "= 1.0" - note: | - Svbare is a new extension name introduced with RVA20. - - name: Sv39 - presence: mandatory - version: "= 1.11" - - name: Svade - presence: mandatory - version: "~> 1.0" - note: | - Svbare is a new extension name introduced with RVA20. - - It is subsequently defined in more detail with the ratification of - `Svadu`. - - name: Ssccptr - presence: mandatory - version: "= 1.0" - note: | - Ssccptr is a new extension name introduced with RVA20. - - name: Sstvecd - presence: mandatory - version: "= 1.0" - note: | - Sstvecd is a new extension name introduced with RVA20. - - name: Sstvala - presence: mandatory - version: "= 1.0" - note: | - Sstvala is a new extension name introduced with RVA20. - - name: Sv48 - presence: optional - version: "= 1.11" - - name: Ssu64xl - presence: optional - version: "= 1.0" - note: | - Ssu64xl is a new extension name introduced with RVA20. \ No newline at end of file + RVA20U64: + marketing_name: RVA20U64 + mode: Unpriv + base: 64 + release: RVA20 + introduction: | + The RVA20U64 profile specifies the ISA features available to user-mode + execution environments in 64-bit applications processors. This is the + most important profile within application processors in + terms of the amount of software that targets this profile. + extensions: + $mref: "RVI20.yaml#/RVI20/profiles/RVI20U64/extensions" + A: + presence: mandatory + C: + presence: mandatory + D: + presence: mandatory + F: + presence: mandatory + M: + presence: mandatory + U: + presence: mandatory + version: "~> 2.0" + param_constraints: + U_MODE_ENDIANESS: + schema: + const: little + Zicntr: + presence: mandatory + #Zifencei: + # How do we remove Zifencei as an option since it is included in the RVI64 profile + # presence: XXX + Ziccif: + presence: mandatory + version: "= 1.0" + note: | + Ziccif is a profile-defined extension introduced with RVA20. + The fetch atomicity requirement facilitates runtime patching + of aligned instructions. + Ziccrse: + presence: mandatory + version: "= 1.0" + note: Ziccrse is a profile-defined extension introduced with RVA20. + Ziccamoa: + presence: mandatory + version: "= 1.0" + note: Ziccamo is a profile-defined extension introduced with RVA20. + Za128rs: + presence: mandatory + version: "= 1.0" + note: | + Za128rs is a profile-defined extension introduced with RVA20. + The minimum reservation set size is effectively determined by the + size of atomic accesses in the `A` extension. + Zicclsm: + presence: mandatory + version: "= 1.0" + note: | + Zicclsm is a profile-defined extension introduced with RVA20. + This requires misaligned support for all regular load and store + instructions (including scalar and vector) but not AMOs or other + specialized forms of memory access. Even though mandated, misaligned + loads and stores might execute extremely slowly. Standard software + distributions should assume their existence only for correctness, not + for performance. + extra_notes: + - presence: optional + text: | + The rationale to not make Q an optional extension is that + quad-precision floating-point is unlikely to be implemented in + hardware, and so we do not require or expect A-profile software to + expend effort optimizing use of Q instructions in case they are + present. + - presence: optional + text: | + Zifencei is not classed as a supported option in the user-mode + profile because it is not sufficient by itself to produce the desired + effect in a multiprogrammed multiprocessor environment without OS + support, and so the instruction cache flush should always be performed + using an OS call rather than using the `fence.i` instruction. + `fence.i` semantics can be expensive to implement for some hardware + memory hierarchy designs, and so alternative non-standard + instruction-cache coherence mechanisms can be used behind the OS + abstraction. A separate extension is being developed for more general + and efficient instruction cache coherence. + - presence: optional + text: | + The execution environment must provide a means to synchronize writes to + instruction memory with instruction fetches, the implementation of which + likely relies on the Zifencei extension. + For example, RISC-V Linux supplies the `__riscv_flush_icache` system call and + a corresponding vDSO call. + recommendations: + - text: | + Implementations are strongly recommended to raise illegal-instruction + exceptions on attempts to execute unimplemented opcodes. + RVA20S64: + marketing_name: RVA20S64 + mode: S + base: 64 + release: RVA20 + introduction: | + The RVA20S64 profile specifies the ISA features available to a + supervisor-mode execution environment in 64-bit applications + processors. RVA20S64 is based on privileged architecture version 1.11. + extensions: + S: + presence: mandatory + version: "= 1.11" + Zifencei: + presence: mandatory + version: "= 2.0" + note: | + Zifencei is mandated as it is the only standard way to support + instruction-cache coherence in RVA20 application processors. A new + instruction-cache coherence mechanism is under development which might + be added as an option in the future. + Svbare: + presence: mandatory + version: "= 1.0" + note: | + Svbare is a new extension name introduced with RVA20. + Sv39: + presence: mandatory + version: "= 1.11" + Svade: + presence: mandatory + version: "~> 1.0" + note: | + Svbare is a new extension name introduced with RVA20. + + It is subsequently defined in more detail with the ratification of + `Svadu`. + Ssccptr: + presence: mandatory + version: "= 1.0" + note: | + Ssccptr is a new extension name introduced with RVA20. + Sstvecd: + presence: mandatory + version: "= 1.0" + note: | + Sstvecd is a new extension name introduced with RVA20. + Sstvala: + presence: mandatory + version: "= 1.0" + note: | + Sstvala is a new extension name introduced with RVA20. + Sv48: + presence: optional + version: "= 1.11" + Ssu64xl: + presence: optional + version: "= 1.0" + note: | + Ssu64xl is a new extension name introduced with RVA20. \ No newline at end of file diff --git a/arch/profile_release/RVA22.yaml b/arch/profile_release/RVA22.yaml index fd4533c0ef..556bf8abf1 100644 --- a/arch/profile_release/RVA22.yaml +++ b/arch/profile_release/RVA22.yaml @@ -32,227 +32,229 @@ RVA22: email: krste@sifive.com company: SiFive profiles: - - name: RVA22U64 - marketing_name: RVA22U64 - mode: Unpriv - base: 64 - release: RVA22 - introduction: | - The RVA22U64 profile specifies the ISA features available to user-mode - execution environments in 64-bit applications processors. This is the - most important profile within application processors in - terms of the amount of software that targets this profile. - extensions: - - name: Zihpm - presence: mandatory - version: "= 2.0" - - name: Zihintpause - presence: mandatory - version: "= 2.0" - note: | - While the `pause` instruction is a HINT can be implemented as a - NOP and hence trivially supported by hardware implementers, its - inclusion in the mandatory extension list signifies that software - should use the instruction whenever it would make sense and that - implementors are expected to exploit this information to optimize - hardware execution. - - name: Zba - presence: mandatory - version: "~> 1.0" - - name: Zbb - presence: mandatory - version: "~> 1.0" - - name: Zbs - presence: mandatory - version: "~> 1.0" - - name: Zic64b - presence: mandatory - version: "= 1.0" - note: | - This is a new extension name for this feature. While the general - RISC-V specifications are agnostic to cache block size, selecting a - common cache block size simplifies the specification and use of the - following cache-block extensions within the application processor - profile. Software does not have to query a discovery mechanism and/or - provide dynamic dispatch to the appropriate code. We choose 64 bytes - at it is effectively an industry standard. Implementations may use - longer cache blocks to reduce tag cost provided they use 64-byte - sub-blocks to remain compatible. Implementations may use shorter cache - blocks provided they sequence cache operations across the multiple - cache blocks comprising a 64-byte block to remain compatible. - - name: Zicbom - presence: mandatory - version: "~> 1.0" - - name: Zicbop - presence: mandatory - version: "~> 1.0" - note: | - As with other HINTS, the inclusion of prefetches in the - mandatory set of extensions indicates that software should generate - these instructions where they are expected to be useful, and hardware - is expected to exploit that information. - - name: Zicboz - presence: mandatory - version: "~> 1.0" - - name: Zfhmin - presence: mandatory - version: "~> 1.0" - note: | - Zfhmin is a small extension that adds support to load/store and convert - IEEE 754 half-precision numbers to and from the IEEE 754 single-precision - format. The hardware cost for this extension is low, and mandating the - extension avoids adding an option to the profile. - - name: Zkt - presence: mandatory - version: "~> 1.0" - note: | - Zkt requires a certain subset of integer instructions execute - with data-independent latency. Mandating this feature enables - portable libraries for safe basic cryptographic operations. It is - expected that application processors will naturally have this property - and so implementation cost is low, if not zero, in most systems that - would support RVA22. - - name: Zfh - presence: optional - version: "~> 1.0" - note: A future profile might mandate V. - - name: V - presence: optional - version: "~> 1.0" - note: | - The smaller vector extensions (Zve32f, Zve32x, Zve64d, Zve64f, - Zve64x) are not provided as separately supported profile options. The - full V extension is specified as the only supported profile option. - - A future profile might mandate V. - - name: Zkn - presence: optional - version: "~> 1.0" - - name: Zks - presence: optional - version: "~> 1.0" - extra_notes: - - presence: optional - text: | - The scalar crypto extensions are expected to be superseded by - vector crypto standards in future profiles, and the scalar extensions - may be removed as supported options once vector crypto is present. - - presence: optional - text: | - The smaller component scalar crypto extensions (Zbc, Zbkb, Zbkc, - Zbkx, Zknd, Zkne, Zknh, Zksed, Zksh) are not provided as separate - options in the profile. Profile implementers should provide all of - the instructions in a given algorithm suite as part of the Zkn or Zks - supported options. - - presence: optional - text: | - Access to the entropy source (Zkr) in a system is usually - carefully controlled. While the design supports unprivileged access - to the entropy source, this is unlikely to be commonly used in an - application processor, and so Zkr was not added as a profile option. - This also means the roll-up Zk was not added as a profile option. - - presence: optional - text: | - The Zfinx, Zdinx, Zhinx, Zhinxmin extensions are incompatible - with the profile mandates to support the F and D extensions. - - name: RVA22S64 - marketing_name: RVA22S64 - mode: S - base: 64 - release: RVA22 - introduction: | - The RVA22S64 profile specifies the ISA features available to a - supervisor-mode execution environment in 64-bit applications - processors. RVA22S64 is based on privileged architecture version - 1.12. - extensions: - - name: S - presence: mandatory - version: "= 1.12" - - name: Sscounterenw - presence: mandatory - version: "= 1.0" - note: | - Sstvala is a new extension name introduced with RVA22. - - name: Svpbmt - presence: mandatory - version: "~> 1.0" - - name: Svinval - presence: mandatory - version: "~> 1.0" - - name: Ssstateen - presence: mandatory - version: "~> 1.0" - when: - implemented: H - note: | - Ssstateen is a new extension name introduced with RVA22. - - name: Shvstvala - presence: mandatory - version: "~> 1.0" - when: - implemented: H - note: | - Shvstvala is a new extension name introduced with RVA22. - - name: Shtvala - presence: mandatory - version: "~> 1.0" - when: - implemented: H - note: | - Shtvala is a new extension name introduced with RVA22. - - name: Shvstvecd - presence: mandatory - version: "~> 1.0" - when: - implemented: H - note: | - Shvstvecd is a new extension name introduced with RVA22. - - name: Shgatpa - presence: mandatory - version: "~> 1.0" - when: - implemented: H - note: | - Shgatpa is a new extension name introduced with RVA22. - - name: Sv57 - presence: optional - version: "~> 1.12" - - name: Svnapot - presence: optional - version: "~> 1.0" - note: | - It is expected that Svnapot will be mandatory in the next - profile release. - - name: Sstc - presence: optional - version: "~> 1.0" - note: | - Sstc was not made mandatory in RVA22S64 as it is a more - disruptive change affecting system-level architecture, and will take - longer for implementations to adopt. It is expected to be made - mandatory in the next profile release. - - name: Sscofpmf - presence: optional - version: "~> 1.0" - note: | - Platforms may choose to mandate the presence of Sscofpmf. - - name: Zkr - presence: optional - version: "~> 1.0" - note: | - Technically, Zk is also a privileged-mode option capturing that - Zkr, Zkn, and Zkt are all implemented. However, the Zk rollup is less - descriptive than specifying the individual extensions explicitly. - - name: H - presence: optional - version: "~> 1.0" - note: | - The following extensions become mandatory when H is implemented: - - * Ssstateen - * Shcounterenw - * Shvstvala - * Shtvala - * Shvstvecd - * Shgatpa \ No newline at end of file + RVA22U64: + marketing_name: RVA22U64 + mode: Unpriv + base: 64 + release: RVA22 + introduction: | + The RVA22U64 profile specifies the ISA features available to user-mode + execution environments in 64-bit applications processors. This is the + most important profile within application processors in + terms of the amount of software that targets this profile. + extensions: + $mref: "RVA20.yaml#/RVA20/profiles/RVA20U64/extensions" + Zihpm: + presence: mandatory + version: "= 2.0" + Zihintpause: + presence: mandatory + version: "= 2.0" + note: | + While the `pause` instruction is a HINT can be implemented as a + NOP and hence trivially supported by hardware implementers, its + inclusion in the mandatory extension list signifies that software + should use the instruction whenever it would make sense and that + implementors are expected to exploit this information to optimize + hardware execution. + Zba: + presence: mandatory + version: "~> 1.0" + Zbb: + presence: mandatory + version: "~> 1.0" + Zbs: + presence: mandatory + version: "~> 1.0" + Zic64b: + presence: mandatory + version: "= 1.0" + note: | + This is a new extension name for this feature. While the general + RISC-V specifications are agnostic to cache block size, selecting a + common cache block size simplifies the specification and use of the + following cache-block extensions within the application processor + profile. Software does not have to query a discovery mechanism and/or + provide dynamic dispatch to the appropriate code. We choose 64 bytes + at it is effectively an industry standard. Implementations may use + longer cache blocks to reduce tag cost provided they use 64-byte + sub-blocks to remain compatible. Implementations may use shorter cache + blocks provided they sequence cache operations across the multiple + cache blocks comprising a 64-byte block to remain compatible. + Zicbom: + presence: mandatory + version: "~> 1.0" + Zicbop: + presence: mandatory + version: "~> 1.0" + note: | + As with other HINTS, the inclusion of prefetches in the + mandatory set of extensions indicates that software should generate + these instructions where they are expected to be useful, and hardware + is expected to exploit that information. + Zicboz: + presence: mandatory + version: "~> 1.0" + Zfhmin: + presence: mandatory + version: "~> 1.0" + note: | + Zfhmin is a small extension that adds support to load/store and convert + IEEE 754 half-precision numbers to and from the IEEE 754 single-precision + format. The hardware cost for this extension is low, and mandating the + extension avoids adding an option to the profile. + Zkt: + presence: mandatory + version: "~> 1.0" + note: | + Zkt requires a certain subset of integer instructions execute + with data-independent latency. Mandating this feature enables + portable libraries for safe basic cryptographic operations. It is + expected that application processors will naturally have this property + and so implementation cost is low, if not zero, in most systems that + would support RVA22. + Zfh: + presence: optional + version: "~> 1.0" + note: A future profile might mandate V. + V: + presence: optional + version: "~> 1.0" + note: | + The smaller vector extensions (Zve32f, Zve32x, Zve64d, Zve64f, + Zve64x) are not provided as separately supported profile options. The + full V extension is specified as the only supported profile option. + + A future profile might mandate V. + Zkn: + presence: optional + version: "~> 1.0" + Zks: + presence: optional + version: "~> 1.0" + extra_notes: + - presence: optional + text: | + The scalar crypto extensions are expected to be superseded by + vector crypto standards in future profiles, and the scalar extensions + may be removed as supported options once vector crypto is present. + - presence: optional + text: | + The smaller component scalar crypto extensions (Zbc, Zbkb, Zbkc, + Zbkx, Zknd, Zkne, Zknh, Zksed, Zksh) are not provided as separate + options in the profile. Profile implementers should provide all of + the instructions in a given algorithm suite as part of the Zkn or Zks + supported options. + - presence: optional + text: | + Access to the entropy source (Zkr) in a system is usually + carefully controlled. While the design supports unprivileged access + to the entropy source, this is unlikely to be commonly used in an + application processor, and so Zkr was not added as a profile option. + This also means the roll-up Zk was not added as a profile option. + - presence: optional + text: | + The Zfinx, Zdinx, Zhinx, Zhinxmin extensions are incompatible + with the profile mandates to support the F and D extensions. + RVA22S64: + marketing_name: RVA22S64 + mode: S + base: 64 + release: RVA22 + introduction: | + The RVA22S64 profile specifies the ISA features available to a + supervisor-mode execution environment in 64-bit applications + processors. RVA22S64 is based on privileged architecture version + 1.12. + extensions: + $mref: "RVA20.yaml#/RVA20/profiles/RVA20S64/extensions" + S: + presence: mandatory + version: "= 1.12" + Sscounterenw: + presence: mandatory + version: "= 1.0" + note: | + Sstvala is a new extension name introduced with RVA22. + Svpbmt: + presence: mandatory + version: "~> 1.0" + Svinval: + presence: mandatory + version: "~> 1.0" + Ssstateen: + presence: mandatory + version: "~> 1.0" + when: + implemented: H + note: | + Ssstateen is a new extension name introduced with RVA22. + Shvstvala: + presence: mandatory + version: "~> 1.0" + when: + implemented: H + note: | + Shvstvala is a new extension name introduced with RVA22. + Shtvala: + presence: mandatory + version: "~> 1.0" + when: + implemented: H + note: | + Shtvala is a new extension name introduced with RVA22. + Shvstvecd: + presence: mandatory + version: "~> 1.0" + when: + implemented: H + note: | + Shvstvecd is a new extension name introduced with RVA22. + Shgatpa: + presence: mandatory + version: "~> 1.0" + when: + implemented: H + note: | + Shgatpa is a new extension name introduced with RVA22. + Sv57: + presence: optional + version: "~> 1.12" + Svnapot: + presence: optional + version: "~> 1.0" + note: | + It is expected that Svnapot will be mandatory in the next + profile release. + Sstc: + presence: optional + version: "~> 1.0" + note: | + Sstc was not made mandatory in RVA22S64 as it is a more + disruptive change affecting system-level architecture, and will take + longer for implementations to adopt. It is expected to be made + mandatory in the next profile release. + Sscofpmf: + presence: optional + version: "~> 1.0" + note: | + Platforms may choose to mandate the presence of Sscofpmf. + Zkr: + presence: optional + version: "~> 1.0" + note: | + Technically, Zk is also a privileged-mode option capturing that + Zkr, Zkn, and Zkt are all implemented. However, the Zk rollup is less + descriptive than specifying the individual extensions explicitly. + H: + presence: optional + version: "~> 1.0" + note: | + The following extensions become mandatory when H is implemented: + + * Ssstateen + * Shcounterenw + * Shvstvala + * Shtvala + * Shvstvecd + * Shgatpa \ No newline at end of file diff --git a/arch/profile_release/RVI20.yaml b/arch/profile_release/RVI20.yaml index 1269cda4e6..74538c7f9b 100644 --- a/arch/profile_release/RVI20.yaml +++ b/arch/profile_release/RVI20.yaml @@ -17,135 +17,73 @@ RVI20: email: krste@sifive.com company: SiFive profiles: - - name: RVI20U32 - marketing_name: RVI20U32 - mode: Unpriv - base: 32 - release: RVI20 - introduction: | - RVI20U32 specifies the ISA features available to generic unprivileged - execution environments. - extensions: - - name: I - presence: mandatory - version: "~> 2.1" - note: | - RVI is the mandatory base ISA for RVA, and is little-endian. - - As per the unprivileged architecture specification, the `ecall` - instruction causes a requested trap to the execution environment. - - Misaligned loads and stores might not be supported. - - The `fence.tso` instruction is mandatory. - - NOTE: The `fence.tso` instruction was incorrectly described as - optional in the 2019 ratified specifications. However, `fence.tso` is - encoded within the standard `fence` encoding such that implementations - must treat it as a simple global fence if they do not natively support - TSO-ordering optimizations. As software can always assume without any - penalty that `fence.tso` is being exploited by a hardware - implementation, there is no advantage to making the instruction a - profile option. Later versions of the unprivileged ISA specifications - correctly indicate that `fence.tso` is mandatory. - - - name: A - presence: optional - version: "= 2.1" - - name: C - presence: optional - version: "= 2.2" - - name: D - presence: optional - version: "= 2.2" - note: | - NOTE: The rationale to not include Q as a profile option is that - quad-precision floating-point is unlikely to be implemented in - hardware, and so we do not require or expect software to expend effort - optimizing use of Q instructions in case they are present. - - name: F - presence: optional - version: "= 2.2" - - name: M - presence: optional - version: "= 2.0" - - name: Zicntr - presence: optional - version: " = 2.0" - - name: Zihpm - presence: optional - version: "= 2.0" - note: | - The number of counters is platform-specific. - - name: Zifencei - presence: optional - recommendations: - - text: | - Implementations are strongly recommended to raise illegal-instruction - exceptions on attempts to execute unimplemented opcodes. - - name: RVI20U64 - marketing_name: RVI20U64 - mode: Unpriv - base: 64 - release: RVI20 - introduction: | - RVI20U64 specifies the ISA features available to generic unprivileged - execution environments. - extensions: - - name: I - presence: mandatory - version: "~> 2.1" - note: | - RVI is the mandatory base ISA for RVA, and is little-endian. - - As per the unprivileged architecture specification, the `ecall` - instruction causes a requested trap to the execution environment. - - Misaligned loads and stores might not be supported. - - The `fence.tso` instruction is mandatory. - - NOTE: The `fence.tso` instruction was incorrectly described as - optional in the 2019 ratified specifications. However, `fence.tso` is - encoded within the standard `fence` encoding such that implementations - must treat it as a simple global fence if they do not natively support - TSO-ordering optimizations. As software can always assume without any - penalty that `fence.tso` is being exploited by a hardware - implementation, there is no advantage to making the instruction a - profile option. Later versions of the unprivileged ISA specifications - correctly indicate that `fence.tso` is mandatory. - - - name: A - presence: optional - version: "= 2.1" - - name: C - presence: optional - version: "= 2.2" - - name: D - presence: optional - version: "= 2.2" - note: | - NOTE: The rationale to not include Q as a profile option is that - quad-precision floating-point is unlikely to be implemented in - hardware, and so we do not require or expect software to expend effort - optimizing use of Q instructions in case they are present. - - name: F - presence: optional - version: "= 2.2" - - name: M - presence: optional - version: "= 2.0" - - name: Zicntr - presence: optional - version: " = 2.0" - - name: Zihpm - presence: optional - version: "= 2.0" - note: | - The number of counters is platform-specific. - - name: Zifencei - presence: optional - recommendations: - - text: | - Implementations are strongly recommended to raise illegal-instruction - exceptions on attempts to execute unimplemented opcodes. \ No newline at end of file + RVI20U32: + marketing_name: RVI20U32 + mode: Unpriv + base: 32 + release: RVI20 + introduction: | + This profile specifies the ISA features available to generic unprivileged + execution environments. + extensions: + I: + presence: mandatory + version: "~> 2.1" + note: | + RVI is the mandatory base ISA for RVA, and is little-endian. + + As per the unprivileged architecture specification, the `ecall` + instruction causes a requested trap to the execution environment. + + Misaligned loads and stores might not be supported. + + The `fence.tso` instruction is mandatory. + + NOTE: The `fence.tso` instruction was incorrectly described as + optional in the 2019 ratified specifications. However, `fence.tso` is + encoded within the standard `fence` encoding such that implementations + must treat it as a simple global fence if they do not natively support + TSO-ordering optimizations. As software can always assume without any + penalty that `fence.tso` is being exploited by a hardware + implementation, there is no advantage to making the instruction a + profile option. Later versions of the unprivileged ISA specifications + correctly indicate that `fence.tso` is mandatory. + A: + presence: optional + version: "= 2.1" + C: + presence: optional + version: "= 2.2" + D: + presence: optional + version: "= 2.2" + note: | + NOTE: The rationale to not include Q as a profile option is that + quad-precision floating-point is unlikely to be implemented in + hardware, and so we do not require or expect software to expend effort + optimizing use of Q instructions in case they are present. + F: + presence: optional + version: "= 2.2" + M: + presence: optional + version: "= 2.0" + Zicntr: + presence: optional + version: " = 2.0" + Zihpm: + presence: optional + version: "= 2.0" + note: | + The number of counters is platform-specific. + Zifencei: + presence: optional + version: "= 2.0" + recommendations: + - text: | + Implementations are strongly recommended to raise illegal-instruction + exceptions on attempts to execute unimplemented opcodes. + RVI20U64: + $mref: "#/RVI20/profiles/RVI20U32" + base: 64 + marketing_name: RVI20U64 \ No newline at end of file diff --git a/backends/certificate_doc/templates/certificate.adoc.erb b/backends/certificate_doc/templates/certificate.adoc.erb index e2d61c14f9..bdbe71f31b 100644 --- a/backends/certificate_doc/templates/certificate.adoc.erb +++ b/backends/certificate_doc/templates/certificate.adoc.erb @@ -117,7 +117,7 @@ None | Requirement ID | Extension | Version | Long Name | Note <% ext_reqs.sort.each do |ext_req| -%> -<% ext_db = cert_model.extension_from_db(ext_req.name) -%> +<% ext_db = arch_def.extension(ext_req.name) -%> | <%= ext_req.req_id %> | <-def,<%= ext_req.name %>>> | <%= ext_req.version_requirement %> @@ -289,7 +289,7 @@ Requirement <%= req.name %> only apply when <%= req.when_pretty %>. [appendix] == Extension Details <% cert_model.in_scope_ext_reqs.sort.each do |ext_req| -%> -<% ext_db = cert_model.extension_from_db(ext_req.name) -%> +<% ext_db = arch_def.extension(ext_req.name) -%> [[ext-<%= ext_req.name %>-def]] === Extension <%= ext_req.name %> + diff --git a/backends/profile_doc/tasks.rake b/backends/profile_doc/tasks.rake index 23118c741d..03aed02634 100644 --- a/backends/profile_doc/tasks.rake +++ b/backends/profile_doc/tasks.rake @@ -87,7 +87,7 @@ namespace :gen do raise ArgumentError, "Missing required option +profile_release+" if profile_release_name.nil? profile_release = arch_def_for("_64").profile_release(profile_release_name) - raise ArgumentError, "No profile release named '#{profile_release_name}" if profile_release.nil? + raise ArgumentError, "No profile release named '#{profile_release_name}'" if profile_release.nil? Rake::Task["#{$root}/gen/profile_doc/pdf/#{profile_release_name}.pdf"].invoke end diff --git a/lib/arch_def.rb b/lib/arch_def.rb index b6fa86279a..ebcf272a31 100644 --- a/lib/arch_def.rb +++ b/lib/arch_def.rb @@ -690,7 +690,8 @@ def profiles @arch_def["profile_releases"].each_value do |pr_data| raise ArgumentError, "Expecting pr_data to be a hash" unless pr_data.is_a?(Hash) - pr_data["profiles"].each do |profile_data| + pr_data["profiles"].each do |profile_name, profile_data| + profile_data["name"] = profile_name profile = Profile.new(profile_data, self) raise ArgumentError, "Profile constructor returned nil" if profile.nil? diff --git a/lib/arch_obj_models/portfolio.rb b/lib/arch_obj_models/portfolio.rb index 891ac9cfa0..820c189d7a 100644 --- a/lib/arch_obj_models/portfolio.rb +++ b/lib/arch_obj_models/portfolio.rb @@ -7,7 +7,7 @@ # Many classes inherit from the ArchDefObject class. This provides facilities for accessing the contents of a # Portfolio Class YAML or Portfolio Model YAML file via the "data" member (hash holding releated YAML file contents). # -# A variable name with a "_portfolio" suffix indicates it is from the porfolio YAML file. +# A variable name with a "_data" suffix indicates it is the raw hash data from the porfolio YAML file. # A variable name with a "_db" suffix indicates it is an object reference from the arch_def database. require_relative "obj" @@ -62,47 +62,35 @@ def description = @data["description"] # @return [Gem::Version] Semantic version of the PortfolioInstance def version = Gem::Version.new(@data["version"]) - # @return [Extension] - Returns named Extension object from database (nil if not found). - def extension_from_db(ext_name) - @arch_def.extension(ext_name) - end - - # @return [Extension] - Returns named Extension object from portfolio (error if not found). - def extension_from_portfolio(ext_name) - # Get extension information from YAML for passed in extension name. - ext_portfolio = @data["extensions"].find {|ext| ext["name"] == ext_name} - raise "Cannot find extension named #{ext_name}" if ext_portfolio.nil? - - ext_portfolio - end - # @return [String] Given an extension +ext_name+, return the presence. # If the extension name isn't found in the portfolio, return "-". def extension_presence(ext_name) # Get extension information from YAML for passed in extension name. - ext_portfolio = @data["extensions"].find {|ext| ext["name"] == ext_name} + ext_data = @data["extensions"][ext_name] - ext_portfolio.nil? ? "-" : ext_portfolio["presence"] + ext_data.nil? ? "-" : ext_data["presence"] end # @return [String] The note associated with extension +ext_name+ # @return [nil] if there is no note for +ext_name+ def extension_note(ext_name) - ext = extension_from_portfolio(ext_name) + # Get extension information from YAML for passed in extension name. + ext_data = @data["extensions"][ext_name] + raise "Cannot find extension named #{ext_name}" if ext_data.nil? - return ext["note"] unless ext.nil? + return ext_data["note"] unless ext_data.nil? end # @return [Array] - # Extensions with their portfolio information. # If desired_presence is provided, only returns extensions with that presence. def in_scope_ext_reqs(desired_presence = nil) in_scope_ext_reqs = [] - @data["extensions"]&.each do |ext_portfolio| - actual_presence = ext_portfolio["presence"] - raise "Missing extension presence for extension #{ext_portfolio["name"]}" if actual_presence.nil? + @data["extensions"]&.each do |ext_name, ext_data| + actual_presence = ext_data["presence"] + raise "Missing extension presence for extension #{ext_name}" if actual_presence.nil? if (actual_presence != "mandatory") && (actual_presence != "optional") - raise "Unknown extension presence of #{actual_presence} for extension #{ext_portfolio["name"]}" + raise "Unknown extension presence of #{actual_presence} for extension #{ext_name}" end add = false @@ -115,8 +103,8 @@ def in_scope_ext_reqs(desired_presence = nil) if add in_scope_ext_reqs << - ExtensionRequirement.new(ext_portfolio["name"], ext_portfolio["version"], presence: actual_presence, - note: ext_portfolio["note"], req_id: "REQ-EXT-" + ext_portfolio["name"]) + ExtensionRequirement.new(ext_name, ext_data["version"], presence: actual_presence, + note: ext_data["note"], req_id: "REQ-EXT-" + ext_name) end end in_scope_ext_reqs @@ -216,17 +204,17 @@ def all_in_scope_ext_params @all_in_scope_ext_params = [] - @data["extensions"].each do |ext_portfolio| + @data["extensions"].each do |ext_name, ext_data| # Find Extension object from database - ext_db = @arch_def.extension(ext_portfolio["name"]) - raise "Cannot find extension named #{ext_portfolio["name"]}" if ext_db.nil? + ext_db = @arch_def.extension(ext_name) + raise "Cannot find extension named #{ext_name}" if ext_db.nil? - ext_portfolio["parameters"]&.each do |param_name, param_data| + ext_data["parameters"]&.each do |param_name, param_data| param_db = ext_db.params.find { |p| p.name == param_name } - raise "There is no param '#{param_name}' in extension '#{ext_portfolio["name"]}" if param_db.nil? + raise "There is no param '#{param_name}' in extension '#{ext_name}" if param_db.nil? next unless ext_db.versions.any? do |ver_hash| - Gem::Requirement.new(ext_portfolio["version"]).satisfied_by?(Gem::Version.new(ver_hash["version"])) && + Gem::Requirement.new(ext_data["version"]).satisfied_by?(Gem::Version.new(ver_hash["version"])) && param_db.defined_in_extension_version?(ver_hash["version"]) end @@ -245,22 +233,22 @@ def in_scope_ext_params(ext_req) ext_params = [] # Local variable, no caching # Get extension information from portfolio YAML for passed in extension requirement. - ext_portfolio = @data["extensions"].find {|ext| ext["name"] == ext_req.name} - raise "Cannot find extension named #{ext_req.name}" if ext_portfolio.nil? + ext_data = @data["extensions"][ext_req.name] + raise "Cannot find extension named #{ext_req.name}" if ext_data.nil? # Find Extension object from database - ext_db = @arch_def.extension(ext_portfolio["name"]) - raise "Cannot find extension named #{ext_portfolio["name"]}" if ext_db.nil? + ext_db = @arch_def.extension(ext_req.name) + raise "Cannot find extension named #{ext_req.name}" if ext_db.nil? # Loop through an extension's parameter constraints (hash) from the portfolio. # Note that "&" is the Ruby safe navigation operator (i.e., skip do loop if nil). - ext_portfolio["parameters"]&.each do |param_name, param_data| + ext_data["parameters"]&.each do |param_name, param_data| # Find ExtensionParameter object from database ext_param_db = ext_db.params.find { |p| p.name == param_name } - raise "There is no param '#{param_name}' in extension '#{ext_portfolio["name"]}" if ext_param_db.nil? + raise "There is no param '#{param_name}' in extension '#{ext_req.name}" if ext_param_db.nil? next unless ext_db.versions.any? do |ver_hash| - Gem::Requirement.new(ext_portfolio["version"]).satisfied_by?(Gem::Version.new(ver_hash["version"])) && + Gem::Requirement.new(ext_data["version"]).satisfied_by?(Gem::Version.new(ver_hash["version"])) && ext_param_db.defined_in_extension_version?(ver_hash["version"]) end diff --git a/lib/arch_obj_models/profile.rb b/lib/arch_obj_models/profile.rb index a83a2b48d0..e3ea02e4b1 100644 --- a/lib/arch_obj_models/profile.rb +++ b/lib/arch_obj_models/profile.rb @@ -37,8 +37,6 @@ def profile_releases def profiles return @profiles unless @profiles.nil? - puts " 2a: profiles for class #{name} called." - @profiles = [] @arch_def.profiles.each do |profile| if profile.profile_class.name == name diff --git a/lib/yaml_loader.rb b/lib/yaml_loader.rb index 6c85f970cf..ce8586ef7d 100644 --- a/lib/yaml_loader.rb +++ b/lib/yaml_loader.rb @@ -48,6 +48,7 @@ def self.expand(filename, obj, yaml_opts = {}) elsif obj.keys.include?("$mref") # we handle the mref key first so that any override will take priority mref = obj["$mref"] + raise ArgumentError, "Missing reference after $mref (did you forget to put a relative reference in quotes?)" if mref.nil? mref_targets = mref.is_a?(String) ? [mref] : mref new_obj = {} @@ -67,11 +68,20 @@ def self.expand(filename, obj, yaml_opts = {}) YamlLoader.load(target_filename, yaml_opts) end - target_obj = target_obj.dig(*mref_target.split("#/")[1].split("/")) - if target_obj.nil? - raise DereferenceError, "JSON Path #{mref_target.split('#')[1]} does not exist in #{relative_path}" + mref_target_suffix = mref_target.split("#/")[1] + mref_target_path = mref_target_suffix.split("/") + begin + target_obj = target_obj.dig(*mref_target_path) + rescue TypeError => e + if e.message == "no implicit conversion of String into Integer" + warn "$mref: \"#{mref_target}\" found in file #{filename} references an Array but needs to reference a Hash" + end + raise e end + raise DereferenceError, "JSON Path #{mref_target_suffix} in file #{filename} does not exist in #{relative_path}" if target_obj.nil? + raise ArgumentError, "$mref: \"#{mref_target}\" in file #{filename} references a #{target_obj.class} but needs to reference a Hash" unless target_obj.is_a?(Hash) + target_obj.each do |target_key, target_value| new_obj[target_key] = expand(filename, target_value, yaml_opts) end From 1e2aa9e08f2e72e71e7b275e71a66c4bdcc484e7 Mon Sep 17 00:00:00 2001 From: James Ball Date: Fri, 8 Nov 2024 12:20:48 -0800 Subject: [PATCH 3/5] Commiting to get $mref fix --- arch/certificate_model/MockCertificateModel.yaml | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/certificate_model/MockCertificateModel.yaml b/arch/certificate_model/MockCertificateModel.yaml index d1eab989fb..b38aa8be99 100644 --- a/arch/certificate_model/MockCertificateModel.yaml +++ b/arch/certificate_model/MockCertificateModel.yaml @@ -42,8 +42,6 @@ MockCertificateModel: - "../profile_release/MockProfileRelease.yaml#/MockProfileRelease/profiles/MP-U-64/extensions" - "../profile_release/MockProfileRelease.yaml#/MockProfileRelease/profiles/MP-S-64/extensions" I: - presence: optional - version: "=2.1.0" note: Changed inherited I extension from mandatory to optional and version is =2.1.0 instead of ~>2.1 MockExt: presence: mandatory From 4e1fe38fcdd075a18ae6749f491e098e2d7e96fb Mon Sep 17 00:00:00 2001 From: James Ball Date: Fri, 8 Nov 2024 12:45:12 -0800 Subject: [PATCH 4/5] Ready to merge in again. --- arch/profile_release/RVA20.yaml | 4 +--- lib/yaml_loader.rb | 4 +++- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/profile_release/RVA20.yaml b/arch/profile_release/RVA20.yaml index 0abdd9f7bd..b1d8770949 100644 --- a/arch/profile_release/RVA20.yaml +++ b/arch/profile_release/RVA20.yaml @@ -44,6 +44,7 @@ RVA20: terms of the amount of software that targets this profile. extensions: $mref: "RVI20.yaml#/RVI20/profiles/RVI20U64/extensions" + $remove: Zifencei # Not allowed as an option for Unpriv ISA (only available in Priv ISA). A: presence: mandatory C: @@ -63,9 +64,6 @@ RVA20: const: little Zicntr: presence: mandatory - #Zifencei: - # How do we remove Zifencei as an option since it is included in the RVI64 profile - # presence: XXX Ziccif: presence: mandatory version: "= 1.0" diff --git a/lib/yaml_loader.rb b/lib/yaml_loader.rb index ce8586ef7d..751fdee5c9 100644 --- a/lib/yaml_loader.rb +++ b/lib/yaml_loader.rb @@ -82,8 +82,10 @@ def self.expand(filename, obj, yaml_opts = {}) raise DereferenceError, "JSON Path #{mref_target_suffix} in file #{filename} does not exist in #{relative_path}" if target_obj.nil? raise ArgumentError, "$mref: \"#{mref_target}\" in file #{filename} references a #{target_obj.class} but needs to reference a Hash" unless target_obj.is_a?(Hash) + target_obj = expand(filename, target_obj, yaml_opts) target_obj.each do |target_key, target_value| - new_obj[target_key] = expand(filename, target_value, yaml_opts) + + new_obj[target_key] = target_value end end From 077034d6d495a61b739c035e22a4d2ffd13ed04c Mon Sep 17 00:00:00 2001 From: James Ball Date: Fri, 8 Nov 2024 12:53:09 -0800 Subject: [PATCH 5/5] Adding note to I extension now works. --- arch/certificate_model/MockCertificateModel.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/certificate_model/MockCertificateModel.yaml b/arch/certificate_model/MockCertificateModel.yaml index b38aa8be99..bb9ef120d3 100644 --- a/arch/certificate_model/MockCertificateModel.yaml +++ b/arch/certificate_model/MockCertificateModel.yaml @@ -42,7 +42,7 @@ MockCertificateModel: - "../profile_release/MockProfileRelease.yaml#/MockProfileRelease/profiles/MP-U-64/extensions" - "../profile_release/MockProfileRelease.yaml#/MockProfileRelease/profiles/MP-S-64/extensions" I: - note: Changed inherited I extension from mandatory to optional and version is =2.1.0 instead of ~>2.1 + note: Just added this note to I extension MockExt: presence: mandatory parameters: