diff --git a/.devcontainer/onCreateCommand.sh b/.devcontainer/onCreateCommand.sh index c51b5e23b1..d4ecba051b 100755 --- a/.devcontainer/onCreateCommand.sh +++ b/.devcontainer/onCreateCommand.sh @@ -1,4 +1,4 @@ #!/bin/bash -npm i +npm i bundle install diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml new file mode 100644 index 0000000000..3063481e8f --- /dev/null +++ b/.pre-commit-config.yaml @@ -0,0 +1,14 @@ +--- +exclude: ^docs/ruby/ # All generated code + +repos: + - repo: https://github.com/pre-commit/pre-commit-hooks + rev: v5.0.0 + hooks: + - id: check-symlinks + - id: end-of-file-fixer + - id: trailing-whitespace + args: [--markdown-linebreak-ext=md] + - id: check-merge-conflict + args: ["--assume-in-merge"] + exclude: \.adoc$ # sections titles Level 6 "=======" get flagged otherwise diff --git a/LICENSE b/LICENSE index c7a4e51d5e..c61afe2393 100644 --- a/LICENSE +++ b/LICENSE @@ -18,7 +18,7 @@ met: NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS +FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN diff --git a/Rakefile b/Rakefile index bddeefd9dc..84461cca27 100644 --- a/Rakefile +++ b/Rakefile @@ -98,7 +98,7 @@ namespace :test do validator.validate(f) end Rake::Task["test:insts"].invoke - puts "All files validate against their schema" + puts "All files validate against their schema" end task idl_model: ["gen:arch", "#{$root}/.stamps/arch-gen-_32.stamp", "#{$root}/.stamps/arch-gen-_64.stamp"] do print "Parsing IDL code for RV32..." @@ -298,7 +298,7 @@ namespace :test do ENV["MANUAL_NAME"] = "isa" ENV["VERSIONS"] = "all" Rake::Task["gen:html_manual"].invoke - + ENV["EXT"] = "B" ENV["VERSION"] = "latest" Rake::Task["gen:ext_pdf"].invoke @@ -371,4 +371,4 @@ namespace :gen do puts "===================================" Rake::Task["#{$root}/gen/profile_doc/pdf/MockProfileRelease.pdf"].invoke end -end \ No newline at end of file +end diff --git a/arch/README.adoc b/arch/README.adoc index 06f5c68596..185100f3b7 100644 --- a/arch/README.adoc +++ b/arch/README.adoc @@ -21,7 +21,7 @@ To tame this challenge, this specification generator takes the following approac The architecture is specified in a series of https://en.wikipedia.org/wiki/YAML[YAML] files for _Extensions_, _Instructions_, and _Control and Status Registers (CSRs)_. -Each extension/instruction/CSR has its own file. +Each extension/instruction/CSR has its own file. == Flow diff --git a/arch/certificate_class/MC.yaml b/arch/certificate_class/MC.yaml index cf2d7512cb..d31c7a25f0 100644 --- a/arch/certificate_class/MC.yaml +++ b/arch/certificate_class/MC.yaml @@ -21,12 +21,12 @@ naming_scheme: | Where: - * Left & right square braces denote optional. + * Left & right square braces denote optional. * \ is a 3 digit integer. It is changed only when mandatory extensions are added to a CRD. ** The one's digit is incremented when a small mandatory extension is added (e.g., Zicond) ** The ten's digit is incremented when a medium mandatory extension is addded (e.g., PMP) ** The hundreds's digit is incremented when a large mandatory extension is addded (e.g., V or H) - * \ is a semantic version (see semver.org) formatted as [..[patch]]. If \ is omitted, the reference applies equally to all versions. + * \ is a semantic version (see semver.org) formatted as [..[patch]]. If \ is omitted, the reference applies equally to all versions. ** A release indicates support for a new optional extension. ** A release indicates one or more of the following changes to the certification tests associated with the CRD. *** Fix test bug or increase test coverage @@ -35,4 +35,4 @@ naming_scheme: | ** A release indicates just CRD specification changes without any difference in functional behavior mandatory_priv_modes: -- M \ No newline at end of file +- M diff --git a/arch/certificate_model/MC100.yaml b/arch/certificate_model/MC100.yaml index a182de1203..4589f965f1 100644 --- a/arch/certificate_model/MC100.yaml +++ b/arch/certificate_model/MC100.yaml @@ -8,7 +8,7 @@ class: $ref: certificate_class/MC.yaml# # Semantic versions within the model -versions: +versions: - version: "1.0.0" # XLEN used by rakefile @@ -139,4 +139,4 @@ extensions: const: little XLEN: schema: - const: 32 \ No newline at end of file + const: 32 diff --git a/arch/certificate_model/MockCertificateModel.yaml b/arch/certificate_model/MockCertificateModel.yaml index 2f19b00b56..188a05b82f 100644 --- a/arch/certificate_model/MockCertificateModel.yaml +++ b/arch/certificate_model/MockCertificateModel.yaml @@ -13,7 +13,7 @@ base: 64 # Semantic versions within the model versions: - version: "1.0.0" - - version: "1.1.0" + - version: "1.1.0" revision_history: - revision: "0.1.0" @@ -223,4 +223,4 @@ recommendations: - text: | Implementations are strongly recommended to raise illegal-instruction exceptions on attempts to execute unimplemented opcodes. -- text: Micky should give Pluto an extra treat \ No newline at end of file +- text: Micky should give Pluto an extra treat diff --git a/arch/csr/F/fcsr.yaml b/arch/csr/F/fcsr.yaml index 3948be255b..a44a5b39c7 100644 --- a/arch/csr/F/fcsr.yaml +++ b/arch/csr/F/fcsr.yaml @@ -42,7 +42,7 @@ description: | modes are encoded as shown in <>. A value of 111 in the instruction's _rm_ field selects the dynamic rounding mode held in `frm`. The behavior of floating-point instructions that depend on - rounding mode when executed with a reserved rounding mode is _reserved_, including both static reserved rounding modes (101-110) and dynamic reserved rounding modes (101-111). Some instructions, including widening conversions, have the _rm_ field but are nevertheless mathematically unaffected by the rounding mode; software should set their _rm_ field to + rounding mode when executed with a reserved rounding mode is _reserved_, including both static reserved rounding modes (101-110) and dynamic reserved rounding modes (101-111). Some instructions, including widening conversions, have the _rm_ field but are nevertheless mathematically unaffected by the rounding mode; software should set their _rm_ field to RNE (000) but implementations must treat the _rm_ field as usual (in particular, with regard to decoding legal vs. reserved encodings). @@ -122,7 +122,7 @@ fields: including both static reserved rounding modes (101-110) and dynamic reserved rounding modes (101-111). Some instructions, including widening conversions, have the _rm_ field but are nevertheless mathematically unaffected by the - rounding mode; software should set their _rm_ field to + rounding mode; software should set their _rm_ field to RNE (000) but implementations must treat the _rm_ field as usual (in particular, with regard to decoding legal vs. reserved encodings). type: RW-H @@ -181,4 +181,4 @@ fields: Set by hardware when a floating point operation is inexact and stays set until explicitly cleared by software. type: RW-H - reset_value: UNDEFINED_LEGAL \ No newline at end of file + reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/H/henvcfg.yaml b/arch/csr/H/henvcfg.yaml index 8086aec419..462bc0f138 100644 --- a/arch/csr/H/henvcfg.yaml +++ b/arch/csr/H/henvcfg.yaml @@ -12,7 +12,7 @@ description: | If bit `henvcfg.FIOM` (Fence of I/O implies Memory) is set to one in henvcfg, `fence` instructions executed when V=1 are modified so the requirement to order accesses to device I/O implies also the requirement to order main memory accesses. - + <> details the modified interpretation of FENCE instruction bits PI, PO, SI, and SO when FIOM=1 and V=1. @@ -71,7 +71,7 @@ description: | The Zicfiss extension adds the `SSE` field in `henvcfg`. If the `SSE` field is set to 1, the Zicfiss extension is activated in VS-mode. When the `SSE` field is 0, the Zicfiss extension remains inactive in VS-mode, and the following rules - apply when `V=1`: + apply when `V=1`: * 32-bit Zicfiss instructions will revert to their behavior as defined by Zimop. * 16-bit Zicfiss instructions will revert to their behavior as defined by Zcmop. @@ -127,12 +127,12 @@ fields: The PBMTE bit controls whether the `Svpbmt` extension is available for use in VS-stage address translation. - + When PBMTE=1, Svpbmt is available for VS-stage address translation. - + When PBMTE=0, the implementation behaves as though `Svpbmt` were not implemented for VS-stage address translation. - + If `Svpbmt` is not implemented, PBMTE is read-only zero. `henvcfg.PBMTE` is read-as-zero if `menvcfg.PBMTE` is zero. @@ -141,7 +141,7 @@ fields: _rs1_=_x0_ and _rs2_=_x0_ suffices to synchronize with respect to the altered interpretation of G-stage and VS-stage PTEs' PBMT fields. - By contrast, if the PBMTE bit in `henvcfg` is changed, executing an `hfence.vvma` with + By contrast, if the PBMTE bit in `henvcfg` is changed, executing an `hfence.vvma` with _rs1_=_x0_ and _rs2_=_x0_ suffices to synchronize with respect to the altered interpretation of VS-stage PTEs' PBMT fields for the currently active VMID. @@ -165,14 +165,14 @@ fields: description: | If the `Svadu` extension is implemented, the ADUE bit controls whether hardware updating of PTE A/D bits is enabled for VS-stage address translation. - + When ADUE=1, hardware updating of PTE A/D bits is enabled during VS-stage address translation, and the implementation behaves as though the Svade extension were not implemented for VS-mode address translation. - + When ADUE=0, the implementation behaves as though Svade were implemented for VS-stage address translation. - + If Svadu is not implemented, ADUE is read-only zero. Furthermore, for implementations with the hypervisor extension, henvcfg.ADUE is read-only @@ -287,4 +287,4 @@ sw_read(): | # henvcfg.ADUE must read-as-zero value = value & ~(1 << 61); } - return value; \ No newline at end of file + return value; diff --git a/arch/csr/H/henvcfgh.yaml b/arch/csr/H/henvcfgh.yaml index 692e159fe9..3b45ec2d44 100644 --- a/arch/csr/H/henvcfgh.yaml +++ b/arch/csr/H/henvcfgh.yaml @@ -47,12 +47,12 @@ fields: The PBMTE bit controls whether the `Svpbmt` extension is available for use in VS-stage address translation. - + When PBMTE=1, Svpbmt is available for VS-stage address translation. - + When PBMTE=0, the implementation behaves as though `Svpbmt` were not implemented for VS-stage address translation. - + If `Svpbmt` is not implemented, PBMTE is read-only zero. `henvcfg.PBMTE` is read-as-zero if `menvcfg.PBMTE` is zero. @@ -61,7 +61,7 @@ fields: _rs1_=_x0_ and _rs2_=_x0_ suffices to synchronize with respect to the altered interpretation of G-stage and VS-stage PTEs' PBMT fields. - By contrast, if the PBMTE bit in `henvcfg` is changed, executing an `hfence.vvma` with + By contrast, if the PBMTE bit in `henvcfg` is changed, executing an `hfence.vvma` with _rs1_=_x0_ and _rs2_=_x0_ suffices to synchronize with respect to the altered interpretation of VS-stage PTEs' PBMT fields for the currently active VMID. @@ -86,14 +86,14 @@ fields: description: | If the `Svadu` extension is implemented, the ADUE bit controls whether hardware updating of PTE A/D bits is enabled for VS-stage address translation. - + When ADUE=1, hardware updating of PTE A/D bits is enabled during VS-stage address translation, and the implementation behaves as though the Svade extension were not implemented for VS-mode address translation. - + When ADUE=0, the implementation behaves as though Svade were implemented for VS-stage address translation. - + If Svadu is not implemented, ADUE is read-only zero. Furthermore, for implementations with the hypervisor extension, henvcfg.ADUE is read-only @@ -104,4 +104,4 @@ fields: reset_value(): | return (implemented?(ExtensionName::Svadu)) ? UNDEFINED_LEGAL : 0; sw_read(): | - return CSR[henvcfg].sw_read()[63:32]; \ No newline at end of file + return CSR[henvcfg].sw_read()[63:32]; diff --git a/arch/csr/H/hgatp.yaml b/arch/csr/H/hgatp.yaml index 01bb120e13..43a84b54a9 100644 --- a/arch/csr/H/hgatp.yaml +++ b/arch/csr/H/hgatp.yaml @@ -225,7 +225,7 @@ fields: return csr_value.PPN; sw_read(): | - if ((CSR[hgatp].MODE == $bits(HgatpMode::Sv32x4)) + if ((CSR[hgatp].MODE == $bits(HgatpMode::Sv32x4)) || (CSR[hgatp].MODE == $bits(HgatpMode::Sv39x4)) || (CSR[hgatp].MODE == $bits(HgatpMode::Sv48x4)) || (CSR[hgatp].MODE == $bits(HgatpMode::Sv57x4))) { @@ -233,4 +233,4 @@ sw_read(): | return $bits(CSR[hgatp]) & ~64'h3; } else { return $bits(CSR[hgatp]); - } \ No newline at end of file + } diff --git a/arch/csr/H/vsatp.yaml b/arch/csr/H/vsatp.yaml index d95e56e45a..fef44032c4 100644 --- a/arch/csr/H/vsatp.yaml +++ b/arch/csr/H/vsatp.yaml @@ -127,7 +127,7 @@ fields: reset_value: UNDEFINED_LEGAL sw_write(csr_value): | if (csr_value.MODE == 0) { - if (virtual_mode?() || IGNORE_INVALID_VSATP_MODE_WRITES_WHEN_V_EQ_ZERO) { + if (virtual_mode?() || IGNORE_INVALID_VSATP_MODE_WRITES_WHEN_V_EQ_ZERO) { # when MODE == Bare, PPN and ASID must be zero if (csr_value.ASID == 0 && csr_value.PPN == 0) { return csr_value.PPN; diff --git a/arch/csr/I/pmpaddrN.layout b/arch/csr/I/pmpaddrN.layout index d42a4cb5cb..076b1d34e8 100644 --- a/arch/csr/I/pmpaddrN.layout +++ b/arch/csr/I/pmpaddrN.layout @@ -1,6 +1,6 @@ # yaml-language-server: $schema=../../../schemas/csr_schema.json -<%- +<%- raise "'pmpaddr_num' must be defined" if pmpaddr_num.nil? pmpcfg_num_32 = (pmpaddr_num / 4) pmpcfg_num_64 = (pmpaddr_num / 8)*2 diff --git a/arch/csr/I/pmpcfg0.yaml b/arch/csr/I/pmpcfg0.yaml index b1a599b023..51714e954a 100644 --- a/arch/csr/I/pmpcfg0.yaml +++ b/arch/csr/I/pmpcfg0.yaml @@ -29,7 +29,7 @@ fields: h! - ! 6:5 ! _Reserved_ Writes shall be ignored. h! A ! 4:3 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -43,7 +43,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -91,7 +91,7 @@ fields: h! - ! 14:13 ! _Reserved_ Writes shall be ignored. h! A ! 12:11 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -105,7 +105,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -153,7 +153,7 @@ fields: h! - ! 22:21 ! _Reserved_ Writes shall be ignored. h! A ! 20:19 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -167,7 +167,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -215,7 +215,7 @@ fields: h! - ! 30:29 ! _Reserved_ Writes shall be ignored. h! A ! 28:27 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -229,7 +229,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -278,7 +278,7 @@ fields: h! - ! 38:37 ! _Reserved_ Writes shall be ignored. h! A ! 36:35 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -292,7 +292,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 34 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 33 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 32 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -341,7 +341,7 @@ fields: h! - ! 46:45 ! _Reserved_ Writes shall be ignored. h! A ! 44:43 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -355,7 +355,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 42 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 41 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 40 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -404,7 +404,7 @@ fields: h! - ! 54:53 ! _Reserved_ Writes shall be ignored. h! A ! 52:51 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -418,7 +418,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 50 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 49 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 48 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -467,7 +467,7 @@ fields: h! - ! 62:61 ! _Reserved_ Writes shall be ignored. h! A ! 60:59 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -481,7 +481,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 58 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 57 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 56 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. diff --git a/arch/csr/I/pmpcfg1.yaml b/arch/csr/I/pmpcfg1.yaml index b4dd1bb588..44e262a696 100644 --- a/arch/csr/I/pmpcfg1.yaml +++ b/arch/csr/I/pmpcfg1.yaml @@ -30,7 +30,7 @@ fields: h! - ! 6:5 ! _Reserved_ Writes shall be ignored. h! A ! 4:3 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -44,7 +44,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -92,7 +92,7 @@ fields: h! - ! 14:13 ! _Reserved_ Writes shall be ignored. h! A ! 12:11 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -106,7 +106,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -154,7 +154,7 @@ fields: h! - ! 22:21 ! _Reserved_ Writes shall be ignored. h! A ! 20:19 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -168,7 +168,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -216,7 +216,7 @@ fields: h! - ! 30:29 ! _Reserved_ Writes shall be ignored. h! A ! 28:27 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -230,7 +230,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. diff --git a/arch/csr/I/pmpcfg10.yaml b/arch/csr/I/pmpcfg10.yaml index b44572844e..aa4343c0fb 100644 --- a/arch/csr/I/pmpcfg10.yaml +++ b/arch/csr/I/pmpcfg10.yaml @@ -29,7 +29,7 @@ fields: h! - ! 6:5 ! _Reserved_ Writes shall be ignored. h! A ! 4:3 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -43,7 +43,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -91,7 +91,7 @@ fields: h! - ! 14:13 ! _Reserved_ Writes shall be ignored. h! A ! 12:11 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -105,7 +105,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -153,7 +153,7 @@ fields: h! - ! 22:21 ! _Reserved_ Writes shall be ignored. h! A ! 20:19 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -167,7 +167,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -215,7 +215,7 @@ fields: h! - ! 30:29 ! _Reserved_ Writes shall be ignored. h! A ! 28:27 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -229,7 +229,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -278,7 +278,7 @@ fields: h! - ! 38:37 ! _Reserved_ Writes shall be ignored. h! A ! 36:35 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -292,7 +292,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 34 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 33 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 32 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -341,7 +341,7 @@ fields: h! - ! 46:45 ! _Reserved_ Writes shall be ignored. h! A ! 44:43 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -355,7 +355,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 42 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 41 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 40 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -404,7 +404,7 @@ fields: h! - ! 54:53 ! _Reserved_ Writes shall be ignored. h! A ! 52:51 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -418,7 +418,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 50 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 49 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 48 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -467,7 +467,7 @@ fields: h! - ! 62:61 ! _Reserved_ Writes shall be ignored. h! A ! 60:59 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -481,7 +481,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 58 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 57 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 56 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. diff --git a/arch/csr/I/pmpcfg11.yaml b/arch/csr/I/pmpcfg11.yaml index cd94a72b14..7ba8d05b68 100644 --- a/arch/csr/I/pmpcfg11.yaml +++ b/arch/csr/I/pmpcfg11.yaml @@ -30,7 +30,7 @@ fields: h! - ! 6:5 ! _Reserved_ Writes shall be ignored. h! A ! 4:3 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -44,7 +44,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -92,7 +92,7 @@ fields: h! - ! 14:13 ! _Reserved_ Writes shall be ignored. h! A ! 12:11 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -106,7 +106,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -154,7 +154,7 @@ fields: h! - ! 22:21 ! _Reserved_ Writes shall be ignored. h! A ! 20:19 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -168,7 +168,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -216,7 +216,7 @@ fields: h! - ! 30:29 ! _Reserved_ Writes shall be ignored. h! A ! 28:27 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -230,7 +230,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. diff --git a/arch/csr/I/pmpcfg12.yaml b/arch/csr/I/pmpcfg12.yaml index fa1e345837..8897f4db98 100644 --- a/arch/csr/I/pmpcfg12.yaml +++ b/arch/csr/I/pmpcfg12.yaml @@ -29,7 +29,7 @@ fields: h! - ! 6:5 ! _Reserved_ Writes shall be ignored. h! A ! 4:3 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -43,7 +43,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -91,7 +91,7 @@ fields: h! - ! 14:13 ! _Reserved_ Writes shall be ignored. h! A ! 12:11 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -105,7 +105,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -153,7 +153,7 @@ fields: h! - ! 22:21 ! _Reserved_ Writes shall be ignored. h! A ! 20:19 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -167,7 +167,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -215,7 +215,7 @@ fields: h! - ! 30:29 ! _Reserved_ Writes shall be ignored. h! A ! 28:27 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -229,7 +229,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -278,7 +278,7 @@ fields: h! - ! 38:37 ! _Reserved_ Writes shall be ignored. h! A ! 36:35 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -292,7 +292,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 34 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 33 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 32 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -341,7 +341,7 @@ fields: h! - ! 46:45 ! _Reserved_ Writes shall be ignored. h! A ! 44:43 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -355,7 +355,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 42 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 41 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 40 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -404,7 +404,7 @@ fields: h! - ! 54:53 ! _Reserved_ Writes shall be ignored. h! A ! 52:51 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -418,7 +418,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 50 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 49 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 48 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -467,7 +467,7 @@ fields: h! - ! 62:61 ! _Reserved_ Writes shall be ignored. h! A ! 60:59 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -481,7 +481,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 58 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 57 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 56 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. diff --git a/arch/csr/I/pmpcfg13.yaml b/arch/csr/I/pmpcfg13.yaml index 207a5aa776..aa151be422 100644 --- a/arch/csr/I/pmpcfg13.yaml +++ b/arch/csr/I/pmpcfg13.yaml @@ -30,7 +30,7 @@ fields: h! - ! 6:5 ! _Reserved_ Writes shall be ignored. h! A ! 4:3 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -44,7 +44,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -92,7 +92,7 @@ fields: h! - ! 14:13 ! _Reserved_ Writes shall be ignored. h! A ! 12:11 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -106,7 +106,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -154,7 +154,7 @@ fields: h! - ! 22:21 ! _Reserved_ Writes shall be ignored. h! A ! 20:19 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -168,7 +168,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -216,7 +216,7 @@ fields: h! - ! 30:29 ! _Reserved_ Writes shall be ignored. h! A ! 28:27 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -230,7 +230,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. diff --git a/arch/csr/I/pmpcfg14.yaml b/arch/csr/I/pmpcfg14.yaml index f17cc62b17..e5c4744d46 100644 --- a/arch/csr/I/pmpcfg14.yaml +++ b/arch/csr/I/pmpcfg14.yaml @@ -29,7 +29,7 @@ fields: h! - ! 6:5 ! _Reserved_ Writes shall be ignored. h! A ! 4:3 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -43,7 +43,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -91,7 +91,7 @@ fields: h! - ! 14:13 ! _Reserved_ Writes shall be ignored. h! A ! 12:11 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -105,7 +105,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -153,7 +153,7 @@ fields: h! - ! 22:21 ! _Reserved_ Writes shall be ignored. h! A ! 20:19 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -167,7 +167,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -215,7 +215,7 @@ fields: h! - ! 30:29 ! _Reserved_ Writes shall be ignored. h! A ! 28:27 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -229,7 +229,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -278,7 +278,7 @@ fields: h! - ! 38:37 ! _Reserved_ Writes shall be ignored. h! A ! 36:35 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -292,7 +292,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 34 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 33 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 32 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -341,7 +341,7 @@ fields: h! - ! 46:45 ! _Reserved_ Writes shall be ignored. h! A ! 44:43 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -355,7 +355,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 42 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 41 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 40 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -404,7 +404,7 @@ fields: h! - ! 54:53 ! _Reserved_ Writes shall be ignored. h! A ! 52:51 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -418,7 +418,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 50 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 49 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 48 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -467,7 +467,7 @@ fields: h! - ! 62:61 ! _Reserved_ Writes shall be ignored. h! A ! 60:59 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -481,7 +481,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 58 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 57 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 56 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. diff --git a/arch/csr/I/pmpcfg15.yaml b/arch/csr/I/pmpcfg15.yaml index 8b267586b5..43454115e7 100644 --- a/arch/csr/I/pmpcfg15.yaml +++ b/arch/csr/I/pmpcfg15.yaml @@ -30,7 +30,7 @@ fields: h! - ! 6:5 ! _Reserved_ Writes shall be ignored. h! A ! 4:3 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -44,7 +44,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -92,7 +92,7 @@ fields: h! - ! 14:13 ! _Reserved_ Writes shall be ignored. h! A ! 12:11 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -106,7 +106,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -154,7 +154,7 @@ fields: h! - ! 22:21 ! _Reserved_ Writes shall be ignored. h! A ! 20:19 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -168,7 +168,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -216,7 +216,7 @@ fields: h! - ! 30:29 ! _Reserved_ Writes shall be ignored. h! A ! 28:27 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -230,7 +230,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. diff --git a/arch/csr/I/pmpcfg2.yaml b/arch/csr/I/pmpcfg2.yaml index 5a502d96bb..bad4210e86 100644 --- a/arch/csr/I/pmpcfg2.yaml +++ b/arch/csr/I/pmpcfg2.yaml @@ -29,7 +29,7 @@ fields: h! - ! 6:5 ! _Reserved_ Writes shall be ignored. h! A ! 4:3 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -43,7 +43,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -91,7 +91,7 @@ fields: h! - ! 14:13 ! _Reserved_ Writes shall be ignored. h! A ! 12:11 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -105,7 +105,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -153,7 +153,7 @@ fields: h! - ! 22:21 ! _Reserved_ Writes shall be ignored. h! A ! 20:19 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -167,7 +167,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -215,7 +215,7 @@ fields: h! - ! 30:29 ! _Reserved_ Writes shall be ignored. h! A ! 28:27 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -229,7 +229,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -278,7 +278,7 @@ fields: h! - ! 38:37 ! _Reserved_ Writes shall be ignored. h! A ! 36:35 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -292,7 +292,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 34 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 33 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 32 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -341,7 +341,7 @@ fields: h! - ! 46:45 ! _Reserved_ Writes shall be ignored. h! A ! 44:43 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -355,7 +355,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 42 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 41 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 40 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -404,7 +404,7 @@ fields: h! - ! 54:53 ! _Reserved_ Writes shall be ignored. h! A ! 52:51 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -418,7 +418,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 50 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 49 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 48 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -467,7 +467,7 @@ fields: h! - ! 62:61 ! _Reserved_ Writes shall be ignored. h! A ! 60:59 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -481,7 +481,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 58 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 57 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 56 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. diff --git a/arch/csr/I/pmpcfg3.yaml b/arch/csr/I/pmpcfg3.yaml index d1a704789f..31f5a48066 100644 --- a/arch/csr/I/pmpcfg3.yaml +++ b/arch/csr/I/pmpcfg3.yaml @@ -30,7 +30,7 @@ fields: h! - ! 6:5 ! _Reserved_ Writes shall be ignored. h! A ! 4:3 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -44,7 +44,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -92,7 +92,7 @@ fields: h! - ! 14:13 ! _Reserved_ Writes shall be ignored. h! A ! 12:11 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -106,7 +106,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -154,7 +154,7 @@ fields: h! - ! 22:21 ! _Reserved_ Writes shall be ignored. h! A ! 20:19 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -168,7 +168,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -216,7 +216,7 @@ fields: h! - ! 30:29 ! _Reserved_ Writes shall be ignored. h! A ! 28:27 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -230,7 +230,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. diff --git a/arch/csr/I/pmpcfg4.yaml b/arch/csr/I/pmpcfg4.yaml index ae6a9c6b55..d55346cc51 100644 --- a/arch/csr/I/pmpcfg4.yaml +++ b/arch/csr/I/pmpcfg4.yaml @@ -29,7 +29,7 @@ fields: h! - ! 6:5 ! _Reserved_ Writes shall be ignored. h! A ! 4:3 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -43,7 +43,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -91,7 +91,7 @@ fields: h! - ! 14:13 ! _Reserved_ Writes shall be ignored. h! A ! 12:11 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -105,7 +105,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -153,7 +153,7 @@ fields: h! - ! 22:21 ! _Reserved_ Writes shall be ignored. h! A ! 20:19 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -167,7 +167,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -215,7 +215,7 @@ fields: h! - ! 30:29 ! _Reserved_ Writes shall be ignored. h! A ! 28:27 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -229,7 +229,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -278,7 +278,7 @@ fields: h! - ! 38:37 ! _Reserved_ Writes shall be ignored. h! A ! 36:35 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -292,7 +292,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 34 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 33 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 32 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -341,7 +341,7 @@ fields: h! - ! 46:45 ! _Reserved_ Writes shall be ignored. h! A ! 44:43 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -355,7 +355,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 42 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 41 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 40 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -404,7 +404,7 @@ fields: h! - ! 54:53 ! _Reserved_ Writes shall be ignored. h! A ! 52:51 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -418,7 +418,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 50 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 49 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 48 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -467,7 +467,7 @@ fields: h! - ! 62:61 ! _Reserved_ Writes shall be ignored. h! A ! 60:59 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -481,7 +481,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 58 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 57 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 56 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. diff --git a/arch/csr/I/pmpcfg5.yaml b/arch/csr/I/pmpcfg5.yaml index 95585e5396..3b9e2477ca 100644 --- a/arch/csr/I/pmpcfg5.yaml +++ b/arch/csr/I/pmpcfg5.yaml @@ -30,7 +30,7 @@ fields: h! - ! 6:5 ! _Reserved_ Writes shall be ignored. h! A ! 4:3 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -44,7 +44,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -92,7 +92,7 @@ fields: h! - ! 14:13 ! _Reserved_ Writes shall be ignored. h! A ! 12:11 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -106,7 +106,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -154,7 +154,7 @@ fields: h! - ! 22:21 ! _Reserved_ Writes shall be ignored. h! A ! 20:19 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -168,7 +168,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -216,7 +216,7 @@ fields: h! - ! 30:29 ! _Reserved_ Writes shall be ignored. h! A ! 28:27 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -230,7 +230,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. diff --git a/arch/csr/I/pmpcfg6.yaml b/arch/csr/I/pmpcfg6.yaml index 6fe859fb69..a7ab336b66 100644 --- a/arch/csr/I/pmpcfg6.yaml +++ b/arch/csr/I/pmpcfg6.yaml @@ -29,7 +29,7 @@ fields: h! - ! 6:5 ! _Reserved_ Writes shall be ignored. h! A ! 4:3 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -43,7 +43,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -91,7 +91,7 @@ fields: h! - ! 14:13 ! _Reserved_ Writes shall be ignored. h! A ! 12:11 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -105,7 +105,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -153,7 +153,7 @@ fields: h! - ! 22:21 ! _Reserved_ Writes shall be ignored. h! A ! 20:19 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -167,7 +167,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -215,7 +215,7 @@ fields: h! - ! 30:29 ! _Reserved_ Writes shall be ignored. h! A ! 28:27 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -229,7 +229,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -278,7 +278,7 @@ fields: h! - ! 38:37 ! _Reserved_ Writes shall be ignored. h! A ! 36:35 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -292,7 +292,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 34 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 33 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 32 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -341,7 +341,7 @@ fields: h! - ! 46:45 ! _Reserved_ Writes shall be ignored. h! A ! 44:43 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -355,7 +355,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 42 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 41 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 40 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -404,7 +404,7 @@ fields: h! - ! 54:53 ! _Reserved_ Writes shall be ignored. h! A ! 52:51 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -418,7 +418,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 50 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 49 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 48 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -467,7 +467,7 @@ fields: h! - ! 62:61 ! _Reserved_ Writes shall be ignored. h! A ! 60:59 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -481,7 +481,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 58 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 57 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 56 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. diff --git a/arch/csr/I/pmpcfg7.yaml b/arch/csr/I/pmpcfg7.yaml index 2639b58700..bebd1871ec 100644 --- a/arch/csr/I/pmpcfg7.yaml +++ b/arch/csr/I/pmpcfg7.yaml @@ -30,7 +30,7 @@ fields: h! - ! 6:5 ! _Reserved_ Writes shall be ignored. h! A ! 4:3 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -44,7 +44,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -92,7 +92,7 @@ fields: h! - ! 14:13 ! _Reserved_ Writes shall be ignored. h! A ! 12:11 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -106,7 +106,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -154,7 +154,7 @@ fields: h! - ! 22:21 ! _Reserved_ Writes shall be ignored. h! A ! 20:19 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -168,7 +168,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -216,7 +216,7 @@ fields: h! - ! 30:29 ! _Reserved_ Writes shall be ignored. h! A ! 28:27 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -230,7 +230,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. diff --git a/arch/csr/I/pmpcfg8.yaml b/arch/csr/I/pmpcfg8.yaml index 7cb54f73c2..fa3b0fbd45 100644 --- a/arch/csr/I/pmpcfg8.yaml +++ b/arch/csr/I/pmpcfg8.yaml @@ -29,7 +29,7 @@ fields: h! - ! 6:5 ! _Reserved_ Writes shall be ignored. h! A ! 4:3 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -43,7 +43,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -91,7 +91,7 @@ fields: h! - ! 14:13 ! _Reserved_ Writes shall be ignored. h! A ! 12:11 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -105,7 +105,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -153,7 +153,7 @@ fields: h! - ! 22:21 ! _Reserved_ Writes shall be ignored. h! A ! 20:19 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -167,7 +167,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -215,7 +215,7 @@ fields: h! - ! 30:29 ! _Reserved_ Writes shall be ignored. h! A ! 28:27 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -229,7 +229,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -278,7 +278,7 @@ fields: h! - ! 38:37 ! _Reserved_ Writes shall be ignored. h! A ! 36:35 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -292,7 +292,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 34 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 33 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 32 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -341,7 +341,7 @@ fields: h! - ! 46:45 ! _Reserved_ Writes shall be ignored. h! A ! 44:43 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -355,7 +355,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 42 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 41 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 40 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -404,7 +404,7 @@ fields: h! - ! 54:53 ! _Reserved_ Writes shall be ignored. h! A ! 52:51 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -418,7 +418,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 50 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 49 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 48 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -467,7 +467,7 @@ fields: h! - ! 62:61 ! _Reserved_ Writes shall be ignored. h! A ! 60:59 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -481,7 +481,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 58 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 57 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 56 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. diff --git a/arch/csr/I/pmpcfg9.yaml b/arch/csr/I/pmpcfg9.yaml index d8daa4a91a..6fccacb66c 100644 --- a/arch/csr/I/pmpcfg9.yaml +++ b/arch/csr/I/pmpcfg9.yaml @@ -30,7 +30,7 @@ fields: h! - ! 6:5 ! _Reserved_ Writes shall be ignored. h! A ! 4:3 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -44,7 +44,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -92,7 +92,7 @@ fields: h! - ! 14:13 ! _Reserved_ Writes shall be ignored. h! A ! 12:11 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -106,7 +106,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -154,7 +154,7 @@ fields: h! - ! 22:21 ! _Reserved_ Writes shall be ignored. h! A ! 20:19 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -168,7 +168,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. @@ -216,7 +216,7 @@ fields: h! - ! 30:29 ! _Reserved_ Writes shall be ignored. h! A ! 28:27 a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -230,7 +230,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. diff --git a/arch/csr/I/pmpcfgN.layout b/arch/csr/I/pmpcfgN.layout index 9c76a61fc6..571f750972 100644 --- a/arch/csr/I/pmpcfgN.layout +++ b/arch/csr/I/pmpcfgN.layout @@ -34,7 +34,7 @@ fields: h! - ! <%= ((i+1)*8)-2 %>:<%= ((i+1)*8)-3 %> ! _Reserved_ Writes shall be ignored. h! A ! <%= ((i+1)*8)-4 %>:<%= ((i+1)*8)-5 %> a! Address matching mode. One of: - + [when="PMP_GRANULARITY < 2"] * *OFF* (0) - Null region (disabled) * *TOR* (1) - Top of range @@ -48,7 +48,7 @@ fields: [when="PMP_GRANULARITY >= 2"] Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - + h! X ! <%= ((i)*8)+2 %> ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. h! W ! <%= ((i)*8)+1 %> ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. h! R ! <%= ((i)*8)+0 %> ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. diff --git a/arch/csr/Zicntr/mcountinhibit.layout b/arch/csr/Zicntr/mcountinhibit.layout index 01d8a4bce1..549b2061e1 100644 --- a/arch/csr/Zicntr/mcountinhibit.layout +++ b/arch/csr/Zicntr/mcountinhibit.layout @@ -74,4 +74,4 @@ fields: return COUNTINHIBIT_EN[<%= hpm_num %>] ? CsrFieldType::RW : CsrFieldType::RO; reset_value(): | return COUNTINHIBIT_EN[<%= hpm_num %>] ? UNDEFINED_LEGAL : 0; - <%- end -%> \ No newline at end of file + <%- end -%> diff --git a/arch/csr/Zihpm/hpmcounter10.yaml b/arch/csr/Zihpm/hpmcounter10.yaml index f88d8c0475..73b4b9c3cb 100644 --- a/arch/csr/Zihpm/hpmcounter10.yaml +++ b/arch/csr/Zihpm/hpmcounter10.yaml @@ -28,10 +28,10 @@ description: | 4+^.>h! `hpmcounter10` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%- elsif ext?(:S) -%> @@ -49,7 +49,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM10`# - ^.>h! `hpmcounter10` behavior + ^.>h! `hpmcounter10` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounter10h.yaml b/arch/csr/Zihpm/hpmcounter10h.yaml index 4f524ae5aa..682f95116c 100644 --- a/arch/csr/Zihpm/hpmcounter10h.yaml +++ b/arch/csr/Zihpm/hpmcounter10h.yaml @@ -20,10 +20,10 @@ description: | 4+^.>h! `hpmcounter10h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/hpmcounter11.yaml b/arch/csr/Zihpm/hpmcounter11.yaml index f0b6df2c06..0cd3adbd9e 100644 --- a/arch/csr/Zihpm/hpmcounter11.yaml +++ b/arch/csr/Zihpm/hpmcounter11.yaml @@ -28,10 +28,10 @@ description: | 4+^.>h! `hpmcounter11` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%- elsif ext?(:S) -%> @@ -49,7 +49,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM11`# - ^.>h! `hpmcounter11` behavior + ^.>h! `hpmcounter11` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounter11h.yaml b/arch/csr/Zihpm/hpmcounter11h.yaml index ae1d606a7a..d710fcfb16 100644 --- a/arch/csr/Zihpm/hpmcounter11h.yaml +++ b/arch/csr/Zihpm/hpmcounter11h.yaml @@ -20,10 +20,10 @@ description: | 4+^.>h! `hpmcounter11h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/hpmcounter12.yaml b/arch/csr/Zihpm/hpmcounter12.yaml index ac643a1684..940be2a1a5 100644 --- a/arch/csr/Zihpm/hpmcounter12.yaml +++ b/arch/csr/Zihpm/hpmcounter12.yaml @@ -28,10 +28,10 @@ description: | 4+^.>h! `hpmcounter12` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%- elsif ext?(:S) -%> @@ -49,7 +49,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM12`# - ^.>h! `hpmcounter12` behavior + ^.>h! `hpmcounter12` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounter12h.yaml b/arch/csr/Zihpm/hpmcounter12h.yaml index 3f4cda485a..da1b608476 100644 --- a/arch/csr/Zihpm/hpmcounter12h.yaml +++ b/arch/csr/Zihpm/hpmcounter12h.yaml @@ -20,10 +20,10 @@ description: | 4+^.>h! `hpmcounter12h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/hpmcounter13.yaml b/arch/csr/Zihpm/hpmcounter13.yaml index 68a8c0e120..251679470a 100644 --- a/arch/csr/Zihpm/hpmcounter13.yaml +++ b/arch/csr/Zihpm/hpmcounter13.yaml @@ -28,10 +28,10 @@ description: | 4+^.>h! `hpmcounter13` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%- elsif ext?(:S) -%> @@ -49,7 +49,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM13`# - ^.>h! `hpmcounter13` behavior + ^.>h! `hpmcounter13` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounter13h.yaml b/arch/csr/Zihpm/hpmcounter13h.yaml index 938204ac07..4f7ad9c11c 100644 --- a/arch/csr/Zihpm/hpmcounter13h.yaml +++ b/arch/csr/Zihpm/hpmcounter13h.yaml @@ -20,10 +20,10 @@ description: | 4+^.>h! `hpmcounter13h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/hpmcounter14.yaml b/arch/csr/Zihpm/hpmcounter14.yaml index c547b8d749..c65d0acd89 100644 --- a/arch/csr/Zihpm/hpmcounter14.yaml +++ b/arch/csr/Zihpm/hpmcounter14.yaml @@ -28,10 +28,10 @@ description: | 4+^.>h! `hpmcounter14` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%- elsif ext?(:S) -%> @@ -49,7 +49,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM14`# - ^.>h! `hpmcounter14` behavior + ^.>h! `hpmcounter14` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounter14h.yaml b/arch/csr/Zihpm/hpmcounter14h.yaml index 79877a08ff..f5da646657 100644 --- a/arch/csr/Zihpm/hpmcounter14h.yaml +++ b/arch/csr/Zihpm/hpmcounter14h.yaml @@ -20,10 +20,10 @@ description: | 4+^.>h! `hpmcounter14h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/hpmcounter15.yaml b/arch/csr/Zihpm/hpmcounter15.yaml index 418b7c3cd5..0a1eeda232 100644 --- a/arch/csr/Zihpm/hpmcounter15.yaml +++ b/arch/csr/Zihpm/hpmcounter15.yaml @@ -28,10 +28,10 @@ description: | 4+^.>h! `hpmcounter15` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%- elsif ext?(:S) -%> @@ -49,7 +49,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM15`# - ^.>h! `hpmcounter15` behavior + ^.>h! `hpmcounter15` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounter15h.yaml b/arch/csr/Zihpm/hpmcounter15h.yaml index bba8da3d12..0349cceaa2 100644 --- a/arch/csr/Zihpm/hpmcounter15h.yaml +++ b/arch/csr/Zihpm/hpmcounter15h.yaml @@ -20,10 +20,10 @@ description: | 4+^.>h! `hpmcounter15h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/hpmcounter16.yaml b/arch/csr/Zihpm/hpmcounter16.yaml index 4c46e4ab6f..fef98c2a27 100644 --- a/arch/csr/Zihpm/hpmcounter16.yaml +++ b/arch/csr/Zihpm/hpmcounter16.yaml @@ -28,10 +28,10 @@ description: | 4+^.>h! `hpmcounter16` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%- elsif ext?(:S) -%> @@ -49,7 +49,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM16`# - ^.>h! `hpmcounter16` behavior + ^.>h! `hpmcounter16` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounter16h.yaml b/arch/csr/Zihpm/hpmcounter16h.yaml index 5e7db6fe5a..350f8f88db 100644 --- a/arch/csr/Zihpm/hpmcounter16h.yaml +++ b/arch/csr/Zihpm/hpmcounter16h.yaml @@ -20,10 +20,10 @@ description: | 4+^.>h! `hpmcounter16h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/hpmcounter17.yaml b/arch/csr/Zihpm/hpmcounter17.yaml index bcc2844fd8..4326683c3c 100644 --- a/arch/csr/Zihpm/hpmcounter17.yaml +++ b/arch/csr/Zihpm/hpmcounter17.yaml @@ -28,10 +28,10 @@ description: | 4+^.>h! `hpmcounter17` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%- elsif ext?(:S) -%> @@ -49,7 +49,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM17`# - ^.>h! `hpmcounter17` behavior + ^.>h! `hpmcounter17` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounter17h.yaml b/arch/csr/Zihpm/hpmcounter17h.yaml index de64d29157..7d77d8dbad 100644 --- a/arch/csr/Zihpm/hpmcounter17h.yaml +++ b/arch/csr/Zihpm/hpmcounter17h.yaml @@ -20,10 +20,10 @@ description: | 4+^.>h! `hpmcounter17h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/hpmcounter18.yaml b/arch/csr/Zihpm/hpmcounter18.yaml index 35219de64a..365ea88897 100644 --- a/arch/csr/Zihpm/hpmcounter18.yaml +++ b/arch/csr/Zihpm/hpmcounter18.yaml @@ -28,10 +28,10 @@ description: | 4+^.>h! `hpmcounter18` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%- elsif ext?(:S) -%> @@ -49,7 +49,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM18`# - ^.>h! `hpmcounter18` behavior + ^.>h! `hpmcounter18` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounter18h.yaml b/arch/csr/Zihpm/hpmcounter18h.yaml index 794dddb2b2..1714bddddb 100644 --- a/arch/csr/Zihpm/hpmcounter18h.yaml +++ b/arch/csr/Zihpm/hpmcounter18h.yaml @@ -20,10 +20,10 @@ description: | 4+^.>h! `hpmcounter18h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/hpmcounter19.yaml b/arch/csr/Zihpm/hpmcounter19.yaml index e1e9e87144..abeb3c0ae9 100644 --- a/arch/csr/Zihpm/hpmcounter19.yaml +++ b/arch/csr/Zihpm/hpmcounter19.yaml @@ -28,10 +28,10 @@ description: | 4+^.>h! `hpmcounter19` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%- elsif ext?(:S) -%> @@ -49,7 +49,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM19`# - ^.>h! `hpmcounter19` behavior + ^.>h! `hpmcounter19` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounter19h.yaml b/arch/csr/Zihpm/hpmcounter19h.yaml index 84f6a83396..fe8d946773 100644 --- a/arch/csr/Zihpm/hpmcounter19h.yaml +++ b/arch/csr/Zihpm/hpmcounter19h.yaml @@ -20,10 +20,10 @@ description: | 4+^.>h! `hpmcounter19h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/hpmcounter20.yaml b/arch/csr/Zihpm/hpmcounter20.yaml index 5db4a0a997..a926406054 100644 --- a/arch/csr/Zihpm/hpmcounter20.yaml +++ b/arch/csr/Zihpm/hpmcounter20.yaml @@ -28,10 +28,10 @@ description: | 4+^.>h! `hpmcounter20` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%- elsif ext?(:S) -%> @@ -49,7 +49,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM20`# - ^.>h! `hpmcounter20` behavior + ^.>h! `hpmcounter20` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounter20h.yaml b/arch/csr/Zihpm/hpmcounter20h.yaml index 692e695bec..db31015b87 100644 --- a/arch/csr/Zihpm/hpmcounter20h.yaml +++ b/arch/csr/Zihpm/hpmcounter20h.yaml @@ -20,10 +20,10 @@ description: | 4+^.>h! `hpmcounter20h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/hpmcounter21.yaml b/arch/csr/Zihpm/hpmcounter21.yaml index ac6a447729..3d8ba93b26 100644 --- a/arch/csr/Zihpm/hpmcounter21.yaml +++ b/arch/csr/Zihpm/hpmcounter21.yaml @@ -28,10 +28,10 @@ description: | 4+^.>h! `hpmcounter21` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%- elsif ext?(:S) -%> @@ -49,7 +49,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM21`# - ^.>h! `hpmcounter21` behavior + ^.>h! `hpmcounter21` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounter21h.yaml b/arch/csr/Zihpm/hpmcounter21h.yaml index 6c6cd2838b..57db30d76e 100644 --- a/arch/csr/Zihpm/hpmcounter21h.yaml +++ b/arch/csr/Zihpm/hpmcounter21h.yaml @@ -20,10 +20,10 @@ description: | 4+^.>h! `hpmcounter21h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/hpmcounter22.yaml b/arch/csr/Zihpm/hpmcounter22.yaml index c422add0db..a2db1a4615 100644 --- a/arch/csr/Zihpm/hpmcounter22.yaml +++ b/arch/csr/Zihpm/hpmcounter22.yaml @@ -28,10 +28,10 @@ description: | 4+^.>h! `hpmcounter22` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%- elsif ext?(:S) -%> @@ -49,7 +49,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM22`# - ^.>h! `hpmcounter22` behavior + ^.>h! `hpmcounter22` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounter22h.yaml b/arch/csr/Zihpm/hpmcounter22h.yaml index f67e7df7a0..c6f5555fc6 100644 --- a/arch/csr/Zihpm/hpmcounter22h.yaml +++ b/arch/csr/Zihpm/hpmcounter22h.yaml @@ -20,10 +20,10 @@ description: | 4+^.>h! `hpmcounter22h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/hpmcounter23.yaml b/arch/csr/Zihpm/hpmcounter23.yaml index 600270bd66..e8c4b5ff4b 100644 --- a/arch/csr/Zihpm/hpmcounter23.yaml +++ b/arch/csr/Zihpm/hpmcounter23.yaml @@ -28,10 +28,10 @@ description: | 4+^.>h! `hpmcounter23` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%- elsif ext?(:S) -%> @@ -49,7 +49,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM23`# - ^.>h! `hpmcounter23` behavior + ^.>h! `hpmcounter23` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounter23h.yaml b/arch/csr/Zihpm/hpmcounter23h.yaml index fab756b4c8..e6b261d231 100644 --- a/arch/csr/Zihpm/hpmcounter23h.yaml +++ b/arch/csr/Zihpm/hpmcounter23h.yaml @@ -20,10 +20,10 @@ description: | 4+^.>h! `hpmcounter23h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/hpmcounter24.yaml b/arch/csr/Zihpm/hpmcounter24.yaml index e30a48ff4e..5a214615d7 100644 --- a/arch/csr/Zihpm/hpmcounter24.yaml +++ b/arch/csr/Zihpm/hpmcounter24.yaml @@ -28,10 +28,10 @@ description: | 4+^.>h! `hpmcounter24` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%- elsif ext?(:S) -%> @@ -49,7 +49,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM24`# - ^.>h! `hpmcounter24` behavior + ^.>h! `hpmcounter24` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounter24h.yaml b/arch/csr/Zihpm/hpmcounter24h.yaml index 9d255c1faa..9602adfb47 100644 --- a/arch/csr/Zihpm/hpmcounter24h.yaml +++ b/arch/csr/Zihpm/hpmcounter24h.yaml @@ -20,10 +20,10 @@ description: | 4+^.>h! `hpmcounter24h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/hpmcounter25.yaml b/arch/csr/Zihpm/hpmcounter25.yaml index 0022adae08..d10352ccd3 100644 --- a/arch/csr/Zihpm/hpmcounter25.yaml +++ b/arch/csr/Zihpm/hpmcounter25.yaml @@ -28,10 +28,10 @@ description: | 4+^.>h! `hpmcounter25` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%- elsif ext?(:S) -%> @@ -49,7 +49,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM25`# - ^.>h! `hpmcounter25` behavior + ^.>h! `hpmcounter25` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounter25h.yaml b/arch/csr/Zihpm/hpmcounter25h.yaml index a91731b4b0..f77f95c9bf 100644 --- a/arch/csr/Zihpm/hpmcounter25h.yaml +++ b/arch/csr/Zihpm/hpmcounter25h.yaml @@ -20,10 +20,10 @@ description: | 4+^.>h! `hpmcounter25h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/hpmcounter26.yaml b/arch/csr/Zihpm/hpmcounter26.yaml index e018ddd3e8..778d77da55 100644 --- a/arch/csr/Zihpm/hpmcounter26.yaml +++ b/arch/csr/Zihpm/hpmcounter26.yaml @@ -28,10 +28,10 @@ description: | 4+^.>h! `hpmcounter26` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%- elsif ext?(:S) -%> @@ -49,7 +49,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM26`# - ^.>h! `hpmcounter26` behavior + ^.>h! `hpmcounter26` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounter26h.yaml b/arch/csr/Zihpm/hpmcounter26h.yaml index 4394957466..3468664027 100644 --- a/arch/csr/Zihpm/hpmcounter26h.yaml +++ b/arch/csr/Zihpm/hpmcounter26h.yaml @@ -20,10 +20,10 @@ description: | 4+^.>h! `hpmcounter26h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/hpmcounter27.yaml b/arch/csr/Zihpm/hpmcounter27.yaml index f4c4bfa213..1e3014f54f 100644 --- a/arch/csr/Zihpm/hpmcounter27.yaml +++ b/arch/csr/Zihpm/hpmcounter27.yaml @@ -28,10 +28,10 @@ description: | 4+^.>h! `hpmcounter27` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%- elsif ext?(:S) -%> @@ -49,7 +49,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM27`# - ^.>h! `hpmcounter27` behavior + ^.>h! `hpmcounter27` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounter27h.yaml b/arch/csr/Zihpm/hpmcounter27h.yaml index 77ebfae20b..bf683b7f9a 100644 --- a/arch/csr/Zihpm/hpmcounter27h.yaml +++ b/arch/csr/Zihpm/hpmcounter27h.yaml @@ -20,10 +20,10 @@ description: | 4+^.>h! `hpmcounter27h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/hpmcounter28.yaml b/arch/csr/Zihpm/hpmcounter28.yaml index 04e32bed25..f0359b73c1 100644 --- a/arch/csr/Zihpm/hpmcounter28.yaml +++ b/arch/csr/Zihpm/hpmcounter28.yaml @@ -28,10 +28,10 @@ description: | 4+^.>h! `hpmcounter28` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%- elsif ext?(:S) -%> @@ -49,7 +49,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM28`# - ^.>h! `hpmcounter28` behavior + ^.>h! `hpmcounter28` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounter28h.yaml b/arch/csr/Zihpm/hpmcounter28h.yaml index bd79376a89..635ba7b1ef 100644 --- a/arch/csr/Zihpm/hpmcounter28h.yaml +++ b/arch/csr/Zihpm/hpmcounter28h.yaml @@ -20,10 +20,10 @@ description: | 4+^.>h! `hpmcounter28h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/hpmcounter29.yaml b/arch/csr/Zihpm/hpmcounter29.yaml index 504ce545a7..479cae0025 100644 --- a/arch/csr/Zihpm/hpmcounter29.yaml +++ b/arch/csr/Zihpm/hpmcounter29.yaml @@ -28,10 +28,10 @@ description: | 4+^.>h! `hpmcounter29` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%- elsif ext?(:S) -%> @@ -49,7 +49,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM29`# - ^.>h! `hpmcounter29` behavior + ^.>h! `hpmcounter29` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounter29h.yaml b/arch/csr/Zihpm/hpmcounter29h.yaml index 708c0095bf..7c76ca6245 100644 --- a/arch/csr/Zihpm/hpmcounter29h.yaml +++ b/arch/csr/Zihpm/hpmcounter29h.yaml @@ -20,10 +20,10 @@ description: | 4+^.>h! `hpmcounter29h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/hpmcounter3.yaml b/arch/csr/Zihpm/hpmcounter3.yaml index e0ef755ed6..99907b9b81 100644 --- a/arch/csr/Zihpm/hpmcounter3.yaml +++ b/arch/csr/Zihpm/hpmcounter3.yaml @@ -28,10 +28,10 @@ description: | 4+^.>h! `hpmcounter3` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%- elsif ext?(:S) -%> @@ -49,7 +49,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM3`# - ^.>h! `hpmcounter3` behavior + ^.>h! `hpmcounter3` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounter30.yaml b/arch/csr/Zihpm/hpmcounter30.yaml index 205e9d6f94..855b1087c2 100644 --- a/arch/csr/Zihpm/hpmcounter30.yaml +++ b/arch/csr/Zihpm/hpmcounter30.yaml @@ -28,10 +28,10 @@ description: | 4+^.>h! `hpmcounter30` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%- elsif ext?(:S) -%> @@ -49,7 +49,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM30`# - ^.>h! `hpmcounter30` behavior + ^.>h! `hpmcounter30` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounter30h.yaml b/arch/csr/Zihpm/hpmcounter30h.yaml index f80aca0dbd..10e30fa681 100644 --- a/arch/csr/Zihpm/hpmcounter30h.yaml +++ b/arch/csr/Zihpm/hpmcounter30h.yaml @@ -20,10 +20,10 @@ description: | 4+^.>h! `hpmcounter30h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/hpmcounter31.yaml b/arch/csr/Zihpm/hpmcounter31.yaml index 8682dd896a..64aa6a6643 100644 --- a/arch/csr/Zihpm/hpmcounter31.yaml +++ b/arch/csr/Zihpm/hpmcounter31.yaml @@ -28,10 +28,10 @@ description: | 4+^.>h! `hpmcounter31` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%- elsif ext?(:S) -%> @@ -49,7 +49,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM31`# - ^.>h! `hpmcounter31` behavior + ^.>h! `hpmcounter31` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounter31h.yaml b/arch/csr/Zihpm/hpmcounter31h.yaml index b842023553..07bf78fe64 100644 --- a/arch/csr/Zihpm/hpmcounter31h.yaml +++ b/arch/csr/Zihpm/hpmcounter31h.yaml @@ -20,10 +20,10 @@ description: | 4+^.>h! `hpmcounter31h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/hpmcounter3h.yaml b/arch/csr/Zihpm/hpmcounter3h.yaml index 11acfe0f8c..ea664cc42c 100644 --- a/arch/csr/Zihpm/hpmcounter3h.yaml +++ b/arch/csr/Zihpm/hpmcounter3h.yaml @@ -20,10 +20,10 @@ description: | 4+^.>h! `hpmcounter3h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/hpmcounter4.yaml b/arch/csr/Zihpm/hpmcounter4.yaml index 0947a5f150..06d2d04cb0 100644 --- a/arch/csr/Zihpm/hpmcounter4.yaml +++ b/arch/csr/Zihpm/hpmcounter4.yaml @@ -28,10 +28,10 @@ description: | 4+^.>h! `hpmcounter4` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%- elsif ext?(:S) -%> @@ -49,7 +49,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM4`# - ^.>h! `hpmcounter4` behavior + ^.>h! `hpmcounter4` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounter4h.yaml b/arch/csr/Zihpm/hpmcounter4h.yaml index b5920dd610..47951185aa 100644 --- a/arch/csr/Zihpm/hpmcounter4h.yaml +++ b/arch/csr/Zihpm/hpmcounter4h.yaml @@ -20,10 +20,10 @@ description: | 4+^.>h! `hpmcounter4h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/hpmcounter5.yaml b/arch/csr/Zihpm/hpmcounter5.yaml index 93c4ab78fc..ff0ce06fa8 100644 --- a/arch/csr/Zihpm/hpmcounter5.yaml +++ b/arch/csr/Zihpm/hpmcounter5.yaml @@ -28,10 +28,10 @@ description: | 4+^.>h! `hpmcounter5` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%- elsif ext?(:S) -%> @@ -49,7 +49,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM5`# - ^.>h! `hpmcounter5` behavior + ^.>h! `hpmcounter5` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounter5h.yaml b/arch/csr/Zihpm/hpmcounter5h.yaml index f637926f6f..354e4465af 100644 --- a/arch/csr/Zihpm/hpmcounter5h.yaml +++ b/arch/csr/Zihpm/hpmcounter5h.yaml @@ -20,10 +20,10 @@ description: | 4+^.>h! `hpmcounter5h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/hpmcounter6.yaml b/arch/csr/Zihpm/hpmcounter6.yaml index ad2646d52b..dd153ff5ab 100644 --- a/arch/csr/Zihpm/hpmcounter6.yaml +++ b/arch/csr/Zihpm/hpmcounter6.yaml @@ -28,10 +28,10 @@ description: | 4+^.>h! `hpmcounter6` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%- elsif ext?(:S) -%> @@ -49,7 +49,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM6`# - ^.>h! `hpmcounter6` behavior + ^.>h! `hpmcounter6` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounter6h.yaml b/arch/csr/Zihpm/hpmcounter6h.yaml index 83996abc56..238c4e6288 100644 --- a/arch/csr/Zihpm/hpmcounter6h.yaml +++ b/arch/csr/Zihpm/hpmcounter6h.yaml @@ -20,10 +20,10 @@ description: | 4+^.>h! `hpmcounter6h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/hpmcounter7.yaml b/arch/csr/Zihpm/hpmcounter7.yaml index 103aa95ff8..b350ebbd64 100644 --- a/arch/csr/Zihpm/hpmcounter7.yaml +++ b/arch/csr/Zihpm/hpmcounter7.yaml @@ -28,10 +28,10 @@ description: | 4+^.>h! `hpmcounter7` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%- elsif ext?(:S) -%> @@ -49,7 +49,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM7`# - ^.>h! `hpmcounter7` behavior + ^.>h! `hpmcounter7` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounter7h.yaml b/arch/csr/Zihpm/hpmcounter7h.yaml index 37ee38eab5..27b2468c83 100644 --- a/arch/csr/Zihpm/hpmcounter7h.yaml +++ b/arch/csr/Zihpm/hpmcounter7h.yaml @@ -20,10 +20,10 @@ description: | 4+^.>h! `hpmcounter7h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/hpmcounter8.yaml b/arch/csr/Zihpm/hpmcounter8.yaml index 3a10004723..7c4a50d312 100644 --- a/arch/csr/Zihpm/hpmcounter8.yaml +++ b/arch/csr/Zihpm/hpmcounter8.yaml @@ -28,10 +28,10 @@ description: | 4+^.>h! `hpmcounter8` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%- elsif ext?(:S) -%> @@ -49,7 +49,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM8`# - ^.>h! `hpmcounter8` behavior + ^.>h! `hpmcounter8` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounter8h.yaml b/arch/csr/Zihpm/hpmcounter8h.yaml index bbba142d7b..5eb7fcf058 100644 --- a/arch/csr/Zihpm/hpmcounter8h.yaml +++ b/arch/csr/Zihpm/hpmcounter8h.yaml @@ -20,10 +20,10 @@ description: | 4+^.>h! `hpmcounter8h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/hpmcounter9.yaml b/arch/csr/Zihpm/hpmcounter9.yaml index 1a62dc3576..91fbcf184a 100644 --- a/arch/csr/Zihpm/hpmcounter9.yaml +++ b/arch/csr/Zihpm/hpmcounter9.yaml @@ -28,10 +28,10 @@ description: | 4+^.>h! `hpmcounter9` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%- elsif ext?(:S) -%> @@ -49,7 +49,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM9`# - ^.>h! `hpmcounter9` behavior + ^.>h! `hpmcounter9` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounter9h.yaml b/arch/csr/Zihpm/hpmcounter9h.yaml index daa0da0127..8a9e203c77 100644 --- a/arch/csr/Zihpm/hpmcounter9h.yaml +++ b/arch/csr/Zihpm/hpmcounter9h.yaml @@ -20,10 +20,10 @@ description: | 4+^.>h! `hpmcounter9h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/hpmcounterN.layout b/arch/csr/Zihpm/hpmcounterN.layout index feba9813cf..c273c374ec 100644 --- a/arch/csr/Zihpm/hpmcounterN.layout +++ b/arch/csr/Zihpm/hpmcounterN.layout @@ -26,10 +26,10 @@ description: | 4+^.>h! `hpmcounter<%= hpm_num %>` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== <%%- elsif ext?(:S) -%> @@ -47,7 +47,7 @@ description: | [%autowidth,cols="1,1",separator="!"] !=== .2+h![.rotate]#`mcounteren.HPM<%= hpm_num %>`# - ^.>h! `hpmcounter<%= hpm_num %>` behavior + ^.>h! `hpmcounter<%= hpm_num %>` behavior .^h! U-mode ! 0 ! `IllegalInstruction` diff --git a/arch/csr/Zihpm/hpmcounterNh.layout b/arch/csr/Zihpm/hpmcounterNh.layout index 8a62747277..b573d35b80 100644 --- a/arch/csr/Zihpm/hpmcounterNh.layout +++ b/arch/csr/Zihpm/hpmcounterNh.layout @@ -18,10 +18,10 @@ description: | 4+^.>h! `hpmcounter<%= hpm_num %>h` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/Zihpm/mhpmcounter10h.yaml b/arch/csr/Zihpm/mhpmcounter10h.yaml index d0921b1086..d020a06c0f 100644 --- a/arch/csr/Zihpm/mhpmcounter10h.yaml +++ b/arch/csr/Zihpm/mhpmcounter10h.yaml @@ -28,4 +28,4 @@ sw_read(): | return read_hpm_counter(10)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/Zihpm/mhpmcounter11h.yaml b/arch/csr/Zihpm/mhpmcounter11h.yaml index 4801751676..51e1157b1f 100644 --- a/arch/csr/Zihpm/mhpmcounter11h.yaml +++ b/arch/csr/Zihpm/mhpmcounter11h.yaml @@ -28,4 +28,4 @@ sw_read(): | return read_hpm_counter(11)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/Zihpm/mhpmcounter12h.yaml b/arch/csr/Zihpm/mhpmcounter12h.yaml index 9b376187f9..552478c7b9 100644 --- a/arch/csr/Zihpm/mhpmcounter12h.yaml +++ b/arch/csr/Zihpm/mhpmcounter12h.yaml @@ -28,4 +28,4 @@ sw_read(): | return read_hpm_counter(12)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/Zihpm/mhpmcounter13h.yaml b/arch/csr/Zihpm/mhpmcounter13h.yaml index 2fa48f8d3c..de931ede39 100644 --- a/arch/csr/Zihpm/mhpmcounter13h.yaml +++ b/arch/csr/Zihpm/mhpmcounter13h.yaml @@ -28,4 +28,4 @@ sw_read(): | return read_hpm_counter(13)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/Zihpm/mhpmcounter14h.yaml b/arch/csr/Zihpm/mhpmcounter14h.yaml index 02a78cf6f3..fad4f5d6ed 100644 --- a/arch/csr/Zihpm/mhpmcounter14h.yaml +++ b/arch/csr/Zihpm/mhpmcounter14h.yaml @@ -28,4 +28,4 @@ sw_read(): | return read_hpm_counter(14)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/Zihpm/mhpmcounter15h.yaml b/arch/csr/Zihpm/mhpmcounter15h.yaml index 6c2694f667..56080a49ce 100644 --- a/arch/csr/Zihpm/mhpmcounter15h.yaml +++ b/arch/csr/Zihpm/mhpmcounter15h.yaml @@ -28,4 +28,4 @@ sw_read(): | return read_hpm_counter(15)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/Zihpm/mhpmcounter16h.yaml b/arch/csr/Zihpm/mhpmcounter16h.yaml index 2efc26bc17..040cf26b59 100644 --- a/arch/csr/Zihpm/mhpmcounter16h.yaml +++ b/arch/csr/Zihpm/mhpmcounter16h.yaml @@ -28,4 +28,4 @@ sw_read(): | return read_hpm_counter(16)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/Zihpm/mhpmcounter17h.yaml b/arch/csr/Zihpm/mhpmcounter17h.yaml index 6983f5a66e..913a812714 100644 --- a/arch/csr/Zihpm/mhpmcounter17h.yaml +++ b/arch/csr/Zihpm/mhpmcounter17h.yaml @@ -28,4 +28,4 @@ sw_read(): | return read_hpm_counter(17)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/Zihpm/mhpmcounter18h.yaml b/arch/csr/Zihpm/mhpmcounter18h.yaml index 2c55efb869..b8dd73f0bd 100644 --- a/arch/csr/Zihpm/mhpmcounter18h.yaml +++ b/arch/csr/Zihpm/mhpmcounter18h.yaml @@ -28,4 +28,4 @@ sw_read(): | return read_hpm_counter(18)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/Zihpm/mhpmcounter19h.yaml b/arch/csr/Zihpm/mhpmcounter19h.yaml index 6810df997a..306eea43cc 100644 --- a/arch/csr/Zihpm/mhpmcounter19h.yaml +++ b/arch/csr/Zihpm/mhpmcounter19h.yaml @@ -28,4 +28,4 @@ sw_read(): | return read_hpm_counter(19)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/Zihpm/mhpmcounter20h.yaml b/arch/csr/Zihpm/mhpmcounter20h.yaml index 00373df919..7366268dec 100644 --- a/arch/csr/Zihpm/mhpmcounter20h.yaml +++ b/arch/csr/Zihpm/mhpmcounter20h.yaml @@ -28,4 +28,4 @@ sw_read(): | return read_hpm_counter(20)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/Zihpm/mhpmcounter21h.yaml b/arch/csr/Zihpm/mhpmcounter21h.yaml index e1759442d0..8686eab27c 100644 --- a/arch/csr/Zihpm/mhpmcounter21h.yaml +++ b/arch/csr/Zihpm/mhpmcounter21h.yaml @@ -28,4 +28,4 @@ sw_read(): | return read_hpm_counter(21)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/Zihpm/mhpmcounter22h.yaml b/arch/csr/Zihpm/mhpmcounter22h.yaml index de6284ce5e..f4049e79c8 100644 --- a/arch/csr/Zihpm/mhpmcounter22h.yaml +++ b/arch/csr/Zihpm/mhpmcounter22h.yaml @@ -28,4 +28,4 @@ sw_read(): | return read_hpm_counter(22)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/Zihpm/mhpmcounter23h.yaml b/arch/csr/Zihpm/mhpmcounter23h.yaml index 5208fa4719..9152e9d9a2 100644 --- a/arch/csr/Zihpm/mhpmcounter23h.yaml +++ b/arch/csr/Zihpm/mhpmcounter23h.yaml @@ -28,4 +28,4 @@ sw_read(): | return read_hpm_counter(23)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/Zihpm/mhpmcounter24h.yaml b/arch/csr/Zihpm/mhpmcounter24h.yaml index 76808b2a66..55bdde30af 100644 --- a/arch/csr/Zihpm/mhpmcounter24h.yaml +++ b/arch/csr/Zihpm/mhpmcounter24h.yaml @@ -28,4 +28,4 @@ sw_read(): | return read_hpm_counter(24)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/Zihpm/mhpmcounter25h.yaml b/arch/csr/Zihpm/mhpmcounter25h.yaml index 1829aca091..3d136816be 100644 --- a/arch/csr/Zihpm/mhpmcounter25h.yaml +++ b/arch/csr/Zihpm/mhpmcounter25h.yaml @@ -28,4 +28,4 @@ sw_read(): | return read_hpm_counter(25)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/Zihpm/mhpmcounter26h.yaml b/arch/csr/Zihpm/mhpmcounter26h.yaml index 3ea26055dd..b98d78a8cc 100644 --- a/arch/csr/Zihpm/mhpmcounter26h.yaml +++ b/arch/csr/Zihpm/mhpmcounter26h.yaml @@ -28,4 +28,4 @@ sw_read(): | return read_hpm_counter(26)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/Zihpm/mhpmcounter27h.yaml b/arch/csr/Zihpm/mhpmcounter27h.yaml index 750305e5a9..b45fd8ebe7 100644 --- a/arch/csr/Zihpm/mhpmcounter27h.yaml +++ b/arch/csr/Zihpm/mhpmcounter27h.yaml @@ -28,4 +28,4 @@ sw_read(): | return read_hpm_counter(27)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/Zihpm/mhpmcounter28h.yaml b/arch/csr/Zihpm/mhpmcounter28h.yaml index d210f2a60c..2167cc2e9c 100644 --- a/arch/csr/Zihpm/mhpmcounter28h.yaml +++ b/arch/csr/Zihpm/mhpmcounter28h.yaml @@ -28,4 +28,4 @@ sw_read(): | return read_hpm_counter(28)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/Zihpm/mhpmcounter29h.yaml b/arch/csr/Zihpm/mhpmcounter29h.yaml index 5f493f5903..e924c64607 100644 --- a/arch/csr/Zihpm/mhpmcounter29h.yaml +++ b/arch/csr/Zihpm/mhpmcounter29h.yaml @@ -28,4 +28,4 @@ sw_read(): | return read_hpm_counter(29)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/Zihpm/mhpmcounter30h.yaml b/arch/csr/Zihpm/mhpmcounter30h.yaml index 387568c415..603f63f891 100644 --- a/arch/csr/Zihpm/mhpmcounter30h.yaml +++ b/arch/csr/Zihpm/mhpmcounter30h.yaml @@ -28,4 +28,4 @@ sw_read(): | return read_hpm_counter(30)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/Zihpm/mhpmcounter31h.yaml b/arch/csr/Zihpm/mhpmcounter31h.yaml index 8d4922a732..da1da7a17e 100644 --- a/arch/csr/Zihpm/mhpmcounter31h.yaml +++ b/arch/csr/Zihpm/mhpmcounter31h.yaml @@ -28,4 +28,4 @@ sw_read(): | return read_hpm_counter(31)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/Zihpm/mhpmcounter3h.yaml b/arch/csr/Zihpm/mhpmcounter3h.yaml index bd9d3e556f..cd0e5dd7c2 100644 --- a/arch/csr/Zihpm/mhpmcounter3h.yaml +++ b/arch/csr/Zihpm/mhpmcounter3h.yaml @@ -28,4 +28,4 @@ sw_read(): | return read_hpm_counter(3)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/Zihpm/mhpmcounter4h.yaml b/arch/csr/Zihpm/mhpmcounter4h.yaml index 94ee0f9260..ca888f72ee 100644 --- a/arch/csr/Zihpm/mhpmcounter4h.yaml +++ b/arch/csr/Zihpm/mhpmcounter4h.yaml @@ -28,4 +28,4 @@ sw_read(): | return read_hpm_counter(4)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/Zihpm/mhpmcounter5h.yaml b/arch/csr/Zihpm/mhpmcounter5h.yaml index 87008b5f83..88ef7737f5 100644 --- a/arch/csr/Zihpm/mhpmcounter5h.yaml +++ b/arch/csr/Zihpm/mhpmcounter5h.yaml @@ -28,4 +28,4 @@ sw_read(): | return read_hpm_counter(5)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/Zihpm/mhpmcounter6h.yaml b/arch/csr/Zihpm/mhpmcounter6h.yaml index c51a0f487a..6907ddba67 100644 --- a/arch/csr/Zihpm/mhpmcounter6h.yaml +++ b/arch/csr/Zihpm/mhpmcounter6h.yaml @@ -28,4 +28,4 @@ sw_read(): | return read_hpm_counter(6)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/Zihpm/mhpmcounter7h.yaml b/arch/csr/Zihpm/mhpmcounter7h.yaml index 0d05d9c9cd..08aa55fb7b 100644 --- a/arch/csr/Zihpm/mhpmcounter7h.yaml +++ b/arch/csr/Zihpm/mhpmcounter7h.yaml @@ -28,4 +28,4 @@ sw_read(): | return read_hpm_counter(7)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/Zihpm/mhpmcounter8h.yaml b/arch/csr/Zihpm/mhpmcounter8h.yaml index 0df82e412f..8ae9a5aed6 100644 --- a/arch/csr/Zihpm/mhpmcounter8h.yaml +++ b/arch/csr/Zihpm/mhpmcounter8h.yaml @@ -28,4 +28,4 @@ sw_read(): | return read_hpm_counter(8)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/Zihpm/mhpmcounter9h.yaml b/arch/csr/Zihpm/mhpmcounter9h.yaml index b3bb95d7c3..9081f053bb 100644 --- a/arch/csr/Zihpm/mhpmcounter9h.yaml +++ b/arch/csr/Zihpm/mhpmcounter9h.yaml @@ -28,4 +28,4 @@ sw_read(): | return read_hpm_counter(9)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/Zihpm/mhpmcounterNh.layout b/arch/csr/Zihpm/mhpmcounterNh.layout index b9f4b2f14c..4c9c42f16d 100644 --- a/arch/csr/Zihpm/mhpmcounterNh.layout +++ b/arch/csr/Zihpm/mhpmcounterNh.layout @@ -26,4 +26,4 @@ sw_read(): | return read_hpm_counter(<%= hpm_num %>)[63:32]; } else { return 0; - } \ No newline at end of file + } diff --git a/arch/csr/cycle.yaml b/arch/csr/cycle.yaml index 50084c604e..99824ed6e9 100644 --- a/arch/csr/cycle.yaml +++ b/arch/csr/cycle.yaml @@ -16,10 +16,10 @@ description: | 4+^.>h! `cycle` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/cycleh.yaml b/arch/csr/cycleh.yaml index 2c2f664d46..720e4b3417 100644 --- a/arch/csr/cycleh.yaml +++ b/arch/csr/cycleh.yaml @@ -17,10 +17,10 @@ description: | 4+^.>h! `cycle` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U diff --git a/arch/csr/hstatus.yaml b/arch/csr/hstatus.yaml index eb2c5940d2..c14c193312 100644 --- a/arch/csr/hstatus.yaml +++ b/arch/csr/hstatus.yaml @@ -90,7 +90,7 @@ fields: amount of time (which can be 0). When both `hstatus.VTW` and `mstatus.TW` are clear, a `wfi` instruction - executes in VS-mode without a timeout period. + executes in VS-mode without a timeout period. The `wfi` instruction is also affected by `mstatus.TW`, as shown below: @@ -99,7 +99,7 @@ fields: .2+! [.rotate]#`mstatus.TW`# .2+! [.rotate]#`hstatus.VTW`# 4+^.>! `wfi` behavior h! HS-mode h! U-mode h! VS-mode h! VU-mode - ! 0 ! 0 ! Wait ! Trap (I) ! Wait ! Trap (V) + ! 0 ! 0 ! Wait ! Trap (I) ! Wait ! Trap (V) ! 0 ! 1 ! Wait ! Trap (I) ! Trap (V) ! Trap (V) ! 1 ! - ! Trap (I) ! Trap (I) ! Trap (I) ! Trap (I) diff --git a/arch/csr/instret.yaml b/arch/csr/instret.yaml index 7f45d01603..779f47c5f3 100644 --- a/arch/csr/instret.yaml +++ b/arch/csr/instret.yaml @@ -16,10 +16,10 @@ description: | 4+^.>h! `instret` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U @@ -68,4 +68,4 @@ sw_read(): | } } - return CSR[minstret].COUNT; \ No newline at end of file + return CSR[minstret].COUNT; diff --git a/arch/csr/instreth.yaml b/arch/csr/instreth.yaml index f4a610ccbc..7a850f01a1 100644 --- a/arch/csr/instreth.yaml +++ b/arch/csr/instreth.yaml @@ -17,10 +17,10 @@ description: | 4+^.>h! `instret` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` + ! 0 ! - ! - ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! `IllegalInstruction` ! 1 ! 0 ! 0 ! read-only ! `IllegalInstruction` ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` - ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `VirtualInstruction` ! `VirtualInstruction` + ! 1 ! 0 ! 1 ! read-only ! `IllegalInstruction` ! read-only ! `VirtualInstruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U @@ -71,4 +71,4 @@ sw_read(): | # since the counter may be shared among harts, reads must be handled # as a builtin function - return read_mcycle(); \ No newline at end of file + return read_mcycle(); diff --git a/arch/csr/mcause.yaml b/arch/csr/mcause.yaml index 5f64818bf1..a097a3f0ef 100644 --- a/arch/csr/mcause.yaml +++ b/arch/csr/mcause.yaml @@ -16,7 +16,7 @@ fields: location_rv64: 63 description: | Written by hardware when a trap is taken into M-mode. - + When set, the last exception was caused by an asynchronous Interrupt. `mcause.INT` is writeable. diff --git a/arch/csr/medeleg.yaml b/arch/csr/medeleg.yaml index 16a7b6c5cf..2757966602 100644 --- a/arch/csr/medeleg.yaml +++ b/arch/csr/medeleg.yaml @@ -67,7 +67,7 @@ fields: .>h! `M-mode` .>h! `S-mode` ! 0 ! M ! M - ! 1 ! M ! S + ! 1 ! M ! S !=== <%- end -%> type: RW @@ -104,7 +104,7 @@ fields: .>h! `M-mode` .>h! `S-mode` ! 0 ! M ! M - ! 1 ! M ! S + ! 1 ! M ! S !=== <%- end -%> @@ -142,7 +142,7 @@ fields: .>h! `M-mode` .>h! `S-mode` ! 0 ! M ! M - ! 1 ! M ! S + ! 1 ! M ! S !=== <%- end -%> type: RW @@ -179,7 +179,7 @@ fields: .>h! `M-mode` .>h! `S-mode` ! 0 ! M ! M - ! 1 ! M ! S + ! 1 ! M ! S !=== <%- end -%> type: RW @@ -220,7 +220,7 @@ fields: .>h! `M-mode` .>h! `S-mode` ! 0 ! M ! M - ! 1 ! M ! S + ! 1 ! M ! S !=== <%- end -%> @@ -258,9 +258,9 @@ fields: .>h! `M-mode` .>h! `S-mode` ! 0 ! M ! M - ! 1 ! M ! S + ! 1 ! M ! S !=== - <%- end -%> + <%- end -%> type: RW reset_value: UNDEFINED_LEGAL @@ -300,9 +300,9 @@ fields: .>h! `M-mode` .>h! `S-mode` ! 0 ! M ! M - ! 1 ! M ! S + ! 1 ! M ! S !=== - <%- end -%> + <%- end -%> type: RW reset_value: UNDEFINED_LEGAL @@ -338,9 +338,9 @@ fields: .>h! `M-mode` .>h! `S-mode` ! 0 ! M ! M - ! 1 ! M ! S + ! 1 ! M ! S !=== - <%- end -%> + <%- end -%> type: RW reset_value: UNDEFINED_LEGAL EU: @@ -375,9 +375,9 @@ fields: .>h! `M-mode` .>h! `S-mode` ! 0 ! M ! M - ! 1 ! M ! S + ! 1 ! M ! S !=== - <%- end -%> + <%- end -%> type: RW reset_value: UNDEFINED_LEGAL @@ -401,7 +401,7 @@ fields: .>h! `M-mode` .>h! `(H)S-mode` ! 0 ! M ! M - ! 1 ! M ! (H)S + ! 1 ! M ! (H)S !=== type: RW reset_value: UNDEFINED_LEGAL @@ -425,7 +425,7 @@ fields: .>h! `M-mode` .>h! `(H)S-mode` ! 0 ! M ! M - ! 1 ! M ! (H)S + ! 1 ! M ! (H)S !=== type: RW reset_value: UNDEFINED_LEGAL @@ -472,9 +472,9 @@ fields: .>h! `M-mode` .>h! `S-mode` ! 0 ! M ! M - ! 1 ! M ! S + ! 1 ! M ! S !=== - <%- end -%> + <%- end -%> type: RW reset_value: UNDEFINED_LEGAL LPF: @@ -509,9 +509,9 @@ fields: .>h! `M-mode` .>h! `S-mode` ! 0 ! M ! M - ! 1 ! M ! S + ! 1 ! M ! S !=== - <%- end -%> + <%- end -%> type: RW reset_value: UNDEFINED_LEGAL @@ -547,9 +547,9 @@ fields: .>h! `M-mode` .>h! `S-mode` ! 0 ! M ! M - ! 1 ! M ! S + ! 1 ! M ! S !=== - <%- end -%> + <%- end -%> type: RW reset_value: UNDEFINED_LEGAL IGPF: @@ -572,7 +572,7 @@ fields: .>h! `M-mode` .>h! `(H)S-mode` ! 0 ! M ! M - ! 1 ! M ! HS + ! 1 ! M ! HS !=== type: RW reset_value: UNDEFINED_LEGAL @@ -597,7 +597,7 @@ fields: .>h! `M-mode` .>h! `(H)S-mode` ! 0 ! M ! M - ! 1 ! M ! HS + ! 1 ! M ! HS !=== type: RW @@ -623,7 +623,7 @@ fields: .>h! `M-mode` .>h! `(H)S-mode` ! 0 ! M ! M - ! 1 ! M ! HS + ! 1 ! M ! HS !=== type: RW @@ -649,7 +649,7 @@ fields: .>h! `M-mode` .>h! `(H)S-mode` ! 0 ! M ! M - ! 1 ! M ! HS + ! 1 ! M ! HS !=== type: RW reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/menvcfg.yaml b/arch/csr/menvcfg.yaml index 31b2d7e998..49d263d8bd 100644 --- a/arch/csr/menvcfg.yaml +++ b/arch/csr/menvcfg.yaml @@ -176,7 +176,7 @@ fields: updating of PTE A/D bits is enabled during S-mode address translation, and the implementation behaves as though the Svade extension were not implemented for S-mode address translation. - + When the hypervisor extension is implemented, if ADUE=1, hardware updating of PTE A/D bits is enabled during G-stage address translation, and the implementation behaves as though the Svade extension were not implemented for G-stage address translation. When ADUE=0, the diff --git a/arch/csr/menvcfgh.yaml b/arch/csr/menvcfgh.yaml index 20e5308c06..41aa7f8163 100644 --- a/arch/csr/menvcfgh.yaml +++ b/arch/csr/menvcfgh.yaml @@ -19,7 +19,7 @@ fields: alias: menvcfg.STCE description: | *STimecmp Enable* - + Alias of `menvcfg.STCE` definedBy: Sstc type: RW @@ -43,4 +43,4 @@ fields: type(): | return (implemented?(ExtensionName::Svadu)) ? CsrFieldType::RO : CsrFieldType::RW; reset_value(): | - return (implemented?(ExtensionName::Svadu)) ? UNDEFINED_LEGAL : 0; \ No newline at end of file + return (implemented?(ExtensionName::Svadu)) ? UNDEFINED_LEGAL : 0; diff --git a/arch/csr/mepc.yaml b/arch/csr/mepc.yaml index 7d291543d3..b08d8ebdad 100644 --- a/arch/csr/mepc.yaml +++ b/arch/csr/mepc.yaml @@ -45,4 +45,4 @@ sw_read(): | return CSR[mepc].PC & ~64'b1; } else { return CSR[mepc].PC; - } \ No newline at end of file + } diff --git a/arch/csr/mhartid.yaml b/arch/csr/mhartid.yaml index 1e5425801d..8b5e50793d 100644 --- a/arch/csr/mhartid.yaml +++ b/arch/csr/mhartid.yaml @@ -17,4 +17,4 @@ fields: description: hart-specific ID. reset_value: UNDEFINED_LEGAL sw_read(): | - return hartid(); \ No newline at end of file + return hartid(); diff --git a/arch/csr/mideleg.yaml b/arch/csr/mideleg.yaml index c8d408f1d8..dab340dcec 100644 --- a/arch/csr/mideleg.yaml +++ b/arch/csr/mideleg.yaml @@ -26,7 +26,7 @@ description: | appropriate level with the `MRET` instruction. To increase performance, implementations can provide individual read/write bits within `mideleg` to indicate that certain exceptions and interrupts should - be processed directly by a lower privilege level. + be processed directly by a lower privilege level. In harts with S-mode, the `mideleg` register must exist, and setting a bit `mideleg` will delegate the @@ -104,7 +104,7 @@ fields: *Virtual Supervisor Software Interrupt delegation* When 1, Virtual Supervisor Software interrupts are delegated to HS-mode. - + Virtual Supervisor Software Interrupts are always delegated to HS-mode, so this field is read-only one. type: RO reset_value: 1 @@ -113,7 +113,7 @@ fields: location: 3 description: | *Machine Software interrupt delegation* - + Since M-mode interrupts cannot be delegated, this field is read-only zero. type: RO reset_value: 0 @@ -121,7 +121,7 @@ fields: location: 5 description: | *Supervisor Timer interrupt delegation* - + When 1, Supervisor Timer interrupts are delegated to HS/S-mode. type: RW reset_value: 0 @@ -131,7 +131,7 @@ fields: *Virutal Supervisor Timer interrupt delegation* When 1, Virtual Supervisor Timer interrupts are delegated to HS-mode. - + Virtual Supervisor Time Interrupts are always delegated to HS-mode, so this field is read-only one. type: RO reset_value: 1 @@ -140,7 +140,7 @@ fields: location: 7 description: | *Machine Timer interrupt delegation* - + Since M-mode interrupts cannot be delegated, this field is read-only zero. type: RO reset_value: 0 @@ -148,7 +148,7 @@ fields: location: 9 description: | *Supervisor External interrupt delegation* - + When 1, Supervisor External interrupts are delegated to HS/S-mode. type: RW reset_value: 0 @@ -165,7 +165,7 @@ fields: location: 11 description: | *Machine External interrupt delegation* - + Since M-mode interrupts cannot be delegated, this field is read-only zero. type: RO reset_value: 0 @@ -173,7 +173,7 @@ fields: location: 12 description: | *Supervisor Guest External Interrupt delegation* - + Supervisor Guest External interrupts are always delegated to HS-mode, so this field is read-only one. type: RO reset_value: 1 diff --git a/arch/csr/mie.yaml b/arch/csr/mie.yaml index 2a51b862dc..927ed583c8 100644 --- a/arch/csr/mie.yaml +++ b/arch/csr/mie.yaml @@ -8,7 +8,7 @@ address: 0x304 priv_mode: M length: MXLEN definedBy: Sm -description: +description: $copy: "mip.yaml#/description" fields: SSIE: @@ -134,4 +134,4 @@ fields: Alias of `vsip.LCOFIE` when `hideleg.LCOFI` is set. Otherwise, `vsip.LCOFIE` is read-only 0. type: RW definedBy: Sscofpmf - reset_value: 0 \ No newline at end of file + reset_value: 0 diff --git a/arch/csr/mimpid.yaml b/arch/csr/mimpid.yaml index 228953b37a..4d35e45c79 100644 --- a/arch/csr/mimpid.yaml +++ b/arch/csr/mimpid.yaml @@ -32,4 +32,4 @@ fields: location_rv64: 63-0 type: RO description: Vendor-specific implementation ID. - reset_value(): return IMP_ID; \ No newline at end of file + reset_value(): return IMP_ID; diff --git a/arch/csr/minstreth.yaml b/arch/csr/minstreth.yaml index 0d3f71ccbd..9930ef02d6 100644 --- a/arch/csr/minstreth.yaml +++ b/arch/csr/minstreth.yaml @@ -28,4 +28,4 @@ fields: return csr_value.COUNT; definedBy: Zicntr sw_read(): | - return CSR[minstret].COUNT[63:32]; \ No newline at end of file + return CSR[minstret].COUNT[63:32]; diff --git a/arch/csr/mip.yaml b/arch/csr/mip.yaml index b1e77a6275..5dd94ffb01 100644 --- a/arch/csr/mip.yaml +++ b/arch/csr/mip.yaml @@ -14,11 +14,11 @@ description: | Note that the CLINT refers to an interrupt controller used by some RISC-V implementations but isn't a ratified RISC-V International standard. - + The `mip` CSR contains information on pending interrupts, while `mie` is the corresponding CSR containing interrupt enable bits. Interrupt cause number _i_ (as reported in the `mcause` CSR) - corresponds to bit _i_ in both `mip` and `mie`. + corresponds to bit _i_ in both `mip` and `mie`. Bits 15:0 are allocated to standard interrupt causes only, while bits 16 and above are designated for platform use. @@ -26,7 +26,7 @@ description: | at the platform's discretion. An interrupt _i_ will trap to M-mode (causing the privilege mode to - change to M-mode) if all of the following are true: + change to M-mode) if all of the following are true: * either the current privilege mode is M and the MIE bit in the `mstatus` register is set, or the current privilege mode has less privilege than M-mode; @@ -261,7 +261,7 @@ fields: - hip.VSTIP description: | *Virtual Supervisor Timer Interrupt Pending* - + Reports the current pending state of a VS-mode timer interrupt <%- if ext?(:Sstc) -%> , which is normally controlled by the `vstimecmp` CSR, but can also be injected by the hypervisor through `hvip.VSTIP`. @@ -294,7 +294,7 @@ fields: location: 7 description: | *Machine Timer Interrupt Pending* - + Reports the current pending state of an M-mode timer interrupt. Bit is controlled by the timer device (using `mtimecmp`), and is not writeable. @@ -357,7 +357,7 @@ fields: *Machine External Interrupt Pending* Reports the current pending state of an M-mode external interrupt. - + MEIP is controlled by the external interrupt controller <% if ext?(:Smaia) %>(AIA) <% end %>. It is not writable by software. type: RO-H @@ -402,4 +402,4 @@ fields: <%- end -%> type: RW-H reset_value: 0 - definedBy: Sscofpmf \ No newline at end of file + definedBy: Sscofpmf diff --git a/arch/csr/misa.yaml b/arch/csr/misa.yaml index 7b9f06b70b..5b3674d809 100644 --- a/arch/csr/misa.yaml +++ b/arch/csr/misa.yaml @@ -184,4 +184,3 @@ sw_read(): | (CSR[misa].C << 2) | (CSR[misa].B << 1) | CSR[misa].A); - \ No newline at end of file diff --git a/arch/csr/mscratch.yaml b/arch/csr/mscratch.yaml index 9a95af596e..544b6bce0c 100644 --- a/arch/csr/mscratch.yaml +++ b/arch/csr/mscratch.yaml @@ -15,4 +15,4 @@ fields: location_rv64: 63-0 description: Scratch value type: RW - reset_value: 0 \ No newline at end of file + reset_value: 0 diff --git a/arch/csr/mstatus.yaml b/arch/csr/mstatus.yaml index 9461de08a5..f496aa1ac1 100644 --- a/arch/csr/mstatus.yaml +++ b/arch/csr/mstatus.yaml @@ -20,7 +20,7 @@ fields: location_rv64: 63 description: | State Dirty. - + Read-only bit that summarizes whether either the FS, XS, or VS fields signal the presence of some dirty state. definedBy: @@ -74,7 +74,7 @@ fields: base: 64 description: | *M-mode Big Endian* - + Controls the endianness of data M-mode (0 = little, 1 = big). Instructions are always little endian, regardless of the data setting. @@ -96,7 +96,7 @@ fields: definedBy: S description: | *S-mode Big Endian* - + Controls the endianness of S-mode (0 = little, 1 = big). Instructions are always little endian, regardless of the data setting. @@ -123,7 +123,7 @@ fields: definedBy: S description: | *S-mode XLEN* - + Sets the effective XLEN for S-mode (0 = 32-bit, 1 = 64-bit, 2 = 128-bit [reserved]). [when,"SXLEN==32"] @@ -135,9 +135,9 @@ fields: [when,"SXLEN=3264"] -- It is not valid to have SXLEN less than UXLEN. - + It is UNDEFINED_LEGAL what will happen if a software sets `mstatus.SXL` to be greater than `mstatus.UXL`. - + It is UNDEFINED_LEGAL to set the MSB of SXL. -- type(): | @@ -172,7 +172,7 @@ fields: definedBy: U description: | U-mode XLEN. - + Sets the effective XLEN for U-mode (0 = 32-bit, 1 = 64-bit, 2 = 128-bit [reserved]). [when,"UXLEN == 32"] @@ -185,9 +185,9 @@ fields: [when,"UXLEN == 3264"] -- It is not valid to have SXLEN less than UXLEN. - + It is UNDEFINED_LEGAL what will happen if a software sets `mstatus.SXL` to be greater than `mstatus.UXL`. - + It is UNDEFINED_LEGAL to set the MSB of UXL. -- type(): | @@ -210,7 +210,7 @@ fields: return csr_value.UXL == 1; } else { return csr_value.UXL <= 1; - } + } reset_value(): | if (UXLEN == 32) { @@ -258,7 +258,7 @@ fields: * writing the `hgtap` CSR, executing an `hfence.gvma`, or executing an `hinval.gvma` while in HS-mode Notably, `mstatus.TVM` does *not* cause - + *`hfence.vvma`, `sfence.w.inval`, or `sfence.inval.ir` to trap. * Any additional traps in VS-mode (controlled via `hstatus.VTVM` instead). @@ -289,7 +289,7 @@ fields: location: 19 description: | Make eXecutable Readable. - + When 1, loads from pages marked readable *or executable* are allowed. When 0, loads from pages marked executable raise a Page Fault exception. definedBy: S @@ -299,7 +299,7 @@ fields: location: 18 description: | permit Supervisor Memory Access. - + When 0, an S-mode read or an M-mode read with mstatus.MPRV=1 and mstatus.MPP=01 to a 'U' (user) page will cause an ILLEGAL INSTRUCTION exception. definedBy: S @@ -321,7 +321,7 @@ fields: location: 17 description: | Modify PRiVilege. - + When 1, loads and stores behave as if the current virutalization mode:privilege level was `mstatus.MPV`:`mstatus.MPP`. @@ -334,7 +334,7 @@ fields: location: 16-15 description: | *Custom (X) extension context Status* - + Summarizes the current state of any custom extension state. Either 0 - Off, 1 - Initial, 2 - Clean, 3 - Dirty. Since there are no custom extensions in the base spec, this field is read-only 0. @@ -344,12 +344,12 @@ fields: location: 14-13 description: | Floating point context status. - + When 0, floating point instructions (from F and D extensions) are disabled, and cause `ILLEGAL INSTRUCTION` exceptions. When a floating point register, or the fCSR register is written, FS obtains the value 3. Values 1 and 2 are valid write values for software, but are not interpreted by hardware - other than to possibly enable a previously-disabled floating point unit. + other than to possibly enable a previously-disabled floating point unit. type(): | if (CSR[misa].F == 1'b1){ return CsrFieldType::RWH; @@ -427,7 +427,7 @@ fields: location: 10-9 description: | Vector context status. - + When 0, vector instructions (from the V extension) are disabled, and cause ILLEGAL INSTRUCTION exceptions. When a vector register or vector CSR is written, VS obtains the value 3. Values 1 and 2 are valid write values for software, but are not interpreted by hardware @@ -468,7 +468,7 @@ fields: location: 8 description: | *S-mode Previous Privilege* - + Written by hardware in two cases: * Written with the prior nominal privilege level when entering (H)S-mode from an exception/interrupt. @@ -498,7 +498,7 @@ fields: location: 7 description: | *M-mode Previous Interrupt Enable* - + Written by hardware in two cases: * Written with prior value of `mstatus.MIE` when entering M-mode from an exception/interrupt. @@ -507,7 +507,7 @@ fields: Can also be written by software without immediate side effect. Other than serving as a record of nested traps as described above, `mstatus.MPIE` does not affect execution. - + type: RW-H reset_value: UNDEFINED_LEGAL UBE: @@ -515,7 +515,7 @@ fields: definedBy: U description: | *U-mode Big Endian* - + Controls the endianness of U-mode (0 = little, 1 = big). Instructions are always little endian, regardless of the data setting. @@ -523,7 +523,7 @@ fields: Since the CPU does not support big endian in U-mode, this is hardwired to 0. [when,"U_MODE_ENDIANESS == 'big'"] - Since the CPU does not support litte endian in U-mode, this is hardwired to 1. + Since the CPU does not support litte endian in U-mode, this is hardwired to 1. type(): | return (U_MODE_ENDIANESS == "dynamic") ? CsrFieldType::RW : CsrFieldType::RO; @@ -558,7 +558,7 @@ fields: location: 3 description: | *M-mode Interrupt Enable* - + Written by hardware in two cases: * Written with the value 0 when entering M-mode from an exception/interrupt. @@ -568,14 +568,14 @@ fields: * When 0, all interrupts are disabled when the current privilege level is M. * When 1, interrupts that are not otherwise disabled with a field in `mie` are enabled. - + type: RW-H reset_value: 0 SIE: location: 1 description: | *S-mode Interrupt Enable* - + Written by hardware in two cases: * Written with the value 0 when entering (H)S-mode from an exception/interrupt. diff --git a/arch/csr/mstatush.yaml b/arch/csr/mstatush.yaml index 329d2a99ec..3fac5fdcb8 100644 --- a/arch/csr/mstatush.yaml +++ b/arch/csr/mstatush.yaml @@ -55,4 +55,3 @@ fields: } else { return UNDEFINED_LEGAL; } - diff --git a/arch/csr/mtval.yaml b/arch/csr/mtval.yaml index e2d4da1a02..067f84b6f5 100644 --- a/arch/csr/mtval.yaml +++ b/arch/csr/mtval.yaml @@ -46,7 +46,7 @@ fields: ! [6] Store/AMO address misaligned ! The misaligned virtual store/AMO address. ! [7] Store/AMO access fault ! The virtual store/AMO address causing the access fault. - + When the store/AMO is misaligned, the reported value is the smallest address on the page causing a fault (_e.g._, if an 8-byte store is equally split across a page and the fault occurs on the second page, address + 4 is reported). @@ -63,34 +63,34 @@ fields: <% unless ext?(:C) %>(same as the value written to `mepc`)<% end %>. ! [13] Load page fault ! The part of the virtual load address causing in the page fault. - + When the load is misaligned, the reported value is the smallest address on the page causing a fault (_e.g._, if an 8-byte load is equally split across a page and the fault occurs on the second page, address + 4 is reported). ! [15] Store/AMO page fault ! The virtual store/AMO address causing in the page fault. - + When the store/AMO is misaligned, the reported value is the smallest address on the page causing a fault (_e.g._, if an 8-byte store is equally split across a page and the fault occurs on the second page, address + 4 is reported). <%- if ext?(:H) -%> ! [20] Instruction guest-page fault ! The <% if ext?(:C) %> portion of the <% end %> virtual PC causing the fault <% unless ext?(:C) %>(same as the value written to `mepc`)<% end %>. - + The guest physical address is reported in `mtval2`. ! [21] Load guest-page fault ! The part of the virtual address causing the fault. When the load is misaligned, the reported value is the smallest address on the page causing a fault (_e.g._, if an 8-byte load is equally split across a page and the fault occurs on the second page, address + 4 is reported). - + The guest physical address is reported in `mtval2`. ! [22] Virutal instruction ! The encoding of the faulting virtual instruction. ! [23] Store/AMO guest-page fault ! The part of the virtual address causing the fault. - + When the store/AMO is misaligned, the reported value is the smallest address on the page causing a fault (_e.g._, if an 8-byte store is equally split across a page and the fault occurs on the second page, address + 4 is reported). - + The guest physical address is reported in `mtval2`. <%- end -%> !=== diff --git a/arch/csr/mtvec.yaml b/arch/csr/mtvec.yaml index f38a48b8c5..265f39fd3e 100644 --- a/arch/csr/mtvec.yaml +++ b/arch/csr/mtvec.yaml @@ -28,7 +28,7 @@ fields: location: 1-0 description: | Vectoring mode for asynchronous interrupts. - + 0 - Direct, 1 - Vectored When Direct, all synchronous exceptions and asynchronous interrupts jump to (`mtvec.BASE` << 2). diff --git a/arch/csr/scause.yaml b/arch/csr/scause.yaml index 21b8b4a547..2e0e585597 100644 --- a/arch/csr/scause.yaml +++ b/arch/csr/scause.yaml @@ -16,7 +16,7 @@ fields: location_rv64: 63 description: | Written by hardware when a trap is taken into S-mode. - + When set, the last exception was caused by an asynchronous Interrupt. `scause.INT` is writeable. diff --git a/arch/csr/schema.adoc b/arch/csr/schema.adoc index e13ceb224d..acdb74bd34 100644 --- a/arch/csr/schema.adoc +++ b/arch/csr/schema.adoc @@ -218,4 +218,3 @@ Custom Write Function:: Alias:: Some fields are aliases for another field, often in a different CSR. THe `alias` key is used to indicate that this field just points somewhere else. - diff --git a/arch/csr/senvcfg.yaml b/arch/csr/senvcfg.yaml index e804e5aaef..1c6aea47d4 100644 --- a/arch/csr/senvcfg.yaml +++ b/arch/csr/senvcfg.yaml @@ -101,7 +101,7 @@ fields: * `01`: The instruction is executed and performs a flush operation * `10`: _Reserved_ * `11`: The instruction is executed and performs an invalidate operation - + See `cbo.inval` for more details. definedBy: Zicbom type: RW-R @@ -142,4 +142,4 @@ fields: See `fence` for more details. type: RW - reset_value: 0 \ No newline at end of file + reset_value: 0 diff --git a/arch/csr/sstatus.yaml b/arch/csr/sstatus.yaml index ba014122e0..c9ae22e33c 100644 --- a/arch/csr/sstatus.yaml +++ b/arch/csr/sstatus.yaml @@ -22,7 +22,7 @@ fields: *State Dirty* Alias of `mstatus.SD`. - + type: RO-H reset_value: UNDEFINED_LEGAL affectedBy: [F, D, V] @@ -34,7 +34,7 @@ fields: *U-mode XLEN* Alias of `mstatus.UXL`. - + type: RO reset_value: UNDEFINED_LEGAL MXR: @@ -44,7 +44,7 @@ fields: *Make eXecutable Readable* Alias of `mstatus.MXR`. - + type: RW reset_value: UNDEFINED_LEGAL SUM: @@ -54,7 +54,7 @@ fields: *permit Supervisor Memory Access* Alias of `mstatus.SUM`. - + type: RW reset_value: UNDEFINED_LEGAL XS: @@ -62,9 +62,9 @@ fields: location: 16-15 description: | Custom (X) extension context Status. - + Alias of `mstatus.XS`. - + type: RO reset_value: UNDEFINED_LEGAL FS: @@ -87,7 +87,7 @@ fields: Alias of `mstatus.VS`. type: RW-H - reset_value: UNDEFINED_LEGAL + reset_value: UNDEFINED_LEGAL definedBy: V SPP: alias: mstatus.SPP @@ -116,7 +116,7 @@ fields: *S-mode Previous Interrupt Enable* Alias of `mstatus.SPIE`. - + type: RW-H definedBy: S reset_value: UNDEFINED_LEGAL @@ -127,6 +127,6 @@ fields: *S-mode Interrupt Enable* Alias of `mstatus.SIE`. - + type: RW-H - reset_value: UNDEFINED_LEGAL \ No newline at end of file + reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/stval.yaml b/arch/csr/stval.yaml index 0e2a64bf43..e301e3c798 100644 --- a/arch/csr/stval.yaml +++ b/arch/csr/stval.yaml @@ -27,7 +27,7 @@ fields: ! [3] Breakpoint ! [when,"REPORT_VA_IN_STVAL_ON_BREAKPOINT == true"] When caused by an EBREAK instruction, the virtual PC of the breakpoint instruction. - + [when,"REPORT_VA_IN_STVAL_ON_BREAKPOINT == false"] When caused by an EBREAK instruction, zero. @@ -45,7 +45,7 @@ fields: ! [6] Store/AMO address misaligned ! The misaligned virtual store/AMO address. ! [7] Store/AMO access fault ! The virtual store/AMO address causing the access fault. - + When the store/AMO is misaligned, the reported value is the smallest address on the page causing a fault (_e.g._, if an 8-byte store is equally split across a page and the fault occurs on the second page, address + 4 is reported). @@ -61,34 +61,34 @@ fields: <% unless ext?(:C) %>(same as the value written to `mepc`)<% end %>. ! [13] Load page fault ! The part of the virtual load address causing in the page fault. - + When the load is misaligned, the reported value is the smallest address on the page causing a fault (_e.g._, if an 8-byte load is equally split across a page and the fault occurs on the second page, address + 4 is reported). ! [15] Store/AMO page fault ! The virtual store/AMO address causing in the page fault. - + When the store/AMO is misaligned, the reported value is the smallest address on the page causing a fault (_e.g._, if an 8-byte store is equally split across a page and the fault occurs on the second page, address + 4 is reported). <%- if ext?(:H) -%> ! [20] Instruction guest-page fault ! The <% if ext?(:C) %> portion of the <% end %> virtual PC causing the fault <% unless ext?(:C) %>(same as the value written to `mepc`)<% end %>. - + The guest physical address is reported in `mtval2`. ! [21] Load guest-page fault ! The part of the virtual address causing the fault. When the load is misaligned, the reported value is the smallest address on the page causing a fault (_e.g._, if an 8-byte load is equally split across a page and the fault occurs on the second page, address + 4 is reported). - + The guest physical address is reported in `mtval2`. ! [22] Virutal instruction ! The encoding of the faulting virtual instruction. ! [23] Store/AMO guest-page fault ! The part of the virtual address causing the fault. - + When the store/AMO is misaligned, the reported value is the smallest address on the page causing a fault (_e.g._, if an 8-byte store is equally split across a page and the fault occurs on the second page, address + 4 is reported). - + The guest physical address is reported in `htval`. <%- end -%> !=== diff --git a/arch/csr/stvec.yaml b/arch/csr/stvec.yaml index acc02efedc..3432f8a89a 100644 --- a/arch/csr/stvec.yaml +++ b/arch/csr/stvec.yaml @@ -30,7 +30,7 @@ fields: location: 1-0 description: | Vectoring mode for asynchronous interrupts. - + 0 - Direct, 1 - Vectored When Direct, all synchronous exceptions and asynchronous interrupts jump to (`stvec.BASE` << 2). diff --git a/arch/csr/time.yaml b/arch/csr/time.yaml index c900402d94..72e4706fa8 100644 --- a/arch/csr/time.yaml +++ b/arch/csr/time.yaml @@ -21,10 +21,10 @@ description: | 4+^.>h! `time` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `Illegal Instruction` ! `Illegal Instruction` ! `Illegal Instruction` ! `Illegal Instruction` - ! 1 ! 0 ! 0 ! read-only ! `Illegal Instruction` ! `Illegal Instruction` ! `Illegal Instruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `Illegal Instruction` ! `Illegal Instruction` - ! 1 ! 0 ! 1 ! read-only ! `Illegal Instruction` ! read-only ! `Illegal Instruction` + ! 0 ! - ! - ! `Illegal Instruction` ! `Illegal Instruction` ! `Illegal Instruction` ! `Illegal Instruction` + ! 1 ! 0 ! 0 ! read-only ! `Illegal Instruction` ! `Illegal Instruction` ! `Illegal Instruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `Illegal Instruction` ! `Illegal Instruction` + ! 1 ! 0 ! 1 ! read-only ! `Illegal Instruction` ! read-only ! `Illegal Instruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== -- diff --git a/arch/csr/timeh.yaml b/arch/csr/timeh.yaml index 8d9ebf3b10..f3aa95bfb0 100644 --- a/arch/csr/timeh.yaml +++ b/arch/csr/timeh.yaml @@ -21,10 +21,10 @@ description: | 4+^.>h! `time` behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `Illegal Instruction` ! `Illegal Instruction` ! `Illegal Instruction` ! `Illegal Instruction` - ! 1 ! 0 ! 0 ! read-only ! `Illegal Instruction` ! `Illegal Instruction` ! `Illegal Instruction` - ! 1 ! 1 ! 0 ! read-only ! read-only ! `Illegal Instruction` ! `Illegal Instruction` - ! 1 ! 0 ! 1 ! read-only ! `Illegal Instruction` ! read-only ! `Illegal Instruction` + ! 0 ! - ! - ! `Illegal Instruction` ! `Illegal Instruction` ! `Illegal Instruction` ! `Illegal Instruction` + ! 1 ! 0 ! 0 ! read-only ! `Illegal Instruction` ! `Illegal Instruction` ! `Illegal Instruction` + ! 1 ! 1 ! 0 ! read-only ! read-only ! `Illegal Instruction` ! `Illegal Instruction` + ! 1 ! 0 ! 1 ! read-only ! `Illegal Instruction` ! read-only ! `Illegal Instruction` ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== -- diff --git a/arch/csr/vscause.yaml b/arch/csr/vscause.yaml index 56c4070585..cfaf02d1dd 100644 --- a/arch/csr/vscause.yaml +++ b/arch/csr/vscause.yaml @@ -16,7 +16,7 @@ fields: location_rv32: 31 description: | Written by hardware when a trap is taken into VS-mode. - + When set, the last exception was caused by an asynchronous Interrupt. `vscause.INT` is writeable. diff --git a/arch/csr/vsstatus.yaml b/arch/csr/vsstatus.yaml index 9a3a9d72bc..5df4d8451c 100644 --- a/arch/csr/vsstatus.yaml +++ b/arch/csr/vsstatus.yaml @@ -23,7 +23,7 @@ fields: location_rv32: 31 description: | *State Dirty* - + Read-only bit that summarizes whether any of the `vsstatus.FS`, <% if ext?(:V) %> `vsstatus.VS`, <% end %> or `vsstatus.XS` fields signal the presence of some dirty state @@ -104,7 +104,7 @@ fields: location: 16-15 description: | *Custom (X) extension context Status* - + Summarizes the current state of any custom extension state. Either 0 - Off, 1 - Initial, 2 - Clean, 3 - Dirty. Since there are no custom extensions, this field is read-only 0. @@ -124,7 +124,7 @@ fields: `vsstatus.FS` is written with the value 3. Values 1 and 2 are valid write values for software, but are not interpreted by hardware - other than to possibly enable a previously-disabled floating point unit. + other than to possibly enable a previously-disabled floating point unit. type: RW-H definedBy: F reset_value: UNDEFINED_LEGAL @@ -138,7 +138,7 @@ fields: Values 1 and 2 are valid write values for software, but are not interpreted by hardware other than to possibly enable a previously-disabled vector unit. type: RW-H - reset_value: UNDEFINED_LEGAL + reset_value: UNDEFINED_LEGAL definedBy: V SPP: location: 8 diff --git a/arch/csr/vstval.yaml b/arch/csr/vstval.yaml index bc1cbfc876..ced416f70a 100644 --- a/arch/csr/vstval.yaml +++ b/arch/csr/vstval.yaml @@ -29,7 +29,7 @@ fields: ! [3] Breakpoint a! [when,"REPORT_VA_IN_VSTVAL_ON_BREAKPOINT == true"] When caused by an EBREAK instruction, the virtual PC of the breakpoint instruction. - + [when,"REPORT_VA_IN_VSTVAL_ON_BREAKPOINT == false"] When caused by an EBREAK instruction, zero. @@ -47,7 +47,7 @@ fields: ! [6] Store/AMO address misaligned ! The misaligned virtual store/AMO address. ! [7] Store/AMO access fault ! The virtual store/AMO address causing the access fault. - + When the store/AMO is misaligned, the reported value is the smallest address on the page causing a fault (_e.g._, if an 8-byte store is equally split across a page and the fault occurs on the second page, address + 4 is reported). @@ -63,34 +63,34 @@ fields: <% unless ext?(:C) %>(same as the value written to `mepc`)<% end %>. ! [13] Load page fault ! The part of the virtual load address causing in the page fault. - + When the load is misaligned, the reported value is the smallest address on the page causing a fault (_e.g._, if an 8-byte load is equally split across a page and the fault occurs on the second page, address + 4 is reported). ! [15] Store/AMO page fault ! The virtual store/AMO address causing in the page fault. - + When the store/AMO is misaligned, the reported value is the smallest address on the page causing a fault (_e.g._, if an 8-byte store is equally split across a page and the fault occurs on the second page, address + 4 is reported). <%- if ext?(:H) -%> ! [20] Instruction guest-page fault ! The <% if ext?(:C) %> portion of the <% end %> virtual PC causing the fault <% unless ext?(:C) %>(same as the value written to `mepc`)<% end %>. - + The guest physical address is reported in `mtval2`. ! [21] Load guest-page fault ! The part of the virtual address causing the fault. When the load is misaligned, the reported value is the smallest address on the page causing a fault (_e.g._, if an 8-byte load is equally split across a page and the fault occurs on the second page, address + 4 is reported). - + The guest physical address is reported in `mtval2`. ! [22] Virutal instruction ! The encoding of the faulting virtual instruction. ! [23] Store/AMO guest-page fault ! The part of the virtual address causing the fault. - + When the store/AMO is misaligned, the reported value is the smallest address on the page causing a fault (_e.g._, if an 8-byte store is equally split across a page and the fault occurs on the second page, address + 4 is reported). - + The guest physical address is reported in `htval`. <%- end -%> !=== diff --git a/arch/csr/vstvec.yaml b/arch/csr/vstvec.yaml index 1d77e20b41..a74254e647 100644 --- a/arch/csr/vstvec.yaml +++ b/arch/csr/vstvec.yaml @@ -31,7 +31,7 @@ fields: location: 1-0 description: | Vectoring mode for asynchronous interrupts taken into VS-mode. - + 0 - Direct, 1 - Vectored When Direct, all synchronous exceptions and asynchronous interrupts jump to (`vstvec.BASE` << 2). @@ -44,4 +44,4 @@ fields: } else { return UNDEFINED_LEGAL_DETERMINISTIC; } - reset_value: 0 \ No newline at end of file + reset_value: 0 diff --git a/arch/ext/A.yaml b/arch/ext/A.yaml index b857f9d791..f72416a5b2 100644 --- a/arch/ext/A.yaml +++ b/arch/ext/A.yaml @@ -80,8 +80,8 @@ params: description: | Strategy used to handle reservation sets. - * "reserve naturally-aligned 64-byte region": Always reserve the 64-byte block containing the LR/SC address - * "reserve naturally-aligned 128-byte region": Always reserve the 128-byte block containing the LR/SC address + * "reserve naturally-aligned 64-byte region": Always reserve the 64-byte block containing the LR/SC address + * "reserve naturally-aligned 128-byte region": Always reserve the 128-byte block containing the LR/SC address * "reserve exactly enough to cover the access": Always reserve exactly the LR/SC access, and no more * "custom": Custom behavior, leading to an 'unpredictable' call on any LR/SC schema: diff --git a/arch/ext/C.yaml b/arch/ext/C.yaml index 5321d7d903..4559fa8c66 100644 --- a/arch/ext/C.yaml +++ b/arch/ext/C.yaml @@ -68,7 +68,7 @@ description: | Double-precision loads and stores are a significant fraction of static and dynamic instructions, hence the motivation to include them in the RV32C and RV64C encoding. - + Although single-precision loads and stores are not a significant source of static or dynamic compression for benchmarks compiled for the currently supported ABIs, for microcontrollers that only provide @@ -240,7 +240,7 @@ description: | //[%header] [float="center",align="center",cols="1a, 2a",frame="none",grid="none"] |=== - | + | [%autowidth,float="right",align="right",cols="^,^",frame="none",grid="none",options="noheader"] !=== !Format ! Meaning @@ -275,14 +275,14 @@ description: | //[cols="20%,10%,10%,10%,10%,10%,10%,10%,10%"] [float="center",align="center",cols="1a, 1a",frame="none",grid="none"] |=== - | + | [%autowidth,cols="<",frame="none",grid="none",options="noheader"] !=== !RVC Register Number !Integer Register Number - !Integer Register ABI Name + !Integer Register ABI Name !Floating-Point Register Number - !Floating-Point Register ABI Name + !Floating-Point Register ABI Name !=== | @@ -300,4 +300,4 @@ params: description: | Indicates whether or not the `C` extension can be disabled with the `misa.C` bit. schema: - type: boolean \ No newline at end of file + type: boolean diff --git a/arch/ext/D.yaml b/arch/ext/D.yaml index a5b20acf8e..a997789999 100644 --- a/arch/ext/D.yaml +++ b/arch/ext/D.yaml @@ -106,4 +106,4 @@ params: description: | Indicates whether or not the `D` extension can be disabled with the `misa.D` bit. schema: - type: boolean \ No newline at end of file + type: boolean diff --git a/arch/ext/F.yaml b/arch/ext/F.yaml index 3193d1a3c4..fd45f3bccc 100644 --- a/arch/ext/F.yaml +++ b/arch/ext/F.yaml @@ -125,7 +125,7 @@ description: | modes are encoded as shown in <>. A value of 111 in the instruction's _rm_ field selects the dynamic rounding mode held in `frm`. The behavior of floating-point instructions that depend on - rounding mode when executed with a reserved rounding mode is _reserved_, including both static reserved rounding modes (101-110) and dynamic reserved rounding modes (101-111). Some instructions, including widening conversions, have the _rm_ field but are nevertheless mathematically unaffected by the rounding mode; software should set their _rm_ field to + rounding mode when executed with a reserved rounding mode is _reserved_, including both static reserved rounding modes (101-110) and dynamic reserved rounding modes (101-111). Some instructions, including widening conversions, have the _rm_ field but are nevertheless mathematically unaffected by the rounding mode; software should set their _rm_ field to RNE (000) but implementations must treat the _rm_ field as usual (in particular, with regard to decoding legal vs. reserved encodings). @@ -270,4 +270,4 @@ params: assert MSTATUS_FS_LEGAL_VALUES.include?(0) && MSTATUS_FS_LEGAL_VALUES.include?(3) if ext?(:F) # if HW is writing FS, then Dirty (3) better be a supported value - assert MSTATUS_FS_LEGAL_VALUES.include?(3) if ext?(:F) && (HW_MSTATUS_FS_DIRTY_UPDATE != "never") \ No newline at end of file + assert MSTATUS_FS_LEGAL_VALUES.include?(3) if ext?(:F) && (HW_MSTATUS_FS_DIRTY_UPDATE != "never") diff --git a/arch/ext/H.yaml b/arch/ext/H.yaml index 0e8bb8bcd1..3ff99325b4 100644 --- a/arch/ext/H.yaml +++ b/arch/ext/H.yaml @@ -161,7 +161,7 @@ params: NUM_EXTERNAL_GUEST_INTERRUPTS: description: | Number of supported virtualized guest interrupts - + Corresponds to the `GEILEN` parameter in the RVI specs schema: type: integer @@ -454,7 +454,7 @@ params: * "always zero": Always write the value zero * "always pseudoinstruction": Always write the pseudoinstruction * "always transformed standard instruction": Always write the transformation of the standard instruction encoding - * "custom": A custom value, which will cause an UNPREDICTABLE event. + * "custom": A custom value, which will cause an UNPREDICTABLE event. schema: type: string enum: @@ -470,7 +470,7 @@ params: * "always zero": Always write the value zero * "always pseudoinstruction": Always write the pseudoinstruction * "always transformed standard instruction": Always write the transformation of the standard instruction encoding - * "custom": A custom value, which will cause an UNPREDICTABLE event. + * "custom": A custom value, which will cause an UNPREDICTABLE event. schema: type: string enum: @@ -636,4 +636,4 @@ params: without raising a trap, in which case the EEI must provide a builtin. schema: type: boolean - default: true \ No newline at end of file + default: true diff --git a/arch/ext/I.yaml b/arch/ext/I.yaml index 72eae0eac0..31a0e9099b 100644 --- a/arch/ext/I.yaml +++ b/arch/ext/I.yaml @@ -12,4 +12,4 @@ versions: changes: - ratified RVWMO memory model and exclusion of FENCE.I, counters, and CSR instructions that were in previous base ISA description: | - Base integer instructions -- TODO \ No newline at end of file + Base integer instructions -- TODO diff --git a/arch/ext/M.yaml b/arch/ext/M.yaml index e5bf5fa1be..25f3af18b4 100644 --- a/arch/ext/M.yaml +++ b/arch/ext/M.yaml @@ -26,4 +26,4 @@ params: description: | Indicates whether or not the `M` extension can be disabled with the `misa.M` bit. schema: - type: boolean \ No newline at end of file + type: boolean diff --git a/arch/ext/MockExt.yaml b/arch/ext/MockExt.yaml index 8ba867c8d4..57cc560d41 100644 --- a/arch/ext/MockExt.yaml +++ b/arch/ext/MockExt.yaml @@ -89,7 +89,7 @@ params: description: foo schema: type: integer - minimum: 1000 + minimum: 1000 maximum: 2048 MOCK_INT_RANGE_0_TO_128: description: foo @@ -153,4 +153,4 @@ params: additionalItems: type: boolean maxItems: 8 - minItems: 8 \ No newline at end of file + minItems: 8 diff --git a/arch/ext/Sm.yaml b/arch/ext/Sm.yaml index 47b5a40a65..fdd3b5d35d 100644 --- a/arch/ext/Sm.yaml +++ b/arch/ext/Sm.yaml @@ -231,8 +231,8 @@ params: maximum: 127 MISALIGNED_LDST: description: | - Does the implementation perform non-atomic misaligned loads and stores to main memory - (does *not* affect misaligned support to device memory)? + Does the implementation perform non-atomic misaligned loads and stores to main memory + (does *not* affect misaligned support to device memory)? If not, the implementation always throws a misaligned exception. schema: type: boolean @@ -282,7 +282,7 @@ params: * by_byte: The load/store appears to be broken into byte-sized accesses that processed sequentially from smallest address to largest address * custom: Something else. Will result in a call to unpredictable() in the execution - schema: + schema: type: string enum: ["by_byte", "custom"] TRAP_ON_ILLEGAL_WLRL: @@ -431,7 +431,7 @@ params: PMA_GRANULARITY: description: | log2 of the smallest supported PMA region. - + Generally, for systems with an MMU, should not be smaller than 12, as that would preclude caching PMP results in the TLB along with virtual memory translations @@ -468,7 +468,7 @@ params: true:: The `misa` CSR returns a non-zero value. - + false:: The `misa` CSR is read-only-0. schema: diff --git a/arch/ext/Smcdeleg.yaml b/arch/ext/Smcdeleg.yaml index cf03c52530..5979178c8a 100644 --- a/arch/ext/Smcdeleg.yaml +++ b/arch/ext/Smcdeleg.yaml @@ -34,4 +34,4 @@ versions: email: gfavor@ventanamicro.com company: Ventana Microsystems - name: John Hauser - email: jh.riscv@jhauser.us \ No newline at end of file + email: jh.riscv@jhauser.us diff --git a/arch/ext/Smhpm.yaml b/arch/ext/Smhpm.yaml index ebb5b18424..fa2d63df3c 100644 --- a/arch/ext/Smhpm.yaml +++ b/arch/ext/Smhpm.yaml @@ -56,7 +56,7 @@ params: description: | Indicates which hardware performance monitor counters can be disabled from `mcountinhibit`. - An unimplemented counter cannot be specified, i.e., if HPM_COUNTER_EN[3] is false, + An unimplemented counter cannot be specified, i.e., if HPM_COUNTER_EN[3] is false, it would be illegal to set COUNTINHIBIT_EN[3] to true. COUNTINHIBIT_EN[1] can never be true, since it corresponds to `mcountinhibit.TM`, @@ -88,4 +88,4 @@ params: items: type: boolean maxItems: 32 - minItems: 32 \ No newline at end of file + minItems: 32 diff --git a/arch/ext/Smpmp.yaml b/arch/ext/Smpmp.yaml index f50f73c6d5..05e0ec6548 100644 --- a/arch/ext/Smpmp.yaml +++ b/arch/ext/Smpmp.yaml @@ -46,7 +46,7 @@ params: must appear to be 0, 16, or 64. Therefore, pmp registers will behave as follows according to NUN_PMP_ENTRIES: - + [separator="!"] !=== ! NUM_PMP_ENTRIES ! pmpaddr<0-15> / pmpcfg<0-3> ! pmpaddr<16-63> / pmpcfg<4-15> @@ -59,7 +59,7 @@ params: if TRAP_ON_UNIMPLEMENTED_CSR is true ** Y = Implemented; access will not cause an exception (from M-mode), but register may be read-only-zero if NUM_PMP_ENTRIES is less than the corresponding register - + [NOTE] `pmpcfgN` for an odd N never exists when XLEN == 64 @@ -72,7 +72,7 @@ params: PMP_GRANULARITY: description: | log2 of the smallest supported PMP region. - + Generally, for systems with an MMU, should not be smaller than 12, as that would preclude caching PMP results in the TLB along with virtual memory translations @@ -82,4 +82,4 @@ params: schema: type: integer minimum: 2 - maximum: 66 \ No newline at end of file + maximum: 66 diff --git a/arch/ext/Sstvala.yaml b/arch/ext/Sstvala.yaml index 118b7811db..98e5fce73e 100644 --- a/arch/ext/Sstvala.yaml +++ b/arch/ext/Sstvala.yaml @@ -9,7 +9,7 @@ description: | and instruction page-fault, access-fault, and misaligned exceptions, and for breakpoint exceptions other than those caused by execution of the `ebreak` or `c.ebreak instructions. - + For virtual-instruction and illegal-instruction exceptions, `stval` must be written with the faulting instruction. @@ -60,4 +60,4 @@ versions: const: true REPORT_ENCODING_IN_STVAL_ON_ILLEGAL_INSTRUCTION: schema: - const: true \ No newline at end of file + const: true diff --git a/arch/ext/Svade.yaml b/arch/ext/Svade.yaml index b776ca6bb8..8dcbf48575 100644 --- a/arch/ext/Svade.yaml +++ b/arch/ext/Svade.yaml @@ -39,4 +39,3 @@ conflicts: Svadu doc_license: name: Creative Commons Attribution 4.0 International License (CC-BY 4.0) url: https://creativecommons.org/licenses/by/4.0/ - diff --git a/arch/ext/Svadu.yaml b/arch/ext/Svadu.yaml index bd505b5be0..93202f7320 100644 --- a/arch/ext/Svadu.yaml +++ b/arch/ext/Svadu.yaml @@ -12,7 +12,7 @@ description: | * When a virtual page is accessed and the A bit is clear, the PTE is updated to set the A bit. When the virtual page is written and the D bit is clear, the PTE is updated to set the D bit. When G-stage address translation is in use - and is not Bare, the G-stage virtual pages may be accessed or written by + and is not Bare, the G-stage virtual pages may be accessed or written by implicit accesses to VS-level memory management data structures, such as page tables. @@ -38,7 +38,7 @@ description: | remote harts. + + The PTE update is not required to be atomic with respect to the memory access - that caused the update and a trap may occur between the PTE update and the + that caused the update and a trap may occur between the PTE update and the memory access that caused the PTE update. If a trap occurs then the A and/or D bit may be updated but the memory access that caused the PTE update might not occur. The hart must not perform the memory access that caused the PTE update @@ -122,4 +122,3 @@ conflicts: Svade doc_license: name: Creative Commons Attribution 4.0 International License (CC-BY 4.0) url: https://creativecommons.org/licenses/by/4.0/ - diff --git a/arch/ext/Svnapot.yaml b/arch/ext/Svnapot.yaml index af42265d33..240f60cf7c 100644 --- a/arch/ext/Svnapot.yaml +++ b/arch/ext/Svnapot.yaml @@ -56,7 +56,7 @@ description: | <>, then a page-fault exception must be raised. * Implicit reads of NAPOT page table entries may create address-translation cache entries mapping - _a_ + _j_*PTESIZE to a copy of _pte_ in which _pte_._ppn_[_i_][_pte_.__napot_bits__-1:0] + _a_ + _j_*PTESIZE to a copy of _pte_ in which _pte_._ppn_[_i_][_pte_.__napot_bits__-1:0] is replaced by _vpn[i][pte.napot_bits_-1:0], for any or all _j_ such that __j__ >> __napot_bits__ = __vpn__[__i__] >> __napot_bits__, all for the address space identified in _satp_ as loaded by step 1. @@ -152,7 +152,7 @@ description: | 1 + 2 + ... - |=== + |=== In such a case, an implementation may or may not support all options. The discoverability mechanism for this extension would be extended to diff --git a/arch/ext/U.yaml b/arch/ext/U.yaml index c7c4fc2532..a3a42d8de3 100644 --- a/arch/ext/U.yaml +++ b/arch/ext/U.yaml @@ -47,4 +47,4 @@ params: without raising a trap, in which case the EEI must provide a builtin. schema: type: boolean - default: true \ No newline at end of file + default: true diff --git a/arch/ext/V.yaml b/arch/ext/V.yaml index e402906050..462b12a6dd 100644 --- a/arch/ext/V.yaml +++ b/arch/ext/V.yaml @@ -46,4 +46,4 @@ params: assert MSTATUS_VS_LEGAL_VALUES.include?(0) && MSTATUS_VS_LEGAL_VALUES.include?(3) if ext?(:V) # if HW is writing VS, then Dirty (3) better be a supported value - assert MSTATUS_VS_LEGAL_VALUES.include?(3) if ext?(:V) && (HW_MSTATUS_VS_DIRTY_UPDATE != "never") \ No newline at end of file + assert MSTATUS_VS_LEGAL_VALUES.include?(3) if ext?(:V) && (HW_MSTATUS_VS_DIRTY_UPDATE != "never") diff --git a/arch/ext/Zalrsc.yaml b/arch/ext/Zalrsc.yaml index d2d0da35f4..90043522f0 100644 --- a/arch/ext/Zalrsc.yaml +++ b/arch/ext/Zalrsc.yaml @@ -310,4 +310,4 @@ description: | starvation-freedom guarantee. However, the weaker livelock-freedom guarantee is sufficient to implement the C11 and C++11 languages, and is substantially easier to provide in some microarchitectural styles. - ==== \ No newline at end of file + ==== diff --git a/arch/ext/Zbc.yaml b/arch/ext/Zbc.yaml index 671fb9c211..1668b20427 100644 --- a/arch/ext/Zbc.yaml +++ b/arch/ext/Zbc.yaml @@ -49,5 +49,3 @@ versions: - name: Andrew Waterman - name: Thomas Wicki - name: Claire Wolf - - diff --git a/arch/ext/Zbs.yaml b/arch/ext/Zbs.yaml index ac5e678359..b7aee60c78 100644 --- a/arch/ext/Zbs.yaml +++ b/arch/ext/Zbs.yaml @@ -54,5 +54,3 @@ versions: - name: Andrew Waterman - name: Thomas Wicki - name: Claire Wolf - - diff --git a/arch/ext/Zcb.yaml b/arch/ext/Zcb.yaml index 53fb28e66f..ccd0012fcb 100644 --- a/arch/ext/Zcb.yaml +++ b/arch/ext/Zcb.yaml @@ -5,12 +5,12 @@ kind: extension name: Zcb long_name: Simple code-size saving instructions description: | - Zcb has simple code-size saving instructions which are easy to implement on all CPUs. + Zcb has simple code-size saving instructions which are easy to implement on all CPUs. All proposed encodings are currently reserved for all architectures, and have no conflicts with any existing extensions. - + The Zcb extension depends on the Zca extension. - - As shown on the individual instruction pages, many of the instructions in Zcb depend upon another extension being implemented. + + As shown on the individual instruction pages, many of the instructions in Zcb depend upon another extension being implemented. For example, c.mul is only implemented if M or Zmmul is implemented, and c.sext.b is only implemented if Zbb is implemented. type: unprivileged @@ -31,12 +31,12 @@ versions: - name: Matteo Perotti - name: Nidal Faour - name: Bill Traynor - - name: Rafael Sene + - name: Rafael Sene - name: Xinlong Wu - name: sinan - name: Jeremy Bennett - - name: Heda Chen + - name: Heda Chen - name: Alasdair Armstrong - name: Graeme Smecher - - name: Nicolas Brunie + - name: Nicolas Brunie - name: Jiawei diff --git a/arch/ext/Zfhmin.yaml b/arch/ext/Zfhmin.yaml index 2f68bfb7a5..024f43efab 100644 --- a/arch/ext/Zfhmin.yaml +++ b/arch/ext/Zfhmin.yaml @@ -50,4 +50,3 @@ versions: requires: name: F version: ">= 2.2" - diff --git a/arch/ext/Zicboz.yaml b/arch/ext/Zicboz.yaml index 84bd7cf424..343b25bafe 100644 --- a/arch/ext/Zicboz.yaml +++ b/arch/ext/Zicboz.yaml @@ -16,4 +16,4 @@ params: The observable size of a cache block, in bytes also_defined_in: [Zicbom, Zicbop] schema: - type: integer \ No newline at end of file + type: integer diff --git a/arch/ext/Zicntr.yaml b/arch/ext/Zicntr.yaml index bd791827a8..85f2ce5e2e 100644 --- a/arch/ext/Zicntr.yaml +++ b/arch/ext/Zicntr.yaml @@ -23,11 +23,11 @@ params: true:: `time`/`timeh` exists, and accessing it will not cause an IllegalInstruction trap - + false:: `time`/`timeh` does not exist. Accessing the CSR will cause an IllegalInstruction trap or enter an unpredictable state, depending on TRAP_ON_UNIMPLEMENTED_CSR. Privileged software may emulate the `time` CSR, or may pass the exception to a lower level. schema: - type: boolean \ No newline at end of file + type: boolean diff --git a/arch/ext/Zihpm.yaml b/arch/ext/Zihpm.yaml index 6b6da5dab5..f7ec3b9baa 100644 --- a/arch/ext/Zihpm.yaml +++ b/arch/ext/Zihpm.yaml @@ -10,5 +10,5 @@ versions: - version: "2.0.0" state: ratified ratification_date: unknown - requires: - name: Smhpm \ No newline at end of file + requires: + name: Smhpm diff --git a/arch/ext/Zkt.yaml b/arch/ext/Zkt.yaml index df11a4e360..d5946dd454 100644 --- a/arch/ext/Zkt.yaml +++ b/arch/ext/Zkt.yaml @@ -105,14 +105,14 @@ description: | If a secret ends up in address calculation affecting a load or store, that is a violation. If a secret affects a branch's condition, that is also a violation. A secret variable location or register becomes a non-secret via - specific zeroization/sanitisation or by being declared ciphertext + specific zeroization/sanitisation or by being declared ciphertext (or otherwise no-longer-secret information). In essence, secrets can only "touch" instructions on the Zkt list while they are secrets. == Specific Instruction Rationale * HINT instruction forms (typically encodings with `rd=x0`) are excluded from - the data-independent time requirement. + the data-independent time requirement. * Floating point (F, D, Q, L extensions) are currently excluded from the constant-time requirement as they have very few applications in standardised cryptography. We may consider adding floating point add, sub, multiply as a @@ -360,4 +360,3 @@ versions: company: name: RISC-V International url: https://riscv.org - diff --git a/arch/inst/A/amoadd.d.yaml b/arch/inst/A/amoadd.d.yaml index bbe674de1e..3d7c6b529e 100644 --- a/arch/inst/A/amoadd.d.yaml +++ b/arch/inst/A/amoadd.d.yaml @@ -6,7 +6,7 @@ name: amoadd.d long_name: Atomic fetch-and-add doubleword description: | Atomically: - + * Load the doubleword at address _rs1_ * Write the loaded value into _rd_ * Add the value of register _rs2_ to the loaded value @@ -96,7 +96,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -136,7 +136,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/A/amoadd.w.yaml b/arch/inst/A/amoadd.w.yaml index 6a70c42fbe..81938edbd3 100644 --- a/arch/inst/A/amoadd.w.yaml +++ b/arch/inst/A/amoadd.w.yaml @@ -6,7 +6,7 @@ name: amoadd.w long_name: Atomic fetch-and-add word description: | Atomically: - + * Load the word at address _rs1_ * Write the sign-extended value into _rd_ * Add the least-significant word of register _rs2_ to the loaded value @@ -95,7 +95,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -135,7 +135,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/A/amoand.d.yaml b/arch/inst/A/amoand.d.yaml index ae9d8dcfd6..3d12556b34 100644 --- a/arch/inst/A/amoand.d.yaml +++ b/arch/inst/A/amoand.d.yaml @@ -6,7 +6,7 @@ name: amoand.d long_name: Atomic fetch-and-and doubleword description: | Atomically: - + * Load the doubleword at address _rs1_ * Write the loaded value into _rd_ * AND the value of register _rs2_ to the loaded value @@ -96,7 +96,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -136,7 +136,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/A/amoand.w.yaml b/arch/inst/A/amoand.w.yaml index 485105d4f7..5125011312 100644 --- a/arch/inst/A/amoand.w.yaml +++ b/arch/inst/A/amoand.w.yaml @@ -6,7 +6,7 @@ name: amoand.w long_name: Atomic fetch-and-and word description: | Atomically: - + * Load the word at address _rs1_ * Write the sign-extended value into _rd_ * AND the least-significant word of register _rs2_ to the loaded value @@ -95,7 +95,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -135,7 +135,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/A/amomax.d.yaml b/arch/inst/A/amomax.d.yaml index a5c1109886..c223bf0177 100644 --- a/arch/inst/A/amomax.d.yaml +++ b/arch/inst/A/amomax.d.yaml @@ -6,7 +6,7 @@ name: amomax.d long_name: Atomic MAX doubleword description: | Atomically: - + * Load the doubleword at address _rs1_ * Write the loaded value into _rd_ * Signed compare the value of register _rs2_ to the loaded value, and select the maximum value @@ -96,7 +96,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -136,7 +136,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/A/amomax.w.yaml b/arch/inst/A/amomax.w.yaml index b8a5b4db7b..2f4602c7df 100644 --- a/arch/inst/A/amomax.w.yaml +++ b/arch/inst/A/amomax.w.yaml @@ -6,7 +6,7 @@ name: amomax.w long_name: Atomic MAX word description: | Atomically: - + * Load the word at address _rs1_ * Write the sign-extended value into _rd_ * Signed compare the least-significant word of register _rs2_ to the loaded value, and select the maximum value @@ -95,7 +95,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -135,7 +135,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/A/amomaxu.d.yaml b/arch/inst/A/amomaxu.d.yaml index 7ccf572b04..821ea8ea74 100644 --- a/arch/inst/A/amomaxu.d.yaml +++ b/arch/inst/A/amomaxu.d.yaml @@ -6,7 +6,7 @@ name: amomaxu.d long_name: Atomic MAX unsigned doubleword description: | Atomically: - + * Load the doubleword at address _rs1_ * Write the loaded value into _rd_ * Unsigned compare the value of register _rs2_ to the loaded value, and select the maximum value @@ -95,7 +95,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -135,7 +135,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/A/amomaxu.w.yaml b/arch/inst/A/amomaxu.w.yaml index 555a689c91..268abc22a6 100644 --- a/arch/inst/A/amomaxu.w.yaml +++ b/arch/inst/A/amomaxu.w.yaml @@ -6,7 +6,7 @@ name: amomaxu.w long_name: Atomic MAX unsigned word description: | Atomically: - + * Load the word at address _rs1_ * Write the sign-extended value into _rd_ * Unsigned compare the least-significant word of register _rs2_ to the loaded value, and select the maximum value @@ -95,7 +95,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -135,7 +135,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/A/amomin.d.yaml b/arch/inst/A/amomin.d.yaml index 367ae39b11..f111b41023 100644 --- a/arch/inst/A/amomin.d.yaml +++ b/arch/inst/A/amomin.d.yaml @@ -6,7 +6,7 @@ name: amomin.d long_name: Atomic MIN doubleword description: | Atomically: - + * Load the doubleword at address _rs1_ * Write the loaded value into _rd_ * Signed compare the value of register _rs2_ to the loaded value, and select the mimimum value @@ -96,7 +96,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -136,7 +136,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/A/amomin.w.yaml b/arch/inst/A/amomin.w.yaml index 3890b056c9..b461a48f85 100644 --- a/arch/inst/A/amomin.w.yaml +++ b/arch/inst/A/amomin.w.yaml @@ -6,7 +6,7 @@ name: amomin.w long_name: Atomic MIN word description: | Atomically: - + * Load the word at address _rs1_ * Write the sign-extended value into _rd_ * Signed compare the least-significant word of register _rs2_ to the loaded value, and select the mimimum value @@ -95,7 +95,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -135,7 +135,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/A/amominu.d.yaml b/arch/inst/A/amominu.d.yaml index 8bfc190554..3252fe8129 100644 --- a/arch/inst/A/amominu.d.yaml +++ b/arch/inst/A/amominu.d.yaml @@ -6,7 +6,7 @@ name: amominu.d long_name: Atomic MIN unsigned doubleword description: | Atomically: - + * Load the doubleword at address _rs1_ * Write the loaded value into _rd_ * Unsigned compare the value of register _rs2_ to the loaded value, and select the mimimum value @@ -96,7 +96,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -136,7 +136,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/A/amominu.w.yaml b/arch/inst/A/amominu.w.yaml index 6f41b3c645..c5eba85a8d 100644 --- a/arch/inst/A/amominu.w.yaml +++ b/arch/inst/A/amominu.w.yaml @@ -6,7 +6,7 @@ name: amominu.w long_name: Atomic MIN unsigned word description: | Atomically: - + * Load the word at address _rs1_ * Write the sign-extended value into _rd_ * Unsigned compare the least-significant word of register _rs2_ to the loaded word, and select the mimimum value @@ -95,7 +95,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -135,7 +135,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/A/amoor.d.yaml b/arch/inst/A/amoor.d.yaml index 63783db759..bb4a019e08 100644 --- a/arch/inst/A/amoor.d.yaml +++ b/arch/inst/A/amoor.d.yaml @@ -6,7 +6,7 @@ name: amoor.d long_name: Atomic fetch-and-or doubleword description: | Atomically: - + * Load the doubleword at address _rs1_ * Write the loaded value into _rd_ * OR the value of register _rs2_ to the loaded value @@ -96,7 +96,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -136,7 +136,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/A/amoor.w.yaml b/arch/inst/A/amoor.w.yaml index ecde879fa6..bd31b909f8 100644 --- a/arch/inst/A/amoor.w.yaml +++ b/arch/inst/A/amoor.w.yaml @@ -6,7 +6,7 @@ name: amoor.w long_name: Atomic fetch-and-or word description: | Atomically: - + * Load the word at address _rs1_ * Write the sign-extended value into _rd_ * OR the least-significant word of register _rs2_ to the loaded value @@ -95,7 +95,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -135,7 +135,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/A/amoswap.d.yaml b/arch/inst/A/amoswap.d.yaml index 6fe322a4c7..e6f065534d 100644 --- a/arch/inst/A/amoswap.d.yaml +++ b/arch/inst/A/amoswap.d.yaml @@ -6,7 +6,7 @@ name: amoswap.d long_name: Atomic SWAP doubleword description: | Atomically: - + * Load the doubleword at address _rs1_ * Write the value into _rd_ * Store the value of register _rs2_ to the address in _rs1_ @@ -95,7 +95,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -135,7 +135,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/A/amoswap.w.yaml b/arch/inst/A/amoswap.w.yaml index 224a7d1733..152b663b65 100644 --- a/arch/inst/A/amoswap.w.yaml +++ b/arch/inst/A/amoswap.w.yaml @@ -6,7 +6,7 @@ name: amoswap.w long_name: Atomic SWAP word description: | Atomically: - + * Load the word at address _rs1_ * Write the sign-extended value into _rd_ * Store the least-significant word of register _rs2_ to the address in _rs1_ @@ -94,7 +94,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -134,7 +134,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/A/amoxor.d.yaml b/arch/inst/A/amoxor.d.yaml index fecb968437..a47e9373c6 100644 --- a/arch/inst/A/amoxor.d.yaml +++ b/arch/inst/A/amoxor.d.yaml @@ -6,7 +6,7 @@ name: amoxor.d long_name: Atomic fetch-and-xor doubleword description: | Atomically: - + * Load the doubleword at address _rs1_ * Write the loaded value into _rd_ * XOR the value of register _rs2_ to the loaded value @@ -96,7 +96,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -136,7 +136,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/A/amoxor.w.yaml b/arch/inst/A/amoxor.w.yaml index e299f6350a..1c262bd09b 100644 --- a/arch/inst/A/amoxor.w.yaml +++ b/arch/inst/A/amoxor.w.yaml @@ -6,7 +6,7 @@ name: amoxor.w long_name: Atomic fetch-and-xor word description: | Atomically: - + * Load the word at address _rs1_ * Write the sign-extended value into _rd_ * XOR the least-significant word of register _rs2_ to the loaded value @@ -95,7 +95,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -135,7 +135,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/A/lr.d.yaml b/arch/inst/A/lr.d.yaml index ca7b2288ec..4844143e8b 100644 --- a/arch/inst/A/lr.d.yaml +++ b/arch/inst/A/lr.d.yaml @@ -135,7 +135,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/A/lr.w.yaml b/arch/inst/A/lr.w.yaml index 0ae9dd0c88..883fedf190 100644 --- a/arch/inst/A/lr.w.yaml +++ b/arch/inst/A/lr.w.yaml @@ -144,7 +144,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/A/sc.d.yaml b/arch/inst/A/sc.d.yaml index 72a0a79f37..3f55a4ec77 100644 --- a/arch/inst/A/sc.d.yaml +++ b/arch/inst/A/sc.d.yaml @@ -228,7 +228,3 @@ sail(): | } } } - - - - diff --git a/arch/inst/A/sc.w.yaml b/arch/inst/A/sc.w.yaml index c8dcac7147..fc29cbc00d 100644 --- a/arch/inst/A/sc.w.yaml +++ b/arch/inst/A/sc.w.yaml @@ -234,7 +234,3 @@ sail(): | } } } - - - - diff --git a/arch/inst/B/add.uw.yaml b/arch/inst/B/add.uw.yaml index c079072064..f8aedbf6db 100644 --- a/arch/inst/B/add.uw.yaml +++ b/arch/inst/B/add.uw.yaml @@ -51,7 +51,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/andn.yaml b/arch/inst/B/andn.yaml index 9de7b36a2f..c377ce8a19 100644 --- a/arch/inst/B/andn.yaml +++ b/arch/inst/B/andn.yaml @@ -56,7 +56,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/bclr.yaml b/arch/inst/B/bclr.yaml index b6b8117f7e..03ebc50ba9 100644 --- a/arch/inst/B/bclr.yaml +++ b/arch/inst/B/bclr.yaml @@ -50,7 +50,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/bclri.yaml b/arch/inst/B/bclri.yaml index c718e3cf5b..7c270a8996 100644 --- a/arch/inst/B/bclri.yaml +++ b/arch/inst/B/bclri.yaml @@ -60,7 +60,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/bext.yaml b/arch/inst/B/bext.yaml index 4d3b4caf7f..92ea15b8f9 100644 --- a/arch/inst/B/bext.yaml +++ b/arch/inst/B/bext.yaml @@ -50,7 +50,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/bexti.yaml b/arch/inst/B/bexti.yaml index fbb2705c5c..44b5687851 100644 --- a/arch/inst/B/bexti.yaml +++ b/arch/inst/B/bexti.yaml @@ -60,7 +60,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/binv.yaml b/arch/inst/B/binv.yaml index 8390947af5..40262f63b5 100644 --- a/arch/inst/B/binv.yaml +++ b/arch/inst/B/binv.yaml @@ -50,7 +50,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/binvi.yaml b/arch/inst/B/binvi.yaml index cd9be980be..ac23c57758 100644 --- a/arch/inst/B/binvi.yaml +++ b/arch/inst/B/binvi.yaml @@ -60,7 +60,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/bset.yaml b/arch/inst/B/bset.yaml index 5cf11e49f8..c0a5e04275 100644 --- a/arch/inst/B/bset.yaml +++ b/arch/inst/B/bset.yaml @@ -50,7 +50,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/bseti.yaml b/arch/inst/B/bseti.yaml index 84466cdded..9b9e69307f 100644 --- a/arch/inst/B/bseti.yaml +++ b/arch/inst/B/bseti.yaml @@ -60,7 +60,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/clmul.yaml b/arch/inst/B/clmul.yaml index 42c1040251..73529d0434 100644 --- a/arch/inst/B/clmul.yaml +++ b/arch/inst/B/clmul.yaml @@ -53,7 +53,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/clmulh.yaml b/arch/inst/B/clmulh.yaml index d93284718d..44b695eaf6 100644 --- a/arch/inst/B/clmulh.yaml +++ b/arch/inst/B/clmulh.yaml @@ -53,7 +53,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/clmulr.yaml b/arch/inst/B/clmulr.yaml index 249382ceb3..7a4033f8a2 100644 --- a/arch/inst/B/clmulr.yaml +++ b/arch/inst/B/clmulr.yaml @@ -52,7 +52,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/clz.yaml b/arch/inst/B/clz.yaml index f17057957d..4349b7bdab 100644 --- a/arch/inst/B/clz.yaml +++ b/arch/inst/B/clz.yaml @@ -45,7 +45,3 @@ sail(): | X(rd) = to_bits(sizeof(xlen), result); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/clzw.yaml b/arch/inst/B/clzw.yaml index 7c5b6224ac..d0ede84fc3 100644 --- a/arch/inst/B/clzw.yaml +++ b/arch/inst/B/clzw.yaml @@ -45,7 +45,3 @@ sail(): | X(rd) = to_bits(sizeof(xlen), result); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/cpop.yaml b/arch/inst/B/cpop.yaml index a095246001..cb9d5a6fea 100644 --- a/arch/inst/B/cpop.yaml +++ b/arch/inst/B/cpop.yaml @@ -60,7 +60,3 @@ sail(): | X(rd) = to_bits(sizeof(xlen), result); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/cpopw.yaml b/arch/inst/B/cpopw.yaml index 59e65f41de..f061ae07be 100644 --- a/arch/inst/B/cpopw.yaml +++ b/arch/inst/B/cpopw.yaml @@ -61,7 +61,3 @@ sail(): | X(rd) = to_bits(sizeof(xlen), result); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/ctz.yaml b/arch/inst/B/ctz.yaml index 848c323528..d39a0f351f 100644 --- a/arch/inst/B/ctz.yaml +++ b/arch/inst/B/ctz.yaml @@ -46,7 +46,3 @@ sail(): | X(rd) = to_bits(sizeof(xlen), result); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/ctzw.yaml b/arch/inst/B/ctzw.yaml index 1ef0981512..97ac4ee965 100644 --- a/arch/inst/B/ctzw.yaml +++ b/arch/inst/B/ctzw.yaml @@ -47,7 +47,3 @@ sail(): | X(rd) = to_bits(sizeof(xlen), result); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/max.yaml b/arch/inst/B/max.yaml index a612ff2821..aab1741110 100644 --- a/arch/inst/B/max.yaml +++ b/arch/inst/B/max.yaml @@ -62,7 +62,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/maxu.yaml b/arch/inst/B/maxu.yaml index bc8e602828..d2cb26ff25 100644 --- a/arch/inst/B/maxu.yaml +++ b/arch/inst/B/maxu.yaml @@ -54,7 +54,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/min.yaml b/arch/inst/B/min.yaml index 0735729634..b7e838fd91 100644 --- a/arch/inst/B/min.yaml +++ b/arch/inst/B/min.yaml @@ -54,7 +54,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/minu.yaml b/arch/inst/B/minu.yaml index 1d4966312b..3a0038c2cd 100644 --- a/arch/inst/B/minu.yaml +++ b/arch/inst/B/minu.yaml @@ -54,7 +54,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/orc.b.yaml b/arch/inst/B/orc.b.yaml index ccb867b57c..6fdedd6265 100644 --- a/arch/inst/B/orc.b.yaml +++ b/arch/inst/B/orc.b.yaml @@ -50,7 +50,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/orn.yaml b/arch/inst/B/orn.yaml index ba06cea155..50f45f0c4d 100644 --- a/arch/inst/B/orn.yaml +++ b/arch/inst/B/orn.yaml @@ -55,7 +55,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/rev8.yaml b/arch/inst/B/rev8.yaml index d2e50680aa..9506294256 100644 --- a/arch/inst/B/rev8.yaml +++ b/arch/inst/B/rev8.yaml @@ -66,7 +66,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/rol.yaml b/arch/inst/B/rol.yaml index f65cf35fa8..251f039bf2 100644 --- a/arch/inst/B/rol.yaml +++ b/arch/inst/B/rol.yaml @@ -57,7 +57,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/rolw.yaml b/arch/inst/B/rolw.yaml index 105f568bae..daadd41df7 100644 --- a/arch/inst/B/rolw.yaml +++ b/arch/inst/B/rolw.yaml @@ -51,7 +51,3 @@ sail(): | X(rd) = sign_extend(result); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/ror.yaml b/arch/inst/B/ror.yaml index a7be3ba466..1d75f3112e 100644 --- a/arch/inst/B/ror.yaml +++ b/arch/inst/B/ror.yaml @@ -57,7 +57,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/rori.yaml b/arch/inst/B/rori.yaml index 1feba8327a..e664533739 100644 --- a/arch/inst/B/rori.yaml +++ b/arch/inst/B/rori.yaml @@ -55,7 +55,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/roriw.yaml b/arch/inst/B/roriw.yaml index 7967bc1967..df7da5ab39 100644 --- a/arch/inst/B/roriw.yaml +++ b/arch/inst/B/roriw.yaml @@ -46,7 +46,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/rorw.yaml b/arch/inst/B/rorw.yaml index 9f25c3dc67..62f4036d11 100644 --- a/arch/inst/B/rorw.yaml +++ b/arch/inst/B/rorw.yaml @@ -51,7 +51,3 @@ sail(): | X(rd) = sign_extend(result); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/sext.b.yaml b/arch/inst/B/sext.b.yaml index 6a7a2018ed..a4d2a4bd47 100644 --- a/arch/inst/B/sext.b.yaml +++ b/arch/inst/B/sext.b.yaml @@ -46,7 +46,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/sext.h.yaml b/arch/inst/B/sext.h.yaml index 2ceef5be84..fe2054f4fa 100644 --- a/arch/inst/B/sext.h.yaml +++ b/arch/inst/B/sext.h.yaml @@ -46,7 +46,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/sh1add.uw.yaml b/arch/inst/B/sh1add.uw.yaml index f85bdb29f8..1d5ee52990 100644 --- a/arch/inst/B/sh1add.uw.yaml +++ b/arch/inst/B/sh1add.uw.yaml @@ -49,7 +49,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/sh1add.yaml b/arch/inst/B/sh1add.yaml index 472dd48b5f..88c89a1e70 100644 --- a/arch/inst/B/sh1add.yaml +++ b/arch/inst/B/sh1add.yaml @@ -45,7 +45,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/sh2add.uw.yaml b/arch/inst/B/sh2add.uw.yaml index a6b6c975d9..2256b8ff91 100644 --- a/arch/inst/B/sh2add.uw.yaml +++ b/arch/inst/B/sh2add.uw.yaml @@ -49,7 +49,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/sh2add.yaml b/arch/inst/B/sh2add.yaml index 952799354f..e0c7e3cc57 100644 --- a/arch/inst/B/sh2add.yaml +++ b/arch/inst/B/sh2add.yaml @@ -45,7 +45,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/sh3add.uw.yaml b/arch/inst/B/sh3add.uw.yaml index 7a64f8049f..9cc2a29a0f 100644 --- a/arch/inst/B/sh3add.uw.yaml +++ b/arch/inst/B/sh3add.uw.yaml @@ -49,7 +49,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/sh3add.yaml b/arch/inst/B/sh3add.yaml index 6f84c5308c..ace5749ef6 100644 --- a/arch/inst/B/sh3add.yaml +++ b/arch/inst/B/sh3add.yaml @@ -45,7 +45,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/slli.uw.yaml b/arch/inst/B/slli.uw.yaml index 98e77bad05..47c9d7d5d4 100644 --- a/arch/inst/B/slli.uw.yaml +++ b/arch/inst/B/slli.uw.yaml @@ -44,7 +44,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/xnor.yaml b/arch/inst/B/xnor.yaml index 9c5444c3c9..fc64d5e2ee 100644 --- a/arch/inst/B/xnor.yaml +++ b/arch/inst/B/xnor.yaml @@ -55,7 +55,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/B/zext.h.yaml b/arch/inst/B/zext.h.yaml index 52c255a379..4e1b492f9f 100644 --- a/arch/inst/B/zext.h.yaml +++ b/arch/inst/B/zext.h.yaml @@ -30,8 +30,8 @@ encoding: location: 19-15 - name: rd location: 11-7 -excludedBy: - anyOf: [Zk, Zkn, Zks, Zbkb] # zext.h instruction is a pseudo-op for `packw` when `Zbkb` is implemented +excludedBy: + anyOf: [Zk, Zkn, Zks, Zbkb] # zext.h instruction is a pseudo-op for `packw` when `Zbkb` is implemented assembly: xd, xs1 access: s: always @@ -58,7 +58,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/C/c.add.yaml b/arch/inst/C/c.add.yaml index 0c67ee6727..678dfbb14a 100644 --- a/arch/inst/C/c.add.yaml +++ b/arch/inst/C/c.add.yaml @@ -6,7 +6,7 @@ name: c.add long_name: Add description: | Add the value in rs2 to rd, and store the result in rd. - C.ADD expands into `add rd, rd, rs2`. + C.ADD expands into `add rd, rd, rs2`. definedBy: anyOf: - C diff --git a/arch/inst/C/c.addi.yaml b/arch/inst/C/c.addi.yaml index aaab1d7070..445543b1be 100644 --- a/arch/inst/C/c.addi.yaml +++ b/arch/inst/C/c.addi.yaml @@ -6,8 +6,8 @@ name: c.addi long_name: Add a sign-extended non-zero immediate description: | C.ADDI adds the non-zero sign-extended 6-bit immediate to the value in register rd then writes the result to rd. - C.ADDI expands into `addi rd, rd, imm`. - C.ADDI is only valid when rd ≠ x0 and imm ≠ 0. + C.ADDI expands into `addi rd, rd, imm`. + C.ADDI is only valid when rd ≠ x0 and imm ≠ 0. The code points with rd=x0 encode the C.NOP instruction; the remaining code points with imm=0 encode HINTs. definedBy: anyOf: @@ -34,4 +34,3 @@ operation(): | } X[rd] = X[rd] + imm; - diff --git a/arch/inst/C/c.addi16sp.yaml b/arch/inst/C/c.addi16sp.yaml index d83c81825e..5b3e531966 100644 --- a/arch/inst/C/c.addi16sp.yaml +++ b/arch/inst/C/c.addi16sp.yaml @@ -5,9 +5,9 @@ kind: instruction name: c.addi16sp long_name: Add a sign-extended non-zero immediate description: | - C.ADDI16SP adds the non-zero sign-extended 6-bit immediate to the value in the stack pointer (sp=x2), where the immediate is scaled to represent multiples of 16 in the range (-512,496). - C.ADDI16SP is used to adjust the stack pointer in procedure prologues and epilogues. - It expands into `addi x2, x2, nzimm[9:4]`. + C.ADDI16SP adds the non-zero sign-extended 6-bit immediate to the value in the stack pointer (sp=x2), where the immediate is scaled to represent multiples of 16 in the range (-512,496). + C.ADDI16SP is used to adjust the stack pointer in procedure prologues and epilogues. + It expands into `addi x2, x2, nzimm[9:4]`. C.ADDI16SP is only valid when nzimm ≠ 0; the code point with nzimm=0 is reserved. definedBy: anyOf: @@ -32,4 +32,3 @@ operation(): | } X[2] = X[2] + imm; - diff --git a/arch/inst/C/c.addi4spn.yaml b/arch/inst/C/c.addi4spn.yaml index e1a102e3c5..d51063be99 100644 --- a/arch/inst/C/c.addi4spn.yaml +++ b/arch/inst/C/c.addi4spn.yaml @@ -5,9 +5,9 @@ kind: instruction name: c.addi4spn long_name: Add a zero-extended non-zero immediate, scaled by 4, to the stack pointer description: | - Adds a zero-extended non-zero immediate, scaled by 4, to the stack pointer, x2, and writes the result to rd'. + Adds a zero-extended non-zero immediate, scaled by 4, to the stack pointer, x2, and writes the result to rd'. This instruction is used to generate pointers to stack-allocated variables. - It expands to `addi rd', x2, nzuimm[9:2]`. + It expands to `addi rd', x2, nzuimm[9:2]`. C.ADDI4SPN is only valid when nzuimm ≠ 0; the code points with nzuimm=0 are reserved. definedBy: anyOf: @@ -34,4 +34,3 @@ operation(): | } X[rd+8] = X[2] + imm; - diff --git a/arch/inst/C/c.addiw.yaml b/arch/inst/C/c.addiw.yaml index 41da2cf8c9..a5c8220c9f 100644 --- a/arch/inst/C/c.addiw.yaml +++ b/arch/inst/C/c.addiw.yaml @@ -5,9 +5,9 @@ kind: instruction name: c.addiw long_name: Add a sign-extended non-zero immediate description: | - C.ADDIW is an RV64C/RV128C-only instruction that performs the same computation as C.ADDI but produces a 32-bit result, then sign-extends result to 64 bits. - C.ADDIW expands into `addiw rd, rd, imm`. - The immediate can be zero for C.ADDIW, where this corresponds to `sext.w rd`. + C.ADDIW is an RV64C/RV128C-only instruction that performs the same computation as C.ADDI but produces a 32-bit result, then sign-extends result to 64 bits. + C.ADDIW expands into `addiw rd, rd, imm`. + The immediate can be zero for C.ADDIW, where this corresponds to `sext.w rd`. C.ADDIW is only valid when rd ≠ x0; the code points with rd=x0 are reserved. definedBy: anyOf: @@ -34,4 +34,3 @@ operation(): | } X[rd] = sext((X[rd] + imm), 32); - diff --git a/arch/inst/C/c.addw.yaml b/arch/inst/C/c.addw.yaml index ec8fe7e01e..61ba1a41f0 100644 --- a/arch/inst/C/c.addw.yaml +++ b/arch/inst/C/c.addw.yaml @@ -7,7 +7,7 @@ long_name: Add word description: | Add the 32-bit values in rs2 from rd, and store the result in rd. The rd and rs2 register indexes should be used as rd+8 and rs2+8 (registers x8-x15). - C.ADDW expands into `addw rd, rd, rs2`. + C.ADDW expands into `addw rd, rd, rs2`. definedBy: anyOf: - C diff --git a/arch/inst/C/c.and.yaml b/arch/inst/C/c.and.yaml index 16914a3712..6f365559b7 100644 --- a/arch/inst/C/c.and.yaml +++ b/arch/inst/C/c.and.yaml @@ -7,7 +7,7 @@ long_name: And description: | And rd with rs2, and store the result in rd The rd and rs2 register indexes should be used as rd+8 and rs2+8 (registers x8-x15). - C.AND expands into `and rd, rd, rs2`. + C.AND expands into `and rd, rd, rs2`. definedBy: anyOf: - C diff --git a/arch/inst/C/c.andi.yaml b/arch/inst/C/c.andi.yaml index 53eb4d142a..c32f5f8e70 100644 --- a/arch/inst/C/c.andi.yaml +++ b/arch/inst/C/c.andi.yaml @@ -7,7 +7,7 @@ long_name: And immediate description: | And an immediate to the value in rd, and store the result in rd. The rd register index should be used as rd+8 (registers x8-x15). - C.ANDI expands into `andi rd, rd, imm`. + C.ANDI expands into `andi rd, rd, imm`. definedBy: anyOf: - C diff --git a/arch/inst/C/c.beqz.yaml b/arch/inst/C/c.beqz.yaml index b8492708ee..75d88ee548 100644 --- a/arch/inst/C/c.beqz.yaml +++ b/arch/inst/C/c.beqz.yaml @@ -5,7 +5,7 @@ kind: instruction name: c.beqz long_name: Branch if Equal Zero description: | - C.BEQZ performs conditional control transfers. The offset is sign-extended and added to the pc to form the branch target address. It can therefore target a ±256 B range. C.BEQZ takes the branch if the value in register rs1' is zero. + C.BEQZ performs conditional control transfers. The offset is sign-extended and added to the pc to form the branch target address. It can therefore target a ±256 B range. C.BEQZ takes the branch if the value in register rs1' is zero. It expands to `beq` `rs1, x0, offset`. definedBy: anyOf: diff --git a/arch/inst/C/c.bnez.yaml b/arch/inst/C/c.bnez.yaml index df99127508..91ee35e96d 100644 --- a/arch/inst/C/c.bnez.yaml +++ b/arch/inst/C/c.bnez.yaml @@ -5,7 +5,7 @@ kind: instruction name: c.bnez long_name: Branch if NOT Equal Zero description: | - C.BEQZ performs conditional control transfers. The offset is sign-extended and added to the pc to form the branch target address. It can therefore target a ±256 B range. C.BEQZ takes the branch if the value in register rs1' is NOT zero. + C.BEQZ performs conditional control transfers. The offset is sign-extended and added to the pc to form the branch target address. It can therefore target a ±256 B range. C.BEQZ takes the branch if the value in register rs1' is NOT zero. It expands to `beq` `rs1, x0, offset`. definedBy: anyOf: diff --git a/arch/inst/C/c.fld.yaml b/arch/inst/C/c.fld.yaml index 524c727e10..4e2c54bca7 100644 --- a/arch/inst/C/c.fld.yaml +++ b/arch/inst/C/c.fld.yaml @@ -3,7 +3,7 @@ $schema: "inst_schema.json#" kind: instruction name: c.fld -long_name: Load double-precision +long_name: Load double-precision description: | Loads a double precision floating-point value from memory into register rd. It computes an effective address by adding the zero-extended offset, scaled by 8, diff --git a/arch/inst/C/c.flw.yaml b/arch/inst/C/c.flw.yaml index 44d121ea6b..e99c975c33 100644 --- a/arch/inst/C/c.flw.yaml +++ b/arch/inst/C/c.flw.yaml @@ -3,7 +3,7 @@ $schema: "inst_schema.json#" kind: instruction name: c.flw -long_name: Load single-precision +long_name: Load single-precision description: | Loads a single precision floating-point value from memory into register rd. It computes an effective address by adding the zero-extended offset, scaled by 4, diff --git a/arch/inst/C/c.fsd.yaml b/arch/inst/C/c.fsd.yaml index 4531761b99..b16493053c 100644 --- a/arch/inst/C/c.fsd.yaml +++ b/arch/inst/C/c.fsd.yaml @@ -3,7 +3,7 @@ $schema: "inst_schema.json#" kind: instruction name: c.fsd -long_name: Store double-precision +long_name: Store double-precision description: | Stores a double precision floating-point value in register rs2 to memory. It computes an effective address by adding the zero-extended offset, scaled by 8, diff --git a/arch/inst/C/c.fsw.yaml b/arch/inst/C/c.fsw.yaml index e7f2586342..b50f1f2574 100644 --- a/arch/inst/C/c.fsw.yaml +++ b/arch/inst/C/c.fsw.yaml @@ -3,7 +3,7 @@ $schema: "inst_schema.json#" kind: instruction name: c.fsw -long_name: Store single-precision +long_name: Store single-precision description: | Stores a single precision floating-point value in register rs2 to memory. It computes an effective address by adding the zero-extended offset, scaled by 4, diff --git a/arch/inst/C/c.jr.yaml b/arch/inst/C/c.jr.yaml index 6342aa3f96..97ede06383 100644 --- a/arch/inst/C/c.jr.yaml +++ b/arch/inst/C/c.jr.yaml @@ -5,7 +5,7 @@ kind: instruction name: c.jr long_name: Jump Register description: | - C.JR (jump register) performs an unconditional control transfer to the address in register rs1. + C.JR (jump register) performs an unconditional control transfer to the address in register rs1. C.JR expands to jalr x0, 0(rs1). definedBy: anyOf: diff --git a/arch/inst/C/c.li.yaml b/arch/inst/C/c.li.yaml index a18ea1bab4..e162bc7fb2 100644 --- a/arch/inst/C/c.li.yaml +++ b/arch/inst/C/c.li.yaml @@ -5,8 +5,8 @@ kind: instruction name: c.li long_name: Load the sign-extended 6-bit immediate description: | - C.LI loads the sign-extended 6-bit immediate, imm, into register rd. - C.LI expands into `addi rd, x0, imm`. + C.LI loads the sign-extended 6-bit immediate, imm, into register rd. + C.LI expands into `addi rd, x0, imm`. C.LI is only valid when rd ≠ x0; the code points with rd=x0 encode HINTs. definedBy: anyOf: @@ -32,4 +32,3 @@ operation(): | } X[rd] = imm; - diff --git a/arch/inst/C/c.lui.yaml b/arch/inst/C/c.lui.yaml index 515c277ddd..85c946574a 100644 --- a/arch/inst/C/c.lui.yaml +++ b/arch/inst/C/c.lui.yaml @@ -5,9 +5,9 @@ kind: instruction name: c.lui long_name: Load the non-zero 6-bit immediate field into bits 17-12 of the destination register description: | - C.LUI loads the non-zero 6-bit immediate field into bits 17-12 of the destination register, clears the bottom 12 bits, and sign-extends bit 17 into all higher bits of the destination. - C.LUI expands into `lui rd, imm`. - C.LUI is only valid when rd≠x0 and rd≠x2, and when the immediate is not equal to zero. + C.LUI loads the non-zero 6-bit immediate field into bits 17-12 of the destination register, clears the bottom 12 bits, and sign-extends bit 17 into all higher bits of the destination. + C.LUI expands into `lui rd, imm`. + C.LUI is only valid when rd≠x0 and rd≠x2, and when the immediate is not equal to zero. The code points with imm=0 are reserved; the remaining code points with rd=x0 are HINTs; and the remaining code points with rd=x2 correspond to the C.ADDI16SP instruction definedBy: anyOf: @@ -34,4 +34,3 @@ operation(): | } X[rd] = imm; - diff --git a/arch/inst/C/c.lw.yaml b/arch/inst/C/c.lw.yaml index 0fa1b48f42..91c2d3a60f 100644 --- a/arch/inst/C/c.lw.yaml +++ b/arch/inst/C/c.lw.yaml @@ -3,7 +3,7 @@ $schema: "inst_schema.json#" kind: instruction name: c.lw -long_name: Load word +long_name: Load word description: | Loads a 32-bit value from memory into register rd. It computes an effective address by adding the zero-extended offset, scaled by 4, diff --git a/arch/inst/C/c.nop.yaml b/arch/inst/C/c.nop.yaml index 9fb3e794bb..804e23ed07 100644 --- a/arch/inst/C/c.nop.yaml +++ b/arch/inst/C/c.nop.yaml @@ -5,7 +5,7 @@ kind: instruction name: c.nop long_name: Non-operation description: | - C.NOP expands into `addi x0, x0, imm`. + C.NOP expands into `addi x0, x0, imm`. definedBy: anyOf: - C @@ -26,4 +26,3 @@ operation(): | if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) { raise(ExceptionCode::IllegalInstruction, mode(), $encoding); } - diff --git a/arch/inst/C/c.or.yaml b/arch/inst/C/c.or.yaml index f6899d9aa8..29c2e379af 100644 --- a/arch/inst/C/c.or.yaml +++ b/arch/inst/C/c.or.yaml @@ -7,7 +7,7 @@ long_name: Or description: | Or rd with rs2, and store the result in rd The rd and rs2 register indexes should be used as rd+8 and rs2+8 (registers x8-x15). - C.OR expands into `or rd, rd, rs2`. + C.OR expands into `or rd, rd, rs2`. definedBy: anyOf: - C diff --git a/arch/inst/C/c.sd.yaml b/arch/inst/C/c.sd.yaml index b9cf43c0a9..ccb9b2d841 100644 --- a/arch/inst/C/c.sd.yaml +++ b/arch/inst/C/c.sd.yaml @@ -3,7 +3,7 @@ $schema: "inst_schema.json#" kind: instruction name: c.sd -long_name: Store double +long_name: Store double description: | Stores a 64-bit value in register rs2 to memory. It computes an effective address by adding the zero-extended offset, scaled by 8, diff --git a/arch/inst/C/c.slli.yaml b/arch/inst/C/c.slli.yaml index 6769be23b6..34457091fe 100644 --- a/arch/inst/C/c.slli.yaml +++ b/arch/inst/C/c.slli.yaml @@ -6,7 +6,7 @@ name: c.slli long_name: Shift left logical immediate description: | Shift the value in rd left by shamt, and store the result back in rd. - C.SLLI expands into `slli rd, rd, shamt`. + C.SLLI expands into `slli rd, rd, shamt`. definedBy: anyOf: - C @@ -47,7 +47,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/C/c.srai.yaml b/arch/inst/C/c.srai.yaml index e0b42444a8..1f3a70b164 100644 --- a/arch/inst/C/c.srai.yaml +++ b/arch/inst/C/c.srai.yaml @@ -7,7 +7,7 @@ long_name: Shift right arithmetical immediate description: | Arithmetic shift (the original sign bit is copied into the vacated upper bits) the value in rd right by shamt, and store the result in rd. The rd register index should be used as rd+8 (registers x8-x15). - C.SRAI expands into `srai rd, rd, shamt`. + C.SRAI expands into `srai rd, rd, shamt`. definedBy: anyOf: - C diff --git a/arch/inst/C/c.srli.yaml b/arch/inst/C/c.srli.yaml index 63a1a35d7a..51b246f48b 100644 --- a/arch/inst/C/c.srli.yaml +++ b/arch/inst/C/c.srli.yaml @@ -7,7 +7,7 @@ long_name: Shift right logical immediate description: | Shift the value in rd right by shamt, and store the result back in rd. The rd register index should be used as rd+8 (registers x8-x15). - C.SRLI expands into `srli rd, rd, shamt`. + C.SRLI expands into `srli rd, rd, shamt`. definedBy: anyOf: - C @@ -47,7 +47,3 @@ sail(): | X(rd+8) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/C/c.sub.yaml b/arch/inst/C/c.sub.yaml index 36f233523f..60af66e88e 100644 --- a/arch/inst/C/c.sub.yaml +++ b/arch/inst/C/c.sub.yaml @@ -7,7 +7,7 @@ long_name: Subtract description: | Subtract the value in rs2 from rd, and store the result in rd. The rd and rs2 register indexes should be used as rd+8 and rs2+8 (registers x8-x15). - C.SUB expands into `sub rd, rd, rs2`. + C.SUB expands into `sub rd, rd, rs2`. definedBy: anyOf: - C diff --git a/arch/inst/C/c.subw.yaml b/arch/inst/C/c.subw.yaml index 40c047a137..2e45ead861 100644 --- a/arch/inst/C/c.subw.yaml +++ b/arch/inst/C/c.subw.yaml @@ -7,7 +7,7 @@ long_name: Subtract word description: | Subtract the 32-bit values in rs2 from rd, and store the result in rd. The rd and rs2 register indexes should be used as rd+8 and rs2+8 (registers x8-x15). - C.SUBW expands into `subw rd, rd, rs2`. + C.SUBW expands into `subw rd, rd, rs2`. definedBy: anyOf: - C diff --git a/arch/inst/C/c.sw.yaml b/arch/inst/C/c.sw.yaml index c4a7d08583..2717ce020e 100644 --- a/arch/inst/C/c.sw.yaml +++ b/arch/inst/C/c.sw.yaml @@ -3,7 +3,7 @@ $schema: "inst_schema.json#" kind: instruction name: c.sw -long_name: Store word +long_name: Store word description: | Stores a 32-bit value in register rs2 to memory. It computes an effective address by adding the zero-extended offset, scaled by 4, diff --git a/arch/inst/C/c.xor.yaml b/arch/inst/C/c.xor.yaml index f15a3bae91..ca04d2a183 100644 --- a/arch/inst/C/c.xor.yaml +++ b/arch/inst/C/c.xor.yaml @@ -7,7 +7,7 @@ long_name: Exclusive Or description: | Exclusive or rd with rs2, and store the result in rd The rd and rs2 register indexes should be used as rd+8 and rs2+8 (registers x8-x15). - C.XOR expands into `xor rd, rd, rs2`. + C.XOR expands into `xor rd, rd, rs2`. definedBy: anyOf: - C diff --git a/arch/inst/D/fadd.d.yaml b/arch/inst/D/fadd.d.yaml index 263afe6565..78b384072f 100644 --- a/arch/inst/D/fadd.d.yaml +++ b/arch/inst/D/fadd.d.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fclass.d.yaml b/arch/inst/D/fclass.d.yaml index 5deb39d6ed..06bd14a880 100644 --- a/arch/inst/D/fclass.d.yaml +++ b/arch/inst/D/fclass.d.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fcvt.d.l.yaml b/arch/inst/D/fcvt.d.l.yaml index 2e5f4dc447..1754fe9c3a 100644 --- a/arch/inst/D/fcvt.d.l.yaml +++ b/arch/inst/D/fcvt.d.l.yaml @@ -25,4 +25,3 @@ access: data_independent_timing: false base: 64 operation(): | - diff --git a/arch/inst/D/fcvt.d.lu.yaml b/arch/inst/D/fcvt.d.lu.yaml index 9668ee9217..71cc3e6ecf 100644 --- a/arch/inst/D/fcvt.d.lu.yaml +++ b/arch/inst/D/fcvt.d.lu.yaml @@ -25,4 +25,3 @@ access: data_independent_timing: false base: 64 operation(): | - diff --git a/arch/inst/D/fcvt.d.s.yaml b/arch/inst/D/fcvt.d.s.yaml index ca93fa3b1c..19fd2e7d7f 100644 --- a/arch/inst/D/fcvt.d.s.yaml +++ b/arch/inst/D/fcvt.d.s.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fcvt.d.w.yaml b/arch/inst/D/fcvt.d.w.yaml index 779e777498..cefecd9309 100644 --- a/arch/inst/D/fcvt.d.w.yaml +++ b/arch/inst/D/fcvt.d.w.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fcvt.d.wu.yaml b/arch/inst/D/fcvt.d.wu.yaml index 897637dd77..9a05ce0389 100644 --- a/arch/inst/D/fcvt.d.wu.yaml +++ b/arch/inst/D/fcvt.d.wu.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fcvt.l.d.yaml b/arch/inst/D/fcvt.l.d.yaml index 3cfa12beac..20352af5dc 100644 --- a/arch/inst/D/fcvt.l.d.yaml +++ b/arch/inst/D/fcvt.l.d.yaml @@ -25,4 +25,3 @@ access: data_independent_timing: false base: 64 operation(): | - diff --git a/arch/inst/D/fcvt.lu.d.yaml b/arch/inst/D/fcvt.lu.d.yaml index aecb2ca0e2..f2e1f103ef 100644 --- a/arch/inst/D/fcvt.lu.d.yaml +++ b/arch/inst/D/fcvt.lu.d.yaml @@ -25,4 +25,3 @@ access: data_independent_timing: false base: 64 operation(): | - diff --git a/arch/inst/D/fcvt.s.d.yaml b/arch/inst/D/fcvt.s.d.yaml index 88d599d53d..6f69d76383 100644 --- a/arch/inst/D/fcvt.s.d.yaml +++ b/arch/inst/D/fcvt.s.d.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fcvt.w.d.yaml b/arch/inst/D/fcvt.w.d.yaml index e2714af755..243fc56946 100644 --- a/arch/inst/D/fcvt.w.d.yaml +++ b/arch/inst/D/fcvt.w.d.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fcvt.wu.d.yaml b/arch/inst/D/fcvt.wu.d.yaml index 59a3ed84d2..abd390d4d1 100644 --- a/arch/inst/D/fcvt.wu.d.yaml +++ b/arch/inst/D/fcvt.wu.d.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fcvtmod.w.d.yaml b/arch/inst/D/fcvtmod.w.d.yaml index 4d186be082..d890f78faf 100644 --- a/arch/inst/D/fcvtmod.w.d.yaml +++ b/arch/inst/D/fcvtmod.w.d.yaml @@ -23,4 +23,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fdiv.d.yaml b/arch/inst/D/fdiv.d.yaml index 5194db5de7..a3c17b19a3 100644 --- a/arch/inst/D/fdiv.d.yaml +++ b/arch/inst/D/fdiv.d.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/feq.d.yaml b/arch/inst/D/feq.d.yaml index 3f0dffd807..e3249eca67 100644 --- a/arch/inst/D/feq.d.yaml +++ b/arch/inst/D/feq.d.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fld.yaml b/arch/inst/D/fld.yaml index a1097d179e..cc6a602560 100644 --- a/arch/inst/D/fld.yaml +++ b/arch/inst/D/fld.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fle.d.yaml b/arch/inst/D/fle.d.yaml index 42b06629a9..149a7ee354 100644 --- a/arch/inst/D/fle.d.yaml +++ b/arch/inst/D/fle.d.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fleq.d.yaml b/arch/inst/D/fleq.d.yaml index 77948081bb..2046c32a7c 100644 --- a/arch/inst/D/fleq.d.yaml +++ b/arch/inst/D/fleq.d.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fli.d.yaml b/arch/inst/D/fli.d.yaml index e78305d406..113895fc0c 100644 --- a/arch/inst/D/fli.d.yaml +++ b/arch/inst/D/fli.d.yaml @@ -23,4 +23,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/flt.d.yaml b/arch/inst/D/flt.d.yaml index 20ae39d591..8ab8d19961 100644 --- a/arch/inst/D/flt.d.yaml +++ b/arch/inst/D/flt.d.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fltq.d.yaml b/arch/inst/D/fltq.d.yaml index f2dc4d0c4e..63b1e93ed1 100644 --- a/arch/inst/D/fltq.d.yaml +++ b/arch/inst/D/fltq.d.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fmadd.d.yaml b/arch/inst/D/fmadd.d.yaml index 8057fb9fbe..c269141a7a 100644 --- a/arch/inst/D/fmadd.d.yaml +++ b/arch/inst/D/fmadd.d.yaml @@ -28,4 +28,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fmax.d.yaml b/arch/inst/D/fmax.d.yaml index ea557fb82b..4e35cc44ca 100644 --- a/arch/inst/D/fmax.d.yaml +++ b/arch/inst/D/fmax.d.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fmaxm.d.yaml b/arch/inst/D/fmaxm.d.yaml index 2ab31feab9..37765a2a53 100644 --- a/arch/inst/D/fmaxm.d.yaml +++ b/arch/inst/D/fmaxm.d.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fmin.d.yaml b/arch/inst/D/fmin.d.yaml index e7928b72e8..b918994061 100644 --- a/arch/inst/D/fmin.d.yaml +++ b/arch/inst/D/fmin.d.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fminm.d.yaml b/arch/inst/D/fminm.d.yaml index d8c6ee3609..06ef3eae89 100644 --- a/arch/inst/D/fminm.d.yaml +++ b/arch/inst/D/fminm.d.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fmsub.d.yaml b/arch/inst/D/fmsub.d.yaml index 6eee5f8e2a..3d582fdf96 100644 --- a/arch/inst/D/fmsub.d.yaml +++ b/arch/inst/D/fmsub.d.yaml @@ -28,4 +28,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fmul.d.yaml b/arch/inst/D/fmul.d.yaml index cc1847a144..5a7d07db6f 100644 --- a/arch/inst/D/fmul.d.yaml +++ b/arch/inst/D/fmul.d.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fmv.d.x.yaml b/arch/inst/D/fmv.d.x.yaml index a6859fbf90..62007aaf2b 100644 --- a/arch/inst/D/fmv.d.x.yaml +++ b/arch/inst/D/fmv.d.x.yaml @@ -23,4 +23,3 @@ access: data_independent_timing: false base: 64 operation(): | - diff --git a/arch/inst/D/fmv.x.d.yaml b/arch/inst/D/fmv.x.d.yaml index dbad3a0066..729fe7dc96 100644 --- a/arch/inst/D/fmv.x.d.yaml +++ b/arch/inst/D/fmv.x.d.yaml @@ -23,4 +23,3 @@ access: data_independent_timing: false base: 64 operation(): | - diff --git a/arch/inst/D/fmvh.x.d.yaml b/arch/inst/D/fmvh.x.d.yaml index c9492bc7ff..86f7d4976b 100644 --- a/arch/inst/D/fmvh.x.d.yaml +++ b/arch/inst/D/fmvh.x.d.yaml @@ -24,4 +24,3 @@ access: data_independent_timing: false base: 32 operation(): | - diff --git a/arch/inst/D/fmvp.d.x.yaml b/arch/inst/D/fmvp.d.x.yaml index a7aee0eb9d..c44068bb4c 100644 --- a/arch/inst/D/fmvp.d.x.yaml +++ b/arch/inst/D/fmvp.d.x.yaml @@ -26,4 +26,3 @@ access: data_independent_timing: false base: 32 operation(): | - diff --git a/arch/inst/D/fnmadd.d.yaml b/arch/inst/D/fnmadd.d.yaml index 4decb59368..6e73fcf6f1 100644 --- a/arch/inst/D/fnmadd.d.yaml +++ b/arch/inst/D/fnmadd.d.yaml @@ -28,4 +28,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fnmsub.d.yaml b/arch/inst/D/fnmsub.d.yaml index a5a0670376..f9f49cee5a 100644 --- a/arch/inst/D/fnmsub.d.yaml +++ b/arch/inst/D/fnmsub.d.yaml @@ -28,4 +28,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fround.d.yaml b/arch/inst/D/fround.d.yaml index 8d5b70109d..b67de8da0f 100644 --- a/arch/inst/D/fround.d.yaml +++ b/arch/inst/D/fround.d.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/froundnx.d.yaml b/arch/inst/D/froundnx.d.yaml index b1c151da91..411f4c8a69 100644 --- a/arch/inst/D/froundnx.d.yaml +++ b/arch/inst/D/froundnx.d.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fsd.yaml b/arch/inst/D/fsd.yaml index fe879dd5e9..989b892002 100644 --- a/arch/inst/D/fsd.yaml +++ b/arch/inst/D/fsd.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fsgnj.d.yaml b/arch/inst/D/fsgnj.d.yaml index e875909320..fdab3944f8 100644 --- a/arch/inst/D/fsgnj.d.yaml +++ b/arch/inst/D/fsgnj.d.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fsgnjn.d.yaml b/arch/inst/D/fsgnjn.d.yaml index 21f54f530f..6e7a206f8b 100644 --- a/arch/inst/D/fsgnjn.d.yaml +++ b/arch/inst/D/fsgnjn.d.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fsgnjx.d.yaml b/arch/inst/D/fsgnjx.d.yaml index 737aef9a5d..b4e55c47c5 100644 --- a/arch/inst/D/fsgnjx.d.yaml +++ b/arch/inst/D/fsgnjx.d.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fsqrt.d.yaml b/arch/inst/D/fsqrt.d.yaml index 5a07724455..657abdfa79 100644 --- a/arch/inst/D/fsqrt.d.yaml +++ b/arch/inst/D/fsqrt.d.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/D/fsub.d.yaml b/arch/inst/D/fsub.d.yaml index f7723cf23e..1bddc6665f 100644 --- a/arch/inst/D/fsub.d.yaml +++ b/arch/inst/D/fsub.d.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/F/fadd.s.yaml b/arch/inst/F/fadd.s.yaml index d5291ea1e8..fdefa3a075 100644 --- a/arch/inst/F/fadd.s.yaml +++ b/arch/inst/F/fadd.s.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: true operation(): | - + @@ -50,7 +50,3 @@ sail(): | } } } - - - - diff --git a/arch/inst/F/fclass.s.yaml b/arch/inst/F/fclass.s.yaml index 29d9505abe..29f391926f 100644 --- a/arch/inst/F/fclass.s.yaml +++ b/arch/inst/F/fclass.s.yaml @@ -72,7 +72,7 @@ operation(): | } else { assert(is_sp_quiet_nan?(sp_value), "Unexpected SP value"); X[rd] = 1 << 9; - } + } @@ -83,7 +83,3 @@ sail(): | F(rd) = nan_box (rd_val_S); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/F/fcvt.l.s.yaml b/arch/inst/F/fcvt.l.s.yaml index a218c623f5..c5d156aa4d 100644 --- a/arch/inst/F/fcvt.l.s.yaml +++ b/arch/inst/F/fcvt.l.s.yaml @@ -25,7 +25,7 @@ access: vu: always data_independent_timing: true operation(): | - + @@ -38,14 +38,10 @@ sail(): | Some(rm') => { let rm_3b = encdec_rounding_mode(rm'); let (fflags, rd_val_S) = riscv_ui64ToF32 (rm_3b, rs1_val_LU); - + accrue_fflags(fflags); F_or_X_S(rd) = rd_val_S; RETIRE_SUCCESS } } } - - - - diff --git a/arch/inst/F/fcvt.lu.s.yaml b/arch/inst/F/fcvt.lu.s.yaml index 262b9ee1f8..a77ccfe534 100644 --- a/arch/inst/F/fcvt.lu.s.yaml +++ b/arch/inst/F/fcvt.lu.s.yaml @@ -25,7 +25,7 @@ access: vu: always data_independent_timing: true operation(): | - + @@ -38,14 +38,10 @@ sail(): | Some(rm') => { let rm_3b = encdec_rounding_mode(rm'); let (fflags, rd_val_S) = riscv_ui64ToF32 (rm_3b, rs1_val_LU); - + accrue_fflags(fflags); F_or_X_S(rd) = rd_val_S; RETIRE_SUCCESS } } } - - - - diff --git a/arch/inst/F/fcvt.s.l.yaml b/arch/inst/F/fcvt.s.l.yaml index 3f1e6f7d88..436bf19060 100644 --- a/arch/inst/F/fcvt.s.l.yaml +++ b/arch/inst/F/fcvt.s.l.yaml @@ -25,7 +25,7 @@ access: vu: always data_independent_timing: true operation(): | - + @@ -38,14 +38,10 @@ sail(): | Some(rm') => { let rm_3b = encdec_rounding_mode(rm'); let (fflags, rd_val_S) = riscv_ui64ToF32 (rm_3b, rs1_val_LU); - + accrue_fflags(fflags); F_or_X_S(rd) = rd_val_S; RETIRE_SUCCESS } } } - - - - diff --git a/arch/inst/F/fcvt.s.lu.yaml b/arch/inst/F/fcvt.s.lu.yaml index ff28f60852..b999a22966 100644 --- a/arch/inst/F/fcvt.s.lu.yaml +++ b/arch/inst/F/fcvt.s.lu.yaml @@ -25,7 +25,7 @@ access: vu: always data_independent_timing: true operation(): | - + @@ -38,14 +38,10 @@ sail(): | Some(rm') => { let rm_3b = encdec_rounding_mode(rm'); let (fflags, rd_val_S) = riscv_ui64ToF32 (rm_3b, rs1_val_LU); - + accrue_fflags(fflags); F_or_X_S(rd) = rd_val_S; RETIRE_SUCCESS } } } - - - - diff --git a/arch/inst/F/fcvt.s.w.yaml b/arch/inst/F/fcvt.s.w.yaml index b4194fd99c..70074ff6d9 100644 --- a/arch/inst/F/fcvt.s.w.yaml +++ b/arch/inst/F/fcvt.s.w.yaml @@ -62,14 +62,10 @@ sail(): | Some(rm') => { let rm_3b = encdec_rounding_mode(rm'); let (fflags, rd_val_S) = riscv_ui64ToF32 (rm_3b, rs1_val_LU); - + accrue_fflags(fflags); F_or_X_S(rd) = rd_val_S; RETIRE_SUCCESS } } } - - - - diff --git a/arch/inst/F/fcvt.s.wu.yaml b/arch/inst/F/fcvt.s.wu.yaml index c8aa4a27b2..783e1a461f 100644 --- a/arch/inst/F/fcvt.s.wu.yaml +++ b/arch/inst/F/fcvt.s.wu.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: true operation(): | - + @@ -37,14 +37,10 @@ sail(): | Some(rm') => { let rm_3b = encdec_rounding_mode(rm'); let (fflags, rd_val_S) = riscv_ui64ToF32 (rm_3b, rs1_val_LU); - + accrue_fflags(fflags); F_or_X_S(rd) = rd_val_S; RETIRE_SUCCESS } } } - - - - diff --git a/arch/inst/F/fcvt.w.s.yaml b/arch/inst/F/fcvt.w.s.yaml index 9763b41d49..5693a60463 100644 --- a/arch/inst/F/fcvt.w.s.yaml +++ b/arch/inst/F/fcvt.w.s.yaml @@ -92,14 +92,10 @@ sail(): | Some(rm') => { let rm_3b = encdec_rounding_mode(rm'); let (fflags, rd_val_S) = riscv_ui64ToF32 (rm_3b, rs1_val_LU); - + accrue_fflags(fflags); F_or_X_S(rd) = rd_val_S; RETIRE_SUCCESS } } } - - - - diff --git a/arch/inst/F/fcvt.wu.s.yaml b/arch/inst/F/fcvt.wu.s.yaml index c8280f82b0..62468f5647 100644 --- a/arch/inst/F/fcvt.wu.s.yaml +++ b/arch/inst/F/fcvt.wu.s.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: true operation(): | - + @@ -37,14 +37,10 @@ sail(): | Some(rm') => { let rm_3b = encdec_rounding_mode(rm'); let (fflags, rd_val_S) = riscv_ui64ToF32 (rm_3b, rs1_val_LU); - + accrue_fflags(fflags); F_or_X_S(rd) = rd_val_S; RETIRE_SUCCESS } } } - - - - diff --git a/arch/inst/F/fdiv.s.yaml b/arch/inst/F/fdiv.s.yaml index 218271c14f..a022a89652 100644 --- a/arch/inst/F/fdiv.s.yaml +++ b/arch/inst/F/fdiv.s.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: true operation(): | - + @@ -50,7 +50,3 @@ sail(): | } } } - - - - diff --git a/arch/inst/F/feq.s.yaml b/arch/inst/F/feq.s.yaml index b704996ce0..5cb61a47bd 100644 --- a/arch/inst/F/feq.s.yaml +++ b/arch/inst/F/feq.s.yaml @@ -52,15 +52,11 @@ sail(): | { let rs1_val_S = F_or_X_S(rs1); let rs2_val_S = F_or_X_S(rs2); - + let (fflags, rd_val) : (bits_fflags, bool) = riscv_f32Le (rs1_val_S, rs2_val_S); - + accrue_fflags(fflags); X(rd) = zero_extend(bool_to_bits(rd_val)); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/F/fle.s.yaml b/arch/inst/F/fle.s.yaml index 79dc623c5b..23cee21f40 100644 --- a/arch/inst/F/fle.s.yaml +++ b/arch/inst/F/fle.s.yaml @@ -53,15 +53,11 @@ sail(): | { let rs1_val_S = F_or_X_S(rs1); let rs2_val_S = F_or_X_S(rs2); - + let (fflags, rd_val) : (bits_fflags, bool) = riscv_f32Le (rs1_val_S, rs2_val_S); - + accrue_fflags(fflags); X(rd) = zero_extend(bool_to_bits(rd_val)); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/F/fleq.s.yaml b/arch/inst/F/fleq.s.yaml index 0f5b5796af..b2645b9d83 100644 --- a/arch/inst/F/fleq.s.yaml +++ b/arch/inst/F/fleq.s.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: true operation(): | - + @@ -32,15 +32,11 @@ sail(): | { let rs1_val_S = F_S(rs1); let rs2_val_S = F_S(rs2); - + let (fflags, rd_val) : (bits_fflags, bool) = riscv_f32Le_quiet (rs1_val_S, rs2_val_S); - + accrue_fflags(fflags); X(rd) = zero_extend(bool_to_bits(rd_val)); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/F/fli.s.yaml b/arch/inst/F/fli.s.yaml index 008c13fa8e..293103c897 100644 --- a/arch/inst/F/fli.s.yaml +++ b/arch/inst/F/fli.s.yaml @@ -22,7 +22,7 @@ access: vu: always data_independent_timing: true operation(): | - + @@ -65,7 +65,3 @@ sail(): | F_S(rd) = bits; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/F/flt.s.yaml b/arch/inst/F/flt.s.yaml index e18c36b47a..e6d63d55bb 100644 --- a/arch/inst/F/flt.s.yaml +++ b/arch/inst/F/flt.s.yaml @@ -40,7 +40,7 @@ operation(): | Boolean sign_a = sp_value_a[31] == 1; Boolean sign_b = sp_value_b[31] == 1; - Boolean a_lt_b = + Boolean a_lt_b = (sign_a != sign_b) ? (sign_a && ((sp_value_a[30:0] | sp_value_b[30:0]) != 0)) # opposite sign, a is negative. a is less than b as long as both are not zero : ((sp_value_a != sp_value_b) && (sign_a != (sp_value_a < sp_value_b))); @@ -55,15 +55,11 @@ sail(): | { let rs1_val_S = F_or_X_S(rs1); let rs2_val_S = F_or_X_S(rs2); - + let (fflags, rd_val) : (bits_fflags, bool) = riscv_f32Le (rs1_val_S, rs2_val_S); - + accrue_fflags(fflags); X(rd) = zero_extend(bool_to_bits(rd_val)); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/F/fltq.s.yaml b/arch/inst/F/fltq.s.yaml index fcda547238..219da4452b 100644 --- a/arch/inst/F/fltq.s.yaml +++ b/arch/inst/F/fltq.s.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: true operation(): | - + @@ -32,15 +32,11 @@ sail(): | { let rs1_val_S = F_S(rs1); let rs2_val_S = F_S(rs2); - + let (fflags, rd_val) : (bits_fflags, bool) = riscv_f32Lt_quiet (rs1_val_S, rs2_val_S); - + accrue_fflags(fflags); X(rd) = zero_extend(bool_to_bits(rd_val)); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/F/flw.yaml b/arch/inst/F/flw.yaml index 700f79d007..1ca5c69284 100644 --- a/arch/inst/F/flw.yaml +++ b/arch/inst/F/flw.yaml @@ -70,7 +70,3 @@ sail(): | } } } - - - - diff --git a/arch/inst/F/fmadd.s.yaml b/arch/inst/F/fmadd.s.yaml index 54ac1e3d49..353d68e44f 100644 --- a/arch/inst/F/fmadd.s.yaml +++ b/arch/inst/F/fmadd.s.yaml @@ -28,7 +28,7 @@ access: vu: always data_independent_timing: true operation(): | - + @@ -54,7 +54,3 @@ sail(): | } } } - - - - diff --git a/arch/inst/F/fmax.s.yaml b/arch/inst/F/fmax.s.yaml index 9a7ade26bc..c617d75432 100644 --- a/arch/inst/F/fmax.s.yaml +++ b/arch/inst/F/fmax.s.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: true operation(): | - + @@ -32,15 +32,11 @@ sail(): | { let rs1_val_S = F_or_X_S(rs1); let rs2_val_S = F_or_X_S(rs2); - + let (fflags, rd_val) : (bits_fflags, bool) = riscv_f32Le (rs1_val_S, rs2_val_S); - + accrue_fflags(fflags); X(rd) = zero_extend(bool_to_bits(rd_val)); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/F/fmaxm.s.yaml b/arch/inst/F/fmaxm.s.yaml index b303bdfdd9..39d20ca1e2 100644 --- a/arch/inst/F/fmaxm.s.yaml +++ b/arch/inst/F/fmaxm.s.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: true operation(): | - + @@ -32,21 +32,17 @@ sail(): | { let rs1_val_S = F_S(rs1); let rs2_val_S = F_S(rs2); - + let is_quiet = true; let (rs2_lt_rs1, fflags) = fle_S (rs2_val_S, rs1_val_S, is_quiet); - + let rd_val_S = if (f_is_NaN_S(rs1_val_S) | f_is_NaN_S(rs2_val_S)) then canonical_NaN_S() else if (f_is_neg_zero_S(rs1_val_S) & f_is_pos_zero_S(rs2_val_S)) then rs2_val_S else if (f_is_neg_zero_S(rs2_val_S) & f_is_pos_zero_S(rs1_val_S)) then rs1_val_S else if rs2_lt_rs1 then rs1_val_S else /* (not rs2_lt_rs1) */ rs2_val_S; - + accrue_fflags(fflags); F_S(rd) = rd_val_S; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/F/fmin.s.yaml b/arch/inst/F/fmin.s.yaml index 667ddee84b..06dd4c629f 100644 --- a/arch/inst/F/fmin.s.yaml +++ b/arch/inst/F/fmin.s.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: true operation(): | - + @@ -32,15 +32,11 @@ sail(): | { let rs1_val_S = F_or_X_S(rs1); let rs2_val_S = F_or_X_S(rs2); - + let (fflags, rd_val) : (bits_fflags, bool) = riscv_f32Le (rs1_val_S, rs2_val_S); - + accrue_fflags(fflags); X(rd) = zero_extend(bool_to_bits(rd_val)); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/F/fminm.s.yaml b/arch/inst/F/fminm.s.yaml index 83b6cf7bf3..da71a465cc 100644 --- a/arch/inst/F/fminm.s.yaml +++ b/arch/inst/F/fminm.s.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: true operation(): | - + @@ -32,21 +32,17 @@ sail(): | { let rs1_val_S = F_S(rs1); let rs2_val_S = F_S(rs2); - + let is_quiet = true; let (rs1_lt_rs2, fflags) = fle_S (rs1_val_S, rs2_val_S, is_quiet); - + let rd_val_S = if (f_is_NaN_S(rs1_val_S) | f_is_NaN_S(rs2_val_S)) then canonical_NaN_S() else if (f_is_neg_zero_S(rs1_val_S) & f_is_pos_zero_S(rs2_val_S)) then rs1_val_S else if (f_is_neg_zero_S(rs2_val_S) & f_is_pos_zero_S(rs1_val_S)) then rs2_val_S else if rs1_lt_rs2 then rs1_val_S else /* (not rs1_lt_rs2) */ rs2_val_S; - + accrue_fflags(fflags); F_S(rd) = rd_val_S; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/F/fmsub.s.yaml b/arch/inst/F/fmsub.s.yaml index b12a96acd5..13d2a7f52e 100644 --- a/arch/inst/F/fmsub.s.yaml +++ b/arch/inst/F/fmsub.s.yaml @@ -28,7 +28,7 @@ access: vu: always data_independent_timing: true operation(): | - + @@ -54,7 +54,3 @@ sail(): | } } } - - - - diff --git a/arch/inst/F/fmul.s.yaml b/arch/inst/F/fmul.s.yaml index c374137a19..66d5392b79 100644 --- a/arch/inst/F/fmul.s.yaml +++ b/arch/inst/F/fmul.s.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: true operation(): | - + @@ -50,7 +50,3 @@ sail(): | } } } - - - - diff --git a/arch/inst/F/fmv.w.x.yaml b/arch/inst/F/fmv.w.x.yaml index e65476f9ac..4b593de630 100644 --- a/arch/inst/F/fmv.w.x.yaml +++ b/arch/inst/F/fmv.w.x.yaml @@ -46,7 +46,3 @@ sail(): | F(rd) = nan_box (rd_val_S); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/F/fmv.x.w.yaml b/arch/inst/F/fmv.x.w.yaml index baf798a9a4..f8887234c9 100644 --- a/arch/inst/F/fmv.x.w.yaml +++ b/arch/inst/F/fmv.x.w.yaml @@ -40,7 +40,3 @@ sail(): | F(rd) = nan_box (rd_val_S); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/F/fnmadd.s.yaml b/arch/inst/F/fnmadd.s.yaml index 6d6675003a..1b0eaecf50 100644 --- a/arch/inst/F/fnmadd.s.yaml +++ b/arch/inst/F/fnmadd.s.yaml @@ -28,7 +28,7 @@ access: vu: always data_independent_timing: true operation(): | - + @@ -54,7 +54,3 @@ sail(): | } } } - - - - diff --git a/arch/inst/F/fnmsub.s.yaml b/arch/inst/F/fnmsub.s.yaml index 61bfb97d14..c1a1997b81 100644 --- a/arch/inst/F/fnmsub.s.yaml +++ b/arch/inst/F/fnmsub.s.yaml @@ -28,7 +28,7 @@ access: vu: always data_independent_timing: true operation(): | - + @@ -54,7 +54,3 @@ sail(): | } } } - - - - diff --git a/arch/inst/F/fround.s.yaml b/arch/inst/F/fround.s.yaml index cd57704a95..83753b0a8c 100644 --- a/arch/inst/F/fround.s.yaml +++ b/arch/inst/F/fround.s.yaml @@ -24,27 +24,23 @@ access: vu: always data_independent_timing: true operation(): | - + sail(): | { let rs1_val_S = F_S(rs1); - + match (select_instr_or_fcsr_rm(rm)) { None() => { handle_illegal(); RETIRE_FAIL }, Some(rm') => { let rm_3b = encdec_rounding_mode(rm'); let (fflags, rd_val_S) = riscv_f32roundToInt(rm_3b, rs1_val_S, false); - + accrue_fflags(fflags); F_S(rd) = rd_val_S; RETIRE_SUCCESS } } } - - - - diff --git a/arch/inst/F/froundnx.s.yaml b/arch/inst/F/froundnx.s.yaml index 828dfd8b6a..b3d8927e04 100644 --- a/arch/inst/F/froundnx.s.yaml +++ b/arch/inst/F/froundnx.s.yaml @@ -24,27 +24,23 @@ access: vu: always data_independent_timing: true operation(): | - + sail(): | { let rs1_val_S = F_S(rs1); - + match (select_instr_or_fcsr_rm(rm)) { None() => { handle_illegal(); RETIRE_FAIL }, Some(rm') => { let rm_3b = encdec_rounding_mode(rm'); let (fflags, rd_val_S) = riscv_f32roundToInt(rm_3b, rs1_val_S, true); - + accrue_fflags(fflags); F_S(rd) = rd_val_S; RETIRE_SUCCESS } } } - - - - diff --git a/arch/inst/F/fsgnj.s.yaml b/arch/inst/F/fsgnj.s.yaml index 46e49f2a0d..544d564e19 100644 --- a/arch/inst/F/fsgnj.s.yaml +++ b/arch/inst/F/fsgnj.s.yaml @@ -49,15 +49,11 @@ sail(): | { let rs1_val_S = F_or_X_S(rs1); let rs2_val_S = F_or_X_S(rs2); - + let (fflags, rd_val) : (bits_fflags, bool) = riscv_f32Le (rs1_val_S, rs2_val_S); - + accrue_fflags(fflags); X(rd) = zero_extend(bool_to_bits(rd_val)); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/F/fsgnjn.s.yaml b/arch/inst/F/fsgnjn.s.yaml index a6b927efa9..286f7bffd2 100644 --- a/arch/inst/F/fsgnjn.s.yaml +++ b/arch/inst/F/fsgnjn.s.yaml @@ -48,15 +48,11 @@ sail(): | { let rs1_val_S = F_or_X_S(rs1); let rs2_val_S = F_or_X_S(rs2); - + let (fflags, rd_val) : (bits_fflags, bool) = riscv_f32Le (rs1_val_S, rs2_val_S); - + accrue_fflags(fflags); X(rd) = zero_extend(bool_to_bits(rd_val)); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/F/fsgnjx.s.yaml b/arch/inst/F/fsgnjx.s.yaml index 720e88e6fb..e6fba22820 100644 --- a/arch/inst/F/fsgnjx.s.yaml +++ b/arch/inst/F/fsgnjx.s.yaml @@ -47,15 +47,11 @@ sail(): | { let rs1_val_S = F_or_X_S(rs1); let rs2_val_S = F_or_X_S(rs2); - + let (fflags, rd_val) : (bits_fflags, bool) = riscv_f32Le (rs1_val_S, rs2_val_S); - + accrue_fflags(fflags); X(rd) = zero_extend(bool_to_bits(rd_val)); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/F/fsqrt.s.yaml b/arch/inst/F/fsqrt.s.yaml index 5a4c708c6c..a869687a29 100644 --- a/arch/inst/F/fsqrt.s.yaml +++ b/arch/inst/F/fsqrt.s.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: true operation(): | - + @@ -37,14 +37,10 @@ sail(): | Some(rm') => { let rm_3b = encdec_rounding_mode(rm'); let (fflags, rd_val_S) = riscv_ui64ToF32 (rm_3b, rs1_val_LU); - + accrue_fflags(fflags); F_or_X_S(rd) = rd_val_S; RETIRE_SUCCESS } } } - - - - diff --git a/arch/inst/F/fsub.s.yaml b/arch/inst/F/fsub.s.yaml index 7a23826750..ecce09860b 100644 --- a/arch/inst/F/fsub.s.yaml +++ b/arch/inst/F/fsub.s.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: true operation(): | - + @@ -50,7 +50,3 @@ sail(): | } } } - - - - diff --git a/arch/inst/F/fsw.yaml b/arch/inst/F/fsw.yaml index 047d045ad0..d2f23782ac 100644 --- a/arch/inst/F/fsw.yaml +++ b/arch/inst/F/fsw.yaml @@ -73,7 +73,3 @@ sail(): | } } } - - - - diff --git a/arch/inst/H/hfence.gvma.yaml b/arch/inst/H/hfence.gvma.yaml index 9645a5c49b..4bffc4c604 100644 --- a/arch/inst/H/hfence.gvma.yaml +++ b/arch/inst/H/hfence.gvma.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/H/hfence.vvma.yaml b/arch/inst/H/hfence.vvma.yaml index e82abec6d8..dd015039f0 100644 --- a/arch/inst/H/hfence.vvma.yaml +++ b/arch/inst/H/hfence.vvma.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/H/hlv.b.yaml b/arch/inst/H/hlv.b.yaml index 227e2e5c0b..c89ccd5c6d 100644 --- a/arch/inst/H/hlv.b.yaml +++ b/arch/inst/H/hlv.b.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/H/hlv.bu.yaml b/arch/inst/H/hlv.bu.yaml index 2c5418ec2c..5938d786a2 100644 --- a/arch/inst/H/hlv.bu.yaml +++ b/arch/inst/H/hlv.bu.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/H/hlv.d.yaml b/arch/inst/H/hlv.d.yaml index 919cc68754..98c27700b9 100644 --- a/arch/inst/H/hlv.d.yaml +++ b/arch/inst/H/hlv.d.yaml @@ -23,4 +23,3 @@ access: data_independent_timing: false base: 64 operation(): | - diff --git a/arch/inst/H/hlv.h.yaml b/arch/inst/H/hlv.h.yaml index 8e7191cb06..6abbd7d9b9 100644 --- a/arch/inst/H/hlv.h.yaml +++ b/arch/inst/H/hlv.h.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/H/hlv.hu.yaml b/arch/inst/H/hlv.hu.yaml index ac69cc127b..99614784cd 100644 --- a/arch/inst/H/hlv.hu.yaml +++ b/arch/inst/H/hlv.hu.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/H/hlv.w.yaml b/arch/inst/H/hlv.w.yaml index 2c56a33d5b..53d318cad3 100644 --- a/arch/inst/H/hlv.w.yaml +++ b/arch/inst/H/hlv.w.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/H/hlv.wu.yaml b/arch/inst/H/hlv.wu.yaml index 9b2aa3fd4a..2b8d652c9a 100644 --- a/arch/inst/H/hlv.wu.yaml +++ b/arch/inst/H/hlv.wu.yaml @@ -23,4 +23,3 @@ access: data_independent_timing: false base: 64 operation(): | - diff --git a/arch/inst/H/hlvx.hu.yaml b/arch/inst/H/hlvx.hu.yaml index 20491065b4..b527451cdf 100644 --- a/arch/inst/H/hlvx.hu.yaml +++ b/arch/inst/H/hlvx.hu.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/H/hlvx.wu.yaml b/arch/inst/H/hlvx.wu.yaml index 0f93baf90d..d764afeb39 100644 --- a/arch/inst/H/hlvx.wu.yaml +++ b/arch/inst/H/hlvx.wu.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/H/hsv.b.yaml b/arch/inst/H/hsv.b.yaml index b05b3dd890..03da5add6b 100644 --- a/arch/inst/H/hsv.b.yaml +++ b/arch/inst/H/hsv.b.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/H/hsv.d.yaml b/arch/inst/H/hsv.d.yaml index 5fa349994f..cda8a6b5b2 100644 --- a/arch/inst/H/hsv.d.yaml +++ b/arch/inst/H/hsv.d.yaml @@ -23,4 +23,3 @@ access: data_independent_timing: false base: 64 operation(): | - diff --git a/arch/inst/H/hsv.h.yaml b/arch/inst/H/hsv.h.yaml index a307f6a5da..2ceb5b6b7b 100644 --- a/arch/inst/H/hsv.h.yaml +++ b/arch/inst/H/hsv.h.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/H/hsv.w.yaml b/arch/inst/H/hsv.w.yaml index e5e778bbdc..2379bc83a1 100644 --- a/arch/inst/H/hsv.w.yaml +++ b/arch/inst/H/hsv.w.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/I/add.yaml b/arch/inst/I/add.yaml index 83706ffdb0..e7038315a8 100644 --- a/arch/inst/I/add.yaml +++ b/arch/inst/I/add.yaml @@ -53,7 +53,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/addi.yaml b/arch/inst/I/addi.yaml index 05db65005f..74adf7a405 100644 --- a/arch/inst/I/addi.yaml +++ b/arch/inst/I/addi.yaml @@ -41,7 +41,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/addiw.yaml b/arch/inst/I/addiw.yaml index 36f72a725f..9060c51ee0 100644 --- a/arch/inst/I/addiw.yaml +++ b/arch/inst/I/addiw.yaml @@ -35,7 +35,3 @@ sail(): | X(rd) = sign_extend(result[31..0]); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/addw.yaml b/arch/inst/I/addw.yaml index de8262a4ec..2abb97ed7f 100644 --- a/arch/inst/I/addw.yaml +++ b/arch/inst/I/addw.yaml @@ -46,7 +46,3 @@ sail(): | X(rd) = sign_extend(result); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/and.yaml b/arch/inst/I/and.yaml index 815c2cbe6d..85a3a2022b 100644 --- a/arch/inst/I/and.yaml +++ b/arch/inst/I/and.yaml @@ -51,7 +51,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/andi.yaml b/arch/inst/I/andi.yaml index 9ef488e427..708d67edb3 100644 --- a/arch/inst/I/andi.yaml +++ b/arch/inst/I/andi.yaml @@ -41,7 +41,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/auipc.yaml b/arch/inst/I/auipc.yaml index f65fdad53d..3aa89876ed 100644 --- a/arch/inst/I/auipc.yaml +++ b/arch/inst/I/auipc.yaml @@ -34,4 +34,3 @@ sail(): | X(rd) = ret; RETIRE_SUCCESS } - diff --git a/arch/inst/I/beq.yaml b/arch/inst/I/beq.yaml index 1dde072bf5..a58721bb6a 100644 --- a/arch/inst/I/beq.yaml +++ b/arch/inst/I/beq.yaml @@ -67,7 +67,3 @@ sail(): | } } else RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/bge.yaml b/arch/inst/I/bge.yaml index 94edce67db..41369cb8ed 100644 --- a/arch/inst/I/bge.yaml +++ b/arch/inst/I/bge.yaml @@ -33,7 +33,7 @@ operation(): | if ($signed(lhs) >= $signed(rhs)) { jump_halfword($pc + imm); } - + sail(): | @@ -68,7 +68,3 @@ sail(): | } } else RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/bgeu.yaml b/arch/inst/I/bgeu.yaml index 687a651164..daa2a490f5 100644 --- a/arch/inst/I/bgeu.yaml +++ b/arch/inst/I/bgeu.yaml @@ -33,7 +33,7 @@ operation(): | if (lhs >= rhs) { jump_halfword($pc + imm); } - + sail(): | @@ -68,7 +68,3 @@ sail(): | } } else RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/blt.yaml b/arch/inst/I/blt.yaml index fca0c00251..beed9ad248 100644 --- a/arch/inst/I/blt.yaml +++ b/arch/inst/I/blt.yaml @@ -33,7 +33,7 @@ operation(): | if ($signed(lhs) < $signed(rhs)) { jump_halfword($pc + imm); } - + sail(): | @@ -68,7 +68,3 @@ sail(): | } } else RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/bltu.yaml b/arch/inst/I/bltu.yaml index 919c8cafce..bfc1ab77fd 100644 --- a/arch/inst/I/bltu.yaml +++ b/arch/inst/I/bltu.yaml @@ -33,7 +33,7 @@ operation(): | if (lhs < rhs) { jump_halfword($pc + imm); } - + sail(): | @@ -68,7 +68,3 @@ sail(): | } } else RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/bne.yaml b/arch/inst/I/bne.yaml index 099ba0db88..96c72a066e 100644 --- a/arch/inst/I/bne.yaml +++ b/arch/inst/I/bne.yaml @@ -33,7 +33,7 @@ operation(): | if (lhs != rhs) { jump_halfword($pc + imm); } - + sail(): | @@ -68,7 +68,3 @@ sail(): | } } else RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/ebreak.yaml b/arch/inst/I/ebreak.yaml index 5b08b202d5..c13b7435fe 100644 --- a/arch/inst/I/ebreak.yaml +++ b/arch/inst/I/ebreak.yaml @@ -40,7 +40,3 @@ sail(): | handle_mem_exception(PC, E_Breakpoint()); RETIRE_FAIL } - - - - diff --git a/arch/inst/I/ecall.yaml b/arch/inst/I/ecall.yaml index 2e6eb97d82..205b43201b 100644 --- a/arch/inst/I/ecall.yaml +++ b/arch/inst/I/ecall.yaml @@ -71,7 +71,3 @@ sail(): | set_next_pc(exception_handler(cur_privilege, CTL_TRAP(t), PC)); RETIRE_FAIL } - - - - diff --git a/arch/inst/I/fence.yaml b/arch/inst/I/fence.yaml index 8edbc57760..b5173ec686 100644 --- a/arch/inst/I/fence.yaml +++ b/arch/inst/I/fence.yaml @@ -20,7 +20,7 @@ description: | [%autowidth] |=== 4+| `pred` 4+| `succ` - + | 27 | 26 |25 | 24 | 23 | 22 | 21| 20 | PI | PO |PR | PW | SI | SO |SR | SW |=== @@ -187,14 +187,14 @@ operation(): | if (pred_o) { pred_w = true; } if (succ_i) { succ_r = true; } if (succ_o) { succ_w = true; } - } + } } else if (mode() == PrivilegeMode::VS || mode() == PrivilegeMode::VU) { if ((CSR[menvcfg].FIOM | CSR[henvcfg].FIOM) == 1) { if (pred_i) { pred_r = true; } if (pred_o) { pred_w = true; } if (succ_i) { succ_r = true; } if (succ_o) { succ_w = true; } - } + } } fence( @@ -216,7 +216,7 @@ sail(): | let fiom = is_fiom_active(); let pred = effective_fence_set(pred, fiom); let succ = effective_fence_set(succ, fiom); - + match (pred, succ) { (_ : bits(2) @ 0b11, _ : bits(2) @ 0b11) => __barrier(Barrier_RISCV_rw_rw()), (_ : bits(2) @ 0b10, _ : bits(2) @ 0b11) => __barrier(Barrier_RISCV_r_rw()), @@ -227,16 +227,12 @@ sail(): | (_ : bits(2) @ 0b11, _ : bits(2) @ 0b10) => __barrier(Barrier_RISCV_rw_r()), (_ : bits(2) @ 0b10, _ : bits(2) @ 0b01) => __barrier(Barrier_RISCV_r_w()), (_ : bits(2) @ 0b01, _ : bits(2) @ 0b10) => __barrier(Barrier_RISCV_w_r()), - + (_ : bits(4) , _ : bits(2) @ 0b00) => (), (_ : bits(2) @ 0b00, _ : bits(4) ) => (), - + _ => { print("FIXME: unsupported fence"); () } }; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/jal.yaml b/arch/inst/I/jal.yaml index fdd537478d..7c0b299d32 100644 --- a/arch/inst/I/jal.yaml +++ b/arch/inst/I/jal.yaml @@ -54,7 +54,3 @@ sail(): | } } } - - - - diff --git a/arch/inst/I/jalr.yaml b/arch/inst/I/jalr.yaml index d3aebbf17f..d3591fd2fc 100644 --- a/arch/inst/I/jalr.yaml +++ b/arch/inst/I/jalr.yaml @@ -60,7 +60,3 @@ sail(): | } } } - - - - diff --git a/arch/inst/I/lb.yaml b/arch/inst/I/lb.yaml index 5c3f1edf99..96c27ead6b 100644 --- a/arch/inst/I/lb.yaml +++ b/arch/inst/I/lb.yaml @@ -58,7 +58,3 @@ sail(): | } } } - - - - diff --git a/arch/inst/I/lbu.yaml b/arch/inst/I/lbu.yaml index ac4cd38a4a..c04ff027f9 100644 --- a/arch/inst/I/lbu.yaml +++ b/arch/inst/I/lbu.yaml @@ -58,7 +58,3 @@ sail(): | } } } - - - - diff --git a/arch/inst/I/ld.yaml b/arch/inst/I/ld.yaml index c4c23b40b9..dc00e7d604 100644 --- a/arch/inst/I/ld.yaml +++ b/arch/inst/I/ld.yaml @@ -58,7 +58,3 @@ sail(): | } } } - - - - diff --git a/arch/inst/I/lh.yaml b/arch/inst/I/lh.yaml index d316e61b82..22cfcfc0ed 100644 --- a/arch/inst/I/lh.yaml +++ b/arch/inst/I/lh.yaml @@ -58,7 +58,3 @@ sail(): | } } } - - - - diff --git a/arch/inst/I/lhu.yaml b/arch/inst/I/lhu.yaml index bea81ff058..7c5da33965 100644 --- a/arch/inst/I/lhu.yaml +++ b/arch/inst/I/lhu.yaml @@ -58,7 +58,3 @@ sail(): | } } } - - - - diff --git a/arch/inst/I/lui.yaml b/arch/inst/I/lui.yaml index 4253ddb06f..2401cf14a3 100644 --- a/arch/inst/I/lui.yaml +++ b/arch/inst/I/lui.yaml @@ -35,7 +35,3 @@ sail(): | X(rd) = ret; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/lw.yaml b/arch/inst/I/lw.yaml index 99b721a42c..db9e087946 100644 --- a/arch/inst/I/lw.yaml +++ b/arch/inst/I/lw.yaml @@ -58,7 +58,3 @@ sail(): | } } } - - - - diff --git a/arch/inst/I/lwu.yaml b/arch/inst/I/lwu.yaml index c33be39846..d20029bc58 100644 --- a/arch/inst/I/lwu.yaml +++ b/arch/inst/I/lwu.yaml @@ -59,7 +59,3 @@ sail(): | } } } - - - - diff --git a/arch/inst/I/mret.yaml b/arch/inst/I/mret.yaml index 356654adc6..114f68c337 100644 --- a/arch/inst/I/mret.yaml +++ b/arch/inst/I/mret.yaml @@ -42,7 +42,3 @@ sail(): | RETIRE_SUCCESS } } - - - - diff --git a/arch/inst/I/or.yaml b/arch/inst/I/or.yaml index 43cb35a281..0297a0cceb 100644 --- a/arch/inst/I/or.yaml +++ b/arch/inst/I/or.yaml @@ -51,7 +51,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/ori.yaml b/arch/inst/I/ori.yaml index fe8a2fa0ba..6785c87e3d 100644 --- a/arch/inst/I/ori.yaml +++ b/arch/inst/I/ori.yaml @@ -32,11 +32,11 @@ operation(): | } else if (imm[4:0] == 1) { # prefetch.r instruction Bits<12> offset = {imm[11:5], rd}; - prefetch_read(offset); + prefetch_read(offset); } else if (imm[4:0] == 3) { # prefetch.r instruction Bits<12> offset = {imm[11:5], rd}; - prefetch_write(offset); + prefetch_write(offset); } } } @@ -66,7 +66,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/sb.yaml b/arch/inst/I/sb.yaml index 06054e650b..f0382d77a3 100644 --- a/arch/inst/I/sb.yaml +++ b/arch/inst/I/sb.yaml @@ -72,7 +72,3 @@ sail(): | } } } - - - - diff --git a/arch/inst/I/sd.yaml b/arch/inst/I/sd.yaml index 62feb06937..0875a49667 100644 --- a/arch/inst/I/sd.yaml +++ b/arch/inst/I/sd.yaml @@ -74,7 +74,3 @@ sail(): | } } } - - - - diff --git a/arch/inst/I/sh.yaml b/arch/inst/I/sh.yaml index 5331d48399..8cfee46418 100644 --- a/arch/inst/I/sh.yaml +++ b/arch/inst/I/sh.yaml @@ -72,7 +72,3 @@ sail(): | } } } - - - - diff --git a/arch/inst/I/sll.yaml b/arch/inst/I/sll.yaml index bdf68a0d20..5695aeaf17 100644 --- a/arch/inst/I/sll.yaml +++ b/arch/inst/I/sll.yaml @@ -57,7 +57,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/slli.yaml b/arch/inst/I/slli.yaml index 1a570568bb..81a703f002 100644 --- a/arch/inst/I/slli.yaml +++ b/arch/inst/I/slli.yaml @@ -56,7 +56,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/slliw.yaml b/arch/inst/I/slliw.yaml index 43b50fa90d..b8092139fd 100644 --- a/arch/inst/I/slliw.yaml +++ b/arch/inst/I/slliw.yaml @@ -40,7 +40,3 @@ sail(): | X(rd) = sign_extend(result); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/sllw.yaml b/arch/inst/I/sllw.yaml index c745500f4c..f540ff056d 100644 --- a/arch/inst/I/sllw.yaml +++ b/arch/inst/I/sllw.yaml @@ -42,7 +42,3 @@ sail(): | X(rd) = sign_extend(result); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/slt.yaml b/arch/inst/I/slt.yaml index d665068912..1d1db5f428 100644 --- a/arch/inst/I/slt.yaml +++ b/arch/inst/I/slt.yaml @@ -57,7 +57,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/slti.yaml b/arch/inst/I/slti.yaml index 5b6abcb175..84fd55a480 100644 --- a/arch/inst/I/slti.yaml +++ b/arch/inst/I/slti.yaml @@ -44,7 +44,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/sltiu.yaml b/arch/inst/I/sltiu.yaml index 4981a7298b..14af783bbc 100644 --- a/arch/inst/I/sltiu.yaml +++ b/arch/inst/I/sltiu.yaml @@ -48,7 +48,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/sltu.yaml b/arch/inst/I/sltu.yaml index c1ee3b10d2..b7087619b8 100644 --- a/arch/inst/I/sltu.yaml +++ b/arch/inst/I/sltu.yaml @@ -54,7 +54,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/sra.yaml b/arch/inst/I/sra.yaml index c088d33a23..55ad5e33fe 100644 --- a/arch/inst/I/sra.yaml +++ b/arch/inst/I/sra.yaml @@ -57,7 +57,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/srai.yaml b/arch/inst/I/srai.yaml index e749b39924..862372f2ab 100644 --- a/arch/inst/I/srai.yaml +++ b/arch/inst/I/srai.yaml @@ -58,7 +58,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/sraiw.yaml b/arch/inst/I/sraiw.yaml index feb39990c5..42fd48d105 100644 --- a/arch/inst/I/sraiw.yaml +++ b/arch/inst/I/sraiw.yaml @@ -43,7 +43,3 @@ sail(): | X(rd) = sign_extend(result); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/sraw.yaml b/arch/inst/I/sraw.yaml index f64645d962..716fd413d4 100644 --- a/arch/inst/I/sraw.yaml +++ b/arch/inst/I/sraw.yaml @@ -45,7 +45,3 @@ sail(): | X(rd) = sign_extend(result); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/srl.yaml b/arch/inst/I/srl.yaml index 2ad1256d66..3219a49abb 100644 --- a/arch/inst/I/srl.yaml +++ b/arch/inst/I/srl.yaml @@ -57,7 +57,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/srli.yaml b/arch/inst/I/srli.yaml index 90a1904fa1..376ffc0cce 100644 --- a/arch/inst/I/srli.yaml +++ b/arch/inst/I/srli.yaml @@ -55,7 +55,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/srliw.yaml b/arch/inst/I/srliw.yaml index f28912f01d..db87361eaf 100644 --- a/arch/inst/I/srliw.yaml +++ b/arch/inst/I/srliw.yaml @@ -42,7 +42,3 @@ sail(): | X(rd) = sign_extend(result); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/srlw.yaml b/arch/inst/I/srlw.yaml index 2df6b6721c..7945a7285f 100644 --- a/arch/inst/I/srlw.yaml +++ b/arch/inst/I/srlw.yaml @@ -42,7 +42,3 @@ sail(): | X(rd) = sign_extend(result); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/sub.yaml b/arch/inst/I/sub.yaml index a031a7782a..85c7921595 100644 --- a/arch/inst/I/sub.yaml +++ b/arch/inst/I/sub.yaml @@ -54,7 +54,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/subw.yaml b/arch/inst/I/subw.yaml index 33d7354e0c..8bc7e276f5 100644 --- a/arch/inst/I/subw.yaml +++ b/arch/inst/I/subw.yaml @@ -44,7 +44,3 @@ sail(): | X(rd) = sign_extend(result); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/sw.yaml b/arch/inst/I/sw.yaml index 135995c75f..0912e04489 100644 --- a/arch/inst/I/sw.yaml +++ b/arch/inst/I/sw.yaml @@ -72,7 +72,3 @@ sail(): | } } } - - - - diff --git a/arch/inst/I/wfi.yaml b/arch/inst/I/wfi.yaml index 0eabdcc63e..ce574396e6 100644 --- a/arch/inst/I/wfi.yaml +++ b/arch/inst/I/wfi.yaml @@ -16,7 +16,7 @@ description: | .2+| [.rotate]#`mstatus.TW`# .2+| [.rotate]#`hstatus.VTW`# 4+^.>| `wfi` behavior h| HS-mode h| U-mode h| VS-mode h| in VU-mode - | 0 | 0 | Wait | Trap (I) | Wait | Trap (V) + | 0 | 0 | Wait | Trap (I) | Wait | Trap (V) | 0 | 1 | Wait | Trap (I) | Trap (V) | Trap (V) | 1 | - | Trap (I) | Trap (I) | Trap (I) | Trap (I) @@ -63,7 +63,7 @@ access_detail: | .2+| [.rotate]#`mstatus.TW`# .2+| [.rotate]#`hstatus.VTW`# 4+^.>| `wfi` behavior h| HS-mode h| U-mode h| VS-mode h| in VU-mode - | 0 | 0 | Wait | Trap (I) | Wait | Trap (V) + | 0 | 0 | Wait | Trap (I) | Wait | Trap (V) | 0 | 1 | Wait | Trap (I) | Trap (V) | Trap (V) | 1 | - | Trap (I) | Trap (I) | Trap (I) | Trap (I) @@ -121,7 +121,3 @@ sail(): | else { platform_wfi(); RETIRE_SUCCESS }, User => { handle_illegal(); RETIRE_FAIL } } - - - - diff --git a/arch/inst/I/xor.yaml b/arch/inst/I/xor.yaml index cec0aa7612..e3438951d3 100644 --- a/arch/inst/I/xor.yaml +++ b/arch/inst/I/xor.yaml @@ -51,7 +51,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/I/xori.yaml b/arch/inst/I/xori.yaml index 169f3dfa33..d92c307423 100644 --- a/arch/inst/I/xori.yaml +++ b/arch/inst/I/xori.yaml @@ -41,7 +41,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/M/div.yaml b/arch/inst/M/div.yaml index ebe7d999ca..32b003a2db 100644 --- a/arch/inst/M/div.yaml +++ b/arch/inst/M/div.yaml @@ -8,7 +8,7 @@ description: | Divide rs1 by rs2, and store the result in rd. The remainder is discarded. Division by zero will put -1 into rd. - + Division resulting in signed overflow (when most negative number is divided by -1) will put the most negative number into rd; definedBy: M @@ -68,7 +68,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/M/divu.yaml b/arch/inst/M/divu.yaml index 0e0543cb6f..75c43ff8d7 100644 --- a/arch/inst/M/divu.yaml +++ b/arch/inst/M/divu.yaml @@ -6,7 +6,7 @@ name: divu long_name: Unsigned division description: | Divide unsigned values in rs1 by rs2, and store the result in rd. - + The remainder is discarded. If the value in rs2 is zero, rd gets the largest unsigned value. @@ -60,7 +60,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/M/divuw.yaml b/arch/inst/M/divuw.yaml index 693d89a5a7..09e928a5b3 100644 --- a/arch/inst/M/divuw.yaml +++ b/arch/inst/M/divuw.yaml @@ -6,7 +6,7 @@ name: divuw long_name: Unsigned 32-bit division description: | Divide the unsigned 32-bit values in rs1 and rs2, and store the sign-extended result in rd. - + The remainder is discarded. If the value in rs2 is zero, rd is written with all 1s. @@ -66,7 +66,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/M/divw.yaml b/arch/inst/M/divw.yaml index 70b3517be0..4a1674859c 100644 --- a/arch/inst/M/divw.yaml +++ b/arch/inst/M/divw.yaml @@ -7,11 +7,11 @@ long_name: Signed 32-bit division description: | Divide the lower 32-bits of register rs1 by the lower 32-bits of register rs2, and store the sign-extended result in rd. - + The remainder is discarded. Division by zero will put -1 into rd. - + Division resulting in signed overflow (when most negative number is divided by -1) will put the most negative number into rd; definedBy: M @@ -75,7 +75,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/M/mul.yaml b/arch/inst/M/mul.yaml index b8624a008d..26c440799c 100644 --- a/arch/inst/M/mul.yaml +++ b/arch/inst/M/mul.yaml @@ -64,7 +64,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/M/mulh.yaml b/arch/inst/M/mulh.yaml index 77921b4f0d..3bb7d5b0a3 100644 --- a/arch/inst/M/mulh.yaml +++ b/arch/inst/M/mulh.yaml @@ -69,7 +69,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/M/mulhsu.yaml b/arch/inst/M/mulhsu.yaml index ad58d2f7d5..3fc37753b0 100644 --- a/arch/inst/M/mulhsu.yaml +++ b/arch/inst/M/mulhsu.yaml @@ -65,7 +65,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/M/mulhu.yaml b/arch/inst/M/mulhu.yaml index af3838350c..436668a0c2 100644 --- a/arch/inst/M/mulhu.yaml +++ b/arch/inst/M/mulhu.yaml @@ -64,7 +64,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/M/mulw.yaml b/arch/inst/M/mulw.yaml index 457ab0bac7..bd6573725d 100644 --- a/arch/inst/M/mulw.yaml +++ b/arch/inst/M/mulw.yaml @@ -66,7 +66,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/M/rem.yaml b/arch/inst/M/rem.yaml index 1f4dfd8c0b..06367f68c8 100644 --- a/arch/inst/M/rem.yaml +++ b/arch/inst/M/rem.yaml @@ -38,7 +38,7 @@ operation(): | # division by zero. Since RISC-V does not have arithmetic exceptions, the result is defined # to be the dividend X[rd] = src1; - + } else if ((src1 == {1'b1, {XLEN-1{1'b0}}}) && (src2 == {XLEN{1'b1}})) { # signed overflow. Since RISC-V does not have arithmetic exceptions, the result is defined # to be zero @@ -65,7 +65,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/M/remu.yaml b/arch/inst/M/remu.yaml index e3ad1c4579..c668b94b55 100644 --- a/arch/inst/M/remu.yaml +++ b/arch/inst/M/remu.yaml @@ -55,7 +55,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/M/remuw.yaml b/arch/inst/M/remuw.yaml index 64a52a1b85..4a4b348fad 100644 --- a/arch/inst/M/remuw.yaml +++ b/arch/inst/M/remuw.yaml @@ -67,7 +67,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/M/remw.yaml b/arch/inst/M/remw.yaml index 9df788d0bb..2c2a1500a2 100644 --- a/arch/inst/M/remw.yaml +++ b/arch/inst/M/remw.yaml @@ -40,7 +40,7 @@ operation(): | # to be the dividend, sign extended to into the 64-bit register Bits<1> sign_bit = src1[31]; X[rd] = {{32{sign_bit}}, src1}; - + } else if ((src1 == {33'b1, 31'b0}) && (src2 == 32'b1)) { # signed overflow. Since RISC-V does not have arithmetic exceptions, the result is defined # to be zero @@ -71,7 +71,3 @@ sail(): | RETIRE_FAIL } } - - - - diff --git a/arch/inst/Q/fadd.q.yaml b/arch/inst/Q/fadd.q.yaml index 7eaf4023f1..3c9886e77a 100644 --- a/arch/inst/Q/fadd.q.yaml +++ b/arch/inst/Q/fadd.q.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fclass.q.yaml b/arch/inst/Q/fclass.q.yaml index 528c2b469a..230ff77736 100644 --- a/arch/inst/Q/fclass.q.yaml +++ b/arch/inst/Q/fclass.q.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fcvt.d.q.yaml b/arch/inst/Q/fcvt.d.q.yaml index 4aaa5d9511..899950f8a8 100644 --- a/arch/inst/Q/fcvt.d.q.yaml +++ b/arch/inst/Q/fcvt.d.q.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fcvt.h.q.yaml b/arch/inst/Q/fcvt.h.q.yaml index b0f9aaf6c7..223ed90243 100644 --- a/arch/inst/Q/fcvt.h.q.yaml +++ b/arch/inst/Q/fcvt.h.q.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fcvt.l.q.yaml b/arch/inst/Q/fcvt.l.q.yaml index c6a76dbacf..aae2df1a0a 100644 --- a/arch/inst/Q/fcvt.l.q.yaml +++ b/arch/inst/Q/fcvt.l.q.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fcvt.lu.q.yaml b/arch/inst/Q/fcvt.lu.q.yaml index 0ee3cf0109..1c75d28f0d 100644 --- a/arch/inst/Q/fcvt.lu.q.yaml +++ b/arch/inst/Q/fcvt.lu.q.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fcvt.q.d.yaml b/arch/inst/Q/fcvt.q.d.yaml index a8c00bcd0c..ce1ae3943b 100644 --- a/arch/inst/Q/fcvt.q.d.yaml +++ b/arch/inst/Q/fcvt.q.d.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fcvt.q.h.yaml b/arch/inst/Q/fcvt.q.h.yaml index e315ca75cc..541f2e10ba 100644 --- a/arch/inst/Q/fcvt.q.h.yaml +++ b/arch/inst/Q/fcvt.q.h.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fcvt.q.l.yaml b/arch/inst/Q/fcvt.q.l.yaml index eff9c93427..092d57110b 100644 --- a/arch/inst/Q/fcvt.q.l.yaml +++ b/arch/inst/Q/fcvt.q.l.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fcvt.q.lu.yaml b/arch/inst/Q/fcvt.q.lu.yaml index fcc7555a20..01572ba4a2 100644 --- a/arch/inst/Q/fcvt.q.lu.yaml +++ b/arch/inst/Q/fcvt.q.lu.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fcvt.q.s.yaml b/arch/inst/Q/fcvt.q.s.yaml index f01c73066c..6f4024c5bf 100644 --- a/arch/inst/Q/fcvt.q.s.yaml +++ b/arch/inst/Q/fcvt.q.s.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fcvt.q.w.yaml b/arch/inst/Q/fcvt.q.w.yaml index e03a6f7af7..d92b57d35b 100644 --- a/arch/inst/Q/fcvt.q.w.yaml +++ b/arch/inst/Q/fcvt.q.w.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fcvt.q.wu.yaml b/arch/inst/Q/fcvt.q.wu.yaml index 2dd85ff079..05c0da5e1c 100644 --- a/arch/inst/Q/fcvt.q.wu.yaml +++ b/arch/inst/Q/fcvt.q.wu.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fcvt.s.q.yaml b/arch/inst/Q/fcvt.s.q.yaml index bb24b7ec78..a772446dab 100644 --- a/arch/inst/Q/fcvt.s.q.yaml +++ b/arch/inst/Q/fcvt.s.q.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fcvt.w.q.yaml b/arch/inst/Q/fcvt.w.q.yaml index c414a695a4..93b69f6247 100644 --- a/arch/inst/Q/fcvt.w.q.yaml +++ b/arch/inst/Q/fcvt.w.q.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fcvt.wu.q.yaml b/arch/inst/Q/fcvt.wu.q.yaml index 54b157cddf..5d66b2af92 100644 --- a/arch/inst/Q/fcvt.wu.q.yaml +++ b/arch/inst/Q/fcvt.wu.q.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fdiv.q.yaml b/arch/inst/Q/fdiv.q.yaml index 56f1cd7c55..63e3fd2f86 100644 --- a/arch/inst/Q/fdiv.q.yaml +++ b/arch/inst/Q/fdiv.q.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/feq.q.yaml b/arch/inst/Q/feq.q.yaml index 8522aaa507..14286fb68a 100644 --- a/arch/inst/Q/feq.q.yaml +++ b/arch/inst/Q/feq.q.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fle.q.yaml b/arch/inst/Q/fle.q.yaml index e684af70ab..9ad903ba24 100644 --- a/arch/inst/Q/fle.q.yaml +++ b/arch/inst/Q/fle.q.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fleq.q.yaml b/arch/inst/Q/fleq.q.yaml index 155862a4c8..5cb9b831ec 100644 --- a/arch/inst/Q/fleq.q.yaml +++ b/arch/inst/Q/fleq.q.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fli.q.yaml b/arch/inst/Q/fli.q.yaml index 87b4eb709e..aa72738305 100644 --- a/arch/inst/Q/fli.q.yaml +++ b/arch/inst/Q/fli.q.yaml @@ -23,4 +23,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/flq.yaml b/arch/inst/Q/flq.yaml index 4ca374e8d3..d013be44a7 100644 --- a/arch/inst/Q/flq.yaml +++ b/arch/inst/Q/flq.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/flt.q.yaml b/arch/inst/Q/flt.q.yaml index 404b81da4a..5a400c7766 100644 --- a/arch/inst/Q/flt.q.yaml +++ b/arch/inst/Q/flt.q.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fltq.q.yaml b/arch/inst/Q/fltq.q.yaml index 04ba644fb3..b80f30f474 100644 --- a/arch/inst/Q/fltq.q.yaml +++ b/arch/inst/Q/fltq.q.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fmadd.q.yaml b/arch/inst/Q/fmadd.q.yaml index 43f288a434..7977f8f95c 100644 --- a/arch/inst/Q/fmadd.q.yaml +++ b/arch/inst/Q/fmadd.q.yaml @@ -28,4 +28,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fmax.q.yaml b/arch/inst/Q/fmax.q.yaml index 5847f13ece..ff2069f090 100644 --- a/arch/inst/Q/fmax.q.yaml +++ b/arch/inst/Q/fmax.q.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fmaxm.q.yaml b/arch/inst/Q/fmaxm.q.yaml index 8805cbb634..9ecca0aeca 100644 --- a/arch/inst/Q/fmaxm.q.yaml +++ b/arch/inst/Q/fmaxm.q.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fmin.q.yaml b/arch/inst/Q/fmin.q.yaml index c46d946dfe..62f30485b0 100644 --- a/arch/inst/Q/fmin.q.yaml +++ b/arch/inst/Q/fmin.q.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fminm.q.yaml b/arch/inst/Q/fminm.q.yaml index 853f02fb6b..516edc0bc4 100644 --- a/arch/inst/Q/fminm.q.yaml +++ b/arch/inst/Q/fminm.q.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fmsub.q.yaml b/arch/inst/Q/fmsub.q.yaml index f036761a9b..c92ed5350f 100644 --- a/arch/inst/Q/fmsub.q.yaml +++ b/arch/inst/Q/fmsub.q.yaml @@ -28,4 +28,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fmul.q.yaml b/arch/inst/Q/fmul.q.yaml index be9d0d85d9..c983cf8fb0 100644 --- a/arch/inst/Q/fmul.q.yaml +++ b/arch/inst/Q/fmul.q.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fmvh.x.q.yaml b/arch/inst/Q/fmvh.x.q.yaml index 73fbe8c67f..f067240ac0 100644 --- a/arch/inst/Q/fmvh.x.q.yaml +++ b/arch/inst/Q/fmvh.x.q.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fmvp.q.x.yaml b/arch/inst/Q/fmvp.q.x.yaml index 2f450b0f62..258e7ccc85 100644 --- a/arch/inst/Q/fmvp.q.x.yaml +++ b/arch/inst/Q/fmvp.q.x.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fnmadd.q.yaml b/arch/inst/Q/fnmadd.q.yaml index 714401052e..de290b9f3e 100644 --- a/arch/inst/Q/fnmadd.q.yaml +++ b/arch/inst/Q/fnmadd.q.yaml @@ -28,4 +28,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fnmsub.q.yaml b/arch/inst/Q/fnmsub.q.yaml index a5d3ea469b..805f14c422 100644 --- a/arch/inst/Q/fnmsub.q.yaml +++ b/arch/inst/Q/fnmsub.q.yaml @@ -28,4 +28,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fround.q.yaml b/arch/inst/Q/fround.q.yaml index 664a7afe89..ea1718ab4d 100644 --- a/arch/inst/Q/fround.q.yaml +++ b/arch/inst/Q/fround.q.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/froundnx.q.yaml b/arch/inst/Q/froundnx.q.yaml index e1a7effcb3..ffea7e08cd 100644 --- a/arch/inst/Q/froundnx.q.yaml +++ b/arch/inst/Q/froundnx.q.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fsgnj.q.yaml b/arch/inst/Q/fsgnj.q.yaml index 0406484c29..489b849900 100644 --- a/arch/inst/Q/fsgnj.q.yaml +++ b/arch/inst/Q/fsgnj.q.yaml @@ -27,4 +27,3 @@ pseudoinstructions: - when: (rs2 == rs1) to: fmv.q operation(): | - diff --git a/arch/inst/Q/fsgnjn.q.yaml b/arch/inst/Q/fsgnjn.q.yaml index 732314c792..3dc53bba5b 100644 --- a/arch/inst/Q/fsgnjn.q.yaml +++ b/arch/inst/Q/fsgnjn.q.yaml @@ -27,4 +27,3 @@ pseudoinstructions: - when: (rs2 == rs1) to: fneg.q operation(): | - diff --git a/arch/inst/Q/fsgnjx.q.yaml b/arch/inst/Q/fsgnjx.q.yaml index 82c27a27e4..2cec0796ab 100644 --- a/arch/inst/Q/fsgnjx.q.yaml +++ b/arch/inst/Q/fsgnjx.q.yaml @@ -27,4 +27,3 @@ pseudoinstructions: - when: (rs2 == rs1) to: fabs.q operation(): | - diff --git a/arch/inst/Q/fsq.yaml b/arch/inst/Q/fsq.yaml index 564999cb99..1b74624a55 100644 --- a/arch/inst/Q/fsq.yaml +++ b/arch/inst/Q/fsq.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fsqrt.q.yaml b/arch/inst/Q/fsqrt.q.yaml index 73c157676e..9fa9ab3467 100644 --- a/arch/inst/Q/fsqrt.q.yaml +++ b/arch/inst/Q/fsqrt.q.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Q/fsub.q.yaml b/arch/inst/Q/fsub.q.yaml index 7695cd7634..0db8b161c1 100644 --- a/arch/inst/Q/fsub.q.yaml +++ b/arch/inst/Q/fsub.q.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/S/sfence.vma.yaml b/arch/inst/S/sfence.vma.yaml index e7e380dddc..8852bf1cfa 100644 --- a/arch/inst/S/sfence.vma.yaml +++ b/arch/inst/S/sfence.vma.yaml @@ -321,7 +321,3 @@ sail(): | Machine => { flush_TLB(asid, addr); RETIRE_SUCCESS } } } - - - - diff --git a/arch/inst/S/sret.yaml b/arch/inst/S/sret.yaml index f4a3f09e64..3dd2755d14 100644 --- a/arch/inst/S/sret.yaml +++ b/arch/inst/S/sret.yaml @@ -29,7 +29,7 @@ description: | |=== *When the current privlege mode is VS-mode* - + `sret` sets `vsstatus.SPP` = 0, `vsstatus.SIE` = `vstatus.SPIE`, and `vsstatus.SPIE` = 1, changes the privlege mode according to the table below, @@ -54,7 +54,7 @@ access: vs: sometimes vu: never access_detail: | - Access is determined as follows: + Access is determined as follows: [%autowidth] |=== @@ -92,7 +92,7 @@ operation(): | raise (ExceptionCode::IllegalInstruction, mode(), $encoding); } else if (mode() == PrivilegeMode::VU || mode() == PrivilegeMode::VS) { raise (ExceptionCode::VirtualInstruction, mode(), $encoding); - } + } } } else { if (mode() != PrivilegeMode::U) { @@ -143,7 +143,3 @@ sail(): | RETIRE_SUCCESS } } - - - - diff --git a/arch/inst/Sdext/dret.yaml b/arch/inst/Sdext/dret.yaml index e2ddf182cd..e8e21a0eab 100644 --- a/arch/inst/Sdext/dret.yaml +++ b/arch/inst/Sdext/dret.yaml @@ -18,4 +18,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Smdbltrp/sctrclr.yaml b/arch/inst/Smdbltrp/sctrclr.yaml index cb1bf2f08c..f5bd33fb3d 100644 --- a/arch/inst/Smdbltrp/sctrclr.yaml +++ b/arch/inst/Smdbltrp/sctrclr.yaml @@ -18,4 +18,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Smrnmi/mnret.yaml b/arch/inst/Smrnmi/mnret.yaml index 0b8abd110a..5019c47bd6 100644 --- a/arch/inst/Smrnmi/mnret.yaml +++ b/arch/inst/Smrnmi/mnret.yaml @@ -18,4 +18,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Svinval/hinval.gvma.yaml b/arch/inst/Svinval/hinval.gvma.yaml index 5e5da11542..e53479102d 100644 --- a/arch/inst/Svinval/hinval.gvma.yaml +++ b/arch/inst/Svinval/hinval.gvma.yaml @@ -85,4 +85,3 @@ operation(): | } # else, silently do nothing } - \ No newline at end of file diff --git a/arch/inst/Svinval/hinval.vvma.yaml b/arch/inst/Svinval/hinval.vvma.yaml index f987382aac..4b65e53c23 100644 --- a/arch/inst/Svinval/hinval.vvma.yaml +++ b/arch/inst/Svinval/hinval.vvma.yaml @@ -85,4 +85,3 @@ operation(): | } # else, silently do nothing } - \ No newline at end of file diff --git a/arch/inst/Svinval/sfence.w.inval.yaml b/arch/inst/Svinval/sfence.w.inval.yaml index 3927e4811e..037c5d0b3e 100644 --- a/arch/inst/Svinval/sfence.w.inval.yaml +++ b/arch/inst/Svinval/sfence.w.inval.yaml @@ -38,4 +38,3 @@ operation(): | vma_type.gstage = true; } order_pgtbl_writes_before_vmafence(vma_type); - \ No newline at end of file diff --git a/arch/inst/Svinval/sinval.vma.yaml b/arch/inst/Svinval/sinval.vma.yaml index 4be7636647..76f77099ed 100644 --- a/arch/inst/Svinval/sinval.vma.yaml +++ b/arch/inst/Svinval/sinval.vma.yaml @@ -95,4 +95,3 @@ operation(): | } # else, silently do nothing } - \ No newline at end of file diff --git a/arch/inst/V/vaadd.vv.yaml b/arch/inst/V/vaadd.vv.yaml index 329c014f9c..3cbcf12412 100644 --- a/arch/inst/V/vaadd.vv.yaml +++ b/arch/inst/V/vaadd.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -102,9 +102,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vaadd.vx.yaml b/arch/inst/V/vaadd.vx.yaml index 12f3ab53c6..e806156133 100644 --- a/arch/inst/V/vaadd.vx.yaml +++ b/arch/inst/V/vaadd.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -111,9 +111,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vaaddu.vv.yaml b/arch/inst/V/vaaddu.vv.yaml index 08fc153ce6..6c9876175c 100644 --- a/arch/inst/V/vaaddu.vv.yaml +++ b/arch/inst/V/vaaddu.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -102,9 +102,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vaaddu.vx.yaml b/arch/inst/V/vaaddu.vx.yaml index e02ff1000c..ed14af74b8 100644 --- a/arch/inst/V/vaaddu.vx.yaml +++ b/arch/inst/V/vaaddu.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -111,9 +111,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vadc.vim.yaml b/arch/inst/V/vadc.vim.yaml index 4979da49e5..a071d8dced 100644 --- a/arch/inst/V/vadc.vim.yaml +++ b/arch/inst/V/vadc.vim.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -33,27 +33,27 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_masked(vd) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + /* for bypassing normal masking in init_masked_result */ vec_trues : vector('n, dec, bool) = undefined; foreach (i from 0 to (num_elem - 1)) { vec_trues[i] = true }; - + let vm_val : vector('n, dec, bool) = read_vmask_carry(num_elem, 0b0, 0b00000); let imm_val : bits('m) = sign_extend(simm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vec_trues); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -61,9 +61,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vadc.vvm.yaml b/arch/inst/V/vadc.vvm.yaml index db8e26b38d..8d3df8a976 100644 --- a/arch/inst/V/vadc.vvm.yaml +++ b/arch/inst/V/vadc.vvm.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -33,27 +33,27 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_masked(vd) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + /* for bypassing normal masking in init_masked_result */ vec_trues : vector('n, dec, bool) = undefined; foreach (i from 0 to (num_elem - 1)) { vec_trues[i] = true }; - + let vm_val : vector('n, dec, bool) = read_vmask_carry(num_elem, 0b0, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vec_trues); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -62,9 +62,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vadc.vxm.yaml b/arch/inst/V/vadc.vxm.yaml index 939eee7f2f..5ea996a2a1 100644 --- a/arch/inst/V/vadc.vxm.yaml +++ b/arch/inst/V/vadc.vxm.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -33,27 +33,27 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_masked(vd) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + /* for bypassing normal masking in init_masked_result */ vec_trues : vector('n, dec, bool) = undefined; foreach (i from 0 to (num_elem - 1)) { vec_trues[i] = true }; - + let vm_val : vector('n, dec, bool) = read_vmask_carry(num_elem, 0b0, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vec_trues); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -62,9 +62,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vadd.vi.yaml b/arch/inst/V/vadd.vi.yaml index f0246118a9..d1f92d0019 100644 --- a/arch/inst/V/vadd.vi.yaml +++ b/arch/inst/V/vadd.vi.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let imm_val : bits('m) = sign_extend(simm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -87,9 +87,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vadd.vv.yaml b/arch/inst/V/vadd.vv.yaml index 94fc3d0f30..889991a14e 100644 --- a/arch/inst/V/vadd.vv.yaml +++ b/arch/inst/V/vadd.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,21 +37,21 @@ sail(): | let LMUL_pow = get_lmul_pow(); let VLEN_pow = get_vlen_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -120,9 +120,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vadd.vx.yaml b/arch/inst/V/vadd.vx.yaml index 4067105f19..fde718be15 100644 --- a/arch/inst/V/vadd.vx.yaml +++ b/arch/inst/V/vadd.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -103,9 +103,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vand.vi.yaml b/arch/inst/V/vand.vi.yaml index eabfb2a017..fe43e62fdd 100644 --- a/arch/inst/V/vand.vi.yaml +++ b/arch/inst/V/vand.vi.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let imm_val : bits('m) = sign_extend(simm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -87,9 +87,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vand.vv.yaml b/arch/inst/V/vand.vv.yaml index 2efc4a5a08..f016448109 100644 --- a/arch/inst/V/vand.vv.yaml +++ b/arch/inst/V/vand.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,21 +37,21 @@ sail(): | let LMUL_pow = get_lmul_pow(); let VLEN_pow = get_vlen_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -120,9 +120,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vand.vx.yaml b/arch/inst/V/vand.vx.yaml index a0ba15ec10..efeb6977bc 100644 --- a/arch/inst/V/vand.vx.yaml +++ b/arch/inst/V/vand.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -103,9 +103,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vasub.vv.yaml b/arch/inst/V/vasub.vv.yaml index fd156c277b..7d1b7c2824 100644 --- a/arch/inst/V/vasub.vv.yaml +++ b/arch/inst/V/vasub.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -102,9 +102,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vasub.vx.yaml b/arch/inst/V/vasub.vx.yaml index b884f38445..54e8f87c6c 100644 --- a/arch/inst/V/vasub.vx.yaml +++ b/arch/inst/V/vasub.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -111,9 +111,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vasubu.vv.yaml b/arch/inst/V/vasubu.vv.yaml index 1597f08641..bc24e0a97d 100644 --- a/arch/inst/V/vasubu.vv.yaml +++ b/arch/inst/V/vasubu.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -102,9 +102,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vasubu.vx.yaml b/arch/inst/V/vasubu.vx.yaml index 7f6f2ee4be..af8d897ccf 100644 --- a/arch/inst/V/vasubu.vx.yaml +++ b/arch/inst/V/vasubu.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -111,9 +111,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vcompress.vm.yaml b/arch/inst/V/vcompress.vm.yaml index b997ea0f34..fd84e7a33f 100644 --- a/arch/inst/V/vcompress.vm.yaml +++ b/arch/inst/V/vcompress.vm.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,19 +35,19 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + /* vcompress should always be executed with a vstart of 0 */ if start_element != 0 | vs1 == vd | vs2 == vd | illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vs1_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; - + /* body elements */ vd_idx : nat = 0; foreach (i from 0 to (num_elem - 1)) { @@ -71,9 +71,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vcpop.m.yaml b/arch/inst/V/vcpop.m.yaml index 788cfbadfc..19bea2ad8e 100644 --- a/arch/inst/V/vcpop.m.yaml +++ b/arch/inst/V/vcpop.m.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vdiv.vv.yaml b/arch/inst/V/vdiv.vv.yaml index 668b545cde..a11d7fca27 100644 --- a/arch/inst/V/vdiv.vv.yaml +++ b/arch/inst/V/vdiv.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -102,9 +102,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vdiv.vx.yaml b/arch/inst/V/vdiv.vx.yaml index 34dbf33f27..88fbb442ab 100644 --- a/arch/inst/V/vdiv.vx.yaml +++ b/arch/inst/V/vdiv.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -111,9 +111,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vdivu.vv.yaml b/arch/inst/V/vdivu.vv.yaml index dad163f7a9..c0f330bb16 100644 --- a/arch/inst/V/vdivu.vv.yaml +++ b/arch/inst/V/vdivu.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -102,9 +102,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vdivu.vx.yaml b/arch/inst/V/vdivu.vx.yaml index 801e9f8ebb..ebf0b05f13 100644 --- a/arch/inst/V/vdivu.vx.yaml +++ b/arch/inst/V/vdivu.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -111,9 +111,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfadd.vf.yaml b/arch/inst/V/vfadd.vf.yaml index 218f5ca4c4..43a191d645 100644 --- a/arch/inst/V/vfadd.vf.yaml +++ b/arch/inst/V/vfadd.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -78,9 +78,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfadd.vv.yaml b/arch/inst/V/vfadd.vv.yaml index 3ece00bef4..e53b9c0306 100644 --- a/arch/inst/V/vfadd.vv.yaml +++ b/arch/inst/V/vfadd.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -67,9 +67,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfclass.v.yaml b/arch/inst/V/vfclass.v.yaml index 2feaae815f..72947448c4 100644 --- a/arch/inst/V/vfclass.v.yaml +++ b/arch/inst/V/vfclass.v.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -34,21 +34,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match vfunary1 { @@ -83,9 +83,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfcvt.f.x.v.yaml b/arch/inst/V/vfcvt.f.x.v.yaml index 5e9165fc7f..c94dd1143f 100644 --- a/arch/inst/V/vfcvt.f.x.v.yaml +++ b/arch/inst/V/vfcvt.f.x.v.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -34,20 +34,20 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match vfunary0 { @@ -108,9 +108,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfcvt.f.xu.v.yaml b/arch/inst/V/vfcvt.f.xu.v.yaml index c4ea16e9ee..f0b93c8643 100644 --- a/arch/inst/V/vfcvt.f.xu.v.yaml +++ b/arch/inst/V/vfcvt.f.xu.v.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -34,20 +34,20 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match vfunary0 { @@ -108,9 +108,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfcvt.rtz.x.f.v.yaml b/arch/inst/V/vfcvt.rtz.x.f.v.yaml index e175d2caf6..f2f2d7a34b 100644 --- a/arch/inst/V/vfcvt.rtz.x.f.v.yaml +++ b/arch/inst/V/vfcvt.rtz.x.f.v.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -34,20 +34,20 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match vfunary0 { @@ -108,9 +108,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfcvt.rtz.xu.f.v.yaml b/arch/inst/V/vfcvt.rtz.xu.f.v.yaml index dd94a1aa63..111c599846 100644 --- a/arch/inst/V/vfcvt.rtz.xu.f.v.yaml +++ b/arch/inst/V/vfcvt.rtz.xu.f.v.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -34,20 +34,20 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match vfunary0 { @@ -108,9 +108,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfcvt.x.f.v.yaml b/arch/inst/V/vfcvt.x.f.v.yaml index afd39c892a..8cca1f4db3 100644 --- a/arch/inst/V/vfcvt.x.f.v.yaml +++ b/arch/inst/V/vfcvt.x.f.v.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -34,20 +34,20 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match vfunary0 { @@ -108,9 +108,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfcvt.xu.f.v.yaml b/arch/inst/V/vfcvt.xu.f.v.yaml index a7c8b61482..7fa8aae9b0 100644 --- a/arch/inst/V/vfcvt.xu.f.v.yaml +++ b/arch/inst/V/vfcvt.xu.f.v.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -34,20 +34,20 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match vfunary0 { @@ -108,9 +108,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfdiv.vf.yaml b/arch/inst/V/vfdiv.vf.yaml index f46bae910e..131540b4e4 100644 --- a/arch/inst/V/vfdiv.vf.yaml +++ b/arch/inst/V/vfdiv.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -78,9 +78,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfdiv.vv.yaml b/arch/inst/V/vfdiv.vv.yaml index 10de2949a3..6590ecbf67 100644 --- a/arch/inst/V/vfdiv.vv.yaml +++ b/arch/inst/V/vfdiv.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -67,9 +67,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfirst.m.yaml b/arch/inst/V/vfirst.m.yaml index e899e06e4b..c05ebe85ca 100644 --- a/arch/inst/V/vfirst.m.yaml +++ b/arch/inst/V/vfirst.m.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -33,28 +33,27 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = unsigned(vlenb) * 8; - + if illegal_vd_unmasked() | not(assert_vstart(0)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs2); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, 0, vs2_val, vm_val); - + index : int = -1; foreach (i from 0 to (num_elem - 1)) { if index == -1 then { if mask[i] & vs2_val[i] then index = i; }; }; - + X(rd) = to_bits(sizeof(xlen), index); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfmacc.vf.yaml b/arch/inst/V/vfmacc.vf.yaml index 99ce1b313e..9c6529d0ce 100644 --- a/arch/inst/V/vfmacc.vf.yaml +++ b/arch/inst/V/vfmacc.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -66,9 +66,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfmacc.vv.yaml b/arch/inst/V/vfmacc.vv.yaml index b16c389a25..ae596e3e3b 100644 --- a/arch/inst/V/vfmacc.vv.yaml +++ b/arch/inst/V/vfmacc.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -66,9 +66,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfmadd.vf.yaml b/arch/inst/V/vfmadd.vf.yaml index 8ebc28dd0c..14d73f06f8 100644 --- a/arch/inst/V/vfmadd.vf.yaml +++ b/arch/inst/V/vfmadd.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -66,9 +66,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfmadd.vv.yaml b/arch/inst/V/vfmadd.vv.yaml index c4828106e2..2541125be1 100644 --- a/arch/inst/V/vfmadd.vv.yaml +++ b/arch/inst/V/vfmadd.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -66,9 +66,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfmax.vf.yaml b/arch/inst/V/vfmax.vf.yaml index 552c300efe..0cc30b7346 100644 --- a/arch/inst/V/vfmax.vf.yaml +++ b/arch/inst/V/vfmax.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -78,9 +78,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfmax.vv.yaml b/arch/inst/V/vfmax.vv.yaml index 2876669455..743ea0f91f 100644 --- a/arch/inst/V/vfmax.vv.yaml +++ b/arch/inst/V/vfmax.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -67,9 +67,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfmerge.vfm.yaml b/arch/inst/V/vfmerge.vfm.yaml index 254c60810d..86dd3a028f 100644 --- a/arch/inst/V/vfmerge.vfm.yaml +++ b/arch/inst/V/vfmerge.vfm.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,19 +37,19 @@ sail(): | let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); /* max(VLMAX,VLEN/SEW)) */ let real_num_elem = if LMUL_pow >= 0 then num_elem else num_elem / (0 - LMUL_pow); /* VLMAX */ - + if illegal_fp_vd_masked(vd, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; - + let tail_ag : agtype = get_vtype_vta(); foreach (i from 0 to (num_elem - 1)) { if i < start_element then { @@ -64,9 +64,8 @@ sail(): | result[i] = if vm_val[i] then rs1_val else vs2_val[i] } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfmin.vf.yaml b/arch/inst/V/vfmin.vf.yaml index e6d871cd03..ab540d32b6 100644 --- a/arch/inst/V/vfmin.vf.yaml +++ b/arch/inst/V/vfmin.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -78,9 +78,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfmin.vv.yaml b/arch/inst/V/vfmin.vv.yaml index abf1b633b5..991efa7e80 100644 --- a/arch/inst/V/vfmin.vv.yaml +++ b/arch/inst/V/vfmin.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -67,9 +67,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfmsac.vf.yaml b/arch/inst/V/vfmsac.vf.yaml index 1f43e1cd8c..34c3c371b5 100644 --- a/arch/inst/V/vfmsac.vf.yaml +++ b/arch/inst/V/vfmsac.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -66,9 +66,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfmsac.vv.yaml b/arch/inst/V/vfmsac.vv.yaml index b4215b02e8..1e734383a0 100644 --- a/arch/inst/V/vfmsac.vv.yaml +++ b/arch/inst/V/vfmsac.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -66,9 +66,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfmsub.vf.yaml b/arch/inst/V/vfmsub.vf.yaml index 7850998414..ced3598cb3 100644 --- a/arch/inst/V/vfmsub.vf.yaml +++ b/arch/inst/V/vfmsub.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -66,9 +66,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfmsub.vv.yaml b/arch/inst/V/vfmsub.vv.yaml index cf3a1fadb0..e33500bb50 100644 --- a/arch/inst/V/vfmsub.vv.yaml +++ b/arch/inst/V/vfmsub.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -66,9 +66,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfmul.vf.yaml b/arch/inst/V/vfmul.vf.yaml index 25c1b668dc..74a6030002 100644 --- a/arch/inst/V/vfmul.vf.yaml +++ b/arch/inst/V/vfmul.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -78,9 +78,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfmul.vv.yaml b/arch/inst/V/vfmul.vv.yaml index b569def984..f1cb3a8c79 100644 --- a/arch/inst/V/vfmul.vv.yaml +++ b/arch/inst/V/vfmul.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -67,9 +67,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfmv.f.s.yaml b/arch/inst/V/vfmv.f.s.yaml index 2a0a9885c5..c3f72cd968 100644 --- a/arch/inst/V/vfmv.f.s.yaml +++ b/arch/inst/V/vfmv.f.s.yaml @@ -22,7 +22,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -31,14 +31,14 @@ sail(): | let rm_3b = fcsr.FRM(); let SEW = get_sew(); let num_elem = get_num_elem(0, SEW); - + if illegal_fp_vd_unmasked(SEW, rm_3b) | SEW > sizeof(flen) then { handle_illegal(); return RETIRE_FAIL }; assert(num_elem > 0 & SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, 0, vs2); match 'm { 16 => F_H(rd) = vs2_val[0], @@ -46,7 +46,6 @@ sail(): | 64 => F_D(rd) = vs2_val[0] }; vstart = zeros(); - + RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfmv.s.f.yaml b/arch/inst/V/vfmv.s.f.yaml index 04ffb840ce..80b57dc40d 100644 --- a/arch/inst/V/vfmv.s.f.yaml +++ b/arch/inst/V/vfmv.s.f.yaml @@ -22,7 +22,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -31,24 +31,24 @@ sail(): | let rm_3b = fcsr.FRM(); let SEW = get_sew(); let num_elem = get_num_elem(0, SEW); - + if illegal_fp_vd_unmasked(SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(num_elem > 0 & SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b1, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, 0, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, 0, vd_val, vm_val); - + /* one body element */ if mask[0] then result[0] = rs1_val; - + /* others treated as tail elements */ let tail_ag : agtype = get_vtype_vta(); foreach (i from 1 to (num_elem - 1)) { @@ -57,9 +57,8 @@ sail(): | AGNOSTIC => vd_val[i] /* TODO: configuration support */ } }; - + write_vreg(num_elem, SEW, 0, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfmv.v.f.yaml b/arch/inst/V/vfmv.v.f.yaml index 51b4404e33..e1fe60deb3 100644 --- a/arch/inst/V/vfmv.v.f.yaml +++ b/arch/inst/V/vfmv.v.f.yaml @@ -22,7 +22,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -32,27 +32,26 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_vd_unmasked(SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b1, 0b00000); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then result[i] = rs1_val }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfncvt.f.f.w.yaml b/arch/inst/V/vfncvt.f.f.w.yaml index c193f5a80f..d07719336d 100644 --- a/arch/inst/V/vfncvt.f.f.w.yaml +++ b/arch/inst/V/vfncvt.f.f.w.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,23 +36,23 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match vfnunary0 { @@ -131,9 +131,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfncvt.f.x.w.yaml b/arch/inst/V/vfncvt.f.x.w.yaml index 5c6c764e8e..64076200d2 100644 --- a/arch/inst/V/vfncvt.f.x.w.yaml +++ b/arch/inst/V/vfncvt.f.x.w.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,23 +36,23 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match vfnunary0 { @@ -131,9 +131,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfncvt.f.xu.w.yaml b/arch/inst/V/vfncvt.f.xu.w.yaml index 37df322068..1ffb9a8cb4 100644 --- a/arch/inst/V/vfncvt.f.xu.w.yaml +++ b/arch/inst/V/vfncvt.f.xu.w.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,23 +36,23 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match vfnunary0 { @@ -131,9 +131,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfncvt.rod.f.f.w.yaml b/arch/inst/V/vfncvt.rod.f.f.w.yaml index 574c2c1726..7b5c051c7a 100644 --- a/arch/inst/V/vfncvt.rod.f.f.w.yaml +++ b/arch/inst/V/vfncvt.rod.f.f.w.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,23 +36,23 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match vfnunary0 { @@ -131,9 +131,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfncvt.rtz.x.f.w.yaml b/arch/inst/V/vfncvt.rtz.x.f.w.yaml index d7ea4bec1e..a4537a2e78 100644 --- a/arch/inst/V/vfncvt.rtz.x.f.w.yaml +++ b/arch/inst/V/vfncvt.rtz.x.f.w.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,23 +36,23 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match vfnunary0 { @@ -131,9 +131,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfncvt.rtz.xu.f.w.yaml b/arch/inst/V/vfncvt.rtz.xu.f.w.yaml index 2bea9fff15..62bede1c42 100644 --- a/arch/inst/V/vfncvt.rtz.xu.f.w.yaml +++ b/arch/inst/V/vfncvt.rtz.xu.f.w.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,23 +36,23 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match vfnunary0 { @@ -131,9 +131,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfncvt.x.f.w.yaml b/arch/inst/V/vfncvt.x.f.w.yaml index f20b998b50..75ff14b03d 100644 --- a/arch/inst/V/vfncvt.x.f.w.yaml +++ b/arch/inst/V/vfncvt.x.f.w.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,23 +36,23 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match vfnunary0 { @@ -131,9 +131,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfncvt.xu.f.w.yaml b/arch/inst/V/vfncvt.xu.f.w.yaml index 6878beea4f..37345ccd04 100644 --- a/arch/inst/V/vfncvt.xu.f.w.yaml +++ b/arch/inst/V/vfncvt.xu.f.w.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,23 +36,23 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match vfnunary0 { @@ -131,9 +131,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfnmacc.vf.yaml b/arch/inst/V/vfnmacc.vf.yaml index 56e6ca4f27..b2c079a45c 100644 --- a/arch/inst/V/vfnmacc.vf.yaml +++ b/arch/inst/V/vfnmacc.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -66,9 +66,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfnmacc.vv.yaml b/arch/inst/V/vfnmacc.vv.yaml index e33d710ef3..7d09fa94d6 100644 --- a/arch/inst/V/vfnmacc.vv.yaml +++ b/arch/inst/V/vfnmacc.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -66,9 +66,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfnmadd.vf.yaml b/arch/inst/V/vfnmadd.vf.yaml index 4f55a64eae..4023db2a30 100644 --- a/arch/inst/V/vfnmadd.vf.yaml +++ b/arch/inst/V/vfnmadd.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -66,9 +66,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfnmadd.vv.yaml b/arch/inst/V/vfnmadd.vv.yaml index adcdaa9312..2f25198c45 100644 --- a/arch/inst/V/vfnmadd.vv.yaml +++ b/arch/inst/V/vfnmadd.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -66,9 +66,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfnmsac.vf.yaml b/arch/inst/V/vfnmsac.vf.yaml index bbfd36edd7..2e2a4c7206 100644 --- a/arch/inst/V/vfnmsac.vf.yaml +++ b/arch/inst/V/vfnmsac.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -66,9 +66,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfnmsac.vv.yaml b/arch/inst/V/vfnmsac.vv.yaml index ebece29cb0..28eddb89cc 100644 --- a/arch/inst/V/vfnmsac.vv.yaml +++ b/arch/inst/V/vfnmsac.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -66,9 +66,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfnmsub.vf.yaml b/arch/inst/V/vfnmsub.vf.yaml index 2af355ef8f..efab79dae7 100644 --- a/arch/inst/V/vfnmsub.vf.yaml +++ b/arch/inst/V/vfnmsub.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -66,9 +66,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfnmsub.vv.yaml b/arch/inst/V/vfnmsub.vv.yaml index 3272bacc4c..d279ebff9e 100644 --- a/arch/inst/V/vfnmsub.vv.yaml +++ b/arch/inst/V/vfnmsub.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -66,9 +66,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfrdiv.vf.yaml b/arch/inst/V/vfrdiv.vf.yaml index 2beaafcb76..78f64d7f1b 100644 --- a/arch/inst/V/vfrdiv.vf.yaml +++ b/arch/inst/V/vfrdiv.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -78,9 +78,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfrec7.v.yaml b/arch/inst/V/vfrec7.v.yaml index e17cc89b4e..40a7439bd3 100644 --- a/arch/inst/V/vfrec7.v.yaml +++ b/arch/inst/V/vfrec7.v.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -34,21 +34,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match vfunary1 { @@ -83,9 +83,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfredmax.vs.yaml b/arch/inst/V/vfredmax.vs.yaml index 9162d9cfdf..12277a66b9 100644 --- a/arch/inst/V/vfredmax.vs.yaml +++ b/arch/inst/V/vfredmax.vs.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,10 +35,9 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem_vs = get_num_elem(LMUL_pow, SEW); - + if funct6 == FVV_VFWREDOSUM | funct6 == FVV_VFWREDUSUM then process_rfvv_widen(funct6, vm, vs2, vs1, vd, num_elem_vs, SEW, LMUL_pow) else process_rfvv_single(funct6, vm, vs2, vs1, vd, num_elem_vs, SEW, LMUL_pow) } - diff --git a/arch/inst/V/vfredmin.vs.yaml b/arch/inst/V/vfredmin.vs.yaml index 2421e017fc..b4609fd352 100644 --- a/arch/inst/V/vfredmin.vs.yaml +++ b/arch/inst/V/vfredmin.vs.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,10 +35,9 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem_vs = get_num_elem(LMUL_pow, SEW); - + if funct6 == FVV_VFWREDOSUM | funct6 == FVV_VFWREDUSUM then process_rfvv_widen(funct6, vm, vs2, vs1, vd, num_elem_vs, SEW, LMUL_pow) else process_rfvv_single(funct6, vm, vs2, vs1, vd, num_elem_vs, SEW, LMUL_pow) } - diff --git a/arch/inst/V/vfredosum.vs.yaml b/arch/inst/V/vfredosum.vs.yaml index e343e1628b..bea668e79e 100644 --- a/arch/inst/V/vfredosum.vs.yaml +++ b/arch/inst/V/vfredosum.vs.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,10 +35,9 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem_vs = get_num_elem(LMUL_pow, SEW); - + if funct6 == FVV_VFWREDOSUM | funct6 == FVV_VFWREDUSUM then process_rfvv_widen(funct6, vm, vs2, vs1, vd, num_elem_vs, SEW, LMUL_pow) else process_rfvv_single(funct6, vm, vs2, vs1, vd, num_elem_vs, SEW, LMUL_pow) } - diff --git a/arch/inst/V/vfredusum.vs.yaml b/arch/inst/V/vfredusum.vs.yaml index 2b6938156e..b8e38ee7d6 100644 --- a/arch/inst/V/vfredusum.vs.yaml +++ b/arch/inst/V/vfredusum.vs.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,10 +35,9 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem_vs = get_num_elem(LMUL_pow, SEW); - + if funct6 == FVV_VFWREDOSUM | funct6 == FVV_VFWREDUSUM then process_rfvv_widen(funct6, vm, vs2, vs1, vd, num_elem_vs, SEW, LMUL_pow) else process_rfvv_single(funct6, vm, vs2, vs1, vd, num_elem_vs, SEW, LMUL_pow) } - diff --git a/arch/inst/V/vfrsqrt7.v.yaml b/arch/inst/V/vfrsqrt7.v.yaml index 2276abd0c3..fbbf128cd0 100644 --- a/arch/inst/V/vfrsqrt7.v.yaml +++ b/arch/inst/V/vfrsqrt7.v.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -34,21 +34,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match vfunary1 { @@ -83,9 +83,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfrsub.vf.yaml b/arch/inst/V/vfrsub.vf.yaml index 7175d5ea17..1dea2de7e3 100644 --- a/arch/inst/V/vfrsub.vf.yaml +++ b/arch/inst/V/vfrsub.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -78,9 +78,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfsgnj.vf.yaml b/arch/inst/V/vfsgnj.vf.yaml index 46fbfb4957..b5bad7a7b6 100644 --- a/arch/inst/V/vfsgnj.vf.yaml +++ b/arch/inst/V/vfsgnj.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -78,9 +78,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfsgnj.vv.yaml b/arch/inst/V/vfsgnj.vv.yaml index f256057d40..c62ba75b27 100644 --- a/arch/inst/V/vfsgnj.vv.yaml +++ b/arch/inst/V/vfsgnj.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -67,9 +67,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfsgnjn.vf.yaml b/arch/inst/V/vfsgnjn.vf.yaml index 6de073a93e..aadd118eed 100644 --- a/arch/inst/V/vfsgnjn.vf.yaml +++ b/arch/inst/V/vfsgnjn.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -78,9 +78,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfsgnjn.vv.yaml b/arch/inst/V/vfsgnjn.vv.yaml index 3e4d499fad..f5e6507af1 100644 --- a/arch/inst/V/vfsgnjn.vv.yaml +++ b/arch/inst/V/vfsgnjn.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -67,9 +67,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfsgnjx.vf.yaml b/arch/inst/V/vfsgnjx.vf.yaml index eb4597bdc8..39e3e1bcc9 100644 --- a/arch/inst/V/vfsgnjx.vf.yaml +++ b/arch/inst/V/vfsgnjx.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -78,9 +78,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfsgnjx.vv.yaml b/arch/inst/V/vfsgnjx.vv.yaml index 3b16d69b60..7f674c9dca 100644 --- a/arch/inst/V/vfsgnjx.vv.yaml +++ b/arch/inst/V/vfsgnjx.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -67,9 +67,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfslide1down.vf.yaml b/arch/inst/V/vfslide1down.vf.yaml index 525f9fb534..e30cfe155d 100644 --- a/arch/inst/V/vfslide1down.vf.yaml +++ b/arch/inst/V/vfslide1down.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -78,9 +78,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfslide1up.vf.yaml b/arch/inst/V/vfslide1up.vf.yaml index a76a2c433f..eb6f1da876 100644 --- a/arch/inst/V/vfslide1up.vf.yaml +++ b/arch/inst/V/vfslide1up.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -78,9 +78,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfsqrt.v.yaml b/arch/inst/V/vfsqrt.v.yaml index f3ddf59242..9fa78136e1 100644 --- a/arch/inst/V/vfsqrt.v.yaml +++ b/arch/inst/V/vfsqrt.v.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -34,21 +34,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match vfunary1 { @@ -83,9 +83,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfsub.vf.yaml b/arch/inst/V/vfsub.vf.yaml index d2ebfd4473..d550048917 100644 --- a/arch/inst/V/vfsub.vf.yaml +++ b/arch/inst/V/vfsub.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -78,9 +78,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfsub.vv.yaml b/arch/inst/V/vfsub.vv.yaml index 6a91b45490..099d1ca6e1 100644 --- a/arch/inst/V/vfsub.vv.yaml +++ b/arch/inst/V/vfsub.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -67,9 +67,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfwadd.vf.yaml b/arch/inst/V/vfwadd.vf.yaml index 26979ae975..8449fafc3c 100644 --- a/arch/inst/V/vfwadd.vf.yaml +++ b/arch/inst/V/vfwadd.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,25 +38,25 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW >= 16 & SEW_widen <= 64); - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -66,9 +66,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfwadd.vv.yaml b/arch/inst/V/vfwadd.vv.yaml index 2a9d94d136..fdc57af864 100644 --- a/arch/inst/V/vfwadd.vv.yaml +++ b/arch/inst/V/vfwadd.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,26 +38,26 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW >= 16 & SEW_widen <= 64); - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -67,9 +67,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfwadd.wf.yaml b/arch/inst/V/vfwadd.wf.yaml index 9849209240..6a169ba6a0 100644 --- a/arch/inst/V/vfwadd.wf.yaml +++ b/arch/inst/V/vfwadd.wf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,24 +38,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW >= 16 & SEW_widen <= 64); - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -64,9 +64,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfwadd.wv.yaml b/arch/inst/V/vfwadd.wv.yaml index 1fd17c23dc..668fde5635 100644 --- a/arch/inst/V/vfwadd.wv.yaml +++ b/arch/inst/V/vfwadd.wv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,25 +38,25 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW >= 16 & SEW_widen <= 64); - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -65,9 +65,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfwcvt.f.f.v.yaml b/arch/inst/V/vfwcvt.f.f.v.yaml index 487d919fbd..13891efc9d 100644 --- a/arch/inst/V/vfwcvt.f.f.v.yaml +++ b/arch/inst/V/vfwcvt.f.f.v.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,24 +36,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW >= 8 & SEW_widen <= 64); - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match vfwunary0 { @@ -123,9 +123,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfwcvt.f.x.v.yaml b/arch/inst/V/vfwcvt.f.x.v.yaml index f6c784e068..a4cac43c79 100644 --- a/arch/inst/V/vfwcvt.f.x.v.yaml +++ b/arch/inst/V/vfwcvt.f.x.v.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,24 +36,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW >= 8 & SEW_widen <= 64); - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match vfwunary0 { @@ -123,9 +123,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfwcvt.f.xu.v.yaml b/arch/inst/V/vfwcvt.f.xu.v.yaml index da71b1a3be..2451307f09 100644 --- a/arch/inst/V/vfwcvt.f.xu.v.yaml +++ b/arch/inst/V/vfwcvt.f.xu.v.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,24 +36,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW >= 8 & SEW_widen <= 64); - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match vfwunary0 { @@ -123,9 +123,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfwcvt.rtz.x.f.v.yaml b/arch/inst/V/vfwcvt.rtz.x.f.v.yaml index 751d91c8be..ccd031fbba 100644 --- a/arch/inst/V/vfwcvt.rtz.x.f.v.yaml +++ b/arch/inst/V/vfwcvt.rtz.x.f.v.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,24 +36,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW >= 8 & SEW_widen <= 64); - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match vfwunary0 { @@ -123,9 +123,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfwcvt.rtz.xu.f.v.yaml b/arch/inst/V/vfwcvt.rtz.xu.f.v.yaml index 271c146197..2df02a61bc 100644 --- a/arch/inst/V/vfwcvt.rtz.xu.f.v.yaml +++ b/arch/inst/V/vfwcvt.rtz.xu.f.v.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,24 +36,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW >= 8 & SEW_widen <= 64); - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match vfwunary0 { @@ -123,9 +123,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfwcvt.x.f.v.yaml b/arch/inst/V/vfwcvt.x.f.v.yaml index e6d8434a4f..b6337cd145 100644 --- a/arch/inst/V/vfwcvt.x.f.v.yaml +++ b/arch/inst/V/vfwcvt.x.f.v.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,24 +36,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW >= 8 & SEW_widen <= 64); - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match vfwunary0 { @@ -123,9 +123,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfwcvt.xu.f.v.yaml b/arch/inst/V/vfwcvt.xu.f.v.yaml index fe088fcb2c..dc47501e7b 100644 --- a/arch/inst/V/vfwcvt.xu.f.v.yaml +++ b/arch/inst/V/vfwcvt.xu.f.v.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,24 +36,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW >= 8 & SEW_widen <= 64); - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match vfwunary0 { @@ -123,9 +123,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfwmacc.vf.yaml b/arch/inst/V/vfwmacc.vf.yaml index 0f015804ab..bb3c336f8d 100644 --- a/arch/inst/V/vfwmacc.vf.yaml +++ b/arch/inst/V/vfwmacc.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,25 +38,25 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW >= 16 & SEW_widen <= 64); - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -67,9 +67,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfwmacc.vv.yaml b/arch/inst/V/vfwmacc.vv.yaml index 0875df4579..18452f228f 100644 --- a/arch/inst/V/vfwmacc.vv.yaml +++ b/arch/inst/V/vfwmacc.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,26 +38,26 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW >= 16 & SEW_widen <= 64); - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -68,9 +68,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfwmsac.vf.yaml b/arch/inst/V/vfwmsac.vf.yaml index 0c33d367f6..2b48219488 100644 --- a/arch/inst/V/vfwmsac.vf.yaml +++ b/arch/inst/V/vfwmsac.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,25 +38,25 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW >= 16 & SEW_widen <= 64); - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -67,9 +67,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfwmsac.vv.yaml b/arch/inst/V/vfwmsac.vv.yaml index d2b52d9c83..06a86bfb54 100644 --- a/arch/inst/V/vfwmsac.vv.yaml +++ b/arch/inst/V/vfwmsac.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,26 +38,26 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW >= 16 & SEW_widen <= 64); - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -68,9 +68,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfwmul.vf.yaml b/arch/inst/V/vfwmul.vf.yaml index db717c712f..c1b8c8982a 100644 --- a/arch/inst/V/vfwmul.vf.yaml +++ b/arch/inst/V/vfwmul.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,25 +38,25 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW >= 16 & SEW_widen <= 64); - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -66,9 +66,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfwmul.vv.yaml b/arch/inst/V/vfwmul.vv.yaml index 8e07e64d7d..e91a5c378d 100644 --- a/arch/inst/V/vfwmul.vv.yaml +++ b/arch/inst/V/vfwmul.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,26 +38,26 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW >= 16 & SEW_widen <= 64); - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -67,9 +67,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfwnmacc.vf.yaml b/arch/inst/V/vfwnmacc.vf.yaml index d65aeb0702..67e5dcfe66 100644 --- a/arch/inst/V/vfwnmacc.vf.yaml +++ b/arch/inst/V/vfwnmacc.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,25 +38,25 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW >= 16 & SEW_widen <= 64); - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -67,9 +67,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfwnmacc.vv.yaml b/arch/inst/V/vfwnmacc.vv.yaml index f670042492..3968400265 100644 --- a/arch/inst/V/vfwnmacc.vv.yaml +++ b/arch/inst/V/vfwnmacc.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,26 +38,26 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW >= 16 & SEW_widen <= 64); - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -68,9 +68,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfwnmsac.vf.yaml b/arch/inst/V/vfwnmsac.vf.yaml index 42e73c7255..f5dc85df9f 100644 --- a/arch/inst/V/vfwnmsac.vf.yaml +++ b/arch/inst/V/vfwnmsac.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,25 +38,25 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW >= 16 & SEW_widen <= 64); - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -67,9 +67,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfwnmsac.vv.yaml b/arch/inst/V/vfwnmsac.vv.yaml index 4ab4e7dfcd..17af8f3393 100644 --- a/arch/inst/V/vfwnmsac.vv.yaml +++ b/arch/inst/V/vfwnmsac.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,26 +38,26 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW >= 16 & SEW_widen <= 64); - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -68,9 +68,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfwredosum.vs.yaml b/arch/inst/V/vfwredosum.vs.yaml index 86b130f17f..ea97af98ac 100644 --- a/arch/inst/V/vfwredosum.vs.yaml +++ b/arch/inst/V/vfwredosum.vs.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,10 +35,9 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem_vs = get_num_elem(LMUL_pow, SEW); - + if funct6 == FVV_VFWREDOSUM | funct6 == FVV_VFWREDUSUM then process_rfvv_widen(funct6, vm, vs2, vs1, vd, num_elem_vs, SEW, LMUL_pow) else process_rfvv_single(funct6, vm, vs2, vs1, vd, num_elem_vs, SEW, LMUL_pow) } - diff --git a/arch/inst/V/vfwredusum.vs.yaml b/arch/inst/V/vfwredusum.vs.yaml index 4e076feeae..b0e69de551 100644 --- a/arch/inst/V/vfwredusum.vs.yaml +++ b/arch/inst/V/vfwredusum.vs.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,10 +35,9 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem_vs = get_num_elem(LMUL_pow, SEW); - + if funct6 == FVV_VFWREDOSUM | funct6 == FVV_VFWREDUSUM then process_rfvv_widen(funct6, vm, vs2, vs1, vd, num_elem_vs, SEW, LMUL_pow) else process_rfvv_single(funct6, vm, vs2, vs1, vd, num_elem_vs, SEW, LMUL_pow) } - diff --git a/arch/inst/V/vfwsub.vf.yaml b/arch/inst/V/vfwsub.vf.yaml index 6ebf50ccda..d06f57f18e 100644 --- a/arch/inst/V/vfwsub.vf.yaml +++ b/arch/inst/V/vfwsub.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,25 +38,25 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW >= 16 & SEW_widen <= 64); - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -66,9 +66,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfwsub.vv.yaml b/arch/inst/V/vfwsub.vv.yaml index 31b111c9e3..02b06af2f6 100644 --- a/arch/inst/V/vfwsub.vv.yaml +++ b/arch/inst/V/vfwsub.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,26 +38,26 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW >= 16 & SEW_widen <= 64); - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -67,9 +67,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfwsub.wf.yaml b/arch/inst/V/vfwsub.wf.yaml index 5ec7bd5d30..1ec5f744c3 100644 --- a/arch/inst/V/vfwsub.wf.yaml +++ b/arch/inst/V/vfwsub.wf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,24 +38,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW >= 16 & SEW_widen <= 64); - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -64,9 +64,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vfwsub.wv.yaml b/arch/inst/V/vfwsub.wv.yaml index f60f19a6ac..c60ee91d16 100644 --- a/arch/inst/V/vfwsub.wv.yaml +++ b/arch/inst/V/vfwsub.wv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,25 +38,25 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW >= 16 & SEW_widen <= 64); - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -65,9 +65,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vid.v.yaml b/arch/inst/V/vid.v.yaml index 85f143afac..b5c27cc73c 100644 --- a/arch/inst/V/vid.v.yaml +++ b/arch/inst/V/vid.v.yaml @@ -22,7 +22,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -31,25 +31,24 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then result[i] = to_bits(SEW, i) }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/viota.m.yaml b/arch/inst/V/viota.m.yaml index f4b1e376eb..1991cdaa97 100644 --- a/arch/inst/V/viota.m.yaml +++ b/arch/inst/V/viota.m.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -33,21 +33,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) | not(assert_vstart(0)) | vd == vs2 then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + sum : int = 0; foreach (i from 0 to (num_elem - 1)) { if mask[i] then { @@ -55,9 +55,8 @@ sail(): | if vs2_val[i] then sum = sum + 1 } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vl1re16.v.yaml b/arch/inst/V/vl1re16.v.yaml index 2d2c4c2eba..0a6cb1075c 100644 --- a/arch/inst/V/vl1re16.v.yaml +++ b/arch/inst/V/vl1re16.v.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vl1re32.v.yaml b/arch/inst/V/vl1re32.v.yaml index e04d176d6c..294c7203e2 100644 --- a/arch/inst/V/vl1re32.v.yaml +++ b/arch/inst/V/vl1re32.v.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vl1re64.v.yaml b/arch/inst/V/vl1re64.v.yaml index b45371d967..0c1a4e6a39 100644 --- a/arch/inst/V/vl1re64.v.yaml +++ b/arch/inst/V/vl1re64.v.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vl1re8.v.yaml b/arch/inst/V/vl1re8.v.yaml index 8cef1447f1..7997910333 100644 --- a/arch/inst/V/vl1re8.v.yaml +++ b/arch/inst/V/vl1re8.v.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vl2re16.v.yaml b/arch/inst/V/vl2re16.v.yaml index ff73f66cea..e0cab471ff 100644 --- a/arch/inst/V/vl2re16.v.yaml +++ b/arch/inst/V/vl2re16.v.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vl2re32.v.yaml b/arch/inst/V/vl2re32.v.yaml index 3e258e9cca..e8e6aeb442 100644 --- a/arch/inst/V/vl2re32.v.yaml +++ b/arch/inst/V/vl2re32.v.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vl2re64.v.yaml b/arch/inst/V/vl2re64.v.yaml index 06d9c4ba15..785489b923 100644 --- a/arch/inst/V/vl2re64.v.yaml +++ b/arch/inst/V/vl2re64.v.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vl2re8.v.yaml b/arch/inst/V/vl2re8.v.yaml index 4820ef3fa9..70f528b523 100644 --- a/arch/inst/V/vl2re8.v.yaml +++ b/arch/inst/V/vl2re8.v.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vl4re16.v.yaml b/arch/inst/V/vl4re16.v.yaml index 1d091962f5..6a8533926f 100644 --- a/arch/inst/V/vl4re16.v.yaml +++ b/arch/inst/V/vl4re16.v.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vl4re32.v.yaml b/arch/inst/V/vl4re32.v.yaml index e2caa0c2c5..50ffcb9b74 100644 --- a/arch/inst/V/vl4re32.v.yaml +++ b/arch/inst/V/vl4re32.v.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vl4re64.v.yaml b/arch/inst/V/vl4re64.v.yaml index 01b32c48a4..8db40b0c62 100644 --- a/arch/inst/V/vl4re64.v.yaml +++ b/arch/inst/V/vl4re64.v.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vl4re8.v.yaml b/arch/inst/V/vl4re8.v.yaml index a56cc57e5b..0361ac50af 100644 --- a/arch/inst/V/vl4re8.v.yaml +++ b/arch/inst/V/vl4re8.v.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vl8re16.v.yaml b/arch/inst/V/vl8re16.v.yaml index 3a9d1b0aed..26214f47d1 100644 --- a/arch/inst/V/vl8re16.v.yaml +++ b/arch/inst/V/vl8re16.v.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vl8re32.v.yaml b/arch/inst/V/vl8re32.v.yaml index 747cf54386..b55e4987ff 100644 --- a/arch/inst/V/vl8re32.v.yaml +++ b/arch/inst/V/vl8re32.v.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vl8re64.v.yaml b/arch/inst/V/vl8re64.v.yaml index 3c32d35621..1d992927d3 100644 --- a/arch/inst/V/vl8re64.v.yaml +++ b/arch/inst/V/vl8re64.v.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vl8re8.v.yaml b/arch/inst/V/vl8re8.v.yaml index f424ac472f..e871bb99d9 100644 --- a/arch/inst/V/vl8re8.v.yaml +++ b/arch/inst/V/vl8re8.v.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vle16.v.yaml b/arch/inst/V/vle16.v.yaml index 993937d6e9..b936f52ac0 100644 --- a/arch/inst/V/vle16.v.yaml +++ b/arch/inst/V/vle16.v.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,9 +38,8 @@ sail(): | let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; let num_elem = get_num_elem(EMUL_pow, EEW); /* # of element of each register group */ let nf_int = nfields_int(nf); - + if illegal_load(vd, vm, nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vlseg(nf_int, vm, vd, load_width_bytes, rs1, EMUL_pow, num_elem) } - diff --git a/arch/inst/V/vle16ff.v.yaml b/arch/inst/V/vle16ff.v.yaml index e27dfed292..50b8812278 100644 --- a/arch/inst/V/vle16ff.v.yaml +++ b/arch/inst/V/vle16ff.v.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,9 +38,8 @@ sail(): | let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; let num_elem = get_num_elem(EMUL_pow, EEW); let nf_int = nfields_int(nf); - + if illegal_load(vd, vm, nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vlsegff(nf_int, vm, vd, load_width_bytes, rs1, EMUL_pow, num_elem) } - diff --git a/arch/inst/V/vle32.v.yaml b/arch/inst/V/vle32.v.yaml index 9106cbb53f..4925426055 100644 --- a/arch/inst/V/vle32.v.yaml +++ b/arch/inst/V/vle32.v.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,9 +38,8 @@ sail(): | let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; let num_elem = get_num_elem(EMUL_pow, EEW); /* # of element of each register group */ let nf_int = nfields_int(nf); - + if illegal_load(vd, vm, nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vlseg(nf_int, vm, vd, load_width_bytes, rs1, EMUL_pow, num_elem) } - diff --git a/arch/inst/V/vle32ff.v.yaml b/arch/inst/V/vle32ff.v.yaml index c19956a1bb..4de0bad438 100644 --- a/arch/inst/V/vle32ff.v.yaml +++ b/arch/inst/V/vle32ff.v.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,9 +38,8 @@ sail(): | let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; let num_elem = get_num_elem(EMUL_pow, EEW); let nf_int = nfields_int(nf); - + if illegal_load(vd, vm, nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vlsegff(nf_int, vm, vd, load_width_bytes, rs1, EMUL_pow, num_elem) } - diff --git a/arch/inst/V/vle64.v.yaml b/arch/inst/V/vle64.v.yaml index 5f455f5a72..75a9f9bb02 100644 --- a/arch/inst/V/vle64.v.yaml +++ b/arch/inst/V/vle64.v.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,9 +38,8 @@ sail(): | let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; let num_elem = get_num_elem(EMUL_pow, EEW); /* # of element of each register group */ let nf_int = nfields_int(nf); - + if illegal_load(vd, vm, nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vlseg(nf_int, vm, vd, load_width_bytes, rs1, EMUL_pow, num_elem) } - diff --git a/arch/inst/V/vle64ff.v.yaml b/arch/inst/V/vle64ff.v.yaml index acafd2aa6d..d9efeff029 100644 --- a/arch/inst/V/vle64ff.v.yaml +++ b/arch/inst/V/vle64ff.v.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,9 +38,8 @@ sail(): | let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; let num_elem = get_num_elem(EMUL_pow, EEW); let nf_int = nfields_int(nf); - + if illegal_load(vd, vm, nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vlsegff(nf_int, vm, vd, load_width_bytes, rs1, EMUL_pow, num_elem) } - diff --git a/arch/inst/V/vle8.v.yaml b/arch/inst/V/vle8.v.yaml index 12169fac50..a36a00ac14 100644 --- a/arch/inst/V/vle8.v.yaml +++ b/arch/inst/V/vle8.v.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,9 +38,8 @@ sail(): | let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; let num_elem = get_num_elem(EMUL_pow, EEW); /* # of element of each register group */ let nf_int = nfields_int(nf); - + if illegal_load(vd, vm, nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vlseg(nf_int, vm, vd, load_width_bytes, rs1, EMUL_pow, num_elem) } - diff --git a/arch/inst/V/vle8ff.v.yaml b/arch/inst/V/vle8ff.v.yaml index 58faf7fe84..e53ade80db 100644 --- a/arch/inst/V/vle8ff.v.yaml +++ b/arch/inst/V/vle8ff.v.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,9 +38,8 @@ sail(): | let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; let num_elem = get_num_elem(EMUL_pow, EEW); let nf_int = nfields_int(nf); - + if illegal_load(vd, vm, nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vlsegff(nf_int, vm, vd, load_width_bytes, rs1, EMUL_pow, num_elem) } - diff --git a/arch/inst/V/vlm.v.yaml b/arch/inst/V/vlm.v.yaml index 87096feca8..e7b17a7088 100644 --- a/arch/inst/V/vlm.v.yaml +++ b/arch/inst/V/vlm.v.yaml @@ -22,7 +22,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -33,10 +33,9 @@ sail(): | let vl_val = unsigned(vl); let evl : int = if vl_val % 8 == 0 then vl_val / 8 else vl_val / 8 + 1; /* the effective vector length is evl=ceil(vl/8) */ let num_elem = get_num_elem(EMUL_pow, EEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + assert(evl >= 0); process_vm(vd_or_vs3, rs1, num_elem, evl, op) } - diff --git a/arch/inst/V/vloxei16.v.yaml b/arch/inst/V/vloxei16.v.yaml index 4c080f551b..333150bfcb 100644 --- a/arch/inst/V/vloxei16.v.yaml +++ b/arch/inst/V/vloxei16.v.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -40,9 +40,8 @@ sail(): | let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow; let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); let nf_int = nfields_int(nf); - + if illegal_indexed_load(vd, vm, nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vlxseg(nf_int, vm, vd, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 3) } - diff --git a/arch/inst/V/vloxei32.v.yaml b/arch/inst/V/vloxei32.v.yaml index 61a1581824..42334c5ef7 100644 --- a/arch/inst/V/vloxei32.v.yaml +++ b/arch/inst/V/vloxei32.v.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -40,9 +40,8 @@ sail(): | let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow; let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); let nf_int = nfields_int(nf); - + if illegal_indexed_load(vd, vm, nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vlxseg(nf_int, vm, vd, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 3) } - diff --git a/arch/inst/V/vloxei64.v.yaml b/arch/inst/V/vloxei64.v.yaml index 9e4ed92f70..cc45f490e5 100644 --- a/arch/inst/V/vloxei64.v.yaml +++ b/arch/inst/V/vloxei64.v.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -40,9 +40,8 @@ sail(): | let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow; let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); let nf_int = nfields_int(nf); - + if illegal_indexed_load(vd, vm, nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vlxseg(nf_int, vm, vd, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 3) } - diff --git a/arch/inst/V/vloxei8.v.yaml b/arch/inst/V/vloxei8.v.yaml index c3dfe99ee3..3db6d4ebb3 100644 --- a/arch/inst/V/vloxei8.v.yaml +++ b/arch/inst/V/vloxei8.v.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -40,9 +40,8 @@ sail(): | let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow; let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); let nf_int = nfields_int(nf); - + if illegal_indexed_load(vd, vm, nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vlxseg(nf_int, vm, vd, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 3) } - diff --git a/arch/inst/V/vloxseg2ei16.v.yaml b/arch/inst/V/vloxseg2ei16.v.yaml index 5aeb4b87b6..8c0275846d 100644 --- a/arch/inst/V/vloxseg2ei16.v.yaml +++ b/arch/inst/V/vloxseg2ei16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vloxseg2ei32.v.yaml b/arch/inst/V/vloxseg2ei32.v.yaml index 5300087dfc..8cf8eed091 100644 --- a/arch/inst/V/vloxseg2ei32.v.yaml +++ b/arch/inst/V/vloxseg2ei32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vloxseg2ei64.v.yaml b/arch/inst/V/vloxseg2ei64.v.yaml index 31f4736c58..b441647b1a 100644 --- a/arch/inst/V/vloxseg2ei64.v.yaml +++ b/arch/inst/V/vloxseg2ei64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vloxseg2ei8.v.yaml b/arch/inst/V/vloxseg2ei8.v.yaml index fdbb69faf0..507fe4f0ac 100644 --- a/arch/inst/V/vloxseg2ei8.v.yaml +++ b/arch/inst/V/vloxseg2ei8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vloxseg3ei16.v.yaml b/arch/inst/V/vloxseg3ei16.v.yaml index 7564e9cbbc..674b1aa849 100644 --- a/arch/inst/V/vloxseg3ei16.v.yaml +++ b/arch/inst/V/vloxseg3ei16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vloxseg3ei32.v.yaml b/arch/inst/V/vloxseg3ei32.v.yaml index c6519f8a46..a2a61f851a 100644 --- a/arch/inst/V/vloxseg3ei32.v.yaml +++ b/arch/inst/V/vloxseg3ei32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vloxseg3ei64.v.yaml b/arch/inst/V/vloxseg3ei64.v.yaml index fb86e732dc..61cc36c827 100644 --- a/arch/inst/V/vloxseg3ei64.v.yaml +++ b/arch/inst/V/vloxseg3ei64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vloxseg3ei8.v.yaml b/arch/inst/V/vloxseg3ei8.v.yaml index 5ca294825e..cd4398986c 100644 --- a/arch/inst/V/vloxseg3ei8.v.yaml +++ b/arch/inst/V/vloxseg3ei8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vloxseg4ei16.v.yaml b/arch/inst/V/vloxseg4ei16.v.yaml index 1960fce8d6..a626500873 100644 --- a/arch/inst/V/vloxseg4ei16.v.yaml +++ b/arch/inst/V/vloxseg4ei16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vloxseg4ei32.v.yaml b/arch/inst/V/vloxseg4ei32.v.yaml index d136ebbc13..d97c7fb958 100644 --- a/arch/inst/V/vloxseg4ei32.v.yaml +++ b/arch/inst/V/vloxseg4ei32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vloxseg4ei64.v.yaml b/arch/inst/V/vloxseg4ei64.v.yaml index 296266ecc9..fcfb19b824 100644 --- a/arch/inst/V/vloxseg4ei64.v.yaml +++ b/arch/inst/V/vloxseg4ei64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vloxseg4ei8.v.yaml b/arch/inst/V/vloxseg4ei8.v.yaml index f59d7f753a..d5c0d50545 100644 --- a/arch/inst/V/vloxseg4ei8.v.yaml +++ b/arch/inst/V/vloxseg4ei8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vloxseg5ei16.v.yaml b/arch/inst/V/vloxseg5ei16.v.yaml index 3485edbd21..3512fb8923 100644 --- a/arch/inst/V/vloxseg5ei16.v.yaml +++ b/arch/inst/V/vloxseg5ei16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vloxseg5ei32.v.yaml b/arch/inst/V/vloxseg5ei32.v.yaml index 18afff1639..3068b99f04 100644 --- a/arch/inst/V/vloxseg5ei32.v.yaml +++ b/arch/inst/V/vloxseg5ei32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vloxseg5ei64.v.yaml b/arch/inst/V/vloxseg5ei64.v.yaml index dbd68647c0..4a1e73e519 100644 --- a/arch/inst/V/vloxseg5ei64.v.yaml +++ b/arch/inst/V/vloxseg5ei64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vloxseg5ei8.v.yaml b/arch/inst/V/vloxseg5ei8.v.yaml index c7014818a2..df2afc27a8 100644 --- a/arch/inst/V/vloxseg5ei8.v.yaml +++ b/arch/inst/V/vloxseg5ei8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vloxseg6ei16.v.yaml b/arch/inst/V/vloxseg6ei16.v.yaml index 1657012d33..f7b0fbdcc0 100644 --- a/arch/inst/V/vloxseg6ei16.v.yaml +++ b/arch/inst/V/vloxseg6ei16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vloxseg6ei32.v.yaml b/arch/inst/V/vloxseg6ei32.v.yaml index c6ac3fc24f..a42e7f335e 100644 --- a/arch/inst/V/vloxseg6ei32.v.yaml +++ b/arch/inst/V/vloxseg6ei32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vloxseg6ei64.v.yaml b/arch/inst/V/vloxseg6ei64.v.yaml index 2c0fc16033..24c9a89a15 100644 --- a/arch/inst/V/vloxseg6ei64.v.yaml +++ b/arch/inst/V/vloxseg6ei64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vloxseg6ei8.v.yaml b/arch/inst/V/vloxseg6ei8.v.yaml index 5685617fa1..af5bc5faa0 100644 --- a/arch/inst/V/vloxseg6ei8.v.yaml +++ b/arch/inst/V/vloxseg6ei8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vloxseg7ei16.v.yaml b/arch/inst/V/vloxseg7ei16.v.yaml index d250dad208..9f113daec8 100644 --- a/arch/inst/V/vloxseg7ei16.v.yaml +++ b/arch/inst/V/vloxseg7ei16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vloxseg7ei32.v.yaml b/arch/inst/V/vloxseg7ei32.v.yaml index 5013d140a3..dc92014b14 100644 --- a/arch/inst/V/vloxseg7ei32.v.yaml +++ b/arch/inst/V/vloxseg7ei32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vloxseg7ei64.v.yaml b/arch/inst/V/vloxseg7ei64.v.yaml index 7fe0ced842..0efc0ce4e0 100644 --- a/arch/inst/V/vloxseg7ei64.v.yaml +++ b/arch/inst/V/vloxseg7ei64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vloxseg7ei8.v.yaml b/arch/inst/V/vloxseg7ei8.v.yaml index e1c2ead11f..a87175475d 100644 --- a/arch/inst/V/vloxseg7ei8.v.yaml +++ b/arch/inst/V/vloxseg7ei8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vloxseg8ei16.v.yaml b/arch/inst/V/vloxseg8ei16.v.yaml index df6f5db256..820eb7d13c 100644 --- a/arch/inst/V/vloxseg8ei16.v.yaml +++ b/arch/inst/V/vloxseg8ei16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vloxseg8ei32.v.yaml b/arch/inst/V/vloxseg8ei32.v.yaml index 195c6ea1af..9d733a3e2e 100644 --- a/arch/inst/V/vloxseg8ei32.v.yaml +++ b/arch/inst/V/vloxseg8ei32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vloxseg8ei64.v.yaml b/arch/inst/V/vloxseg8ei64.v.yaml index f2747cd5b9..ff37314bff 100644 --- a/arch/inst/V/vloxseg8ei64.v.yaml +++ b/arch/inst/V/vloxseg8ei64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vloxseg8ei8.v.yaml b/arch/inst/V/vloxseg8ei8.v.yaml index f0d5ec5f7a..689a553540 100644 --- a/arch/inst/V/vloxseg8ei8.v.yaml +++ b/arch/inst/V/vloxseg8ei8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlse16.v.yaml b/arch/inst/V/vlse16.v.yaml index c5a7f1aa73..f82b342534 100644 --- a/arch/inst/V/vlse16.v.yaml +++ b/arch/inst/V/vlse16.v.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -40,9 +40,8 @@ sail(): | let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; let num_elem = get_num_elem(EMUL_pow, EEW); let nf_int = nfields_int(nf); - + if illegal_load(vd, vm, nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vlsseg(nf_int, vm, vd, load_width_bytes, rs1, rs2, EMUL_pow, num_elem) } - diff --git a/arch/inst/V/vlse32.v.yaml b/arch/inst/V/vlse32.v.yaml index 01849349b8..6ba2a8abe7 100644 --- a/arch/inst/V/vlse32.v.yaml +++ b/arch/inst/V/vlse32.v.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -40,9 +40,8 @@ sail(): | let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; let num_elem = get_num_elem(EMUL_pow, EEW); let nf_int = nfields_int(nf); - + if illegal_load(vd, vm, nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vlsseg(nf_int, vm, vd, load_width_bytes, rs1, rs2, EMUL_pow, num_elem) } - diff --git a/arch/inst/V/vlse64.v.yaml b/arch/inst/V/vlse64.v.yaml index d24b18466a..76e1be0642 100644 --- a/arch/inst/V/vlse64.v.yaml +++ b/arch/inst/V/vlse64.v.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -40,9 +40,8 @@ sail(): | let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; let num_elem = get_num_elem(EMUL_pow, EEW); let nf_int = nfields_int(nf); - + if illegal_load(vd, vm, nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vlsseg(nf_int, vm, vd, load_width_bytes, rs1, rs2, EMUL_pow, num_elem) } - diff --git a/arch/inst/V/vlse8.v.yaml b/arch/inst/V/vlse8.v.yaml index bf78965509..ad57806cf2 100644 --- a/arch/inst/V/vlse8.v.yaml +++ b/arch/inst/V/vlse8.v.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -40,9 +40,8 @@ sail(): | let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; let num_elem = get_num_elem(EMUL_pow, EEW); let nf_int = nfields_int(nf); - + if illegal_load(vd, vm, nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vlsseg(nf_int, vm, vd, load_width_bytes, rs1, rs2, EMUL_pow, num_elem) } - diff --git a/arch/inst/V/vlseg2e16.v.yaml b/arch/inst/V/vlseg2e16.v.yaml index a2cab4bab2..fb571d744d 100644 --- a/arch/inst/V/vlseg2e16.v.yaml +++ b/arch/inst/V/vlseg2e16.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg2e16ff.v.yaml b/arch/inst/V/vlseg2e16ff.v.yaml index a4014b189a..0bcfe9e14a 100644 --- a/arch/inst/V/vlseg2e16ff.v.yaml +++ b/arch/inst/V/vlseg2e16ff.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg2e32.v.yaml b/arch/inst/V/vlseg2e32.v.yaml index e5d3ae3c0d..d81a1047ed 100644 --- a/arch/inst/V/vlseg2e32.v.yaml +++ b/arch/inst/V/vlseg2e32.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg2e32ff.v.yaml b/arch/inst/V/vlseg2e32ff.v.yaml index 8158140277..d1a6348b5b 100644 --- a/arch/inst/V/vlseg2e32ff.v.yaml +++ b/arch/inst/V/vlseg2e32ff.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg2e64.v.yaml b/arch/inst/V/vlseg2e64.v.yaml index bfacab1141..2c93a94423 100644 --- a/arch/inst/V/vlseg2e64.v.yaml +++ b/arch/inst/V/vlseg2e64.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg2e64ff.v.yaml b/arch/inst/V/vlseg2e64ff.v.yaml index ed5c70bbe7..ca5ad1b9de 100644 --- a/arch/inst/V/vlseg2e64ff.v.yaml +++ b/arch/inst/V/vlseg2e64ff.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg2e8.v.yaml b/arch/inst/V/vlseg2e8.v.yaml index 734ecbca96..9d80b185b3 100644 --- a/arch/inst/V/vlseg2e8.v.yaml +++ b/arch/inst/V/vlseg2e8.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg2e8ff.v.yaml b/arch/inst/V/vlseg2e8ff.v.yaml index 848b4e8f7b..427db8eae2 100644 --- a/arch/inst/V/vlseg2e8ff.v.yaml +++ b/arch/inst/V/vlseg2e8ff.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg3e16.v.yaml b/arch/inst/V/vlseg3e16.v.yaml index 0a8c6870ad..f5d7e55456 100644 --- a/arch/inst/V/vlseg3e16.v.yaml +++ b/arch/inst/V/vlseg3e16.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg3e16ff.v.yaml b/arch/inst/V/vlseg3e16ff.v.yaml index 44472d70ec..76d8d97c4e 100644 --- a/arch/inst/V/vlseg3e16ff.v.yaml +++ b/arch/inst/V/vlseg3e16ff.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg3e32.v.yaml b/arch/inst/V/vlseg3e32.v.yaml index 080f21018f..d982464fe0 100644 --- a/arch/inst/V/vlseg3e32.v.yaml +++ b/arch/inst/V/vlseg3e32.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg3e32ff.v.yaml b/arch/inst/V/vlseg3e32ff.v.yaml index 08bc7cb9d4..1634338f12 100644 --- a/arch/inst/V/vlseg3e32ff.v.yaml +++ b/arch/inst/V/vlseg3e32ff.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg3e64.v.yaml b/arch/inst/V/vlseg3e64.v.yaml index a73c8cab70..4de2fb503d 100644 --- a/arch/inst/V/vlseg3e64.v.yaml +++ b/arch/inst/V/vlseg3e64.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg3e64ff.v.yaml b/arch/inst/V/vlseg3e64ff.v.yaml index f6a23acb46..0f73b786a8 100644 --- a/arch/inst/V/vlseg3e64ff.v.yaml +++ b/arch/inst/V/vlseg3e64ff.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg3e8.v.yaml b/arch/inst/V/vlseg3e8.v.yaml index 4679966e07..f858ec9c74 100644 --- a/arch/inst/V/vlseg3e8.v.yaml +++ b/arch/inst/V/vlseg3e8.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg3e8ff.v.yaml b/arch/inst/V/vlseg3e8ff.v.yaml index 0474c4bb96..aeed7424b0 100644 --- a/arch/inst/V/vlseg3e8ff.v.yaml +++ b/arch/inst/V/vlseg3e8ff.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg4e16.v.yaml b/arch/inst/V/vlseg4e16.v.yaml index ad493e6894..e017e09839 100644 --- a/arch/inst/V/vlseg4e16.v.yaml +++ b/arch/inst/V/vlseg4e16.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg4e16ff.v.yaml b/arch/inst/V/vlseg4e16ff.v.yaml index 31acfb5a8f..3144cc7771 100644 --- a/arch/inst/V/vlseg4e16ff.v.yaml +++ b/arch/inst/V/vlseg4e16ff.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg4e32.v.yaml b/arch/inst/V/vlseg4e32.v.yaml index ac08fa0603..eaf5e45e94 100644 --- a/arch/inst/V/vlseg4e32.v.yaml +++ b/arch/inst/V/vlseg4e32.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg4e32ff.v.yaml b/arch/inst/V/vlseg4e32ff.v.yaml index 03a02f42ed..fc92eeb66c 100644 --- a/arch/inst/V/vlseg4e32ff.v.yaml +++ b/arch/inst/V/vlseg4e32ff.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg4e64.v.yaml b/arch/inst/V/vlseg4e64.v.yaml index 8915697f5f..e7630b5e65 100644 --- a/arch/inst/V/vlseg4e64.v.yaml +++ b/arch/inst/V/vlseg4e64.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg4e64ff.v.yaml b/arch/inst/V/vlseg4e64ff.v.yaml index 8190586ee7..b64e45fa2a 100644 --- a/arch/inst/V/vlseg4e64ff.v.yaml +++ b/arch/inst/V/vlseg4e64ff.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg4e8.v.yaml b/arch/inst/V/vlseg4e8.v.yaml index 91c8f4b8aa..471bcc07d0 100644 --- a/arch/inst/V/vlseg4e8.v.yaml +++ b/arch/inst/V/vlseg4e8.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg4e8ff.v.yaml b/arch/inst/V/vlseg4e8ff.v.yaml index df6e6831e9..67165fa3de 100644 --- a/arch/inst/V/vlseg4e8ff.v.yaml +++ b/arch/inst/V/vlseg4e8ff.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg5e16.v.yaml b/arch/inst/V/vlseg5e16.v.yaml index 30f713959a..9ba626b4a0 100644 --- a/arch/inst/V/vlseg5e16.v.yaml +++ b/arch/inst/V/vlseg5e16.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg5e16ff.v.yaml b/arch/inst/V/vlseg5e16ff.v.yaml index 15c3a245a9..2f1eaa609e 100644 --- a/arch/inst/V/vlseg5e16ff.v.yaml +++ b/arch/inst/V/vlseg5e16ff.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg5e32.v.yaml b/arch/inst/V/vlseg5e32.v.yaml index 13966d00bd..eb45144de7 100644 --- a/arch/inst/V/vlseg5e32.v.yaml +++ b/arch/inst/V/vlseg5e32.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg5e32ff.v.yaml b/arch/inst/V/vlseg5e32ff.v.yaml index 5bae358761..e0cc52c874 100644 --- a/arch/inst/V/vlseg5e32ff.v.yaml +++ b/arch/inst/V/vlseg5e32ff.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg5e64.v.yaml b/arch/inst/V/vlseg5e64.v.yaml index d87028734a..e989cc4a4e 100644 --- a/arch/inst/V/vlseg5e64.v.yaml +++ b/arch/inst/V/vlseg5e64.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg5e64ff.v.yaml b/arch/inst/V/vlseg5e64ff.v.yaml index 7be6eb1776..06440b7923 100644 --- a/arch/inst/V/vlseg5e64ff.v.yaml +++ b/arch/inst/V/vlseg5e64ff.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg5e8.v.yaml b/arch/inst/V/vlseg5e8.v.yaml index b0ed00bd08..e853590c04 100644 --- a/arch/inst/V/vlseg5e8.v.yaml +++ b/arch/inst/V/vlseg5e8.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg5e8ff.v.yaml b/arch/inst/V/vlseg5e8ff.v.yaml index 80e2df81a1..e77ecaefe5 100644 --- a/arch/inst/V/vlseg5e8ff.v.yaml +++ b/arch/inst/V/vlseg5e8ff.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg6e16.v.yaml b/arch/inst/V/vlseg6e16.v.yaml index 0c051a9998..8f546c7db2 100644 --- a/arch/inst/V/vlseg6e16.v.yaml +++ b/arch/inst/V/vlseg6e16.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg6e16ff.v.yaml b/arch/inst/V/vlseg6e16ff.v.yaml index 54cc9196b6..352ed94898 100644 --- a/arch/inst/V/vlseg6e16ff.v.yaml +++ b/arch/inst/V/vlseg6e16ff.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg6e32.v.yaml b/arch/inst/V/vlseg6e32.v.yaml index 888a5c837c..3ec853fd6c 100644 --- a/arch/inst/V/vlseg6e32.v.yaml +++ b/arch/inst/V/vlseg6e32.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg6e32ff.v.yaml b/arch/inst/V/vlseg6e32ff.v.yaml index a0637baed7..e6ee665530 100644 --- a/arch/inst/V/vlseg6e32ff.v.yaml +++ b/arch/inst/V/vlseg6e32ff.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg6e64.v.yaml b/arch/inst/V/vlseg6e64.v.yaml index 602d9974a8..d281c07ea9 100644 --- a/arch/inst/V/vlseg6e64.v.yaml +++ b/arch/inst/V/vlseg6e64.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg6e64ff.v.yaml b/arch/inst/V/vlseg6e64ff.v.yaml index f2629c19e1..64bccae0b8 100644 --- a/arch/inst/V/vlseg6e64ff.v.yaml +++ b/arch/inst/V/vlseg6e64ff.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg6e8.v.yaml b/arch/inst/V/vlseg6e8.v.yaml index a0180b9718..6205f7654f 100644 --- a/arch/inst/V/vlseg6e8.v.yaml +++ b/arch/inst/V/vlseg6e8.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg6e8ff.v.yaml b/arch/inst/V/vlseg6e8ff.v.yaml index b56808326f..96772b71f8 100644 --- a/arch/inst/V/vlseg6e8ff.v.yaml +++ b/arch/inst/V/vlseg6e8ff.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg7e16.v.yaml b/arch/inst/V/vlseg7e16.v.yaml index 5851806e6d..80608625b1 100644 --- a/arch/inst/V/vlseg7e16.v.yaml +++ b/arch/inst/V/vlseg7e16.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg7e16ff.v.yaml b/arch/inst/V/vlseg7e16ff.v.yaml index 20954ba6cb..ad5a0c8e7b 100644 --- a/arch/inst/V/vlseg7e16ff.v.yaml +++ b/arch/inst/V/vlseg7e16ff.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg7e32.v.yaml b/arch/inst/V/vlseg7e32.v.yaml index 1cf2c33733..c03e22bd00 100644 --- a/arch/inst/V/vlseg7e32.v.yaml +++ b/arch/inst/V/vlseg7e32.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg7e32ff.v.yaml b/arch/inst/V/vlseg7e32ff.v.yaml index e395b063e3..5022199140 100644 --- a/arch/inst/V/vlseg7e32ff.v.yaml +++ b/arch/inst/V/vlseg7e32ff.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg7e64.v.yaml b/arch/inst/V/vlseg7e64.v.yaml index 05e1628301..9198968c59 100644 --- a/arch/inst/V/vlseg7e64.v.yaml +++ b/arch/inst/V/vlseg7e64.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg7e64ff.v.yaml b/arch/inst/V/vlseg7e64ff.v.yaml index 565aacb909..f19ae2b3d7 100644 --- a/arch/inst/V/vlseg7e64ff.v.yaml +++ b/arch/inst/V/vlseg7e64ff.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg7e8.v.yaml b/arch/inst/V/vlseg7e8.v.yaml index 21de27f840..8d5b005220 100644 --- a/arch/inst/V/vlseg7e8.v.yaml +++ b/arch/inst/V/vlseg7e8.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg7e8ff.v.yaml b/arch/inst/V/vlseg7e8ff.v.yaml index 8eec8031ce..6b70df5dde 100644 --- a/arch/inst/V/vlseg7e8ff.v.yaml +++ b/arch/inst/V/vlseg7e8ff.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg8e16.v.yaml b/arch/inst/V/vlseg8e16.v.yaml index ec175bb376..123b19b579 100644 --- a/arch/inst/V/vlseg8e16.v.yaml +++ b/arch/inst/V/vlseg8e16.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg8e16ff.v.yaml b/arch/inst/V/vlseg8e16ff.v.yaml index 7a99d24021..638b68a82e 100644 --- a/arch/inst/V/vlseg8e16ff.v.yaml +++ b/arch/inst/V/vlseg8e16ff.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg8e32.v.yaml b/arch/inst/V/vlseg8e32.v.yaml index 79372ae84c..39b89cdad8 100644 --- a/arch/inst/V/vlseg8e32.v.yaml +++ b/arch/inst/V/vlseg8e32.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg8e32ff.v.yaml b/arch/inst/V/vlseg8e32ff.v.yaml index 9bd0906b50..a2ab52d771 100644 --- a/arch/inst/V/vlseg8e32ff.v.yaml +++ b/arch/inst/V/vlseg8e32ff.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg8e64.v.yaml b/arch/inst/V/vlseg8e64.v.yaml index ed5befa23b..f7952833be 100644 --- a/arch/inst/V/vlseg8e64.v.yaml +++ b/arch/inst/V/vlseg8e64.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg8e64ff.v.yaml b/arch/inst/V/vlseg8e64ff.v.yaml index af4e15d51b..28c0e9a735 100644 --- a/arch/inst/V/vlseg8e64ff.v.yaml +++ b/arch/inst/V/vlseg8e64ff.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg8e8.v.yaml b/arch/inst/V/vlseg8e8.v.yaml index e1937c9acf..7b1c864aeb 100644 --- a/arch/inst/V/vlseg8e8.v.yaml +++ b/arch/inst/V/vlseg8e8.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlseg8e8ff.v.yaml b/arch/inst/V/vlseg8e8ff.v.yaml index cb825c00e4..503786f11d 100644 --- a/arch/inst/V/vlseg8e8ff.v.yaml +++ b/arch/inst/V/vlseg8e8ff.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlsseg2e16.v.yaml b/arch/inst/V/vlsseg2e16.v.yaml index 691eb363b8..a8700b96d2 100644 --- a/arch/inst/V/vlsseg2e16.v.yaml +++ b/arch/inst/V/vlsseg2e16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlsseg2e32.v.yaml b/arch/inst/V/vlsseg2e32.v.yaml index 8f89e78878..06df364b82 100644 --- a/arch/inst/V/vlsseg2e32.v.yaml +++ b/arch/inst/V/vlsseg2e32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlsseg2e64.v.yaml b/arch/inst/V/vlsseg2e64.v.yaml index fdce278022..ad42e35e3b 100644 --- a/arch/inst/V/vlsseg2e64.v.yaml +++ b/arch/inst/V/vlsseg2e64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlsseg2e8.v.yaml b/arch/inst/V/vlsseg2e8.v.yaml index 7edea0e2aa..f5d11dfacf 100644 --- a/arch/inst/V/vlsseg2e8.v.yaml +++ b/arch/inst/V/vlsseg2e8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlsseg3e16.v.yaml b/arch/inst/V/vlsseg3e16.v.yaml index 7f381ef3be..e56df9143d 100644 --- a/arch/inst/V/vlsseg3e16.v.yaml +++ b/arch/inst/V/vlsseg3e16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlsseg3e32.v.yaml b/arch/inst/V/vlsseg3e32.v.yaml index ecb4348063..836a5ccccd 100644 --- a/arch/inst/V/vlsseg3e32.v.yaml +++ b/arch/inst/V/vlsseg3e32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlsseg3e64.v.yaml b/arch/inst/V/vlsseg3e64.v.yaml index 94d3ad2f3c..0fbc2ece18 100644 --- a/arch/inst/V/vlsseg3e64.v.yaml +++ b/arch/inst/V/vlsseg3e64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlsseg3e8.v.yaml b/arch/inst/V/vlsseg3e8.v.yaml index e9569dba2a..d9f2702970 100644 --- a/arch/inst/V/vlsseg3e8.v.yaml +++ b/arch/inst/V/vlsseg3e8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlsseg4e16.v.yaml b/arch/inst/V/vlsseg4e16.v.yaml index 3bb9ee4a79..2946801a27 100644 --- a/arch/inst/V/vlsseg4e16.v.yaml +++ b/arch/inst/V/vlsseg4e16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlsseg4e32.v.yaml b/arch/inst/V/vlsseg4e32.v.yaml index e63f5c9e2c..f9e9adb8e3 100644 --- a/arch/inst/V/vlsseg4e32.v.yaml +++ b/arch/inst/V/vlsseg4e32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlsseg4e64.v.yaml b/arch/inst/V/vlsseg4e64.v.yaml index 66f4af48aa..7091310b91 100644 --- a/arch/inst/V/vlsseg4e64.v.yaml +++ b/arch/inst/V/vlsseg4e64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlsseg4e8.v.yaml b/arch/inst/V/vlsseg4e8.v.yaml index 6e213656e1..e7755782f0 100644 --- a/arch/inst/V/vlsseg4e8.v.yaml +++ b/arch/inst/V/vlsseg4e8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlsseg5e16.v.yaml b/arch/inst/V/vlsseg5e16.v.yaml index 9276507db4..d96600999d 100644 --- a/arch/inst/V/vlsseg5e16.v.yaml +++ b/arch/inst/V/vlsseg5e16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlsseg5e32.v.yaml b/arch/inst/V/vlsseg5e32.v.yaml index 2b41e5682f..36dcfda260 100644 --- a/arch/inst/V/vlsseg5e32.v.yaml +++ b/arch/inst/V/vlsseg5e32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlsseg5e64.v.yaml b/arch/inst/V/vlsseg5e64.v.yaml index de46f05e90..43ef731d9c 100644 --- a/arch/inst/V/vlsseg5e64.v.yaml +++ b/arch/inst/V/vlsseg5e64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlsseg5e8.v.yaml b/arch/inst/V/vlsseg5e8.v.yaml index c69373c6bd..512237dfc5 100644 --- a/arch/inst/V/vlsseg5e8.v.yaml +++ b/arch/inst/V/vlsseg5e8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlsseg6e16.v.yaml b/arch/inst/V/vlsseg6e16.v.yaml index f3773952c1..fda481b602 100644 --- a/arch/inst/V/vlsseg6e16.v.yaml +++ b/arch/inst/V/vlsseg6e16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlsseg6e32.v.yaml b/arch/inst/V/vlsseg6e32.v.yaml index b610b0ff5c..3e4927eb41 100644 --- a/arch/inst/V/vlsseg6e32.v.yaml +++ b/arch/inst/V/vlsseg6e32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlsseg6e64.v.yaml b/arch/inst/V/vlsseg6e64.v.yaml index 2db70cc53a..379f481bb4 100644 --- a/arch/inst/V/vlsseg6e64.v.yaml +++ b/arch/inst/V/vlsseg6e64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlsseg6e8.v.yaml b/arch/inst/V/vlsseg6e8.v.yaml index 0b849f331b..16080240a8 100644 --- a/arch/inst/V/vlsseg6e8.v.yaml +++ b/arch/inst/V/vlsseg6e8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlsseg7e16.v.yaml b/arch/inst/V/vlsseg7e16.v.yaml index ced663fe59..464b1013d0 100644 --- a/arch/inst/V/vlsseg7e16.v.yaml +++ b/arch/inst/V/vlsseg7e16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlsseg7e32.v.yaml b/arch/inst/V/vlsseg7e32.v.yaml index 3b8367b12e..990fcab164 100644 --- a/arch/inst/V/vlsseg7e32.v.yaml +++ b/arch/inst/V/vlsseg7e32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlsseg7e64.v.yaml b/arch/inst/V/vlsseg7e64.v.yaml index 658ed6a205..7dc4459c30 100644 --- a/arch/inst/V/vlsseg7e64.v.yaml +++ b/arch/inst/V/vlsseg7e64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlsseg7e8.v.yaml b/arch/inst/V/vlsseg7e8.v.yaml index 1884be49c8..de905eaf9c 100644 --- a/arch/inst/V/vlsseg7e8.v.yaml +++ b/arch/inst/V/vlsseg7e8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlsseg8e16.v.yaml b/arch/inst/V/vlsseg8e16.v.yaml index 3f9c32777b..d563b23877 100644 --- a/arch/inst/V/vlsseg8e16.v.yaml +++ b/arch/inst/V/vlsseg8e16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlsseg8e32.v.yaml b/arch/inst/V/vlsseg8e32.v.yaml index 895b199382..a37c82d999 100644 --- a/arch/inst/V/vlsseg8e32.v.yaml +++ b/arch/inst/V/vlsseg8e32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlsseg8e64.v.yaml b/arch/inst/V/vlsseg8e64.v.yaml index 74fbb37b16..c9a6e417cd 100644 --- a/arch/inst/V/vlsseg8e64.v.yaml +++ b/arch/inst/V/vlsseg8e64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vlsseg8e8.v.yaml b/arch/inst/V/vlsseg8e8.v.yaml index a04abb0a96..71d8ed23da 100644 --- a/arch/inst/V/vlsseg8e8.v.yaml +++ b/arch/inst/V/vlsseg8e8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vluxei16.v.yaml b/arch/inst/V/vluxei16.v.yaml index 2d4405c37b..69010d3ea8 100644 --- a/arch/inst/V/vluxei16.v.yaml +++ b/arch/inst/V/vluxei16.v.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -40,9 +40,8 @@ sail(): | let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow; let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); let nf_int = nfields_int(nf); - + if illegal_indexed_load(vd, vm, nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vlxseg(nf_int, vm, vd, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 1) } - diff --git a/arch/inst/V/vluxei32.v.yaml b/arch/inst/V/vluxei32.v.yaml index 617abc17cf..eee624fabc 100644 --- a/arch/inst/V/vluxei32.v.yaml +++ b/arch/inst/V/vluxei32.v.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -40,9 +40,8 @@ sail(): | let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow; let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); let nf_int = nfields_int(nf); - + if illegal_indexed_load(vd, vm, nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vlxseg(nf_int, vm, vd, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 1) } - diff --git a/arch/inst/V/vluxei64.v.yaml b/arch/inst/V/vluxei64.v.yaml index 6889bc85c4..3429c2c320 100644 --- a/arch/inst/V/vluxei64.v.yaml +++ b/arch/inst/V/vluxei64.v.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -40,9 +40,8 @@ sail(): | let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow; let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); let nf_int = nfields_int(nf); - + if illegal_indexed_load(vd, vm, nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vlxseg(nf_int, vm, vd, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 1) } - diff --git a/arch/inst/V/vluxei8.v.yaml b/arch/inst/V/vluxei8.v.yaml index 7d9422a608..64cffe056a 100644 --- a/arch/inst/V/vluxei8.v.yaml +++ b/arch/inst/V/vluxei8.v.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -40,9 +40,8 @@ sail(): | let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow; let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); let nf_int = nfields_int(nf); - + if illegal_indexed_load(vd, vm, nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vlxseg(nf_int, vm, vd, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 1) } - diff --git a/arch/inst/V/vluxseg2ei16.v.yaml b/arch/inst/V/vluxseg2ei16.v.yaml index 0cedd4919b..fa80ccdc7b 100644 --- a/arch/inst/V/vluxseg2ei16.v.yaml +++ b/arch/inst/V/vluxseg2ei16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vluxseg2ei32.v.yaml b/arch/inst/V/vluxseg2ei32.v.yaml index 248a6014d9..9d5656f6eb 100644 --- a/arch/inst/V/vluxseg2ei32.v.yaml +++ b/arch/inst/V/vluxseg2ei32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vluxseg2ei64.v.yaml b/arch/inst/V/vluxseg2ei64.v.yaml index aa44de53fa..38996c6230 100644 --- a/arch/inst/V/vluxseg2ei64.v.yaml +++ b/arch/inst/V/vluxseg2ei64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vluxseg2ei8.v.yaml b/arch/inst/V/vluxseg2ei8.v.yaml index 47d086f240..6c714e5709 100644 --- a/arch/inst/V/vluxseg2ei8.v.yaml +++ b/arch/inst/V/vluxseg2ei8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vluxseg3ei16.v.yaml b/arch/inst/V/vluxseg3ei16.v.yaml index 63ead2f0b4..5d4ba029c3 100644 --- a/arch/inst/V/vluxseg3ei16.v.yaml +++ b/arch/inst/V/vluxseg3ei16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vluxseg3ei32.v.yaml b/arch/inst/V/vluxseg3ei32.v.yaml index 093273266b..6a4ecd4985 100644 --- a/arch/inst/V/vluxseg3ei32.v.yaml +++ b/arch/inst/V/vluxseg3ei32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vluxseg3ei64.v.yaml b/arch/inst/V/vluxseg3ei64.v.yaml index b5b036c663..dad4d516e0 100644 --- a/arch/inst/V/vluxseg3ei64.v.yaml +++ b/arch/inst/V/vluxseg3ei64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vluxseg3ei8.v.yaml b/arch/inst/V/vluxseg3ei8.v.yaml index d12058ae95..e162ada5ca 100644 --- a/arch/inst/V/vluxseg3ei8.v.yaml +++ b/arch/inst/V/vluxseg3ei8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vluxseg4ei16.v.yaml b/arch/inst/V/vluxseg4ei16.v.yaml index 868d2bbe2d..e6e85799fa 100644 --- a/arch/inst/V/vluxseg4ei16.v.yaml +++ b/arch/inst/V/vluxseg4ei16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vluxseg4ei32.v.yaml b/arch/inst/V/vluxseg4ei32.v.yaml index ebcbe075b3..16bfdda268 100644 --- a/arch/inst/V/vluxseg4ei32.v.yaml +++ b/arch/inst/V/vluxseg4ei32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vluxseg4ei64.v.yaml b/arch/inst/V/vluxseg4ei64.v.yaml index 91c3d60c5a..65de58e161 100644 --- a/arch/inst/V/vluxseg4ei64.v.yaml +++ b/arch/inst/V/vluxseg4ei64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vluxseg4ei8.v.yaml b/arch/inst/V/vluxseg4ei8.v.yaml index fe4afd3e9a..d0ab239540 100644 --- a/arch/inst/V/vluxseg4ei8.v.yaml +++ b/arch/inst/V/vluxseg4ei8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vluxseg5ei16.v.yaml b/arch/inst/V/vluxseg5ei16.v.yaml index 4a8948b02c..cb8c43f71a 100644 --- a/arch/inst/V/vluxseg5ei16.v.yaml +++ b/arch/inst/V/vluxseg5ei16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vluxseg5ei32.v.yaml b/arch/inst/V/vluxseg5ei32.v.yaml index c061b297ab..3bf89d6aff 100644 --- a/arch/inst/V/vluxseg5ei32.v.yaml +++ b/arch/inst/V/vluxseg5ei32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vluxseg5ei64.v.yaml b/arch/inst/V/vluxseg5ei64.v.yaml index 6cc02268ab..ddb29d4bbe 100644 --- a/arch/inst/V/vluxseg5ei64.v.yaml +++ b/arch/inst/V/vluxseg5ei64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vluxseg5ei8.v.yaml b/arch/inst/V/vluxseg5ei8.v.yaml index 29c178c477..01870a1c51 100644 --- a/arch/inst/V/vluxseg5ei8.v.yaml +++ b/arch/inst/V/vluxseg5ei8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vluxseg6ei16.v.yaml b/arch/inst/V/vluxseg6ei16.v.yaml index 4d652a37fe..3326c77ff7 100644 --- a/arch/inst/V/vluxseg6ei16.v.yaml +++ b/arch/inst/V/vluxseg6ei16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vluxseg6ei32.v.yaml b/arch/inst/V/vluxseg6ei32.v.yaml index 84ba75c8d5..596227162b 100644 --- a/arch/inst/V/vluxseg6ei32.v.yaml +++ b/arch/inst/V/vluxseg6ei32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vluxseg6ei64.v.yaml b/arch/inst/V/vluxseg6ei64.v.yaml index 69446e2146..ef5b21469f 100644 --- a/arch/inst/V/vluxseg6ei64.v.yaml +++ b/arch/inst/V/vluxseg6ei64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vluxseg6ei8.v.yaml b/arch/inst/V/vluxseg6ei8.v.yaml index 599231bca4..93db5170dc 100644 --- a/arch/inst/V/vluxseg6ei8.v.yaml +++ b/arch/inst/V/vluxseg6ei8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vluxseg7ei16.v.yaml b/arch/inst/V/vluxseg7ei16.v.yaml index 8bc62c8fa9..0d0d1223bf 100644 --- a/arch/inst/V/vluxseg7ei16.v.yaml +++ b/arch/inst/V/vluxseg7ei16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vluxseg7ei32.v.yaml b/arch/inst/V/vluxseg7ei32.v.yaml index 39b46639d3..09661bd0da 100644 --- a/arch/inst/V/vluxseg7ei32.v.yaml +++ b/arch/inst/V/vluxseg7ei32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vluxseg7ei64.v.yaml b/arch/inst/V/vluxseg7ei64.v.yaml index 83c4e97dd2..da5490090f 100644 --- a/arch/inst/V/vluxseg7ei64.v.yaml +++ b/arch/inst/V/vluxseg7ei64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vluxseg7ei8.v.yaml b/arch/inst/V/vluxseg7ei8.v.yaml index aebfab4e8c..9bf03adc45 100644 --- a/arch/inst/V/vluxseg7ei8.v.yaml +++ b/arch/inst/V/vluxseg7ei8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vluxseg8ei16.v.yaml b/arch/inst/V/vluxseg8ei16.v.yaml index 6440102881..b64e783f4f 100644 --- a/arch/inst/V/vluxseg8ei16.v.yaml +++ b/arch/inst/V/vluxseg8ei16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vluxseg8ei32.v.yaml b/arch/inst/V/vluxseg8ei32.v.yaml index 68b490bee0..5f53f3b233 100644 --- a/arch/inst/V/vluxseg8ei32.v.yaml +++ b/arch/inst/V/vluxseg8ei32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vluxseg8ei64.v.yaml b/arch/inst/V/vluxseg8ei64.v.yaml index d1b1bc7383..6a5eaffaad 100644 --- a/arch/inst/V/vluxseg8ei64.v.yaml +++ b/arch/inst/V/vluxseg8ei64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vluxseg8ei8.v.yaml b/arch/inst/V/vluxseg8ei8.v.yaml index 2cce23a759..0775f15d8f 100644 --- a/arch/inst/V/vluxseg8ei8.v.yaml +++ b/arch/inst/V/vluxseg8ei8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vmacc.vv.yaml b/arch/inst/V/vmacc.vv.yaml index 2f962c1db6..2cfaba7c9e 100644 --- a/arch/inst/V/vmacc.vv.yaml +++ b/arch/inst/V/vmacc.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -60,9 +60,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmacc.vx.yaml b/arch/inst/V/vmacc.vx.yaml index 6ecc901da7..eae6032500 100644 --- a/arch/inst/V/vmacc.vx.yaml +++ b/arch/inst/V/vmacc.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -60,9 +60,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmadc.vi.yaml b/arch/inst/V/vmadc.vi.yaml index 27249cc474..06f7081b9f 100644 --- a/arch/inst/V/vmadc.vi.yaml +++ b/arch/inst/V/vmadc.vi.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -33,20 +33,20 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let imm_val : bits('m) = sign_extend(simm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_carry(num_elem, SEW, LMUL_pow, vd_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -55,9 +55,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmadc.vim.yaml b/arch/inst/V/vmadc.vim.yaml index ffb08eb00f..f7add6ff82 100644 --- a/arch/inst/V/vmadc.vim.yaml +++ b/arch/inst/V/vmadc.vim.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -33,21 +33,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask_carry(num_elem, 0b0, 0b00000); let imm_val : bits('m) = sign_extend(simm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_carry(num_elem, SEW, LMUL_pow, vd_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -56,9 +56,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmadc.vv.yaml b/arch/inst/V/vmadc.vv.yaml index f2dfe86147..18f0baafd0 100644 --- a/arch/inst/V/vmadc.vv.yaml +++ b/arch/inst/V/vmadc.vv.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -33,20 +33,20 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_carry(num_elem, SEW, LMUL_pow, vd_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -56,9 +56,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmadc.vvm.yaml b/arch/inst/V/vmadc.vvm.yaml index 5ad1bc2fe1..a367b3624c 100644 --- a/arch/inst/V/vmadc.vvm.yaml +++ b/arch/inst/V/vmadc.vvm.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -33,21 +33,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask_carry(num_elem, 0b0, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_carry(num_elem, SEW, LMUL_pow, vd_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -57,9 +57,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmadc.vx.yaml b/arch/inst/V/vmadc.vx.yaml index 06689d0e77..e216e96b54 100644 --- a/arch/inst/V/vmadc.vx.yaml +++ b/arch/inst/V/vmadc.vx.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -33,20 +33,20 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_carry(num_elem, SEW, LMUL_pow, vd_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -56,9 +56,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmadc.vxm.yaml b/arch/inst/V/vmadc.vxm.yaml index 4f9f699ca0..42be4e178e 100644 --- a/arch/inst/V/vmadc.vxm.yaml +++ b/arch/inst/V/vmadc.vxm.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -33,21 +33,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask_carry(num_elem, 0b0, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_carry(num_elem, SEW, LMUL_pow, vd_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -57,9 +57,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmadd.vv.yaml b/arch/inst/V/vmadd.vv.yaml index fda328eb37..d126ca055c 100644 --- a/arch/inst/V/vmadd.vv.yaml +++ b/arch/inst/V/vmadd.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -60,9 +60,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmadd.vx.yaml b/arch/inst/V/vmadd.vx.yaml index 5600d21f16..605641cd1f 100644 --- a/arch/inst/V/vmadd.vx.yaml +++ b/arch/inst/V/vmadd.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -60,9 +60,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmand.mm.yaml b/arch/inst/V/vmand.mm.yaml index 0897e5ad0f..71b3d684bf 100644 --- a/arch/inst/V/vmand.mm.yaml +++ b/arch/inst/V/vmand.mm.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -33,20 +33,20 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = unsigned(vlenb) * 8; - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vs1_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs1); let vs2_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_carry(num_elem, SEW, 0, vd_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -61,9 +61,8 @@ sail(): | } } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmandn.mm.yaml b/arch/inst/V/vmandn.mm.yaml index a5dd1ba9ad..78e38995c0 100644 --- a/arch/inst/V/vmandn.mm.yaml +++ b/arch/inst/V/vmandn.mm.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vmax.vv.yaml b/arch/inst/V/vmax.vv.yaml index ed446c2ae9..c3047be500 100644 --- a/arch/inst/V/vmax.vv.yaml +++ b/arch/inst/V/vmax.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,21 +37,21 @@ sail(): | let LMUL_pow = get_lmul_pow(); let VLEN_pow = get_vlen_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -120,9 +120,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmax.vx.yaml b/arch/inst/V/vmax.vx.yaml index 796bf3f121..6766e04533 100644 --- a/arch/inst/V/vmax.vx.yaml +++ b/arch/inst/V/vmax.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -103,9 +103,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmaxu.vv.yaml b/arch/inst/V/vmaxu.vv.yaml index 1e3b423da5..986712f510 100644 --- a/arch/inst/V/vmaxu.vv.yaml +++ b/arch/inst/V/vmaxu.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,21 +37,21 @@ sail(): | let LMUL_pow = get_lmul_pow(); let VLEN_pow = get_vlen_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -120,9 +120,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmaxu.vx.yaml b/arch/inst/V/vmaxu.vx.yaml index 86af7591ae..b5c1649621 100644 --- a/arch/inst/V/vmaxu.vx.yaml +++ b/arch/inst/V/vmaxu.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -103,9 +103,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmerge.vim.yaml b/arch/inst/V/vmerge.vim.yaml index a190535f31..80a4b3b5f6 100644 --- a/arch/inst/V/vmerge.vim.yaml +++ b/arch/inst/V/vmerge.vim.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,18 +36,18 @@ sail(): | let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); /* max(VLMAX,VLEN/SEW)) */ let real_num_elem = if LMUL_pow >= 0 then num_elem else num_elem / (0 - LMUL_pow); /* VLMAX */ - + if illegal_vd_masked(vd) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, 0b00000); let imm_val : bits('m) = sign_extend(simm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; - + let tail_ag : agtype = get_vtype_vta(); foreach (i from 0 to (num_elem - 1)) { if i < start_element then { @@ -62,9 +62,8 @@ sail(): | result[i] = if vm_val[i] then imm_val else vs2_val[i] } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmerge.vvm.yaml b/arch/inst/V/vmerge.vvm.yaml index 12977cc004..ad5f77d978 100644 --- a/arch/inst/V/vmerge.vvm.yaml +++ b/arch/inst/V/vmerge.vvm.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,18 +36,18 @@ sail(): | let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); /* max(VLMAX,VLEN/SEW)) */ let real_num_elem = if LMUL_pow >= 0 then num_elem else num_elem / (0 - LMUL_pow); /* VLMAX */ - + if illegal_vd_masked(vd) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; - + let tail_ag : agtype = get_vtype_vta(); foreach (i from 0 to (num_elem - 1)) { if i < start_element then { @@ -62,9 +62,8 @@ sail(): | result[i] = if vm_val[i] then vs1_val[i] else vs2_val[i] } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmerge.vxm.yaml b/arch/inst/V/vmerge.vxm.yaml index d40cf5031f..1dbddcabab 100644 --- a/arch/inst/V/vmerge.vxm.yaml +++ b/arch/inst/V/vmerge.vxm.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,18 +36,18 @@ sail(): | let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); /* max(VLMAX,VLEN/SEW)) */ let real_num_elem = if LMUL_pow >= 0 then num_elem else num_elem / (0 - LMUL_pow); /* VLMAX */ - + if illegal_vd_masked(vd) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; - + let tail_ag : agtype = get_vtype_vta(); foreach (i from 0 to (num_elem - 1)) { if i < start_element then { @@ -62,9 +62,8 @@ sail(): | result[i] = if vm_val[i] then rs1_val else vs2_val[i] } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmfeq.vf.yaml b/arch/inst/V/vmfeq.vf.yaml index cc637854e0..3e9412057c 100644 --- a/arch/inst/V/vmfeq.vf.yaml +++ b/arch/inst/V/vmfeq.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_vd_unmasked(SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -65,9 +65,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmfeq.vv.yaml b/arch/inst/V/vmfeq.vv.yaml index 131d35caa0..2663d6d031 100644 --- a/arch/inst/V/vmfeq.vv.yaml +++ b/arch/inst/V/vmfeq.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_vd_unmasked(SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -63,9 +63,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmfge.vf.yaml b/arch/inst/V/vmfge.vf.yaml index c449201be6..2e7cf5ff3e 100644 --- a/arch/inst/V/vmfge.vf.yaml +++ b/arch/inst/V/vmfge.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_vd_unmasked(SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -65,9 +65,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmfgt.vf.yaml b/arch/inst/V/vmfgt.vf.yaml index 3a7c121aa5..13197e5704 100644 --- a/arch/inst/V/vmfgt.vf.yaml +++ b/arch/inst/V/vmfgt.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_vd_unmasked(SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -65,9 +65,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmfle.vf.yaml b/arch/inst/V/vmfle.vf.yaml index 405a2073ab..f85b9dbf53 100644 --- a/arch/inst/V/vmfle.vf.yaml +++ b/arch/inst/V/vmfle.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_vd_unmasked(SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -65,9 +65,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmfle.vv.yaml b/arch/inst/V/vmfle.vv.yaml index 7937c55477..318034f107 100644 --- a/arch/inst/V/vmfle.vv.yaml +++ b/arch/inst/V/vmfle.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_vd_unmasked(SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -63,9 +63,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmflt.vf.yaml b/arch/inst/V/vmflt.vf.yaml index 3260c4d263..77d68c8381 100644 --- a/arch/inst/V/vmflt.vf.yaml +++ b/arch/inst/V/vmflt.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_vd_unmasked(SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -65,9 +65,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmflt.vv.yaml b/arch/inst/V/vmflt.vv.yaml index a89bab6ba6..676841f717 100644 --- a/arch/inst/V/vmflt.vv.yaml +++ b/arch/inst/V/vmflt.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_vd_unmasked(SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -63,9 +63,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmfne.vf.yaml b/arch/inst/V/vmfne.vf.yaml index f8dc41881e..adf5cd410e 100644 --- a/arch/inst/V/vmfne.vf.yaml +++ b/arch/inst/V/vmfne.vf.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_vd_unmasked(SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -65,9 +65,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmfne.vv.yaml b/arch/inst/V/vmfne.vv.yaml index 49052496ca..a5078c955d 100644 --- a/arch/inst/V/vmfne.vv.yaml +++ b/arch/inst/V/vmfne.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,22 +36,22 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_fp_vd_unmasked(SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW != 8); - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -63,9 +63,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmin.vv.yaml b/arch/inst/V/vmin.vv.yaml index 77b5c4b753..4b5c9cad97 100644 --- a/arch/inst/V/vmin.vv.yaml +++ b/arch/inst/V/vmin.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,21 +37,21 @@ sail(): | let LMUL_pow = get_lmul_pow(); let VLEN_pow = get_vlen_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -120,9 +120,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmin.vx.yaml b/arch/inst/V/vmin.vx.yaml index 93b7149dba..12be058ede 100644 --- a/arch/inst/V/vmin.vx.yaml +++ b/arch/inst/V/vmin.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -103,9 +103,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vminu.vv.yaml b/arch/inst/V/vminu.vv.yaml index fb5523ec90..897d4b1207 100644 --- a/arch/inst/V/vminu.vv.yaml +++ b/arch/inst/V/vminu.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,21 +37,21 @@ sail(): | let LMUL_pow = get_lmul_pow(); let VLEN_pow = get_vlen_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -120,9 +120,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vminu.vx.yaml b/arch/inst/V/vminu.vx.yaml index 25835e6f8b..890b564300 100644 --- a/arch/inst/V/vminu.vx.yaml +++ b/arch/inst/V/vminu.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -103,9 +103,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmnand.mm.yaml b/arch/inst/V/vmnand.mm.yaml index 8b81cd5e07..e32a80db47 100644 --- a/arch/inst/V/vmnand.mm.yaml +++ b/arch/inst/V/vmnand.mm.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -33,20 +33,20 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = unsigned(vlenb) * 8; - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vs1_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs1); let vs2_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_carry(num_elem, SEW, 0, vd_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -61,9 +61,8 @@ sail(): | } } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmnor.mm.yaml b/arch/inst/V/vmnor.mm.yaml index 6666bd9a56..e0ccff3e3f 100644 --- a/arch/inst/V/vmnor.mm.yaml +++ b/arch/inst/V/vmnor.mm.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -33,20 +33,20 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = unsigned(vlenb) * 8; - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vs1_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs1); let vs2_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_carry(num_elem, SEW, 0, vd_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -61,9 +61,8 @@ sail(): | } } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmor.mm.yaml b/arch/inst/V/vmor.mm.yaml index 4997ebe693..81e64a938b 100644 --- a/arch/inst/V/vmor.mm.yaml +++ b/arch/inst/V/vmor.mm.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -33,20 +33,20 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = unsigned(vlenb) * 8; - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vs1_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs1); let vs2_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_carry(num_elem, SEW, 0, vd_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -61,9 +61,8 @@ sail(): | } } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmorn.mm.yaml b/arch/inst/V/vmorn.mm.yaml index 2307206bb7..89e53e8fec 100644 --- a/arch/inst/V/vmorn.mm.yaml +++ b/arch/inst/V/vmorn.mm.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vmsbc.vv.yaml b/arch/inst/V/vmsbc.vv.yaml index b0e07e9108..f7fa84ea2b 100644 --- a/arch/inst/V/vmsbc.vv.yaml +++ b/arch/inst/V/vmsbc.vv.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -33,20 +33,20 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_carry(num_elem, SEW, LMUL_pow, vd_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -56,9 +56,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmsbc.vvm.yaml b/arch/inst/V/vmsbc.vvm.yaml index af3db9f4fe..c4837da151 100644 --- a/arch/inst/V/vmsbc.vvm.yaml +++ b/arch/inst/V/vmsbc.vvm.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -33,21 +33,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask_carry(num_elem, 0b0, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_carry(num_elem, SEW, LMUL_pow, vd_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -57,9 +57,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmsbc.vx.yaml b/arch/inst/V/vmsbc.vx.yaml index 3179ccd99b..2caf127ca2 100644 --- a/arch/inst/V/vmsbc.vx.yaml +++ b/arch/inst/V/vmsbc.vx.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -33,20 +33,20 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_carry(num_elem, SEW, LMUL_pow, vd_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -56,9 +56,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmsbc.vxm.yaml b/arch/inst/V/vmsbc.vxm.yaml index 2e54d64e24..f0865388b0 100644 --- a/arch/inst/V/vmsbc.vxm.yaml +++ b/arch/inst/V/vmsbc.vxm.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -33,21 +33,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask_carry(num_elem, 0b0, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_carry(num_elem, SEW, LMUL_pow, vd_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -57,9 +57,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmsbf.m.yaml b/arch/inst/V/vmsbf.m.yaml index bfc1ab0a36..fe85db16a6 100644 --- a/arch/inst/V/vmsbf.m.yaml +++ b/arch/inst/V/vmsbf.m.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -33,21 +33,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = unsigned(vlenb) * 8; - + if illegal_normal(vd, vm) | not(assert_vstart(0)) | vd == vs2 then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, 0, vd_val, vm_val); - + found_elem : bool = false; foreach (i from 0 to (num_elem - 1)) { if mask[i] then { @@ -55,9 +55,8 @@ sail(): | result[i] = if found_elem then false else true } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmseq.vi.yaml b/arch/inst/V/vmseq.vi.yaml index 1111623e52..fc52fa6a6e 100644 --- a/arch/inst/V/vmseq.vi.yaml +++ b/arch/inst/V/vmseq.vi.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let imm_val : bits('m) = sign_extend(simm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -63,9 +63,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmseq.vv.yaml b/arch/inst/V/vmseq.vv.yaml index 288533e63b..cfb1bb786e 100644 --- a/arch/inst/V/vmseq.vv.yaml +++ b/arch/inst/V/vmseq.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -63,9 +63,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmseq.vx.yaml b/arch/inst/V/vmseq.vx.yaml index 3353ae1f3c..55003e0e7f 100644 --- a/arch/inst/V/vmseq.vx.yaml +++ b/arch/inst/V/vmseq.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -65,9 +65,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmsgt.vi.yaml b/arch/inst/V/vmsgt.vi.yaml index 20db0adf9e..946b787fb8 100644 --- a/arch/inst/V/vmsgt.vi.yaml +++ b/arch/inst/V/vmsgt.vi.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let imm_val : bits('m) = sign_extend(simm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -63,9 +63,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmsgt.vx.yaml b/arch/inst/V/vmsgt.vx.yaml index b7829e81d5..fd878324b2 100644 --- a/arch/inst/V/vmsgt.vx.yaml +++ b/arch/inst/V/vmsgt.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -65,9 +65,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmsgtu.vi.yaml b/arch/inst/V/vmsgtu.vi.yaml index 281acc772b..9119f759c2 100644 --- a/arch/inst/V/vmsgtu.vi.yaml +++ b/arch/inst/V/vmsgtu.vi.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let imm_val : bits('m) = sign_extend(simm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -63,9 +63,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmsgtu.vx.yaml b/arch/inst/V/vmsgtu.vx.yaml index 2ea8494fb5..5943925efb 100644 --- a/arch/inst/V/vmsgtu.vx.yaml +++ b/arch/inst/V/vmsgtu.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -65,9 +65,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmsif.m.yaml b/arch/inst/V/vmsif.m.yaml index 9b04f46a49..0082106586 100644 --- a/arch/inst/V/vmsif.m.yaml +++ b/arch/inst/V/vmsif.m.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -33,21 +33,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = unsigned(vlenb) * 8; - + if illegal_normal(vd, vm) | not(assert_vstart(0)) | vd == vs2 then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, 0, vd_val, vm_val); - + found_elem : bool = false; foreach (i from 0 to (num_elem - 1)) { if mask[i] then { @@ -55,9 +55,8 @@ sail(): | if vs2_val[i] then found_elem = true } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmsle.vi.yaml b/arch/inst/V/vmsle.vi.yaml index 2f0fa5a9b3..a7d5d7367e 100644 --- a/arch/inst/V/vmsle.vi.yaml +++ b/arch/inst/V/vmsle.vi.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let imm_val : bits('m) = sign_extend(simm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -63,9 +63,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmsle.vv.yaml b/arch/inst/V/vmsle.vv.yaml index 12003d18ee..6a41afaaa1 100644 --- a/arch/inst/V/vmsle.vv.yaml +++ b/arch/inst/V/vmsle.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -63,9 +63,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmsle.vx.yaml b/arch/inst/V/vmsle.vx.yaml index f36e30dfee..a8474a3889 100644 --- a/arch/inst/V/vmsle.vx.yaml +++ b/arch/inst/V/vmsle.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -65,9 +65,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmsleu.vi.yaml b/arch/inst/V/vmsleu.vi.yaml index 568e1c9663..0adb60845b 100644 --- a/arch/inst/V/vmsleu.vi.yaml +++ b/arch/inst/V/vmsleu.vi.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let imm_val : bits('m) = sign_extend(simm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -63,9 +63,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmsleu.vv.yaml b/arch/inst/V/vmsleu.vv.yaml index ce1a24e968..953e32a489 100644 --- a/arch/inst/V/vmsleu.vv.yaml +++ b/arch/inst/V/vmsleu.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -63,9 +63,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmsleu.vx.yaml b/arch/inst/V/vmsleu.vx.yaml index b97fc1f375..7a1122585f 100644 --- a/arch/inst/V/vmsleu.vx.yaml +++ b/arch/inst/V/vmsleu.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -65,9 +65,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmslt.vv.yaml b/arch/inst/V/vmslt.vv.yaml index 20da4ac039..f275667bd8 100644 --- a/arch/inst/V/vmslt.vv.yaml +++ b/arch/inst/V/vmslt.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -63,9 +63,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmslt.vx.yaml b/arch/inst/V/vmslt.vx.yaml index 978a9d5e98..b44cd616b7 100644 --- a/arch/inst/V/vmslt.vx.yaml +++ b/arch/inst/V/vmslt.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -65,9 +65,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmsltu.vv.yaml b/arch/inst/V/vmsltu.vv.yaml index 99bf21b162..7da2e1662b 100644 --- a/arch/inst/V/vmsltu.vv.yaml +++ b/arch/inst/V/vmsltu.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -63,9 +63,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmsltu.vx.yaml b/arch/inst/V/vmsltu.vx.yaml index d6edc38022..92d8ecbceb 100644 --- a/arch/inst/V/vmsltu.vx.yaml +++ b/arch/inst/V/vmsltu.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -65,9 +65,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmsne.vi.yaml b/arch/inst/V/vmsne.vi.yaml index fb3913dd40..8f9fe39bbf 100644 --- a/arch/inst/V/vmsne.vi.yaml +++ b/arch/inst/V/vmsne.vi.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let imm_val : bits('m) = sign_extend(simm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -63,9 +63,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmsne.vv.yaml b/arch/inst/V/vmsne.vv.yaml index d4155d0fe0..69cb50f337 100644 --- a/arch/inst/V/vmsne.vv.yaml +++ b/arch/inst/V/vmsne.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -63,9 +63,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmsne.vx.yaml b/arch/inst/V/vmsne.vx.yaml index fabb8489ad..0e642b27ed 100644 --- a/arch/inst/V/vmsne.vx.yaml +++ b/arch/inst/V/vmsne.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { let res : bool = match funct6 { @@ -65,9 +65,8 @@ sail(): | result[i] = res } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmsof.m.yaml b/arch/inst/V/vmsof.m.yaml index 561216b3c4..6d6ff006fe 100644 --- a/arch/inst/V/vmsof.m.yaml +++ b/arch/inst/V/vmsof.m.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -33,21 +33,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = unsigned(vlenb) * 8; - + if illegal_normal(vd, vm) | not(assert_vstart(0)) | vd == vs2 then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs2_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_cmp(num_elem, SEW, 0, vd_val, vm_val); - + found_elem : bool = false; foreach (i from 0 to (num_elem - 1)) { if mask[i] then { @@ -59,9 +59,8 @@ sail(): | } } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmul.vv.yaml b/arch/inst/V/vmul.vv.yaml index 6de1b16ec4..7d91cd8a5b 100644 --- a/arch/inst/V/vmul.vv.yaml +++ b/arch/inst/V/vmul.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -102,9 +102,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmul.vx.yaml b/arch/inst/V/vmul.vx.yaml index f75d0e7794..e05e8672d2 100644 --- a/arch/inst/V/vmul.vx.yaml +++ b/arch/inst/V/vmul.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -111,9 +111,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmulh.vv.yaml b/arch/inst/V/vmulh.vv.yaml index 43469bc27f..e189c650e0 100644 --- a/arch/inst/V/vmulh.vv.yaml +++ b/arch/inst/V/vmulh.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -102,9 +102,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmulh.vx.yaml b/arch/inst/V/vmulh.vx.yaml index 36e4291544..4cf640bad2 100644 --- a/arch/inst/V/vmulh.vx.yaml +++ b/arch/inst/V/vmulh.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -111,9 +111,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmulhsu.vv.yaml b/arch/inst/V/vmulhsu.vv.yaml index 0d91b69f6d..bb9a147cf2 100644 --- a/arch/inst/V/vmulhsu.vv.yaml +++ b/arch/inst/V/vmulhsu.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -102,9 +102,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmulhsu.vx.yaml b/arch/inst/V/vmulhsu.vx.yaml index 768b155fad..f81024ed11 100644 --- a/arch/inst/V/vmulhsu.vx.yaml +++ b/arch/inst/V/vmulhsu.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -111,9 +111,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmulhu.vv.yaml b/arch/inst/V/vmulhu.vv.yaml index 8d3dc32041..a78c29831f 100644 --- a/arch/inst/V/vmulhu.vv.yaml +++ b/arch/inst/V/vmulhu.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -102,9 +102,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmulhu.vx.yaml b/arch/inst/V/vmulhu.vx.yaml index baa34f7efc..1ab5613bb2 100644 --- a/arch/inst/V/vmulhu.vx.yaml +++ b/arch/inst/V/vmulhu.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -111,9 +111,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmv.s.x.yaml b/arch/inst/V/vmv.s.x.yaml index bbe68c70aa..2d4a355584 100644 --- a/arch/inst/V/vmv.s.x.yaml +++ b/arch/inst/V/vmv.s.x.yaml @@ -22,7 +22,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -30,24 +30,24 @@ sail(): | { let SEW = get_sew(); let num_elem = get_num_elem(0, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + assert(num_elem > 0); let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b1, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, 'm); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, 0, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, 0, vd_val, vm_val); - + /* one body element */ if mask[0] then result[0] = rs1_val; - + /* others treated as tail elements */ let tail_ag : agtype = get_vtype_vta(); foreach (i from 1 to (num_elem - 1)) { @@ -56,9 +56,8 @@ sail(): | AGNOSTIC => vd_val[i] /* TODO: configuration support */ } }; - + write_vreg(num_elem, SEW, 0, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmv.v.i.yaml b/arch/inst/V/vmv.v.i.yaml index 6a4f451d8a..dee7de9eca 100644 --- a/arch/inst/V/vmv.v.i.yaml +++ b/arch/inst/V/vmv.v.i.yaml @@ -22,7 +22,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -31,26 +31,25 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b1, 0b00000); let imm_val : bits('m) = sign_extend(simm); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then result[i] = imm_val }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmv.v.v.yaml b/arch/inst/V/vmv.v.v.yaml index 477036e397..29cdff6084 100644 --- a/arch/inst/V/vmv.v.v.yaml +++ b/arch/inst/V/vmv.v.v.yaml @@ -22,7 +22,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -31,26 +31,25 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b1, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then result[i] = vs1_val[i] }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmv.v.x.yaml b/arch/inst/V/vmv.v.x.yaml index 0375fa96d8..5efb079a00 100644 --- a/arch/inst/V/vmv.v.x.yaml +++ b/arch/inst/V/vmv.v.x.yaml @@ -22,7 +22,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -31,26 +31,25 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let rs1_val : bits('m) = get_scalar(rs1, 'm); let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b1, 0b00000); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then result[i] = rs1_val }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmv.x.s.yaml b/arch/inst/V/vmv.x.s.yaml index 0c126cbb33..40aed3db6d 100644 --- a/arch/inst/V/vmv.x.s.yaml +++ b/arch/inst/V/vmv.x.s.yaml @@ -22,7 +22,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -30,19 +30,18 @@ sail(): | { let SEW = get_sew(); let num_elem = get_num_elem(0, SEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + assert(num_elem > 0); let 'n = num_elem; let 'm = SEW; - + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, 0, vs2); X(rd) = if sizeof(xlen) < SEW then slice(vs2_val[0], 0, sizeof(xlen)) else if sizeof(xlen) > SEW then sign_extend(vs2_val[0]) else vs2_val[0]; vstart = zeros(); - + RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmv1r.v.yaml b/arch/inst/V/vmv1r.v.yaml index 1a059cec6e..4d3d470ed3 100644 --- a/arch/inst/V/vmv1r.v.yaml +++ b/arch/inst/V/vmv1r.v.yaml @@ -22,7 +22,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -32,25 +32,24 @@ sail(): | let SEW = get_sew(); let imm_val = unsigned(zero_extend(sizeof(xlen), simm)); let EMUL = imm_val + 1; - + if not(EMUL == 1 | EMUL == 2 | EMUL == 4 | EMUL == 8) then { handle_illegal(); return RETIRE_FAIL }; - + let EMUL_pow = log2(EMUL); let num_elem = get_num_elem(EMUL_pow, SEW); let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b1, 0b00000); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, EMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, EMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; - + foreach (i from 0 to (num_elem - 1)) { result[i] = if i < start_element then vd_val[i] else vs2_val[i] }; - + write_vreg(num_elem, SEW, EMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmv2r.v.yaml b/arch/inst/V/vmv2r.v.yaml index 0c4b695e8b..88b8705a1e 100644 --- a/arch/inst/V/vmv2r.v.yaml +++ b/arch/inst/V/vmv2r.v.yaml @@ -22,7 +22,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -32,25 +32,24 @@ sail(): | let SEW = get_sew(); let imm_val = unsigned(zero_extend(sizeof(xlen), simm)); let EMUL = imm_val + 1; - + if not(EMUL == 1 | EMUL == 2 | EMUL == 4 | EMUL == 8) then { handle_illegal(); return RETIRE_FAIL }; - + let EMUL_pow = log2(EMUL); let num_elem = get_num_elem(EMUL_pow, SEW); let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b1, 0b00000); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, EMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, EMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; - + foreach (i from 0 to (num_elem - 1)) { result[i] = if i < start_element then vd_val[i] else vs2_val[i] }; - + write_vreg(num_elem, SEW, EMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmv4r.v.yaml b/arch/inst/V/vmv4r.v.yaml index 5da446a959..99ac5a720c 100644 --- a/arch/inst/V/vmv4r.v.yaml +++ b/arch/inst/V/vmv4r.v.yaml @@ -22,7 +22,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -32,25 +32,24 @@ sail(): | let SEW = get_sew(); let imm_val = unsigned(zero_extend(sizeof(xlen), simm)); let EMUL = imm_val + 1; - + if not(EMUL == 1 | EMUL == 2 | EMUL == 4 | EMUL == 8) then { handle_illegal(); return RETIRE_FAIL }; - + let EMUL_pow = log2(EMUL); let num_elem = get_num_elem(EMUL_pow, SEW); let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b1, 0b00000); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, EMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, EMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; - + foreach (i from 0 to (num_elem - 1)) { result[i] = if i < start_element then vd_val[i] else vs2_val[i] }; - + write_vreg(num_elem, SEW, EMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmv8r.v.yaml b/arch/inst/V/vmv8r.v.yaml index 1154eb63ea..66074274c7 100644 --- a/arch/inst/V/vmv8r.v.yaml +++ b/arch/inst/V/vmv8r.v.yaml @@ -22,7 +22,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -32,25 +32,24 @@ sail(): | let SEW = get_sew(); let imm_val = unsigned(zero_extend(sizeof(xlen), simm)); let EMUL = imm_val + 1; - + if not(EMUL == 1 | EMUL == 2 | EMUL == 4 | EMUL == 8) then { handle_illegal(); return RETIRE_FAIL }; - + let EMUL_pow = log2(EMUL); let num_elem = get_num_elem(EMUL_pow, SEW); let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b1, 0b00000); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, EMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, EMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; - + foreach (i from 0 to (num_elem - 1)) { result[i] = if i < start_element then vd_val[i] else vs2_val[i] }; - + write_vreg(num_elem, SEW, EMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmxnor.mm.yaml b/arch/inst/V/vmxnor.mm.yaml index 9701400e8e..e4f9dbf04e 100644 --- a/arch/inst/V/vmxnor.mm.yaml +++ b/arch/inst/V/vmxnor.mm.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -33,20 +33,20 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = unsigned(vlenb) * 8; - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vs1_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs1); let vs2_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_carry(num_elem, SEW, 0, vd_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -61,9 +61,8 @@ sail(): | } } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vmxor.mm.yaml b/arch/inst/V/vmxor.mm.yaml index 1f65ed0e37..ec0ea44ef2 100644 --- a/arch/inst/V/vmxor.mm.yaml +++ b/arch/inst/V/vmxor.mm.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -33,20 +33,20 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = unsigned(vlenb) * 8; - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vs1_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs1); let vs2_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs2); let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result_carry(num_elem, SEW, 0, vd_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -61,9 +61,8 @@ sail(): | } } }; - + write_vmask(num_elem, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vnclip.wi.yaml b/arch/inst/V/vnclip.wi.yaml index ffdc9e4dcf..e231052abb 100644 --- a/arch/inst/V/vnclip.wi.yaml +++ b/arch/inst/V/vnclip.wi.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,24 +37,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); let imm_val : bits('m) = sign_extend(simm); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + assert(SEW_widen <= 64); foreach (i from 0 to (num_elem - 1)) { if mask[i] then { @@ -73,9 +73,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vnclip.wv.yaml b/arch/inst/V/vnclip.wv.yaml index 29112c838e..faca59c938 100644 --- a/arch/inst/V/vnclip.wv.yaml +++ b/arch/inst/V/vnclip.wv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,24 +37,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + assert(SEW_widen <= 64); foreach (i from 0 to (num_elem - 1)) { if mask[i] then { @@ -73,9 +73,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vnclip.wx.yaml b/arch/inst/V/vnclip.wx.yaml index adf57842d3..ee879075e5 100644 --- a/arch/inst/V/vnclip.wx.yaml +++ b/arch/inst/V/vnclip.wx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,24 +37,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + assert(SEW_widen <= 64); foreach (i from 0 to (num_elem - 1)) { if mask[i] then { @@ -73,9 +73,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vnclipu.wi.yaml b/arch/inst/V/vnclipu.wi.yaml index 9d2789f0b9..7cf326ed0c 100644 --- a/arch/inst/V/vnclipu.wi.yaml +++ b/arch/inst/V/vnclipu.wi.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,24 +37,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); let imm_val : bits('m) = sign_extend(simm); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + assert(SEW_widen <= 64); foreach (i from 0 to (num_elem - 1)) { if mask[i] then { @@ -73,9 +73,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vnclipu.wv.yaml b/arch/inst/V/vnclipu.wv.yaml index 075172d522..b4a565a40e 100644 --- a/arch/inst/V/vnclipu.wv.yaml +++ b/arch/inst/V/vnclipu.wv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,24 +37,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + assert(SEW_widen <= 64); foreach (i from 0 to (num_elem - 1)) { if mask[i] then { @@ -73,9 +73,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vnclipu.wx.yaml b/arch/inst/V/vnclipu.wx.yaml index 3e102c019c..af13d2fe96 100644 --- a/arch/inst/V/vnclipu.wx.yaml +++ b/arch/inst/V/vnclipu.wx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,24 +37,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + assert(SEW_widen <= 64); foreach (i from 0 to (num_elem - 1)) { if mask[i] then { @@ -73,9 +73,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vnmsac.vv.yaml b/arch/inst/V/vnmsac.vv.yaml index 8489b01a01..f9426f75c8 100644 --- a/arch/inst/V/vnmsac.vv.yaml +++ b/arch/inst/V/vnmsac.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -60,9 +60,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vnmsac.vx.yaml b/arch/inst/V/vnmsac.vx.yaml index dcd3e2aa2c..307b1d45a1 100644 --- a/arch/inst/V/vnmsac.vx.yaml +++ b/arch/inst/V/vnmsac.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -60,9 +60,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vnmsub.vv.yaml b/arch/inst/V/vnmsub.vv.yaml index 9b34de28de..23c4cfdaf3 100644 --- a/arch/inst/V/vnmsub.vv.yaml +++ b/arch/inst/V/vnmsub.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -60,9 +60,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vnmsub.vx.yaml b/arch/inst/V/vnmsub.vx.yaml index 9e1b63f0fb..95270f1a9d 100644 --- a/arch/inst/V/vnmsub.vx.yaml +++ b/arch/inst/V/vnmsub.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -60,9 +60,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vnsra.wi.yaml b/arch/inst/V/vnsra.wi.yaml index bc8a52603a..67e6aaa0f9 100644 --- a/arch/inst/V/vnsra.wi.yaml +++ b/arch/inst/V/vnsra.wi.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,24 +37,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); let imm_val : bits('m) = sign_extend(simm); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + assert(SEW_widen <= 64); foreach (i from 0 to (num_elem - 1)) { if mask[i] then { @@ -72,9 +72,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vnsra.wv.yaml b/arch/inst/V/vnsra.wv.yaml index 678d1b3793..a9e6be1155 100644 --- a/arch/inst/V/vnsra.wv.yaml +++ b/arch/inst/V/vnsra.wv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,24 +37,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + assert(SEW_widen <= 64); foreach (i from 0 to (num_elem - 1)) { if mask[i] then { @@ -72,9 +72,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vnsra.wx.yaml b/arch/inst/V/vnsra.wx.yaml index 61bbe59f23..f8e6b05597 100644 --- a/arch/inst/V/vnsra.wx.yaml +++ b/arch/inst/V/vnsra.wx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,24 +37,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + assert(SEW_widen <= 64); foreach (i from 0 to (num_elem - 1)) { if mask[i] then { @@ -72,9 +72,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vnsrl.wi.yaml b/arch/inst/V/vnsrl.wi.yaml index 7ab138f445..7b35f84f1b 100644 --- a/arch/inst/V/vnsrl.wi.yaml +++ b/arch/inst/V/vnsrl.wi.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,24 +37,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); let imm_val : bits('m) = sign_extend(simm); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + assert(SEW_widen <= 64); foreach (i from 0 to (num_elem - 1)) { if mask[i] then { @@ -72,9 +72,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vnsrl.wv.yaml b/arch/inst/V/vnsrl.wv.yaml index 4629cfa968..3c8c95679a 100644 --- a/arch/inst/V/vnsrl.wv.yaml +++ b/arch/inst/V/vnsrl.wv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,24 +37,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + assert(SEW_widen <= 64); foreach (i from 0 to (num_elem - 1)) { if mask[i] then { @@ -72,9 +72,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vnsrl.wx.yaml b/arch/inst/V/vnsrl.wx.yaml index 0ece78c6d4..92b3679cf6 100644 --- a/arch/inst/V/vnsrl.wx.yaml +++ b/arch/inst/V/vnsrl.wx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,24 +37,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + assert(SEW_widen <= 64); foreach (i from 0 to (num_elem - 1)) { if mask[i] then { @@ -72,9 +72,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vor.vi.yaml b/arch/inst/V/vor.vi.yaml index afccdd98ea..99f59df679 100644 --- a/arch/inst/V/vor.vi.yaml +++ b/arch/inst/V/vor.vi.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let imm_val : bits('m) = sign_extend(simm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -87,9 +87,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vor.vv.yaml b/arch/inst/V/vor.vv.yaml index 130894e9bb..c832084738 100644 --- a/arch/inst/V/vor.vv.yaml +++ b/arch/inst/V/vor.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,21 +37,21 @@ sail(): | let LMUL_pow = get_lmul_pow(); let VLEN_pow = get_vlen_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -120,9 +120,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vor.vx.yaml b/arch/inst/V/vor.vx.yaml index b38fe65844..9ad6b20d1e 100644 --- a/arch/inst/V/vor.vx.yaml +++ b/arch/inst/V/vor.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -103,9 +103,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vredand.vs.yaml b/arch/inst/V/vredand.vs.yaml index fa531e5e92..135ed6bb39 100644 --- a/arch/inst/V/vredand.vs.yaml +++ b/arch/inst/V/vredand.vs.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,20 +36,20 @@ sail(): | let LMUL_pow = get_lmul_pow(); let num_elem_vs = get_num_elem(LMUL_pow, SEW); let num_elem_vd = get_num_elem(0, SEW); /* vd regardless of LMUL setting */ - + if illegal_reduction() then { handle_illegal(); return RETIRE_FAIL }; - + if unsigned(vl) == 0 then return RETIRE_SUCCESS; /* if vl=0, no operation is performed */ - + let 'n = num_elem_vs; let 'd = num_elem_vd; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem_vs, vm, 0b00000); let vd_val : vector('d, dec, bits('m)) = read_vreg(num_elem_vd, SEW, 0, vd); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem_vs, SEW, LMUL_pow, vs2); let mask : vector('n, dec, bool) = init_masked_source(num_elem_vs, LMUL_pow, vm_val); - + sum : bits('m) = read_single_element(SEW, 0, vs1); /* vs1 regardless of LMUL setting */ foreach (i from 0 to (num_elem_vs - 1)) { if mask[i] then { @@ -65,11 +65,10 @@ sail(): | } } }; - + write_single_element(SEW, 0, vd, sum); /* other elements in vd are treated as tail elements, currently remain unchanged */ /* TODO: configuration support for agnostic behavior */ vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vredmax.vs.yaml b/arch/inst/V/vredmax.vs.yaml index 428f7dc539..9d1b12a38e 100644 --- a/arch/inst/V/vredmax.vs.yaml +++ b/arch/inst/V/vredmax.vs.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,20 +36,20 @@ sail(): | let LMUL_pow = get_lmul_pow(); let num_elem_vs = get_num_elem(LMUL_pow, SEW); let num_elem_vd = get_num_elem(0, SEW); /* vd regardless of LMUL setting */ - + if illegal_reduction() then { handle_illegal(); return RETIRE_FAIL }; - + if unsigned(vl) == 0 then return RETIRE_SUCCESS; /* if vl=0, no operation is performed */ - + let 'n = num_elem_vs; let 'd = num_elem_vd; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem_vs, vm, 0b00000); let vd_val : vector('d, dec, bits('m)) = read_vreg(num_elem_vd, SEW, 0, vd); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem_vs, SEW, LMUL_pow, vs2); let mask : vector('n, dec, bool) = init_masked_source(num_elem_vs, LMUL_pow, vm_val); - + sum : bits('m) = read_single_element(SEW, 0, vs1); /* vs1 regardless of LMUL setting */ foreach (i from 0 to (num_elem_vs - 1)) { if mask[i] then { @@ -65,11 +65,10 @@ sail(): | } } }; - + write_single_element(SEW, 0, vd, sum); /* other elements in vd are treated as tail elements, currently remain unchanged */ /* TODO: configuration support for agnostic behavior */ vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vredmaxu.vs.yaml b/arch/inst/V/vredmaxu.vs.yaml index 548ab1858b..977d71dac4 100644 --- a/arch/inst/V/vredmaxu.vs.yaml +++ b/arch/inst/V/vredmaxu.vs.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,20 +36,20 @@ sail(): | let LMUL_pow = get_lmul_pow(); let num_elem_vs = get_num_elem(LMUL_pow, SEW); let num_elem_vd = get_num_elem(0, SEW); /* vd regardless of LMUL setting */ - + if illegal_reduction() then { handle_illegal(); return RETIRE_FAIL }; - + if unsigned(vl) == 0 then return RETIRE_SUCCESS; /* if vl=0, no operation is performed */ - + let 'n = num_elem_vs; let 'd = num_elem_vd; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem_vs, vm, 0b00000); let vd_val : vector('d, dec, bits('m)) = read_vreg(num_elem_vd, SEW, 0, vd); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem_vs, SEW, LMUL_pow, vs2); let mask : vector('n, dec, bool) = init_masked_source(num_elem_vs, LMUL_pow, vm_val); - + sum : bits('m) = read_single_element(SEW, 0, vs1); /* vs1 regardless of LMUL setting */ foreach (i from 0 to (num_elem_vs - 1)) { if mask[i] then { @@ -65,11 +65,10 @@ sail(): | } } }; - + write_single_element(SEW, 0, vd, sum); /* other elements in vd are treated as tail elements, currently remain unchanged */ /* TODO: configuration support for agnostic behavior */ vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vredmin.vs.yaml b/arch/inst/V/vredmin.vs.yaml index 41ac773bcd..df9b4ba46d 100644 --- a/arch/inst/V/vredmin.vs.yaml +++ b/arch/inst/V/vredmin.vs.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,20 +36,20 @@ sail(): | let LMUL_pow = get_lmul_pow(); let num_elem_vs = get_num_elem(LMUL_pow, SEW); let num_elem_vd = get_num_elem(0, SEW); /* vd regardless of LMUL setting */ - + if illegal_reduction() then { handle_illegal(); return RETIRE_FAIL }; - + if unsigned(vl) == 0 then return RETIRE_SUCCESS; /* if vl=0, no operation is performed */ - + let 'n = num_elem_vs; let 'd = num_elem_vd; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem_vs, vm, 0b00000); let vd_val : vector('d, dec, bits('m)) = read_vreg(num_elem_vd, SEW, 0, vd); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem_vs, SEW, LMUL_pow, vs2); let mask : vector('n, dec, bool) = init_masked_source(num_elem_vs, LMUL_pow, vm_val); - + sum : bits('m) = read_single_element(SEW, 0, vs1); /* vs1 regardless of LMUL setting */ foreach (i from 0 to (num_elem_vs - 1)) { if mask[i] then { @@ -65,11 +65,10 @@ sail(): | } } }; - + write_single_element(SEW, 0, vd, sum); /* other elements in vd are treated as tail elements, currently remain unchanged */ /* TODO: configuration support for agnostic behavior */ vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vredminu.vs.yaml b/arch/inst/V/vredminu.vs.yaml index 64c924b881..f3ee165cb8 100644 --- a/arch/inst/V/vredminu.vs.yaml +++ b/arch/inst/V/vredminu.vs.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,20 +36,20 @@ sail(): | let LMUL_pow = get_lmul_pow(); let num_elem_vs = get_num_elem(LMUL_pow, SEW); let num_elem_vd = get_num_elem(0, SEW); /* vd regardless of LMUL setting */ - + if illegal_reduction() then { handle_illegal(); return RETIRE_FAIL }; - + if unsigned(vl) == 0 then return RETIRE_SUCCESS; /* if vl=0, no operation is performed */ - + let 'n = num_elem_vs; let 'd = num_elem_vd; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem_vs, vm, 0b00000); let vd_val : vector('d, dec, bits('m)) = read_vreg(num_elem_vd, SEW, 0, vd); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem_vs, SEW, LMUL_pow, vs2); let mask : vector('n, dec, bool) = init_masked_source(num_elem_vs, LMUL_pow, vm_val); - + sum : bits('m) = read_single_element(SEW, 0, vs1); /* vs1 regardless of LMUL setting */ foreach (i from 0 to (num_elem_vs - 1)) { if mask[i] then { @@ -65,11 +65,10 @@ sail(): | } } }; - + write_single_element(SEW, 0, vd, sum); /* other elements in vd are treated as tail elements, currently remain unchanged */ /* TODO: configuration support for agnostic behavior */ vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vredor.vs.yaml b/arch/inst/V/vredor.vs.yaml index 3c54847de1..121bee827f 100644 --- a/arch/inst/V/vredor.vs.yaml +++ b/arch/inst/V/vredor.vs.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,20 +36,20 @@ sail(): | let LMUL_pow = get_lmul_pow(); let num_elem_vs = get_num_elem(LMUL_pow, SEW); let num_elem_vd = get_num_elem(0, SEW); /* vd regardless of LMUL setting */ - + if illegal_reduction() then { handle_illegal(); return RETIRE_FAIL }; - + if unsigned(vl) == 0 then return RETIRE_SUCCESS; /* if vl=0, no operation is performed */ - + let 'n = num_elem_vs; let 'd = num_elem_vd; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem_vs, vm, 0b00000); let vd_val : vector('d, dec, bits('m)) = read_vreg(num_elem_vd, SEW, 0, vd); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem_vs, SEW, LMUL_pow, vs2); let mask : vector('n, dec, bool) = init_masked_source(num_elem_vs, LMUL_pow, vm_val); - + sum : bits('m) = read_single_element(SEW, 0, vs1); /* vs1 regardless of LMUL setting */ foreach (i from 0 to (num_elem_vs - 1)) { if mask[i] then { @@ -65,11 +65,10 @@ sail(): | } } }; - + write_single_element(SEW, 0, vd, sum); /* other elements in vd are treated as tail elements, currently remain unchanged */ /* TODO: configuration support for agnostic behavior */ vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vredsum.vs.yaml b/arch/inst/V/vredsum.vs.yaml index d254f41674..be0b41c8b3 100644 --- a/arch/inst/V/vredsum.vs.yaml +++ b/arch/inst/V/vredsum.vs.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,20 +36,20 @@ sail(): | let LMUL_pow = get_lmul_pow(); let num_elem_vs = get_num_elem(LMUL_pow, SEW); let num_elem_vd = get_num_elem(0, SEW); /* vd regardless of LMUL setting */ - + if illegal_reduction() then { handle_illegal(); return RETIRE_FAIL }; - + if unsigned(vl) == 0 then return RETIRE_SUCCESS; /* if vl=0, no operation is performed */ - + let 'n = num_elem_vs; let 'd = num_elem_vd; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem_vs, vm, 0b00000); let vd_val : vector('d, dec, bits('m)) = read_vreg(num_elem_vd, SEW, 0, vd); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem_vs, SEW, LMUL_pow, vs2); let mask : vector('n, dec, bool) = init_masked_source(num_elem_vs, LMUL_pow, vm_val); - + sum : bits('m) = read_single_element(SEW, 0, vs1); /* vs1 regardless of LMUL setting */ foreach (i from 0 to (num_elem_vs - 1)) { if mask[i] then { @@ -65,11 +65,10 @@ sail(): | } } }; - + write_single_element(SEW, 0, vd, sum); /* other elements in vd are treated as tail elements, currently remain unchanged */ /* TODO: configuration support for agnostic behavior */ vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vredxor.vs.yaml b/arch/inst/V/vredxor.vs.yaml index bf47cb6012..b9500c5acf 100644 --- a/arch/inst/V/vredxor.vs.yaml +++ b/arch/inst/V/vredxor.vs.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -36,20 +36,20 @@ sail(): | let LMUL_pow = get_lmul_pow(); let num_elem_vs = get_num_elem(LMUL_pow, SEW); let num_elem_vd = get_num_elem(0, SEW); /* vd regardless of LMUL setting */ - + if illegal_reduction() then { handle_illegal(); return RETIRE_FAIL }; - + if unsigned(vl) == 0 then return RETIRE_SUCCESS; /* if vl=0, no operation is performed */ - + let 'n = num_elem_vs; let 'd = num_elem_vd; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem_vs, vm, 0b00000); let vd_val : vector('d, dec, bits('m)) = read_vreg(num_elem_vd, SEW, 0, vd); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem_vs, SEW, LMUL_pow, vs2); let mask : vector('n, dec, bool) = init_masked_source(num_elem_vs, LMUL_pow, vm_val); - + sum : bits('m) = read_single_element(SEW, 0, vs1); /* vs1 regardless of LMUL setting */ foreach (i from 0 to (num_elem_vs - 1)) { if mask[i] then { @@ -65,11 +65,10 @@ sail(): | } } }; - + write_single_element(SEW, 0, vd, sum); /* other elements in vd are treated as tail elements, currently remain unchanged */ /* TODO: configuration support for agnostic behavior */ vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vrem.vv.yaml b/arch/inst/V/vrem.vv.yaml index 175ce9362a..54b4458720 100644 --- a/arch/inst/V/vrem.vv.yaml +++ b/arch/inst/V/vrem.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -102,9 +102,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vrem.vx.yaml b/arch/inst/V/vrem.vx.yaml index d04de82d66..976f7a73b8 100644 --- a/arch/inst/V/vrem.vx.yaml +++ b/arch/inst/V/vrem.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -111,9 +111,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vremu.vv.yaml b/arch/inst/V/vremu.vv.yaml index e0f547263e..4262b9e292 100644 --- a/arch/inst/V/vremu.vv.yaml +++ b/arch/inst/V/vremu.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -102,9 +102,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vremu.vx.yaml b/arch/inst/V/vremu.vx.yaml index f187971281..3709f7afc7 100644 --- a/arch/inst/V/vremu.vx.yaml +++ b/arch/inst/V/vremu.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -111,9 +111,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vrgather.vi.yaml b/arch/inst/V/vrgather.vi.yaml index cce4802a6f..8f8c6f157c 100644 --- a/arch/inst/V/vrgather.vi.yaml +++ b/arch/inst/V/vrgather.vi.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,21 +37,21 @@ sail(): | let LMUL_pow = get_lmul_pow(); let VLEN_pow = get_vlen_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let imm_val : nat = unsigned(zero_extend(sizeof(xlen), simm)); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -73,9 +73,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vrgather.vv.yaml b/arch/inst/V/vrgather.vv.yaml index 3b902476ce..17c92e6d44 100644 --- a/arch/inst/V/vrgather.vv.yaml +++ b/arch/inst/V/vrgather.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,21 +37,21 @@ sail(): | let LMUL_pow = get_lmul_pow(); let VLEN_pow = get_vlen_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -120,9 +120,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vrgather.vx.yaml b/arch/inst/V/vrgather.vx.yaml index fef288091c..10763af3b6 100644 --- a/arch/inst/V/vrgather.vx.yaml +++ b/arch/inst/V/vrgather.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,21 +37,21 @@ sail(): | let LMUL_pow = get_lmul_pow(); let VLEN_pow = get_vlen_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : nat = unsigned(X(rs1)); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -73,9 +73,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vrgatherei16.vv.yaml b/arch/inst/V/vrgatherei16.vv.yaml index 6588d9cc93..3edfd3f2b3 100644 --- a/arch/inst/V/vrgatherei16.vv.yaml +++ b/arch/inst/V/vrgatherei16.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,21 +37,21 @@ sail(): | let LMUL_pow = get_lmul_pow(); let VLEN_pow = get_vlen_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -120,9 +120,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vrsub.vi.yaml b/arch/inst/V/vrsub.vi.yaml index c2e1a4fe13..5e369d5e16 100644 --- a/arch/inst/V/vrsub.vi.yaml +++ b/arch/inst/V/vrsub.vi.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let imm_val : bits('m) = sign_extend(simm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -87,9 +87,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vrsub.vx.yaml b/arch/inst/V/vrsub.vx.yaml index 28dc3fd334..2981fdbe07 100644 --- a/arch/inst/V/vrsub.vx.yaml +++ b/arch/inst/V/vrsub.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -103,9 +103,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vs1r.v.yaml b/arch/inst/V/vs1r.v.yaml index 89a88c8237..16af81c2f4 100644 --- a/arch/inst/V/vs1r.v.yaml +++ b/arch/inst/V/vs1r.v.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vs2r.v.yaml b/arch/inst/V/vs2r.v.yaml index 1f8e6a218c..ca01f05fd9 100644 --- a/arch/inst/V/vs2r.v.yaml +++ b/arch/inst/V/vs2r.v.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vs4r.v.yaml b/arch/inst/V/vs4r.v.yaml index 5c2cf8bc23..a035f4cc44 100644 --- a/arch/inst/V/vs4r.v.yaml +++ b/arch/inst/V/vs4r.v.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vs8r.v.yaml b/arch/inst/V/vs8r.v.yaml index 2eb6a086e7..31126a57fe 100644 --- a/arch/inst/V/vs8r.v.yaml +++ b/arch/inst/V/vs8r.v.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsadd.vi.yaml b/arch/inst/V/vsadd.vi.yaml index 0d80780338..59d37d92d3 100644 --- a/arch/inst/V/vsadd.vi.yaml +++ b/arch/inst/V/vsadd.vi.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let imm_val : bits('m) = sign_extend(simm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -87,9 +87,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vsadd.vv.yaml b/arch/inst/V/vsadd.vv.yaml index d293482c70..6a9e51dc6a 100644 --- a/arch/inst/V/vsadd.vv.yaml +++ b/arch/inst/V/vsadd.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,21 +37,21 @@ sail(): | let LMUL_pow = get_lmul_pow(); let VLEN_pow = get_vlen_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -120,9 +120,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vsadd.vx.yaml b/arch/inst/V/vsadd.vx.yaml index cb9ae0d4d9..cd4d2f1f53 100644 --- a/arch/inst/V/vsadd.vx.yaml +++ b/arch/inst/V/vsadd.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -103,9 +103,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vsaddu.vi.yaml b/arch/inst/V/vsaddu.vi.yaml index 5c264d5547..0aac71bce9 100644 --- a/arch/inst/V/vsaddu.vi.yaml +++ b/arch/inst/V/vsaddu.vi.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let imm_val : bits('m) = sign_extend(simm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -87,9 +87,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vsaddu.vv.yaml b/arch/inst/V/vsaddu.vv.yaml index 870e4ab1cd..e2514e2c75 100644 --- a/arch/inst/V/vsaddu.vv.yaml +++ b/arch/inst/V/vsaddu.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,21 +37,21 @@ sail(): | let LMUL_pow = get_lmul_pow(); let VLEN_pow = get_vlen_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -120,9 +120,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vsaddu.vx.yaml b/arch/inst/V/vsaddu.vx.yaml index eb1916e2b2..5cfbc7fc21 100644 --- a/arch/inst/V/vsaddu.vx.yaml +++ b/arch/inst/V/vsaddu.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -103,9 +103,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vsbc.vvm.yaml b/arch/inst/V/vsbc.vvm.yaml index 0ae6c376ba..646653fc54 100644 --- a/arch/inst/V/vsbc.vvm.yaml +++ b/arch/inst/V/vsbc.vvm.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -33,27 +33,27 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_masked(vd) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + /* for bypassing normal masking in init_masked_result */ vec_trues : vector('n, dec, bool) = undefined; foreach (i from 0 to (num_elem - 1)) { vec_trues[i] = true }; - + let vm_val : vector('n, dec, bool) = read_vmask_carry(num_elem, 0b0, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vec_trues); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -62,9 +62,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vsbc.vxm.yaml b/arch/inst/V/vsbc.vxm.yaml index 5731aed41b..f3a6fabcbe 100644 --- a/arch/inst/V/vsbc.vxm.yaml +++ b/arch/inst/V/vsbc.vxm.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -33,27 +33,27 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_vd_masked(vd) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + /* for bypassing normal masking in init_masked_result */ vec_trues : vector('n, dec, bool) = undefined; foreach (i from 0 to (num_elem - 1)) { vec_trues[i] = true }; - + let vm_val : vector('n, dec, bool) = read_vmask_carry(num_elem, 0b0, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vec_trues); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -62,9 +62,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vse16.v.yaml b/arch/inst/V/vse16.v.yaml index dfd3b2b0ab..46f1bef23e 100644 --- a/arch/inst/V/vse16.v.yaml +++ b/arch/inst/V/vse16.v.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,9 +38,8 @@ sail(): | let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; let num_elem = get_num_elem(EMUL_pow, EEW); let nf_int = nfields_int(nf); - + if illegal_store(nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vsseg(nf_int, vm, vs3, load_width_bytes, rs1, EMUL_pow, num_elem) } - diff --git a/arch/inst/V/vse32.v.yaml b/arch/inst/V/vse32.v.yaml index 9e067d782d..9db60760de 100644 --- a/arch/inst/V/vse32.v.yaml +++ b/arch/inst/V/vse32.v.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,9 +38,8 @@ sail(): | let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; let num_elem = get_num_elem(EMUL_pow, EEW); let nf_int = nfields_int(nf); - + if illegal_store(nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vsseg(nf_int, vm, vs3, load_width_bytes, rs1, EMUL_pow, num_elem) } - diff --git a/arch/inst/V/vse64.v.yaml b/arch/inst/V/vse64.v.yaml index 1744b91e1f..3fbfabaedc 100644 --- a/arch/inst/V/vse64.v.yaml +++ b/arch/inst/V/vse64.v.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,9 +38,8 @@ sail(): | let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; let num_elem = get_num_elem(EMUL_pow, EEW); let nf_int = nfields_int(nf); - + if illegal_store(nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vsseg(nf_int, vm, vs3, load_width_bytes, rs1, EMUL_pow, num_elem) } - diff --git a/arch/inst/V/vse8.v.yaml b/arch/inst/V/vse8.v.yaml index fd92238197..b3be72b1e6 100644 --- a/arch/inst/V/vse8.v.yaml +++ b/arch/inst/V/vse8.v.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,9 +38,8 @@ sail(): | let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; let num_elem = get_num_elem(EMUL_pow, EEW); let nf_int = nfields_int(nf); - + if illegal_store(nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vsseg(nf_int, vm, vs3, load_width_bytes, rs1, EMUL_pow, num_elem) } - diff --git a/arch/inst/V/vsetivli.yaml b/arch/inst/V/vsetivli.yaml index f8b35e0b79..623b27b242 100644 --- a/arch/inst/V/vsetivli.yaml +++ b/arch/inst/V/vsetivli.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,10 +35,10 @@ sail(): | let LMUL_pow_ori = get_lmul_pow(); let SEW_pow_ori = get_sew_pow(); let ratio_pow_ori = SEW_pow_ori - LMUL_pow_ori; - + /* set vtype */ vtype->bits() = 0b0 @ zeros(sizeof(xlen) - 9) @ ma @ ta @ sew @ lmul; - + /* check legal SEW and LMUL and calculate VLMAX */ let LMUL_pow_new = get_lmul_pow(); let SEW_pow_new = get_sew_pow(); @@ -54,7 +54,7 @@ sail(): | }; let VLMAX = int_power(2, VLEN_pow + LMUL_pow_new - SEW_pow_new); let AVL = unsigned(uimm); /* AVL is encoded as 5-bit zero-extended imm in the rs1 field */ - + /* set vl according to VLMAX and AVL */ vl = if AVL <= VLMAX then to_bits(sizeof(xlen), AVL) else if AVL < 2 * VLMAX then to_bits(sizeof(xlen), (AVL + 1) / 2) @@ -65,11 +65,10 @@ sail(): | X(rd) = vl; print_reg("CSR vtype <- " ^ BitStr(vtype.bits())); print_reg("CSR vl <- " ^ BitStr(vl)); - + /* reset vstart to 0 */ vstart = zeros(); print_reg("CSR vstart <- " ^ BitStr(vstart)); - + RETIRE_SUCCESS } - diff --git a/arch/inst/V/vsetvl.yaml b/arch/inst/V/vsetvl.yaml index c7341e9da8..a66a6759f4 100644 --- a/arch/inst/V/vsetvl.yaml +++ b/arch/inst/V/vsetvl.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsetvli.yaml b/arch/inst/V/vsetvli.yaml index ad90125f49..93995b7655 100644 --- a/arch/inst/V/vsetvli.yaml +++ b/arch/inst/V/vsetvli.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,7 +35,7 @@ sail(): | let LMUL_pow_ori = get_lmul_pow(); let SEW_pow_ori = get_sew_pow(); let ratio_pow_ori = SEW_pow_ori - LMUL_pow_ori; - + /* set vtype */ match op { VSETVLI => { @@ -46,7 +46,7 @@ sail(): | vtype->bits() = X(rs2) } }; - + /* check legal SEW and LMUL and calculate VLMAX */ let LMUL_pow_new = get_lmul_pow(); let SEW_pow_new = get_sew_pow(); @@ -61,7 +61,7 @@ sail(): | return RETIRE_SUCCESS }; let VLMAX = int_power(2, VLEN_pow + LMUL_pow_new - SEW_pow_new); - + /* set vl according to VLMAX and AVL */ if (rs1 != 0b00000) then { /* normal stripmining */ let rs1_val = X(rs1); @@ -90,14 +90,10 @@ sail(): | }; print_reg("CSR vtype <- " ^ BitStr(vtype.bits())); print_reg("CSR vl <- " ^ BitStr(vl)); - + /* reset vstart to 0 */ vstart = zeros(); print_reg("CSR vstart <- " ^ BitStr(vstart)); - + RETIRE_SUCCESS } - - - - diff --git a/arch/inst/V/vsext.vf2.yaml b/arch/inst/V/vsext.vf2.yaml index e62d410305..2a16a12022 100644 --- a/arch/inst/V/vsext.vf2.yaml +++ b/arch/inst/V/vsext.vf2.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,23 +35,23 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_half = SEW / 2; let LMUL_pow_half = LMUL_pow - 1; - + if illegal_variable_width(vd, vm, SEW_half, LMUL_pow_half) | not(valid_reg_overlap(vs2, vd, LMUL_pow_half, LMUL_pow)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_half; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_half, LMUL_pow_half, vs2); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + assert(SEW > SEW_half); foreach (i from 0 to (num_elem - 1)) { if mask[i] then { @@ -61,9 +61,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vsext.vf4.yaml b/arch/inst/V/vsext.vf4.yaml index 93c595aaea..430cd84aba 100644 --- a/arch/inst/V/vsext.vf4.yaml +++ b/arch/inst/V/vsext.vf4.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,23 +35,23 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_quart = SEW / 4; let LMUL_pow_quart = LMUL_pow - 2; - + if illegal_variable_width(vd, vm, SEW_quart, LMUL_pow_quart) | not(valid_reg_overlap(vs2, vd, LMUL_pow_quart, LMUL_pow)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_quart; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_quart, LMUL_pow_quart, vs2); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + assert(SEW > SEW_quart); foreach (i from 0 to (num_elem - 1)) { if mask[i] then { @@ -61,9 +61,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vsext.vf8.yaml b/arch/inst/V/vsext.vf8.yaml index 14cb8c2222..4c1c171a7d 100644 --- a/arch/inst/V/vsext.vf8.yaml +++ b/arch/inst/V/vsext.vf8.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,23 +35,23 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_eighth = SEW / 8; let LMUL_pow_eighth = LMUL_pow - 3; - + if illegal_variable_width(vd, vm, SEW_eighth, LMUL_pow_eighth) | not(valid_reg_overlap(vs2, vd, LMUL_pow_eighth, LMUL_pow)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_eighth; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_eighth, LMUL_pow_eighth, vs2); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + assert(SEW > SEW_eighth); foreach (i from 0 to (num_elem - 1)) { if mask[i] then { @@ -61,9 +61,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vslide1down.vx.yaml b/arch/inst/V/vslide1down.vx.yaml index 604c111f99..fdf239d02b 100644 --- a/arch/inst/V/vslide1down.vx.yaml +++ b/arch/inst/V/vslide1down.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -111,9 +111,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vslide1up.vx.yaml b/arch/inst/V/vslide1up.vx.yaml index 7879c052cc..12201fa9da 100644 --- a/arch/inst/V/vslide1up.vx.yaml +++ b/arch/inst/V/vslide1up.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -111,9 +111,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vslidedown.vi.yaml b/arch/inst/V/vslidedown.vi.yaml index 2d512fef9e..5253fa5aad 100644 --- a/arch/inst/V/vslidedown.vi.yaml +++ b/arch/inst/V/vslidedown.vi.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,21 +37,21 @@ sail(): | let LMUL_pow = get_lmul_pow(); let VLEN_pow = get_vlen_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let imm_val : nat = unsigned(zero_extend(sizeof(xlen), simm)); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -73,9 +73,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vslidedown.vx.yaml b/arch/inst/V/vslidedown.vx.yaml index 265c9b957b..ed5f7b0669 100644 --- a/arch/inst/V/vslidedown.vx.yaml +++ b/arch/inst/V/vslidedown.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,21 +37,21 @@ sail(): | let LMUL_pow = get_lmul_pow(); let VLEN_pow = get_vlen_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : nat = unsigned(X(rs1)); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -73,9 +73,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vslideup.vi.yaml b/arch/inst/V/vslideup.vi.yaml index 1f21c090c8..cdda8b516b 100644 --- a/arch/inst/V/vslideup.vi.yaml +++ b/arch/inst/V/vslideup.vi.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,21 +37,21 @@ sail(): | let LMUL_pow = get_lmul_pow(); let VLEN_pow = get_vlen_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let imm_val : nat = unsigned(zero_extend(sizeof(xlen), simm)); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -73,9 +73,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vslideup.vx.yaml b/arch/inst/V/vslideup.vx.yaml index 3e7b93e0dd..4ac68fa347 100644 --- a/arch/inst/V/vslideup.vx.yaml +++ b/arch/inst/V/vslideup.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,21 +37,21 @@ sail(): | let LMUL_pow = get_lmul_pow(); let VLEN_pow = get_vlen_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : nat = unsigned(X(rs1)); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -73,9 +73,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vsll.vi.yaml b/arch/inst/V/vsll.vi.yaml index 3365ef202f..317629bf0b 100644 --- a/arch/inst/V/vsll.vi.yaml +++ b/arch/inst/V/vsll.vi.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let imm_val : bits('m) = sign_extend(simm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -87,9 +87,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vsll.vv.yaml b/arch/inst/V/vsll.vv.yaml index d3298a0004..505eb734f7 100644 --- a/arch/inst/V/vsll.vv.yaml +++ b/arch/inst/V/vsll.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,21 +37,21 @@ sail(): | let LMUL_pow = get_lmul_pow(); let VLEN_pow = get_vlen_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -120,9 +120,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vsll.vx.yaml b/arch/inst/V/vsll.vx.yaml index 0cd9cceb54..7f92227356 100644 --- a/arch/inst/V/vsll.vx.yaml +++ b/arch/inst/V/vsll.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -103,9 +103,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vsm.v.yaml b/arch/inst/V/vsm.v.yaml index 4d9ae91406..a50fe111d8 100644 --- a/arch/inst/V/vsm.v.yaml +++ b/arch/inst/V/vsm.v.yaml @@ -22,7 +22,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -33,10 +33,9 @@ sail(): | let vl_val = unsigned(vl); let evl : int = if vl_val % 8 == 0 then vl_val / 8 else vl_val / 8 + 1; /* the effective vector length is evl=ceil(vl/8) */ let num_elem = get_num_elem(EMUL_pow, EEW); - + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - + assert(evl >= 0); process_vm(vd_or_vs3, rs1, num_elem, evl, op) } - diff --git a/arch/inst/V/vsmul.vv.yaml b/arch/inst/V/vsmul.vv.yaml index f920f1bd3c..33a0955db5 100644 --- a/arch/inst/V/vsmul.vv.yaml +++ b/arch/inst/V/vsmul.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,21 +37,21 @@ sail(): | let LMUL_pow = get_lmul_pow(); let VLEN_pow = get_vlen_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -120,9 +120,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vsmul.vx.yaml b/arch/inst/V/vsmul.vx.yaml index e0e1e8c37f..8d76ae1ee6 100644 --- a/arch/inst/V/vsmul.vx.yaml +++ b/arch/inst/V/vsmul.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -103,9 +103,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vsoxei16.v.yaml b/arch/inst/V/vsoxei16.v.yaml index afd40f9c8d..ded610f658 100644 --- a/arch/inst/V/vsoxei16.v.yaml +++ b/arch/inst/V/vsoxei16.v.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -40,9 +40,8 @@ sail(): | let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow; let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); /* number of data and indices are the same */ let nf_int = nfields_int(nf); - + if illegal_indexed_store(nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vsxseg(nf_int, vm, vs3, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 1) } - diff --git a/arch/inst/V/vsoxei32.v.yaml b/arch/inst/V/vsoxei32.v.yaml index 1c95ac6ce1..c66fc7baf3 100644 --- a/arch/inst/V/vsoxei32.v.yaml +++ b/arch/inst/V/vsoxei32.v.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -40,9 +40,8 @@ sail(): | let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow; let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); /* number of data and indices are the same */ let nf_int = nfields_int(nf); - + if illegal_indexed_store(nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vsxseg(nf_int, vm, vs3, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 1) } - diff --git a/arch/inst/V/vsoxei64.v.yaml b/arch/inst/V/vsoxei64.v.yaml index d53f924371..1077b0db43 100644 --- a/arch/inst/V/vsoxei64.v.yaml +++ b/arch/inst/V/vsoxei64.v.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -40,9 +40,8 @@ sail(): | let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow; let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); /* number of data and indices are the same */ let nf_int = nfields_int(nf); - + if illegal_indexed_store(nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vsxseg(nf_int, vm, vs3, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 1) } - diff --git a/arch/inst/V/vsoxei8.v.yaml b/arch/inst/V/vsoxei8.v.yaml index e7aca8d1af..a45891a501 100644 --- a/arch/inst/V/vsoxei8.v.yaml +++ b/arch/inst/V/vsoxei8.v.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -40,9 +40,8 @@ sail(): | let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow; let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); /* number of data and indices are the same */ let nf_int = nfields_int(nf); - + if illegal_indexed_store(nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vsxseg(nf_int, vm, vs3, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 1) } - diff --git a/arch/inst/V/vsoxseg2ei16.v.yaml b/arch/inst/V/vsoxseg2ei16.v.yaml index ac714ab249..e86e45ad30 100644 --- a/arch/inst/V/vsoxseg2ei16.v.yaml +++ b/arch/inst/V/vsoxseg2ei16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsoxseg2ei32.v.yaml b/arch/inst/V/vsoxseg2ei32.v.yaml index 28784077ee..9b45cee7a7 100644 --- a/arch/inst/V/vsoxseg2ei32.v.yaml +++ b/arch/inst/V/vsoxseg2ei32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsoxseg2ei64.v.yaml b/arch/inst/V/vsoxseg2ei64.v.yaml index 5ff3e3093f..95f803fbf3 100644 --- a/arch/inst/V/vsoxseg2ei64.v.yaml +++ b/arch/inst/V/vsoxseg2ei64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsoxseg2ei8.v.yaml b/arch/inst/V/vsoxseg2ei8.v.yaml index f1e6c2b464..4234761a3b 100644 --- a/arch/inst/V/vsoxseg2ei8.v.yaml +++ b/arch/inst/V/vsoxseg2ei8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsoxseg3ei16.v.yaml b/arch/inst/V/vsoxseg3ei16.v.yaml index 779e5b3ff0..fe32adab1f 100644 --- a/arch/inst/V/vsoxseg3ei16.v.yaml +++ b/arch/inst/V/vsoxseg3ei16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsoxseg3ei32.v.yaml b/arch/inst/V/vsoxseg3ei32.v.yaml index ea66ccc72b..3c66f7a410 100644 --- a/arch/inst/V/vsoxseg3ei32.v.yaml +++ b/arch/inst/V/vsoxseg3ei32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsoxseg3ei64.v.yaml b/arch/inst/V/vsoxseg3ei64.v.yaml index bfd6807798..ca20fe8fa8 100644 --- a/arch/inst/V/vsoxseg3ei64.v.yaml +++ b/arch/inst/V/vsoxseg3ei64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsoxseg3ei8.v.yaml b/arch/inst/V/vsoxseg3ei8.v.yaml index f2ed7f2231..4df149f008 100644 --- a/arch/inst/V/vsoxseg3ei8.v.yaml +++ b/arch/inst/V/vsoxseg3ei8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsoxseg4ei16.v.yaml b/arch/inst/V/vsoxseg4ei16.v.yaml index 5621b133a3..9a386ba92f 100644 --- a/arch/inst/V/vsoxseg4ei16.v.yaml +++ b/arch/inst/V/vsoxseg4ei16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsoxseg4ei32.v.yaml b/arch/inst/V/vsoxseg4ei32.v.yaml index 16968f0608..9bf3d9447e 100644 --- a/arch/inst/V/vsoxseg4ei32.v.yaml +++ b/arch/inst/V/vsoxseg4ei32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsoxseg4ei64.v.yaml b/arch/inst/V/vsoxseg4ei64.v.yaml index 04f00844d4..0b1d62d811 100644 --- a/arch/inst/V/vsoxseg4ei64.v.yaml +++ b/arch/inst/V/vsoxseg4ei64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsoxseg4ei8.v.yaml b/arch/inst/V/vsoxseg4ei8.v.yaml index eff7930123..078aa7a6c7 100644 --- a/arch/inst/V/vsoxseg4ei8.v.yaml +++ b/arch/inst/V/vsoxseg4ei8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsoxseg5ei16.v.yaml b/arch/inst/V/vsoxseg5ei16.v.yaml index 3b5d82c7e2..182b82153e 100644 --- a/arch/inst/V/vsoxseg5ei16.v.yaml +++ b/arch/inst/V/vsoxseg5ei16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsoxseg5ei32.v.yaml b/arch/inst/V/vsoxseg5ei32.v.yaml index 6956fd4b80..865cd68d7c 100644 --- a/arch/inst/V/vsoxseg5ei32.v.yaml +++ b/arch/inst/V/vsoxseg5ei32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsoxseg5ei64.v.yaml b/arch/inst/V/vsoxseg5ei64.v.yaml index ad4248d04f..ba7330e7b7 100644 --- a/arch/inst/V/vsoxseg5ei64.v.yaml +++ b/arch/inst/V/vsoxseg5ei64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsoxseg5ei8.v.yaml b/arch/inst/V/vsoxseg5ei8.v.yaml index d0aec1c02c..85dcb2bb9e 100644 --- a/arch/inst/V/vsoxseg5ei8.v.yaml +++ b/arch/inst/V/vsoxseg5ei8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsoxseg6ei16.v.yaml b/arch/inst/V/vsoxseg6ei16.v.yaml index 28ee6c458b..6a4630a843 100644 --- a/arch/inst/V/vsoxseg6ei16.v.yaml +++ b/arch/inst/V/vsoxseg6ei16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsoxseg6ei32.v.yaml b/arch/inst/V/vsoxseg6ei32.v.yaml index c5ba2071a2..1ff23a1325 100644 --- a/arch/inst/V/vsoxseg6ei32.v.yaml +++ b/arch/inst/V/vsoxseg6ei32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsoxseg6ei64.v.yaml b/arch/inst/V/vsoxseg6ei64.v.yaml index 0b10f91333..3ccbd64506 100644 --- a/arch/inst/V/vsoxseg6ei64.v.yaml +++ b/arch/inst/V/vsoxseg6ei64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsoxseg6ei8.v.yaml b/arch/inst/V/vsoxseg6ei8.v.yaml index 17d875acc5..a40cae05f9 100644 --- a/arch/inst/V/vsoxseg6ei8.v.yaml +++ b/arch/inst/V/vsoxseg6ei8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsoxseg7ei16.v.yaml b/arch/inst/V/vsoxseg7ei16.v.yaml index 0206c3b385..f6378ac9ce 100644 --- a/arch/inst/V/vsoxseg7ei16.v.yaml +++ b/arch/inst/V/vsoxseg7ei16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsoxseg7ei32.v.yaml b/arch/inst/V/vsoxseg7ei32.v.yaml index 5e338157e5..3359414cda 100644 --- a/arch/inst/V/vsoxseg7ei32.v.yaml +++ b/arch/inst/V/vsoxseg7ei32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsoxseg7ei64.v.yaml b/arch/inst/V/vsoxseg7ei64.v.yaml index c0e2ef20d1..c92e974315 100644 --- a/arch/inst/V/vsoxseg7ei64.v.yaml +++ b/arch/inst/V/vsoxseg7ei64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsoxseg7ei8.v.yaml b/arch/inst/V/vsoxseg7ei8.v.yaml index b12c9a0799..8be28249c4 100644 --- a/arch/inst/V/vsoxseg7ei8.v.yaml +++ b/arch/inst/V/vsoxseg7ei8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsoxseg8ei16.v.yaml b/arch/inst/V/vsoxseg8ei16.v.yaml index 9dc37142d7..7231e6accb 100644 --- a/arch/inst/V/vsoxseg8ei16.v.yaml +++ b/arch/inst/V/vsoxseg8ei16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsoxseg8ei32.v.yaml b/arch/inst/V/vsoxseg8ei32.v.yaml index 4aa50321d1..f1b306a0f8 100644 --- a/arch/inst/V/vsoxseg8ei32.v.yaml +++ b/arch/inst/V/vsoxseg8ei32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsoxseg8ei64.v.yaml b/arch/inst/V/vsoxseg8ei64.v.yaml index 404ff34a7c..71e1e6404e 100644 --- a/arch/inst/V/vsoxseg8ei64.v.yaml +++ b/arch/inst/V/vsoxseg8ei64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsoxseg8ei8.v.yaml b/arch/inst/V/vsoxseg8ei8.v.yaml index e27be1e85c..f2ae507256 100644 --- a/arch/inst/V/vsoxseg8ei8.v.yaml +++ b/arch/inst/V/vsoxseg8ei8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsra.vi.yaml b/arch/inst/V/vsra.vi.yaml index 0e2ea30cc2..794126b651 100644 --- a/arch/inst/V/vsra.vi.yaml +++ b/arch/inst/V/vsra.vi.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let imm_val : bits('m) = sign_extend(simm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -87,9 +87,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vsra.vv.yaml b/arch/inst/V/vsra.vv.yaml index 5d2d61969e..961684129f 100644 --- a/arch/inst/V/vsra.vv.yaml +++ b/arch/inst/V/vsra.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,21 +37,21 @@ sail(): | let LMUL_pow = get_lmul_pow(); let VLEN_pow = get_vlen_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -120,9 +120,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vsra.vx.yaml b/arch/inst/V/vsra.vx.yaml index f22bc1767f..ce374fd8dc 100644 --- a/arch/inst/V/vsra.vx.yaml +++ b/arch/inst/V/vsra.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -103,9 +103,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vsrl.vi.yaml b/arch/inst/V/vsrl.vi.yaml index 5a3bf199b9..a3186c341e 100644 --- a/arch/inst/V/vsrl.vi.yaml +++ b/arch/inst/V/vsrl.vi.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let imm_val : bits('m) = sign_extend(simm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -87,9 +87,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vsrl.vv.yaml b/arch/inst/V/vsrl.vv.yaml index b4414af0a4..9ab40d6447 100644 --- a/arch/inst/V/vsrl.vv.yaml +++ b/arch/inst/V/vsrl.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,21 +37,21 @@ sail(): | let LMUL_pow = get_lmul_pow(); let VLEN_pow = get_vlen_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -120,9 +120,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vsrl.vx.yaml b/arch/inst/V/vsrl.vx.yaml index 18b4f18377..dc0fc032f8 100644 --- a/arch/inst/V/vsrl.vx.yaml +++ b/arch/inst/V/vsrl.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -103,9 +103,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vsse16.v.yaml b/arch/inst/V/vsse16.v.yaml index d65aa432bb..2bfe4dcd69 100644 --- a/arch/inst/V/vsse16.v.yaml +++ b/arch/inst/V/vsse16.v.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -40,9 +40,8 @@ sail(): | let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; let num_elem = get_num_elem(EMUL_pow, EEW); let nf_int = nfields_int(nf); - + if illegal_store(nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vssseg(nf_int, vm, vs3, load_width_bytes, rs1, rs2, EMUL_pow, num_elem) } - diff --git a/arch/inst/V/vsse32.v.yaml b/arch/inst/V/vsse32.v.yaml index 782458d9ba..3f543d07eb 100644 --- a/arch/inst/V/vsse32.v.yaml +++ b/arch/inst/V/vsse32.v.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -40,9 +40,8 @@ sail(): | let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; let num_elem = get_num_elem(EMUL_pow, EEW); let nf_int = nfields_int(nf); - + if illegal_store(nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vssseg(nf_int, vm, vs3, load_width_bytes, rs1, rs2, EMUL_pow, num_elem) } - diff --git a/arch/inst/V/vsse64.v.yaml b/arch/inst/V/vsse64.v.yaml index 8184877628..dbfba21610 100644 --- a/arch/inst/V/vsse64.v.yaml +++ b/arch/inst/V/vsse64.v.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -40,9 +40,8 @@ sail(): | let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; let num_elem = get_num_elem(EMUL_pow, EEW); let nf_int = nfields_int(nf); - + if illegal_store(nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vssseg(nf_int, vm, vs3, load_width_bytes, rs1, rs2, EMUL_pow, num_elem) } - diff --git a/arch/inst/V/vsse8.v.yaml b/arch/inst/V/vsse8.v.yaml index 262c0bf443..66257c58e0 100644 --- a/arch/inst/V/vsse8.v.yaml +++ b/arch/inst/V/vsse8.v.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -40,9 +40,8 @@ sail(): | let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; let num_elem = get_num_elem(EMUL_pow, EEW); let nf_int = nfields_int(nf); - + if illegal_store(nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vssseg(nf_int, vm, vs3, load_width_bytes, rs1, rs2, EMUL_pow, num_elem) } - diff --git a/arch/inst/V/vsseg2e16.v.yaml b/arch/inst/V/vsseg2e16.v.yaml index 6fcf055677..cd4e5be9da 100644 --- a/arch/inst/V/vsseg2e16.v.yaml +++ b/arch/inst/V/vsseg2e16.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsseg2e32.v.yaml b/arch/inst/V/vsseg2e32.v.yaml index 857a1c32c8..601e3b9944 100644 --- a/arch/inst/V/vsseg2e32.v.yaml +++ b/arch/inst/V/vsseg2e32.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsseg2e64.v.yaml b/arch/inst/V/vsseg2e64.v.yaml index ed0d637b32..62ed3f80d3 100644 --- a/arch/inst/V/vsseg2e64.v.yaml +++ b/arch/inst/V/vsseg2e64.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsseg2e8.v.yaml b/arch/inst/V/vsseg2e8.v.yaml index 6e6b747610..e66d94ecb4 100644 --- a/arch/inst/V/vsseg2e8.v.yaml +++ b/arch/inst/V/vsseg2e8.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsseg3e16.v.yaml b/arch/inst/V/vsseg3e16.v.yaml index 9c65966107..ffde8ab7e8 100644 --- a/arch/inst/V/vsseg3e16.v.yaml +++ b/arch/inst/V/vsseg3e16.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsseg3e32.v.yaml b/arch/inst/V/vsseg3e32.v.yaml index d67eeb0eb3..68e204cc68 100644 --- a/arch/inst/V/vsseg3e32.v.yaml +++ b/arch/inst/V/vsseg3e32.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsseg3e64.v.yaml b/arch/inst/V/vsseg3e64.v.yaml index 4d0506f000..f32e623f2b 100644 --- a/arch/inst/V/vsseg3e64.v.yaml +++ b/arch/inst/V/vsseg3e64.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsseg3e8.v.yaml b/arch/inst/V/vsseg3e8.v.yaml index b2c604e67a..4816d14c4e 100644 --- a/arch/inst/V/vsseg3e8.v.yaml +++ b/arch/inst/V/vsseg3e8.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsseg4e16.v.yaml b/arch/inst/V/vsseg4e16.v.yaml index aaa25044d6..538a9b67df 100644 --- a/arch/inst/V/vsseg4e16.v.yaml +++ b/arch/inst/V/vsseg4e16.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsseg4e32.v.yaml b/arch/inst/V/vsseg4e32.v.yaml index b1c3ca1a9a..41b149778a 100644 --- a/arch/inst/V/vsseg4e32.v.yaml +++ b/arch/inst/V/vsseg4e32.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsseg4e64.v.yaml b/arch/inst/V/vsseg4e64.v.yaml index d15d70a4f1..6203e10869 100644 --- a/arch/inst/V/vsseg4e64.v.yaml +++ b/arch/inst/V/vsseg4e64.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsseg4e8.v.yaml b/arch/inst/V/vsseg4e8.v.yaml index 2daa992505..2514dfdbed 100644 --- a/arch/inst/V/vsseg4e8.v.yaml +++ b/arch/inst/V/vsseg4e8.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsseg5e16.v.yaml b/arch/inst/V/vsseg5e16.v.yaml index cc5f8611fb..100f59fbfa 100644 --- a/arch/inst/V/vsseg5e16.v.yaml +++ b/arch/inst/V/vsseg5e16.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsseg5e32.v.yaml b/arch/inst/V/vsseg5e32.v.yaml index a9e9df1c0e..ad3a2cb19f 100644 --- a/arch/inst/V/vsseg5e32.v.yaml +++ b/arch/inst/V/vsseg5e32.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsseg5e64.v.yaml b/arch/inst/V/vsseg5e64.v.yaml index 7f43ce73e8..ff071f25cf 100644 --- a/arch/inst/V/vsseg5e64.v.yaml +++ b/arch/inst/V/vsseg5e64.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsseg5e8.v.yaml b/arch/inst/V/vsseg5e8.v.yaml index aa3a30a971..fda9c36a02 100644 --- a/arch/inst/V/vsseg5e8.v.yaml +++ b/arch/inst/V/vsseg5e8.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsseg6e16.v.yaml b/arch/inst/V/vsseg6e16.v.yaml index a4b52768a6..4b2e5983e5 100644 --- a/arch/inst/V/vsseg6e16.v.yaml +++ b/arch/inst/V/vsseg6e16.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsseg6e32.v.yaml b/arch/inst/V/vsseg6e32.v.yaml index c52e48bd0b..1d08c1db38 100644 --- a/arch/inst/V/vsseg6e32.v.yaml +++ b/arch/inst/V/vsseg6e32.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsseg6e64.v.yaml b/arch/inst/V/vsseg6e64.v.yaml index 3b8da09140..a267cb199a 100644 --- a/arch/inst/V/vsseg6e64.v.yaml +++ b/arch/inst/V/vsseg6e64.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsseg6e8.v.yaml b/arch/inst/V/vsseg6e8.v.yaml index b9ba9d4720..b5e3a702de 100644 --- a/arch/inst/V/vsseg6e8.v.yaml +++ b/arch/inst/V/vsseg6e8.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsseg7e16.v.yaml b/arch/inst/V/vsseg7e16.v.yaml index 9c10d52f67..e0220080a5 100644 --- a/arch/inst/V/vsseg7e16.v.yaml +++ b/arch/inst/V/vsseg7e16.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsseg7e32.v.yaml b/arch/inst/V/vsseg7e32.v.yaml index 7167a70dcd..3a6a885287 100644 --- a/arch/inst/V/vsseg7e32.v.yaml +++ b/arch/inst/V/vsseg7e32.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsseg7e64.v.yaml b/arch/inst/V/vsseg7e64.v.yaml index 6872cf1e34..b2935f7d66 100644 --- a/arch/inst/V/vsseg7e64.v.yaml +++ b/arch/inst/V/vsseg7e64.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsseg7e8.v.yaml b/arch/inst/V/vsseg7e8.v.yaml index 30772c55bd..1851b32c22 100644 --- a/arch/inst/V/vsseg7e8.v.yaml +++ b/arch/inst/V/vsseg7e8.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsseg8e16.v.yaml b/arch/inst/V/vsseg8e16.v.yaml index 84a60a143e..65e45fad95 100644 --- a/arch/inst/V/vsseg8e16.v.yaml +++ b/arch/inst/V/vsseg8e16.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsseg8e32.v.yaml b/arch/inst/V/vsseg8e32.v.yaml index 82924389fd..46bc8e9c73 100644 --- a/arch/inst/V/vsseg8e32.v.yaml +++ b/arch/inst/V/vsseg8e32.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsseg8e64.v.yaml b/arch/inst/V/vsseg8e64.v.yaml index 84df8f1040..736480a8cc 100644 --- a/arch/inst/V/vsseg8e64.v.yaml +++ b/arch/inst/V/vsseg8e64.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsseg8e8.v.yaml b/arch/inst/V/vsseg8e8.v.yaml index 86947bdb89..3903f33c79 100644 --- a/arch/inst/V/vsseg8e8.v.yaml +++ b/arch/inst/V/vsseg8e8.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vssra.vi.yaml b/arch/inst/V/vssra.vi.yaml index 0c662c4501..d89c9d999e 100644 --- a/arch/inst/V/vssra.vi.yaml +++ b/arch/inst/V/vssra.vi.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let imm_val : bits('m) = sign_extend(simm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -87,9 +87,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vssra.vv.yaml b/arch/inst/V/vssra.vv.yaml index 7ff2e9f96e..7b8f6aa474 100644 --- a/arch/inst/V/vssra.vv.yaml +++ b/arch/inst/V/vssra.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,21 +37,21 @@ sail(): | let LMUL_pow = get_lmul_pow(); let VLEN_pow = get_vlen_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -120,9 +120,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vssra.vx.yaml b/arch/inst/V/vssra.vx.yaml index 0de7ada823..24f3e58212 100644 --- a/arch/inst/V/vssra.vx.yaml +++ b/arch/inst/V/vssra.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -103,9 +103,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vssrl.vi.yaml b/arch/inst/V/vssrl.vi.yaml index f95b0e46e7..c763b4663e 100644 --- a/arch/inst/V/vssrl.vi.yaml +++ b/arch/inst/V/vssrl.vi.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let imm_val : bits('m) = sign_extend(simm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -87,9 +87,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vssrl.vv.yaml b/arch/inst/V/vssrl.vv.yaml index 7ee05c89ce..abc1547ff7 100644 --- a/arch/inst/V/vssrl.vv.yaml +++ b/arch/inst/V/vssrl.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,21 +37,21 @@ sail(): | let LMUL_pow = get_lmul_pow(); let VLEN_pow = get_vlen_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -120,9 +120,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vssrl.vx.yaml b/arch/inst/V/vssrl.vx.yaml index 34f7ea8ae6..b5f8e4d92d 100644 --- a/arch/inst/V/vssrl.vx.yaml +++ b/arch/inst/V/vssrl.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -103,9 +103,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vssseg2e16.v.yaml b/arch/inst/V/vssseg2e16.v.yaml index 3b1e6560cc..66ef1a90a7 100644 --- a/arch/inst/V/vssseg2e16.v.yaml +++ b/arch/inst/V/vssseg2e16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vssseg2e32.v.yaml b/arch/inst/V/vssseg2e32.v.yaml index 0682979317..e562929f30 100644 --- a/arch/inst/V/vssseg2e32.v.yaml +++ b/arch/inst/V/vssseg2e32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vssseg2e64.v.yaml b/arch/inst/V/vssseg2e64.v.yaml index 17af81de8d..a6914aa38e 100644 --- a/arch/inst/V/vssseg2e64.v.yaml +++ b/arch/inst/V/vssseg2e64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vssseg2e8.v.yaml b/arch/inst/V/vssseg2e8.v.yaml index 3f0c872a9a..8f70c16480 100644 --- a/arch/inst/V/vssseg2e8.v.yaml +++ b/arch/inst/V/vssseg2e8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vssseg3e16.v.yaml b/arch/inst/V/vssseg3e16.v.yaml index a2be5743f3..94d3a04196 100644 --- a/arch/inst/V/vssseg3e16.v.yaml +++ b/arch/inst/V/vssseg3e16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vssseg3e32.v.yaml b/arch/inst/V/vssseg3e32.v.yaml index c23e342eee..16a6827d1d 100644 --- a/arch/inst/V/vssseg3e32.v.yaml +++ b/arch/inst/V/vssseg3e32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vssseg3e64.v.yaml b/arch/inst/V/vssseg3e64.v.yaml index e42be34ada..2808af060c 100644 --- a/arch/inst/V/vssseg3e64.v.yaml +++ b/arch/inst/V/vssseg3e64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vssseg3e8.v.yaml b/arch/inst/V/vssseg3e8.v.yaml index 5ba1cabddc..0a19eeefd5 100644 --- a/arch/inst/V/vssseg3e8.v.yaml +++ b/arch/inst/V/vssseg3e8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vssseg4e16.v.yaml b/arch/inst/V/vssseg4e16.v.yaml index 2dcf2c097c..01bce54ccf 100644 --- a/arch/inst/V/vssseg4e16.v.yaml +++ b/arch/inst/V/vssseg4e16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vssseg4e32.v.yaml b/arch/inst/V/vssseg4e32.v.yaml index 9152f5384c..f506f43e24 100644 --- a/arch/inst/V/vssseg4e32.v.yaml +++ b/arch/inst/V/vssseg4e32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vssseg4e64.v.yaml b/arch/inst/V/vssseg4e64.v.yaml index 4f109fc9a1..f4206f314d 100644 --- a/arch/inst/V/vssseg4e64.v.yaml +++ b/arch/inst/V/vssseg4e64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vssseg4e8.v.yaml b/arch/inst/V/vssseg4e8.v.yaml index 73145dbdbd..ca7215e3b1 100644 --- a/arch/inst/V/vssseg4e8.v.yaml +++ b/arch/inst/V/vssseg4e8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vssseg5e16.v.yaml b/arch/inst/V/vssseg5e16.v.yaml index e050b894f4..8762c52abf 100644 --- a/arch/inst/V/vssseg5e16.v.yaml +++ b/arch/inst/V/vssseg5e16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vssseg5e32.v.yaml b/arch/inst/V/vssseg5e32.v.yaml index c380333f87..973965755b 100644 --- a/arch/inst/V/vssseg5e32.v.yaml +++ b/arch/inst/V/vssseg5e32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vssseg5e64.v.yaml b/arch/inst/V/vssseg5e64.v.yaml index 9c0013b3f4..043883ad7b 100644 --- a/arch/inst/V/vssseg5e64.v.yaml +++ b/arch/inst/V/vssseg5e64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vssseg5e8.v.yaml b/arch/inst/V/vssseg5e8.v.yaml index 368b767df5..2897b4d342 100644 --- a/arch/inst/V/vssseg5e8.v.yaml +++ b/arch/inst/V/vssseg5e8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vssseg6e16.v.yaml b/arch/inst/V/vssseg6e16.v.yaml index 88d3e887d0..b28278b126 100644 --- a/arch/inst/V/vssseg6e16.v.yaml +++ b/arch/inst/V/vssseg6e16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vssseg6e32.v.yaml b/arch/inst/V/vssseg6e32.v.yaml index 443a44bb65..81bceee89b 100644 --- a/arch/inst/V/vssseg6e32.v.yaml +++ b/arch/inst/V/vssseg6e32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vssseg6e64.v.yaml b/arch/inst/V/vssseg6e64.v.yaml index 316883effd..aa96b349b1 100644 --- a/arch/inst/V/vssseg6e64.v.yaml +++ b/arch/inst/V/vssseg6e64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vssseg6e8.v.yaml b/arch/inst/V/vssseg6e8.v.yaml index 6421447d9d..893688b919 100644 --- a/arch/inst/V/vssseg6e8.v.yaml +++ b/arch/inst/V/vssseg6e8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vssseg7e16.v.yaml b/arch/inst/V/vssseg7e16.v.yaml index 3779098009..4a29f6b368 100644 --- a/arch/inst/V/vssseg7e16.v.yaml +++ b/arch/inst/V/vssseg7e16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vssseg7e32.v.yaml b/arch/inst/V/vssseg7e32.v.yaml index faaa0b21d7..9a1c17897f 100644 --- a/arch/inst/V/vssseg7e32.v.yaml +++ b/arch/inst/V/vssseg7e32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vssseg7e64.v.yaml b/arch/inst/V/vssseg7e64.v.yaml index 5721de1cc7..682f8ed2ba 100644 --- a/arch/inst/V/vssseg7e64.v.yaml +++ b/arch/inst/V/vssseg7e64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vssseg7e8.v.yaml b/arch/inst/V/vssseg7e8.v.yaml index 4661484025..5be77062c2 100644 --- a/arch/inst/V/vssseg7e8.v.yaml +++ b/arch/inst/V/vssseg7e8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vssseg8e16.v.yaml b/arch/inst/V/vssseg8e16.v.yaml index fe68e03f6b..bd3acecbbb 100644 --- a/arch/inst/V/vssseg8e16.v.yaml +++ b/arch/inst/V/vssseg8e16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vssseg8e32.v.yaml b/arch/inst/V/vssseg8e32.v.yaml index 41ced6eefb..3e43ac8e46 100644 --- a/arch/inst/V/vssseg8e32.v.yaml +++ b/arch/inst/V/vssseg8e32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vssseg8e64.v.yaml b/arch/inst/V/vssseg8e64.v.yaml index 3792410a37..ce587b8a63 100644 --- a/arch/inst/V/vssseg8e64.v.yaml +++ b/arch/inst/V/vssseg8e64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vssseg8e8.v.yaml b/arch/inst/V/vssseg8e8.v.yaml index c938f64443..733f17a9c2 100644 --- a/arch/inst/V/vssseg8e8.v.yaml +++ b/arch/inst/V/vssseg8e8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vssub.vv.yaml b/arch/inst/V/vssub.vv.yaml index f714c68950..fe57f480c5 100644 --- a/arch/inst/V/vssub.vv.yaml +++ b/arch/inst/V/vssub.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,21 +37,21 @@ sail(): | let LMUL_pow = get_lmul_pow(); let VLEN_pow = get_vlen_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -120,9 +120,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vssub.vx.yaml b/arch/inst/V/vssub.vx.yaml index 2e0e0e36b9..ea715dcbd5 100644 --- a/arch/inst/V/vssub.vx.yaml +++ b/arch/inst/V/vssub.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -103,9 +103,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vssubu.vv.yaml b/arch/inst/V/vssubu.vv.yaml index 9f65cded26..d74a1bbd0f 100644 --- a/arch/inst/V/vssubu.vv.yaml +++ b/arch/inst/V/vssubu.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,21 +37,21 @@ sail(): | let LMUL_pow = get_lmul_pow(); let VLEN_pow = get_vlen_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -120,9 +120,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vssubu.vx.yaml b/arch/inst/V/vssubu.vx.yaml index 81e4d6b05b..b810030a69 100644 --- a/arch/inst/V/vssubu.vx.yaml +++ b/arch/inst/V/vssubu.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -103,9 +103,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vsub.vv.yaml b/arch/inst/V/vsub.vv.yaml index a257e86d59..9df0336ee5 100644 --- a/arch/inst/V/vsub.vv.yaml +++ b/arch/inst/V/vsub.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,21 +37,21 @@ sail(): | let LMUL_pow = get_lmul_pow(); let VLEN_pow = get_vlen_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -120,9 +120,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vsub.vx.yaml b/arch/inst/V/vsub.vx.yaml index 193e7408de..64b3190444 100644 --- a/arch/inst/V/vsub.vx.yaml +++ b/arch/inst/V/vsub.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -103,9 +103,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vsuxei16.v.yaml b/arch/inst/V/vsuxei16.v.yaml index c9f0b53887..11de9a7e33 100644 --- a/arch/inst/V/vsuxei16.v.yaml +++ b/arch/inst/V/vsuxei16.v.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -40,9 +40,8 @@ sail(): | let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow; let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); /* number of data and indices are the same */ let nf_int = nfields_int(nf); - + if illegal_indexed_store(nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vsxseg(nf_int, vm, vs3, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 1) } - diff --git a/arch/inst/V/vsuxei32.v.yaml b/arch/inst/V/vsuxei32.v.yaml index 07c6bc5a87..8e2587fa38 100644 --- a/arch/inst/V/vsuxei32.v.yaml +++ b/arch/inst/V/vsuxei32.v.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -40,9 +40,8 @@ sail(): | let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow; let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); /* number of data and indices are the same */ let nf_int = nfields_int(nf); - + if illegal_indexed_store(nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vsxseg(nf_int, vm, vs3, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 1) } - diff --git a/arch/inst/V/vsuxei64.v.yaml b/arch/inst/V/vsuxei64.v.yaml index 15a59cbc45..690030d766 100644 --- a/arch/inst/V/vsuxei64.v.yaml +++ b/arch/inst/V/vsuxei64.v.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -40,9 +40,8 @@ sail(): | let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow; let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); /* number of data and indices are the same */ let nf_int = nfields_int(nf); - + if illegal_indexed_store(nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vsxseg(nf_int, vm, vs3, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 1) } - diff --git a/arch/inst/V/vsuxei8.v.yaml b/arch/inst/V/vsuxei8.v.yaml index 717c6f4fca..26fd5fd07a 100644 --- a/arch/inst/V/vsuxei8.v.yaml +++ b/arch/inst/V/vsuxei8.v.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -40,9 +40,8 @@ sail(): | let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow; let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); /* number of data and indices are the same */ let nf_int = nfields_int(nf); - + if illegal_indexed_store(nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL }; - + process_vsxseg(nf_int, vm, vs3, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 1) } - diff --git a/arch/inst/V/vsuxseg2ei16.v.yaml b/arch/inst/V/vsuxseg2ei16.v.yaml index c87cde8601..c6dd0cc861 100644 --- a/arch/inst/V/vsuxseg2ei16.v.yaml +++ b/arch/inst/V/vsuxseg2ei16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsuxseg2ei32.v.yaml b/arch/inst/V/vsuxseg2ei32.v.yaml index 6a4aabb4d0..29c9586941 100644 --- a/arch/inst/V/vsuxseg2ei32.v.yaml +++ b/arch/inst/V/vsuxseg2ei32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsuxseg2ei64.v.yaml b/arch/inst/V/vsuxseg2ei64.v.yaml index 5e08c3e73e..1004b04004 100644 --- a/arch/inst/V/vsuxseg2ei64.v.yaml +++ b/arch/inst/V/vsuxseg2ei64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsuxseg2ei8.v.yaml b/arch/inst/V/vsuxseg2ei8.v.yaml index de8bb55516..d17af839eb 100644 --- a/arch/inst/V/vsuxseg2ei8.v.yaml +++ b/arch/inst/V/vsuxseg2ei8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsuxseg3ei16.v.yaml b/arch/inst/V/vsuxseg3ei16.v.yaml index 160f074ea7..f996907a8b 100644 --- a/arch/inst/V/vsuxseg3ei16.v.yaml +++ b/arch/inst/V/vsuxseg3ei16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsuxseg3ei32.v.yaml b/arch/inst/V/vsuxseg3ei32.v.yaml index 3c951c9c27..fa693dce22 100644 --- a/arch/inst/V/vsuxseg3ei32.v.yaml +++ b/arch/inst/V/vsuxseg3ei32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsuxseg3ei64.v.yaml b/arch/inst/V/vsuxseg3ei64.v.yaml index 44e633dfd4..9402fb997a 100644 --- a/arch/inst/V/vsuxseg3ei64.v.yaml +++ b/arch/inst/V/vsuxseg3ei64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsuxseg3ei8.v.yaml b/arch/inst/V/vsuxseg3ei8.v.yaml index d4131bea18..a6df381933 100644 --- a/arch/inst/V/vsuxseg3ei8.v.yaml +++ b/arch/inst/V/vsuxseg3ei8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsuxseg4ei16.v.yaml b/arch/inst/V/vsuxseg4ei16.v.yaml index 5a23914244..bf4d87142a 100644 --- a/arch/inst/V/vsuxseg4ei16.v.yaml +++ b/arch/inst/V/vsuxseg4ei16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsuxseg4ei32.v.yaml b/arch/inst/V/vsuxseg4ei32.v.yaml index de1b0e8203..c730eff6c0 100644 --- a/arch/inst/V/vsuxseg4ei32.v.yaml +++ b/arch/inst/V/vsuxseg4ei32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsuxseg4ei64.v.yaml b/arch/inst/V/vsuxseg4ei64.v.yaml index c1c358f120..c263a3317e 100644 --- a/arch/inst/V/vsuxseg4ei64.v.yaml +++ b/arch/inst/V/vsuxseg4ei64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsuxseg4ei8.v.yaml b/arch/inst/V/vsuxseg4ei8.v.yaml index a69f3e9e4d..64bbffc451 100644 --- a/arch/inst/V/vsuxseg4ei8.v.yaml +++ b/arch/inst/V/vsuxseg4ei8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsuxseg5ei16.v.yaml b/arch/inst/V/vsuxseg5ei16.v.yaml index d151e28a46..6b7ac97eac 100644 --- a/arch/inst/V/vsuxseg5ei16.v.yaml +++ b/arch/inst/V/vsuxseg5ei16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsuxseg5ei32.v.yaml b/arch/inst/V/vsuxseg5ei32.v.yaml index 81abe68b2a..a5afbb5972 100644 --- a/arch/inst/V/vsuxseg5ei32.v.yaml +++ b/arch/inst/V/vsuxseg5ei32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsuxseg5ei64.v.yaml b/arch/inst/V/vsuxseg5ei64.v.yaml index 266d105129..a4c7a1e509 100644 --- a/arch/inst/V/vsuxseg5ei64.v.yaml +++ b/arch/inst/V/vsuxseg5ei64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsuxseg5ei8.v.yaml b/arch/inst/V/vsuxseg5ei8.v.yaml index 522b019a43..4e3fa113bc 100644 --- a/arch/inst/V/vsuxseg5ei8.v.yaml +++ b/arch/inst/V/vsuxseg5ei8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsuxseg6ei16.v.yaml b/arch/inst/V/vsuxseg6ei16.v.yaml index 2d29c3d2d7..480cefc65f 100644 --- a/arch/inst/V/vsuxseg6ei16.v.yaml +++ b/arch/inst/V/vsuxseg6ei16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsuxseg6ei32.v.yaml b/arch/inst/V/vsuxseg6ei32.v.yaml index 3f52d6f71a..f504d7402b 100644 --- a/arch/inst/V/vsuxseg6ei32.v.yaml +++ b/arch/inst/V/vsuxseg6ei32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsuxseg6ei64.v.yaml b/arch/inst/V/vsuxseg6ei64.v.yaml index 9da3f96c5f..3dc2a966e8 100644 --- a/arch/inst/V/vsuxseg6ei64.v.yaml +++ b/arch/inst/V/vsuxseg6ei64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsuxseg6ei8.v.yaml b/arch/inst/V/vsuxseg6ei8.v.yaml index a2d74f76c3..2755d986b5 100644 --- a/arch/inst/V/vsuxseg6ei8.v.yaml +++ b/arch/inst/V/vsuxseg6ei8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsuxseg7ei16.v.yaml b/arch/inst/V/vsuxseg7ei16.v.yaml index aaf2ae9801..b741b04f40 100644 --- a/arch/inst/V/vsuxseg7ei16.v.yaml +++ b/arch/inst/V/vsuxseg7ei16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsuxseg7ei32.v.yaml b/arch/inst/V/vsuxseg7ei32.v.yaml index 0aa35c1093..49ae744ff3 100644 --- a/arch/inst/V/vsuxseg7ei32.v.yaml +++ b/arch/inst/V/vsuxseg7ei32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsuxseg7ei64.v.yaml b/arch/inst/V/vsuxseg7ei64.v.yaml index da607c1c34..eb7b21ba38 100644 --- a/arch/inst/V/vsuxseg7ei64.v.yaml +++ b/arch/inst/V/vsuxseg7ei64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsuxseg7ei8.v.yaml b/arch/inst/V/vsuxseg7ei8.v.yaml index 003994175c..dd52ac3d75 100644 --- a/arch/inst/V/vsuxseg7ei8.v.yaml +++ b/arch/inst/V/vsuxseg7ei8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsuxseg8ei16.v.yaml b/arch/inst/V/vsuxseg8ei16.v.yaml index d9894ceb28..ed979fec2c 100644 --- a/arch/inst/V/vsuxseg8ei16.v.yaml +++ b/arch/inst/V/vsuxseg8ei16.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsuxseg8ei32.v.yaml b/arch/inst/V/vsuxseg8ei32.v.yaml index bfbe6a963e..5ac1dcab0a 100644 --- a/arch/inst/V/vsuxseg8ei32.v.yaml +++ b/arch/inst/V/vsuxseg8ei32.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsuxseg8ei64.v.yaml b/arch/inst/V/vsuxseg8ei64.v.yaml index c7e171677a..f7dc31b9ea 100644 --- a/arch/inst/V/vsuxseg8ei64.v.yaml +++ b/arch/inst/V/vsuxseg8ei64.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vsuxseg8ei8.v.yaml b/arch/inst/V/vsuxseg8ei8.v.yaml index 225b9ce8b9..2099cd741b 100644 --- a/arch/inst/V/vsuxseg8ei8.v.yaml +++ b/arch/inst/V/vsuxseg8ei8.v.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/V/vwadd.vv.yaml b/arch/inst/V/vwadd.vv.yaml index 3b237223ef..0203707309 100644 --- a/arch/inst/V/vwadd.vv.yaml +++ b/arch/inst/V/vwadd.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,25 +37,25 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -69,9 +69,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwadd.vx.yaml b/arch/inst/V/vwadd.vx.yaml index ed73789835..010532791a 100644 --- a/arch/inst/V/vwadd.vx.yaml +++ b/arch/inst/V/vwadd.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,24 +37,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -68,9 +68,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwadd.wv.yaml b/arch/inst/V/vwadd.wv.yaml index 035b427550..a6a851919a 100644 --- a/arch/inst/V/vwadd.wv.yaml +++ b/arch/inst/V/vwadd.wv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,24 +37,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -65,9 +65,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwadd.wx.yaml b/arch/inst/V/vwadd.wx.yaml index 07a880ebe1..fd78c086a7 100644 --- a/arch/inst/V/vwadd.wx.yaml +++ b/arch/inst/V/vwadd.wx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,23 +37,23 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -64,9 +64,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwaddu.vv.yaml b/arch/inst/V/vwaddu.vv.yaml index e2c3933611..e0e0e20ab2 100644 --- a/arch/inst/V/vwaddu.vv.yaml +++ b/arch/inst/V/vwaddu.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,25 +37,25 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -69,9 +69,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwaddu.vx.yaml b/arch/inst/V/vwaddu.vx.yaml index cf58098a23..87870e44e9 100644 --- a/arch/inst/V/vwaddu.vx.yaml +++ b/arch/inst/V/vwaddu.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,24 +37,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -68,9 +68,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwaddu.wv.yaml b/arch/inst/V/vwaddu.wv.yaml index 198b61f010..799fd3761d 100644 --- a/arch/inst/V/vwaddu.wv.yaml +++ b/arch/inst/V/vwaddu.wv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,24 +37,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -65,9 +65,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwaddu.wx.yaml b/arch/inst/V/vwaddu.wx.yaml index 8eb165cdd5..8719530b10 100644 --- a/arch/inst/V/vwaddu.wx.yaml +++ b/arch/inst/V/vwaddu.wx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,23 +37,23 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -64,9 +64,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwmacc.vv.yaml b/arch/inst/V/vwmacc.vv.yaml index 5d41ec9a8e..78246982d7 100644 --- a/arch/inst/V/vwmacc.vv.yaml +++ b/arch/inst/V/vwmacc.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,25 +37,25 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -65,9 +65,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwmacc.vx.yaml b/arch/inst/V/vwmacc.vx.yaml index 8f1e04ea9e..1faf42a624 100644 --- a/arch/inst/V/vwmacc.vx.yaml +++ b/arch/inst/V/vwmacc.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,24 +37,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -65,9 +65,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwmaccsu.vv.yaml b/arch/inst/V/vwmaccsu.vv.yaml index a635909f9b..347cc21ffb 100644 --- a/arch/inst/V/vwmaccsu.vv.yaml +++ b/arch/inst/V/vwmaccsu.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,25 +37,25 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -65,9 +65,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwmaccsu.vx.yaml b/arch/inst/V/vwmaccsu.vx.yaml index 36901bbaca..bbb92960c2 100644 --- a/arch/inst/V/vwmaccsu.vx.yaml +++ b/arch/inst/V/vwmaccsu.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,24 +37,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -65,9 +65,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwmaccu.vv.yaml b/arch/inst/V/vwmaccu.vv.yaml index 57612798b2..6b2d0406c4 100644 --- a/arch/inst/V/vwmaccu.vv.yaml +++ b/arch/inst/V/vwmaccu.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,25 +37,25 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -65,9 +65,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwmaccu.vx.yaml b/arch/inst/V/vwmaccu.vx.yaml index edf1449086..0e3537eeeb 100644 --- a/arch/inst/V/vwmaccu.vx.yaml +++ b/arch/inst/V/vwmaccu.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,24 +37,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -65,9 +65,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwmaccus.vx.yaml b/arch/inst/V/vwmaccus.vx.yaml index 0e30709299..1704aace52 100644 --- a/arch/inst/V/vwmaccus.vx.yaml +++ b/arch/inst/V/vwmaccus.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,24 +37,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -65,9 +65,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwmul.vv.yaml b/arch/inst/V/vwmul.vv.yaml index a32fda5df2..88ffd777c9 100644 --- a/arch/inst/V/vwmul.vv.yaml +++ b/arch/inst/V/vwmul.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,25 +37,25 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -69,9 +69,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwmul.vx.yaml b/arch/inst/V/vwmul.vx.yaml index 5dc3c3d254..56b2fdf908 100644 --- a/arch/inst/V/vwmul.vx.yaml +++ b/arch/inst/V/vwmul.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,24 +37,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -68,9 +68,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwmulsu.vv.yaml b/arch/inst/V/vwmulsu.vv.yaml index d7ee5d18dc..32a53d3af9 100644 --- a/arch/inst/V/vwmulsu.vv.yaml +++ b/arch/inst/V/vwmulsu.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,25 +37,25 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -69,9 +69,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwmulsu.vx.yaml b/arch/inst/V/vwmulsu.vx.yaml index 4bc0ea6f9f..6d8b53e9bb 100644 --- a/arch/inst/V/vwmulsu.vx.yaml +++ b/arch/inst/V/vwmulsu.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,24 +37,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -68,9 +68,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwmulu.vv.yaml b/arch/inst/V/vwmulu.vv.yaml index 1d157720db..8686115d5a 100644 --- a/arch/inst/V/vwmulu.vv.yaml +++ b/arch/inst/V/vwmulu.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,25 +37,25 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -69,9 +69,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwmulu.vx.yaml b/arch/inst/V/vwmulu.vx.yaml index 1911028610..8433bb6222 100644 --- a/arch/inst/V/vwmulu.vx.yaml +++ b/arch/inst/V/vwmulu.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,24 +37,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -68,9 +68,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwredsum.vs.yaml b/arch/inst/V/vwredsum.vs.yaml index 869c4fbef1..0032bcfd6c 100644 --- a/arch/inst/V/vwredsum.vs.yaml +++ b/arch/inst/V/vwredsum.vs.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,21 +38,21 @@ sail(): | let LMUL_pow_widen = LMUL_pow + 1; let num_elem_vs = get_num_elem(LMUL_pow, SEW); let num_elem_vd = get_num_elem(0, SEW_widen); /* vd regardless of LMUL setting */ - + if illegal_reduction_widen(SEW_widen, LMUL_pow_widen) then { handle_illegal(); return RETIRE_FAIL }; - + if unsigned(vl) == 0 then return RETIRE_SUCCESS; /* if vl=0, no operation is performed */ - + let 'n = num_elem_vs; let 'd = num_elem_vd; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem_vs, vm, 0b00000); let vd_val : vector('d, dec, bits('o)) = read_vreg(num_elem_vd, SEW_widen, 0, vd); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem_vs, SEW, LMUL_pow, vs2); let mask : vector('n, dec, bool) = init_masked_source(num_elem_vs, LMUL_pow, vm_val); - + sum : bits('o) = read_single_element(SEW_widen, 0, vs1); /* vs1 regardless of LMUL setting */ foreach (i from 0 to (num_elem_vs - 1)) { if mask[i] then { @@ -63,11 +63,10 @@ sail(): | sum = sum + elem } }; - + write_single_element(SEW_widen, 0, vd, sum); /* other elements in vd are treated as tail elements, currently remain unchanged */ /* TODO: configuration support for agnostic behavior */ vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwredsumu.vs.yaml b/arch/inst/V/vwredsumu.vs.yaml index d3739d1879..700f88b76d 100644 --- a/arch/inst/V/vwredsumu.vs.yaml +++ b/arch/inst/V/vwredsumu.vs.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -38,21 +38,21 @@ sail(): | let LMUL_pow_widen = LMUL_pow + 1; let num_elem_vs = get_num_elem(LMUL_pow, SEW); let num_elem_vd = get_num_elem(0, SEW_widen); /* vd regardless of LMUL setting */ - + if illegal_reduction_widen(SEW_widen, LMUL_pow_widen) then { handle_illegal(); return RETIRE_FAIL }; - + if unsigned(vl) == 0 then return RETIRE_SUCCESS; /* if vl=0, no operation is performed */ - + let 'n = num_elem_vs; let 'd = num_elem_vd; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem_vs, vm, 0b00000); let vd_val : vector('d, dec, bits('o)) = read_vreg(num_elem_vd, SEW_widen, 0, vd); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem_vs, SEW, LMUL_pow, vs2); let mask : vector('n, dec, bool) = init_masked_source(num_elem_vs, LMUL_pow, vm_val); - + sum : bits('o) = read_single_element(SEW_widen, 0, vs1); /* vs1 regardless of LMUL setting */ foreach (i from 0 to (num_elem_vs - 1)) { if mask[i] then { @@ -63,11 +63,10 @@ sail(): | sum = sum + elem } }; - + write_single_element(SEW_widen, 0, vd, sum); /* other elements in vd are treated as tail elements, currently remain unchanged */ /* TODO: configuration support for agnostic behavior */ vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwsub.vv.yaml b/arch/inst/V/vwsub.vv.yaml index def690adea..14530949a3 100644 --- a/arch/inst/V/vwsub.vv.yaml +++ b/arch/inst/V/vwsub.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,25 +37,25 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -69,9 +69,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwsub.vx.yaml b/arch/inst/V/vwsub.vx.yaml index 037a57975b..66a3c69f09 100644 --- a/arch/inst/V/vwsub.vx.yaml +++ b/arch/inst/V/vwsub.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,24 +37,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -68,9 +68,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwsub.wv.yaml b/arch/inst/V/vwsub.wv.yaml index d295bd7853..8af49ee0a5 100644 --- a/arch/inst/V/vwsub.wv.yaml +++ b/arch/inst/V/vwsub.wv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,24 +37,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -65,9 +65,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwsub.wx.yaml b/arch/inst/V/vwsub.wx.yaml index 76b836b677..a91894f1b6 100644 --- a/arch/inst/V/vwsub.wx.yaml +++ b/arch/inst/V/vwsub.wx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,23 +37,23 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -64,9 +64,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwsubu.vv.yaml b/arch/inst/V/vwsubu.vv.yaml index c2b5c8eb02..2b05bf5121 100644 --- a/arch/inst/V/vwsubu.vv.yaml +++ b/arch/inst/V/vwsubu.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,25 +37,25 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -69,9 +69,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwsubu.vx.yaml b/arch/inst/V/vwsubu.vx.yaml index d70695bb23..0838d847b9 100644 --- a/arch/inst/V/vwsubu.vx.yaml +++ b/arch/inst/V/vwsubu.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,24 +37,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -68,9 +68,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwsubu.wv.yaml b/arch/inst/V/vwsubu.wv.yaml index 5da6b8f105..dec2d06988 100644 --- a/arch/inst/V/vwsubu.wv.yaml +++ b/arch/inst/V/vwsubu.wv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,24 +37,24 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -65,9 +65,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vwsubu.wx.yaml b/arch/inst/V/vwsubu.wx.yaml index 3aab9d1b11..84243dc457 100644 --- a/arch/inst/V/vwsubu.wx.yaml +++ b/arch/inst/V/vwsubu.wx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,23 +37,23 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_widen; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); result : vector('n, dec, bits('o)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -64,9 +64,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vxor.vi.yaml b/arch/inst/V/vxor.vi.yaml index 9f1e02491b..40c5570701 100644 --- a/arch/inst/V/vxor.vi.yaml +++ b/arch/inst/V/vxor.vi.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let imm_val : bits('m) = sign_extend(simm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -87,9 +87,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vxor.vv.yaml b/arch/inst/V/vxor.vv.yaml index 32f05d9f84..9e3067f6be 100644 --- a/arch/inst/V/vxor.vv.yaml +++ b/arch/inst/V/vxor.vv.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,21 +37,21 @@ sail(): | let LMUL_pow = get_lmul_pow(); let VLEN_pow = get_vlen_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -120,9 +120,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vxor.vx.yaml b/arch/inst/V/vxor.vx.yaml index 405e521ed5..8ed77e0db8 100644 --- a/arch/inst/V/vxor.vx.yaml +++ b/arch/inst/V/vxor.vx.yaml @@ -26,7 +26,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,21 +35,21 @@ sail(): | let SEW = get_sew(); let LMUL_pow = get_lmul_pow(); let num_elem = get_num_elem(LMUL_pow, SEW); - + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar(rs1, SEW); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + foreach (i from 0 to (num_elem - 1)) { if mask[i] then { result[i] = match funct6 { @@ -103,9 +103,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vzext.vf2.yaml b/arch/inst/V/vzext.vf2.yaml index f3ef6b579e..c978587ca4 100644 --- a/arch/inst/V/vzext.vf2.yaml +++ b/arch/inst/V/vzext.vf2.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,23 +35,23 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_half = SEW / 2; let LMUL_pow_half = LMUL_pow - 1; - + if illegal_variable_width(vd, vm, SEW_half, LMUL_pow_half) | not(valid_reg_overlap(vs2, vd, LMUL_pow_half, LMUL_pow)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_half; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_half, LMUL_pow_half, vs2); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + assert(SEW > SEW_half); foreach (i from 0 to (num_elem - 1)) { if mask[i] then { @@ -61,9 +61,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vzext.vf4.yaml b/arch/inst/V/vzext.vf4.yaml index 70832f5062..a39b7b8813 100644 --- a/arch/inst/V/vzext.vf4.yaml +++ b/arch/inst/V/vzext.vf4.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,23 +35,23 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_quart = SEW / 4; let LMUL_pow_quart = LMUL_pow - 2; - + if illegal_variable_width(vd, vm, SEW_quart, LMUL_pow_quart) | not(valid_reg_overlap(vs2, vd, LMUL_pow_quart, LMUL_pow)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_quart; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_quart, LMUL_pow_quart, vs2); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + assert(SEW > SEW_quart); foreach (i from 0 to (num_elem - 1)) { if mask[i] then { @@ -61,9 +61,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/V/vzext.vf8.yaml b/arch/inst/V/vzext.vf8.yaml index 8e0fb1c888..4fce98f036 100644 --- a/arch/inst/V/vzext.vf8.yaml +++ b/arch/inst/V/vzext.vf8.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -35,23 +35,23 @@ sail(): | let num_elem = get_num_elem(LMUL_pow, SEW); let SEW_eighth = SEW / 8; let LMUL_pow_eighth = LMUL_pow - 3; - + if illegal_variable_width(vd, vm, SEW_eighth, LMUL_pow_eighth) | not(valid_reg_overlap(vs2, vd, LMUL_pow_eighth, LMUL_pow)) then { handle_illegal(); return RETIRE_FAIL }; - + let 'n = num_elem; let 'm = SEW; let 'o = SEW_eighth; - + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_eighth, LMUL_pow_eighth, vs2); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; - + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - + assert(SEW > SEW_eighth); foreach (i from 0 to (num_elem - 1)) { if mask[i] then { @@ -61,9 +61,8 @@ sail(): | } } }; - + write_vreg(num_elem, SEW, LMUL_pow, vd, result); vstart = zeros(); RETIRE_SUCCESS } - diff --git a/arch/inst/Zabha/amoadd.b.yaml b/arch/inst/Zabha/amoadd.b.yaml index 5024808c2a..a88fe6b2ce 100644 --- a/arch/inst/Zabha/amoadd.b.yaml +++ b/arch/inst/Zabha/amoadd.b.yaml @@ -28,7 +28,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -82,7 +82,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -122,4 +122,3 @@ sail(): | RETIRE_FAIL } } - diff --git a/arch/inst/Zabha/amoadd.h.yaml b/arch/inst/Zabha/amoadd.h.yaml index 07ef0b18f5..5b96e77791 100644 --- a/arch/inst/Zabha/amoadd.h.yaml +++ b/arch/inst/Zabha/amoadd.h.yaml @@ -28,7 +28,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -82,7 +82,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -122,4 +122,3 @@ sail(): | RETIRE_FAIL } } - diff --git a/arch/inst/Zabha/amoand.b.yaml b/arch/inst/Zabha/amoand.b.yaml index abb64cf26b..a8f3e6fc2b 100644 --- a/arch/inst/Zabha/amoand.b.yaml +++ b/arch/inst/Zabha/amoand.b.yaml @@ -28,7 +28,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -82,7 +82,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -122,4 +122,3 @@ sail(): | RETIRE_FAIL } } - diff --git a/arch/inst/Zabha/amoand.h.yaml b/arch/inst/Zabha/amoand.h.yaml index dd21970bb4..9be12f7119 100644 --- a/arch/inst/Zabha/amoand.h.yaml +++ b/arch/inst/Zabha/amoand.h.yaml @@ -28,7 +28,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -82,7 +82,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -122,4 +122,3 @@ sail(): | RETIRE_FAIL } } - diff --git a/arch/inst/Zabha/amocas.b.yaml b/arch/inst/Zabha/amocas.b.yaml index a54fff572a..58be77749b 100644 --- a/arch/inst/Zabha/amocas.b.yaml +++ b/arch/inst/Zabha/amocas.b.yaml @@ -28,4 +28,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zabha/amocas.h.yaml b/arch/inst/Zabha/amocas.h.yaml index 7406e4a4fa..5ea2e2b728 100644 --- a/arch/inst/Zabha/amocas.h.yaml +++ b/arch/inst/Zabha/amocas.h.yaml @@ -28,4 +28,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zabha/amomax.b.yaml b/arch/inst/Zabha/amomax.b.yaml index bb49fc9f38..2ca5f28596 100644 --- a/arch/inst/Zabha/amomax.b.yaml +++ b/arch/inst/Zabha/amomax.b.yaml @@ -28,7 +28,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -82,7 +82,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -122,4 +122,3 @@ sail(): | RETIRE_FAIL } } - diff --git a/arch/inst/Zabha/amomax.h.yaml b/arch/inst/Zabha/amomax.h.yaml index e89c043a5e..b8ae26f1ae 100644 --- a/arch/inst/Zabha/amomax.h.yaml +++ b/arch/inst/Zabha/amomax.h.yaml @@ -28,7 +28,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -82,7 +82,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -122,4 +122,3 @@ sail(): | RETIRE_FAIL } } - diff --git a/arch/inst/Zabha/amomaxu.b.yaml b/arch/inst/Zabha/amomaxu.b.yaml index 5cde35d5dc..8fad8f562e 100644 --- a/arch/inst/Zabha/amomaxu.b.yaml +++ b/arch/inst/Zabha/amomaxu.b.yaml @@ -28,7 +28,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -82,7 +82,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -122,4 +122,3 @@ sail(): | RETIRE_FAIL } } - diff --git a/arch/inst/Zabha/amomaxu.h.yaml b/arch/inst/Zabha/amomaxu.h.yaml index ea6538fb57..9952ef3566 100644 --- a/arch/inst/Zabha/amomaxu.h.yaml +++ b/arch/inst/Zabha/amomaxu.h.yaml @@ -28,7 +28,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -82,7 +82,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -122,4 +122,3 @@ sail(): | RETIRE_FAIL } } - diff --git a/arch/inst/Zabha/amomin.b.yaml b/arch/inst/Zabha/amomin.b.yaml index bba1d9afe6..58f898f01e 100644 --- a/arch/inst/Zabha/amomin.b.yaml +++ b/arch/inst/Zabha/amomin.b.yaml @@ -28,7 +28,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -82,7 +82,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -122,4 +122,3 @@ sail(): | RETIRE_FAIL } } - diff --git a/arch/inst/Zabha/amomin.h.yaml b/arch/inst/Zabha/amomin.h.yaml index 71164e406e..7cb010ba0d 100644 --- a/arch/inst/Zabha/amomin.h.yaml +++ b/arch/inst/Zabha/amomin.h.yaml @@ -28,7 +28,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -82,7 +82,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -122,4 +122,3 @@ sail(): | RETIRE_FAIL } } - diff --git a/arch/inst/Zabha/amominu.b.yaml b/arch/inst/Zabha/amominu.b.yaml index 1ec23a812a..aaf8204d5f 100644 --- a/arch/inst/Zabha/amominu.b.yaml +++ b/arch/inst/Zabha/amominu.b.yaml @@ -28,7 +28,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -82,7 +82,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -122,4 +122,3 @@ sail(): | RETIRE_FAIL } } - diff --git a/arch/inst/Zabha/amominu.h.yaml b/arch/inst/Zabha/amominu.h.yaml index be68c59476..b805456a58 100644 --- a/arch/inst/Zabha/amominu.h.yaml +++ b/arch/inst/Zabha/amominu.h.yaml @@ -28,7 +28,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -82,7 +82,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -122,4 +122,3 @@ sail(): | RETIRE_FAIL } } - diff --git a/arch/inst/Zabha/amoor.b.yaml b/arch/inst/Zabha/amoor.b.yaml index 7fc2858244..c339a8c1e2 100644 --- a/arch/inst/Zabha/amoor.b.yaml +++ b/arch/inst/Zabha/amoor.b.yaml @@ -28,7 +28,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -82,7 +82,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -122,4 +122,3 @@ sail(): | RETIRE_FAIL } } - diff --git a/arch/inst/Zabha/amoor.h.yaml b/arch/inst/Zabha/amoor.h.yaml index 85d3a704dd..5c637e671a 100644 --- a/arch/inst/Zabha/amoor.h.yaml +++ b/arch/inst/Zabha/amoor.h.yaml @@ -28,7 +28,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -82,7 +82,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -122,4 +122,3 @@ sail(): | RETIRE_FAIL } } - diff --git a/arch/inst/Zabha/amoswap.b.yaml b/arch/inst/Zabha/amoswap.b.yaml index 68d63647e6..e3370fa270 100644 --- a/arch/inst/Zabha/amoswap.b.yaml +++ b/arch/inst/Zabha/amoswap.b.yaml @@ -28,7 +28,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -82,7 +82,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -122,4 +122,3 @@ sail(): | RETIRE_FAIL } } - diff --git a/arch/inst/Zabha/amoswap.h.yaml b/arch/inst/Zabha/amoswap.h.yaml index 76cf8d38ac..81ad25a56d 100644 --- a/arch/inst/Zabha/amoswap.h.yaml +++ b/arch/inst/Zabha/amoswap.h.yaml @@ -28,7 +28,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -82,7 +82,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -122,4 +122,3 @@ sail(): | RETIRE_FAIL } } - diff --git a/arch/inst/Zabha/amoxor.b.yaml b/arch/inst/Zabha/amoxor.b.yaml index ba29559e24..6cc6b94082 100644 --- a/arch/inst/Zabha/amoxor.b.yaml +++ b/arch/inst/Zabha/amoxor.b.yaml @@ -28,7 +28,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -82,7 +82,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -122,4 +122,3 @@ sail(): | RETIRE_FAIL } } - diff --git a/arch/inst/Zabha/amoxor.h.yaml b/arch/inst/Zabha/amoxor.h.yaml index 3017d2291f..a03c9def1c 100644 --- a/arch/inst/Zabha/amoxor.h.yaml +++ b/arch/inst/Zabha/amoxor.h.yaml @@ -28,7 +28,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -82,7 +82,7 @@ sail(): | AMOXOR => rs2_val ^ loaded, AMOAND => rs2_val & loaded, AMOOR => rs2_val | loaded, - + /* These operations convert bitvectors to integer values using [un]signed, * and back using to_bits(). */ @@ -122,4 +122,3 @@ sail(): | RETIRE_FAIL } } - diff --git a/arch/inst/Zacas/amocas.d.yaml b/arch/inst/Zacas/amocas.d.yaml index 8b7dfe1676..d7adbc8fd2 100644 --- a/arch/inst/Zacas/amocas.d.yaml +++ b/arch/inst/Zacas/amocas.d.yaml @@ -28,4 +28,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zacas/amocas.q.yaml b/arch/inst/Zacas/amocas.q.yaml index 63fa46f737..7c375ab204 100644 --- a/arch/inst/Zacas/amocas.q.yaml +++ b/arch/inst/Zacas/amocas.q.yaml @@ -29,4 +29,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zacas/amocas.w.yaml b/arch/inst/Zacas/amocas.w.yaml index 0e64eccde3..5cb79b0d6a 100644 --- a/arch/inst/Zacas/amocas.w.yaml +++ b/arch/inst/Zacas/amocas.w.yaml @@ -28,4 +28,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zalasr/lb.aq.yaml b/arch/inst/Zalasr/lb.aq.yaml index 8b649b9350..c77cff6d42 100644 --- a/arch/inst/Zalasr/lb.aq.yaml +++ b/arch/inst/Zalasr/lb.aq.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -55,4 +55,3 @@ sail(): | } } } - diff --git a/arch/inst/Zalasr/ld.aq.yaml b/arch/inst/Zalasr/ld.aq.yaml index 90a37dad12..227d21844f 100644 --- a/arch/inst/Zalasr/ld.aq.yaml +++ b/arch/inst/Zalasr/ld.aq.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -55,4 +55,3 @@ sail(): | } } } - diff --git a/arch/inst/Zalasr/lh.aq.yaml b/arch/inst/Zalasr/lh.aq.yaml index 9d3a81213e..34542cece4 100644 --- a/arch/inst/Zalasr/lh.aq.yaml +++ b/arch/inst/Zalasr/lh.aq.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -55,4 +55,3 @@ sail(): | } } } - diff --git a/arch/inst/Zalasr/lw.aq.yaml b/arch/inst/Zalasr/lw.aq.yaml index 65a5435e4c..b0acbfb8d8 100644 --- a/arch/inst/Zalasr/lw.aq.yaml +++ b/arch/inst/Zalasr/lw.aq.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -55,4 +55,3 @@ sail(): | } } } - diff --git a/arch/inst/Zalasr/sb.rl.yaml b/arch/inst/Zalasr/sb.rl.yaml index 19b6fd35a4..4f2a76c0ba 100644 --- a/arch/inst/Zalasr/sb.rl.yaml +++ b/arch/inst/Zalasr/sb.rl.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -70,4 +70,3 @@ sail(): | } } } - diff --git a/arch/inst/Zalasr/sd.rl.yaml b/arch/inst/Zalasr/sd.rl.yaml index 49af9816bd..ea8d449540 100644 --- a/arch/inst/Zalasr/sd.rl.yaml +++ b/arch/inst/Zalasr/sd.rl.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -70,4 +70,3 @@ sail(): | } } } - diff --git a/arch/inst/Zalasr/sh.rl.yaml b/arch/inst/Zalasr/sh.rl.yaml index d28714762d..6265013096 100644 --- a/arch/inst/Zalasr/sh.rl.yaml +++ b/arch/inst/Zalasr/sh.rl.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -70,4 +70,3 @@ sail(): | } } } - diff --git a/arch/inst/Zalasr/sw.rl.yaml b/arch/inst/Zalasr/sw.rl.yaml index 48535507bc..f93fa6709c 100644 --- a/arch/inst/Zalasr/sw.rl.yaml +++ b/arch/inst/Zalasr/sw.rl.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -70,4 +70,3 @@ sail(): | } } } - diff --git a/arch/inst/Zawrs/wrs.nto.yaml b/arch/inst/Zawrs/wrs.nto.yaml index 4c130ba859..8ca9e6479a 100644 --- a/arch/inst/Zawrs/wrs.nto.yaml +++ b/arch/inst/Zawrs/wrs.nto.yaml @@ -18,4 +18,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zawrs/wrs.sto.yaml b/arch/inst/Zawrs/wrs.sto.yaml index d623a43ea4..7052d117c7 100644 --- a/arch/inst/Zawrs/wrs.sto.yaml +++ b/arch/inst/Zawrs/wrs.sto.yaml @@ -18,4 +18,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zbkb/brev8.yaml b/arch/inst/Zbkb/brev8.yaml index 2a2d5598d6..4993648fc4 100644 --- a/arch/inst/Zbkb/brev8.yaml +++ b/arch/inst/Zbkb/brev8.yaml @@ -23,4 +23,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zbkb/unzip.yaml b/arch/inst/Zbkb/unzip.yaml index 6927616eac..64bff932a8 100644 --- a/arch/inst/Zbkb/unzip.yaml +++ b/arch/inst/Zbkb/unzip.yaml @@ -24,4 +24,3 @@ access: data_independent_timing: false base: 32 operation(): | - diff --git a/arch/inst/Zbkb/zip.yaml b/arch/inst/Zbkb/zip.yaml index a542b172ec..b5a3b27330 100644 --- a/arch/inst/Zbkb/zip.yaml +++ b/arch/inst/Zbkb/zip.yaml @@ -24,4 +24,3 @@ access: data_independent_timing: false base: 32 operation(): | - diff --git a/arch/inst/Zbkx/xperm4.yaml b/arch/inst/Zbkx/xperm4.yaml index a422462e29..0e1c05fb73 100644 --- a/arch/inst/Zbkx/xperm4.yaml +++ b/arch/inst/Zbkx/xperm4.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zbkx/xperm8.yaml b/arch/inst/Zbkx/xperm8.yaml index 5f6bb5a596..a0afff2de2 100644 --- a/arch/inst/Zbkx/xperm8.yaml +++ b/arch/inst/Zbkx/xperm8.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zbp/gorci.yaml b/arch/inst/Zbp/gorci.yaml index 4b61d319b5..1b7037d2c5 100644 --- a/arch/inst/Zbp/gorci.yaml +++ b/arch/inst/Zbp/gorci.yaml @@ -26,4 +26,3 @@ access: data_independent_timing: false base: 64 operation(): | - diff --git a/arch/inst/Zbp/grevi.yaml b/arch/inst/Zbp/grevi.yaml index 89bc7860a1..1fa748351c 100644 --- a/arch/inst/Zbp/grevi.yaml +++ b/arch/inst/Zbp/grevi.yaml @@ -26,4 +26,3 @@ access: data_independent_timing: false base: 64 operation(): | - diff --git a/arch/inst/Zbp/shfli.yaml b/arch/inst/Zbp/shfli.yaml index 3b30aae230..c903c6ae89 100644 --- a/arch/inst/Zbp/shfli.yaml +++ b/arch/inst/Zbp/shfli.yaml @@ -26,4 +26,3 @@ access: data_independent_timing: false base: 64 operation(): | - diff --git a/arch/inst/Zbp/unshfli.yaml b/arch/inst/Zbp/unshfli.yaml index 8038269f76..0f49c53244 100644 --- a/arch/inst/Zbp/unshfli.yaml +++ b/arch/inst/Zbp/unshfli.yaml @@ -26,4 +26,3 @@ access: data_independent_timing: false base: 64 operation(): | - diff --git a/arch/inst/Zbp/xperm16.yaml b/arch/inst/Zbp/xperm16.yaml index afd0ea3fee..ad079aadb6 100644 --- a/arch/inst/Zbp/xperm16.yaml +++ b/arch/inst/Zbp/xperm16.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zbp/xperm32.yaml b/arch/inst/Zbp/xperm32.yaml index 8045330dbc..796b190713 100644 --- a/arch/inst/Zbp/xperm32.yaml +++ b/arch/inst/Zbp/xperm32.yaml @@ -26,4 +26,3 @@ access: data_independent_timing: false base: 64 operation(): | - diff --git a/arch/inst/Zcb/c.lbu.yaml b/arch/inst/Zcb/c.lbu.yaml index b521eb8868..0c0a4a0a96 100644 --- a/arch/inst/Zcb/c.lbu.yaml +++ b/arch/inst/Zcb/c.lbu.yaml @@ -3,7 +3,7 @@ $schema: "inst_schema.json#" kind: instruction name: c.lbu -long_name: Load unsigned byte, 16-bit encoding +long_name: Load unsigned byte, 16-bit encoding description: | Loads a 8-bit value from memory into register rd. It computes an effective address by adding the zero-extended offset, to the base address in register rs1. diff --git a/arch/inst/Zcb/c.lh.yaml b/arch/inst/Zcb/c.lh.yaml index 938bf6936a..2c29ba108b 100644 --- a/arch/inst/Zcb/c.lh.yaml +++ b/arch/inst/Zcb/c.lh.yaml @@ -3,7 +3,7 @@ $schema: "inst_schema.json#" kind: instruction name: c.lh -long_name: Load signed halfword, 16-bit encoding +long_name: Load signed halfword, 16-bit encoding description: | Loads a 16-bit value from memory into register rd. It computes an effective address by adding the zero-extended offset, to the base address in register rs1. diff --git a/arch/inst/Zcb/c.lhu.yaml b/arch/inst/Zcb/c.lhu.yaml index e4567e26e5..1d71ead419 100644 --- a/arch/inst/Zcb/c.lhu.yaml +++ b/arch/inst/Zcb/c.lhu.yaml @@ -3,7 +3,7 @@ $schema: "inst_schema.json#" kind: instruction name: c.lhu -long_name: Load unsigned halfword, 16-bit encoding +long_name: Load unsigned halfword, 16-bit encoding description: | Loads a 16-bit value from memory into register rd. It computes an effective address by adding the zero-extended offset, to the base address in register rs1. diff --git a/arch/inst/Zcb/c.mul.yaml b/arch/inst/Zcb/c.mul.yaml index 60f22a711b..f27561dbb2 100644 --- a/arch/inst/Zcb/c.mul.yaml +++ b/arch/inst/Zcb/c.mul.yaml @@ -42,7 +42,3 @@ sail(): | X(rsdc) = result_wide[(sizeof(xlen) - 1) .. 0]; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/Zcb/c.not.yaml b/arch/inst/Zcb/c.not.yaml index 2b1ac36514..8612ca93e4 100644 --- a/arch/inst/Zcb/c.not.yaml +++ b/arch/inst/Zcb/c.not.yaml @@ -5,7 +5,7 @@ kind: instruction name: c.not long_name: Bitwise not, 16-bit encoding description: | - This instruction takes a single source/destination operand. + This instruction takes a single source/destination operand. This instruction takes the one’s complement of rd'/rs1' and writes the result to the same register. definedBy: @@ -36,7 +36,3 @@ sail(): | X(rsdc) = X(rsdc) XOR -1; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/Zcb/c.sb.yaml b/arch/inst/Zcb/c.sb.yaml index 95512638b2..f4dcfa76cb 100644 --- a/arch/inst/Zcb/c.sb.yaml +++ b/arch/inst/Zcb/c.sb.yaml @@ -3,7 +3,7 @@ $schema: "inst_schema.json#" kind: instruction name: c.sb -long_name: Store unsigned byte, 16-bit encoding +long_name: Store unsigned byte, 16-bit encoding description: | Stores a 8-bit value from register rs2 into memory. It computes an effective address by adding the zero-extended offset, to the base address in register rs1. diff --git a/arch/inst/Zcb/c.sext.b.yaml b/arch/inst/Zcb/c.sext.b.yaml index f7d368af76..0bd3c24de8 100644 --- a/arch/inst/Zcb/c.sext.b.yaml +++ b/arch/inst/Zcb/c.sext.b.yaml @@ -5,8 +5,8 @@ kind: instruction name: c.sext.b long_name: Sign-extend byte, 16-bit encoding description: | - This instruction takes a single source/destination operand. - This instruction sign-extends the least-significant byte of the source to XLEN by copying + This instruction takes a single source/destination operand. + This instruction sign-extends the least-significant byte of the source to XLEN by copying the most-significant bit in the byte (i.e., bit 7) to all of the more-significant bits. definedBy: @@ -49,7 +49,3 @@ sail(): | X(rsdc) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/Zcb/c.sext.h.yaml b/arch/inst/Zcb/c.sext.h.yaml index 23e181f5f8..8f80616050 100644 --- a/arch/inst/Zcb/c.sext.h.yaml +++ b/arch/inst/Zcb/c.sext.h.yaml @@ -5,8 +5,8 @@ kind: instruction name: c.sext.h long_name: Sign-extend halfword, 16-bit encoding description: | - This instruction takes a single source/destination operand. - This instruction sign-extends the least-significant halfword of the source to XLEN by copying + This instruction takes a single source/destination operand. + This instruction sign-extends the least-significant halfword of the source to XLEN by copying the most-significant bit in the halfword (i.e., bit 15) to all of the more-significant bits. definedBy: @@ -49,7 +49,3 @@ sail(): | X(rsdc) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/Zcb/c.sh.yaml b/arch/inst/Zcb/c.sh.yaml index eeb0d9511b..39d357048f 100644 --- a/arch/inst/Zcb/c.sh.yaml +++ b/arch/inst/Zcb/c.sh.yaml @@ -3,7 +3,7 @@ $schema: "inst_schema.json#" kind: instruction name: c.sh -long_name: Store unsigned halfword, 16-bit encoding +long_name: Store unsigned halfword, 16-bit encoding description: | Stores a 16-bit value from register rs2 into memory. It computes an effective address by adding the zero-extended offset, to the base address in register rs1. diff --git a/arch/inst/Zcb/c.zext.b.yaml b/arch/inst/Zcb/c.zext.b.yaml index a59b37ac64..0049b6229d 100644 --- a/arch/inst/Zcb/c.zext.b.yaml +++ b/arch/inst/Zcb/c.zext.b.yaml @@ -5,7 +5,7 @@ kind: instruction name: c.zext.b long_name: Zero-extend byte, 16-bit encoding description: | - This instruction takes a single source/destination operand. + This instruction takes a single source/destination operand. This instruction zero-extends the least-significant byte of the source to XLEN by inserting 0's into all of the bits more significant than 7. @@ -49,7 +49,3 @@ sail(): | X(rsdc) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/Zcb/c.zext.h.yaml b/arch/inst/Zcb/c.zext.h.yaml index 2be0b9bf34..aeff66ef03 100644 --- a/arch/inst/Zcb/c.zext.h.yaml +++ b/arch/inst/Zcb/c.zext.h.yaml @@ -5,7 +5,7 @@ kind: instruction name: c.zext.h long_name: Zero-extend halfword, 16-bit encoding description: | - This instruction takes a single source/destination operand. + This instruction takes a single source/destination operand. This instruction zero-extends the least-significant halfword of the source to XLEN by inserting 0's into all of the bits more significant than 15. @@ -49,7 +49,3 @@ sail(): | X(rsdc) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/Zcb/c.zext.w.yaml b/arch/inst/Zcb/c.zext.w.yaml index fc892c6bf2..ea226cd043 100644 --- a/arch/inst/Zcb/c.zext.w.yaml +++ b/arch/inst/Zcb/c.zext.w.yaml @@ -5,7 +5,7 @@ kind: instruction name: c.zext.w long_name: Zero-extend word, 16-bit encoding description: | - This instruction takes a single source/destination operand. + This instruction takes a single source/destination operand. It zero-extends the least-significant word of the operand to XLEN bits by inserting zeros into all of the bits more significant than 31. definedBy: @@ -49,7 +49,3 @@ sail(): | X(rsdc) = result; RETIRE_SUCCESS } - - - - diff --git a/arch/inst/Zfbfmin/fcvt.bf16.s.yaml b/arch/inst/Zfbfmin/fcvt.bf16.s.yaml index 9d31847a57..50e616b591 100644 --- a/arch/inst/Zfbfmin/fcvt.bf16.s.yaml +++ b/arch/inst/Zfbfmin/fcvt.bf16.s.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfbfmin/fcvt.s.bf16.yaml b/arch/inst/Zfbfmin/fcvt.s.bf16.yaml index 70af2004a3..c6d2dcb9c1 100644 --- a/arch/inst/Zfbfmin/fcvt.s.bf16.yaml +++ b/arch/inst/Zfbfmin/fcvt.s.bf16.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/fadd.h.yaml b/arch/inst/Zfh/fadd.h.yaml index 51ac99df59..8ff9819fef 100644 --- a/arch/inst/Zfh/fadd.h.yaml +++ b/arch/inst/Zfh/fadd.h.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/fclass.h.yaml b/arch/inst/Zfh/fclass.h.yaml index 2943a71848..dff44fbda8 100644 --- a/arch/inst/Zfh/fclass.h.yaml +++ b/arch/inst/Zfh/fclass.h.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/fcvt.d.h.yaml b/arch/inst/Zfh/fcvt.d.h.yaml index d3f147dfcb..5f309dcb2e 100644 --- a/arch/inst/Zfh/fcvt.d.h.yaml +++ b/arch/inst/Zfh/fcvt.d.h.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/fcvt.h.d.yaml b/arch/inst/Zfh/fcvt.h.d.yaml index b0d4e2ee23..83d8d53ef5 100644 --- a/arch/inst/Zfh/fcvt.h.d.yaml +++ b/arch/inst/Zfh/fcvt.h.d.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/fcvt.h.l.yaml b/arch/inst/Zfh/fcvt.h.l.yaml index c3b75a0264..a91e39fe6e 100644 --- a/arch/inst/Zfh/fcvt.h.l.yaml +++ b/arch/inst/Zfh/fcvt.h.l.yaml @@ -25,4 +25,3 @@ access: data_independent_timing: false base: 64 operation(): | - diff --git a/arch/inst/Zfh/fcvt.h.lu.yaml b/arch/inst/Zfh/fcvt.h.lu.yaml index 037811c384..8bca318380 100644 --- a/arch/inst/Zfh/fcvt.h.lu.yaml +++ b/arch/inst/Zfh/fcvt.h.lu.yaml @@ -25,4 +25,3 @@ access: data_independent_timing: false base: 64 operation(): | - diff --git a/arch/inst/Zfh/fcvt.h.s.yaml b/arch/inst/Zfh/fcvt.h.s.yaml index 808ef24b67..65f87f4e93 100644 --- a/arch/inst/Zfh/fcvt.h.s.yaml +++ b/arch/inst/Zfh/fcvt.h.s.yaml @@ -24,7 +24,7 @@ encoding: - name: rm location: 14-12 - name: fd - location: 11-7 + location: 11-7 access: s: always u: always @@ -76,14 +76,10 @@ sail(): | Some(rm') => { let rm_3b = encdec_rounding_mode(rm'); let (fflags, rd_val_H) = riscv_ui64ToF16 (rm_3b, rs1_val_LU); - + accrue_fflags(fflags); F_or_X_H(rd) = rd_val_H; RETIRE_SUCCESS } } } - - - - diff --git a/arch/inst/Zfh/fcvt.h.w.yaml b/arch/inst/Zfh/fcvt.h.w.yaml index c17da2a24a..435226b964 100644 --- a/arch/inst/Zfh/fcvt.h.w.yaml +++ b/arch/inst/Zfh/fcvt.h.w.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/fcvt.h.wu.yaml b/arch/inst/Zfh/fcvt.h.wu.yaml index 4e0a0b503b..d1e3e0793e 100644 --- a/arch/inst/Zfh/fcvt.h.wu.yaml +++ b/arch/inst/Zfh/fcvt.h.wu.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/fcvt.l.h.yaml b/arch/inst/Zfh/fcvt.l.h.yaml index c7efe1383d..f024f191d2 100644 --- a/arch/inst/Zfh/fcvt.l.h.yaml +++ b/arch/inst/Zfh/fcvt.l.h.yaml @@ -25,4 +25,3 @@ access: data_independent_timing: false base: 64 operation(): | - diff --git a/arch/inst/Zfh/fcvt.lu.h.yaml b/arch/inst/Zfh/fcvt.lu.h.yaml index 8d98111e76..24adfb47a7 100644 --- a/arch/inst/Zfh/fcvt.lu.h.yaml +++ b/arch/inst/Zfh/fcvt.lu.h.yaml @@ -25,4 +25,3 @@ access: data_independent_timing: false base: 64 operation(): | - diff --git a/arch/inst/Zfh/fcvt.s.h.yaml b/arch/inst/Zfh/fcvt.s.h.yaml index 9ebd1fe1d9..dc69ea9fbf 100644 --- a/arch/inst/Zfh/fcvt.s.h.yaml +++ b/arch/inst/Zfh/fcvt.s.h.yaml @@ -21,7 +21,7 @@ encoding: - name: rm location: 14-12 - name: fd - location: 11-7 + location: 11-7 access: s: always u: always @@ -49,7 +49,7 @@ operation(): | # frac is a 24-bit significand, the bottom 9 bits LSB are extracted and OR-red # into a sticky flag, the top 15 MSBs are extracted, the LSB of this top slice - # is OR-red with the sticky + # is OR-red with the sticky Bits<16> frac16 = (frac >> 9) | ((frac & 0x1ff) != 0 ? 1 : 0); if ((exp | frac16) == 0) { f[fd] = nan_box<16, FLEN>(packToF16UI( sign, 0, 0 )); @@ -73,14 +73,10 @@ sail(): | Some(rm') => { let rm_3b = encdec_rounding_mode(rm'); let (fflags, rd_val_H) = riscv_ui64ToF16 (rm_3b, rs1_val_LU); - + accrue_fflags(fflags); F_or_X_H(rd) = rd_val_H; RETIRE_SUCCESS } } } - - - - diff --git a/arch/inst/Zfh/fcvt.w.h.yaml b/arch/inst/Zfh/fcvt.w.h.yaml index 91734b0f8c..03c31e5e96 100644 --- a/arch/inst/Zfh/fcvt.w.h.yaml +++ b/arch/inst/Zfh/fcvt.w.h.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/fcvt.wu.h.yaml b/arch/inst/Zfh/fcvt.wu.h.yaml index ed7163ee7a..2020304a6b 100644 --- a/arch/inst/Zfh/fcvt.wu.h.yaml +++ b/arch/inst/Zfh/fcvt.wu.h.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/fdiv.h.yaml b/arch/inst/Zfh/fdiv.h.yaml index 9d0c7b840f..ae879ef059 100644 --- a/arch/inst/Zfh/fdiv.h.yaml +++ b/arch/inst/Zfh/fdiv.h.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/feq.h.yaml b/arch/inst/Zfh/feq.h.yaml index 77c687a95c..a2ca9119e9 100644 --- a/arch/inst/Zfh/feq.h.yaml +++ b/arch/inst/Zfh/feq.h.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/fle.h.yaml b/arch/inst/Zfh/fle.h.yaml index 212d00238b..0328f9f524 100644 --- a/arch/inst/Zfh/fle.h.yaml +++ b/arch/inst/Zfh/fle.h.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/fleq.h.yaml b/arch/inst/Zfh/fleq.h.yaml index 13dd113635..7a7a35eda5 100644 --- a/arch/inst/Zfh/fleq.h.yaml +++ b/arch/inst/Zfh/fleq.h.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/flh.yaml b/arch/inst/Zfh/flh.yaml index 5a25dc1da5..76b99366e6 100644 --- a/arch/inst/Zfh/flh.yaml +++ b/arch/inst/Zfh/flh.yaml @@ -69,7 +69,3 @@ sail(): | } } } - - - - diff --git a/arch/inst/Zfh/fli.h.yaml b/arch/inst/Zfh/fli.h.yaml index 28932bea84..fb22d80106 100644 --- a/arch/inst/Zfh/fli.h.yaml +++ b/arch/inst/Zfh/fli.h.yaml @@ -23,4 +23,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/flt.h.yaml b/arch/inst/Zfh/flt.h.yaml index e379cc4b65..6e90a95cab 100644 --- a/arch/inst/Zfh/flt.h.yaml +++ b/arch/inst/Zfh/flt.h.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/fltq.h.yaml b/arch/inst/Zfh/fltq.h.yaml index 59d17dfadc..7b3ce83cbe 100644 --- a/arch/inst/Zfh/fltq.h.yaml +++ b/arch/inst/Zfh/fltq.h.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/fmadd.h.yaml b/arch/inst/Zfh/fmadd.h.yaml index f8e496d6b5..71971aac5e 100644 --- a/arch/inst/Zfh/fmadd.h.yaml +++ b/arch/inst/Zfh/fmadd.h.yaml @@ -28,4 +28,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/fmax.h.yaml b/arch/inst/Zfh/fmax.h.yaml index e42b1f0964..c4d132a5b2 100644 --- a/arch/inst/Zfh/fmax.h.yaml +++ b/arch/inst/Zfh/fmax.h.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/fmaxm.h.yaml b/arch/inst/Zfh/fmaxm.h.yaml index 1c8ad0fd37..d75b0d3252 100644 --- a/arch/inst/Zfh/fmaxm.h.yaml +++ b/arch/inst/Zfh/fmaxm.h.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/fmin.h.yaml b/arch/inst/Zfh/fmin.h.yaml index f132ad6be8..84699940cd 100644 --- a/arch/inst/Zfh/fmin.h.yaml +++ b/arch/inst/Zfh/fmin.h.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/fminm.h.yaml b/arch/inst/Zfh/fminm.h.yaml index 368564f3b2..17ed7b705a 100644 --- a/arch/inst/Zfh/fminm.h.yaml +++ b/arch/inst/Zfh/fminm.h.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/fmsub.h.yaml b/arch/inst/Zfh/fmsub.h.yaml index 6a04f45136..9b17b7d823 100644 --- a/arch/inst/Zfh/fmsub.h.yaml +++ b/arch/inst/Zfh/fmsub.h.yaml @@ -28,4 +28,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/fmul.h.yaml b/arch/inst/Zfh/fmul.h.yaml index 09ec68e0e6..b6185aa0cd 100644 --- a/arch/inst/Zfh/fmul.h.yaml +++ b/arch/inst/Zfh/fmul.h.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/fmv.h.x.yaml b/arch/inst/Zfh/fmv.h.x.yaml index 701e871f4f..e6c8e76481 100644 --- a/arch/inst/Zfh/fmv.h.x.yaml +++ b/arch/inst/Zfh/fmv.h.x.yaml @@ -40,7 +40,3 @@ sail(): | F(rd) = nan_box (rd_val_H); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/Zfh/fmv.x.h.yaml b/arch/inst/Zfh/fmv.x.h.yaml index 2695790312..ecd3085647 100644 --- a/arch/inst/Zfh/fmv.x.h.yaml +++ b/arch/inst/Zfh/fmv.x.h.yaml @@ -22,7 +22,7 @@ encoding: - name: fs1 location: 19-15 - name: rd - location: 11-7 + location: 11-7 access: s: always u: always @@ -42,7 +42,3 @@ sail(): | F(rd) = nan_box (rd_val_H); RETIRE_SUCCESS } - - - - diff --git a/arch/inst/Zfh/fnmadd.h.yaml b/arch/inst/Zfh/fnmadd.h.yaml index 8598d12334..61b3efbcde 100644 --- a/arch/inst/Zfh/fnmadd.h.yaml +++ b/arch/inst/Zfh/fnmadd.h.yaml @@ -28,4 +28,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/fnmsub.h.yaml b/arch/inst/Zfh/fnmsub.h.yaml index 226882bdc2..1f59bda402 100644 --- a/arch/inst/Zfh/fnmsub.h.yaml +++ b/arch/inst/Zfh/fnmsub.h.yaml @@ -28,4 +28,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/fround.h.yaml b/arch/inst/Zfh/fround.h.yaml index 4fa3d1d504..0276757155 100644 --- a/arch/inst/Zfh/fround.h.yaml +++ b/arch/inst/Zfh/fround.h.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/froundnx.h.yaml b/arch/inst/Zfh/froundnx.h.yaml index ec5f4fdebc..a2477a5042 100644 --- a/arch/inst/Zfh/froundnx.h.yaml +++ b/arch/inst/Zfh/froundnx.h.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/fsgnj.h.yaml b/arch/inst/Zfh/fsgnj.h.yaml index d0f1d6dbe0..a3a42471d4 100644 --- a/arch/inst/Zfh/fsgnj.h.yaml +++ b/arch/inst/Zfh/fsgnj.h.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/fsgnjn.h.yaml b/arch/inst/Zfh/fsgnjn.h.yaml index 54b4e0d8a2..b6454c3768 100644 --- a/arch/inst/Zfh/fsgnjn.h.yaml +++ b/arch/inst/Zfh/fsgnjn.h.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/fsgnjx.h.yaml b/arch/inst/Zfh/fsgnjx.h.yaml index b52101aea6..8b30873bf1 100644 --- a/arch/inst/Zfh/fsgnjx.h.yaml +++ b/arch/inst/Zfh/fsgnjx.h.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/fsh.yaml b/arch/inst/Zfh/fsh.yaml index 90d13183d7..6edc5d18fd 100644 --- a/arch/inst/Zfh/fsh.yaml +++ b/arch/inst/Zfh/fsh.yaml @@ -37,7 +37,7 @@ operation(): | XReg virtual_address = X[rs1] + $signed(imm); Bits<16> hp_value = f[fs2][15:0]; - + write_memory<16>(virtual_address, hp_value, $encoding); @@ -80,7 +80,3 @@ sail(): | } } } - - - - diff --git a/arch/inst/Zfh/fsqrt.h.yaml b/arch/inst/Zfh/fsqrt.h.yaml index d38f243790..61d70bfc8e 100644 --- a/arch/inst/Zfh/fsqrt.h.yaml +++ b/arch/inst/Zfh/fsqrt.h.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zfh/fsub.h.yaml b/arch/inst/Zfh/fsub.h.yaml index 956661d97e..a280c6fa52 100644 --- a/arch/inst/Zfh/fsub.h.yaml +++ b/arch/inst/Zfh/fsub.h.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zicbom/cbo.clean.yaml b/arch/inst/Zicbom/cbo.clean.yaml index 0d933f2071..04c8461d77 100644 --- a/arch/inst/Zicbom/cbo.clean.yaml +++ b/arch/inst/Zicbom/cbo.clean.yaml @@ -5,7 +5,7 @@ kind: instruction name: cbo.clean long_name: Cache Block Clean description: | - Cleans an entire cache block globally throughout the system. + Cleans an entire cache block globally throughout the system. Exactly what happens is coherence protocol-dependent, but in general it is expected that after this operation(): @@ -34,7 +34,7 @@ description: | <%- end -%> CBO operations never raise a misaligned address fault. - + definedBy: Zicbom assembly: "TODO" encoding: @@ -59,14 +59,13 @@ access_detail: | 4+^.>h! `cbo.clean` Instruction Behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `Illegal Instruction` ! `Illegal Instruction` ! `Virtual Instruction` ! `Virtual Instruction` - ! 1 ! 0 ! 0 ! executes ! `Illegal Instruction` ! `Virtual Instruction` ! `Virtual Instruction` - ! 1 ! 1 ! 0 ! executes ! executes ! `Virtual Instruction` ! `Virtual Instruction` - ! 1 ! 0 ! 1 ! executes ! `Illegal Instruction` ! executes ! `Virtual Instruction` + ! 0 ! - ! - ! `Illegal Instruction` ! `Illegal Instruction` ! `Virtual Instruction` ! `Virtual Instruction` + ! 1 ! 0 ! 0 ! executes ! `Illegal Instruction` ! `Virtual Instruction` ! `Virtual Instruction` + ! 1 ! 1 ! 0 ! executes ! executes ! `Virtual Instruction` ! `Virtual Instruction` + ! 1 ! 0 ! 1 ! executes ! `Illegal Instruction` ! executes ! `Virtual Instruction` ! 1 ! 1 ! 1 ! executes ! executes ! executes ! executes !=== # operation(): | # let cache_block_address = X[rs1] & ~(CACHE_BLOCK_SIZE-1); # CACHE_BLOCK_CLEAN(cache_block_address); - diff --git a/arch/inst/Zicbom/cbo.flush.yaml b/arch/inst/Zicbom/cbo.flush.yaml index 1f9d0e382d..068a2d2381 100644 --- a/arch/inst/Zicbom/cbo.flush.yaml +++ b/arch/inst/Zicbom/cbo.flush.yaml @@ -26,7 +26,7 @@ description: | Because cache blocks are naturally aligned and always fit in a single PMP or PMA regions, the PMP and PMA access checks only need to check a single address in the line. <%- end -%> - + CBO operations never raise a misaligned address fault. definedBy: Zicbom assembly: "TODO" @@ -52,10 +52,10 @@ access_detail: | 4+^.>h! `cbo.flush` Instruction Behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `Illegal Instruction` ! `Illegal Instruction` ! `Virtual Instruction` ! `Virtual Instruction` - ! 1 ! 0 ! 0 ! executes ! `Illegal Instruction` ! `Virtual Instruction` ! `Virtual Instruction` - ! 1 ! 1 ! 0 ! executes ! executes ! `Virtual Instruction` ! `Virtual Instruction` - ! 1 ! 0 ! 1 ! executes ! `Illegal Instruction` ! executes ! `Virtual Instruction` + ! 0 ! - ! - ! `Illegal Instruction` ! `Illegal Instruction` ! `Virtual Instruction` ! `Virtual Instruction` + ! 1 ! 0 ! 0 ! executes ! `Illegal Instruction` ! `Virtual Instruction` ! `Virtual Instruction` + ! 1 ! 1 ! 0 ! executes ! executes ! `Virtual Instruction` ! `Virtual Instruction` + ! 1 ! 0 ! 1 ! executes ! `Illegal Instruction` ! executes ! `Virtual Instruction` ! 1 ! 1 ! 1 ! executes ! executes ! executes ! executes !=== # operation(): | @@ -67,4 +67,3 @@ access_detail: | # if (has_fault?) { # raise(code); # } - diff --git a/arch/inst/Zicbom/cbo.inval.yaml b/arch/inst/Zicbom/cbo.inval.yaml index cfd36a7671..f0d1d9ac80 100644 --- a/arch/inst/Zicbom/cbo.inval.yaml +++ b/arch/inst/Zicbom/cbo.inval.yaml @@ -25,20 +25,20 @@ description: | 5+^.>h! `cbe.inval` Operation .^h! M-mode .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 00 ! - ! - ! Invalidate ! `Illegal Instruction` ! `Illegal Instruction` ! `Virtual Instruction` ! `Virtual Instruction` - ! 01 ! 00 ! 00 ! Invalidate ! Flush ! `Illegal Instruction` ! `Virtual Instruction` ! `Virtual Instruction` - ! 01 ! 00 ! 01 ! Invalidate ! Flush ! `Illegal Instruction` ! Flush ! `Virtual Instruction` - ! 01 ! 00 ! 11 ! Invalidate ! Flush ! `Illegal Instruction` ! Flush ! `Virtual Instruction` - ! 01 ! 01 ! 00 ! Invalidate ! Flush ! Flush ! `Virtual Instruction` ! `Virtual Instruction` + ! 00 ! - ! - ! Invalidate ! `Illegal Instruction` ! `Illegal Instruction` ! `Virtual Instruction` ! `Virtual Instruction` + ! 01 ! 00 ! 00 ! Invalidate ! Flush ! `Illegal Instruction` ! `Virtual Instruction` ! `Virtual Instruction` + ! 01 ! 00 ! 01 ! Invalidate ! Flush ! `Illegal Instruction` ! Flush ! `Virtual Instruction` + ! 01 ! 00 ! 11 ! Invalidate ! Flush ! `Illegal Instruction` ! Flush ! `Virtual Instruction` + ! 01 ! 01 ! 00 ! Invalidate ! Flush ! Flush ! `Virtual Instruction` ! `Virtual Instruction` ! 01 ! 01 ! 01 ! Invalidate ! Flush ! Flush ! Flush ! Flush ! 01 ! 01 ! 11 ! Invalidate ! Flush ! Flush ! Flush ! Flush ! 01 ! 11 ! 00 ! Invalidate ! Flush ! Flush ! `Virtual Instruction` ! `Virtual Instruction` ! 01 ! 11 ! 01 ! Invalidate ! Flush ! Flush ! Flush ! Flush ! 01 ! 11 ! 11 ! Invalidate ! Flush ! Flush ! Flush ! Flush - ! 11 ! 00 ! 00 ! Invalidate ! Invalidate ! `Illegal Instruction` ! `Virtual Instruction` ! `Virtual Instruction` - ! 11 ! 00 ! 01 ! Invalidate ! Invalidate ! `Illegal Instruction` ! Flush ! `Virtual Instruction` - ! 11 ! 00 ! 11 ! Invalidate ! Invalidate ! `Illegal Instruction` ! Invalidate ! `Virtual Instruction` - ! 11 ! 01 ! 00 ! Invalidate ! Invalidate ! Flush ! `Virtual Instruction` ! `Virtual Instruction` + ! 11 ! 00 ! 00 ! Invalidate ! Invalidate ! `Illegal Instruction` ! `Virtual Instruction` ! `Virtual Instruction` + ! 11 ! 00 ! 01 ! Invalidate ! Invalidate ! `Illegal Instruction` ! Flush ! `Virtual Instruction` + ! 11 ! 00 ! 11 ! Invalidate ! Invalidate ! `Illegal Instruction` ! Invalidate ! `Virtual Instruction` + ! 11 ! 01 ! 00 ! Invalidate ! Invalidate ! Flush ! `Virtual Instruction` ! `Virtual Instruction` ! 11 ! 01 ! 01 ! Invalidate ! Invalidate ! Flush ! Flush ! Flush ! 11 ! 01 ! 11 ! Invalidate ! Invalidate ! Flush ! Invalidate ! Flush ! 11 ! 11 ! 00 ! Invalidate ! Invalidate ! Invalidate ! `Virtual Instruction` ! `Virtual Instruction` @@ -65,7 +65,7 @@ description: | Because cache blocks are naturally aligned and always fit in a single PMP or PMA regions, the PMP and PMA access checks only need to check a single address in the line. <%- end -%> - + CBO operations never raise a misaligned address fault. definedBy: Zicbom assembly: "TODO" @@ -95,10 +95,10 @@ access_detail: | 4+^.>h! `cbo.inval` Instruction Behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 00 ! - ! - ! `Illegal Instruction` ! `Illegal Instruction` ! `Virtual Instruction` ! `Virtual Instruction` - ! 01/11 ! 00 ! 00 ! executes ! `Illegal Instruction` ! `Virtual Instruction` ! `Virtual Instruction` - ! 01/11 ! 01/11 ! 00 ! executes ! executes ! `Virtual Instruction` ! `Virtual Instruction` - ! 01/11 ! 00 ! 01/11 ! executes ! `Illegal Instruction` ! executes ! `Virtual Instruction` + ! 00 ! - ! - ! `Illegal Instruction` ! `Illegal Instruction` ! `Virtual Instruction` ! `Virtual Instruction` + ! 01/11 ! 00 ! 00 ! executes ! `Illegal Instruction` ! `Virtual Instruction` ! `Virtual Instruction` + ! 01/11 ! 01/11 ! 00 ! executes ! executes ! `Virtual Instruction` ! `Virtual Instruction` + ! 01/11 ! 00 ! 01/11 ! executes ! `Illegal Instruction` ! executes ! `Virtual Instruction` ! 01/11 ! 01/11 ! 01/11 ! executes ! executes ! executes ! executes !=== # operation(): | diff --git a/arch/inst/Zicboz/cbo.zero.yaml b/arch/inst/Zicboz/cbo.zero.yaml index 476c7b1a67..8457260bdb 100644 --- a/arch/inst/Zicboz/cbo.zero.yaml +++ b/arch/inst/Zicboz/cbo.zero.yaml @@ -28,7 +28,7 @@ description: | Because cache blocks are naturally aligned and always fit in a single PMP or PMA regions, the PMP and PMA access checks only need to check a single address in the line. <%- end -%> - + CBO operations never raise a misaligned address fault. definedBy: Zicboz assembly: "TODO" @@ -54,16 +54,16 @@ access_detail: | 4+^.>h! `cbo.zero` Instruction Behavior .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode - ! 0 ! - ! - ! `Illegal Instruction` ! `Illegal Instruction` ! `Virtual Instruction` ! `Virtual Instruction` - ! 1 ! 0 ! 0 ! executes ! `Illegal Instruction` ! `Virtual Instruction` ! `Virtual Instruction` - ! 1 ! 1 ! 0 ! executes ! executes ! `Virtual Instruction` ! `Virtual Instruction` - ! 1 ! 0 ! 1 ! executes ! `Illegal Instruction` ! executes ! `Virtual Instruction` + ! 0 ! - ! - ! `Illegal Instruction` ! `Illegal Instruction` ! `Virtual Instruction` ! `Virtual Instruction` + ! 1 ! 0 ! 0 ! executes ! `Illegal Instruction` ! `Virtual Instruction` ! `Virtual Instruction` + ! 1 ! 1 ! 0 ! executes ! executes ! `Virtual Instruction` ! `Virtual Instruction` + ! 1 ! 0 ! 1 ! executes ! `Illegal Instruction` ! executes ! `Virtual Instruction` ! 1 ! 1 ! 1 ! executes ! executes ! executes ! executes !=== operation(): | if ((mode() == PrivilegeMode::M && CSR[menvcfg].CBZE == 0) || (mode() == PrivilegeMode::U && CSR[senvcfg].CBZE == 0)) { - raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); } else if ((mode() == PrivilegeMode::VS && CSR[henvcfg].CBZE ==0) || (mode() == PrivilegeMode::VU && (CSR[henvcfg].CBZE | CSR[senvcfg].CBZE) == 0)) { diff --git a/arch/inst/Zicfilp/lpad.yaml b/arch/inst/Zicfilp/lpad.yaml index 376bce829f..d06692598c 100644 --- a/arch/inst/Zicfilp/lpad.yaml +++ b/arch/inst/Zicfilp/lpad.yaml @@ -21,4 +21,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zicfiss/ssamoswap.d.yaml b/arch/inst/Zicfiss/ssamoswap.d.yaml index 6c1ca2738b..6c6018c080 100644 --- a/arch/inst/Zicfiss/ssamoswap.d.yaml +++ b/arch/inst/Zicfiss/ssamoswap.d.yaml @@ -28,4 +28,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zicfiss/ssamoswap.w.yaml b/arch/inst/Zicfiss/ssamoswap.w.yaml index 1c608eef01..df5c208cea 100644 --- a/arch/inst/Zicfiss/ssamoswap.w.yaml +++ b/arch/inst/Zicfiss/ssamoswap.w.yaml @@ -28,4 +28,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zicfiss/sspopchk.x1.yaml b/arch/inst/Zicfiss/sspopchk.x1.yaml index 31d6c20e50..f81089bca3 100644 --- a/arch/inst/Zicfiss/sspopchk.x1.yaml +++ b/arch/inst/Zicfiss/sspopchk.x1.yaml @@ -18,4 +18,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zicfiss/sspopchk.x5.yaml b/arch/inst/Zicfiss/sspopchk.x5.yaml index 9f77ca1c15..9fc5f4bfe9 100644 --- a/arch/inst/Zicfiss/sspopchk.x5.yaml +++ b/arch/inst/Zicfiss/sspopchk.x5.yaml @@ -18,4 +18,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zicfiss/sspush.x1.yaml b/arch/inst/Zicfiss/sspush.x1.yaml index 6d4a0b8803..bb4361007a 100644 --- a/arch/inst/Zicfiss/sspush.x1.yaml +++ b/arch/inst/Zicfiss/sspush.x1.yaml @@ -18,4 +18,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zicfiss/sspush.x5.yaml b/arch/inst/Zicfiss/sspush.x5.yaml index e4b7957c17..d2c6e13c0a 100644 --- a/arch/inst/Zicfiss/sspush.x5.yaml +++ b/arch/inst/Zicfiss/sspush.x5.yaml @@ -18,4 +18,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zicfiss/ssrdp.yaml b/arch/inst/Zicfiss/ssrdp.yaml index 93597b957f..4204bbe1f9 100644 --- a/arch/inst/Zicfiss/ssrdp.yaml +++ b/arch/inst/Zicfiss/ssrdp.yaml @@ -21,4 +21,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zicond/czero.eqz.yaml b/arch/inst/Zicond/czero.eqz.yaml index f14e7397b2..539e7e4224 100644 --- a/arch/inst/Zicond/czero.eqz.yaml +++ b/arch/inst/Zicond/czero.eqz.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,4 +37,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - diff --git a/arch/inst/Zicond/czero.nez.yaml b/arch/inst/Zicond/czero.nez.yaml index c8dcd203da..5dc0a21024 100644 --- a/arch/inst/Zicond/czero.nez.yaml +++ b/arch/inst/Zicond/czero.nez.yaml @@ -24,7 +24,7 @@ access: vu: always data_independent_timing: false operation(): | - + @@ -37,4 +37,3 @@ sail(): | X(rd) = result; RETIRE_SUCCESS } - diff --git a/arch/inst/Zicsr/csrrc.yaml b/arch/inst/Zicsr/csrrc.yaml index c03fda2b81..283cccab7c 100644 --- a/arch/inst/Zicsr/csrrc.yaml +++ b/arch/inst/Zicsr/csrrc.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zicsr/csrrci.yaml b/arch/inst/Zicsr/csrrci.yaml index 3473497ef7..95b2a16254 100644 --- a/arch/inst/Zicsr/csrrci.yaml +++ b/arch/inst/Zicsr/csrrci.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zicsr/csrrs.yaml b/arch/inst/Zicsr/csrrs.yaml index 38b1ca38ae..5a5ea9f9cb 100644 --- a/arch/inst/Zicsr/csrrs.yaml +++ b/arch/inst/Zicsr/csrrs.yaml @@ -68,7 +68,3 @@ sail(): | RETIRE_SUCCESS } } - - - - diff --git a/arch/inst/Zicsr/csrrsi.yaml b/arch/inst/Zicsr/csrrsi.yaml index 2ad946d199..67f2cd1717 100644 --- a/arch/inst/Zicsr/csrrsi.yaml +++ b/arch/inst/Zicsr/csrrsi.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zicsr/csrrw.yaml b/arch/inst/Zicsr/csrrw.yaml index 0e4ba92c7a..9625c3895b 100644 --- a/arch/inst/Zicsr/csrrw.yaml +++ b/arch/inst/Zicsr/csrrw.yaml @@ -31,7 +31,7 @@ access: operation(): | if (rd != 0) { X[rd] = CSR[csr].sw_read(); - } + } # writes the value in X[rs1] to the CSR, # performing any WARL transformations first @@ -64,7 +64,3 @@ sail(): | RETIRE_SUCCESS } } - - - - diff --git a/arch/inst/Zicsr/csrrwi.yaml b/arch/inst/Zicsr/csrrwi.yaml index 7a304af4f9..1da44ef621 100644 --- a/arch/inst/Zicsr/csrrwi.yaml +++ b/arch/inst/Zicsr/csrrwi.yaml @@ -31,7 +31,7 @@ access: operation(): | if (rd != 0) { X[rd] = CSR[csr].sw_read(); - } + } # writes the zero-extended immediate to the CSR, # performing any WARL transformations first @@ -64,7 +64,3 @@ sail(): | RETIRE_SUCCESS } } - - - - diff --git a/arch/inst/Zifencei/fence.i.yaml b/arch/inst/Zifencei/fence.i.yaml index f829bb9618..63793c2f9a 100644 --- a/arch/inst/Zifencei/fence.i.yaml +++ b/arch/inst/Zifencei/fence.i.yaml @@ -53,7 +53,3 @@ operation(): | sail(): | { /* __barrier(Barrier_RISCV_i); */ RETIRE_SUCCESS } - - - - diff --git a/arch/inst/Zimop/mop.r.n.yaml b/arch/inst/Zimop/mop.r.n.yaml index bc90d9beb7..dcce06e567 100644 --- a/arch/inst/Zimop/mop.r.n.yaml +++ b/arch/inst/Zimop/mop.r.n.yaml @@ -93,4 +93,3 @@ pseudoinstructions: - when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x3) && (mop_r_t_27_26 == 0x3) to: mop.r.31 operation(): | - diff --git a/arch/inst/Zimop/mop.rr.n.yaml b/arch/inst/Zimop/mop.rr.n.yaml index e8de57ec70..4681771f11 100644 --- a/arch/inst/Zimop/mop.rr.n.yaml +++ b/arch/inst/Zimop/mop.rr.n.yaml @@ -45,4 +45,3 @@ pseudoinstructions: - when: (mop_rr_t_30 == 0x1) && (mop_rr_t_27_26 == 0x3) to: mop.rr.7 operation(): | - diff --git a/arch/inst/Zk/aes32dsi.yaml b/arch/inst/Zk/aes32dsi.yaml index 4c6a4b8fe4..e192c720b4 100644 --- a/arch/inst/Zk/aes32dsi.yaml +++ b/arch/inst/Zk/aes32dsi.yaml @@ -28,4 +28,3 @@ access: vu: always data_independent_timing: true operation(): | - diff --git a/arch/inst/Zk/aes32dsmi.yaml b/arch/inst/Zk/aes32dsmi.yaml index d94fef7d47..760aa80561 100644 --- a/arch/inst/Zk/aes32dsmi.yaml +++ b/arch/inst/Zk/aes32dsmi.yaml @@ -28,4 +28,3 @@ access: vu: always data_independent_timing: true operation(): | - diff --git a/arch/inst/Zk/aes32esi.yaml b/arch/inst/Zk/aes32esi.yaml index 378aa0670b..dde5813257 100644 --- a/arch/inst/Zk/aes32esi.yaml +++ b/arch/inst/Zk/aes32esi.yaml @@ -28,4 +28,3 @@ access: vu: always data_independent_timing: true operation(): | - diff --git a/arch/inst/Zk/aes32esmi.yaml b/arch/inst/Zk/aes32esmi.yaml index 879bf4114a..39a54cf930 100644 --- a/arch/inst/Zk/aes32esmi.yaml +++ b/arch/inst/Zk/aes32esmi.yaml @@ -28,4 +28,3 @@ access: vu: always data_independent_timing: true operation(): | - diff --git a/arch/inst/Zk/aes64ds.yaml b/arch/inst/Zk/aes64ds.yaml index 07ebdac8c1..61dfb89de8 100644 --- a/arch/inst/Zk/aes64ds.yaml +++ b/arch/inst/Zk/aes64ds.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: true operation(): | - diff --git a/arch/inst/Zk/aes64dsm.yaml b/arch/inst/Zk/aes64dsm.yaml index b4f744fd02..eef0dbbcba 100644 --- a/arch/inst/Zk/aes64dsm.yaml +++ b/arch/inst/Zk/aes64dsm.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: true operation(): | - diff --git a/arch/inst/Zk/aes64es.yaml b/arch/inst/Zk/aes64es.yaml index 4e50e40622..5963c7a06f 100644 --- a/arch/inst/Zk/aes64es.yaml +++ b/arch/inst/Zk/aes64es.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: true operation(): | - diff --git a/arch/inst/Zk/aes64esm.yaml b/arch/inst/Zk/aes64esm.yaml index af29db499e..3013b2a069 100644 --- a/arch/inst/Zk/aes64esm.yaml +++ b/arch/inst/Zk/aes64esm.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: true operation(): | - diff --git a/arch/inst/Zk/aes64im.yaml b/arch/inst/Zk/aes64im.yaml index d0ab1847c7..3b5a5388b3 100644 --- a/arch/inst/Zk/aes64im.yaml +++ b/arch/inst/Zk/aes64im.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: true operation(): | - diff --git a/arch/inst/Zk/aes64ks1i.yaml b/arch/inst/Zk/aes64ks1i.yaml index 30b9e1cfc5..48520c22dd 100644 --- a/arch/inst/Zk/aes64ks1i.yaml +++ b/arch/inst/Zk/aes64ks1i.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: true operation(): | - diff --git a/arch/inst/Zk/aes64ks2.yaml b/arch/inst/Zk/aes64ks2.yaml index a332f844cc..e2189ca925 100644 --- a/arch/inst/Zk/aes64ks2.yaml +++ b/arch/inst/Zk/aes64ks2.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: true operation(): | - diff --git a/arch/inst/Zk/pack.yaml b/arch/inst/Zk/pack.yaml index 49e915a75c..1a4a5d0488 100644 --- a/arch/inst/Zk/pack.yaml +++ b/arch/inst/Zk/pack.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: true operation(): | - diff --git a/arch/inst/Zk/packh.yaml b/arch/inst/Zk/packh.yaml index 3e8b5f79e3..6101e75fc9 100644 --- a/arch/inst/Zk/packh.yaml +++ b/arch/inst/Zk/packh.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: true operation(): | - diff --git a/arch/inst/Zk/packw.yaml b/arch/inst/Zk/packw.yaml index 12b2f0eb63..b7a986491a 100644 --- a/arch/inst/Zk/packw.yaml +++ b/arch/inst/Zk/packw.yaml @@ -29,4 +29,3 @@ pseudoinstructions: - when: (rs2 == 0x0) to: zext.h operation(): | - diff --git a/arch/inst/Zk/sha256sig0.yaml b/arch/inst/Zk/sha256sig0.yaml index 8a6ac1cb66..2ec32995d2 100644 --- a/arch/inst/Zk/sha256sig0.yaml +++ b/arch/inst/Zk/sha256sig0.yaml @@ -23,4 +23,3 @@ access: vu: always data_independent_timing: true operation(): | - diff --git a/arch/inst/Zk/sha256sig1.yaml b/arch/inst/Zk/sha256sig1.yaml index 3776129333..5534e26786 100644 --- a/arch/inst/Zk/sha256sig1.yaml +++ b/arch/inst/Zk/sha256sig1.yaml @@ -23,4 +23,3 @@ access: vu: always data_independent_timing: true operation(): | - diff --git a/arch/inst/Zk/sha256sum0.yaml b/arch/inst/Zk/sha256sum0.yaml index eda4a5c351..c80507c041 100644 --- a/arch/inst/Zk/sha256sum0.yaml +++ b/arch/inst/Zk/sha256sum0.yaml @@ -23,4 +23,3 @@ access: vu: always data_independent_timing: true operation(): | - diff --git a/arch/inst/Zk/sha256sum1.yaml b/arch/inst/Zk/sha256sum1.yaml index fa4876685f..94849b65e3 100644 --- a/arch/inst/Zk/sha256sum1.yaml +++ b/arch/inst/Zk/sha256sum1.yaml @@ -23,4 +23,3 @@ access: vu: always data_independent_timing: true operation(): | - diff --git a/arch/inst/Zk/sha512sig0.yaml b/arch/inst/Zk/sha512sig0.yaml index f7d4f909ad..65e4fecdac 100644 --- a/arch/inst/Zk/sha512sig0.yaml +++ b/arch/inst/Zk/sha512sig0.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: true operation(): | - diff --git a/arch/inst/Zk/sha512sig0h.yaml b/arch/inst/Zk/sha512sig0h.yaml index 872046027b..36e442d5ec 100644 --- a/arch/inst/Zk/sha512sig0h.yaml +++ b/arch/inst/Zk/sha512sig0h.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: true operation(): | - diff --git a/arch/inst/Zk/sha512sig0l.yaml b/arch/inst/Zk/sha512sig0l.yaml index df86a03562..b45759fe5c 100644 --- a/arch/inst/Zk/sha512sig0l.yaml +++ b/arch/inst/Zk/sha512sig0l.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: true operation(): | - diff --git a/arch/inst/Zk/sha512sig1.yaml b/arch/inst/Zk/sha512sig1.yaml index e75977bb4a..83965f0fe9 100644 --- a/arch/inst/Zk/sha512sig1.yaml +++ b/arch/inst/Zk/sha512sig1.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: true operation(): | - diff --git a/arch/inst/Zk/sha512sig1h.yaml b/arch/inst/Zk/sha512sig1h.yaml index 2ae02b4e36..6dacd3aadd 100644 --- a/arch/inst/Zk/sha512sig1h.yaml +++ b/arch/inst/Zk/sha512sig1h.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: true operation(): | - diff --git a/arch/inst/Zk/sha512sig1l.yaml b/arch/inst/Zk/sha512sig1l.yaml index c1f26069dd..e9312f90e4 100644 --- a/arch/inst/Zk/sha512sig1l.yaml +++ b/arch/inst/Zk/sha512sig1l.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: true operation(): | - diff --git a/arch/inst/Zk/sha512sum0.yaml b/arch/inst/Zk/sha512sum0.yaml index 3d8c409c60..86ab004387 100644 --- a/arch/inst/Zk/sha512sum0.yaml +++ b/arch/inst/Zk/sha512sum0.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: true operation(): | - diff --git a/arch/inst/Zk/sha512sum0r.yaml b/arch/inst/Zk/sha512sum0r.yaml index db81f95f54..c535ac0919 100644 --- a/arch/inst/Zk/sha512sum0r.yaml +++ b/arch/inst/Zk/sha512sum0r.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: true operation(): | - diff --git a/arch/inst/Zk/sha512sum1.yaml b/arch/inst/Zk/sha512sum1.yaml index ddc243d7da..ab6ab69deb 100644 --- a/arch/inst/Zk/sha512sum1.yaml +++ b/arch/inst/Zk/sha512sum1.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: true operation(): | - diff --git a/arch/inst/Zk/sha512sum1r.yaml b/arch/inst/Zk/sha512sum1r.yaml index b4fb002ac5..e1d04a9ab1 100644 --- a/arch/inst/Zk/sha512sum1r.yaml +++ b/arch/inst/Zk/sha512sum1r.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: true operation(): | - diff --git a/arch/inst/Zks/sm3p0.yaml b/arch/inst/Zks/sm3p0.yaml index 9c42bf2e9e..b0fbadc4a2 100644 --- a/arch/inst/Zks/sm3p0.yaml +++ b/arch/inst/Zks/sm3p0.yaml @@ -23,4 +23,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zks/sm3p1.yaml b/arch/inst/Zks/sm3p1.yaml index 6a51a96a1d..9931846057 100644 --- a/arch/inst/Zks/sm3p1.yaml +++ b/arch/inst/Zks/sm3p1.yaml @@ -23,4 +23,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zks/sm4ed.yaml b/arch/inst/Zks/sm4ed.yaml index b8512294cc..df729eb2f7 100644 --- a/arch/inst/Zks/sm4ed.yaml +++ b/arch/inst/Zks/sm4ed.yaml @@ -27,4 +27,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zks/sm4ks.yaml b/arch/inst/Zks/sm4ks.yaml index 9854e61b56..6ae18d806f 100644 --- a/arch/inst/Zks/sm4ks.yaml +++ b/arch/inst/Zks/sm4ks.yaml @@ -27,4 +27,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvbb/vandn.vv.yaml b/arch/inst/Zvbb/vandn.vv.yaml index 27667b63e5..4da0076e0f 100644 --- a/arch/inst/Zvbb/vandn.vv.yaml +++ b/arch/inst/Zvbb/vandn.vv.yaml @@ -27,4 +27,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvbb/vandn.vx.yaml b/arch/inst/Zvbb/vandn.vx.yaml index 252b3444cc..2ffe56347b 100644 --- a/arch/inst/Zvbb/vandn.vx.yaml +++ b/arch/inst/Zvbb/vandn.vx.yaml @@ -27,4 +27,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvbb/vbrev.v.yaml b/arch/inst/Zvbb/vbrev.v.yaml index 175e50f27d..71cebe3090 100644 --- a/arch/inst/Zvbb/vbrev.v.yaml +++ b/arch/inst/Zvbb/vbrev.v.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvbb/vbrev8.v.yaml b/arch/inst/Zvbb/vbrev8.v.yaml index 14df079e20..4a4007d42b 100644 --- a/arch/inst/Zvbb/vbrev8.v.yaml +++ b/arch/inst/Zvbb/vbrev8.v.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvbb/vclz.v.yaml b/arch/inst/Zvbb/vclz.v.yaml index 52776b73d7..4365156a78 100644 --- a/arch/inst/Zvbb/vclz.v.yaml +++ b/arch/inst/Zvbb/vclz.v.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvbb/vcpop.v.yaml b/arch/inst/Zvbb/vcpop.v.yaml index 0145035e4d..fefb67c383 100644 --- a/arch/inst/Zvbb/vcpop.v.yaml +++ b/arch/inst/Zvbb/vcpop.v.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvbb/vctz.v.yaml b/arch/inst/Zvbb/vctz.v.yaml index 0b03fbad5f..d059535764 100644 --- a/arch/inst/Zvbb/vctz.v.yaml +++ b/arch/inst/Zvbb/vctz.v.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvbb/vrev8.v.yaml b/arch/inst/Zvbb/vrev8.v.yaml index 79477546ea..6fad0de88c 100644 --- a/arch/inst/Zvbb/vrev8.v.yaml +++ b/arch/inst/Zvbb/vrev8.v.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvbb/vrol.vv.yaml b/arch/inst/Zvbb/vrol.vv.yaml index 1c54fa1040..cd07d39b11 100644 --- a/arch/inst/Zvbb/vrol.vv.yaml +++ b/arch/inst/Zvbb/vrol.vv.yaml @@ -27,4 +27,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvbb/vrol.vx.yaml b/arch/inst/Zvbb/vrol.vx.yaml index 395871d9e3..1210af58e9 100644 --- a/arch/inst/Zvbb/vrol.vx.yaml +++ b/arch/inst/Zvbb/vrol.vx.yaml @@ -27,4 +27,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvbb/vror.vi.yaml b/arch/inst/Zvbb/vror.vi.yaml index f2dc45e568..78eebbb5af 100644 --- a/arch/inst/Zvbb/vror.vi.yaml +++ b/arch/inst/Zvbb/vror.vi.yaml @@ -27,4 +27,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvbb/vror.vv.yaml b/arch/inst/Zvbb/vror.vv.yaml index 5289f2f82c..f2f40fe91a 100644 --- a/arch/inst/Zvbb/vror.vv.yaml +++ b/arch/inst/Zvbb/vror.vv.yaml @@ -27,4 +27,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvbb/vror.vx.yaml b/arch/inst/Zvbb/vror.vx.yaml index 40a3469c72..d2a77d6b71 100644 --- a/arch/inst/Zvbb/vror.vx.yaml +++ b/arch/inst/Zvbb/vror.vx.yaml @@ -27,4 +27,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvbb/vwsll.vi.yaml b/arch/inst/Zvbb/vwsll.vi.yaml index 86264addbd..591c1bed5f 100644 --- a/arch/inst/Zvbb/vwsll.vi.yaml +++ b/arch/inst/Zvbb/vwsll.vi.yaml @@ -27,4 +27,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvbb/vwsll.vv.yaml b/arch/inst/Zvbb/vwsll.vv.yaml index 4e6c43fd1d..2b3a21c375 100644 --- a/arch/inst/Zvbb/vwsll.vv.yaml +++ b/arch/inst/Zvbb/vwsll.vv.yaml @@ -27,4 +27,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvbb/vwsll.vx.yaml b/arch/inst/Zvbb/vwsll.vx.yaml index 56c02f8186..bee40592d9 100644 --- a/arch/inst/Zvbb/vwsll.vx.yaml +++ b/arch/inst/Zvbb/vwsll.vx.yaml @@ -27,4 +27,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvbc/vclmul.vv.yaml b/arch/inst/Zvbc/vclmul.vv.yaml index bb69c75efe..5546905fea 100644 --- a/arch/inst/Zvbc/vclmul.vv.yaml +++ b/arch/inst/Zvbc/vclmul.vv.yaml @@ -27,4 +27,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvbc/vclmul.vx.yaml b/arch/inst/Zvbc/vclmul.vx.yaml index 550a283921..9e965b1be5 100644 --- a/arch/inst/Zvbc/vclmul.vx.yaml +++ b/arch/inst/Zvbc/vclmul.vx.yaml @@ -27,4 +27,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvbc/vclmulh.vv.yaml b/arch/inst/Zvbc/vclmulh.vv.yaml index bce6dbdcff..4a077cfc01 100644 --- a/arch/inst/Zvbc/vclmulh.vv.yaml +++ b/arch/inst/Zvbc/vclmulh.vv.yaml @@ -27,4 +27,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvbc/vclmulh.vx.yaml b/arch/inst/Zvbc/vclmulh.vx.yaml index 5bd7e1ae36..ff4ed94672 100644 --- a/arch/inst/Zvbc/vclmulh.vx.yaml +++ b/arch/inst/Zvbc/vclmulh.vx.yaml @@ -27,4 +27,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvfbfmin/vfncvtbf16.f.f.w.yaml b/arch/inst/Zvfbfmin/vfncvtbf16.f.f.w.yaml index b1ee08cf45..c6e7afbed6 100644 --- a/arch/inst/Zvfbfmin/vfncvtbf16.f.f.w.yaml +++ b/arch/inst/Zvfbfmin/vfncvtbf16.f.f.w.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvfbfmin/vfwcvtbf16.f.f.v.yaml b/arch/inst/Zvfbfmin/vfwcvtbf16.f.f.v.yaml index 0da2a89c25..c5300811c6 100644 --- a/arch/inst/Zvfbfmin/vfwcvtbf16.f.f.v.yaml +++ b/arch/inst/Zvfbfmin/vfwcvtbf16.f.f.v.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvfbfwma/vfwmaccbf16.vf.yaml b/arch/inst/Zvfbfwma/vfwmaccbf16.vf.yaml index a80a385139..fa975d1b45 100644 --- a/arch/inst/Zvfbfwma/vfwmaccbf16.vf.yaml +++ b/arch/inst/Zvfbfwma/vfwmaccbf16.vf.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvfbfwma/vfwmaccbf16.vv.yaml b/arch/inst/Zvfbfwma/vfwmaccbf16.vv.yaml index d50b3db0d0..dc775e29b2 100644 --- a/arch/inst/Zvfbfwma/vfwmaccbf16.vv.yaml +++ b/arch/inst/Zvfbfwma/vfwmaccbf16.vv.yaml @@ -26,4 +26,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvkg/vghsh.vv.yaml b/arch/inst/Zvkg/vghsh.vv.yaml index ffaa788274..25cf67cf70 100644 --- a/arch/inst/Zvkg/vghsh.vv.yaml +++ b/arch/inst/Zvkg/vghsh.vv.yaml @@ -24,4 +24,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvkg/vgmul.vv.yaml b/arch/inst/Zvkg/vgmul.vv.yaml index a1d2dc1edd..c4e1a173f7 100644 --- a/arch/inst/Zvkg/vgmul.vv.yaml +++ b/arch/inst/Zvkg/vgmul.vv.yaml @@ -22,4 +22,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvkn/vaesdf.vs.yaml b/arch/inst/Zvkn/vaesdf.vs.yaml index 0996304f18..9a870b3d77 100644 --- a/arch/inst/Zvkn/vaesdf.vs.yaml +++ b/arch/inst/Zvkn/vaesdf.vs.yaml @@ -23,4 +23,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvkn/vaesdf.vv.yaml b/arch/inst/Zvkn/vaesdf.vv.yaml index aa4a6c059b..7ecb3e260b 100644 --- a/arch/inst/Zvkn/vaesdf.vv.yaml +++ b/arch/inst/Zvkn/vaesdf.vv.yaml @@ -23,4 +23,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvkn/vaesdm.vs.yaml b/arch/inst/Zvkn/vaesdm.vs.yaml index 68f3a30046..4f6ba265c4 100644 --- a/arch/inst/Zvkn/vaesdm.vs.yaml +++ b/arch/inst/Zvkn/vaesdm.vs.yaml @@ -23,4 +23,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvkn/vaesdm.vv.yaml b/arch/inst/Zvkn/vaesdm.vv.yaml index c3c043f209..3fc90fcec7 100644 --- a/arch/inst/Zvkn/vaesdm.vv.yaml +++ b/arch/inst/Zvkn/vaesdm.vv.yaml @@ -23,4 +23,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvkn/vaesef.vs.yaml b/arch/inst/Zvkn/vaesef.vs.yaml index c335467b3e..b3d18719d4 100644 --- a/arch/inst/Zvkn/vaesef.vs.yaml +++ b/arch/inst/Zvkn/vaesef.vs.yaml @@ -23,4 +23,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvkn/vaesef.vv.yaml b/arch/inst/Zvkn/vaesef.vv.yaml index 07d123a8fc..0e692cf83e 100644 --- a/arch/inst/Zvkn/vaesef.vv.yaml +++ b/arch/inst/Zvkn/vaesef.vv.yaml @@ -23,4 +23,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvkn/vaesem.vs.yaml b/arch/inst/Zvkn/vaesem.vs.yaml index 5744007528..7010af1bb2 100644 --- a/arch/inst/Zvkn/vaesem.vs.yaml +++ b/arch/inst/Zvkn/vaesem.vs.yaml @@ -23,4 +23,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvkn/vaesem.vv.yaml b/arch/inst/Zvkn/vaesem.vv.yaml index cb29270c01..ae5618f1d1 100644 --- a/arch/inst/Zvkn/vaesem.vv.yaml +++ b/arch/inst/Zvkn/vaesem.vv.yaml @@ -23,4 +23,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvkn/vaeskf1.vi.yaml b/arch/inst/Zvkn/vaeskf1.vi.yaml index acfc9c1f46..ea88d6459c 100644 --- a/arch/inst/Zvkn/vaeskf1.vi.yaml +++ b/arch/inst/Zvkn/vaeskf1.vi.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvkn/vaeskf2.vi.yaml b/arch/inst/Zvkn/vaeskf2.vi.yaml index bb5e680840..c00b3621dc 100644 --- a/arch/inst/Zvkn/vaeskf2.vi.yaml +++ b/arch/inst/Zvkn/vaeskf2.vi.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvkn/vaesz.vs.yaml b/arch/inst/Zvkn/vaesz.vs.yaml index 8d471a6155..970a9bae82 100644 --- a/arch/inst/Zvkn/vaesz.vs.yaml +++ b/arch/inst/Zvkn/vaesz.vs.yaml @@ -23,4 +23,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvkn/vsha2ch.vv.yaml b/arch/inst/Zvkn/vsha2ch.vv.yaml index c7c3072897..d29bd4d82e 100644 --- a/arch/inst/Zvkn/vsha2ch.vv.yaml +++ b/arch/inst/Zvkn/vsha2ch.vv.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvkn/vsha2cl.vv.yaml b/arch/inst/Zvkn/vsha2cl.vv.yaml index af0a15046a..9aa0dd3c20 100644 --- a/arch/inst/Zvkn/vsha2cl.vv.yaml +++ b/arch/inst/Zvkn/vsha2cl.vv.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvkn/vsha2ms.vv.yaml b/arch/inst/Zvkn/vsha2ms.vv.yaml index 3ed25d80f7..57e5cea2c3 100644 --- a/arch/inst/Zvkn/vsha2ms.vv.yaml +++ b/arch/inst/Zvkn/vsha2ms.vv.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvks/vsm3c.vi.yaml b/arch/inst/Zvks/vsm3c.vi.yaml index ce7ee47ade..03d5de481a 100644 --- a/arch/inst/Zvks/vsm3c.vi.yaml +++ b/arch/inst/Zvks/vsm3c.vi.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvks/vsm3me.vv.yaml b/arch/inst/Zvks/vsm3me.vv.yaml index 083bc526b0..25b76850b5 100644 --- a/arch/inst/Zvks/vsm3me.vv.yaml +++ b/arch/inst/Zvks/vsm3me.vv.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvks/vsm4k.vi.yaml b/arch/inst/Zvks/vsm4k.vi.yaml index fb641d68f9..14056756f2 100644 --- a/arch/inst/Zvks/vsm4k.vi.yaml +++ b/arch/inst/Zvks/vsm4k.vi.yaml @@ -25,4 +25,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvks/vsm4r.vs.yaml b/arch/inst/Zvks/vsm4r.vs.yaml index 9fa81255a6..e21b716374 100644 --- a/arch/inst/Zvks/vsm4r.vs.yaml +++ b/arch/inst/Zvks/vsm4r.vs.yaml @@ -23,4 +23,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/inst/Zvks/vsm4r.vv.yaml b/arch/inst/Zvks/vsm4r.vv.yaml index 40f6c8b670..e1d60fd3d8 100644 --- a/arch/inst/Zvks/vsm4r.vv.yaml +++ b/arch/inst/Zvks/vsm4r.vv.yaml @@ -23,4 +23,3 @@ access: vu: always data_independent_timing: false operation(): | - diff --git a/arch/isa/builtin_functions.idl b/arch/isa/builtin_functions.idl index 0769847528..9c47a0cb48 100644 --- a/arch/isa/builtin_functions.idl +++ b/arch/isa/builtin_functions.idl @@ -422,11 +422,11 @@ builtin function atomically_set_pte_a { U32 pte_len description { Atomically: - + * Reads the _pte_len_ value at _pte_addr_ ** If the read value does not exactly equal pte_value, returns false * Sets the 'A' bit and writes the result to _pte_addr_ - * return true + * return true Preconditions: @@ -442,7 +442,7 @@ builtin function atomically_set_pte_a_d { U32 pte_len description { Atomically: - + * Reads the _pte_len_ value at _pte_addr_ ** If the read value does not exactly equal pte_value, returns false * Sets the 'A' and 'D' bits and writes the result to _pte_addr_ diff --git a/arch/isa/fp.idl b/arch/isa/fp.idl index fcaeb70d26..62c018d1ce 100644 --- a/arch/isa/fp.idl +++ b/arch/isa/fp.idl @@ -314,7 +314,7 @@ function softfloat_shiftRightJam64 { be zero. If any nonzero bits are shifted off, they are "jammed" into the least-significant bit of the shifted value by setting the least-significant bit to 1. This shifted-and-jammed value is returned. - + The value of 'dist' can be arbitrarily large. In particular, if +dist+ is greater than 64, the result will be either 0 or 1, depending on whether +a+ is zero or nonzero. @@ -484,4 +484,4 @@ function softfloat_normRoundPackToF32 { return softfloat_roundPackToF32(sign, exp, sig << shiftDist, mode); } } -} \ No newline at end of file +} diff --git a/arch/isa/globals.isa b/arch/isa/globals.isa index 4145e7391f..1c47f17720 100644 --- a/arch/isa/globals.isa +++ b/arch/isa/globals.isa @@ -887,7 +887,7 @@ function pmp_match_64 { arguments Bits paddr description { Given a physical address, see if any PMP entry matches. - + If there is a complete match, return the PmpCfg that guards the region. If there is no match or a partial match, report that result. } @@ -955,7 +955,7 @@ function pmp_match_32 { arguments Bits paddr description { Given a physical address, see if any PMP entry matches. - + If there is a complete match, return the PmpCfg that guards the region. If there is no match or a partial match, report that result. } @@ -1023,7 +1023,7 @@ function pmp_match { arguments Bits paddr description { Given a physical address, see if any PMP entry matches. - + If there is a complete match, return the PmpCfg that guards the region. If there is no match or a partial match, report that result. } @@ -1423,7 +1423,7 @@ function translate_gstage { raise_guest_page_fault(op, gpaddr, vaddr, tinst_value_for_guest_page_fault(op, encoding, true), effective_mode); } } - } + } } function tinst_value_for_guest_page_fault { @@ -1715,7 +1715,7 @@ function gstage_page_walk { # first level is x4 for G-stage, so add two bits to the vpn size U32 this_vpn_size = (i == (LEVELS - 1)) ? VPN_SIZE + 2 : VPN_SIZE; U32 vpn = (gpaddr >> (12 + VPN_SIZE*i)) & ((1 << this_vpn_size) - 1); - + Bits pte_paddr = (ppn << 12) + (vpn * (PTESIZE/8)); # check hw page table access permission @@ -2219,7 +2219,7 @@ function translate { +effective_mode+. The translation will depend on the effective privilege mode. - + May raise a Page Fault or Access Fault. The final physical address is *not* access checked (for PMP, PMA, etc., violations). @@ -2251,7 +2251,7 @@ function translate { # there is no translation in M-mode return vaddr; } - + SatpMode translation_mode = current_translation_mode(effective_mode); @@ -2317,7 +2317,7 @@ function canonical_vaddr? { return true; } else if (satp_mode == SatpMode::Sv32) { # Sv32 uses all 32 bits of the VA - return true; + return true; } else if (satp_mode == SatpMode::Sv39) { return eaddr[63:39] == {25{eaddr[38]}}; } else if (satp_mode == SatpMode::Sv48) { @@ -2343,7 +2343,7 @@ function canonical_gpaddr? { return true; } else if (satp_mode == SatpMode::Sv32) { # Sv32 uses all 32 bits of the VA - return true; + return true; } else if ((XLEN > 32) && (satp_mode == SatpMode::Sv39)) { return gpaddr[63:39] == {25{gpaddr[38]}}; } else if ((XLEN > 32) && (satp_mode == SatpMode::Sv48)) { @@ -2430,7 +2430,7 @@ function read_memory { if (aligned) { return read_memory_aligned(virtual_address, encoding); } - + # access isn't naturally aligned, but it still might be atomic if this hart supports # Misliagned Atomicity Granules. We won't know that, though, until after translation since PMAs # apply to physical addresses @@ -2754,7 +2754,7 @@ function write_memory { if (aligned) { write_memory_aligned(virtual_address, value, encoding); } - + # access isn't naturally aligned, but it still might be atomic if this hart supports # Misliagned Atomicity Granules. We won't know that, though, until after translation since PMAs # apply to physical addresses diff --git a/arch/isa/util.idl b/arch/isa/util.idl index 3b8370c89f..097b51ccb2 100644 --- a/arch/isa/util.idl +++ b/arch/isa/util.idl @@ -177,7 +177,7 @@ function in_naturally_aligned_region? { } body { XReg Mask = (N/8) - 1; - + return (address & ~Mask) == ((address + length - 1) & ~Mask); } } @@ -199,4 +199,4 @@ function contains? { target_start >= region_start && (target_start + target_size) <= (region_start + region_size); } -} \ No newline at end of file +} diff --git a/arch/manual/isa/20240411/contents.yaml b/arch/manual/isa/20240411/contents.yaml index 91901d70a2..3ade2dea11 100644 --- a/arch/manual/isa/20240411/contents.yaml +++ b/arch/manual/isa/20240411/contents.yaml @@ -218,4 +218,4 @@ volumes: - [Svvptc, "1.0.0"] - [Sstc, "1.0.0"] - [Sscofpmf, "1.0.0"] - - [H, "1.0.0"] \ No newline at end of file + - [H, "1.0.0"] diff --git a/arch/manual/isa/isa.yaml b/arch/manual/isa/isa.yaml index ed762ec096..7d573628b3 100644 --- a/arch/manual/isa/isa.yaml +++ b/arch/manual/isa/isa.yaml @@ -5,4 +5,4 @@ license: id: CC-BY-4.0 name: Creative Commons Attribution 4.0 International Public License url: https://creativecommons.org/licenses/by/4.0/legalcode -# versions are found in by search all subdirectories for "contents.yaml" \ No newline at end of file +# versions are found in by search all subdirectories for "contents.yaml" diff --git a/arch/profile_class/MockProfileClass.yaml b/arch/profile_class/MockProfileClass.yaml index d7f2af6e7e..613e4460b1 100644 --- a/arch/profile_class/MockProfileClass.yaml +++ b/arch/profile_class/MockProfileClass.yaml @@ -12,4 +12,4 @@ MockProfileClass: doc_license: name: Creative Commons Attribution 4.0 International License url: https://creativecommons.org/licenses/by/4.0/ - text_url: https://creativecommons.org/licenses/by/4.0/legalcode.txt \ No newline at end of file + text_url: https://creativecommons.org/licenses/by/4.0/legalcode.txt diff --git a/arch/profile_class/RVA.yaml b/arch/profile_class/RVA.yaml index db88fc9ccc..9c0df8d1ad 100644 --- a/arch/profile_class/RVA.yaml +++ b/arch/profile_class/RVA.yaml @@ -18,18 +18,18 @@ RVA: substantial fraction of software to be delivered to end-customers in binary form, compatibility across multiple implementations from different RISC-V vendors is required. - + The RVIA ISA extension ratification process ensures that all processor vendors have agreed to the specification of a standard extension if present. However, by themselves, the ISA extension specifications do not guarantee that a certain set of standard extensions will be present in all implementations. - + *The primary goal of the RVA profiles is to align processor vendors targeting binary software markets, so software can rely on the existence of a certain set of ISA features in a particular generation of RISC-V implementations.* - + Alignment is not only for compatibility, but also to ensure RISC-V is competitive in these markets. The binary app markets are also generally those with the most competitive performance requirements @@ -48,7 +48,7 @@ RVA: for certain limited cases, and binary app markets will not support a wide range of optional features, particularly for the nascent RISC-V binary app ecosystems. - + To maintain alignment and increase RISC-V competitiveness over time, the mandatory set of extensions must increase over time in successive generations of RVA profile. (RVA profiles may eventually have to @@ -63,11 +63,11 @@ RVA: considerable investment, and no single binary app ecosystem can justify the development costs of these processors, especially for RISC-V in its early stage of adoption. - + While the heart of the profile is the set of mandatory extensions, there are several kinds of optional extension that serve important roles in the profile. - + The first kind are _localized_ _options_, whose presence or use necessarily differs along geo-political and/or jurisdictional boundaries, with crypto being the obvious example. These will always @@ -75,7 +75,7 @@ RVA: perfectly acceptable to handle this optionality on other architectures, as the use of the extensions is well contained in certain libraries. - + The second kind of optional extension is a _development_ _option_, which represents a new ISA extension in an early part of its lifecycle but which is intended to become mandatory in a later generation of the @@ -87,7 +87,7 @@ RVA: Denoting an extension as a _development_ _option_ signals to the community that development should be prioritized for such extensions as they will become mandatory. - + The third kind of optional extension are _expansion_ _options_, which are those that may have a large implementation cost but are not always needed in a particular platform, and which can be readily handled by @@ -99,7 +99,7 @@ RVA: future matrix extensions. These have large implementation costs, and use of matrix instructions can be readily supported with discovery and alternate math libraries. - + The fourth kind of optional extensions are _transitory_ _options_, where it is not clear if the extension will change to a mandatory, localized, or expansion option, or be possibly dropped over time. @@ -113,7 +113,7 @@ RVA: term. Denoting an option as transitory signals to the community that this extension may be removed in a future profile, though the time scale may span many years. - + Except for the localized options, it could be argued that other three kinds of option could be left out of profiles. Binary distributions of applications willing to invest in discovery can use an optional @@ -142,4 +142,4 @@ RVA: doc_license: name: Creative Commons Attribution 4.0 International License url: https://creativecommons.org/licenses/by/4.0/ - text_url: https://creativecommons.org/licenses/by/4.0/legalcode.txt \ No newline at end of file + text_url: https://creativecommons.org/licenses/by/4.0/legalcode.txt diff --git a/arch/profile_class/RVB.yaml b/arch/profile_class/RVB.yaml index f9529ef1db..ea4239f699 100644 --- a/arch/profile_class/RVB.yaml +++ b/arch/profile_class/RVB.yaml @@ -47,4 +47,4 @@ RVB: doc_license: name: Creative Commons Attribution 4.0 International License url: https://creativecommons.org/licenses/by/4.0/ - text_url: https://creativecommons.org/licenses/by/4.0/legalcode.txt \ No newline at end of file + text_url: https://creativecommons.org/licenses/by/4.0/legalcode.txt diff --git a/arch/profile_class/RVI.yaml b/arch/profile_class/RVI.yaml index ed900ef3d5..daad9e90c3 100644 --- a/arch/profile_class/RVI.yaml +++ b/arch/profile_class/RVI.yaml @@ -3,7 +3,7 @@ RVI: introduction: The RVI profile class documents the initial set of unprivileged instructions. description: | The RVI profile class provides a generic target for software toolchains - and represent the minimum level of compatibility with RISC-V ratified standards. + and represent the minimum level of compatibility with RISC-V ratified standards. NOTE: Profiles in this class are designated as _unprivileged_ profiles as opposed to _user_-_mode_ profiles. Code using this profile class can run in any @@ -25,4 +25,4 @@ RVI: doc_license: name: Creative Commons Attribution 4.0 International License url: https://creativecommons.org/licenses/by/4.0/ - text_url: https://creativecommons.org/licenses/by/4.0/legalcode.txt \ No newline at end of file + text_url: https://creativecommons.org/licenses/by/4.0/legalcode.txt diff --git a/arch/profile_release/MockProfileRelease.yaml b/arch/profile_release/MockProfileRelease.yaml index 45104cdec2..6b18b173de 100644 --- a/arch/profile_release/MockProfileRelease.yaml +++ b/arch/profile_release/MockProfileRelease.yaml @@ -4,7 +4,7 @@ MockProfileRelease: class: MockProfileClass release: 20 state: ratified # current status ["ratified", "development"] - versions: + versions: - version: "1.0" ratification_date: "2024-01-01" introduction: Here's the Mock Profile Release introduction. @@ -50,21 +50,21 @@ MockProfileRelease: presence: mandatory note: This should be listed as mandatory in MP-S-64 and optional in MP-U-64. S: - presence: + presence: optional: localized version: "~> 1.12" Zifencei: - presence: + presence: optional: development version: "~> 2.0" - note: + note: Zihpm: - presence: + presence: optional: expansion version: "~> 2.0" note: Made this a expansion option Sv48: - presence: + presence: optional: transitory version: "~> 1.11" note: Made this a transitory option @@ -78,23 +78,23 @@ MockProfileRelease: Here's the first extra note for the optional extensions section. In this case, we don't differentiate between optional types. This note is multiple lines. - - presence: + - presence: optional: localized text: Here's the first extra note for the localized optional extensions section. - - presence: + - presence: optional: localized text: Here's the second extra note for the localized optional extensions section. - - presence: + - presence: optional: development text: Here's the first extra note for the development optional extensions section. - - presence: + - presence: optional: expansion text: Here's the first extra note for the expansion optional extensions section. - - presence: + - presence: optional: transitory text: Here's the first extra note for the transitory optional extensions section. recommendations: - text: | Implementations are strongly recommended to raise illegal-instruction exceptions on attempts to execute unimplemented opcodes. - - text: Micky should give Pluto an extra treat \ No newline at end of file + - text: Micky should give Pluto an extra treat diff --git a/arch/profile_release/RVA20.yaml b/arch/profile_release/RVA20.yaml index 279024c2c1..b920ef7176 100644 --- a/arch/profile_release/RVA20.yaml +++ b/arch/profile_release/RVA20.yaml @@ -7,7 +7,7 @@ RVA20: ratification_date: "2023-04-03" # Semantic versions within the release - versions: + versions: - version: "1.0.0" introduction: | @@ -162,7 +162,7 @@ RVA20: version: "~> 1.0" note: | Svbare is a new extension name introduced with RVA20. - + It is subsequently defined in more detail with the ratification of `Svadu`. Ssccptr: @@ -187,4 +187,4 @@ RVA20: presence: optional version: "~> 1.0" note: | - Ssu64xl is a new extension name introduced with RVA20. \ No newline at end of file + Ssu64xl is a new extension name introduced with RVA20. diff --git a/arch/profile_release/RVA22.yaml b/arch/profile_release/RVA22.yaml index 9cf0c14e97..3df8200624 100644 --- a/arch/profile_release/RVA22.yaml +++ b/arch/profile_release/RVA22.yaml @@ -7,7 +7,7 @@ RVA22: ratification_date: "2023-04-03" # Semantic versions within the release - versions: + versions: - version: "1.0.0" introduction: | @@ -124,7 +124,7 @@ RVA22: The smaller vector extensions (Zve32f, Zve32x, Zve64d, Zve64f, Zve64x) are not provided as separately supported profile options. The full V extension is specified as the only supported profile option. - + A future profile might mandate V. Zkn: presence: optional @@ -255,7 +255,7 @@ RVA22: version: "~> 1.0" note: | The following extensions become mandatory when H is implemented: - + * Ssstateen * Shcounterenw * Shvstvala @@ -265,4 +265,4 @@ RVA22: recommendations: - text: | Implementations are strongly recommended to raise illegal-instruction - exceptions on attempts to execute unimplemented opcodes. \ No newline at end of file + exceptions on attempts to execute unimplemented opcodes. diff --git a/arch/profile_release/RVI20.yaml b/arch/profile_release/RVI20.yaml index 07e8e10811..3bd5b67504 100644 --- a/arch/profile_release/RVI20.yaml +++ b/arch/profile_release/RVI20.yaml @@ -7,7 +7,7 @@ RVI20: ratification_date: "2023-04-03" # Semantic versions within the release - versions: + versions: - version: "1.0.0" introduction: | @@ -31,14 +31,14 @@ RVI20: version: "~> 2.1" note: | RVI is the mandatory base ISA for RVA, and is little-endian. - + As per the unprivileged architecture specification, the `ecall` instruction causes a requested trap to the execution environment. - + Misaligned loads and stores might not be supported. - + The `fence.tso` instruction is mandatory. - + NOTE: The `fence.tso` instruction was incorrectly described as optional in the 2019 ratified specifications. However, `fence.tso` is encoded within the standard `fence` encoding such that implementations @@ -86,4 +86,4 @@ RVI20: RVI20U64: $inherits: "#/RVI20/profiles/RVI20U32" base: 64 - marketing_name: RVI20U64 \ No newline at end of file + marketing_name: RVI20U64 diff --git a/arch/prose/idl.adoc b/arch/prose/idl.adoc index d8f4bdb243..a67cdbadba 100644 --- a/arch/prose/idl.adoc +++ b/arch/prose/idl.adoc @@ -367,7 +367,7 @@ Literals may contain any number of underscores after the initial digit for clari # gotcha -17 # 15 decimal: the literal is 17, unsigned, in 5-bits. when negated, the sign bit lost --13 # 3 decimal: the literal is 13, unsigned, in 4-bits. when negated, the sign bit is lost +-13 # 3 decimal: the literal is 13, unsigned, in 4-bits. when negated, the sign bit is lost ---- @@ -425,7 +425,7 @@ The result of a binary operation is signed if both operands are signed; otherwis .2+| 0 | `i[idx]` | `Bits<1>` | Extract a single bit from bit position `idx`. + `i` must be an integral type or an array. + Result is unsigned, regardless of the sign of `i`. - + | `i[msb:lsb]` | `Bits` | Extract a range of bits between `msb` and `lsb`, inclusive. + `i` must be an integral type. + Result is unsigned, regardless of the sign of `i`. @@ -470,19 +470,19 @@ The result of a binary operation is signed if both operands are signed; otherwis | `i - j` | `Bits` | Subtraction + The carry bit is discarded. + - If the carry bit is needed, the operands can be widened prior to subtraction. + If the carry bit is needed, the operands can be widened prior to subtraction. -.3+| 8 | `i << j` a| +.3+| 8 | `i << j` a| [%autowidth] !=== ! When ! Then ! `j` is literal ! `Bits` ! `j` is variable ! `typeof(i)` -!=== +!=== | Left logical shift. + When the shift amount is known at compile time, the result is widened to not lose any data. + When the shift amount is not known at compile time, the shifted bits are discarded. - + | `i >> j` | `typeof(i)` | Right logical shift. | `i >>> j` | `typeof(i)` | Right arithmetic shift. @@ -519,7 +519,7 @@ The result of a binary operation is signed if both operands are signed; otherwis === Mutable variables -Variables must be declared with a type. Variable names must begin with a lowercase letter and can be followed by any number of letters (any case), numbers, or an underscore. +Variables must be declared with a type. Variable names must begin with a lowercase letter and can be followed by any number of letters (any case), numbers, or an underscore. Variables may be optionally initialized when they are declared using the assignment operator. Variables that are not explicitly initialized are implicitly initialized to zero (for Bits) or false (for Boolean). @@ -553,7 +553,7 @@ Two builtin variables exist: | Name | Type | Scope | Description | `$pc` | `Bits` | Global | The current program counter of the hart -| `$encoding` | `Bits`, where VARIABLE is the length of the last fetched insruction | Instruction, Csr | The encoding of the last fetched instruction. Only accessible in Instruction scope and Csr scope (cannot be used in functions). +| `$encoding` | `Bits`, where VARIABLE is the length of the last fetched insruction | Instruction, Csr | The encoding of the last fetched instruction. Only accessible in Instruction scope and Csr scope (cannot be used in functions). |=== === Constants @@ -590,7 +590,7 @@ All configuration parameters are added to Global scope for compilation. == Type conversions -Type conversions occur when dissimilar types are used in some binary operators or assignments. +Type conversions occur when dissimilar types are used in some binary operators or assignments. `Bits` types are converted as follows: @@ -767,7 +767,7 @@ Functions must be given a textual description; this is to promote IDL as an exec All arguments and return values are passed by value. There are no references or variable addresses in IDL. -Functions must live in global scope. Functions cannot be nested. +Functions must live in global scope. Functions cannot be nested. A function may return zero or more values of any valid type. A function may accept zero or more arguments of any valid type. @@ -781,7 +781,7 @@ IDL supports templated functions that take a compile-time-known constant as an a IDL only supports template values (_i.e._, you cannot pass a type as a template argument). Template values must be a Bits type. -Template functions are called using C++-style syntax, with the template argument enclosed in angle brackets. +Template functions are called using C++-style syntax, with the template argument enclosed in angle brackets. IDL cannot infer template arguments; they must be provided explictly. @@ -939,7 +939,7 @@ instret: field.sw_write(csr_value):: -The "sw_write(csr_value)" function of a CSR field executes when a software write (via a `Zicsr` instruction) occurs. It takes a single value, `csr_value`, that is an implicitly-defined bitfield of the CSR populated with the values software is trying to write. It returns a Bits value repsenting what hardware is actually going to write into the field, where N is the width of the field. sw_write may also return the special value `UNDEFINED_LEGAL_DETERMINISTIC` to indicate that the written value is undefined, but it will be a legal value for the field and is deterministically determined based on the sequence of instructions leading to the write. +The "sw_write(csr_value)" function of a CSR field executes when a software write (via a `Zicsr` instruction) occurs. It takes a single value, `csr_value`, that is an implicitly-defined bitfield of the CSR populated with the values software is trying to write. It returns a Bits value repsenting what hardware is actually going to write into the field, where N is the width of the field. sw_write may also return the special value `UNDEFINED_LEGAL_DETERMINISTIC` to indicate that the written value is undefined, but it will be a legal value for the field and is deterministically determined based on the sequence of instructions leading to the write. [NOTE] Note that the sw_read is specified for the entire CSR and the sw_write is specified for a CSR field. diff --git a/arch/prose/interrupts.adoc b/arch/prose/interrupts.adoc index 935c96cab9..82571cac88 100644 --- a/arch/prose/interrupts.adoc +++ b/arch/prose/interrupts.adoc @@ -1,7 +1,7 @@ [[sec:interrupts]] = Interrupts -== Machine Interrupt (`mip` and `mie`) Registers +== Machine Interrupt (`mip` and `mie`) Registers The `mip` register is an MXLEN-bit read/write register containing information on pending interrupts, while `mie` is the corresponding @@ -179,4 +179,4 @@ Restricted views of the `mip` and `mie` registers appear as the `sip` and `sie` registers for supervisor level. If an interrupt is delegated to S-mode by setting a bit in the `mideleg` register, it becomes visible in the `sip` register and is maskable using the `sie` register. -Otherwise, the corresponding bits in `sip` and `sie` are read-only zero. \ No newline at end of file +Otherwise, the corresponding bits in `sip` and `sie` are read-only zero. diff --git a/backends/arch_gen/lib/arch_gen.rb b/backends/arch_gen/lib/arch_gen.rb index 7f424fd6ff..e888579235 100644 --- a/backends/arch_gen/lib/arch_gen.rb +++ b/backends/arch_gen/lib/arch_gen.rb @@ -165,7 +165,7 @@ def params_extra_validation private :params_extra_validation # validate the params.yaml file of a config. - # + # # This does several things: # # * Generates a config-specific schmea based on: @@ -314,13 +314,13 @@ def gen_arch_def manual_info_files = Dir.glob($root / "arch" / "manual" / "**" / "#{manual_id}.yaml") raise "Could not find manual info '#{manual_id}'.yaml, needed by #{f}" if manual_info_files.empty? raise "Found multiple manual infos '#{manual_id}'.yaml, needed by #{f}" if manual_info_files.size > 1 - + manual_info_file = manual_info_files.first manual_hash[manual_id] = YamlLoader.load(manual_info_file, permitted_classes:[Date]) manual_hash[manual_id]["__source"] = manual_info_file # TODO: schema validation end - + manual_hash[manual_id]["versions"] ||= [] manual_hash[manual_id]["versions"] << YamlLoader.load(f, permitted_classes:[Date]) # TODO: schema validation @@ -645,7 +645,7 @@ def maybe_add_csr(csr_name, extra_env = {}) end belongs = csr_obj.exists_in_cfg?(arch_def_mock) - + @implemented_csrs ||= [] @implemented_csrs << csr_name if belongs diff --git a/backends/arch_gen/tasks.rake b/backends/arch_gen/tasks.rake index e8ebbf40d9..fca19e28ef 100644 --- a/backends/arch_gen/tasks.rake +++ b/backends/arch_gen/tasks.rake @@ -134,7 +134,7 @@ rule %r{#{$root}/\.stamps/arch-gen-.*\.stamp} => proc { |tname| "#{ARCH_GEN_DIR}/tasks.rake", arch_files, config_files, - + # the stamp file is not actually dependent on the Ruby object model, # but in general we want to rebuild anything using this stamp when the object model changes obj_model_files.map(&:to_s) diff --git a/backends/certificate_doc/tasks.rake b/backends/certificate_doc/tasks.rake index 106c38c11b..33c3d0d296 100644 --- a/backends/certificate_doc/tasks.rake +++ b/backends/certificate_doc/tasks.rake @@ -17,7 +17,7 @@ Dir.glob("#{$root}/arch/certificate_model/*.yaml") do |f| base = cert_model_obj["base"] raise "Missing certificate model base" if base.nil? - + file "#{$root}/gen/certificate_doc/adoc/#{cert_model_name}.adoc" => [ "#{$root}/arch/certificate_model/#{cert_model_name}.yaml", "#{$root}/arch/certificate_class/#{cert_class_name}.yaml", @@ -40,7 +40,7 @@ Dir.glob("#{$root}/arch/certificate_model/*.yaml") do |f| erb = ERB.new(File.read("#{CERT_DOC_DIR}/templates/certificate.adoc.erb"), trim_mode: "-") erb.filename = "#{CERT_DOC_DIR}/templates/certificate.adoc.erb" - + FileUtils.mkdir_p File.dirname(t.name) File.write t.name, AsciidocUtils.resolve_links(arch_def.find_replace_links(erb.result(binding))) puts "Generated adoc source at #{t.name}" @@ -122,4 +122,4 @@ namespace :gen do Rake::Task["#{$root}/gen/certificate_doc/html/#{args[:cert_model_name]}.html"].invoke end -end \ No newline at end of file +end diff --git a/backends/certificate_doc/templates/certificate.adoc.erb b/backends/certificate_doc/templates/certificate.adoc.erb index b71e4d1d47..740a98f763 100644 --- a/backends/certificate_doc/templates/certificate.adoc.erb +++ b/backends/certificate_doc/templates/certificate.adoc.erb @@ -1,5 +1,5 @@ // Number heading sections (e.g., 1.0, 1.1, etc.) -:sectnums: +:sectnums: // Add a table of contents for HTML (and VSCode adoc preview) :toc: left @@ -27,7 +27,7 @@ History of documentation changes that eventually lead to releases. | Date | Revision | Changes <% cert_model.revision_history.each do |rev| -%> -| <%= rev.date %> +| <%= rev.date %> | <%= rev.revision %> a| <% rev.changes.each do |change| %> * <%= change %> @@ -118,8 +118,8 @@ None <% ext_reqs.sort.each do |ext_req| -%> <% ext = arch_def.extension(ext_req.name) -%> -| <%= ext_req.req_id %> -| <-def,<%= ext_req.name %>>> +| <%= ext_req.req_id %> +| <-def,<%= ext_req.name %>>> | <%= ext_req.version_requirement %> | <%= ext.nil? ? "" : ext.long_name %> | <%= ext_req.note.nil? ? "" : ext_req.note %> @@ -153,7 +153,7 @@ not provided in the associated standard. === IN-SCOPE Parameters -These implementation-dependent options defined by MANDATORY or OPTIONAL extensions are IN-SCOPE. +These implementation-dependent options defined by MANDATORY or OPTIONAL extensions are IN-SCOPE. An implementation must abide by the "Allowed Value(s)" to obtain a certificate. If the "Allowed Value(s)" is "Any" then any value allowed by the type is acceptable. @@ -178,8 +178,8 @@ a| <%= in_scope_ext_param.note %> === OUT-OF-SCOPE Parameters -These implementation-dependent options defined by MANDATORY or OPTIONAL extensions are OUT-OF-SCOPE. -There are no restrictions on their values for certification purposes because the certificate +These implementation-dependent options defined by MANDATORY or OPTIONAL extensions are OUT-OF-SCOPE. +There are no restrictions on their values for certification purposes because the certificate doesn't cover the behavior of the associated RISC-V standard as a function of these parameters. <% if cert_model.all_out_of_scope_params.empty? -%> @@ -309,7 +309,7 @@ Requirement <%= req.name %> only apply when <%= req.when_pretty %>. Changes::: <% v.changes.each do |c| -%> - * <%= c %> + * <%= c %> <% end -%> <% end -%> @@ -413,20 +413,20 @@ This instruction has different encodings in RV32 and RV64. RV32:: + [wavedrom, ,svg,subs='attributes',width="100%"] -.... +.... <%= JSON.dump inst.wavedrom_desc(32) %> .... RV64:: + [wavedrom, ,svg,subs='attributes',width="100%"] -.... +.... <%= JSON.dump inst.wavedrom_desc(64) %> .... ==== <% else -%> [wavedrom, ,svg,subs='attributes',width="100%"] -.... +.... <%= JSON.dump inst.wavedrom_desc(inst.base.nil? ? 32 : inst.base) %> .... <% end -%> @@ -689,4 +689,4 @@ This CSR may return a value that is different from what is stored in hardware. ---- <%- end -%> -<% end # do csrs -%> \ No newline at end of file +<% end # do csrs -%> diff --git a/backends/cfg_html_doc/templates/ext.adoc.erb b/backends/cfg_html_doc/templates/ext.adoc.erb index 1808e49413..eaa8d34ef2 100644 --- a/backends/cfg_html_doc/templates/ext.adoc.erb +++ b/backends/cfg_html_doc/templates/ext.adoc.erb @@ -15,7 +15,7 @@ Implemented Version:: <%= ext_version.version %> Changes::: <% v.changes.each do |c| -%> - * <%= c %> + * <%= c %> <% end -%> <%- end -%> @@ -62,4 +62,4 @@ This extension has the following implementation options: -- <%- end -%> -<%- end -%> \ No newline at end of file +<%- end -%> diff --git a/backends/cfg_html_doc/templates/func.adoc.erb b/backends/cfg_html_doc/templates/func.adoc.erb index 83eb37aafd..3c281bbff7 100644 --- a/backends/cfg_html_doc/templates/func.adoc.erb +++ b/backends/cfg_html_doc/templates/func.adoc.erb @@ -35,4 +35,4 @@ Pruned:: ==== <%- end -%> -<%- end -%> \ No newline at end of file +<%- end -%> diff --git a/backends/cfg_html_doc/templates/inst.adoc.erb b/backends/cfg_html_doc/templates/inst.adoc.erb index 7159fdced2..dd0a2c5a15 100644 --- a/backends/cfg_html_doc/templates/inst.adoc.erb +++ b/backends/cfg_html_doc/templates/inst.adoc.erb @@ -20,20 +20,20 @@ This instruction has different encodings in RV32 and RV64. RV32:: + [wavedrom, ,svg,subs='attributes',width="100%"] -.... +.... <%= JSON.dump inst.wavedrom_desc(32) %> .... RV64:: + [wavedrom, ,svg,subs='attributes',width="100%"] -.... +.... <%= JSON.dump inst.wavedrom_desc(64) %> .... ==== <%- else -%> [wavedrom, ,svg,subs='attributes',width="100%"] -.... +.... <%= JSON.dump inst.wavedrom_desc(arch_def.param_values["XLEN"]) %> .... <%- end -%> @@ -132,4 +132,3 @@ This instruction may result in the following synchronous exceptions: <%- end -%> <%- end -%> - diff --git a/backends/cfg_html_doc/templates/landing.adoc.erb b/backends/cfg_html_doc/templates/landing.adoc.erb index 6f30dbe50e..6f66fa3ce4 100644 --- a/backends/cfg_html_doc/templates/landing.adoc.erb +++ b/backends/cfg_html_doc/templates/landing.adoc.erb @@ -14,4 +14,4 @@ Additionally, the following documentation is also included: * xref:prose:idl.adoc[IDL language reference] This site was generated using -https://github.com/riscv-software-src/riscv-unified-db[the RISC-V Unified Database]. \ No newline at end of file +https://github.com/riscv-software-src/riscv-unified-db[the RISC-V Unified Database]. diff --git a/backends/cfg_html_doc/templates/toc.adoc.erb b/backends/cfg_html_doc/templates/toc.adoc.erb index 0282723d52..6c951bccc7 100644 --- a/backends/cfg_html_doc/templates/toc.adoc.erb +++ b/backends/cfg_html_doc/templates/toc.adoc.erb @@ -19,4 +19,4 @@ * xref:funcs:funcs.adoc[Global function defintions] .Appendix -* xref:prose:idl.adoc[IDL guide] \ No newline at end of file +* xref:prose:idl.adoc[IDL guide] diff --git a/backends/ext_pdf_doc/idl_lexer.rb b/backends/ext_pdf_doc/idl_lexer.rb index c9998e9301..c89af9fe0d 100644 --- a/backends/ext_pdf_doc/idl_lexer.rb +++ b/backends/ext_pdf_doc/idl_lexer.rb @@ -5,7 +5,7 @@ module Lexers class Idl < RegexLexer tag "idl" filenames "idl", "isa" - + title "IDL" desc "ISA Description Language" diff --git a/backends/ext_pdf_doc/templates/ext_pdf.adoc.erb b/backends/ext_pdf_doc/templates/ext_pdf.adoc.erb index 44501d85b2..faf81fae88 100644 --- a/backends/ext_pdf_doc/templates/ext_pdf.adoc.erb +++ b/backends/ext_pdf_doc/templates/ext_pdf.adoc.erb @@ -167,7 +167,7 @@ Design document:: <%= version.url %> Changes:: <% version.changes.each do |c| -%> - * <%= c %> + * <%= c %> <% end -%> <%- end -%> diff --git a/backends/manual/templates/csr.adoc.erb b/backends/manual/templates/csr.adoc.erb index 23e1205a98..b5e59f47f1 100644 --- a/backends/manual/templates/csr.adoc.erb +++ b/backends/manual/templates/csr.adoc.erb @@ -167,4 +167,3 @@ This CSR may return a value that is different from what is stored in hardware. <%= csr.sw_read_ast(arch_def.symtab).gen_adoc %> ---- <%- end -%> - diff --git a/backends/manual/templates/ext.adoc.erb b/backends/manual/templates/ext.adoc.erb index 410576a9cf..a3e5fdfa1e 100644 --- a/backends/manual/templates/ext.adoc.erb +++ b/backends/manual/templates/ext.adoc.erb @@ -67,4 +67,4 @@ h| Description a| <%= param.desc %> -- <%- end -%> -<%- end -%> \ No newline at end of file +<%- end -%> diff --git a/backends/manual/templates/func.adoc.erb b/backends/manual/templates/func.adoc.erb index 9c723b238b..a725f3014a 100644 --- a/backends/manual/templates/func.adoc.erb +++ b/backends/manual/templates/func.adoc.erb @@ -39,4 +39,4 @@ None ---- <%- end -%> -<%- end -%> \ No newline at end of file +<%- end -%> diff --git a/backends/manual/templates/instruction.adoc.erb b/backends/manual/templates/instruction.adoc.erb index 32d9af233d..c1339a4323 100644 --- a/backends/manual/templates/instruction.adoc.erb +++ b/backends/manual/templates/instruction.adoc.erb @@ -40,20 +40,20 @@ This instruction has different encodings in RV32 and RV64. RV32:: + [wavedrom, ,svg,subs='attributes',width="100%"] -.... +.... <%= JSON.dump inst.wavedrom_desc(32) %> .... RV64:: + [wavedrom, ,svg,subs='attributes',width="100%"] -.... +.... <%= JSON.dump inst.wavedrom_desc(64) %> .... ==== <%- else -%> [wavedrom, ,svg,subs='attributes',width="100%"] -.... +.... <%= JSON.dump inst.wavedrom_desc(inst.base.nil? ? 32 : inst.base) %> .... <%- end -%> @@ -153,4 +153,3 @@ This instruction may result in the following synchronous exceptions: <%- end -%> <%- end -%> - diff --git a/backends/manual/templates/isa_version_index.adoc.erb b/backends/manual/templates/isa_version_index.adoc.erb index 4f68f1a898..59037e3fcd 100644 --- a/backends/manual/templates/isa_version_index.adoc.erb +++ b/backends/manual/templates/isa_version_index.adoc.erb @@ -7,4 +7,3 @@ This version is RATIFIED. It will not change. <%- else -%> This version is a DRAFT. It may change. <%- end -%> - diff --git a/backends/manual/templates/param_list.adoc.erb b/backends/manual/templates/param_list.adoc.erb index 518e382538..dd273b85b9 100644 --- a/backends/manual/templates/param_list.adoc.erb +++ b/backends/manual/templates/param_list.adoc.erb @@ -15,4 +15,4 @@ The following <%= params.size %> parameters are defined in this manual: | <%= param.exts.map { |ext| "`#{ext.name}`"}.join(", ") %> a| <%= param.desc %> <%- end -%> -|=== \ No newline at end of file +|=== diff --git a/backends/manual/templates/playbook.yml.erb b/backends/manual/templates/playbook.yml.erb index fddeaf6373..3ffafdf7a5 100644 --- a/backends/manual/templates/playbook.yml.erb +++ b/backends/manual/templates/playbook.yml.erb @@ -102,4 +102,4 @@ ui: .doc .admonitionblock td.icon i.icon-when::after { text-transform: none; - } \ No newline at end of file + } diff --git a/backends/portfolio_doc/templates/family_intro.erb b/backends/portfolio_doc/templates/family_intro.erb index 30314419cd..837125fb64 100644 --- a/backends/portfolio_doc/templates/family_intro.erb +++ b/backends/portfolio_doc/templates/family_intro.erb @@ -8,4 +8,4 @@ === <%= portfolio_class.name %> Class Description -<%= portfolio_class.description %> \ No newline at end of file +<%= portfolio_class.description %> diff --git a/backends/profile_doc/templates/profile.adoc.erb b/backends/profile_doc/templates/profile.adoc.erb index 166ec08b7e..e310413d04 100644 --- a/backends/profile_doc/templates/profile.adoc.erb +++ b/backends/profile_doc/templates/profile.adoc.erb @@ -363,7 +363,7 @@ The <%= profile_class.marketing_name %> Profile Class references <%= profile_release.introduction %> -<%= profile_release.marketing_name %> has <%= profile_release.referenced_extensions.reduce(0) { |sum, ext| sum + ext.params.size } %> +<%= profile_release.marketing_name %> has <%= profile_release.referenced_extensions.reduce(0) { |sum, ext| sum + ext.params.size } %> associated implementation-defined parameters across all its defined profiles. <% unless profile_release.description.nil? -%> @@ -438,7 +438,7 @@ associated implementation-defined parameters. Changes::: <% v.changes.each do |c| -%> - * <%= c %> + * <%= c %> <% end -%> <%- end -%> @@ -524,20 +524,20 @@ This instruction has different encodings in RV32 and RV64. RV32:: + [wavedrom, ,svg,subs='attributes',width="100%"] -.... +.... <%= JSON.dump inst.wavedrom_desc(32) %> .... RV64:: + [wavedrom, ,svg,subs='attributes',width="100%"] -.... +.... <%= JSON.dump inst.wavedrom_desc(64) %> .... ==== <% else -%> [wavedrom, ,svg,subs='attributes',width="100%"] -.... +.... <%= JSON.dump inst.wavedrom_desc(inst.base.nil? ? 32 : inst.base) %> .... <% end -%> @@ -698,4 +698,4 @@ This CSR format changes dynamically with XLEN. <% end -%> -<% end -%> \ No newline at end of file +<% end -%> diff --git a/bin/pre-commit b/bin/pre-commit index b7b56416cc..ccf0660f40 100755 --- a/bin/pre-commit +++ b/bin/pre-commit @@ -3,4 +3,3 @@ ROOT=$(dirname $(dirname $(realpath $BASH_SOURCE[0]))) ${ROOT}/bin/bash -c "source ${ROOT}/.home/.venv/bin/activate && pre-commit $@" - diff --git a/cfgs/_32/implemented_exts.yaml b/cfgs/_32/implemented_exts.yaml index 11151c2451..a532cca51e 100644 --- a/cfgs/_32/implemented_exts.yaml +++ b/cfgs/_32/implemented_exts.yaml @@ -1 +1 @@ -implemented_extensions: [] \ No newline at end of file +implemented_extensions: [] diff --git a/cfgs/_64/implemented_exts.yaml b/cfgs/_64/implemented_exts.yaml index 11151c2451..a532cca51e 100644 --- a/cfgs/_64/implemented_exts.yaml +++ b/cfgs/_64/implemented_exts.yaml @@ -1 +1 @@ -implemented_extensions: [] \ No newline at end of file +implemented_extensions: [] diff --git a/cfgs/config_validation.rb b/cfgs/config_validation.rb index 40d428d3f8..23d5828906 100644 --- a/cfgs/config_validation.rb +++ b/cfgs/config_validation.rb @@ -22,7 +22,7 @@ assert [nil, 32].include?(UXLEN) if ext?(:S) && ext?(:U) && SXLEN == 32 max_va_width = - if ext?(:Sv57) + if ext?(:Sv57) 57 elsif ext?(:Sv48) 48 diff --git a/cfgs/generic_rv64/params.yaml b/cfgs/generic_rv64/params.yaml index 4ed77881a7..ace3ee74d5 100644 --- a/cfgs/generic_rv64/params.yaml +++ b/cfgs/generic_rv64/params.yaml @@ -448,8 +448,8 @@ params: # Strategy used to handle reservation sets # - # * "reserve naturally-aligned 64-byte region": Always reserve the 64-byte block containing the LR/SC address - # * "reserve naturally-aligned 128-byte region": Always reserve the 128-byte block containing the LR/SC address + # * "reserve naturally-aligned 64-byte region": Always reserve the 64-byte block containing the LR/SC address + # * "reserve naturally-aligned 128-byte region": Always reserve the 128-byte block containing the LR/SC address # * "reserve exactly enough to cover the access": Always reserve exactly the LR/SC access, and no more # * "custom": Custom behavior, leading to an 'unpredictable' call on any LR/SC LRSC_RESERVATION_STRATEGY: reserve naturally-aligned 64-byte region diff --git a/docs/index.html b/docs/index.html index 4b05e2f88d..9786ceb706 100644 --- a/docs/index.html +++ b/docs/index.html @@ -13,4 +13,4 @@

Ruby documentation

- \ No newline at end of file + diff --git a/lib/DB_MODEL.README.adoc b/lib/DB_MODEL.README.adoc index 6c08061d82..982562fb4b 100644 --- a/lib/DB_MODEL.README.adoc +++ b/lib/DB_MODEL.README.adoc @@ -2,7 +2,7 @@ A Ruby interface for https://github.com/riscv-software-src/riscv-unified-db[`riscv-unified-db`] is located in the `lib` directory. It can be used to query the database in the context of a configuration through a set of object models. -The main class is `ArchDef`, which represents all of the database information plus any known configuration parameters. An `ArchDef` must be initialized from a configuration in the `cfg` directory. Two configurations are provided -- _32 and _64 -- that represent generic RV32/RV64 machines (_i.e._, the only known configuration parameter is `MXLEN`). +The main class is `ArchDef`, which represents all of the database information plus any known configuration parameters. An `ArchDef` must be initialized from a configuration in the `cfg` directory. Two configurations are provided -- _32 and _64 -- that represent generic RV32/RV64 machines (_i.e._, the only known configuration parameter is `MXLEN`). == Configuration files @@ -13,7 +13,7 @@ A configuration consists of a folder under `cfgs`. Inside that folder, there are `cfg.yaml`:: A YAML object (hash) that currently contains only one field `type`. `type` can be one of: -* "partially configured": The configuration has some parameters and/or implemented extensions known, but others are not known. Examples of a _partially configured_ configuration are the generic _32/_64 configs and a profile (which has some known/mandatory extensions, but also many unknown/optional extensions). +* "partially configured": The configuration has some parameters and/or implemented extensions known, but others are not known. Examples of a _partially configured_ configuration are the generic _32/_64 configs and a profile (which has some known/mandatory extensions, but also many unknown/optional extensions). * "fully configured": The configuration exhaustively lists a set of implmented extensions and parameters. An example of a _fully configured_ configuration is the `generic_rv64` example, which represents a theoritical implementation of RV64. In a _fully configured_ configuration, any extension that isn't known to be implemented is treated as unimplmented, and will be pruned out of the database for certain operations. `implemented_exts.yaml`:: @@ -96,4 +96,4 @@ arch_def.implemented_csrs # the `mstatus.MPRV` CSR field arch_def.csr("mstatus").field("MPRV") #=> CsrField ----- \ No newline at end of file +---- diff --git a/lib/arch_def.rb b/lib/arch_def.rb index 8a297af7f6..3c68215318 100644 --- a/lib/arch_def.rb +++ b/lib/arch_def.rb @@ -1,8 +1,8 @@ # frozen_string_literal: true # Many classes have an "arch_def" member which is an ArchDef (not ArchDefObject) class. -# The "arch_def" member contains the "database" of RISC-V standards including extensions, instructions, -# CSRs, Profiles, and Certificates. +# The "arch_def" member contains the "database" of RISC-V standards including extensions, instructions, +# CSRs, Profiles, and Certificates. # # The arch_def member has methods such as: # extensions() Array of all extensions known to the database (even if not implemented). @@ -179,7 +179,7 @@ def type_check(show_progress: true, io: $stdout) unless field.type_ast(@symtab).nil? if ((possible_xlens.include?(32) && csr.defined_in_base32? && field.defined_in_base32?) || (possible_xlens.include?(64) && csr.defined_in_base64? && field.defined_in_base64?)) - field.type_checked_type_ast(@symtab) + field.type_checked_type_ast(@symtab) end end unless field.reset_value_ast(@symtab).nil? @@ -911,7 +911,7 @@ def ref(uri) def implemented_csrs return @implemented_csrs unless @implemented_csrs.nil? - @implemented_csrs = + @implemented_csrs = if @arch_def.key?("implemented_csrs") csrs.select { |c| @arch_def["implemented_csrs"].include?(c.name) } else diff --git a/lib/arch_obj_models/certificate.rb b/lib/arch_obj_models/certificate.rb index 5b8f0552a9..833c2f1728 100644 --- a/lib/arch_obj_models/certificate.rb +++ b/lib/arch_obj_models/certificate.rb @@ -136,4 +136,4 @@ def requirement_groups end @requirement_groups end -end \ No newline at end of file +end diff --git a/lib/arch_obj_models/csr.rb b/lib/arch_obj_models/csr.rb index 77613e8eeb..4747e05b3c 100644 --- a/lib/arch_obj_models/csr.rb +++ b/lib/arch_obj_models/csr.rb @@ -272,7 +272,7 @@ def length_cond64 # @return [String] Pretty-printed length string def length_pretty(arch_def, effective_xlen=nil) if dynamic_length?(arch_def) - cond = + cond = case @data["length"] when "MXLEN" "CSR[misa].MXL == %%" diff --git a/lib/arch_obj_models/csr_field.rb b/lib/arch_obj_models/csr_field.rb index 8ee73555e9..a793ba0882 100644 --- a/lib/arch_obj_models/csr_field.rb +++ b/lib/arch_obj_models/csr_field.rb @@ -174,7 +174,7 @@ def type(symtab) idl = @data["type()"] raise "type() is nil for #{csr.name}.#{name} #{@data}?" if idl.nil? - + # value_result = Idl::AstNode.value_try do ast = type_checked_type_ast(symtab) @@ -786,4 +786,4 @@ def location_pretty(arch_def, effective_xlen = nil) def type_desc(arch_def) TYPE_DESC_MAP[type(arch_def.symtab)] end -end \ No newline at end of file +end diff --git a/lib/arch_obj_models/extension.rb b/lib/arch_obj_models/extension.rb index b40aff3c55..1d978c39b8 100644 --- a/lib/arch_obj_models/extension.rb +++ b/lib/arch_obj_models/extension.rb @@ -77,7 +77,7 @@ def name_potentially_with_link(exts) if exts.size == 1 "<>" - else + else "#{name}" end end @@ -462,7 +462,7 @@ def initialize(data) data.each do |key, value| if key == "optional" raise ArgumentError, "Extension presence hash #{data} missing type of optional" if value.nil? - raise ArgumentError, "Unknown extension presence optional #{value} for type of optional" unless + raise ArgumentError, "Unknown extension presence optional #{value} for type of optional" unless ["localized", "development", "expansion", "transitory"].include?(value) @presence = key @@ -476,7 +476,7 @@ def initialize(data) end end - def mandatory? = (@presence == mandatory) + def mandatory? = (@presence == mandatory) def optional? = (@presence == optional) # Class methods diff --git a/lib/arch_obj_models/instruction.rb b/lib/arch_obj_models/instruction.rb index 8daaa54be5..ee347bb4b4 100644 --- a/lib/arch_obj_models/instruction.rb +++ b/lib/arch_obj_models/instruction.rb @@ -259,7 +259,7 @@ def size @range.size end end - + # decode field constructions from YAML file, rather than riscv-opcodes # eventually, we will move so that all instructions use the YAML file, class DecodeVariable @@ -524,7 +524,7 @@ def initialize(format, decode_vars) @format.chars.each_with_index do |c, idx| if c == "-" next if field_chars.empty? - + field_text = field_chars.join("") field_lsb = @format.size - idx field_msb = @format.size - idx - 1 + field_text.size diff --git a/lib/arch_obj_models/obj.rb b/lib/arch_obj_models/obj.rb index 215c4ec47d..2e6b62176a 100644 --- a/lib/arch_obj_models/obj.rb +++ b/lib/arch_obj_models/obj.rb @@ -68,7 +68,7 @@ def inspect # @return [Array] List of keys added by this ArchDefObject def keys = @data.keys - + # @param k (see Hash#key?) # @return (see Hash#key?) def key?(k) = @data.key?(k) @@ -106,7 +106,7 @@ def defined_by?(*args) end elsif args.size == 2 raise ArgumentError, "First parameter must be an extension name" unless args[0].respond_to?(:to_s) - version = args[1].is_a?(Gem::Version) ? args[1] : Gem::Version.new(args[1]) + version = args[1].is_a?(Gem::Version) ? args[1] : Gem::Version.new(args[1]) defined_by.satisfied_by? do |r| r.name == args[0] && r.version_requirement.satisfied_by?(version) @@ -365,7 +365,7 @@ def self.all_of(*conds) cond = SchemaCondition.new({ "allOf" => conds }) - + SchemaCondition.new(cond.minimize) end @@ -474,7 +474,7 @@ def satisfied_by?(&block) class AlwaysTrueSchemaCondition def to_rb = "true" - + def satisfied_by? = true def empty? = true diff --git a/lib/arch_obj_models/portfolio.rb b/lib/arch_obj_models/portfolio.rb index e378cdc017..3ad3306d57 100644 --- a/lib/arch_obj_models/portfolio.rb +++ b/lib/arch_obj_models/portfolio.rb @@ -2,7 +2,7 @@ # A "Portfolio" is a named & versioned grouping of extensions (each with a name and version). # Each Portfolio Instance is a member of a Portfolio Class: # RVA20U64 and MC100 are examples of portfolio instances -# RVA and MC are examples of portfolio classes +# RVA and MC are examples of portfolio classes # # Many classes inherit from the ArchDefObject class. This provides facilities for accessing the contents of a # Portfolio Class YAML or Portfolio Model YAML file via the "data" member (hash holding releated YAML file contents). @@ -76,7 +76,7 @@ def extension_presence(ext_name) # @return [Array] def version_strongest_presence(ext_name, ext_versions) presences = [] - + # See if any extension requirement in this profile lists this version as either mandatory or optional. ext_versions.map do |v| mandatory = mandatory_ext_reqs.any? { |ext_req| ext_req.satisfied_by?(ext_name, v.version) } @@ -113,8 +113,8 @@ def in_scope_ext_reqs(desired_presence = nil) in_scope_ext_reqs = [] # Convert desired_present argument to ExtensionPresence object if not nil. - desired_presence_converted = - desired_presence.nil? ? nil : + desired_presence_converted = + desired_presence.nil? ? nil : desired_presence.is_a?(String) ? desired_presence : desired_presence.is_a?(ExtensionPresence) ? desired_presence : ExtensionPresence.new(desired_presence) @@ -134,7 +134,7 @@ def in_scope_ext_reqs(desired_presence = nil) end if match - in_scope_ext_reqs << + in_scope_ext_reqs << ExtensionRequirement.new(ext_name, ext_data["version"], presence: actual_presence_obj, note: ext_data["note"], req_id: "REQ-EXT-" + ext_name) end @@ -253,7 +253,7 @@ def allowed_values # sorts by name def <=>(other) - raise ArgumentError, + raise ArgumentError, "InScopeExtensionParameter are only comparable to other parameter constraints" unless other.is_a?(InScopeExtensionParameter) @param.name <=> other.param.name end @@ -272,7 +272,7 @@ def all_in_scope_ext_params @all_in_scope_ext_params = [] - @data["extensions"].each do |ext_name, ext_data| + @data["extensions"].each do |ext_name, ext_data| # Find Extension object from database ext = @arch_def.extension(ext_name) raise "Cannot find extension named #{ext_name}" if ext.nil? @@ -286,7 +286,7 @@ def all_in_scope_ext_params param.defined_in_extension_version?(ext_ver.version) end - @all_in_scope_ext_params << + @all_in_scope_ext_params << InScopeExtensionParameter.new(param, param_data["schema"], param_data["note"]) end end @@ -303,7 +303,7 @@ def in_scope_ext_params(ext_req) # Get extension information from portfolio YAML for passed in extension requirement. ext_data = @data["extensions"][ext_req.name] raise "Cannot find extension named #{ext_req.name}" if ext_data.nil? - + # Find Extension object from database ext = @arch_def.extension(ext_req.name) raise "Cannot find extension named #{ext_req.name}" if ext.nil? @@ -330,7 +330,7 @@ def in_scope_ext_params(ext_req) # @return [Array] Parameters out of scope across all in scope extensions (those listed in the portfolio). def all_out_of_scope_params return @all_out_of_scope_params unless @all_out_of_scope_params.nil? - + @all_out_of_scope_params = [] in_scope_ext_reqs.each do |ext_req| ext = @arch_def.extension(ext_req.name) @@ -350,11 +350,11 @@ def all_out_of_scope_params # @return [Array] Parameters that are out of scope for named extension. def out_of_scope_params(ext_name) - all_out_of_scope_params.select{|param| param.exts.any? {|ext| ext.name == ext_name} } + all_out_of_scope_params.select{|param| param.exts.any? {|ext| ext.name == ext_name} } end # @return [Array] - # All the in-scope extensions (those in the portfolio) that define this parameter in the database + # All the in-scope extensions (those in the portfolio) that define this parameter in the database # and the parameter is in-scope (listed in that extension's list of parameters in the portfolio). def all_in_scope_exts_with_param(param) raise ArgumentError, "Expecting ExtensionParameter" unless param.is_a?(ExtensionParameter) @@ -383,7 +383,7 @@ def all_in_scope_exts_with_param(param) end # @return [Array] - # All the in-scope extensions (those in the portfolio) that define this parameter in the database + # All the in-scope extensions (those in the portfolio) that define this parameter in the database # but the parameter is out-of-scope (not listed in that extension's list of parameters in the portfolio). def all_in_scope_exts_without_param(param) raise ArgumentError, "Expecting ExtensionParameter" unless param.is_a?(ExtensionParameter) @@ -444,7 +444,7 @@ def revision_history class ExtraNote < ArchDefObject def initialize(data) - super(data) + super(data) @presence_obj = ExtensionPresence.new(@data["presence"]) end @@ -463,7 +463,7 @@ def extra_notes @extra_notes end - # @param desired_presence [ExtensionPresence] + # @param desired_presence [ExtensionPresence] # @return [String] Note for desired_presence # @return [nil] No note for desired_presence def extra_notes_for_presence(desired_presence_obj) @@ -493,4 +493,4 @@ def recommendations end @recommendations end -end \ No newline at end of file +end diff --git a/lib/arch_obj_models/profile.rb b/lib/arch_obj_models/profile.rb index 44d63f3b45..c63be19a21 100644 --- a/lib/arch_obj_models/profile.rb +++ b/lib/arch_obj_models/profile.rb @@ -231,7 +231,7 @@ def ext_req_to_adoc(ext_req) # @return [Array] def ext_note_to_adoc(ext_name) ret = [] - + unless extension_note(ext_name).nil? ret << "+" ret << "[NOTE]" @@ -239,7 +239,7 @@ def ext_note_to_adoc(ext_name) ret << extension_note(ext_name) ret << "--" end - + ret end -end \ No newline at end of file +end diff --git a/lib/arch_obj_models/schema.rb b/lib/arch_obj_models/schema.rb index c5cbbc998c..041e1da7cb 100644 --- a/lib/arch_obj_models/schema.rb +++ b/lib/arch_obj_models/schema.rb @@ -6,7 +6,7 @@ # # Used when an object in the database specifies a constraint using JSON schema # For example, extension parameters -class Schema +class Schema def initialize(schema_hash) raise ArgumentError, "Expecting hash" unless schema_hash.is_a?(Hash) @@ -77,9 +77,9 @@ def to_pretty_s(schema_hash = @schema_hash) "" end - array_str = if items.nil? + array_str = if items.nil? size_str + "array" - else + else if items.is_a?(Hash) "#{size_str}array of #{to_pretty_s(items)}" elsif items.is_a?(Array) @@ -89,7 +89,7 @@ def to_pretty_s(schema_hash = @schema_hash) end additional_items = schema_hash["additionalItems"] if additional_items - str = str + "additional items are: +\n  " + + str = str + "additional items are: +\n  " + to_pretty_s(additional_items) end str @@ -161,4 +161,3 @@ def to_idl_type Idl::Type.from_json_schema(@schema_hash) end end - diff --git a/lib/asciidoc_extensions.js b/lib/asciidoc_extensions.js index 7da2f377b4..91520a8039 100644 --- a/lib/asciidoc_extensions.js +++ b/lib/asciidoc_extensions.js @@ -1,3 +1,3 @@ const asciidoctor = require('asciidoctor')() const registry = asciidoctor.Extensions.create() -require('./asciidoc_when_extension.js')(registry) \ No newline at end of file +require('./asciidoc_when_extension.js')(registry) diff --git a/lib/idl/ast.rb b/lib/idl/ast.rb index e113b0ee13..7059b9be2b 100644 --- a/lib/idl/ast.rb +++ b/lib/idl/ast.rb @@ -1266,7 +1266,7 @@ def freeze_tree(global_symtab) type(global_symtab) freeze end - + # @return [Integer] The number of bits in the Bitfield def size(symtab) @size.value(symtab) @@ -1834,7 +1834,7 @@ def execute_unknown(symtab) end when :bits var = symtab.get(lhs.text_value) - value_result = value_try do + value_result = value_try do v = rhs.value(symtab) var.value = (lhs.value & ~0) | ((v & 1) << idx.value(symtab)) end @@ -2559,7 +2559,7 @@ def to_ast # # This will result in a BitsCaseAst: # - # $bits(ExceptionCode::LoadAccessFault) + # $bits(ExceptionCode::LoadAccessFault) class BitsCastAst < AstNode include Rvalue @@ -2826,7 +2826,7 @@ def value(symtab) # cached_value = @value_cache[symtab] # return cached_value unless cached_value.nil? - value = + value = if op == ">>>" lhs_value = lhs.value(symtab) if lhs_value & (1 << (lhs.type(symtab).width - 1)).zero? @@ -2995,7 +2995,7 @@ def value(symtab) else v end - + warn "WARNING: The value of '#{text_value}' (#{lhs.type(symtab).const?}, #{rhs.type(symtab).const?}) is truncated from #{v} to #{v_trunc} because the result is only #{type(symtab).width} bits" if v != v_trunc v_trunc end @@ -3445,7 +3445,7 @@ def freeze_tree(global_symtab) # @!macro type_check def type_check(symtab) enum_def_type = @enum_def_type - + type_error "No symbol #{@enum_class_name} has been defined" if enum_def_type.nil? type_error "#{@enum_class_name} is not an enum type" unless enum_def_type.is_a?(EnumerationType) @@ -4526,7 +4526,7 @@ def template_arg_nodes def template_values(symtab, unknown_ok: false) return EMPTY_ARRAY unless template? - if unknown_ok + if unknown_ok template_arg_nodes.map do |e| val = nil value_result = value_try do @@ -4954,7 +4954,7 @@ def return_type(symtab) rtype = rtype.ref_type if rtype.kind == :enum rtype end - + Type.new(:tuple, tuple_types:) end diff --git a/lib/idl/idl.treetop b/lib/idl/idl.treetop index a054cb2d56..43e9dae440 100644 --- a/lib/idl/idl.treetop +++ b/lib/idl/idl.treetop @@ -15,7 +15,7 @@ grammar Idl struct_definition / function_definition - / + / space+ )+ end @@ -298,7 +298,7 @@ grammar Idl / concatenation_expression / - field_access_expression + field_access_expression / function_call # Ast is assigned in function_call rule / diff --git a/lib/idl/passes/gen_adoc.rb b/lib/idl/passes/gen_adoc.rb index fdf2c43068..21ddb8be16 100644 --- a/lib/idl/passes/gen_adoc.rb +++ b/lib/idl/passes/gen_adoc.rb @@ -301,7 +301,7 @@ def gen_adoc(indent = 0, indent_spaces: 2) if idx_text =~ /[0-9]+/ "#{' '*indent}#{csr_text}" else - if @archdef.csr(csr_text).nil? + if @archdef.csr(csr_text).nil? "#{' '*indent}#{csr_text}" else "#{' '*indent}%%LINK%csr_field;#{idx_text}.#{@field_name};#{csr_text}%%" diff --git a/lib/idl/passes/gen_option_adoc.rb b/lib/idl/passes/gen_option_adoc.rb index 5557dfc443..059530ce7c 100644 --- a/lib/idl/passes/gen_option_adoc.rb +++ b/lib/idl/passes/gen_option_adoc.rb @@ -26,7 +26,7 @@ def gen_option_adoc class IfAst def gen_option_adoc - adoc = + adoc = <<~ADOC [when,"#{if_cond.to_idl}"] #{if_body.gen_option_adoc} diff --git a/lib/idl/passes/reachable_functions.rb b/lib/idl/passes/reachable_functions.rb index 2c9472babe..ca4379501f 100644 --- a/lib/idl/passes/reachable_functions.rb +++ b/lib/idl/passes/reachable_functions.rb @@ -146,7 +146,7 @@ def reachable_functions(symtab) # condition not known fns = fns.concat action.reachable_functions(symtab) if action.is_a?(FunctionCallExpressionAst) end - + fns end end diff --git a/lib/idl/symbol_table.rb b/lib/idl/symbol_table.rb index 1fe9a3fe81..f78acd9a25 100644 --- a/lib/idl/symbol_table.rb +++ b/lib/idl/symbol_table.rb @@ -196,7 +196,7 @@ def deep_freeze # set up the global clone that be used as a mutable table @global_clone_pool = [] - 5.times do + 5.times do copy = SymbolTable.allocate copy.instance_variable_set(:@scopes, [@scopes[0]]) copy.instance_variable_set(:@callstack, [@callstack[0]]) @@ -335,7 +335,7 @@ def add_at!(level, name, var) raise "Level #{level} is too large #{@scopes.size}" if level >= @scopes.size raise "Symbol #{name} already defined" unless @scopes[0...level].select { |h| h.key? name }.empty? - + @scopes[level][name] = var end diff --git a/lib/idl/tests/helpers.rb b/lib/idl/tests/helpers.rb index ca26eb4ab3..8ef30e6c00 100644 --- a/lib/idl/tests/helpers.rb +++ b/lib/idl/tests/helpers.rb @@ -39,4 +39,4 @@ def setup @symtab = Idl::SymbolTable.new(@archdef, 32) @compiler = Idl::Compiler.new(@archdef) end -end \ No newline at end of file +end diff --git a/lib/idl/tests/test_lexer.rb b/lib/idl/tests/test_lexer.rb index b69cfc8bf1..a279b6cde5 100644 --- a/lib/idl/tests/test_lexer.rb +++ b/lib/idl/tests/test_lexer.rb @@ -24,11 +24,11 @@ def test_function } XReg index = shamt & (xlen() - 1); FUNC - + tokens.each do |token, chunk| puts token puts chunk end end -end \ No newline at end of file +end diff --git a/lib/resolver.rb b/lib/resolver.rb index 2427ff5b9f..494d7c9f50 100644 --- a/lib/resolver.rb +++ b/lib/resolver.rb @@ -17,4 +17,4 @@ def resolve(input_file, output_file) obj = YamlLoader.load(input_file, permitted_classes: [Date]) File.write(output_file, YAML::dump(obj)) end -end \ No newline at end of file +end diff --git a/lib/test/test_yaml_loader.rb b/lib/test/test_yaml_loader.rb index 562d93d41b..c7285fa445 100644 --- a/lib/test/test_yaml_loader.rb +++ b/lib/test/test_yaml_loader.rb @@ -42,7 +42,7 @@ def test_multiple_remove - key3 key4: value4 YAML - + f = Tempfile.new("yml") f.write(yaml) f.flush @@ -346,10 +346,10 @@ def test_copy_in_the_same_document obj1: target10: abc - target11: + target11: $copy: "#/$defs/target1" target12: def - target13: + target13: $copy: "#/$defs/target3" YAML @@ -359,11 +359,11 @@ def test_copy_in_the_same_document f.flush doc = YamlLoader.load(f.path) - assert_equal({ - "target10" => "abc", - "target11" => "A string", - "target12" => "def", - "target13" => "Another string" + assert_equal({ + "target10" => "abc", + "target11" => "A string", + "target12" => "def", + "target13" => "Another string" }, doc["obj1"]) end @@ -384,10 +384,10 @@ def test_copy_in_the_different_document yaml2 = <<~YAML obj1: target10: abc - target11: + target11: $copy: "#{f1_path.basename}#/$defs/target1" target12: def - target13: + target13: $copy: "#{f1_path.basename}#/$defs/target3" YAML @@ -396,11 +396,11 @@ def test_copy_in_the_different_document f2.flush doc = YamlLoader.load(f2.path) - assert_equal({ - "target10" => "abc", - "target11" => "A string", - "target12" => "def", - "target13" => "Another string" + assert_equal({ + "target10" => "abc", + "target11" => "A string", + "target12" => "def", + "target13" => "Another string" }, doc["obj1"]) end diff --git a/lib/validate.rb b/lib/validate.rb index c2215b4335..3375922d28 100644 --- a/lib/validate.rb +++ b/lib/validate.rb @@ -245,7 +245,7 @@ def validate_instruction_encoding(inst_name, encoding) vars_match = variables.count { |variable| ary_from_location(variable["location"]).include?(i) } if vars_match.zero? raise ValidationError, "In instruction #{inst_name}, no variable or encoding bit covers bit #{i}" - elsif vars_match != 1 + elsif vars_match != 1 raise ValidationError, "In instruction, #{inst_name}, bit #{i} is covered by more than one variable" end else diff --git a/lib/yaml_loader.rb b/lib/yaml_loader.rb index 06f994865a..691ab45f3c 100644 --- a/lib/yaml_loader.rb +++ b/lib/yaml_loader.rb @@ -48,7 +48,7 @@ def self.expand(filename, obj, yaml_opts = {}) obj_doc else obj_doc.dig(*(obj_path.split("/")[1..])) - + end raise "#{obj['$ref']} cannot be found" if target_obj.nil? @@ -92,7 +92,7 @@ def self.expand(filename, obj, yaml_opts = {}) inherits_target_suffix = inherits_target.split("#/")[1] inherits_target_path = inherits_target_suffix.split("/") begin - target_obj = target_obj.dig(*inherits_target_path) + target_obj = target_obj.dig(*inherits_target_path) rescue TypeError => e if e.message == "no implicit conversion of String into Integer" warn "$inherits: \"#{inherits_target}\" found in file #{filename} references an Array but needs to reference a Hash" diff --git a/lib/yaml_resolver.py b/lib/yaml_resolver.py index 47e6c87f39..3b9b1ab5cd 100644 --- a/lib/yaml_resolver.py +++ b/lib/yaml_resolver.py @@ -34,7 +34,7 @@ def dig(obj, *keys): return dig(next_obj, *keys[1:]) except KeyError: return None - + resolved_objs = {} def resolve(path, rel_path, arch_root): if path in resolved_objs: diff --git a/schemas/cert_class_schema.json b/schemas/cert_class_schema.json index d7f7ff80c1..c7cd83438e 100644 --- a/schemas/cert_class_schema.json +++ b/schemas/cert_class_schema.json @@ -44,4 +44,4 @@ "$ref": "schema_defs.json#/$defs/__source" } } -} \ No newline at end of file +} diff --git a/schemas/cert_model_schema.json b/schemas/cert_model_schema.json index b205514459..65d514106d 100644 --- a/schemas/cert_model_schema.json +++ b/schemas/cert_model_schema.json @@ -196,4 +196,4 @@ "$ref": "schema_defs.json#/$defs/__source" } } -} \ No newline at end of file +} diff --git a/schemas/csr_schema.json b/schemas/csr_schema.json index 16ef9686c2..78ee09fee8 100644 --- a/schemas/csr_schema.json +++ b/schemas/csr_schema.json @@ -193,7 +193,7 @@ "description": "Descriptive name for the CSR" }, "description": { - "oneOf": [ + "oneOf": [ { "type": "string", "description": "A full Asciidoc description of the CSR, intended to be used as documentation." diff --git a/schemas/ext_schema.json b/schemas/ext_schema.json index 724e93128b..79c38d4b40 100644 --- a/schemas/ext_schema.json +++ b/schemas/ext_schema.json @@ -145,9 +145,9 @@ "additionalProperties": false } }, - "ratification_date": { + "ratification_date": { "oneOf": [ - {"type": "string", "pattern": "^20[0-9][0-9]-(0[1-9]|1[0-2])$", "$comment": "When ratification date is known", + {"type": "string", "pattern": "^20[0-9][0-9]-(0[1-9]|1[0-2])$", "$comment": "When ratification date is known", "description": "A specific year and month in YYYY-MM format", "examples": ["2019-01", "2024-12"] }, {"type": "string", "pattern": "^unknown$", "$comment": "When ratification date is unknown" }, {"type": "null", "$comment": "When version isn't ratified" } @@ -289,4 +289,4 @@ }, "$ref": "#/$defs/ext_data" -} \ No newline at end of file +} diff --git a/schemas/manual_version_schema.json b/schemas/manual_version_schema.json index 9557413ffa..e6b6320d55 100644 --- a/schemas/manual_version_schema.json +++ b/schemas/manual_version_schema.json @@ -95,4 +95,4 @@ } }, "additionalProperties": false -} \ No newline at end of file +} diff --git a/schemas/schema_defs.json b/schemas/schema_defs.json index 1b954ba328..86d57b4046 100644 --- a/schemas/schema_defs.json +++ b/schemas/schema_defs.json @@ -226,4 +226,4 @@ } } } -} \ No newline at end of file +}