diff --git a/.github/workflows/nightly.yml b/.github/workflows/nightly.yml index 084687ad4f..73c2dfd92e 100644 --- a/.github/workflows/nightly.yml +++ b/.github/workflows/nightly.yml @@ -2,7 +2,7 @@ name: Regression test on: schedule: - - cron: '30 2 * * *' + - cron: "30 2 * * *" workflow_dispatch: jobs: @@ -27,28 +27,28 @@ jobs: if: ${{ needs.check_date.outputs.should_run != 'false' }} runs-on: ubuntu-latest steps: - - name: Clone Github Repo Action - uses: actions/checkout@v4 - - name: Setup apptainer - uses: eWaterCycle/setup-apptainer@v2.0.0 - - name: Get container from cache - id: cache-sif - uses: actions/cache@v3 - with: - path: .singularity/image.sif - key: ${{ hashFiles('container.def', 'bin/.container-tag') }} - - name: Get gems and node files from cache - id: cache-bundle-npm - uses: actions/cache@v3 - with: - path: | - .home/.gems - node_modules - key: ${{ hashFiles('Gemfile.lock') }}-${{ hashFiles('package-lock.json') }} - - if: ${{ steps.cache-sif.outputs.cache-hit != 'true' }} - name: Build container - run: ./bin/build_container - - name: Setup project - run: ./bin/setup - - name: Run regression - run: ./do test:nightly + - name: Clone Github Repo Action + uses: actions/checkout@v4 + - name: Setup apptainer + uses: eWaterCycle/setup-apptainer@v2.0.0 + - name: Get container from cache + id: cache-sif + uses: actions/cache@v3 + with: + path: .singularity/image.sif + key: ${{ hashFiles('container.def', 'bin/.container-tag') }} + - name: Get gems and node files from cache + id: cache-bundle-npm + uses: actions/cache@v3 + with: + path: | + .home/.gems + node_modules + key: ${{ hashFiles('Gemfile.lock') }}-${{ hashFiles('package-lock.json') }} + - if: ${{ steps.cache-sif.outputs.cache-hit != 'true' }} + name: Build container + run: ./bin/build_container + - name: Setup project + run: ./bin/setup + - name: Run regression + run: ./do test:nightly diff --git a/.github/workflows/pages.yml b/.github/workflows/pages.yml index 37213d4ca9..fd50016655 100644 --- a/.github/workflows/pages.yml +++ b/.github/workflows/pages.yml @@ -2,7 +2,7 @@ name: Deploy pages on: push: branches: - - main + - main workflow_dispatch: permissions: contents: read @@ -18,73 +18,73 @@ jobs: name: github-pages url: ${{ steps.deployment.outputs.page_url }} steps: - - name: Clone Github Repo Action - uses: actions/checkout@v4 - - name: Setup apptainer - uses: eWaterCycle/setup-apptainer@v2.0.0 - - name: Get container from cache - id: cache-sif - uses: actions/cache@v3 - with: - path: .singularity/image.sif - key: ${{ hashFiles('container.def', 'bin/.container-tag') }} - - name: Get gems and node files from cache - id: cache-bundle-npm - uses: actions/cache@v3 - with: - path: | - .home/.gems - node_modules - key: ${{ hashFiles('Gemfile.lock') }}-${{ hashFiles('package-lock.json') }} - - if: ${{ steps.cache-sif.outputs.cache-hit != 'true' }} - name: Build container - run: ./bin/build_container - - name: Setup project - run: ./bin/setup - - name: Build manual - run: ./do gen:html_manual MANUAL_NAME=isa VERSIONS=all - - name: Build html documentation for generic_rv64 - run: ./do gen:html[generic_rv64] - - name: Generate YARD docs - run: ./do gen:tool_doc - - name: Create _site/example_cfg - run: mkdir -p _site/example_cfg - - name: Create _site/manual - run: mkdir -p _site/manual - - name: Create _site/pdfs - run: mkdir -p _site/pdfs - - name: Create _site/htmls - run: mkdir -p _site/htmls - - name: Copy cfg html - run: cp -R gen/cfg_html_doc/generic_rv64/html _site/example_cfg - - name: Create RVA20 Profile Release PDF Spec - run: ./do gen:profile[RVA20] - - name: Copy RVA20 Profile Release PDF - run: cp gen/profile_doc/pdf/RVA20.pdf _site/pdfs/RVA20.pdf - - name: Create RVA22 Profile Release PDF Spec - run: ./do gen:profile[RVA22] - - name: Copy RVA22 Profile Release PDF - run: cp gen/profile_doc/pdf/RVA22.pdf _site/pdfs/RVA22.pdf - - name: Create RVI20 Profile Release PDF Spec - run: ./do gen:profile[RVI20] - - name: Copy RVI20 Profile Release PDF - run: cp gen/profile_doc/pdf/RVA20.pdf _site/pdfs/RVI20.pdf - - name: Create MC100 PDF Spec - run: ./do gen:cert_model_pdf[MC100] - - name: Copy MC100 PDF - run: cp gen/certificate_doc/pdf/MC100.pdf _site/pdfs/MC100.pdf - - name: Create MC100 HTML Spec - run: ./do gen:cert_model_html[MC100] - - name: Copy MC100 HTML - run: cp gen/certificate_doc/html/MC100.html _site/htmls/MC100.html - - name: Copy manual html - run: cp -R gen/manual/isa/top/all/html _site/manual - - name: Setup Pages - uses: actions/configure-pages@v5 - - name: Upload artifact - uses: actions/upload-pages-artifact@v3 - with: - path: '_site' - - name: Deploy to GitHub Pages - id: deployment - uses: actions/deploy-pages@v4 + - name: Clone Github Repo Action + uses: actions/checkout@v4 + - name: Setup apptainer + uses: eWaterCycle/setup-apptainer@v2.0.0 + - name: Get container from cache + id: cache-sif + uses: actions/cache@v3 + with: + path: .singularity/image.sif + key: ${{ hashFiles('container.def', 'bin/.container-tag') }} + - name: Get gems and node files from cache + id: cache-bundle-npm + uses: actions/cache@v3 + with: + path: | + .home/.gems + node_modules + key: ${{ hashFiles('Gemfile.lock') }}-${{ hashFiles('package-lock.json') }} + - if: ${{ steps.cache-sif.outputs.cache-hit != 'true' }} + name: Build container + run: ./bin/build_container + - name: Setup project + run: ./bin/setup + - name: Build manual + run: ./do gen:html_manual MANUAL_NAME=isa VERSIONS=all + - name: Build html documentation for generic_rv64 + run: ./do gen:html[generic_rv64] + - name: Generate YARD docs + run: ./do gen:tool_doc + - name: Create _site/example_cfg + run: mkdir -p _site/example_cfg + - name: Create _site/manual + run: mkdir -p _site/manual + - name: Create _site/pdfs + run: mkdir -p _site/pdfs + - name: Create _site/htmls + run: mkdir -p _site/htmls + - name: Copy cfg html + run: cp -R gen/cfg_html_doc/generic_rv64/html _site/example_cfg + - name: Create RVA20 Profile Release PDF Spec + run: ./do gen:profile[RVA20] + - name: Copy RVA20 Profile Release PDF + run: cp gen/profile_doc/pdf/RVA20.pdf _site/pdfs/RVA20.pdf + - name: Create RVA22 Profile Release PDF Spec + run: ./do gen:profile[RVA22] + - name: Copy RVA22 Profile Release PDF + run: cp gen/profile_doc/pdf/RVA22.pdf _site/pdfs/RVA22.pdf + - name: Create RVI20 Profile Release PDF Spec + run: ./do gen:profile[RVI20] + - name: Copy RVI20 Profile Release PDF + run: cp gen/profile_doc/pdf/RVA20.pdf _site/pdfs/RVI20.pdf + - name: Create MC100 PDF Spec + run: ./do gen:cert_model_pdf[MC100] + - name: Copy MC100 PDF + run: cp gen/certificate_doc/pdf/MC100.pdf _site/pdfs/MC100.pdf + - name: Create MC100 HTML Spec + run: ./do gen:cert_model_html[MC100] + - name: Copy MC100 HTML + run: cp gen/certificate_doc/html/MC100.html _site/htmls/MC100.html + - name: Copy manual html + run: cp -R gen/manual/isa/top/all/html _site/manual + - name: Setup Pages + uses: actions/configure-pages@v5 + - name: Upload artifact + uses: actions/upload-pages-artifact@v3 + with: + path: "_site" + - name: Deploy to GitHub Pages + id: deployment + uses: actions/deploy-pages@v4 diff --git a/.github/workflows/regress.yml b/.github/workflows/regress.yml index 9f3fa519cd..b46dc57a37 100644 --- a/.github/workflows/regress.yml +++ b/.github/workflows/regress.yml @@ -2,7 +2,7 @@ name: Regression test on: pull_request: branches: - - main + - main workflow_dispatch: jobs: regress-smoke: @@ -40,29 +40,29 @@ jobs: MANUAL_NAME: isa VERSIONS: all steps: - - name: Clone Github Repo Action - uses: actions/checkout@v4 - - name: Setup apptainer - uses: eWaterCycle/setup-apptainer@v2.0.0 - - name: Get container from cache - id: cache-sif - uses: actions/cache@v3 - with: - path: .singularity/image.sif - key: ${{ hashFiles('container.def', 'bin/.container-tag') }} - - name: Get gems and node files from cache - id: cache-bundle-npm - uses: actions/cache@v3 - with: - path: | - .home/.gems - node_modules - key: ${{ hashFiles('Gemfile.lock') }}-${{ hashFiles('package-lock.json') }} - - if: ${{ steps.cache-sif.outputs.cache-hit != 'true' }} - name: Build container - run: ./bin/build_container - - name: Generate HTML ISA manual - run: ./do gen:html_manual + - name: Clone Github Repo Action + uses: actions/checkout@v4 + - name: Setup apptainer + uses: eWaterCycle/setup-apptainer@v2.0.0 + - name: Get container from cache + id: cache-sif + uses: actions/cache@v3 + with: + path: .singularity/image.sif + key: ${{ hashFiles('container.def', 'bin/.container-tag') }} + - name: Get gems and node files from cache + id: cache-bundle-npm + uses: actions/cache@v3 + with: + path: | + .home/.gems + node_modules + key: ${{ hashFiles('Gemfile.lock') }}-${{ hashFiles('package-lock.json') }} + - if: ${{ steps.cache-sif.outputs.cache-hit != 'true' }} + name: Build container + run: ./bin/build_container + - name: Generate HTML ISA manual + run: ./do gen:html_manual regress-gen-ext-pdf: runs-on: ubuntu-latest needs: regress-smoke @@ -70,80 +70,80 @@ jobs: EXT: B VERSION: latest steps: - - name: Clone Github Repo Action - uses: actions/checkout@v4 - - name: Setup apptainer - uses: eWaterCycle/setup-apptainer@v2.0.0 - - name: Get container from cache - id: cache-sif - uses: actions/cache@v3 - with: - path: .singularity/image.sif - key: ${{ hashFiles('container.def', 'bin/.container-tag') }} - - name: Get gems and node files from cache - id: cache-bundle-npm - uses: actions/cache@v3 - with: - path: | - .home/.gems - node_modules - key: ${{ hashFiles('Gemfile.lock') }}-${{ hashFiles('package-lock.json') }} - - if: ${{ steps.cache-sif.outputs.cache-hit != 'true' }} - name: Build container - run: ./bin/build_container - - name: Generate extension PDF - run: ./do gen:ext_pdf + - name: Clone Github Repo Action + uses: actions/checkout@v4 + - name: Setup apptainer + uses: eWaterCycle/setup-apptainer@v2.0.0 + - name: Get container from cache + id: cache-sif + uses: actions/cache@v3 + with: + path: .singularity/image.sif + key: ${{ hashFiles('container.def', 'bin/.container-tag') }} + - name: Get gems and node files from cache + id: cache-bundle-npm + uses: actions/cache@v3 + with: + path: | + .home/.gems + node_modules + key: ${{ hashFiles('Gemfile.lock') }}-${{ hashFiles('package-lock.json') }} + - if: ${{ steps.cache-sif.outputs.cache-hit != 'true' }} + name: Build container + run: ./bin/build_container + - name: Generate extension PDF + run: ./do gen:ext_pdf regress-gen-certificate: runs-on: ubuntu-latest needs: regress-smoke steps: - - name: Clone Github Repo Action - uses: actions/checkout@v4 - - name: Setup apptainer - uses: eWaterCycle/setup-apptainer@v2.0.0 - - name: Get container from cache - id: cache-sif - uses: actions/cache@v3 - with: - path: .singularity/image.sif - key: ${{ hashFiles('container.def', 'bin/.container-tag') }} - - name: Get gems and node files from cache - id: cache-bundle-npm - uses: actions/cache@v3 - with: - path: | - .home/.gems - node_modules - key: ${{ hashFiles('Gemfile.lock') }}-${{ hashFiles('package-lock.json') }} - - if: ${{ steps.cache-sif.outputs.cache-hit != 'true' }} - name: Build container - run: ./bin/build_container - - name: Generate extension PDF - run: ./do gen:cert_model_pdf[MockCertificateModel] + - name: Clone Github Repo Action + uses: actions/checkout@v4 + - name: Setup apptainer + uses: eWaterCycle/setup-apptainer@v2.0.0 + - name: Get container from cache + id: cache-sif + uses: actions/cache@v3 + with: + path: .singularity/image.sif + key: ${{ hashFiles('container.def', 'bin/.container-tag') }} + - name: Get gems and node files from cache + id: cache-bundle-npm + uses: actions/cache@v3 + with: + path: | + .home/.gems + node_modules + key: ${{ hashFiles('Gemfile.lock') }}-${{ hashFiles('package-lock.json') }} + - if: ${{ steps.cache-sif.outputs.cache-hit != 'true' }} + name: Build container + run: ./bin/build_container + - name: Generate extension PDF + run: ./do gen:cert_model_pdf[MockCertificateModel] regress-gen-profile: runs-on: ubuntu-latest needs: regress-smoke steps: - - name: Clone Github Repo Action - uses: actions/checkout@v4 - - name: Setup apptainer - uses: eWaterCycle/setup-apptainer@v2.0.0 - - name: Get container from cache - id: cache-sif - uses: actions/cache@v3 - with: - path: .singularity/image.sif - key: ${{ hashFiles('container.def', 'bin/.container-tag') }} - - name: Get gems and node files from cache - id: cache-bundle-npm - uses: actions/cache@v3 - with: - path: | - .home/.gems - node_modules - key: ${{ hashFiles('Gemfile.lock') }}-${{ hashFiles('package-lock.json') }} - - if: ${{ steps.cache-sif.outputs.cache-hit != 'true' }} - name: Build container - run: ./bin/build_container - - name: Generate extension PDF - run: ./do gen:profile[MockProfileRelease] + - name: Clone Github Repo Action + uses: actions/checkout@v4 + - name: Setup apptainer + uses: eWaterCycle/setup-apptainer@v2.0.0 + - name: Get container from cache + id: cache-sif + uses: actions/cache@v3 + with: + path: .singularity/image.sif + key: ${{ hashFiles('container.def', 'bin/.container-tag') }} + - name: Get gems and node files from cache + id: cache-bundle-npm + uses: actions/cache@v3 + with: + path: | + .home/.gems + node_modules + key: ${{ hashFiles('Gemfile.lock') }}-${{ hashFiles('package-lock.json') }} + - if: ${{ steps.cache-sif.outputs.cache-hit != 'true' }} + name: Build container + run: ./bin/build_container + - name: Generate extension PDF + run: ./do gen:profile[MockProfileRelease] diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml index 5412ccb614..c01d26e961 100644 --- a/.pre-commit-config.yaml +++ b/.pre-commit-config.yaml @@ -14,12 +14,13 @@ repos: exclude: \.adoc$ # sections titles Level 6 "=======" get flagged otherwise - id: check-json exclude: ^\.devcontainer/ # Uses JSONC (comments) + - id: check-yaml - repo: https://github.com/rbubley/mirrors-prettier rev: v3.3.3 hooks: - id: prettier - files: \.json$ + files: \.(json|yml|yaml)$ exclude: schemas/json-schema-draft-07.json - repo: https://github.com/python-jsonschema/check-jsonschema diff --git a/.solargraph.yml b/.solargraph.yml index ecddf8a95f..864b4acc8a 100644 --- a/.solargraph.yml +++ b/.solargraph.yml @@ -1,17 +1,17 @@ --- include: -- "lib/**/*.rb" -- "tasks/**/*.rake" + - "lib/**/*.rb" + - "tasks/**/*.rake" exclude: -- spec/**/* -- test/**/* -- vendor/**/* -- ".home/**/*" + - spec/**/* + - test/**/* + - vendor/**/* + - ".home/**/*" require: [] domains: [] reporters: -- rubocop -- require_not_found + - rubocop + - require_not_found formatter: rubocop: cops: safe @@ -19,6 +19,6 @@ formatter: only: [] extra_args: [] require_paths: -- /usr/lib/ruby/3.2.0 + - /usr/lib/ruby/3.2.0 plugins: [] max_files: 5000 diff --git a/Gemfile.lock b/Gemfile.lock index f2664dee0d..5774c36394 100644 --- a/Gemfile.lock +++ b/Gemfile.lock @@ -50,6 +50,8 @@ GEM language_server-protocol (3.17.0.3) matrix (0.4.2) minitest (5.24.1) + nokogiri (1.16.5-aarch64-linux) + racc (~> 1.4) nokogiri (1.16.5-x86_64-linux) racc (~> 1.4) parallel (1.24.0) @@ -140,6 +142,7 @@ GEM yard (0.9.36) PLATFORMS + aarch64-linux-gnu x86_64-linux-gnu DEPENDENCIES diff --git a/arch/certificate_class/MC.yaml b/arch/certificate_class/MC.yaml index d31c7a25f0..5650ea203f 100644 --- a/arch/certificate_class/MC.yaml +++ b/arch/certificate_class/MC.yaml @@ -35,4 +35,4 @@ naming_scheme: | ** A release indicates just CRD specification changes without any difference in functional behavior mandatory_priv_modes: -- M + - M diff --git a/arch/certificate_class/MockCertificateClass.yaml b/arch/certificate_class/MockCertificateClass.yaml index eebbbbbacd..4dc404972d 100644 --- a/arch/certificate_class/MockCertificateClass.yaml +++ b/arch/certificate_class/MockCertificateClass.yaml @@ -13,4 +13,4 @@ naming_scheme: | A Mock certificate class or model can have any name as long as it can be a hash key. mandatory_priv_modes: -- M + - M diff --git a/arch/certificate_model/MC100.yaml b/arch/certificate_model/MC100.yaml index 4589f965f1..4fdad7097c 100644 --- a/arch/certificate_model/MC100.yaml +++ b/arch/certificate_model/MC100.yaml @@ -9,63 +9,63 @@ class: # Semantic versions within the model versions: -- version: "1.0.0" + - version: "1.0.0" # XLEN used by rakefile base: 32 revision_history: -- revision: "0.7.0" - date: 2024-07-29 - changes: - - First version after moving non-microcontroller content in this document to a new document - called "RISC-V CRDs (Certification Requirement Documents)" - - Change MC100 Unpriv ISA spec from - "https://riscv.org/wp-content/uploads/2016/06/riscv-spec-v2.1.pdf[riscv-spec-v2.1], May 31, - 2016" to https://github.com/riscv/riscv-isa-manual/releases/tag/Ratified-IMAFDQC since the - former isn't ratified by the latter is the oldest ratified version. - - Added requirements for WFI instruction - - Added requirements related to msip memory-mapped register -- revision: "0.6.0" - date: 2024-07-11 - changes: - - Supporting multiple MC versions to support customers wanting to certify existing microcontrollers not using the latest version of ratified standards. - - Changed versioning scheme to use major.minor.patch instead of 3-digit major & minor. - - Added a table showing the mapping from MC version to ISA manuals. - - Reluctantly made interrupts OUT OF SCOPE for MC100 since only the CLINT interrupt controller - was ratified at that time and isn't anticipated to be the interrupt controller used by MC100 implementations. - - Clarified MANDATORY behaviors for mie and mip CSRs - - Removed canonical discovery recipe because the OPT-* options directly inform the certification - tests and certification reference model of the status of the various options. Also, canonical - discovery recipes (e.g., probing for CLIC) violate the certification approach of avoiding writing - potentially illegal values to CSR fields. - - Added more options for interrupts - - Moved non-microcontroller content in this document to a new document called "RISC-V Certification Plans" -- revision: "0.5.0" - date: 2024-06-03 - changes: - - Renamed to "RISC-V Microcontroller Certification Plan" based on Jason's recommendation - - Added mvendorid, marchid, mimpid, and mhardid read-only priv CSRs because Allen pointed out - these are mandatory in M-mode v1.13 (probably older versions too, haven't looked yet). - - Added table showing mapping of MC versions to associated RISC-V specifications -- revision: "0.4.0" - date: 2024-06-03 - changes: - - Added M-mode instruction requirements - - Made Zicntr MANDATORY due to very low cost for implementations to support (in the spirit of minimizing options). - - Removed OPT-CNTR-PREC since minstret and mcycle must be a full 64 bits to be standard-compliant. -- revision: "0.3.0" - date: 2024-05-25 - changes: - - Includes Zicntr as OPTIONAL and then has only 32-bit counters for instret and cycle. -- revision: "0.2.0" - date: 2024-05-20 - changes: - - Very early draft -- revision: "0.1.0" - date: 2024-05-16 - changes: - - Initial version + - revision: "0.7.0" + date: 2024-07-29 + changes: + - First version after moving non-microcontroller content in this document to a new document + called "RISC-V CRDs (Certification Requirement Documents)" + - Change MC100 Unpriv ISA spec from + "https://riscv.org/wp-content/uploads/2016/06/riscv-spec-v2.1.pdf[riscv-spec-v2.1], May 31, + 2016" to https://github.com/riscv/riscv-isa-manual/releases/tag/Ratified-IMAFDQC since the + former isn't ratified by the latter is the oldest ratified version. + - Added requirements for WFI instruction + - Added requirements related to msip memory-mapped register + - revision: "0.6.0" + date: 2024-07-11 + changes: + - Supporting multiple MC versions to support customers wanting to certify existing microcontrollers not using the latest version of ratified standards. + - Changed versioning scheme to use major.minor.patch instead of 3-digit major & minor. + - Added a table showing the mapping from MC version to ISA manuals. + - Reluctantly made interrupts OUT OF SCOPE for MC100 since only the CLINT interrupt controller + was ratified at that time and isn't anticipated to be the interrupt controller used by MC100 implementations. + - Clarified MANDATORY behaviors for mie and mip CSRs + - Removed canonical discovery recipe because the OPT-* options directly inform the certification + tests and certification reference model of the status of the various options. Also, canonical + discovery recipes (e.g., probing for CLIC) violate the certification approach of avoiding writing + potentially illegal values to CSR fields. + - Added more options for interrupts + - Moved non-microcontroller content in this document to a new document called "RISC-V Certification Plans" + - revision: "0.5.0" + date: 2024-06-03 + changes: + - Renamed to "RISC-V Microcontroller Certification Plan" based on Jason's recommendation + - Added mvendorid, marchid, mimpid, and mhardid read-only priv CSRs because Allen pointed out + these are mandatory in M-mode v1.13 (probably older versions too, haven't looked yet). + - Added table showing mapping of MC versions to associated RISC-V specifications + - revision: "0.4.0" + date: 2024-06-03 + changes: + - Added M-mode instruction requirements + - Made Zicntr MANDATORY due to very low cost for implementations to support (in the spirit of minimizing options). + - Removed OPT-CNTR-PREC since minstret and mcycle must be a full 64 bits to be standard-compliant. + - revision: "0.3.0" + date: 2024-05-25 + changes: + - Includes Zicntr as OPTIONAL and then has only 32-bit counters for instret and cycle. + - revision: "0.2.0" + date: 2024-05-20 + changes: + - Very early draft + - revision: "0.1.0" + date: 2024-05-16 + changes: + - Initial version description: | MC100 can be though of as minimal 32-bit RISC-V processors with M-mode support: @@ -104,39 +104,39 @@ extensions: version: "~> 2.0" presence: mandatory parameters: - TIME_CSR_IMPLEMENTED: {} # Unconstrained + TIME_CSR_IMPLEMENTED: {} # Unconstrained Sm: version: "~> 1.11.0" presence: mandatory parameters: - MTVEC_BASE_ALIGNMENT_DIRECT: {} # Unconstrained - MTVEC_BASE_ALIGNMENT_VECTORED: {} # Unconstrained - ARCH_ID: {} # Unconstrained - IMP_ID: {} # Unconstrained - VENDOR_ID_BANK: {} # Unconstrained - VENDOR_ID_OFFSET: {} # Unconstrained - MISA_CSR_IMPLEMENTED: {} # Unconstrained - MTVAL_WIDTH: {} # Unconstrained - MTVEC_MODES: {} # Unconstrained - PHYS_ADDR_WIDTH: {} # Unconstrained - MISALIGNED_LDST: {} # Unconstrained - MISALIGNED_LDST_EXCEPTION_PRIORITY : {} # Unconstrained - MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE: {} # Unconstrained - MISALIGNED_SPLIT_STRATEGY: - schema: - const: by_byte - PRECISE_SYNCHRONOUS_EXCEPTIONS: - schema: - const: true - TRAP_ON_ECALL_FROM_M: - schema: - const: true - TRAP_ON_EBREAK: - schema: - const: true - M_MODE_ENDIANESS: - schema: - const: little - XLEN: - schema: - const: 32 + MTVEC_BASE_ALIGNMENT_DIRECT: {} # Unconstrained + MTVEC_BASE_ALIGNMENT_VECTORED: {} # Unconstrained + ARCH_ID: {} # Unconstrained + IMP_ID: {} # Unconstrained + VENDOR_ID_BANK: {} # Unconstrained + VENDOR_ID_OFFSET: {} # Unconstrained + MISA_CSR_IMPLEMENTED: {} # Unconstrained + MTVAL_WIDTH: {} # Unconstrained + MTVEC_MODES: {} # Unconstrained + PHYS_ADDR_WIDTH: {} # Unconstrained + MISALIGNED_LDST: {} # Unconstrained + MISALIGNED_LDST_EXCEPTION_PRIORITY: {} # Unconstrained + MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE: {} # Unconstrained + MISALIGNED_SPLIT_STRATEGY: + schema: + const: by_byte + PRECISE_SYNCHRONOUS_EXCEPTIONS: + schema: + const: true + TRAP_ON_ECALL_FROM_M: + schema: + const: true + TRAP_ON_EBREAK: + schema: + const: true + M_MODE_ENDIANESS: + schema: + const: little + XLEN: + schema: + const: 32 diff --git a/arch/certificate_model/MockCertificateModel.yaml b/arch/certificate_model/MockCertificateModel.yaml index 188a05b82f..951c892ee9 100644 --- a/arch/certificate_model/MockCertificateModel.yaml +++ b/arch/certificate_model/MockCertificateModel.yaml @@ -16,14 +16,14 @@ versions: - version: "1.1.0" revision_history: -- revision: "0.1.0" - date: 2024-10-04 - changes: - - Created to test CRDs -- revision: "0.2.0" - date: 2024-10-05 - changes: - - Also created to test CRDs + - revision: "0.1.0" + date: 2024-10-04 + changes: + - Created to test CRDs + - revision: "0.2.0" + date: 2024-10-05 + changes: + - Also created to test CRDs description: | Mock CRD description: @@ -40,8 +40,8 @@ debug_manual_revision: "0.13.2" # XXX - Remove version information since specifying priv/unpriv ISA manual should imply this. extensions: $inherits: - - "profile_release/MockProfileRelease.yaml#/MockProfileRelease/profiles/MP-U-64/extensions" - - "profile_release/MockProfileRelease.yaml#/MockProfileRelease/profiles/MP-S-64/extensions" + - "profile_release/MockProfileRelease.yaml#/MockProfileRelease/profiles/MP-U-64/extensions" + - "profile_release/MockProfileRelease.yaml#/MockProfileRelease/profiles/MP-S-64/extensions" I: note: Just added this note to I extension MockExt: @@ -70,17 +70,17 @@ extensions: MOCK_ARRAY_BOOL_ARRAY_OF_8_FIRST_2_FALSE: {} MOCK_ARRAY_STRING_ENUM1: schema: - const : DEF + const: DEF MOCK_ARRAY_STRING_ENUM2: schema: - contains: { const : DEF } + contains: { const: DEF } C: version: "~> 2.2" presence: mandatory parameters: - MUTABLE_MISA_C: - schema: - const: false + MUTABLE_MISA_C: + schema: + const: false note: | Here's a multi-line note + for the C extension. @@ -91,68 +91,68 @@ extensions: version: "~> 2.0" presence: mandatory parameters: - TIME_CSR_IMPLEMENTED: {} # Unconstrained + TIME_CSR_IMPLEMENTED: {} # Unconstrained Sm: version: "~> 1.11" presence: mandatory parameters: - MTVEC_BASE_ALIGNMENT_DIRECT: {} # Unconstrained - MTVEC_BASE_ALIGNMENT_VECTORED: {} # Unconstrained - ARCH_ID: {} # Unconstrained - IMP_ID: {} # Unconstrained - VENDOR_ID_BANK: {} # Unconstrained - VENDOR_ID_OFFSET: {} # Unconstrained - MISA_CSR_IMPLEMENTED: {} # Unconstrained - MTVAL_WIDTH: {} # Unconstrained - MTVEC_MODES: - note: Here's a note for MTVEC_MODES parameter. - schema: - contains: { const : 0 } - PHYS_ADDR_WIDTH: {} # Unconstrained - PRECISE_SYNCHRONOUS_EXCEPTIONS: - schema: - const: true - TRAP_ON_ECALL_FROM_M: - schema: - const: true - TRAP_ON_EBREAK: - schema: - const: true - REPORT_VA_IN_MTVAL_ON_BREAKPOINT: - schema: - const: true - REPORT_VA_IN_MTVAL_ON_INSTRUCTION_ACCESS_FAULT: - schema: - const: true - REPORT_VA_IN_MTVAL_ON_LOAD_ACCESS_FAULT: - schema: - const: true - REPORT_VA_IN_MTVAL_ON_STORE_AMO_ACCESS_FAULT: - schema: - const: true - REPORT_ENCODING_IN_MTVAL_ON_ILLEGAL_INSTRUCTION: - schema: - const: true - M_MODE_ENDIANESS: - schema: - const: little - # Uncomment when GitHub issue # is fixed. - #schema: - #- when: - # version: "=1.0.0" - # then: - # const: little - #- when: - # version: "=1.1.0" - # then: - # enum: [little, big] - XLEN: - schema: - const: 64 - CONFIG_PTR_ADDRESS: - schema: - const: 0xdeadbeef - note: "This parameter and its associated CSR shouldn't be here. See GitHub issue #53." + MTVEC_BASE_ALIGNMENT_DIRECT: {} # Unconstrained + MTVEC_BASE_ALIGNMENT_VECTORED: {} # Unconstrained + ARCH_ID: {} # Unconstrained + IMP_ID: {} # Unconstrained + VENDOR_ID_BANK: {} # Unconstrained + VENDOR_ID_OFFSET: {} # Unconstrained + MISA_CSR_IMPLEMENTED: {} # Unconstrained + MTVAL_WIDTH: {} # Unconstrained + MTVEC_MODES: + note: Here's a note for MTVEC_MODES parameter. + schema: + contains: { const: 0 } + PHYS_ADDR_WIDTH: {} # Unconstrained + PRECISE_SYNCHRONOUS_EXCEPTIONS: + schema: + const: true + TRAP_ON_ECALL_FROM_M: + schema: + const: true + TRAP_ON_EBREAK: + schema: + const: true + REPORT_VA_IN_MTVAL_ON_BREAKPOINT: + schema: + const: true + REPORT_VA_IN_MTVAL_ON_INSTRUCTION_ACCESS_FAULT: + schema: + const: true + REPORT_VA_IN_MTVAL_ON_LOAD_ACCESS_FAULT: + schema: + const: true + REPORT_VA_IN_MTVAL_ON_STORE_AMO_ACCESS_FAULT: + schema: + const: true + REPORT_ENCODING_IN_MTVAL_ON_ILLEGAL_INSTRUCTION: + schema: + const: true + M_MODE_ENDIANESS: + schema: + const: little + # Uncomment when GitHub issue # is fixed. + #schema: + #- when: + # version: "=1.0.0" + # then: + # const: little + #- when: + # version: "=1.1.0" + # then: + # enum: [little, big] + XLEN: + schema: + const: 64 + CONFIG_PTR_ADDRESS: + schema: + const: 0xdeadbeef + note: "This parameter and its associated CSR shouldn't be here. See GitHub issue #53." Zifencei: presence: optional note: "Here's a note for Zifencei" @@ -160,16 +160,16 @@ extensions: presence: optional note: "Testing CACHE_BLOCK_SIZE parameter which is also defined by Zicbom." parameters: - CACHE_BLOCK_SIZE: - schema: - const: 64 + CACHE_BLOCK_SIZE: + schema: + const: 64 Zicbom: presence: optional note: "Testing CACHE_BLOCK_SIZE parameter which is also defined by Zicbop." parameters: - CACHE_BLOCK_SIZE: - schema: - const: 64 + CACHE_BLOCK_SIZE: + schema: + const: 64 Zba: presence: mandatory version: "~> 1.0" @@ -188,10 +188,10 @@ requirement_groups: description: | A bunch of additional requirements not associated with an extension. requirements: - - name: REQ-ANY-XLEN-001 - description: Must pay your taxes on time - - name: REQ-ANY-XLEN-002 - description: Don't count your chickens before they're hatched! + - name: REQ-ANY-XLEN-001 + description: Must pay your taxes on time + - name: REQ-ANY-XLEN-002 + description: Don't count your chickens before they're hatched! - name: Req-Grp-XLEN32 when: @@ -199,8 +199,8 @@ requirement_groups: description: | A bunch of additional requirements only that should show up for XLEN=32 requirements: - - name: REQ-XLEN32-001 - description: Need lots of extra CSRs with `h` suffix + - name: REQ-XLEN32-001 + description: Need lots of extra CSRs with `h` suffix - name: Req-Grp-XLEN64 when: @@ -208,19 +208,19 @@ requirement_groups: description: | A bunch of additional requirements only that should show up for XLEN=64 requirements: - - name: REQ-XLEN64-001 - description: Can avoid adding extra CSRs with `h` suffix + - name: REQ-XLEN64-001 + description: Can avoid adding extra CSRs with `h` suffix extra_notes: -- presence: optional - text: Here's the first extra note for the optional extensions section. -- presence: mandatory - text: | - Here's the first extra note for the mandatory extensions section. - This note is multiple lines. -- presence: optional - text: Here's the second extra note for the optional extensions section. + - presence: optional + text: Here's the first extra note for the optional extensions section. + - presence: mandatory + text: | + Here's the first extra note for the mandatory extensions section. + This note is multiple lines. + - presence: optional + text: Here's the second extra note for the optional extensions section. recommendations: -- text: | - Implementations are strongly recommended to raise illegal-instruction - exceptions on attempts to execute unimplemented opcodes. -- text: Micky should give Pluto an extra treat + - text: | + Implementations are strongly recommended to raise illegal-instruction + exceptions on attempts to execute unimplemented opcodes. + - text: Micky should give Pluto an extra treat diff --git a/arch/common/inst_variable_types.yaml b/arch/common/inst_variable_types.yaml index 359523020c..7824ae5acf 100644 --- a/arch/common/inst_variable_types.yaml +++ b/arch/common/inst_variable_types.yaml @@ -1,5 +1,4 @@ # yaml-language-server: $schema=../../schemas/inst_variable_metadatas.json --- - itype_imm: location: 31-20 diff --git a/arch/csr/H/hcounteren.yaml b/arch/csr/H/hcounteren.yaml index 7623bce731..46b2f2f1bb 100644 --- a/arch/csr/H/hcounteren.yaml +++ b/arch/csr/H/hcounteren.yaml @@ -2,7 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/H/hcounteren.layout - $schema: csr_schema.json# kind: csr name: hcounteren diff --git a/arch/csr/H/hgatp.yaml b/arch/csr/H/hgatp.yaml index 43a84b54a9..034b1d0178 100644 --- a/arch/csr/H/hgatp.yaml +++ b/arch/csr/H/hgatp.yaml @@ -198,7 +198,7 @@ fields: location_rv32: 21-0 location_rv64: 43-0 description: | - The physical page number (PPN) of the guest-physical root page table. + The physical page number (PPN) of the guest-physical root page table. type(): | if (!SV32X4_TRANSLATION && !SV39X4_TRANSLATION && !SV48X4_TRANSLATION && !SV57X4_TRANSLATION) { # Bare is the only supported mode, PPN is always 0 diff --git a/arch/csr/I/mcounteren.yaml b/arch/csr/I/mcounteren.yaml index eb904c4542..23c4a48656 100644 --- a/arch/csr/I/mcounteren.yaml +++ b/arch/csr/I/mcounteren.yaml @@ -2,7 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/mcounteren.layout - $schema: csr_schema.json# kind: csr name: mcounteren @@ -84,7 +83,6 @@ description: | . <%- end -%> - definedBy: U # actually, defined by RV64, but must implement U-mode for this CSR to exist fields: CY: diff --git a/arch/csr/I/pmpaddr0.yaml b/arch/csr/I/pmpaddr0.yaml index 22ef1b4938..250d438c06 100644 --- a/arch/csr/I/pmpaddr0.yaml +++ b/arch/csr/I/pmpaddr0.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr0 diff --git a/arch/csr/I/pmpaddr1.yaml b/arch/csr/I/pmpaddr1.yaml index 1c5ccf42b9..5e24bf677c 100644 --- a/arch/csr/I/pmpaddr1.yaml +++ b/arch/csr/I/pmpaddr1.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr1 diff --git a/arch/csr/I/pmpaddr10.yaml b/arch/csr/I/pmpaddr10.yaml index 55fc27da34..a7da04a4b6 100644 --- a/arch/csr/I/pmpaddr10.yaml +++ b/arch/csr/I/pmpaddr10.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr10 diff --git a/arch/csr/I/pmpaddr11.yaml b/arch/csr/I/pmpaddr11.yaml index deca16c148..a8ccd0b6bc 100644 --- a/arch/csr/I/pmpaddr11.yaml +++ b/arch/csr/I/pmpaddr11.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr11 diff --git a/arch/csr/I/pmpaddr12.yaml b/arch/csr/I/pmpaddr12.yaml index bc4a1a004a..10f1f2efe5 100644 --- a/arch/csr/I/pmpaddr12.yaml +++ b/arch/csr/I/pmpaddr12.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr12 diff --git a/arch/csr/I/pmpaddr13.yaml b/arch/csr/I/pmpaddr13.yaml index 99b51637a5..99d40a0936 100644 --- a/arch/csr/I/pmpaddr13.yaml +++ b/arch/csr/I/pmpaddr13.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr13 diff --git a/arch/csr/I/pmpaddr14.yaml b/arch/csr/I/pmpaddr14.yaml index 0223aa2ab4..cda0e1265e 100644 --- a/arch/csr/I/pmpaddr14.yaml +++ b/arch/csr/I/pmpaddr14.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr14 diff --git a/arch/csr/I/pmpaddr15.yaml b/arch/csr/I/pmpaddr15.yaml index 5465794652..1cb1232715 100644 --- a/arch/csr/I/pmpaddr15.yaml +++ b/arch/csr/I/pmpaddr15.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr15 diff --git a/arch/csr/I/pmpaddr16.yaml b/arch/csr/I/pmpaddr16.yaml index 8c4a403d84..d766d82fa5 100644 --- a/arch/csr/I/pmpaddr16.yaml +++ b/arch/csr/I/pmpaddr16.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr16 diff --git a/arch/csr/I/pmpaddr17.yaml b/arch/csr/I/pmpaddr17.yaml index 31ea87ecda..94b5b47b47 100644 --- a/arch/csr/I/pmpaddr17.yaml +++ b/arch/csr/I/pmpaddr17.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr17 diff --git a/arch/csr/I/pmpaddr18.yaml b/arch/csr/I/pmpaddr18.yaml index 42927d3e5b..1006a07df5 100644 --- a/arch/csr/I/pmpaddr18.yaml +++ b/arch/csr/I/pmpaddr18.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr18 diff --git a/arch/csr/I/pmpaddr19.yaml b/arch/csr/I/pmpaddr19.yaml index 1d6d4e3320..7caa8cfbed 100644 --- a/arch/csr/I/pmpaddr19.yaml +++ b/arch/csr/I/pmpaddr19.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr19 diff --git a/arch/csr/I/pmpaddr2.yaml b/arch/csr/I/pmpaddr2.yaml index 7b028ad20c..8805ecdafe 100644 --- a/arch/csr/I/pmpaddr2.yaml +++ b/arch/csr/I/pmpaddr2.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr2 diff --git a/arch/csr/I/pmpaddr20.yaml b/arch/csr/I/pmpaddr20.yaml index 4706bddad8..2479fbb520 100644 --- a/arch/csr/I/pmpaddr20.yaml +++ b/arch/csr/I/pmpaddr20.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr20 diff --git a/arch/csr/I/pmpaddr21.yaml b/arch/csr/I/pmpaddr21.yaml index 235ebd0882..27f99fec38 100644 --- a/arch/csr/I/pmpaddr21.yaml +++ b/arch/csr/I/pmpaddr21.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr21 diff --git a/arch/csr/I/pmpaddr22.yaml b/arch/csr/I/pmpaddr22.yaml index da683c397e..e738359032 100644 --- a/arch/csr/I/pmpaddr22.yaml +++ b/arch/csr/I/pmpaddr22.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr22 diff --git a/arch/csr/I/pmpaddr23.yaml b/arch/csr/I/pmpaddr23.yaml index 86fd9e5682..b23078e01e 100644 --- a/arch/csr/I/pmpaddr23.yaml +++ b/arch/csr/I/pmpaddr23.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr23 diff --git a/arch/csr/I/pmpaddr24.yaml b/arch/csr/I/pmpaddr24.yaml index eb23278cf9..f07a22f661 100644 --- a/arch/csr/I/pmpaddr24.yaml +++ b/arch/csr/I/pmpaddr24.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr24 diff --git a/arch/csr/I/pmpaddr25.yaml b/arch/csr/I/pmpaddr25.yaml index 779b656eba..c3a791b223 100644 --- a/arch/csr/I/pmpaddr25.yaml +++ b/arch/csr/I/pmpaddr25.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr25 diff --git a/arch/csr/I/pmpaddr26.yaml b/arch/csr/I/pmpaddr26.yaml index 6a1b7445e8..ad2d1cb063 100644 --- a/arch/csr/I/pmpaddr26.yaml +++ b/arch/csr/I/pmpaddr26.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr26 diff --git a/arch/csr/I/pmpaddr27.yaml b/arch/csr/I/pmpaddr27.yaml index 3960dda990..ef27d3bf9c 100644 --- a/arch/csr/I/pmpaddr27.yaml +++ b/arch/csr/I/pmpaddr27.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr27 diff --git a/arch/csr/I/pmpaddr28.yaml b/arch/csr/I/pmpaddr28.yaml index 062e089ded..b7f1bf4278 100644 --- a/arch/csr/I/pmpaddr28.yaml +++ b/arch/csr/I/pmpaddr28.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr28 diff --git a/arch/csr/I/pmpaddr29.yaml b/arch/csr/I/pmpaddr29.yaml index 770c88ddce..7a0a971ad6 100644 --- a/arch/csr/I/pmpaddr29.yaml +++ b/arch/csr/I/pmpaddr29.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr29 diff --git a/arch/csr/I/pmpaddr3.yaml b/arch/csr/I/pmpaddr3.yaml index b533c59961..7d79c0b926 100644 --- a/arch/csr/I/pmpaddr3.yaml +++ b/arch/csr/I/pmpaddr3.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr3 diff --git a/arch/csr/I/pmpaddr30.yaml b/arch/csr/I/pmpaddr30.yaml index 6ef468278b..0b8481e85d 100644 --- a/arch/csr/I/pmpaddr30.yaml +++ b/arch/csr/I/pmpaddr30.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr30 diff --git a/arch/csr/I/pmpaddr31.yaml b/arch/csr/I/pmpaddr31.yaml index 031f099eb0..cb6889d511 100644 --- a/arch/csr/I/pmpaddr31.yaml +++ b/arch/csr/I/pmpaddr31.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr31 diff --git a/arch/csr/I/pmpaddr32.yaml b/arch/csr/I/pmpaddr32.yaml index 9c6b6b9b1b..ef38ca7aab 100644 --- a/arch/csr/I/pmpaddr32.yaml +++ b/arch/csr/I/pmpaddr32.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr32 diff --git a/arch/csr/I/pmpaddr33.yaml b/arch/csr/I/pmpaddr33.yaml index 6f90b581e4..8bac474921 100644 --- a/arch/csr/I/pmpaddr33.yaml +++ b/arch/csr/I/pmpaddr33.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr33 diff --git a/arch/csr/I/pmpaddr34.yaml b/arch/csr/I/pmpaddr34.yaml index 64c83a7e52..8c06828a18 100644 --- a/arch/csr/I/pmpaddr34.yaml +++ b/arch/csr/I/pmpaddr34.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr34 diff --git a/arch/csr/I/pmpaddr35.yaml b/arch/csr/I/pmpaddr35.yaml index 9ed46e1dd6..8cc63fde59 100644 --- a/arch/csr/I/pmpaddr35.yaml +++ b/arch/csr/I/pmpaddr35.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr35 diff --git a/arch/csr/I/pmpaddr36.yaml b/arch/csr/I/pmpaddr36.yaml index 770a97f9a5..4b22831126 100644 --- a/arch/csr/I/pmpaddr36.yaml +++ b/arch/csr/I/pmpaddr36.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr36 diff --git a/arch/csr/I/pmpaddr37.yaml b/arch/csr/I/pmpaddr37.yaml index a93a78a011..957132029e 100644 --- a/arch/csr/I/pmpaddr37.yaml +++ b/arch/csr/I/pmpaddr37.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr37 diff --git a/arch/csr/I/pmpaddr38.yaml b/arch/csr/I/pmpaddr38.yaml index b74030c198..4979a53a5e 100644 --- a/arch/csr/I/pmpaddr38.yaml +++ b/arch/csr/I/pmpaddr38.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr38 diff --git a/arch/csr/I/pmpaddr39.yaml b/arch/csr/I/pmpaddr39.yaml index f9966eaa98..41340b4953 100644 --- a/arch/csr/I/pmpaddr39.yaml +++ b/arch/csr/I/pmpaddr39.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr39 diff --git a/arch/csr/I/pmpaddr4.yaml b/arch/csr/I/pmpaddr4.yaml index 4ea909757e..0a5d45b7ab 100644 --- a/arch/csr/I/pmpaddr4.yaml +++ b/arch/csr/I/pmpaddr4.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr4 diff --git a/arch/csr/I/pmpaddr40.yaml b/arch/csr/I/pmpaddr40.yaml index 496d6a9b88..21b3cf11fe 100644 --- a/arch/csr/I/pmpaddr40.yaml +++ b/arch/csr/I/pmpaddr40.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr40 diff --git a/arch/csr/I/pmpaddr41.yaml b/arch/csr/I/pmpaddr41.yaml index c187fa435b..6bb1bafc97 100644 --- a/arch/csr/I/pmpaddr41.yaml +++ b/arch/csr/I/pmpaddr41.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr41 diff --git a/arch/csr/I/pmpaddr42.yaml b/arch/csr/I/pmpaddr42.yaml index 4daef7a3c4..bdab7845a1 100644 --- a/arch/csr/I/pmpaddr42.yaml +++ b/arch/csr/I/pmpaddr42.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr42 diff --git a/arch/csr/I/pmpaddr43.yaml b/arch/csr/I/pmpaddr43.yaml index e8dd8f9493..91b1812bcf 100644 --- a/arch/csr/I/pmpaddr43.yaml +++ b/arch/csr/I/pmpaddr43.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr43 diff --git a/arch/csr/I/pmpaddr44.yaml b/arch/csr/I/pmpaddr44.yaml index 1ccd84dfc5..5d0cdfca6f 100644 --- a/arch/csr/I/pmpaddr44.yaml +++ b/arch/csr/I/pmpaddr44.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr44 diff --git a/arch/csr/I/pmpaddr45.yaml b/arch/csr/I/pmpaddr45.yaml index e600d8e97e..18e02b28cd 100644 --- a/arch/csr/I/pmpaddr45.yaml +++ b/arch/csr/I/pmpaddr45.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr45 diff --git a/arch/csr/I/pmpaddr46.yaml b/arch/csr/I/pmpaddr46.yaml index 9869421e0d..950b7b2b89 100644 --- a/arch/csr/I/pmpaddr46.yaml +++ b/arch/csr/I/pmpaddr46.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr46 diff --git a/arch/csr/I/pmpaddr47.yaml b/arch/csr/I/pmpaddr47.yaml index 7f5b867a43..fb6a5f4222 100644 --- a/arch/csr/I/pmpaddr47.yaml +++ b/arch/csr/I/pmpaddr47.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr47 diff --git a/arch/csr/I/pmpaddr48.yaml b/arch/csr/I/pmpaddr48.yaml index 739549f6c2..9eba2608ad 100644 --- a/arch/csr/I/pmpaddr48.yaml +++ b/arch/csr/I/pmpaddr48.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr48 diff --git a/arch/csr/I/pmpaddr49.yaml b/arch/csr/I/pmpaddr49.yaml index e14ed4ff65..26cb239966 100644 --- a/arch/csr/I/pmpaddr49.yaml +++ b/arch/csr/I/pmpaddr49.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr49 diff --git a/arch/csr/I/pmpaddr5.yaml b/arch/csr/I/pmpaddr5.yaml index 998712e5ca..8a73ce45e6 100644 --- a/arch/csr/I/pmpaddr5.yaml +++ b/arch/csr/I/pmpaddr5.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr5 diff --git a/arch/csr/I/pmpaddr50.yaml b/arch/csr/I/pmpaddr50.yaml index 6226177fc2..69aff1deca 100644 --- a/arch/csr/I/pmpaddr50.yaml +++ b/arch/csr/I/pmpaddr50.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr50 diff --git a/arch/csr/I/pmpaddr51.yaml b/arch/csr/I/pmpaddr51.yaml index 45461b0011..d5d6464f49 100644 --- a/arch/csr/I/pmpaddr51.yaml +++ b/arch/csr/I/pmpaddr51.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr51 diff --git a/arch/csr/I/pmpaddr52.yaml b/arch/csr/I/pmpaddr52.yaml index 9369082553..49ace51ac0 100644 --- a/arch/csr/I/pmpaddr52.yaml +++ b/arch/csr/I/pmpaddr52.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr52 diff --git a/arch/csr/I/pmpaddr53.yaml b/arch/csr/I/pmpaddr53.yaml index 8e6e625ec9..222efed3b3 100644 --- a/arch/csr/I/pmpaddr53.yaml +++ b/arch/csr/I/pmpaddr53.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr53 diff --git a/arch/csr/I/pmpaddr54.yaml b/arch/csr/I/pmpaddr54.yaml index be5082f313..6f7e7677d5 100644 --- a/arch/csr/I/pmpaddr54.yaml +++ b/arch/csr/I/pmpaddr54.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr54 diff --git a/arch/csr/I/pmpaddr55.yaml b/arch/csr/I/pmpaddr55.yaml index 0602b076f8..0f9d5a5063 100644 --- a/arch/csr/I/pmpaddr55.yaml +++ b/arch/csr/I/pmpaddr55.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr55 diff --git a/arch/csr/I/pmpaddr56.yaml b/arch/csr/I/pmpaddr56.yaml index 0a2be33f06..4ca1bd3e55 100644 --- a/arch/csr/I/pmpaddr56.yaml +++ b/arch/csr/I/pmpaddr56.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr56 diff --git a/arch/csr/I/pmpaddr57.yaml b/arch/csr/I/pmpaddr57.yaml index 1896ef4c64..bde0f738bf 100644 --- a/arch/csr/I/pmpaddr57.yaml +++ b/arch/csr/I/pmpaddr57.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr57 diff --git a/arch/csr/I/pmpaddr58.yaml b/arch/csr/I/pmpaddr58.yaml index 78838af7d4..6fa1aa32e5 100644 --- a/arch/csr/I/pmpaddr58.yaml +++ b/arch/csr/I/pmpaddr58.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr58 diff --git a/arch/csr/I/pmpaddr59.yaml b/arch/csr/I/pmpaddr59.yaml index 8494a9ee53..794787cfd1 100644 --- a/arch/csr/I/pmpaddr59.yaml +++ b/arch/csr/I/pmpaddr59.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr59 diff --git a/arch/csr/I/pmpaddr6.yaml b/arch/csr/I/pmpaddr6.yaml index eba8235753..28733415e1 100644 --- a/arch/csr/I/pmpaddr6.yaml +++ b/arch/csr/I/pmpaddr6.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr6 diff --git a/arch/csr/I/pmpaddr60.yaml b/arch/csr/I/pmpaddr60.yaml index b33f867e99..2932496683 100644 --- a/arch/csr/I/pmpaddr60.yaml +++ b/arch/csr/I/pmpaddr60.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr60 diff --git a/arch/csr/I/pmpaddr61.yaml b/arch/csr/I/pmpaddr61.yaml index 55c4244d9c..9570264235 100644 --- a/arch/csr/I/pmpaddr61.yaml +++ b/arch/csr/I/pmpaddr61.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr61 diff --git a/arch/csr/I/pmpaddr62.yaml b/arch/csr/I/pmpaddr62.yaml index ba3ffcece2..0ae068f5d1 100644 --- a/arch/csr/I/pmpaddr62.yaml +++ b/arch/csr/I/pmpaddr62.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr62 diff --git a/arch/csr/I/pmpaddr63.yaml b/arch/csr/I/pmpaddr63.yaml index 40cf7a6e29..d448de1db1 100644 --- a/arch/csr/I/pmpaddr63.yaml +++ b/arch/csr/I/pmpaddr63.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr63 diff --git a/arch/csr/I/pmpaddr7.yaml b/arch/csr/I/pmpaddr7.yaml index 105d6cbf22..710c597570 100644 --- a/arch/csr/I/pmpaddr7.yaml +++ b/arch/csr/I/pmpaddr7.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr7 diff --git a/arch/csr/I/pmpaddr8.yaml b/arch/csr/I/pmpaddr8.yaml index 355789fcbc..e6807b1669 100644 --- a/arch/csr/I/pmpaddr8.yaml +++ b/arch/csr/I/pmpaddr8.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr8 diff --git a/arch/csr/I/pmpaddr9.yaml b/arch/csr/I/pmpaddr9.yaml index 827cb70d2e..5cefea0afd 100644 --- a/arch/csr/I/pmpaddr9.yaml +++ b/arch/csr/I/pmpaddr9.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpaddrN.layout - - $schema: csr_schema.json# kind: csr name: pmpaddr9 diff --git a/arch/csr/I/pmpcfg0.yaml b/arch/csr/I/pmpcfg0.yaml index 51714e954a..63d55e9e34 100644 --- a/arch/csr/I/pmpcfg0.yaml +++ b/arch/csr/I/pmpcfg0.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpcfgN.layout - - $schema: csr_schema.json# kind: csr name: pmpcfg0 @@ -17,39 +15,39 @@ fields: pmp0cfg: location: 7-0 description: | - *PMP configuration for entry 0* + *PMP configuration for entry 0* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 6:5 ! _Reserved_ Writes shall be ignored. - h! A ! 4:3 - a! Address matching mode. One of: + h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 6:5 ! _Reserved_ Writes shall be ignored. + h! A ! 4:3 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 0) { return CsrFieldType::RWR; @@ -79,39 +77,39 @@ fields: pmp1cfg: location: 15-8 description: | - *PMP configuration for entry 1* + *PMP configuration for entry 1* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 14:13 ! _Reserved_ Writes shall be ignored. - h! A ! 12:11 - a! Address matching mode. One of: + h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 14:13 ! _Reserved_ Writes shall be ignored. + h! A ! 12:11 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 1) { return CsrFieldType::RWR; @@ -141,39 +139,39 @@ fields: pmp2cfg: location: 23-16 description: | - *PMP configuration for entry 2* + *PMP configuration for entry 2* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 22:21 ! _Reserved_ Writes shall be ignored. - h! A ! 20:19 - a! Address matching mode. One of: + h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 22:21 ! _Reserved_ Writes shall be ignored. + h! A ! 20:19 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 2) { return CsrFieldType::RWR; @@ -203,39 +201,39 @@ fields: pmp3cfg: location: 31-24 description: | - *PMP configuration for entry 3* + *PMP configuration for entry 3* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 30:29 ! _Reserved_ Writes shall be ignored. - h! A ! 28:27 - a! Address matching mode. One of: + h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 30:29 ! _Reserved_ Writes shall be ignored. + h! A ! 28:27 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 3) { return CsrFieldType::RWR; @@ -266,39 +264,39 @@ fields: location: 39-32 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 4* + *PMP configuration for entry 4* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 39 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 38:37 ! _Reserved_ Writes shall be ignored. - h! A ! 36:35 - a! Address matching mode. One of: + h! L ! 39 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 38:37 ! _Reserved_ Writes shall be ignored. + h! A ! 36:35 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 34 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 33 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 32 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 34 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 33 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 32 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 4) { return CsrFieldType::RWR; @@ -329,39 +327,39 @@ fields: location: 47-40 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 5* + *PMP configuration for entry 5* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 47 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 46:45 ! _Reserved_ Writes shall be ignored. - h! A ! 44:43 - a! Address matching mode. One of: + h! L ! 47 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 46:45 ! _Reserved_ Writes shall be ignored. + h! A ! 44:43 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 42 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 41 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 40 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 42 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 41 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 40 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 5) { return CsrFieldType::RWR; @@ -392,39 +390,39 @@ fields: location: 55-48 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 6* + *PMP configuration for entry 6* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 55 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 54:53 ! _Reserved_ Writes shall be ignored. - h! A ! 52:51 - a! Address matching mode. One of: + h! L ! 55 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 54:53 ! _Reserved_ Writes shall be ignored. + h! A ! 52:51 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 50 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 49 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 48 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 50 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 49 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 48 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 6) { return CsrFieldType::RWR; @@ -455,39 +453,39 @@ fields: location: 63-56 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 7* + *PMP configuration for entry 7* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 63 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 62:61 ! _Reserved_ Writes shall be ignored. - h! A ! 60:59 - a! Address matching mode. One of: + h! L ! 63 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 62:61 ! _Reserved_ Writes shall be ignored. + h! A ! 60:59 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 58 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 57 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 56 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 58 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 57 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 56 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 7) { return CsrFieldType::RWR; diff --git a/arch/csr/I/pmpcfg1.yaml b/arch/csr/I/pmpcfg1.yaml index 44e262a696..7d1f4480e2 100644 --- a/arch/csr/I/pmpcfg1.yaml +++ b/arch/csr/I/pmpcfg1.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpcfgN.layout - - $schema: csr_schema.json# kind: csr name: pmpcfg1 @@ -18,39 +16,39 @@ fields: pmp4cfg: location: 7-0 description: | - *PMP configuration for entry 4* + *PMP configuration for entry 4* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 6:5 ! _Reserved_ Writes shall be ignored. - h! A ! 4:3 - a! Address matching mode. One of: + h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 6:5 ! _Reserved_ Writes shall be ignored. + h! A ! 4:3 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 4) { return CsrFieldType::RWR; @@ -80,39 +78,39 @@ fields: pmp5cfg: location: 15-8 description: | - *PMP configuration for entry 5* + *PMP configuration for entry 5* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 14:13 ! _Reserved_ Writes shall be ignored. - h! A ! 12:11 - a! Address matching mode. One of: + h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 14:13 ! _Reserved_ Writes shall be ignored. + h! A ! 12:11 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 5) { return CsrFieldType::RWR; @@ -142,39 +140,39 @@ fields: pmp6cfg: location: 23-16 description: | - *PMP configuration for entry 6* + *PMP configuration for entry 6* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 22:21 ! _Reserved_ Writes shall be ignored. - h! A ! 20:19 - a! Address matching mode. One of: + h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 22:21 ! _Reserved_ Writes shall be ignored. + h! A ! 20:19 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 6) { return CsrFieldType::RWR; @@ -204,39 +202,39 @@ fields: pmp7cfg: location: 31-24 description: | - *PMP configuration for entry 7* + *PMP configuration for entry 7* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 30:29 ! _Reserved_ Writes shall be ignored. - h! A ! 28:27 - a! Address matching mode. One of: + h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 30:29 ! _Reserved_ Writes shall be ignored. + h! A ! 28:27 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 7) { return CsrFieldType::RWR; diff --git a/arch/csr/I/pmpcfg10.yaml b/arch/csr/I/pmpcfg10.yaml index aa4343c0fb..1773750b61 100644 --- a/arch/csr/I/pmpcfg10.yaml +++ b/arch/csr/I/pmpcfg10.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpcfgN.layout - - $schema: csr_schema.json# kind: csr name: pmpcfg10 @@ -17,39 +15,39 @@ fields: pmp40cfg: location: 7-0 description: | - *PMP configuration for entry 40* + *PMP configuration for entry 40* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 6:5 ! _Reserved_ Writes shall be ignored. - h! A ! 4:3 - a! Address matching mode. One of: + h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 6:5 ! _Reserved_ Writes shall be ignored. + h! A ! 4:3 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 40) { return CsrFieldType::RWR; @@ -79,39 +77,39 @@ fields: pmp41cfg: location: 15-8 description: | - *PMP configuration for entry 41* + *PMP configuration for entry 41* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 14:13 ! _Reserved_ Writes shall be ignored. - h! A ! 12:11 - a! Address matching mode. One of: + h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 14:13 ! _Reserved_ Writes shall be ignored. + h! A ! 12:11 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 41) { return CsrFieldType::RWR; @@ -141,39 +139,39 @@ fields: pmp42cfg: location: 23-16 description: | - *PMP configuration for entry 42* + *PMP configuration for entry 42* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 22:21 ! _Reserved_ Writes shall be ignored. - h! A ! 20:19 - a! Address matching mode. One of: + h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 22:21 ! _Reserved_ Writes shall be ignored. + h! A ! 20:19 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 42) { return CsrFieldType::RWR; @@ -203,39 +201,39 @@ fields: pmp43cfg: location: 31-24 description: | - *PMP configuration for entry 43* + *PMP configuration for entry 43* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 30:29 ! _Reserved_ Writes shall be ignored. - h! A ! 28:27 - a! Address matching mode. One of: + h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 30:29 ! _Reserved_ Writes shall be ignored. + h! A ! 28:27 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 43) { return CsrFieldType::RWR; @@ -266,39 +264,39 @@ fields: location: 39-32 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 44* + *PMP configuration for entry 44* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 39 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 38:37 ! _Reserved_ Writes shall be ignored. - h! A ! 36:35 - a! Address matching mode. One of: + h! L ! 39 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 38:37 ! _Reserved_ Writes shall be ignored. + h! A ! 36:35 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 34 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 33 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 32 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 34 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 33 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 32 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 44) { return CsrFieldType::RWR; @@ -329,39 +327,39 @@ fields: location: 47-40 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 45* + *PMP configuration for entry 45* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 47 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 46:45 ! _Reserved_ Writes shall be ignored. - h! A ! 44:43 - a! Address matching mode. One of: + h! L ! 47 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 46:45 ! _Reserved_ Writes shall be ignored. + h! A ! 44:43 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 42 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 41 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 40 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 42 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 41 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 40 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 45) { return CsrFieldType::RWR; @@ -392,39 +390,39 @@ fields: location: 55-48 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 46* + *PMP configuration for entry 46* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 55 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 54:53 ! _Reserved_ Writes shall be ignored. - h! A ! 52:51 - a! Address matching mode. One of: + h! L ! 55 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 54:53 ! _Reserved_ Writes shall be ignored. + h! A ! 52:51 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 50 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 49 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 48 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 50 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 49 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 48 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 46) { return CsrFieldType::RWR; @@ -455,39 +453,39 @@ fields: location: 63-56 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 47* + *PMP configuration for entry 47* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 63 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 62:61 ! _Reserved_ Writes shall be ignored. - h! A ! 60:59 - a! Address matching mode. One of: + h! L ! 63 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 62:61 ! _Reserved_ Writes shall be ignored. + h! A ! 60:59 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 58 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 57 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 56 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 58 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 57 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 56 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 47) { return CsrFieldType::RWR; diff --git a/arch/csr/I/pmpcfg11.yaml b/arch/csr/I/pmpcfg11.yaml index 7ba8d05b68..de85b308ad 100644 --- a/arch/csr/I/pmpcfg11.yaml +++ b/arch/csr/I/pmpcfg11.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpcfgN.layout - - $schema: csr_schema.json# kind: csr name: pmpcfg11 @@ -18,39 +16,39 @@ fields: pmp44cfg: location: 7-0 description: | - *PMP configuration for entry 44* + *PMP configuration for entry 44* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 6:5 ! _Reserved_ Writes shall be ignored. - h! A ! 4:3 - a! Address matching mode. One of: + h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 6:5 ! _Reserved_ Writes shall be ignored. + h! A ! 4:3 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 44) { return CsrFieldType::RWR; @@ -80,39 +78,39 @@ fields: pmp45cfg: location: 15-8 description: | - *PMP configuration for entry 45* + *PMP configuration for entry 45* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 14:13 ! _Reserved_ Writes shall be ignored. - h! A ! 12:11 - a! Address matching mode. One of: + h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 14:13 ! _Reserved_ Writes shall be ignored. + h! A ! 12:11 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 45) { return CsrFieldType::RWR; @@ -142,39 +140,39 @@ fields: pmp46cfg: location: 23-16 description: | - *PMP configuration for entry 46* + *PMP configuration for entry 46* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 22:21 ! _Reserved_ Writes shall be ignored. - h! A ! 20:19 - a! Address matching mode. One of: + h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 22:21 ! _Reserved_ Writes shall be ignored. + h! A ! 20:19 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 46) { return CsrFieldType::RWR; @@ -204,39 +202,39 @@ fields: pmp47cfg: location: 31-24 description: | - *PMP configuration for entry 47* + *PMP configuration for entry 47* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 30:29 ! _Reserved_ Writes shall be ignored. - h! A ! 28:27 - a! Address matching mode. One of: + h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 30:29 ! _Reserved_ Writes shall be ignored. + h! A ! 28:27 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 47) { return CsrFieldType::RWR; diff --git a/arch/csr/I/pmpcfg12.yaml b/arch/csr/I/pmpcfg12.yaml index 8897f4db98..959226127c 100644 --- a/arch/csr/I/pmpcfg12.yaml +++ b/arch/csr/I/pmpcfg12.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpcfgN.layout - - $schema: csr_schema.json# kind: csr name: pmpcfg12 @@ -17,39 +15,39 @@ fields: pmp48cfg: location: 7-0 description: | - *PMP configuration for entry 48* + *PMP configuration for entry 48* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 6:5 ! _Reserved_ Writes shall be ignored. - h! A ! 4:3 - a! Address matching mode. One of: + h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 6:5 ! _Reserved_ Writes shall be ignored. + h! A ! 4:3 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 48) { return CsrFieldType::RWR; @@ -79,39 +77,39 @@ fields: pmp49cfg: location: 15-8 description: | - *PMP configuration for entry 49* + *PMP configuration for entry 49* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 14:13 ! _Reserved_ Writes shall be ignored. - h! A ! 12:11 - a! Address matching mode. One of: + h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 14:13 ! _Reserved_ Writes shall be ignored. + h! A ! 12:11 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 49) { return CsrFieldType::RWR; @@ -141,39 +139,39 @@ fields: pmp50cfg: location: 23-16 description: | - *PMP configuration for entry 50* + *PMP configuration for entry 50* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 22:21 ! _Reserved_ Writes shall be ignored. - h! A ! 20:19 - a! Address matching mode. One of: + h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 22:21 ! _Reserved_ Writes shall be ignored. + h! A ! 20:19 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 50) { return CsrFieldType::RWR; @@ -203,39 +201,39 @@ fields: pmp51cfg: location: 31-24 description: | - *PMP configuration for entry 51* + *PMP configuration for entry 51* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 30:29 ! _Reserved_ Writes shall be ignored. - h! A ! 28:27 - a! Address matching mode. One of: + h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 30:29 ! _Reserved_ Writes shall be ignored. + h! A ! 28:27 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 51) { return CsrFieldType::RWR; @@ -266,39 +264,39 @@ fields: location: 39-32 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 52* + *PMP configuration for entry 52* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 39 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 38:37 ! _Reserved_ Writes shall be ignored. - h! A ! 36:35 - a! Address matching mode. One of: + h! L ! 39 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 38:37 ! _Reserved_ Writes shall be ignored. + h! A ! 36:35 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 34 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 33 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 32 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 34 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 33 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 32 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 52) { return CsrFieldType::RWR; @@ -329,39 +327,39 @@ fields: location: 47-40 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 53* + *PMP configuration for entry 53* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 47 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 46:45 ! _Reserved_ Writes shall be ignored. - h! A ! 44:43 - a! Address matching mode. One of: + h! L ! 47 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 46:45 ! _Reserved_ Writes shall be ignored. + h! A ! 44:43 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 42 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 41 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 40 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 42 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 41 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 40 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 53) { return CsrFieldType::RWR; @@ -392,39 +390,39 @@ fields: location: 55-48 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 54* + *PMP configuration for entry 54* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 55 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 54:53 ! _Reserved_ Writes shall be ignored. - h! A ! 52:51 - a! Address matching mode. One of: + h! L ! 55 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 54:53 ! _Reserved_ Writes shall be ignored. + h! A ! 52:51 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 50 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 49 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 48 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 50 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 49 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 48 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 54) { return CsrFieldType::RWR; @@ -455,39 +453,39 @@ fields: location: 63-56 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 55* + *PMP configuration for entry 55* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 63 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 62:61 ! _Reserved_ Writes shall be ignored. - h! A ! 60:59 - a! Address matching mode. One of: + h! L ! 63 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 62:61 ! _Reserved_ Writes shall be ignored. + h! A ! 60:59 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 58 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 57 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 56 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 58 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 57 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 56 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 55) { return CsrFieldType::RWR; diff --git a/arch/csr/I/pmpcfg13.yaml b/arch/csr/I/pmpcfg13.yaml index aa151be422..2d937261f0 100644 --- a/arch/csr/I/pmpcfg13.yaml +++ b/arch/csr/I/pmpcfg13.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpcfgN.layout - - $schema: csr_schema.json# kind: csr name: pmpcfg13 @@ -18,39 +16,39 @@ fields: pmp52cfg: location: 7-0 description: | - *PMP configuration for entry 52* + *PMP configuration for entry 52* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 6:5 ! _Reserved_ Writes shall be ignored. - h! A ! 4:3 - a! Address matching mode. One of: + h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 6:5 ! _Reserved_ Writes shall be ignored. + h! A ! 4:3 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 52) { return CsrFieldType::RWR; @@ -80,39 +78,39 @@ fields: pmp53cfg: location: 15-8 description: | - *PMP configuration for entry 53* + *PMP configuration for entry 53* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 14:13 ! _Reserved_ Writes shall be ignored. - h! A ! 12:11 - a! Address matching mode. One of: + h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 14:13 ! _Reserved_ Writes shall be ignored. + h! A ! 12:11 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 53) { return CsrFieldType::RWR; @@ -142,39 +140,39 @@ fields: pmp54cfg: location: 23-16 description: | - *PMP configuration for entry 54* + *PMP configuration for entry 54* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 22:21 ! _Reserved_ Writes shall be ignored. - h! A ! 20:19 - a! Address matching mode. One of: + h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 22:21 ! _Reserved_ Writes shall be ignored. + h! A ! 20:19 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 54) { return CsrFieldType::RWR; @@ -204,39 +202,39 @@ fields: pmp55cfg: location: 31-24 description: | - *PMP configuration for entry 55* + *PMP configuration for entry 55* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 30:29 ! _Reserved_ Writes shall be ignored. - h! A ! 28:27 - a! Address matching mode. One of: + h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 30:29 ! _Reserved_ Writes shall be ignored. + h! A ! 28:27 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 55) { return CsrFieldType::RWR; diff --git a/arch/csr/I/pmpcfg14.yaml b/arch/csr/I/pmpcfg14.yaml index e5c4744d46..e3e6bb44c5 100644 --- a/arch/csr/I/pmpcfg14.yaml +++ b/arch/csr/I/pmpcfg14.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpcfgN.layout - - $schema: csr_schema.json# kind: csr name: pmpcfg14 @@ -17,39 +15,39 @@ fields: pmp56cfg: location: 7-0 description: | - *PMP configuration for entry 56* + *PMP configuration for entry 56* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 6:5 ! _Reserved_ Writes shall be ignored. - h! A ! 4:3 - a! Address matching mode. One of: + h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 6:5 ! _Reserved_ Writes shall be ignored. + h! A ! 4:3 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 56) { return CsrFieldType::RWR; @@ -79,39 +77,39 @@ fields: pmp57cfg: location: 15-8 description: | - *PMP configuration for entry 57* + *PMP configuration for entry 57* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 14:13 ! _Reserved_ Writes shall be ignored. - h! A ! 12:11 - a! Address matching mode. One of: + h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 14:13 ! _Reserved_ Writes shall be ignored. + h! A ! 12:11 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 57) { return CsrFieldType::RWR; @@ -141,39 +139,39 @@ fields: pmp58cfg: location: 23-16 description: | - *PMP configuration for entry 58* + *PMP configuration for entry 58* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 22:21 ! _Reserved_ Writes shall be ignored. - h! A ! 20:19 - a! Address matching mode. One of: + h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 22:21 ! _Reserved_ Writes shall be ignored. + h! A ! 20:19 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 58) { return CsrFieldType::RWR; @@ -203,39 +201,39 @@ fields: pmp59cfg: location: 31-24 description: | - *PMP configuration for entry 59* + *PMP configuration for entry 59* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 30:29 ! _Reserved_ Writes shall be ignored. - h! A ! 28:27 - a! Address matching mode. One of: + h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 30:29 ! _Reserved_ Writes shall be ignored. + h! A ! 28:27 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 59) { return CsrFieldType::RWR; @@ -266,39 +264,39 @@ fields: location: 39-32 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 60* + *PMP configuration for entry 60* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 39 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 38:37 ! _Reserved_ Writes shall be ignored. - h! A ! 36:35 - a! Address matching mode. One of: + h! L ! 39 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 38:37 ! _Reserved_ Writes shall be ignored. + h! A ! 36:35 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 34 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 33 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 32 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 34 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 33 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 32 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 60) { return CsrFieldType::RWR; @@ -329,39 +327,39 @@ fields: location: 47-40 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 61* + *PMP configuration for entry 61* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 47 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 46:45 ! _Reserved_ Writes shall be ignored. - h! A ! 44:43 - a! Address matching mode. One of: + h! L ! 47 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 46:45 ! _Reserved_ Writes shall be ignored. + h! A ! 44:43 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 42 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 41 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 40 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 42 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 41 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 40 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 61) { return CsrFieldType::RWR; @@ -392,39 +390,39 @@ fields: location: 55-48 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 62* + *PMP configuration for entry 62* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 55 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 54:53 ! _Reserved_ Writes shall be ignored. - h! A ! 52:51 - a! Address matching mode. One of: + h! L ! 55 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 54:53 ! _Reserved_ Writes shall be ignored. + h! A ! 52:51 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 50 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 49 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 48 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 50 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 49 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 48 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 62) { return CsrFieldType::RWR; @@ -455,39 +453,39 @@ fields: location: 63-56 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 63* + *PMP configuration for entry 63* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 63 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 62:61 ! _Reserved_ Writes shall be ignored. - h! A ! 60:59 - a! Address matching mode. One of: + h! L ! 63 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 62:61 ! _Reserved_ Writes shall be ignored. + h! A ! 60:59 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 58 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 57 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 56 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 58 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 57 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 56 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 63) { return CsrFieldType::RWR; diff --git a/arch/csr/I/pmpcfg15.yaml b/arch/csr/I/pmpcfg15.yaml index 43454115e7..410c6d15e5 100644 --- a/arch/csr/I/pmpcfg15.yaml +++ b/arch/csr/I/pmpcfg15.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpcfgN.layout - - $schema: csr_schema.json# kind: csr name: pmpcfg15 @@ -18,39 +16,39 @@ fields: pmp60cfg: location: 7-0 description: | - *PMP configuration for entry 60* + *PMP configuration for entry 60* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 6:5 ! _Reserved_ Writes shall be ignored. - h! A ! 4:3 - a! Address matching mode. One of: + h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 6:5 ! _Reserved_ Writes shall be ignored. + h! A ! 4:3 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 60) { return CsrFieldType::RWR; @@ -80,39 +78,39 @@ fields: pmp61cfg: location: 15-8 description: | - *PMP configuration for entry 61* + *PMP configuration for entry 61* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 14:13 ! _Reserved_ Writes shall be ignored. - h! A ! 12:11 - a! Address matching mode. One of: + h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 14:13 ! _Reserved_ Writes shall be ignored. + h! A ! 12:11 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 61) { return CsrFieldType::RWR; @@ -142,39 +140,39 @@ fields: pmp62cfg: location: 23-16 description: | - *PMP configuration for entry 62* + *PMP configuration for entry 62* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 22:21 ! _Reserved_ Writes shall be ignored. - h! A ! 20:19 - a! Address matching mode. One of: + h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 22:21 ! _Reserved_ Writes shall be ignored. + h! A ! 20:19 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 62) { return CsrFieldType::RWR; @@ -204,39 +202,39 @@ fields: pmp63cfg: location: 31-24 description: | - *PMP configuration for entry 63* + *PMP configuration for entry 63* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 30:29 ! _Reserved_ Writes shall be ignored. - h! A ! 28:27 - a! Address matching mode. One of: + h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 30:29 ! _Reserved_ Writes shall be ignored. + h! A ! 28:27 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 63) { return CsrFieldType::RWR; diff --git a/arch/csr/I/pmpcfg2.yaml b/arch/csr/I/pmpcfg2.yaml index bad4210e86..c3422f116a 100644 --- a/arch/csr/I/pmpcfg2.yaml +++ b/arch/csr/I/pmpcfg2.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpcfgN.layout - - $schema: csr_schema.json# kind: csr name: pmpcfg2 @@ -17,39 +15,39 @@ fields: pmp8cfg: location: 7-0 description: | - *PMP configuration for entry 8* + *PMP configuration for entry 8* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 6:5 ! _Reserved_ Writes shall be ignored. - h! A ! 4:3 - a! Address matching mode. One of: + h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 6:5 ! _Reserved_ Writes shall be ignored. + h! A ! 4:3 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 8) { return CsrFieldType::RWR; @@ -79,39 +77,39 @@ fields: pmp9cfg: location: 15-8 description: | - *PMP configuration for entry 9* + *PMP configuration for entry 9* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 14:13 ! _Reserved_ Writes shall be ignored. - h! A ! 12:11 - a! Address matching mode. One of: + h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 14:13 ! _Reserved_ Writes shall be ignored. + h! A ! 12:11 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 9) { return CsrFieldType::RWR; @@ -141,39 +139,39 @@ fields: pmp10cfg: location: 23-16 description: | - *PMP configuration for entry 10* + *PMP configuration for entry 10* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 22:21 ! _Reserved_ Writes shall be ignored. - h! A ! 20:19 - a! Address matching mode. One of: + h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 22:21 ! _Reserved_ Writes shall be ignored. + h! A ! 20:19 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 10) { return CsrFieldType::RWR; @@ -203,39 +201,39 @@ fields: pmp11cfg: location: 31-24 description: | - *PMP configuration for entry 11* + *PMP configuration for entry 11* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 30:29 ! _Reserved_ Writes shall be ignored. - h! A ! 28:27 - a! Address matching mode. One of: + h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 30:29 ! _Reserved_ Writes shall be ignored. + h! A ! 28:27 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 11) { return CsrFieldType::RWR; @@ -266,39 +264,39 @@ fields: location: 39-32 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 12* + *PMP configuration for entry 12* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 39 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 38:37 ! _Reserved_ Writes shall be ignored. - h! A ! 36:35 - a! Address matching mode. One of: + h! L ! 39 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 38:37 ! _Reserved_ Writes shall be ignored. + h! A ! 36:35 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 34 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 33 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 32 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 34 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 33 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 32 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 12) { return CsrFieldType::RWR; @@ -329,39 +327,39 @@ fields: location: 47-40 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 13* + *PMP configuration for entry 13* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 47 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 46:45 ! _Reserved_ Writes shall be ignored. - h! A ! 44:43 - a! Address matching mode. One of: + h! L ! 47 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 46:45 ! _Reserved_ Writes shall be ignored. + h! A ! 44:43 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 42 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 41 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 40 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 42 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 41 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 40 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 13) { return CsrFieldType::RWR; @@ -392,39 +390,39 @@ fields: location: 55-48 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 14* + *PMP configuration for entry 14* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 55 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 54:53 ! _Reserved_ Writes shall be ignored. - h! A ! 52:51 - a! Address matching mode. One of: + h! L ! 55 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 54:53 ! _Reserved_ Writes shall be ignored. + h! A ! 52:51 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 50 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 49 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 48 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 50 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 49 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 48 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 14) { return CsrFieldType::RWR; @@ -455,39 +453,39 @@ fields: location: 63-56 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 15* + *PMP configuration for entry 15* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 63 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 62:61 ! _Reserved_ Writes shall be ignored. - h! A ! 60:59 - a! Address matching mode. One of: + h! L ! 63 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 62:61 ! _Reserved_ Writes shall be ignored. + h! A ! 60:59 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 58 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 57 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 56 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 58 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 57 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 56 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 15) { return CsrFieldType::RWR; diff --git a/arch/csr/I/pmpcfg3.yaml b/arch/csr/I/pmpcfg3.yaml index 31f5a48066..d1002e342f 100644 --- a/arch/csr/I/pmpcfg3.yaml +++ b/arch/csr/I/pmpcfg3.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpcfgN.layout - - $schema: csr_schema.json# kind: csr name: pmpcfg3 @@ -18,39 +16,39 @@ fields: pmp12cfg: location: 7-0 description: | - *PMP configuration for entry 12* + *PMP configuration for entry 12* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 6:5 ! _Reserved_ Writes shall be ignored. - h! A ! 4:3 - a! Address matching mode. One of: + h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 6:5 ! _Reserved_ Writes shall be ignored. + h! A ! 4:3 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 12) { return CsrFieldType::RWR; @@ -80,39 +78,39 @@ fields: pmp13cfg: location: 15-8 description: | - *PMP configuration for entry 13* + *PMP configuration for entry 13* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 14:13 ! _Reserved_ Writes shall be ignored. - h! A ! 12:11 - a! Address matching mode. One of: + h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 14:13 ! _Reserved_ Writes shall be ignored. + h! A ! 12:11 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 13) { return CsrFieldType::RWR; @@ -142,39 +140,39 @@ fields: pmp14cfg: location: 23-16 description: | - *PMP configuration for entry 14* + *PMP configuration for entry 14* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 22:21 ! _Reserved_ Writes shall be ignored. - h! A ! 20:19 - a! Address matching mode. One of: + h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 22:21 ! _Reserved_ Writes shall be ignored. + h! A ! 20:19 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 14) { return CsrFieldType::RWR; @@ -204,39 +202,39 @@ fields: pmp15cfg: location: 31-24 description: | - *PMP configuration for entry 15* + *PMP configuration for entry 15* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 30:29 ! _Reserved_ Writes shall be ignored. - h! A ! 28:27 - a! Address matching mode. One of: + h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 30:29 ! _Reserved_ Writes shall be ignored. + h! A ! 28:27 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 15) { return CsrFieldType::RWR; diff --git a/arch/csr/I/pmpcfg4.yaml b/arch/csr/I/pmpcfg4.yaml index d55346cc51..4b1b6b335d 100644 --- a/arch/csr/I/pmpcfg4.yaml +++ b/arch/csr/I/pmpcfg4.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpcfgN.layout - - $schema: csr_schema.json# kind: csr name: pmpcfg4 @@ -17,39 +15,39 @@ fields: pmp16cfg: location: 7-0 description: | - *PMP configuration for entry 16* + *PMP configuration for entry 16* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 6:5 ! _Reserved_ Writes shall be ignored. - h! A ! 4:3 - a! Address matching mode. One of: + h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 6:5 ! _Reserved_ Writes shall be ignored. + h! A ! 4:3 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 16) { return CsrFieldType::RWR; @@ -79,39 +77,39 @@ fields: pmp17cfg: location: 15-8 description: | - *PMP configuration for entry 17* + *PMP configuration for entry 17* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 14:13 ! _Reserved_ Writes shall be ignored. - h! A ! 12:11 - a! Address matching mode. One of: + h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 14:13 ! _Reserved_ Writes shall be ignored. + h! A ! 12:11 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 17) { return CsrFieldType::RWR; @@ -141,39 +139,39 @@ fields: pmp18cfg: location: 23-16 description: | - *PMP configuration for entry 18* + *PMP configuration for entry 18* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 22:21 ! _Reserved_ Writes shall be ignored. - h! A ! 20:19 - a! Address matching mode. One of: + h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 22:21 ! _Reserved_ Writes shall be ignored. + h! A ! 20:19 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 18) { return CsrFieldType::RWR; @@ -203,39 +201,39 @@ fields: pmp19cfg: location: 31-24 description: | - *PMP configuration for entry 19* + *PMP configuration for entry 19* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 30:29 ! _Reserved_ Writes shall be ignored. - h! A ! 28:27 - a! Address matching mode. One of: + h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 30:29 ! _Reserved_ Writes shall be ignored. + h! A ! 28:27 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 19) { return CsrFieldType::RWR; @@ -266,39 +264,39 @@ fields: location: 39-32 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 20* + *PMP configuration for entry 20* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 39 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 38:37 ! _Reserved_ Writes shall be ignored. - h! A ! 36:35 - a! Address matching mode. One of: + h! L ! 39 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 38:37 ! _Reserved_ Writes shall be ignored. + h! A ! 36:35 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 34 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 33 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 32 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 34 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 33 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 32 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 20) { return CsrFieldType::RWR; @@ -329,39 +327,39 @@ fields: location: 47-40 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 21* + *PMP configuration for entry 21* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 47 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 46:45 ! _Reserved_ Writes shall be ignored. - h! A ! 44:43 - a! Address matching mode. One of: + h! L ! 47 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 46:45 ! _Reserved_ Writes shall be ignored. + h! A ! 44:43 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 42 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 41 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 40 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 42 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 41 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 40 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 21) { return CsrFieldType::RWR; @@ -392,39 +390,39 @@ fields: location: 55-48 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 22* + *PMP configuration for entry 22* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 55 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 54:53 ! _Reserved_ Writes shall be ignored. - h! A ! 52:51 - a! Address matching mode. One of: + h! L ! 55 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 54:53 ! _Reserved_ Writes shall be ignored. + h! A ! 52:51 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 50 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 49 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 48 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 50 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 49 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 48 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 22) { return CsrFieldType::RWR; @@ -455,39 +453,39 @@ fields: location: 63-56 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 23* + *PMP configuration for entry 23* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 63 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 62:61 ! _Reserved_ Writes shall be ignored. - h! A ! 60:59 - a! Address matching mode. One of: + h! L ! 63 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 62:61 ! _Reserved_ Writes shall be ignored. + h! A ! 60:59 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 58 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 57 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 56 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 58 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 57 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 56 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 23) { return CsrFieldType::RWR; diff --git a/arch/csr/I/pmpcfg5.yaml b/arch/csr/I/pmpcfg5.yaml index 3b9e2477ca..afc26fccc5 100644 --- a/arch/csr/I/pmpcfg5.yaml +++ b/arch/csr/I/pmpcfg5.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpcfgN.layout - - $schema: csr_schema.json# kind: csr name: pmpcfg5 @@ -18,39 +16,39 @@ fields: pmp20cfg: location: 7-0 description: | - *PMP configuration for entry 20* + *PMP configuration for entry 20* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 6:5 ! _Reserved_ Writes shall be ignored. - h! A ! 4:3 - a! Address matching mode. One of: + h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 6:5 ! _Reserved_ Writes shall be ignored. + h! A ! 4:3 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 20) { return CsrFieldType::RWR; @@ -80,39 +78,39 @@ fields: pmp21cfg: location: 15-8 description: | - *PMP configuration for entry 21* + *PMP configuration for entry 21* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 14:13 ! _Reserved_ Writes shall be ignored. - h! A ! 12:11 - a! Address matching mode. One of: + h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 14:13 ! _Reserved_ Writes shall be ignored. + h! A ! 12:11 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 21) { return CsrFieldType::RWR; @@ -142,39 +140,39 @@ fields: pmp22cfg: location: 23-16 description: | - *PMP configuration for entry 22* + *PMP configuration for entry 22* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 22:21 ! _Reserved_ Writes shall be ignored. - h! A ! 20:19 - a! Address matching mode. One of: + h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 22:21 ! _Reserved_ Writes shall be ignored. + h! A ! 20:19 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 22) { return CsrFieldType::RWR; @@ -204,39 +202,39 @@ fields: pmp23cfg: location: 31-24 description: | - *PMP configuration for entry 23* + *PMP configuration for entry 23* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 30:29 ! _Reserved_ Writes shall be ignored. - h! A ! 28:27 - a! Address matching mode. One of: + h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 30:29 ! _Reserved_ Writes shall be ignored. + h! A ! 28:27 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 23) { return CsrFieldType::RWR; diff --git a/arch/csr/I/pmpcfg6.yaml b/arch/csr/I/pmpcfg6.yaml index a7ab336b66..609f67617f 100644 --- a/arch/csr/I/pmpcfg6.yaml +++ b/arch/csr/I/pmpcfg6.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpcfgN.layout - - $schema: csr_schema.json# kind: csr name: pmpcfg6 @@ -17,39 +15,39 @@ fields: pmp24cfg: location: 7-0 description: | - *PMP configuration for entry 24* + *PMP configuration for entry 24* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 6:5 ! _Reserved_ Writes shall be ignored. - h! A ! 4:3 - a! Address matching mode. One of: + h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 6:5 ! _Reserved_ Writes shall be ignored. + h! A ! 4:3 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 24) { return CsrFieldType::RWR; @@ -79,39 +77,39 @@ fields: pmp25cfg: location: 15-8 description: | - *PMP configuration for entry 25* + *PMP configuration for entry 25* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 14:13 ! _Reserved_ Writes shall be ignored. - h! A ! 12:11 - a! Address matching mode. One of: + h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 14:13 ! _Reserved_ Writes shall be ignored. + h! A ! 12:11 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 25) { return CsrFieldType::RWR; @@ -141,39 +139,39 @@ fields: pmp26cfg: location: 23-16 description: | - *PMP configuration for entry 26* + *PMP configuration for entry 26* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 22:21 ! _Reserved_ Writes shall be ignored. - h! A ! 20:19 - a! Address matching mode. One of: + h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 22:21 ! _Reserved_ Writes shall be ignored. + h! A ! 20:19 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 26) { return CsrFieldType::RWR; @@ -203,39 +201,39 @@ fields: pmp27cfg: location: 31-24 description: | - *PMP configuration for entry 27* + *PMP configuration for entry 27* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 30:29 ! _Reserved_ Writes shall be ignored. - h! A ! 28:27 - a! Address matching mode. One of: + h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 30:29 ! _Reserved_ Writes shall be ignored. + h! A ! 28:27 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 27) { return CsrFieldType::RWR; @@ -266,39 +264,39 @@ fields: location: 39-32 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 28* + *PMP configuration for entry 28* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 39 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 38:37 ! _Reserved_ Writes shall be ignored. - h! A ! 36:35 - a! Address matching mode. One of: + h! L ! 39 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 38:37 ! _Reserved_ Writes shall be ignored. + h! A ! 36:35 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 34 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 33 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 32 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 34 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 33 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 32 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 28) { return CsrFieldType::RWR; @@ -329,39 +327,39 @@ fields: location: 47-40 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 29* + *PMP configuration for entry 29* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 47 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 46:45 ! _Reserved_ Writes shall be ignored. - h! A ! 44:43 - a! Address matching mode. One of: + h! L ! 47 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 46:45 ! _Reserved_ Writes shall be ignored. + h! A ! 44:43 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 42 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 41 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 40 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 42 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 41 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 40 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 29) { return CsrFieldType::RWR; @@ -392,39 +390,39 @@ fields: location: 55-48 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 30* + *PMP configuration for entry 30* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 55 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 54:53 ! _Reserved_ Writes shall be ignored. - h! A ! 52:51 - a! Address matching mode. One of: + h! L ! 55 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 54:53 ! _Reserved_ Writes shall be ignored. + h! A ! 52:51 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 50 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 49 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 48 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 50 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 49 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 48 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 30) { return CsrFieldType::RWR; @@ -455,39 +453,39 @@ fields: location: 63-56 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 31* + *PMP configuration for entry 31* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 63 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 62:61 ! _Reserved_ Writes shall be ignored. - h! A ! 60:59 - a! Address matching mode. One of: + h! L ! 63 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 62:61 ! _Reserved_ Writes shall be ignored. + h! A ! 60:59 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 58 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 57 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 56 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 58 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 57 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 56 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 31) { return CsrFieldType::RWR; diff --git a/arch/csr/I/pmpcfg7.yaml b/arch/csr/I/pmpcfg7.yaml index bebd1871ec..d56da433ed 100644 --- a/arch/csr/I/pmpcfg7.yaml +++ b/arch/csr/I/pmpcfg7.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpcfgN.layout - - $schema: csr_schema.json# kind: csr name: pmpcfg7 @@ -18,39 +16,39 @@ fields: pmp28cfg: location: 7-0 description: | - *PMP configuration for entry 28* + *PMP configuration for entry 28* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 6:5 ! _Reserved_ Writes shall be ignored. - h! A ! 4:3 - a! Address matching mode. One of: + h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 6:5 ! _Reserved_ Writes shall be ignored. + h! A ! 4:3 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 28) { return CsrFieldType::RWR; @@ -80,39 +78,39 @@ fields: pmp29cfg: location: 15-8 description: | - *PMP configuration for entry 29* + *PMP configuration for entry 29* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 14:13 ! _Reserved_ Writes shall be ignored. - h! A ! 12:11 - a! Address matching mode. One of: + h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 14:13 ! _Reserved_ Writes shall be ignored. + h! A ! 12:11 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 29) { return CsrFieldType::RWR; @@ -142,39 +140,39 @@ fields: pmp30cfg: location: 23-16 description: | - *PMP configuration for entry 30* + *PMP configuration for entry 30* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 22:21 ! _Reserved_ Writes shall be ignored. - h! A ! 20:19 - a! Address matching mode. One of: + h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 22:21 ! _Reserved_ Writes shall be ignored. + h! A ! 20:19 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 30) { return CsrFieldType::RWR; @@ -204,39 +202,39 @@ fields: pmp31cfg: location: 31-24 description: | - *PMP configuration for entry 31* + *PMP configuration for entry 31* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 30:29 ! _Reserved_ Writes shall be ignored. - h! A ! 28:27 - a! Address matching mode. One of: + h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 30:29 ! _Reserved_ Writes shall be ignored. + h! A ! 28:27 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 31) { return CsrFieldType::RWR; diff --git a/arch/csr/I/pmpcfg8.yaml b/arch/csr/I/pmpcfg8.yaml index fa3b0fbd45..de8650e6ca 100644 --- a/arch/csr/I/pmpcfg8.yaml +++ b/arch/csr/I/pmpcfg8.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpcfgN.layout - - $schema: csr_schema.json# kind: csr name: pmpcfg8 @@ -17,39 +15,39 @@ fields: pmp32cfg: location: 7-0 description: | - *PMP configuration for entry 32* + *PMP configuration for entry 32* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 6:5 ! _Reserved_ Writes shall be ignored. - h! A ! 4:3 - a! Address matching mode. One of: + h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 6:5 ! _Reserved_ Writes shall be ignored. + h! A ! 4:3 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 32) { return CsrFieldType::RWR; @@ -79,39 +77,39 @@ fields: pmp33cfg: location: 15-8 description: | - *PMP configuration for entry 33* + *PMP configuration for entry 33* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 14:13 ! _Reserved_ Writes shall be ignored. - h! A ! 12:11 - a! Address matching mode. One of: + h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 14:13 ! _Reserved_ Writes shall be ignored. + h! A ! 12:11 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 33) { return CsrFieldType::RWR; @@ -141,39 +139,39 @@ fields: pmp34cfg: location: 23-16 description: | - *PMP configuration for entry 34* + *PMP configuration for entry 34* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 22:21 ! _Reserved_ Writes shall be ignored. - h! A ! 20:19 - a! Address matching mode. One of: + h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 22:21 ! _Reserved_ Writes shall be ignored. + h! A ! 20:19 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 34) { return CsrFieldType::RWR; @@ -203,39 +201,39 @@ fields: pmp35cfg: location: 31-24 description: | - *PMP configuration for entry 35* + *PMP configuration for entry 35* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 30:29 ! _Reserved_ Writes shall be ignored. - h! A ! 28:27 - a! Address matching mode. One of: + h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 30:29 ! _Reserved_ Writes shall be ignored. + h! A ! 28:27 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 35) { return CsrFieldType::RWR; @@ -266,39 +264,39 @@ fields: location: 39-32 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 36* + *PMP configuration for entry 36* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 39 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 38:37 ! _Reserved_ Writes shall be ignored. - h! A ! 36:35 - a! Address matching mode. One of: + h! L ! 39 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 38:37 ! _Reserved_ Writes shall be ignored. + h! A ! 36:35 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 34 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 33 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 32 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 34 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 33 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 32 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 36) { return CsrFieldType::RWR; @@ -329,39 +327,39 @@ fields: location: 47-40 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 37* + *PMP configuration for entry 37* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 47 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 46:45 ! _Reserved_ Writes shall be ignored. - h! A ! 44:43 - a! Address matching mode. One of: + h! L ! 47 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 46:45 ! _Reserved_ Writes shall be ignored. + h! A ! 44:43 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 42 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 41 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 40 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 42 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 41 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 40 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 37) { return CsrFieldType::RWR; @@ -392,39 +390,39 @@ fields: location: 55-48 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 38* + *PMP configuration for entry 38* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 55 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 54:53 ! _Reserved_ Writes shall be ignored. - h! A ! 52:51 - a! Address matching mode. One of: + h! L ! 55 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 54:53 ! _Reserved_ Writes shall be ignored. + h! A ! 52:51 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 50 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 49 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 48 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 50 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 49 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 48 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 38) { return CsrFieldType::RWR; @@ -455,39 +453,39 @@ fields: location: 63-56 base: 64 # upper half doesn't exist in RV32 description: | - *PMP configuration for entry 39* + *PMP configuration for entry 39* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 63 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 62:61 ! _Reserved_ Writes shall be ignored. - h! A ! 60:59 - a! Address matching mode. One of: + h! L ! 63 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 62:61 ! _Reserved_ Writes shall be ignored. + h! A ! 60:59 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 58 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 57 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 56 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 58 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 57 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 56 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 39) { return CsrFieldType::RWR; diff --git a/arch/csr/I/pmpcfg9.yaml b/arch/csr/I/pmpcfg9.yaml index 6fccacb66c..c5878baa08 100644 --- a/arch/csr/I/pmpcfg9.yaml +++ b/arch/csr/I/pmpcfg9.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/I/pmpcfgN.layout - - $schema: csr_schema.json# kind: csr name: pmpcfg9 @@ -18,39 +16,39 @@ fields: pmp36cfg: location: 7-0 description: | - *PMP configuration for entry 36* + *PMP configuration for entry 36* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 6:5 ! _Reserved_ Writes shall be ignored. - h! A ! 4:3 - a! Address matching mode. One of: + h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 6:5 ! _Reserved_ Writes shall be ignored. + h! A ! 4:3 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 2 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 0 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 36) { return CsrFieldType::RWR; @@ -80,39 +78,39 @@ fields: pmp37cfg: location: 15-8 description: | - *PMP configuration for entry 37* + *PMP configuration for entry 37* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 14:13 ! _Reserved_ Writes shall be ignored. - h! A ! 12:11 - a! Address matching mode. One of: + h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 14:13 ! _Reserved_ Writes shall be ignored. + h! A ! 12:11 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 10 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 8 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 37) { return CsrFieldType::RWR; @@ -142,39 +140,39 @@ fields: pmp38cfg: location: 23-16 description: | - *PMP configuration for entry 38* + *PMP configuration for entry 38* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 22:21 ! _Reserved_ Writes shall be ignored. - h! A ! 20:19 - a! Address matching mode. One of: + h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 22:21 ! _Reserved_ Writes shall be ignored. + h! A ! 20:19 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 18 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 16 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 38) { return CsrFieldType::RWR; @@ -204,39 +202,39 @@ fields: pmp39cfg: location: 31-24 description: | - *PMP configuration for entry 39* + *PMP configuration for entry 39* - The bits are as follows: + The bits are as follows: - [separator="!",%autowidth] - !=== - ! Name ! Location ! Description + [separator="!",%autowidth] + !=== + ! Name ! Location ! Description - h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. - h! - ! 30:29 ! _Reserved_ Writes shall be ignored. - h! A ! 28:27 - a! Address matching mode. One of: + h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry. + h! - ! 30:29 ! _Reserved_ Writes shall be ignored. + h! A ! 28:27 + a! Address matching mode. One of: - [when="PMP_GRANULARITY < 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NA4* (2) - Naturally aligned four-byte region - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY < 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NA4* (2) - Naturally aligned four-byte region + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - * *OFF* (0) - Null region (disabled) - * *TOR* (1) - Top of range - * *NAPOT* (3) - Natrually aligned power of two + [when="PMP_GRANULARITY >= 2"] + * *OFF* (0) - Null region (disabled) + * *TOR* (1) - Top of range + * *NAPOT* (3) - Natrually aligned power of two - [when="PMP_GRANULARITY >= 2"] - Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). + [when="PMP_GRANULARITY >= 2"] + Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes). - h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. - h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. - h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. - !=== + h! X ! 26 ! When clear, instruction fetchs cause an `Access Fault` for the matching region and privilege mode. + h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode. + h! R ! 24 ! When clear, loads cause an `Access Fault` for the matching region and privilege mode. + !=== - The combination of R = 0, W = 1 is reserved. + The combination of R = 0, W = 1 is reserved. type(): | if (NUM_PMP_ENTRIES > 39) { return CsrFieldType::RWR; diff --git a/arch/csr/S/scounteren.yaml b/arch/csr/S/scounteren.yaml index f0055805a9..395ec77d8d 100644 --- a/arch/csr/S/scounteren.yaml +++ b/arch/csr/S/scounteren.yaml @@ -2,7 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/S/scounteren.layout - $schema: csr_schema.json# kind: csr name: scounteren diff --git a/arch/csr/Zicntr/mcountinhibit.yaml b/arch/csr/Zicntr/mcountinhibit.yaml index a8d3fe8230..685b453579 100644 --- a/arch/csr/Zicntr/mcountinhibit.yaml +++ b/arch/csr/Zicntr/mcountinhibit.yaml @@ -2,7 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zicntr/mcountinhibit.layout - $schema: csr_schema.json# kind: csr name: mcountinhibit @@ -44,8 +43,8 @@ description: | definedBy: anyOf: - - name: Sm - - name: Smhpm + - name: Sm + - name: Smhpm fields: CY: location: 0 diff --git a/arch/csr/Zihpm/hpmcounter10.yaml b/arch/csr/Zihpm/hpmcounter10.yaml index 73b4b9c3cb..509504b052 100644 --- a/arch/csr/Zihpm/hpmcounter10.yaml +++ b/arch/csr/Zihpm/hpmcounter10.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter10 diff --git a/arch/csr/Zihpm/hpmcounter10h.yaml b/arch/csr/Zihpm/hpmcounter10h.yaml index 682f95116c..86c92aae09 100644 --- a/arch/csr/Zihpm/hpmcounter10h.yaml +++ b/arch/csr/Zihpm/hpmcounter10h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter10h diff --git a/arch/csr/Zihpm/hpmcounter11.yaml b/arch/csr/Zihpm/hpmcounter11.yaml index 0cd3adbd9e..81e45feb52 100644 --- a/arch/csr/Zihpm/hpmcounter11.yaml +++ b/arch/csr/Zihpm/hpmcounter11.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter11 diff --git a/arch/csr/Zihpm/hpmcounter11h.yaml b/arch/csr/Zihpm/hpmcounter11h.yaml index d710fcfb16..2d0954a5e2 100644 --- a/arch/csr/Zihpm/hpmcounter11h.yaml +++ b/arch/csr/Zihpm/hpmcounter11h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter11h diff --git a/arch/csr/Zihpm/hpmcounter12.yaml b/arch/csr/Zihpm/hpmcounter12.yaml index 940be2a1a5..0960f7578e 100644 --- a/arch/csr/Zihpm/hpmcounter12.yaml +++ b/arch/csr/Zihpm/hpmcounter12.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter12 diff --git a/arch/csr/Zihpm/hpmcounter12h.yaml b/arch/csr/Zihpm/hpmcounter12h.yaml index da1b608476..696b277901 100644 --- a/arch/csr/Zihpm/hpmcounter12h.yaml +++ b/arch/csr/Zihpm/hpmcounter12h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter12h diff --git a/arch/csr/Zihpm/hpmcounter13.yaml b/arch/csr/Zihpm/hpmcounter13.yaml index 251679470a..24e9fc06fe 100644 --- a/arch/csr/Zihpm/hpmcounter13.yaml +++ b/arch/csr/Zihpm/hpmcounter13.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter13 diff --git a/arch/csr/Zihpm/hpmcounter13h.yaml b/arch/csr/Zihpm/hpmcounter13h.yaml index 4f7ad9c11c..7eac1cb8be 100644 --- a/arch/csr/Zihpm/hpmcounter13h.yaml +++ b/arch/csr/Zihpm/hpmcounter13h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter13h diff --git a/arch/csr/Zihpm/hpmcounter14.yaml b/arch/csr/Zihpm/hpmcounter14.yaml index c65d0acd89..8708dd5a6b 100644 --- a/arch/csr/Zihpm/hpmcounter14.yaml +++ b/arch/csr/Zihpm/hpmcounter14.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter14 diff --git a/arch/csr/Zihpm/hpmcounter14h.yaml b/arch/csr/Zihpm/hpmcounter14h.yaml index f5da646657..f34cb427a6 100644 --- a/arch/csr/Zihpm/hpmcounter14h.yaml +++ b/arch/csr/Zihpm/hpmcounter14h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter14h diff --git a/arch/csr/Zihpm/hpmcounter15.yaml b/arch/csr/Zihpm/hpmcounter15.yaml index 0a1eeda232..007f40d8c7 100644 --- a/arch/csr/Zihpm/hpmcounter15.yaml +++ b/arch/csr/Zihpm/hpmcounter15.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter15 diff --git a/arch/csr/Zihpm/hpmcounter15h.yaml b/arch/csr/Zihpm/hpmcounter15h.yaml index 0349cceaa2..3212ae429a 100644 --- a/arch/csr/Zihpm/hpmcounter15h.yaml +++ b/arch/csr/Zihpm/hpmcounter15h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter15h diff --git a/arch/csr/Zihpm/hpmcounter16.yaml b/arch/csr/Zihpm/hpmcounter16.yaml index fef98c2a27..016420bf0f 100644 --- a/arch/csr/Zihpm/hpmcounter16.yaml +++ b/arch/csr/Zihpm/hpmcounter16.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter16 diff --git a/arch/csr/Zihpm/hpmcounter16h.yaml b/arch/csr/Zihpm/hpmcounter16h.yaml index 350f8f88db..9ffa840191 100644 --- a/arch/csr/Zihpm/hpmcounter16h.yaml +++ b/arch/csr/Zihpm/hpmcounter16h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter16h diff --git a/arch/csr/Zihpm/hpmcounter17.yaml b/arch/csr/Zihpm/hpmcounter17.yaml index 4326683c3c..15f4889bdb 100644 --- a/arch/csr/Zihpm/hpmcounter17.yaml +++ b/arch/csr/Zihpm/hpmcounter17.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter17 diff --git a/arch/csr/Zihpm/hpmcounter17h.yaml b/arch/csr/Zihpm/hpmcounter17h.yaml index 7d77d8dbad..801ef507f7 100644 --- a/arch/csr/Zihpm/hpmcounter17h.yaml +++ b/arch/csr/Zihpm/hpmcounter17h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter17h diff --git a/arch/csr/Zihpm/hpmcounter18.yaml b/arch/csr/Zihpm/hpmcounter18.yaml index 365ea88897..1b378ac50a 100644 --- a/arch/csr/Zihpm/hpmcounter18.yaml +++ b/arch/csr/Zihpm/hpmcounter18.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter18 diff --git a/arch/csr/Zihpm/hpmcounter18h.yaml b/arch/csr/Zihpm/hpmcounter18h.yaml index 1714bddddb..cd38aad1ba 100644 --- a/arch/csr/Zihpm/hpmcounter18h.yaml +++ b/arch/csr/Zihpm/hpmcounter18h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter18h diff --git a/arch/csr/Zihpm/hpmcounter19.yaml b/arch/csr/Zihpm/hpmcounter19.yaml index abeb3c0ae9..f0a27a7a43 100644 --- a/arch/csr/Zihpm/hpmcounter19.yaml +++ b/arch/csr/Zihpm/hpmcounter19.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter19 diff --git a/arch/csr/Zihpm/hpmcounter19h.yaml b/arch/csr/Zihpm/hpmcounter19h.yaml index fe8d946773..b408c5a470 100644 --- a/arch/csr/Zihpm/hpmcounter19h.yaml +++ b/arch/csr/Zihpm/hpmcounter19h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter19h diff --git a/arch/csr/Zihpm/hpmcounter20.yaml b/arch/csr/Zihpm/hpmcounter20.yaml index a926406054..60b930bb11 100644 --- a/arch/csr/Zihpm/hpmcounter20.yaml +++ b/arch/csr/Zihpm/hpmcounter20.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter20 diff --git a/arch/csr/Zihpm/hpmcounter20h.yaml b/arch/csr/Zihpm/hpmcounter20h.yaml index db31015b87..e1a78f6113 100644 --- a/arch/csr/Zihpm/hpmcounter20h.yaml +++ b/arch/csr/Zihpm/hpmcounter20h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter20h diff --git a/arch/csr/Zihpm/hpmcounter21.yaml b/arch/csr/Zihpm/hpmcounter21.yaml index 3d8ba93b26..60ad4c6fcd 100644 --- a/arch/csr/Zihpm/hpmcounter21.yaml +++ b/arch/csr/Zihpm/hpmcounter21.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter21 diff --git a/arch/csr/Zihpm/hpmcounter21h.yaml b/arch/csr/Zihpm/hpmcounter21h.yaml index 57db30d76e..2158d10930 100644 --- a/arch/csr/Zihpm/hpmcounter21h.yaml +++ b/arch/csr/Zihpm/hpmcounter21h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter21h diff --git a/arch/csr/Zihpm/hpmcounter22.yaml b/arch/csr/Zihpm/hpmcounter22.yaml index a2db1a4615..2f5b264652 100644 --- a/arch/csr/Zihpm/hpmcounter22.yaml +++ b/arch/csr/Zihpm/hpmcounter22.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter22 diff --git a/arch/csr/Zihpm/hpmcounter22h.yaml b/arch/csr/Zihpm/hpmcounter22h.yaml index c6f5555fc6..f8987c1b86 100644 --- a/arch/csr/Zihpm/hpmcounter22h.yaml +++ b/arch/csr/Zihpm/hpmcounter22h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter22h diff --git a/arch/csr/Zihpm/hpmcounter23.yaml b/arch/csr/Zihpm/hpmcounter23.yaml index e8c4b5ff4b..ec6b89bfa7 100644 --- a/arch/csr/Zihpm/hpmcounter23.yaml +++ b/arch/csr/Zihpm/hpmcounter23.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter23 diff --git a/arch/csr/Zihpm/hpmcounter23h.yaml b/arch/csr/Zihpm/hpmcounter23h.yaml index e6b261d231..c9b572cd51 100644 --- a/arch/csr/Zihpm/hpmcounter23h.yaml +++ b/arch/csr/Zihpm/hpmcounter23h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter23h diff --git a/arch/csr/Zihpm/hpmcounter24.yaml b/arch/csr/Zihpm/hpmcounter24.yaml index 5a214615d7..aec19cb8d0 100644 --- a/arch/csr/Zihpm/hpmcounter24.yaml +++ b/arch/csr/Zihpm/hpmcounter24.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter24 diff --git a/arch/csr/Zihpm/hpmcounter24h.yaml b/arch/csr/Zihpm/hpmcounter24h.yaml index 9602adfb47..6ccbffcf00 100644 --- a/arch/csr/Zihpm/hpmcounter24h.yaml +++ b/arch/csr/Zihpm/hpmcounter24h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter24h diff --git a/arch/csr/Zihpm/hpmcounter25.yaml b/arch/csr/Zihpm/hpmcounter25.yaml index d10352ccd3..577984436f 100644 --- a/arch/csr/Zihpm/hpmcounter25.yaml +++ b/arch/csr/Zihpm/hpmcounter25.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter25 diff --git a/arch/csr/Zihpm/hpmcounter25h.yaml b/arch/csr/Zihpm/hpmcounter25h.yaml index f77f95c9bf..2662d4d51b 100644 --- a/arch/csr/Zihpm/hpmcounter25h.yaml +++ b/arch/csr/Zihpm/hpmcounter25h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter25h diff --git a/arch/csr/Zihpm/hpmcounter26.yaml b/arch/csr/Zihpm/hpmcounter26.yaml index 778d77da55..20b5e5ccc5 100644 --- a/arch/csr/Zihpm/hpmcounter26.yaml +++ b/arch/csr/Zihpm/hpmcounter26.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter26 diff --git a/arch/csr/Zihpm/hpmcounter26h.yaml b/arch/csr/Zihpm/hpmcounter26h.yaml index 3468664027..e9c8b11c48 100644 --- a/arch/csr/Zihpm/hpmcounter26h.yaml +++ b/arch/csr/Zihpm/hpmcounter26h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter26h diff --git a/arch/csr/Zihpm/hpmcounter27.yaml b/arch/csr/Zihpm/hpmcounter27.yaml index 1e3014f54f..52ba19b207 100644 --- a/arch/csr/Zihpm/hpmcounter27.yaml +++ b/arch/csr/Zihpm/hpmcounter27.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter27 diff --git a/arch/csr/Zihpm/hpmcounter27h.yaml b/arch/csr/Zihpm/hpmcounter27h.yaml index bf683b7f9a..5b18c3fc64 100644 --- a/arch/csr/Zihpm/hpmcounter27h.yaml +++ b/arch/csr/Zihpm/hpmcounter27h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter27h diff --git a/arch/csr/Zihpm/hpmcounter28.yaml b/arch/csr/Zihpm/hpmcounter28.yaml index f0359b73c1..220586b963 100644 --- a/arch/csr/Zihpm/hpmcounter28.yaml +++ b/arch/csr/Zihpm/hpmcounter28.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter28 diff --git a/arch/csr/Zihpm/hpmcounter28h.yaml b/arch/csr/Zihpm/hpmcounter28h.yaml index 635ba7b1ef..6aaa60f563 100644 --- a/arch/csr/Zihpm/hpmcounter28h.yaml +++ b/arch/csr/Zihpm/hpmcounter28h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter28h diff --git a/arch/csr/Zihpm/hpmcounter29.yaml b/arch/csr/Zihpm/hpmcounter29.yaml index 479cae0025..f63b3babc8 100644 --- a/arch/csr/Zihpm/hpmcounter29.yaml +++ b/arch/csr/Zihpm/hpmcounter29.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter29 diff --git a/arch/csr/Zihpm/hpmcounter29h.yaml b/arch/csr/Zihpm/hpmcounter29h.yaml index 7c76ca6245..65f583acc1 100644 --- a/arch/csr/Zihpm/hpmcounter29h.yaml +++ b/arch/csr/Zihpm/hpmcounter29h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter29h diff --git a/arch/csr/Zihpm/hpmcounter3.yaml b/arch/csr/Zihpm/hpmcounter3.yaml index 99907b9b81..a41868cae5 100644 --- a/arch/csr/Zihpm/hpmcounter3.yaml +++ b/arch/csr/Zihpm/hpmcounter3.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter3 diff --git a/arch/csr/Zihpm/hpmcounter30.yaml b/arch/csr/Zihpm/hpmcounter30.yaml index 855b1087c2..855006edb8 100644 --- a/arch/csr/Zihpm/hpmcounter30.yaml +++ b/arch/csr/Zihpm/hpmcounter30.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter30 diff --git a/arch/csr/Zihpm/hpmcounter30h.yaml b/arch/csr/Zihpm/hpmcounter30h.yaml index 10e30fa681..8e04748de2 100644 --- a/arch/csr/Zihpm/hpmcounter30h.yaml +++ b/arch/csr/Zihpm/hpmcounter30h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter30h diff --git a/arch/csr/Zihpm/hpmcounter31.yaml b/arch/csr/Zihpm/hpmcounter31.yaml index 64aa6a6643..431dd46790 100644 --- a/arch/csr/Zihpm/hpmcounter31.yaml +++ b/arch/csr/Zihpm/hpmcounter31.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter31 diff --git a/arch/csr/Zihpm/hpmcounter31h.yaml b/arch/csr/Zihpm/hpmcounter31h.yaml index 07bf78fe64..4d1edf7976 100644 --- a/arch/csr/Zihpm/hpmcounter31h.yaml +++ b/arch/csr/Zihpm/hpmcounter31h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter31h diff --git a/arch/csr/Zihpm/hpmcounter3h.yaml b/arch/csr/Zihpm/hpmcounter3h.yaml index ea664cc42c..157cef8459 100644 --- a/arch/csr/Zihpm/hpmcounter3h.yaml +++ b/arch/csr/Zihpm/hpmcounter3h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter3h diff --git a/arch/csr/Zihpm/hpmcounter4.yaml b/arch/csr/Zihpm/hpmcounter4.yaml index 06d2d04cb0..44fc65db97 100644 --- a/arch/csr/Zihpm/hpmcounter4.yaml +++ b/arch/csr/Zihpm/hpmcounter4.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter4 diff --git a/arch/csr/Zihpm/hpmcounter4h.yaml b/arch/csr/Zihpm/hpmcounter4h.yaml index 47951185aa..26902cc18d 100644 --- a/arch/csr/Zihpm/hpmcounter4h.yaml +++ b/arch/csr/Zihpm/hpmcounter4h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter4h diff --git a/arch/csr/Zihpm/hpmcounter5.yaml b/arch/csr/Zihpm/hpmcounter5.yaml index ff0ce06fa8..fd1be13a94 100644 --- a/arch/csr/Zihpm/hpmcounter5.yaml +++ b/arch/csr/Zihpm/hpmcounter5.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter5 diff --git a/arch/csr/Zihpm/hpmcounter5h.yaml b/arch/csr/Zihpm/hpmcounter5h.yaml index 354e4465af..81d40289f1 100644 --- a/arch/csr/Zihpm/hpmcounter5h.yaml +++ b/arch/csr/Zihpm/hpmcounter5h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter5h diff --git a/arch/csr/Zihpm/hpmcounter6.yaml b/arch/csr/Zihpm/hpmcounter6.yaml index dd153ff5ab..8834e0c214 100644 --- a/arch/csr/Zihpm/hpmcounter6.yaml +++ b/arch/csr/Zihpm/hpmcounter6.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter6 diff --git a/arch/csr/Zihpm/hpmcounter6h.yaml b/arch/csr/Zihpm/hpmcounter6h.yaml index 238c4e6288..b60dee03e0 100644 --- a/arch/csr/Zihpm/hpmcounter6h.yaml +++ b/arch/csr/Zihpm/hpmcounter6h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter6h diff --git a/arch/csr/Zihpm/hpmcounter7.yaml b/arch/csr/Zihpm/hpmcounter7.yaml index b350ebbd64..57841b7dde 100644 --- a/arch/csr/Zihpm/hpmcounter7.yaml +++ b/arch/csr/Zihpm/hpmcounter7.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter7 diff --git a/arch/csr/Zihpm/hpmcounter7h.yaml b/arch/csr/Zihpm/hpmcounter7h.yaml index 27b2468c83..6f37af9577 100644 --- a/arch/csr/Zihpm/hpmcounter7h.yaml +++ b/arch/csr/Zihpm/hpmcounter7h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter7h diff --git a/arch/csr/Zihpm/hpmcounter8.yaml b/arch/csr/Zihpm/hpmcounter8.yaml index 7c4a50d312..a99cd0ce8f 100644 --- a/arch/csr/Zihpm/hpmcounter8.yaml +++ b/arch/csr/Zihpm/hpmcounter8.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter8 diff --git a/arch/csr/Zihpm/hpmcounter8h.yaml b/arch/csr/Zihpm/hpmcounter8h.yaml index 5eb7fcf058..83175ce6ea 100644 --- a/arch/csr/Zihpm/hpmcounter8h.yaml +++ b/arch/csr/Zihpm/hpmcounter8h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter8h diff --git a/arch/csr/Zihpm/hpmcounter9.yaml b/arch/csr/Zihpm/hpmcounter9.yaml index 91fbcf184a..126d8ad017 100644 --- a/arch/csr/Zihpm/hpmcounter9.yaml +++ b/arch/csr/Zihpm/hpmcounter9.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter9 diff --git a/arch/csr/Zihpm/hpmcounter9h.yaml b/arch/csr/Zihpm/hpmcounter9h.yaml index 8a9e203c77..100a8c9de1 100644 --- a/arch/csr/Zihpm/hpmcounter9h.yaml +++ b/arch/csr/Zihpm/hpmcounter9h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/hpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: hpmcounter9h diff --git a/arch/csr/Zihpm/mhpmcounter10.yaml b/arch/csr/Zihpm/mhpmcounter10.yaml index abcf005aed..8bbc5e1d9d 100644 --- a/arch/csr/Zihpm/mhpmcounter10.yaml +++ b/arch/csr/Zihpm/mhpmcounter10.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter10 @@ -42,8 +40,8 @@ fields: [when="HPM_COUNTER_EN[10] == false"] Unimplemented performance counter. Must be read-only 0 (access does not cause trap). - type(): 'return (HPM_COUNTER_EN[10]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[10]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[10]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[10]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[10]) { return read_hpm_counter(10); diff --git a/arch/csr/Zihpm/mhpmcounter10h.yaml b/arch/csr/Zihpm/mhpmcounter10h.yaml index d020a06c0f..c17a6fdcef 100644 --- a/arch/csr/Zihpm/mhpmcounter10h.yaml +++ b/arch/csr/Zihpm/mhpmcounter10h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter10h @@ -21,8 +19,8 @@ fields: alias: mhpmcounter.COUNT10[63:32] description: | Upper bits of counter. - type(): 'return (HPM_COUNTER_EN[10]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[10]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[10]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[10]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[10]) { return read_hpm_counter(10)[63:32]; diff --git a/arch/csr/Zihpm/mhpmcounter11.yaml b/arch/csr/Zihpm/mhpmcounter11.yaml index 311fc0cf10..0501702a38 100644 --- a/arch/csr/Zihpm/mhpmcounter11.yaml +++ b/arch/csr/Zihpm/mhpmcounter11.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter11 @@ -42,8 +40,8 @@ fields: [when="HPM_COUNTER_EN[11] == false"] Unimplemented performance counter. Must be read-only 0 (access does not cause trap). - type(): 'return (HPM_COUNTER_EN[11]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[11]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[11]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[11]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[11]) { return read_hpm_counter(11); diff --git a/arch/csr/Zihpm/mhpmcounter11h.yaml b/arch/csr/Zihpm/mhpmcounter11h.yaml index 51e1157b1f..8514ff4dc9 100644 --- a/arch/csr/Zihpm/mhpmcounter11h.yaml +++ b/arch/csr/Zihpm/mhpmcounter11h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter11h @@ -21,8 +19,8 @@ fields: alias: mhpmcounter.COUNT11[63:32] description: | Upper bits of counter. - type(): 'return (HPM_COUNTER_EN[11]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[11]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[11]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[11]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[11]) { return read_hpm_counter(11)[63:32]; diff --git a/arch/csr/Zihpm/mhpmcounter12.yaml b/arch/csr/Zihpm/mhpmcounter12.yaml index fb1f3e895a..f0aceebd18 100644 --- a/arch/csr/Zihpm/mhpmcounter12.yaml +++ b/arch/csr/Zihpm/mhpmcounter12.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter12 @@ -42,8 +40,8 @@ fields: [when="HPM_COUNTER_EN[12] == false"] Unimplemented performance counter. Must be read-only 0 (access does not cause trap). - type(): 'return (HPM_COUNTER_EN[12]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[12]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[12]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[12]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[12]) { return read_hpm_counter(12); diff --git a/arch/csr/Zihpm/mhpmcounter12h.yaml b/arch/csr/Zihpm/mhpmcounter12h.yaml index 552478c7b9..2f648514d1 100644 --- a/arch/csr/Zihpm/mhpmcounter12h.yaml +++ b/arch/csr/Zihpm/mhpmcounter12h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter12h @@ -21,8 +19,8 @@ fields: alias: mhpmcounter.COUNT12[63:32] description: | Upper bits of counter. - type(): 'return (HPM_COUNTER_EN[12]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[12]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[12]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[12]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[12]) { return read_hpm_counter(12)[63:32]; diff --git a/arch/csr/Zihpm/mhpmcounter13.yaml b/arch/csr/Zihpm/mhpmcounter13.yaml index 5ac7000070..10fc117dfd 100644 --- a/arch/csr/Zihpm/mhpmcounter13.yaml +++ b/arch/csr/Zihpm/mhpmcounter13.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter13 @@ -42,8 +40,8 @@ fields: [when="HPM_COUNTER_EN[13] == false"] Unimplemented performance counter. Must be read-only 0 (access does not cause trap). - type(): 'return (HPM_COUNTER_EN[13]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[13]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[13]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[13]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[13]) { return read_hpm_counter(13); diff --git a/arch/csr/Zihpm/mhpmcounter13h.yaml b/arch/csr/Zihpm/mhpmcounter13h.yaml index de931ede39..57b60ca1cd 100644 --- a/arch/csr/Zihpm/mhpmcounter13h.yaml +++ b/arch/csr/Zihpm/mhpmcounter13h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter13h @@ -21,8 +19,8 @@ fields: alias: mhpmcounter.COUNT13[63:32] description: | Upper bits of counter. - type(): 'return (HPM_COUNTER_EN[13]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[13]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[13]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[13]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[13]) { return read_hpm_counter(13)[63:32]; diff --git a/arch/csr/Zihpm/mhpmcounter14.yaml b/arch/csr/Zihpm/mhpmcounter14.yaml index f9da216b03..2285c2cca4 100644 --- a/arch/csr/Zihpm/mhpmcounter14.yaml +++ b/arch/csr/Zihpm/mhpmcounter14.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter14 @@ -42,8 +40,8 @@ fields: [when="HPM_COUNTER_EN[14] == false"] Unimplemented performance counter. Must be read-only 0 (access does not cause trap). - type(): 'return (HPM_COUNTER_EN[14]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[14]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[14]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[14]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[14]) { return read_hpm_counter(14); diff --git a/arch/csr/Zihpm/mhpmcounter14h.yaml b/arch/csr/Zihpm/mhpmcounter14h.yaml index fad4f5d6ed..63791d24f9 100644 --- a/arch/csr/Zihpm/mhpmcounter14h.yaml +++ b/arch/csr/Zihpm/mhpmcounter14h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter14h @@ -21,8 +19,8 @@ fields: alias: mhpmcounter.COUNT14[63:32] description: | Upper bits of counter. - type(): 'return (HPM_COUNTER_EN[14]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[14]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[14]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[14]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[14]) { return read_hpm_counter(14)[63:32]; diff --git a/arch/csr/Zihpm/mhpmcounter15.yaml b/arch/csr/Zihpm/mhpmcounter15.yaml index fa067b80e4..a487e21c5b 100644 --- a/arch/csr/Zihpm/mhpmcounter15.yaml +++ b/arch/csr/Zihpm/mhpmcounter15.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter15 @@ -42,8 +40,8 @@ fields: [when="HPM_COUNTER_EN[15] == false"] Unimplemented performance counter. Must be read-only 0 (access does not cause trap). - type(): 'return (HPM_COUNTER_EN[15]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[15]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[15]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[15]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[15]) { return read_hpm_counter(15); diff --git a/arch/csr/Zihpm/mhpmcounter15h.yaml b/arch/csr/Zihpm/mhpmcounter15h.yaml index 56080a49ce..040f97e017 100644 --- a/arch/csr/Zihpm/mhpmcounter15h.yaml +++ b/arch/csr/Zihpm/mhpmcounter15h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter15h @@ -21,8 +19,8 @@ fields: alias: mhpmcounter.COUNT15[63:32] description: | Upper bits of counter. - type(): 'return (HPM_COUNTER_EN[15]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[15]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[15]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[15]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[15]) { return read_hpm_counter(15)[63:32]; diff --git a/arch/csr/Zihpm/mhpmcounter16.yaml b/arch/csr/Zihpm/mhpmcounter16.yaml index 3c0a9f6eb9..9ff6a82635 100644 --- a/arch/csr/Zihpm/mhpmcounter16.yaml +++ b/arch/csr/Zihpm/mhpmcounter16.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter16 @@ -42,8 +40,8 @@ fields: [when="HPM_COUNTER_EN[16] == false"] Unimplemented performance counter. Must be read-only 0 (access does not cause trap). - type(): 'return (HPM_COUNTER_EN[16]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[16]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[16]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[16]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[16]) { return read_hpm_counter(16); diff --git a/arch/csr/Zihpm/mhpmcounter16h.yaml b/arch/csr/Zihpm/mhpmcounter16h.yaml index 040cf26b59..1bbbb515ae 100644 --- a/arch/csr/Zihpm/mhpmcounter16h.yaml +++ b/arch/csr/Zihpm/mhpmcounter16h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter16h @@ -21,8 +19,8 @@ fields: alias: mhpmcounter.COUNT16[63:32] description: | Upper bits of counter. - type(): 'return (HPM_COUNTER_EN[16]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[16]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[16]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[16]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[16]) { return read_hpm_counter(16)[63:32]; diff --git a/arch/csr/Zihpm/mhpmcounter17.yaml b/arch/csr/Zihpm/mhpmcounter17.yaml index a053f43f7f..6c30f92d62 100644 --- a/arch/csr/Zihpm/mhpmcounter17.yaml +++ b/arch/csr/Zihpm/mhpmcounter17.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter17 @@ -42,8 +40,8 @@ fields: [when="HPM_COUNTER_EN[17] == false"] Unimplemented performance counter. Must be read-only 0 (access does not cause trap). - type(): 'return (HPM_COUNTER_EN[17]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[17]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[17]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[17]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[17]) { return read_hpm_counter(17); diff --git a/arch/csr/Zihpm/mhpmcounter17h.yaml b/arch/csr/Zihpm/mhpmcounter17h.yaml index 913a812714..d7450adaba 100644 --- a/arch/csr/Zihpm/mhpmcounter17h.yaml +++ b/arch/csr/Zihpm/mhpmcounter17h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter17h @@ -21,8 +19,8 @@ fields: alias: mhpmcounter.COUNT17[63:32] description: | Upper bits of counter. - type(): 'return (HPM_COUNTER_EN[17]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[17]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[17]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[17]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[17]) { return read_hpm_counter(17)[63:32]; diff --git a/arch/csr/Zihpm/mhpmcounter18.yaml b/arch/csr/Zihpm/mhpmcounter18.yaml index 8487fd3641..02b6dcd4fc 100644 --- a/arch/csr/Zihpm/mhpmcounter18.yaml +++ b/arch/csr/Zihpm/mhpmcounter18.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter18 @@ -42,8 +40,8 @@ fields: [when="HPM_COUNTER_EN[18] == false"] Unimplemented performance counter. Must be read-only 0 (access does not cause trap). - type(): 'return (HPM_COUNTER_EN[18]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[18]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[18]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[18]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[18]) { return read_hpm_counter(18); diff --git a/arch/csr/Zihpm/mhpmcounter18h.yaml b/arch/csr/Zihpm/mhpmcounter18h.yaml index b8dd73f0bd..4d9cffaac9 100644 --- a/arch/csr/Zihpm/mhpmcounter18h.yaml +++ b/arch/csr/Zihpm/mhpmcounter18h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter18h @@ -21,8 +19,8 @@ fields: alias: mhpmcounter.COUNT18[63:32] description: | Upper bits of counter. - type(): 'return (HPM_COUNTER_EN[18]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[18]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[18]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[18]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[18]) { return read_hpm_counter(18)[63:32]; diff --git a/arch/csr/Zihpm/mhpmcounter19.yaml b/arch/csr/Zihpm/mhpmcounter19.yaml index df0b9be79d..0e45c395c8 100644 --- a/arch/csr/Zihpm/mhpmcounter19.yaml +++ b/arch/csr/Zihpm/mhpmcounter19.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter19 @@ -42,8 +40,8 @@ fields: [when="HPM_COUNTER_EN[19] == false"] Unimplemented performance counter. Must be read-only 0 (access does not cause trap). - type(): 'return (HPM_COUNTER_EN[19]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[19]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[19]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[19]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[19]) { return read_hpm_counter(19); diff --git a/arch/csr/Zihpm/mhpmcounter19h.yaml b/arch/csr/Zihpm/mhpmcounter19h.yaml index 306eea43cc..63857f32ec 100644 --- a/arch/csr/Zihpm/mhpmcounter19h.yaml +++ b/arch/csr/Zihpm/mhpmcounter19h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter19h @@ -21,8 +19,8 @@ fields: alias: mhpmcounter.COUNT19[63:32] description: | Upper bits of counter. - type(): 'return (HPM_COUNTER_EN[19]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[19]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[19]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[19]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[19]) { return read_hpm_counter(19)[63:32]; diff --git a/arch/csr/Zihpm/mhpmcounter20.yaml b/arch/csr/Zihpm/mhpmcounter20.yaml index c902cf875d..6f7d6d1e85 100644 --- a/arch/csr/Zihpm/mhpmcounter20.yaml +++ b/arch/csr/Zihpm/mhpmcounter20.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter20 @@ -42,8 +40,8 @@ fields: [when="HPM_COUNTER_EN[20] == false"] Unimplemented performance counter. Must be read-only 0 (access does not cause trap). - type(): 'return (HPM_COUNTER_EN[20]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[20]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[20]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[20]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[20]) { return read_hpm_counter(20); diff --git a/arch/csr/Zihpm/mhpmcounter20h.yaml b/arch/csr/Zihpm/mhpmcounter20h.yaml index 7366268dec..ee8760ed75 100644 --- a/arch/csr/Zihpm/mhpmcounter20h.yaml +++ b/arch/csr/Zihpm/mhpmcounter20h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter20h @@ -21,8 +19,8 @@ fields: alias: mhpmcounter.COUNT20[63:32] description: | Upper bits of counter. - type(): 'return (HPM_COUNTER_EN[20]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[20]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[20]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[20]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[20]) { return read_hpm_counter(20)[63:32]; diff --git a/arch/csr/Zihpm/mhpmcounter21.yaml b/arch/csr/Zihpm/mhpmcounter21.yaml index 961203af38..b5cfa7a02d 100644 --- a/arch/csr/Zihpm/mhpmcounter21.yaml +++ b/arch/csr/Zihpm/mhpmcounter21.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter21 @@ -42,8 +40,8 @@ fields: [when="HPM_COUNTER_EN[21] == false"] Unimplemented performance counter. Must be read-only 0 (access does not cause trap). - type(): 'return (HPM_COUNTER_EN[21]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[21]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[21]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[21]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[21]) { return read_hpm_counter(21); diff --git a/arch/csr/Zihpm/mhpmcounter21h.yaml b/arch/csr/Zihpm/mhpmcounter21h.yaml index 8686eab27c..2437ed36bb 100644 --- a/arch/csr/Zihpm/mhpmcounter21h.yaml +++ b/arch/csr/Zihpm/mhpmcounter21h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter21h @@ -21,8 +19,8 @@ fields: alias: mhpmcounter.COUNT21[63:32] description: | Upper bits of counter. - type(): 'return (HPM_COUNTER_EN[21]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[21]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[21]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[21]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[21]) { return read_hpm_counter(21)[63:32]; diff --git a/arch/csr/Zihpm/mhpmcounter22.yaml b/arch/csr/Zihpm/mhpmcounter22.yaml index 1f1df6c96f..d35d8671dc 100644 --- a/arch/csr/Zihpm/mhpmcounter22.yaml +++ b/arch/csr/Zihpm/mhpmcounter22.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter22 @@ -42,8 +40,8 @@ fields: [when="HPM_COUNTER_EN[22] == false"] Unimplemented performance counter. Must be read-only 0 (access does not cause trap). - type(): 'return (HPM_COUNTER_EN[22]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[22]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[22]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[22]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[22]) { return read_hpm_counter(22); diff --git a/arch/csr/Zihpm/mhpmcounter22h.yaml b/arch/csr/Zihpm/mhpmcounter22h.yaml index f4049e79c8..2be137d451 100644 --- a/arch/csr/Zihpm/mhpmcounter22h.yaml +++ b/arch/csr/Zihpm/mhpmcounter22h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter22h @@ -21,8 +19,8 @@ fields: alias: mhpmcounter.COUNT22[63:32] description: | Upper bits of counter. - type(): 'return (HPM_COUNTER_EN[22]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[22]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[22]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[22]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[22]) { return read_hpm_counter(22)[63:32]; diff --git a/arch/csr/Zihpm/mhpmcounter23.yaml b/arch/csr/Zihpm/mhpmcounter23.yaml index 83c25f79f9..380c27d78d 100644 --- a/arch/csr/Zihpm/mhpmcounter23.yaml +++ b/arch/csr/Zihpm/mhpmcounter23.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter23 @@ -42,8 +40,8 @@ fields: [when="HPM_COUNTER_EN[23] == false"] Unimplemented performance counter. Must be read-only 0 (access does not cause trap). - type(): 'return (HPM_COUNTER_EN[23]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[23]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[23]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[23]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[23]) { return read_hpm_counter(23); diff --git a/arch/csr/Zihpm/mhpmcounter23h.yaml b/arch/csr/Zihpm/mhpmcounter23h.yaml index 9152e9d9a2..980c373798 100644 --- a/arch/csr/Zihpm/mhpmcounter23h.yaml +++ b/arch/csr/Zihpm/mhpmcounter23h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter23h @@ -21,8 +19,8 @@ fields: alias: mhpmcounter.COUNT23[63:32] description: | Upper bits of counter. - type(): 'return (HPM_COUNTER_EN[23]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[23]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[23]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[23]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[23]) { return read_hpm_counter(23)[63:32]; diff --git a/arch/csr/Zihpm/mhpmcounter24.yaml b/arch/csr/Zihpm/mhpmcounter24.yaml index c68626718c..4f66699999 100644 --- a/arch/csr/Zihpm/mhpmcounter24.yaml +++ b/arch/csr/Zihpm/mhpmcounter24.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter24 @@ -42,8 +40,8 @@ fields: [when="HPM_COUNTER_EN[24] == false"] Unimplemented performance counter. Must be read-only 0 (access does not cause trap). - type(): 'return (HPM_COUNTER_EN[24]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[24]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[24]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[24]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[24]) { return read_hpm_counter(24); diff --git a/arch/csr/Zihpm/mhpmcounter24h.yaml b/arch/csr/Zihpm/mhpmcounter24h.yaml index 55bdde30af..c609c26583 100644 --- a/arch/csr/Zihpm/mhpmcounter24h.yaml +++ b/arch/csr/Zihpm/mhpmcounter24h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter24h @@ -21,8 +19,8 @@ fields: alias: mhpmcounter.COUNT24[63:32] description: | Upper bits of counter. - type(): 'return (HPM_COUNTER_EN[24]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[24]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[24]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[24]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[24]) { return read_hpm_counter(24)[63:32]; diff --git a/arch/csr/Zihpm/mhpmcounter25.yaml b/arch/csr/Zihpm/mhpmcounter25.yaml index dca9e40282..ca1ea51987 100644 --- a/arch/csr/Zihpm/mhpmcounter25.yaml +++ b/arch/csr/Zihpm/mhpmcounter25.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter25 @@ -42,8 +40,8 @@ fields: [when="HPM_COUNTER_EN[25] == false"] Unimplemented performance counter. Must be read-only 0 (access does not cause trap). - type(): 'return (HPM_COUNTER_EN[25]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[25]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[25]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[25]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[25]) { return read_hpm_counter(25); diff --git a/arch/csr/Zihpm/mhpmcounter25h.yaml b/arch/csr/Zihpm/mhpmcounter25h.yaml index 3d136816be..147c52d261 100644 --- a/arch/csr/Zihpm/mhpmcounter25h.yaml +++ b/arch/csr/Zihpm/mhpmcounter25h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter25h @@ -21,8 +19,8 @@ fields: alias: mhpmcounter.COUNT25[63:32] description: | Upper bits of counter. - type(): 'return (HPM_COUNTER_EN[25]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[25]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[25]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[25]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[25]) { return read_hpm_counter(25)[63:32]; diff --git a/arch/csr/Zihpm/mhpmcounter26.yaml b/arch/csr/Zihpm/mhpmcounter26.yaml index 0f70f1721d..9175778c05 100644 --- a/arch/csr/Zihpm/mhpmcounter26.yaml +++ b/arch/csr/Zihpm/mhpmcounter26.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter26 @@ -42,8 +40,8 @@ fields: [when="HPM_COUNTER_EN[26] == false"] Unimplemented performance counter. Must be read-only 0 (access does not cause trap). - type(): 'return (HPM_COUNTER_EN[26]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[26]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[26]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[26]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[26]) { return read_hpm_counter(26); diff --git a/arch/csr/Zihpm/mhpmcounter26h.yaml b/arch/csr/Zihpm/mhpmcounter26h.yaml index b98d78a8cc..11138a32a5 100644 --- a/arch/csr/Zihpm/mhpmcounter26h.yaml +++ b/arch/csr/Zihpm/mhpmcounter26h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter26h @@ -21,8 +19,8 @@ fields: alias: mhpmcounter.COUNT26[63:32] description: | Upper bits of counter. - type(): 'return (HPM_COUNTER_EN[26]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[26]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[26]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[26]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[26]) { return read_hpm_counter(26)[63:32]; diff --git a/arch/csr/Zihpm/mhpmcounter27.yaml b/arch/csr/Zihpm/mhpmcounter27.yaml index 2682ce3749..0cc6b33f94 100644 --- a/arch/csr/Zihpm/mhpmcounter27.yaml +++ b/arch/csr/Zihpm/mhpmcounter27.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter27 @@ -42,8 +40,8 @@ fields: [when="HPM_COUNTER_EN[27] == false"] Unimplemented performance counter. Must be read-only 0 (access does not cause trap). - type(): 'return (HPM_COUNTER_EN[27]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[27]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[27]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[27]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[27]) { return read_hpm_counter(27); diff --git a/arch/csr/Zihpm/mhpmcounter27h.yaml b/arch/csr/Zihpm/mhpmcounter27h.yaml index b45fd8ebe7..8139cf8f7c 100644 --- a/arch/csr/Zihpm/mhpmcounter27h.yaml +++ b/arch/csr/Zihpm/mhpmcounter27h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter27h @@ -21,8 +19,8 @@ fields: alias: mhpmcounter.COUNT27[63:32] description: | Upper bits of counter. - type(): 'return (HPM_COUNTER_EN[27]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[27]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[27]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[27]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[27]) { return read_hpm_counter(27)[63:32]; diff --git a/arch/csr/Zihpm/mhpmcounter28.yaml b/arch/csr/Zihpm/mhpmcounter28.yaml index a1c4fbb257..f214594745 100644 --- a/arch/csr/Zihpm/mhpmcounter28.yaml +++ b/arch/csr/Zihpm/mhpmcounter28.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter28 @@ -42,8 +40,8 @@ fields: [when="HPM_COUNTER_EN[28] == false"] Unimplemented performance counter. Must be read-only 0 (access does not cause trap). - type(): 'return (HPM_COUNTER_EN[28]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[28]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[28]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[28]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[28]) { return read_hpm_counter(28); diff --git a/arch/csr/Zihpm/mhpmcounter28h.yaml b/arch/csr/Zihpm/mhpmcounter28h.yaml index 2167cc2e9c..995afc7501 100644 --- a/arch/csr/Zihpm/mhpmcounter28h.yaml +++ b/arch/csr/Zihpm/mhpmcounter28h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter28h @@ -21,8 +19,8 @@ fields: alias: mhpmcounter.COUNT28[63:32] description: | Upper bits of counter. - type(): 'return (HPM_COUNTER_EN[28]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[28]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[28]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[28]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[28]) { return read_hpm_counter(28)[63:32]; diff --git a/arch/csr/Zihpm/mhpmcounter29.yaml b/arch/csr/Zihpm/mhpmcounter29.yaml index 6127a0c550..367de7cfec 100644 --- a/arch/csr/Zihpm/mhpmcounter29.yaml +++ b/arch/csr/Zihpm/mhpmcounter29.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter29 @@ -42,8 +40,8 @@ fields: [when="HPM_COUNTER_EN[29] == false"] Unimplemented performance counter. Must be read-only 0 (access does not cause trap). - type(): 'return (HPM_COUNTER_EN[29]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[29]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[29]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[29]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[29]) { return read_hpm_counter(29); diff --git a/arch/csr/Zihpm/mhpmcounter29h.yaml b/arch/csr/Zihpm/mhpmcounter29h.yaml index e924c64607..f6f68ee5b4 100644 --- a/arch/csr/Zihpm/mhpmcounter29h.yaml +++ b/arch/csr/Zihpm/mhpmcounter29h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter29h @@ -21,8 +19,8 @@ fields: alias: mhpmcounter.COUNT29[63:32] description: | Upper bits of counter. - type(): 'return (HPM_COUNTER_EN[29]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[29]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[29]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[29]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[29]) { return read_hpm_counter(29)[63:32]; diff --git a/arch/csr/Zihpm/mhpmcounter3.yaml b/arch/csr/Zihpm/mhpmcounter3.yaml index 61729e21ab..5c8dd1c6e1 100644 --- a/arch/csr/Zihpm/mhpmcounter3.yaml +++ b/arch/csr/Zihpm/mhpmcounter3.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter3 @@ -42,8 +40,8 @@ fields: [when="HPM_COUNTER_EN[3] == false"] Unimplemented performance counter. Must be read-only 0 (access does not cause trap). - type(): 'return (HPM_COUNTER_EN[3]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[3]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[3]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[3]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[3]) { return read_hpm_counter(3); diff --git a/arch/csr/Zihpm/mhpmcounter30.yaml b/arch/csr/Zihpm/mhpmcounter30.yaml index a4ab437be7..441eaab905 100644 --- a/arch/csr/Zihpm/mhpmcounter30.yaml +++ b/arch/csr/Zihpm/mhpmcounter30.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter30 @@ -42,8 +40,8 @@ fields: [when="HPM_COUNTER_EN[30] == false"] Unimplemented performance counter. Must be read-only 0 (access does not cause trap). - type(): 'return (HPM_COUNTER_EN[30]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[30]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[30]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[30]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[30]) { return read_hpm_counter(30); diff --git a/arch/csr/Zihpm/mhpmcounter30h.yaml b/arch/csr/Zihpm/mhpmcounter30h.yaml index 603f63f891..01d5668808 100644 --- a/arch/csr/Zihpm/mhpmcounter30h.yaml +++ b/arch/csr/Zihpm/mhpmcounter30h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter30h @@ -21,8 +19,8 @@ fields: alias: mhpmcounter.COUNT30[63:32] description: | Upper bits of counter. - type(): 'return (HPM_COUNTER_EN[30]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[30]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[30]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[30]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[30]) { return read_hpm_counter(30)[63:32]; diff --git a/arch/csr/Zihpm/mhpmcounter31.yaml b/arch/csr/Zihpm/mhpmcounter31.yaml index 32c98cd502..917c8d533b 100644 --- a/arch/csr/Zihpm/mhpmcounter31.yaml +++ b/arch/csr/Zihpm/mhpmcounter31.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter31 @@ -42,8 +40,8 @@ fields: [when="HPM_COUNTER_EN[31] == false"] Unimplemented performance counter. Must be read-only 0 (access does not cause trap). - type(): 'return (HPM_COUNTER_EN[31]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[31]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[31]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[31]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[31]) { return read_hpm_counter(31); diff --git a/arch/csr/Zihpm/mhpmcounter31h.yaml b/arch/csr/Zihpm/mhpmcounter31h.yaml index da1da7a17e..185b961c33 100644 --- a/arch/csr/Zihpm/mhpmcounter31h.yaml +++ b/arch/csr/Zihpm/mhpmcounter31h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter31h @@ -21,8 +19,8 @@ fields: alias: mhpmcounter.COUNT31[63:32] description: | Upper bits of counter. - type(): 'return (HPM_COUNTER_EN[31]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[31]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[31]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[31]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[31]) { return read_hpm_counter(31)[63:32]; diff --git a/arch/csr/Zihpm/mhpmcounter3h.yaml b/arch/csr/Zihpm/mhpmcounter3h.yaml index cd0e5dd7c2..5b95135dca 100644 --- a/arch/csr/Zihpm/mhpmcounter3h.yaml +++ b/arch/csr/Zihpm/mhpmcounter3h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter3h @@ -21,8 +19,8 @@ fields: alias: mhpmcounter.COUNT3[63:32] description: | Upper bits of counter. - type(): 'return (HPM_COUNTER_EN[3]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[3]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[3]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[3]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[3]) { return read_hpm_counter(3)[63:32]; diff --git a/arch/csr/Zihpm/mhpmcounter4.yaml b/arch/csr/Zihpm/mhpmcounter4.yaml index eb5b9bbade..9fc827b0bf 100644 --- a/arch/csr/Zihpm/mhpmcounter4.yaml +++ b/arch/csr/Zihpm/mhpmcounter4.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter4 @@ -42,8 +40,8 @@ fields: [when="HPM_COUNTER_EN[4] == false"] Unimplemented performance counter. Must be read-only 0 (access does not cause trap). - type(): 'return (HPM_COUNTER_EN[4]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[4]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[4]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[4]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[4]) { return read_hpm_counter(4); diff --git a/arch/csr/Zihpm/mhpmcounter4h.yaml b/arch/csr/Zihpm/mhpmcounter4h.yaml index ca888f72ee..ff2ffb6a2b 100644 --- a/arch/csr/Zihpm/mhpmcounter4h.yaml +++ b/arch/csr/Zihpm/mhpmcounter4h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter4h @@ -21,8 +19,8 @@ fields: alias: mhpmcounter.COUNT4[63:32] description: | Upper bits of counter. - type(): 'return (HPM_COUNTER_EN[4]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[4]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[4]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[4]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[4]) { return read_hpm_counter(4)[63:32]; diff --git a/arch/csr/Zihpm/mhpmcounter5.yaml b/arch/csr/Zihpm/mhpmcounter5.yaml index 5fa038e73a..b4c035e04f 100644 --- a/arch/csr/Zihpm/mhpmcounter5.yaml +++ b/arch/csr/Zihpm/mhpmcounter5.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter5 @@ -42,8 +40,8 @@ fields: [when="HPM_COUNTER_EN[5] == false"] Unimplemented performance counter. Must be read-only 0 (access does not cause trap). - type(): 'return (HPM_COUNTER_EN[5]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[5]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[5]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[5]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[5]) { return read_hpm_counter(5); diff --git a/arch/csr/Zihpm/mhpmcounter5h.yaml b/arch/csr/Zihpm/mhpmcounter5h.yaml index 88ef7737f5..e8cc95b13b 100644 --- a/arch/csr/Zihpm/mhpmcounter5h.yaml +++ b/arch/csr/Zihpm/mhpmcounter5h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter5h @@ -21,8 +19,8 @@ fields: alias: mhpmcounter.COUNT5[63:32] description: | Upper bits of counter. - type(): 'return (HPM_COUNTER_EN[5]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[5]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[5]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[5]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[5]) { return read_hpm_counter(5)[63:32]; diff --git a/arch/csr/Zihpm/mhpmcounter6.yaml b/arch/csr/Zihpm/mhpmcounter6.yaml index 97527ec463..187e00a28b 100644 --- a/arch/csr/Zihpm/mhpmcounter6.yaml +++ b/arch/csr/Zihpm/mhpmcounter6.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter6 @@ -42,8 +40,8 @@ fields: [when="HPM_COUNTER_EN[6] == false"] Unimplemented performance counter. Must be read-only 0 (access does not cause trap). - type(): 'return (HPM_COUNTER_EN[6]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[6]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[6]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[6]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[6]) { return read_hpm_counter(6); diff --git a/arch/csr/Zihpm/mhpmcounter6h.yaml b/arch/csr/Zihpm/mhpmcounter6h.yaml index 6907ddba67..356a42d65f 100644 --- a/arch/csr/Zihpm/mhpmcounter6h.yaml +++ b/arch/csr/Zihpm/mhpmcounter6h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter6h @@ -21,8 +19,8 @@ fields: alias: mhpmcounter.COUNT6[63:32] description: | Upper bits of counter. - type(): 'return (HPM_COUNTER_EN[6]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[6]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[6]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[6]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[6]) { return read_hpm_counter(6)[63:32]; diff --git a/arch/csr/Zihpm/mhpmcounter7.yaml b/arch/csr/Zihpm/mhpmcounter7.yaml index cfb4ba8943..7d56e48d5a 100644 --- a/arch/csr/Zihpm/mhpmcounter7.yaml +++ b/arch/csr/Zihpm/mhpmcounter7.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter7 @@ -42,8 +40,8 @@ fields: [when="HPM_COUNTER_EN[7] == false"] Unimplemented performance counter. Must be read-only 0 (access does not cause trap). - type(): 'return (HPM_COUNTER_EN[7]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[7]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[7]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[7]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[7]) { return read_hpm_counter(7); diff --git a/arch/csr/Zihpm/mhpmcounter7h.yaml b/arch/csr/Zihpm/mhpmcounter7h.yaml index 08aa55fb7b..ae80b017a5 100644 --- a/arch/csr/Zihpm/mhpmcounter7h.yaml +++ b/arch/csr/Zihpm/mhpmcounter7h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter7h @@ -21,8 +19,8 @@ fields: alias: mhpmcounter.COUNT7[63:32] description: | Upper bits of counter. - type(): 'return (HPM_COUNTER_EN[7]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[7]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[7]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[7]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[7]) { return read_hpm_counter(7)[63:32]; diff --git a/arch/csr/Zihpm/mhpmcounter8.yaml b/arch/csr/Zihpm/mhpmcounter8.yaml index 2c71caa783..a29a653bcc 100644 --- a/arch/csr/Zihpm/mhpmcounter8.yaml +++ b/arch/csr/Zihpm/mhpmcounter8.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter8 @@ -42,8 +40,8 @@ fields: [when="HPM_COUNTER_EN[8] == false"] Unimplemented performance counter. Must be read-only 0 (access does not cause trap). - type(): 'return (HPM_COUNTER_EN[8]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[8]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[8]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[8]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[8]) { return read_hpm_counter(8); diff --git a/arch/csr/Zihpm/mhpmcounter8h.yaml b/arch/csr/Zihpm/mhpmcounter8h.yaml index 8ae9a5aed6..ab07e4a7cd 100644 --- a/arch/csr/Zihpm/mhpmcounter8h.yaml +++ b/arch/csr/Zihpm/mhpmcounter8h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter8h @@ -21,8 +19,8 @@ fields: alias: mhpmcounter.COUNT8[63:32] description: | Upper bits of counter. - type(): 'return (HPM_COUNTER_EN[8]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[8]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[8]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[8]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[8]) { return read_hpm_counter(8)[63:32]; diff --git a/arch/csr/Zihpm/mhpmcounter9.yaml b/arch/csr/Zihpm/mhpmcounter9.yaml index 73392f5f19..729999ee53 100644 --- a/arch/csr/Zihpm/mhpmcounter9.yaml +++ b/arch/csr/Zihpm/mhpmcounter9.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterN.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter9 @@ -42,8 +40,8 @@ fields: [when="HPM_COUNTER_EN[9] == false"] Unimplemented performance counter. Must be read-only 0 (access does not cause trap). - type(): 'return (HPM_COUNTER_EN[9]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[9]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[9]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[9]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[9]) { return read_hpm_counter(9); diff --git a/arch/csr/Zihpm/mhpmcounter9h.yaml b/arch/csr/Zihpm/mhpmcounter9h.yaml index 9081f053bb..307d049b43 100644 --- a/arch/csr/Zihpm/mhpmcounter9h.yaml +++ b/arch/csr/Zihpm/mhpmcounter9h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmcounterNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmcounter9h @@ -21,8 +19,8 @@ fields: alias: mhpmcounter.COUNT9[63:32] description: | Upper bits of counter. - type(): 'return (HPM_COUNTER_EN[9]) ? CsrFieldType::RWH : CsrFieldType::RO;' - reset_value(): 'return (HPM_COUNTER_EN[9]) ? UNDEFINED_LEGAL : 0;' + type(): "return (HPM_COUNTER_EN[9]) ? CsrFieldType::RWH : CsrFieldType::RO;" + reset_value(): "return (HPM_COUNTER_EN[9]) ? UNDEFINED_LEGAL : 0;" sw_read(): | if (HPM_COUNTER_EN[9]) { return read_hpm_counter(9)[63:32]; diff --git a/arch/csr/Zihpm/mhpmevent10.yaml b/arch/csr/Zihpm/mhpmevent10.yaml index 9b56c7491a..52359704cf 100644 --- a/arch/csr/Zihpm/mhpmevent10.yaml +++ b/arch/csr/Zihpm/mhpmevent10.yaml @@ -1,10 +1,7 @@ - - # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventN.layout # yaml-language-server: $schema=../../../schemas/csr_schema.json - $schema: csr_schema.json# kind: csr name: mhpmevent10 diff --git a/arch/csr/Zihpm/mhpmevent10h.yaml b/arch/csr/Zihpm/mhpmevent10h.yaml index 9fe80eb61f..ddc90479cd 100644 --- a/arch/csr/Zihpm/mhpmevent10h.yaml +++ b/arch/csr/Zihpm/mhpmevent10h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmevent10h diff --git a/arch/csr/Zihpm/mhpmevent11.yaml b/arch/csr/Zihpm/mhpmevent11.yaml index 500c11cbcc..f07693ca2c 100644 --- a/arch/csr/Zihpm/mhpmevent11.yaml +++ b/arch/csr/Zihpm/mhpmevent11.yaml @@ -1,10 +1,7 @@ - - # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventN.layout # yaml-language-server: $schema=../../../schemas/csr_schema.json - $schema: csr_schema.json# kind: csr name: mhpmevent11 diff --git a/arch/csr/Zihpm/mhpmevent11h.yaml b/arch/csr/Zihpm/mhpmevent11h.yaml index 7d1b6e9976..10a4d69ab0 100644 --- a/arch/csr/Zihpm/mhpmevent11h.yaml +++ b/arch/csr/Zihpm/mhpmevent11h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmevent11h diff --git a/arch/csr/Zihpm/mhpmevent12.yaml b/arch/csr/Zihpm/mhpmevent12.yaml index 3e06293c72..4233c540bf 100644 --- a/arch/csr/Zihpm/mhpmevent12.yaml +++ b/arch/csr/Zihpm/mhpmevent12.yaml @@ -1,10 +1,7 @@ - - # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventN.layout # yaml-language-server: $schema=../../../schemas/csr_schema.json - $schema: csr_schema.json# kind: csr name: mhpmevent12 diff --git a/arch/csr/Zihpm/mhpmevent12h.yaml b/arch/csr/Zihpm/mhpmevent12h.yaml index 054594b0d4..1561213e0b 100644 --- a/arch/csr/Zihpm/mhpmevent12h.yaml +++ b/arch/csr/Zihpm/mhpmevent12h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmevent12h diff --git a/arch/csr/Zihpm/mhpmevent13.yaml b/arch/csr/Zihpm/mhpmevent13.yaml index 5b4d051baf..b6691e1726 100644 --- a/arch/csr/Zihpm/mhpmevent13.yaml +++ b/arch/csr/Zihpm/mhpmevent13.yaml @@ -1,10 +1,7 @@ - - # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventN.layout # yaml-language-server: $schema=../../../schemas/csr_schema.json - $schema: csr_schema.json# kind: csr name: mhpmevent13 diff --git a/arch/csr/Zihpm/mhpmevent13h.yaml b/arch/csr/Zihpm/mhpmevent13h.yaml index 74ed46fdec..9d6a4c4f48 100644 --- a/arch/csr/Zihpm/mhpmevent13h.yaml +++ b/arch/csr/Zihpm/mhpmevent13h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmevent13h diff --git a/arch/csr/Zihpm/mhpmevent14.yaml b/arch/csr/Zihpm/mhpmevent14.yaml index 5b09f43685..ed534b8417 100644 --- a/arch/csr/Zihpm/mhpmevent14.yaml +++ b/arch/csr/Zihpm/mhpmevent14.yaml @@ -1,10 +1,7 @@ - - # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventN.layout # yaml-language-server: $schema=../../../schemas/csr_schema.json - $schema: csr_schema.json# kind: csr name: mhpmevent14 diff --git a/arch/csr/Zihpm/mhpmevent14h.yaml b/arch/csr/Zihpm/mhpmevent14h.yaml index eb395e86dd..53e1db9431 100644 --- a/arch/csr/Zihpm/mhpmevent14h.yaml +++ b/arch/csr/Zihpm/mhpmevent14h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmevent14h diff --git a/arch/csr/Zihpm/mhpmevent15.yaml b/arch/csr/Zihpm/mhpmevent15.yaml index 5c72db6da2..2140c2a97e 100644 --- a/arch/csr/Zihpm/mhpmevent15.yaml +++ b/arch/csr/Zihpm/mhpmevent15.yaml @@ -1,10 +1,7 @@ - - # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventN.layout # yaml-language-server: $schema=../../../schemas/csr_schema.json - $schema: csr_schema.json# kind: csr name: mhpmevent15 diff --git a/arch/csr/Zihpm/mhpmevent15h.yaml b/arch/csr/Zihpm/mhpmevent15h.yaml index 2914c5aa4a..a8298f5a03 100644 --- a/arch/csr/Zihpm/mhpmevent15h.yaml +++ b/arch/csr/Zihpm/mhpmevent15h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmevent15h diff --git a/arch/csr/Zihpm/mhpmevent16.yaml b/arch/csr/Zihpm/mhpmevent16.yaml index 6eefa2918a..7b041c5e8d 100644 --- a/arch/csr/Zihpm/mhpmevent16.yaml +++ b/arch/csr/Zihpm/mhpmevent16.yaml @@ -1,10 +1,7 @@ - - # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventN.layout # yaml-language-server: $schema=../../../schemas/csr_schema.json - $schema: csr_schema.json# kind: csr name: mhpmevent16 diff --git a/arch/csr/Zihpm/mhpmevent16h.yaml b/arch/csr/Zihpm/mhpmevent16h.yaml index 86c4539a12..7257f46c5f 100644 --- a/arch/csr/Zihpm/mhpmevent16h.yaml +++ b/arch/csr/Zihpm/mhpmevent16h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmevent16h diff --git a/arch/csr/Zihpm/mhpmevent17.yaml b/arch/csr/Zihpm/mhpmevent17.yaml index 235850d379..698dde435d 100644 --- a/arch/csr/Zihpm/mhpmevent17.yaml +++ b/arch/csr/Zihpm/mhpmevent17.yaml @@ -1,10 +1,7 @@ - - # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventN.layout # yaml-language-server: $schema=../../../schemas/csr_schema.json - $schema: csr_schema.json# kind: csr name: mhpmevent17 diff --git a/arch/csr/Zihpm/mhpmevent17h.yaml b/arch/csr/Zihpm/mhpmevent17h.yaml index e73159f139..70e07cc5b5 100644 --- a/arch/csr/Zihpm/mhpmevent17h.yaml +++ b/arch/csr/Zihpm/mhpmevent17h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmevent17h diff --git a/arch/csr/Zihpm/mhpmevent18.yaml b/arch/csr/Zihpm/mhpmevent18.yaml index 124d21a203..c6f2dfc40c 100644 --- a/arch/csr/Zihpm/mhpmevent18.yaml +++ b/arch/csr/Zihpm/mhpmevent18.yaml @@ -1,10 +1,7 @@ - - # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventN.layout # yaml-language-server: $schema=../../../schemas/csr_schema.json - $schema: csr_schema.json# kind: csr name: mhpmevent18 diff --git a/arch/csr/Zihpm/mhpmevent18h.yaml b/arch/csr/Zihpm/mhpmevent18h.yaml index 5d8f55fdcf..4cd34aaafa 100644 --- a/arch/csr/Zihpm/mhpmevent18h.yaml +++ b/arch/csr/Zihpm/mhpmevent18h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmevent18h diff --git a/arch/csr/Zihpm/mhpmevent19.yaml b/arch/csr/Zihpm/mhpmevent19.yaml index 381680576e..39dd37ef6e 100644 --- a/arch/csr/Zihpm/mhpmevent19.yaml +++ b/arch/csr/Zihpm/mhpmevent19.yaml @@ -1,10 +1,7 @@ - - # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventN.layout # yaml-language-server: $schema=../../../schemas/csr_schema.json - $schema: csr_schema.json# kind: csr name: mhpmevent19 diff --git a/arch/csr/Zihpm/mhpmevent19h.yaml b/arch/csr/Zihpm/mhpmevent19h.yaml index 30cf360770..2d67a0db2e 100644 --- a/arch/csr/Zihpm/mhpmevent19h.yaml +++ b/arch/csr/Zihpm/mhpmevent19h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmevent19h diff --git a/arch/csr/Zihpm/mhpmevent20.yaml b/arch/csr/Zihpm/mhpmevent20.yaml index 370a5c4ce1..2c6645a79f 100644 --- a/arch/csr/Zihpm/mhpmevent20.yaml +++ b/arch/csr/Zihpm/mhpmevent20.yaml @@ -1,10 +1,7 @@ - - # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventN.layout # yaml-language-server: $schema=../../../schemas/csr_schema.json - $schema: csr_schema.json# kind: csr name: mhpmevent20 diff --git a/arch/csr/Zihpm/mhpmevent20h.yaml b/arch/csr/Zihpm/mhpmevent20h.yaml index 1073830fd4..32f9027ac7 100644 --- a/arch/csr/Zihpm/mhpmevent20h.yaml +++ b/arch/csr/Zihpm/mhpmevent20h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmevent20h diff --git a/arch/csr/Zihpm/mhpmevent21.yaml b/arch/csr/Zihpm/mhpmevent21.yaml index 9164044e1e..257aec1e18 100644 --- a/arch/csr/Zihpm/mhpmevent21.yaml +++ b/arch/csr/Zihpm/mhpmevent21.yaml @@ -1,10 +1,7 @@ - - # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventN.layout # yaml-language-server: $schema=../../../schemas/csr_schema.json - $schema: csr_schema.json# kind: csr name: mhpmevent21 diff --git a/arch/csr/Zihpm/mhpmevent21h.yaml b/arch/csr/Zihpm/mhpmevent21h.yaml index cbb2757da8..f5fa3dfe28 100644 --- a/arch/csr/Zihpm/mhpmevent21h.yaml +++ b/arch/csr/Zihpm/mhpmevent21h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmevent21h diff --git a/arch/csr/Zihpm/mhpmevent22.yaml b/arch/csr/Zihpm/mhpmevent22.yaml index a441461886..4731ba4e72 100644 --- a/arch/csr/Zihpm/mhpmevent22.yaml +++ b/arch/csr/Zihpm/mhpmevent22.yaml @@ -1,10 +1,7 @@ - - # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventN.layout # yaml-language-server: $schema=../../../schemas/csr_schema.json - $schema: csr_schema.json# kind: csr name: mhpmevent22 diff --git a/arch/csr/Zihpm/mhpmevent22h.yaml b/arch/csr/Zihpm/mhpmevent22h.yaml index 1806b27898..a8adbe8a1e 100644 --- a/arch/csr/Zihpm/mhpmevent22h.yaml +++ b/arch/csr/Zihpm/mhpmevent22h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmevent22h diff --git a/arch/csr/Zihpm/mhpmevent23.yaml b/arch/csr/Zihpm/mhpmevent23.yaml index 0c3d7d2f73..cc78b7c595 100644 --- a/arch/csr/Zihpm/mhpmevent23.yaml +++ b/arch/csr/Zihpm/mhpmevent23.yaml @@ -1,10 +1,7 @@ - - # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventN.layout # yaml-language-server: $schema=../../../schemas/csr_schema.json - $schema: csr_schema.json# kind: csr name: mhpmevent23 diff --git a/arch/csr/Zihpm/mhpmevent23h.yaml b/arch/csr/Zihpm/mhpmevent23h.yaml index 41a9f0b02f..ba1566e3d1 100644 --- a/arch/csr/Zihpm/mhpmevent23h.yaml +++ b/arch/csr/Zihpm/mhpmevent23h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmevent23h diff --git a/arch/csr/Zihpm/mhpmevent24.yaml b/arch/csr/Zihpm/mhpmevent24.yaml index b566e153ca..cd86cfa8ff 100644 --- a/arch/csr/Zihpm/mhpmevent24.yaml +++ b/arch/csr/Zihpm/mhpmevent24.yaml @@ -1,10 +1,7 @@ - - # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventN.layout # yaml-language-server: $schema=../../../schemas/csr_schema.json - $schema: csr_schema.json# kind: csr name: mhpmevent24 diff --git a/arch/csr/Zihpm/mhpmevent24h.yaml b/arch/csr/Zihpm/mhpmevent24h.yaml index 560463c510..69adfe7536 100644 --- a/arch/csr/Zihpm/mhpmevent24h.yaml +++ b/arch/csr/Zihpm/mhpmevent24h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmevent24h diff --git a/arch/csr/Zihpm/mhpmevent25.yaml b/arch/csr/Zihpm/mhpmevent25.yaml index 55879cabe9..79ce58cbd0 100644 --- a/arch/csr/Zihpm/mhpmevent25.yaml +++ b/arch/csr/Zihpm/mhpmevent25.yaml @@ -1,10 +1,7 @@ - - # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventN.layout # yaml-language-server: $schema=../../../schemas/csr_schema.json - $schema: csr_schema.json# kind: csr name: mhpmevent25 diff --git a/arch/csr/Zihpm/mhpmevent25h.yaml b/arch/csr/Zihpm/mhpmevent25h.yaml index 1eefa3bdfe..411ba06a52 100644 --- a/arch/csr/Zihpm/mhpmevent25h.yaml +++ b/arch/csr/Zihpm/mhpmevent25h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmevent25h diff --git a/arch/csr/Zihpm/mhpmevent26.yaml b/arch/csr/Zihpm/mhpmevent26.yaml index 0efdccb2ab..3537d02c35 100644 --- a/arch/csr/Zihpm/mhpmevent26.yaml +++ b/arch/csr/Zihpm/mhpmevent26.yaml @@ -1,10 +1,7 @@ - - # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventN.layout # yaml-language-server: $schema=../../../schemas/csr_schema.json - $schema: csr_schema.json# kind: csr name: mhpmevent26 diff --git a/arch/csr/Zihpm/mhpmevent26h.yaml b/arch/csr/Zihpm/mhpmevent26h.yaml index 73bd744a72..276bf866fa 100644 --- a/arch/csr/Zihpm/mhpmevent26h.yaml +++ b/arch/csr/Zihpm/mhpmevent26h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmevent26h diff --git a/arch/csr/Zihpm/mhpmevent27.yaml b/arch/csr/Zihpm/mhpmevent27.yaml index 22d5be09ce..339b1afc40 100644 --- a/arch/csr/Zihpm/mhpmevent27.yaml +++ b/arch/csr/Zihpm/mhpmevent27.yaml @@ -1,10 +1,7 @@ - - # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventN.layout # yaml-language-server: $schema=../../../schemas/csr_schema.json - $schema: csr_schema.json# kind: csr name: mhpmevent27 diff --git a/arch/csr/Zihpm/mhpmevent27h.yaml b/arch/csr/Zihpm/mhpmevent27h.yaml index cb1a55da6b..f5136e8ec1 100644 --- a/arch/csr/Zihpm/mhpmevent27h.yaml +++ b/arch/csr/Zihpm/mhpmevent27h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmevent27h diff --git a/arch/csr/Zihpm/mhpmevent28.yaml b/arch/csr/Zihpm/mhpmevent28.yaml index 172b0e1aa8..c38cdcab03 100644 --- a/arch/csr/Zihpm/mhpmevent28.yaml +++ b/arch/csr/Zihpm/mhpmevent28.yaml @@ -1,10 +1,7 @@ - - # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventN.layout # yaml-language-server: $schema=../../../schemas/csr_schema.json - $schema: csr_schema.json# kind: csr name: mhpmevent28 diff --git a/arch/csr/Zihpm/mhpmevent28h.yaml b/arch/csr/Zihpm/mhpmevent28h.yaml index 1f3bb09abd..6f5b083ed0 100644 --- a/arch/csr/Zihpm/mhpmevent28h.yaml +++ b/arch/csr/Zihpm/mhpmevent28h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmevent28h diff --git a/arch/csr/Zihpm/mhpmevent29.yaml b/arch/csr/Zihpm/mhpmevent29.yaml index 42bbe1ef88..393ec1fd5c 100644 --- a/arch/csr/Zihpm/mhpmevent29.yaml +++ b/arch/csr/Zihpm/mhpmevent29.yaml @@ -1,10 +1,7 @@ - - # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventN.layout # yaml-language-server: $schema=../../../schemas/csr_schema.json - $schema: csr_schema.json# kind: csr name: mhpmevent29 diff --git a/arch/csr/Zihpm/mhpmevent29h.yaml b/arch/csr/Zihpm/mhpmevent29h.yaml index a7c41c7ab3..11c6f67d7f 100644 --- a/arch/csr/Zihpm/mhpmevent29h.yaml +++ b/arch/csr/Zihpm/mhpmevent29h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmevent29h diff --git a/arch/csr/Zihpm/mhpmevent3.yaml b/arch/csr/Zihpm/mhpmevent3.yaml index 2f309d6d94..64006dee4e 100644 --- a/arch/csr/Zihpm/mhpmevent3.yaml +++ b/arch/csr/Zihpm/mhpmevent3.yaml @@ -1,10 +1,7 @@ - - # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventN.layout # yaml-language-server: $schema=../../../schemas/csr_schema.json - $schema: csr_schema.json# kind: csr name: mhpmevent3 diff --git a/arch/csr/Zihpm/mhpmevent30.yaml b/arch/csr/Zihpm/mhpmevent30.yaml index eb485ec4fd..17a7b1a94c 100644 --- a/arch/csr/Zihpm/mhpmevent30.yaml +++ b/arch/csr/Zihpm/mhpmevent30.yaml @@ -1,10 +1,7 @@ - - # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventN.layout # yaml-language-server: $schema=../../../schemas/csr_schema.json - $schema: csr_schema.json# kind: csr name: mhpmevent30 diff --git a/arch/csr/Zihpm/mhpmevent30h.yaml b/arch/csr/Zihpm/mhpmevent30h.yaml index 3de930101c..27b55926c8 100644 --- a/arch/csr/Zihpm/mhpmevent30h.yaml +++ b/arch/csr/Zihpm/mhpmevent30h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmevent30h diff --git a/arch/csr/Zihpm/mhpmevent31.yaml b/arch/csr/Zihpm/mhpmevent31.yaml index 2e19278f22..281363e275 100644 --- a/arch/csr/Zihpm/mhpmevent31.yaml +++ b/arch/csr/Zihpm/mhpmevent31.yaml @@ -1,10 +1,7 @@ - - # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventN.layout # yaml-language-server: $schema=../../../schemas/csr_schema.json - $schema: csr_schema.json# kind: csr name: mhpmevent31 diff --git a/arch/csr/Zihpm/mhpmevent31h.yaml b/arch/csr/Zihpm/mhpmevent31h.yaml index 7e03cc52ec..0dca0fbe7f 100644 --- a/arch/csr/Zihpm/mhpmevent31h.yaml +++ b/arch/csr/Zihpm/mhpmevent31h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmevent31h diff --git a/arch/csr/Zihpm/mhpmevent3h.yaml b/arch/csr/Zihpm/mhpmevent3h.yaml index a2e4999af5..b92a0a8e0c 100644 --- a/arch/csr/Zihpm/mhpmevent3h.yaml +++ b/arch/csr/Zihpm/mhpmevent3h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmevent3h diff --git a/arch/csr/Zihpm/mhpmevent4.yaml b/arch/csr/Zihpm/mhpmevent4.yaml index 62e60497f5..4c42d7c2de 100644 --- a/arch/csr/Zihpm/mhpmevent4.yaml +++ b/arch/csr/Zihpm/mhpmevent4.yaml @@ -1,10 +1,7 @@ - - # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventN.layout # yaml-language-server: $schema=../../../schemas/csr_schema.json - $schema: csr_schema.json# kind: csr name: mhpmevent4 diff --git a/arch/csr/Zihpm/mhpmevent4h.yaml b/arch/csr/Zihpm/mhpmevent4h.yaml index 9981a53d11..e70ed1280d 100644 --- a/arch/csr/Zihpm/mhpmevent4h.yaml +++ b/arch/csr/Zihpm/mhpmevent4h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmevent4h diff --git a/arch/csr/Zihpm/mhpmevent5.yaml b/arch/csr/Zihpm/mhpmevent5.yaml index 6f84cbb999..a5dcd5c673 100644 --- a/arch/csr/Zihpm/mhpmevent5.yaml +++ b/arch/csr/Zihpm/mhpmevent5.yaml @@ -1,10 +1,7 @@ - - # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventN.layout # yaml-language-server: $schema=../../../schemas/csr_schema.json - $schema: csr_schema.json# kind: csr name: mhpmevent5 diff --git a/arch/csr/Zihpm/mhpmevent5h.yaml b/arch/csr/Zihpm/mhpmevent5h.yaml index 9194e47940..b8db07f6f7 100644 --- a/arch/csr/Zihpm/mhpmevent5h.yaml +++ b/arch/csr/Zihpm/mhpmevent5h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmevent5h diff --git a/arch/csr/Zihpm/mhpmevent6.yaml b/arch/csr/Zihpm/mhpmevent6.yaml index d60f46635d..a9bdf1c39a 100644 --- a/arch/csr/Zihpm/mhpmevent6.yaml +++ b/arch/csr/Zihpm/mhpmevent6.yaml @@ -1,10 +1,7 @@ - - # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventN.layout # yaml-language-server: $schema=../../../schemas/csr_schema.json - $schema: csr_schema.json# kind: csr name: mhpmevent6 diff --git a/arch/csr/Zihpm/mhpmevent6h.yaml b/arch/csr/Zihpm/mhpmevent6h.yaml index 4bcfb41419..d6e9003aa5 100644 --- a/arch/csr/Zihpm/mhpmevent6h.yaml +++ b/arch/csr/Zihpm/mhpmevent6h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmevent6h diff --git a/arch/csr/Zihpm/mhpmevent7.yaml b/arch/csr/Zihpm/mhpmevent7.yaml index a439e216e3..2cc53fd9b9 100644 --- a/arch/csr/Zihpm/mhpmevent7.yaml +++ b/arch/csr/Zihpm/mhpmevent7.yaml @@ -1,10 +1,7 @@ - - # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventN.layout # yaml-language-server: $schema=../../../schemas/csr_schema.json - $schema: csr_schema.json# kind: csr name: mhpmevent7 diff --git a/arch/csr/Zihpm/mhpmevent7h.yaml b/arch/csr/Zihpm/mhpmevent7h.yaml index a35879b13a..f04327a66b 100644 --- a/arch/csr/Zihpm/mhpmevent7h.yaml +++ b/arch/csr/Zihpm/mhpmevent7h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmevent7h diff --git a/arch/csr/Zihpm/mhpmevent8.yaml b/arch/csr/Zihpm/mhpmevent8.yaml index 2b7d071270..769eb3ab16 100644 --- a/arch/csr/Zihpm/mhpmevent8.yaml +++ b/arch/csr/Zihpm/mhpmevent8.yaml @@ -1,10 +1,7 @@ - - # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventN.layout # yaml-language-server: $schema=../../../schemas/csr_schema.json - $schema: csr_schema.json# kind: csr name: mhpmevent8 diff --git a/arch/csr/Zihpm/mhpmevent8h.yaml b/arch/csr/Zihpm/mhpmevent8h.yaml index c3abcd1623..0370dc3186 100644 --- a/arch/csr/Zihpm/mhpmevent8h.yaml +++ b/arch/csr/Zihpm/mhpmevent8h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmevent8h diff --git a/arch/csr/Zihpm/mhpmevent9.yaml b/arch/csr/Zihpm/mhpmevent9.yaml index 821178e99b..1674e0c646 100644 --- a/arch/csr/Zihpm/mhpmevent9.yaml +++ b/arch/csr/Zihpm/mhpmevent9.yaml @@ -1,10 +1,7 @@ - - # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventN.layout # yaml-language-server: $schema=../../../schemas/csr_schema.json - $schema: csr_schema.json# kind: csr name: mhpmevent9 diff --git a/arch/csr/Zihpm/mhpmevent9h.yaml b/arch/csr/Zihpm/mhpmevent9h.yaml index 90ebe2e27d..946464b3b0 100644 --- a/arch/csr/Zihpm/mhpmevent9h.yaml +++ b/arch/csr/Zihpm/mhpmevent9h.yaml @@ -2,8 +2,6 @@ # WARNING: This file is auto-generated from arch/csr/Zihpm/mhpmeventNh.layout - - $schema: csr_schema.json# kind: csr name: mhpmevent9h diff --git a/arch/csr/hstatus.yaml b/arch/csr/hstatus.yaml index c14c193312..9e667159d3 100644 --- a/arch/csr/hstatus.yaml +++ b/arch/csr/hstatus.yaml @@ -40,7 +40,6 @@ fields: [when,"VSXLEN = 64"] Because the implementation only supports a single VSXLEN == 64, this field is read-only-1. - type(): | if ((VSXLEN == 32) || (VSXLEN == 64)) { return CsrFieldType::RO; diff --git a/arch/csr/mcause.yaml b/arch/csr/mcause.yaml index a097a3f0ef..11b8b07d58 100644 --- a/arch/csr/mcause.yaml +++ b/arch/csr/mcause.yaml @@ -1,6 +1,5 @@ # yaml-language-server: $schema=../../schemas/csr_schema.json - $schema: "csr_schema.json#" kind: csr name: mcause diff --git a/arch/csr/mconfigptr.yaml b/arch/csr/mconfigptr.yaml index 49fad5cc8f..571d16d159 100644 --- a/arch/csr/mconfigptr.yaml +++ b/arch/csr/mconfigptr.yaml @@ -36,7 +36,6 @@ description: | M-mode software towards the beginning of the boot process. ==== - priv_mode: M length: MXLEN definedBy: diff --git a/arch/csr/mideleg.yaml b/arch/csr/mideleg.yaml index dab340dcec..9318f9d3d6 100644 --- a/arch/csr/mideleg.yaml +++ b/arch/csr/mideleg.yaml @@ -11,13 +11,13 @@ definedBy: # after 1.9.1, mideleg does not exist whe S-mode is not implemented # we can represent that by making mideleg an S extension CSR post 1.9.1 oneOf: - - name: Sm - version: "<= 1.9.1" - - allOf: - - name: S - version: "> 1.9.1" - name: Sm - version: "> 1.9.1" + version: "<= 1.9.1" + - allOf: + - name: S + version: "> 1.9.1" + - name: Sm + version: "> 1.9.1" description: | Controls exception delegation from M-mode to HS/S-mode diff --git a/arch/csr/mstatus.yaml b/arch/csr/mstatus.yaml index f496aa1ac1..54e0e7aaf4 100644 --- a/arch/csr/mstatus.yaml +++ b/arch/csr/mstatus.yaml @@ -24,7 +24,7 @@ fields: Read-only bit that summarizes whether either the FS, XS, or VS fields signal the presence of some dirty state. definedBy: - anyOf: [F,V] # NOTE: if you implement a custom extension overlay that writes to XS, then you need to add your extension here in the overlay as well + anyOf: [F, V] # NOTE: if you implement a custom extension overlay that writes to XS, then you need to add your extension here in the overlay as well type(): | # this is read-only if FS and VS are both read-only # otherwise, it is read-only with hardware update diff --git a/arch/csr/scause.yaml b/arch/csr/scause.yaml index 2e0e585597..c206cd60de 100644 --- a/arch/csr/scause.yaml +++ b/arch/csr/scause.yaml @@ -1,6 +1,5 @@ # yaml-language-server: $schema=../../schemas/csr_schema.json - $schema: "csr_schema.json#" kind: csr name: scause diff --git a/arch/ext/A.yaml b/arch/ext/A.yaml index f72416a5b2..ec0ee84087 100644 --- a/arch/ext/A.yaml +++ b/arch/ext/A.yaml @@ -9,16 +9,16 @@ company: name: RISC-V International url: https://riscv.org versions: -- version: "2.1.0" - state: ratified - ratification_date: 2019-12 - contributors: - - name: Unknown - email: unknown@void.segfault - company: Unknown - implies: - - [Zaamo, "1.0.0"] - - [Zalrsc, "1.0.0"] + - version: "2.1.0" + state: ratified + ratification_date: 2019-12 + contributors: + - name: Unknown + email: unknown@void.segfault + company: Unknown + implies: + - [Zaamo, "1.0.0"] + - [Zalrsc, "1.0.0"] description: | The atomic-instruction extension, named `A`, contains @@ -87,10 +87,10 @@ params: schema: type: string enum: - - reserve naturally-aligned 64-byte region - - reserve naturally-aligned 128-byte region - - reserve exactly enough to cover the access - - custom + - reserve naturally-aligned 64-byte region + - reserve naturally-aligned 128-byte region + - reserve exactly enough to cover the access + - custom LRSC_FAIL_ON_VA_SYNONYM: description: | Whether or not an `sc.l`/`sc.d` will fail if its VA does not match the VA of the prior @@ -107,9 +107,9 @@ params: schema: type: string enum: - - always raise misaligned exception - - always raise access fault - - custom + - always raise misaligned exception + - always raise access fault + - custom LRSC_FAIL_ON_NON_EXACT_LRSC: description: | Whether or not a Store Conditional fails if its physical address and size do not diff --git a/arch/ext/B.yaml b/arch/ext/B.yaml index b7eac4986c..51b7928c09 100644 --- a/arch/ext/B.yaml +++ b/arch/ext/B.yaml @@ -12,18 +12,18 @@ doc_license: name: Creative Commons Attribution 4.0 International License url: https://creativecommons.org/licenses/by/4.0/ versions: -- version: "1.0.0" - state: ratified - ratification_date: 2024-04 - contributors: - - name: Ved Shanbhogue - email: ved@rivosinc.com - company: Rivos, Inc. - url: https://drive.google.com/file/d/1SgLoasaBjs5WboQMaU3wpHkjUwV71UZn/view - implies: - - [Zba, "1.0.0"] - - [Zbb, "1.0.0"] - - [Zbs, "1.0.0"] + - version: "1.0.0" + state: ratified + ratification_date: 2024-04 + contributors: + - name: Ved Shanbhogue + email: ved@rivosinc.com + company: Rivos, Inc. + url: https://drive.google.com/file/d/1SgLoasaBjs5WboQMaU3wpHkjUwV71UZn/view + implies: + - [Zba, "1.0.0"] + - [Zbb, "1.0.0"] + - [Zbs, "1.0.0"] description: | The B standard extension comprises instructions provided by the `Zba`, `Zbb`, and `Zbs` extensions. diff --git a/arch/ext/C.yaml b/arch/ext/C.yaml index 4559fa8c66..6020da8843 100644 --- a/arch/ext/C.yaml +++ b/arch/ext/C.yaml @@ -12,9 +12,9 @@ doc_license: name: Creative Commons Attribution 4.0 International License url: https://creativecommons.org/licenses/by/4.0/ versions: -- version: "2.2.0" - state: ratified - ratification_date: 2019-12 + - version: "2.2.0" + state: ratified + ratification_date: 2019-12 description: | The `C` extension reduces static and dynamic code size by adding short 16-bit instruction encodings for common operations. The C diff --git a/arch/ext/D.yaml b/arch/ext/D.yaml index a997789999..849ee00423 100644 --- a/arch/ext/D.yaml +++ b/arch/ext/D.yaml @@ -6,12 +6,12 @@ name: D type: unprivileged long_name: Double-precision floating-point versions: -- version: "2.2.0" - state: ratified - ratification_date: 2019-12 - changes: - - Define NaN-boxing scheme, changed definition of FMAX and FMIN - implies: [F, "2.2.0"] + - version: "2.2.0" + state: ratified + ratification_date: 2019-12 + changes: + - Define NaN-boxing scheme, changed definition of FMAX and FMIN + implies: [F, "2.2.0"] description: | The `D` extension adds double-precision floating-point computational instructions compliant diff --git a/arch/ext/F.yaml b/arch/ext/F.yaml index fd45f3bccc..e24d2f2570 100644 --- a/arch/ext/F.yaml +++ b/arch/ext/F.yaml @@ -6,11 +6,11 @@ name: F type: unprivileged long_name: Single-precision floating-point versions: -- version: "2.2.0" - state: ratified - ratification_date: 2019-12 - changes: - - Define NaN-boxing scheme, changed definition of FMAX and FMIN + - version: "2.2.0" + state: ratified + ratification_date: 2019-12 + changes: + - Define NaN-boxing scheme, changed definition of FMAX and FMIN description: | This chapter describes the standard instruction-set extension for single-precision floating-point, which is named "F" and adds @@ -262,7 +262,7 @@ params: type: array items: type: integer - enum: [0,1,2,3] + enum: [0, 1, 2, 3] maxItems: 4 uniqueItems: true also_defined_in: S diff --git a/arch/ext/H.yaml b/arch/ext/H.yaml index 3ff99325b4..e63b9863b3 100644 --- a/arch/ext/H.yaml +++ b/arch/ext/H.yaml @@ -6,41 +6,41 @@ name: H type: privileged long_name: Hypervisor versions: -- version: "1.0.0" - state: ratified - ratification_date: 2019-12 - requires: - name: S - version: '>= 1.12.0' + - version: "1.0.0" + state: ratified + ratification_date: 2019-12 + requires: + name: S + version: ">= 1.12.0" interrupt_codes: -- num: 2 - name: Virtual supervisor software interrupt - var: VirtualSupervisorSoftware -- num: 6 - name: Virtual supervisor timer interrupt - var: VirtualSupervisorTimer -- num: 10 - name: Virtual supervisor external interrupt - var: VirtualSupervisorExternal -- num: 12 - name: Supervisor guest external interrupt - var: SupervisorGuestExternal + - num: 2 + name: Virtual supervisor software interrupt + var: VirtualSupervisorSoftware + - num: 6 + name: Virtual supervisor timer interrupt + var: VirtualSupervisorTimer + - num: 10 + name: Virtual supervisor external interrupt + var: VirtualSupervisorExternal + - num: 12 + name: Supervisor guest external interrupt + var: SupervisorGuestExternal exception_codes: -- num: 10 - name: Environment call from VS-mode - var: VScall -- num: 20 - name: Instruction guest page fault - var: InstructionGuestPageFault -- num: 21 - name: Load guest page fault - var: LoadGuestPageFault -- num: 22 - name: Virtual instruction - var: VirtualInstruction -- num: 23 - name: Store/AMO guest page fault - var: StoreAmoGuestPageFault + - num: 10 + name: Environment call from VS-mode + var: VScall + - num: 20 + name: Instruction guest page fault + var: InstructionGuestPageFault + - num: 21 + name: Load guest page fault + var: LoadGuestPageFault + - num: 22 + name: Virtual instruction + var: VirtualInstruction + - num: 23 + name: Store/AMO guest page fault + var: StoreAmoGuestPageFault description: | This chapter describes the RISC-V hypervisor extension, which virtualizes the supervisor-level architecture to support the efficient @@ -458,10 +458,10 @@ params: schema: type: string enum: - - "always zero" - - "always pseudoinstruction" - - "always transformed standard instruction" - - "custom" + - "always zero" + - "always pseudoinstruction" + - "always transformed standard instruction" + - "custom" TINST_VALUE_ON_FINAL_STORE_AMO_GUEST_PAGE_FAULT: description: | Value to write into htval/mtval2 when there is a guest page fault on a final translation. @@ -474,10 +474,10 @@ params: schema: type: string enum: - - "always zero" - - "always pseudoinstruction" - - "always transformed standard instruction" - - "custom" + - "always zero" + - "always pseudoinstruction" + - "always transformed standard instruction" + - "custom" TINST_VALUE_ON_FINAL_INSTRUCTION_GUEST_PAGE_FAULT: description: | Value to write into htval/mtval2 when there is a guest page fault on a final translation. @@ -488,8 +488,8 @@ params: schema: type: string enum: - - "always zero" - - "always pseudoinstruction" + - "always zero" + - "always pseudoinstruction" TINST_VALUE_ON_INSTRUCTION_ADDRESS_MISALIGNED: description: | Value written into htinst/mtinst when there is an instruction address misaligned exception. @@ -500,8 +500,8 @@ params: schema: type: string enum: - - "always zero" - - "custom" + - "always zero" + - "custom" TINST_VALUE_ON_BREAKPOINT: description: | Value written into htinst/mtinst on a Breakpoint exception from VU/VS-mode. @@ -511,7 +511,7 @@ params: * "custom": Write a custom value, which resuls in UNPREDICTABLE schema: type: string - enum: ['always zero', 'custom'] + enum: ["always zero", "custom"] TINST_VALUE_ON_VIRTUAL_INSTRUCTION: description: | Value written into htinst/mtinst on a VirtualInstruction exception from VU/VS-mode. @@ -521,7 +521,7 @@ params: * "custom": Write a custom value, which resuls in UNPREDICTABLE schema: type: string - enum: ['always zero', 'custom'] + enum: ["always zero", "custom"] TINST_VALUE_ON_LOAD_ADDRESS_MISALIGNED: description: | Value written into htinst/mtinst on a VirtualInstruction exception from VU/VS-mode. @@ -532,7 +532,7 @@ params: * "custom": Write a custom value, which resuls in UNPREDICTABLE schema: type: string - enum: ['always zero', 'always transformed standard instruction', 'custom'] + enum: ["always zero", "always transformed standard instruction", "custom"] TINST_VALUE_ON_LOAD_ACCESS_FAULT: description: | Value written into htinst/mtinst on an AccessFault exception from VU/VS-mode. @@ -543,7 +543,7 @@ params: * "custom": Write a custom value, which resuls in UNPREDICTABLE schema: type: string - enum: ['always zero', 'always transformed standard instruction', 'custom'] + enum: ["always zero", "always transformed standard instruction", "custom"] TINST_VALUE_ON_STORE_AMO_ADDRESS_MISALIGNED: description: | Value written into htinst/mtinst on a VirtualInstruction exception from VU/VS-mode. @@ -554,7 +554,7 @@ params: * "custom": Write a custom value, which resuls in UNPREDICTABLE schema: type: string - enum: ['always zero', 'always transformed standard instruction', 'custom'] + enum: ["always zero", "always transformed standard instruction", "custom"] TINST_VALUE_ON_STORE_AMO_ACCESS_FAULT: description: | Value written into htinst/mtinst on an AccessFault exception from VU/VS-mode. @@ -565,7 +565,7 @@ params: * "custom": Write a custom value, which resuls in UNPREDICTABLE schema: type: string - enum: ['always zero', 'always transformed standard instruction', 'custom'] + enum: ["always zero", "always transformed standard instruction", "custom"] TINST_VALUE_ON_UCALL: description: | Value written into htinst/mtinst on a UCall exception from VU/VS-mode. @@ -575,7 +575,7 @@ params: * "custom": Write a custom value, which resuls in UNPREDICTABLE schema: type: string - enum: ['always zero', 'custom'] + enum: ["always zero", "custom"] TINST_VALUE_ON_SCALL: description: | Value written into htinst/mtinst on a SCall exception from VU/VS-mode. @@ -585,7 +585,7 @@ params: * "custom": Write a custom value, which resuls in UNPREDICTABLE schema: type: string - enum: ['always zero', 'custom'] + enum: ["always zero", "custom"] TINST_VALUE_ON_MCALL: description: | Value written into htinst/mtinst on a MCall exception from VU/VS-mode. @@ -595,7 +595,7 @@ params: * "custom": Write a custom value, which resuls in UNPREDICTABLE schema: type: string - enum: ['always zero', 'custom'] + enum: ["always zero", "custom"] TINST_VALUE_ON_VSCALL: description: | Value written into htinst/mtinst on a VSCall exception from VU/VS-mode. @@ -605,7 +605,7 @@ params: * "custom": Write a custom value, which resuls in UNPREDICTABLE schema: type: string - enum: ['always zero', 'custom'] + enum: ["always zero", "custom"] TINST_VALUE_ON_LOAD_PAGE_FAULT: description: | Value written into htinst/mtinst on a LoadPageFault exception from VU/VS-mode. @@ -616,7 +616,7 @@ params: * "custom": Write a custom value, which resuls in UNPREDICTABLE schema: type: string - enum: ['always zero', 'always transformed standard instruction', 'custom'] + enum: ["always zero", "always transformed standard instruction", "custom"] TINST_VALUE_ON_STORE_AMO_PAGE_FAULT: description: | Value written into htinst/mtinst on a StoreAmoPageFault exception from VU/VS-mode. @@ -627,7 +627,7 @@ params: * "custom": Write a custom value, which resuls in UNPREDICTABLE schema: type: string - enum: ['always zero', 'always transformed standard instruction', 'custom'] + enum: ["always zero", "always transformed standard instruction", "custom"] TRAP_ON_ECALL_FROM_VS: description: | Whether or not an ECALL-from-VS-mode causes a synchronous exception. diff --git a/arch/ext/I.yaml b/arch/ext/I.yaml index 31a0e9099b..a7d919782f 100644 --- a/arch/ext/I.yaml +++ b/arch/ext/I.yaml @@ -6,10 +6,10 @@ name: I type: unprivileged long_name: Base integer ISA (RV32I or RV64I) versions: -- version: "2.1.0" - state: ratified - ratification_date: 2019-06 - changes: - - ratified RVWMO memory model and exclusion of FENCE.I, counters, and CSR instructions that were in previous base ISA + - version: "2.1.0" + state: ratified + ratification_date: 2019-06 + changes: + - ratified RVWMO memory model and exclusion of FENCE.I, counters, and CSR instructions that were in previous base ISA description: | Base integer instructions -- TODO diff --git a/arch/ext/M.yaml b/arch/ext/M.yaml index 25f3af18b4..5c5b3dff59 100644 --- a/arch/ext/M.yaml +++ b/arch/ext/M.yaml @@ -6,9 +6,9 @@ name: M type: unprivileged long_name: Integer multiply and divide instructions versions: -- version: "2.0.0" - state: ratified - ratification_date: 2019-12 + - version: "2.0.0" + state: ratified + ratification_date: 2019-12 description: | This chapter describes the standard integer multiplication and division instruction extension, which is named `M` and contains instructions diff --git a/arch/ext/MockExt.yaml b/arch/ext/MockExt.yaml index 57cc560d41..594bfbd4a7 100644 --- a/arch/ext/MockExt.yaml +++ b/arch/ext/MockExt.yaml @@ -7,11 +7,11 @@ type: privileged long_name: Mock Extension (for testing database) description: This is just for testing versions: -- version: "0.9.9" - state: development -- version: "1.0.0" - state: ratified - ratification_date: 2024-04 + - version: "0.9.9" + state: development + - version: "1.0.0" + state: ratified + ratification_date: 2024-04 params: MOCK_ENUM_2_INTS: description: foo @@ -148,8 +148,8 @@ params: schema: type: array items: - - const: false - - const: false + - const: false + - const: false additionalItems: type: boolean maxItems: 8 diff --git a/arch/ext/S.yaml b/arch/ext/S.yaml index 34e33bc920..d7fecf677a 100644 --- a/arch/ext/S.yaml +++ b/arch/ext/S.yaml @@ -6,12 +6,12 @@ name: S type: privileged long_name: Supervisor mode versions: -- version: "1.12.0" - state: ratified - ratification_date: 2021-12 - requires: - name: U - version: "= 1.12.0" + - version: "1.12.0" + state: ratified + ratification_date: 2021-12 + requires: + name: U + version: "= 1.12.0" description: | This chapter describes the RISC-V supervisor-level architecture, which contains a common core that is used with various supervisor-level @@ -207,15 +207,13 @@ params: Whether or not `stvec.MODE` supports Direct (0). schema: type: boolean - extra_validation: - assert STVEC_MODE_DIRECT || STVEC_MODE_VECTORED + extra_validation: assert STVEC_MODE_DIRECT || STVEC_MODE_VECTORED STVEC_MODE_VECTORED: description: | Whether or not `stvec.MODE` supports Vectored (1). schema: type: boolean - extra_validation: - assert STVEC_MODE_DIRECT || STVEC_MODE_VECTORED + extra_validation: assert STVEC_MODE_DIRECT || STVEC_MODE_VECTORED SATP_MODE_BARE: description: | Whether or not satp.MODE == Bare is supported. @@ -245,8 +243,7 @@ params: schema: type: boolean default: false - extra_validation: - assert TRAP_ON_SFENCE_VMA_WHEN_SATP_MODE_IS_READ_ONLY == false if ext?(:Sv32) || ext?(:Sv39) || ext?(:Sv48) || ext?(:Sv57) + extra_validation: assert TRAP_ON_SFENCE_VMA_WHEN_SATP_MODE_IS_READ_ONLY == false if ext?(:Sv32) || ext?(:Sv39) || ext?(:Sv48) || ext?(:Sv57) MSTATUS_FS_WRITEABLE: description: | When `S` is enabled but `F` is not, mstatus.FS is optionally writeable. @@ -254,8 +251,7 @@ params: This parameter only has an effect when both S and F mode are disabled. schema: type: boolean - extra_validation: - assert MSTATUS_FS_WRITEABLE == true if ext?(:F) + extra_validation: assert MSTATUS_FS_WRITEABLE == true if ext?(:F) MSTATUS_VS_WRITEABLE: description: | When `S` is enabled but `V` is not, mstatus.VS is optionally writeable. @@ -263,8 +259,7 @@ params: This parameter only has an effect when both S and V mode are disabled. schema: type: boolean - extra_validation: - assert MSTATUS_VS_WRITEABLE == true if ext?(:V) + extra_validation: assert MSTATUS_VS_WRITEABLE == true if ext?(:V) MSTATUS_FS_LEGAL_VALUES: description: | The set of values that mstatus.FS will accept from a software write. @@ -272,7 +267,7 @@ params: type: array items: type: integer - enum: [0,1,2,3] + enum: [0, 1, 2, 3] maxItems: 4 uniqueItems: true also_defined_in: F @@ -285,7 +280,7 @@ params: type: array items: type: integer - enum: [0,1,2,3] + enum: [0, 1, 2, 3] maxItems: 4 uniqueItems: true also_defined_in: V diff --git a/arch/ext/Sm.yaml b/arch/ext/Sm.yaml index fdd3b5d35d..db631b92f0 100644 --- a/arch/ext/Sm.yaml +++ b/arch/ext/Sm.yaml @@ -6,90 +6,90 @@ name: Sm type: privileged long_name: Machine mode versions: -- version: "1.11.0" - state: ratified - ratification_date: 2019-12 - changes: - - Moved Machine spec to *Ratified* status. - - Improvements to the description and commentary. - - Specified which interrupt sources are reserved for standard use. - - Allocated some synchronous exception causes for custom use. - - Specified the priority ordering of synchronous exceptions. - - Added specification that xRET instructions may, but are not required - to, clear LR reservations if A extension present. - - Made the `mstatus`.MPP field *WARL*, rather than *WLRL*. - - Made the unused `__x__ip` fields *WPRI*, rather than *WIRI*. - - Made the unused `misa` fields *WARL*, rather than *WIRI*. - - Rectified an editing error that misdescribed the mechanism by which - `mstatus.__x__IE` is written upon an exception. - - Described scheme for emulating misaligned AMOs. - - Specified the behavior of the `misa` and `__x__epc` registers in systems - with variable IALIGN. - - Specified the behavior of writing self-contradictory values to the - `misa` register. - - Specified contents of CSRs across XLEN modification. - - Moved PLIC chapter into its own document. -- version: "1.12.0" - state: ratified - ratification_date: 2021-12 - changes: - - Changed MRET to clear `mstatus`.MPRV when leaving M-mode. - - Relaxed I/O regions have been specified to follow RVWMO. The previous - specification implied that PPO rules other than fences and - acquire/release annotations did not apply. - - Constrained the LR/SC reservation set size and shape when using - page-based virtual memory. - - PMP changes require an SFENCE.VMA on any hart that implements - page-based virtual memory, even if VM is not currently enabled. - - Removed the N extension. - - Defined the mandatory RV32-only CSR `mstatush`, which contains most of - the same fields as the upper 32 bits of RV64's `mstatus`. - - Defined the mandatory CSR `mconfigptr`, which if nonzero contains the - address of a configuration data structure. - - Defined optional `mseccfg` and `mseccfgh` CSRs, which control the - machine's security configuration. - - Defined `menvcfg` CSR (and RV32-only `menvcfgh`), which control various characteristics - of the execution environment. - - Designated part of SYSTEM major opcode for custom use. - - Permitted the unconditional delegation of less-privileged interrupts. - - Added optional big-endian and bi-endian support. - - Made priority of load/store/AMO address-misaligned exceptions - implementation-defined relative to load/store/AMO page-fault and - access-fault exceptions. - - Software breakpoint exceptions are permitted to write either 0 or the - `pc` to `__x__tval`. - - Specified relaxed constraints for implicit reads of non-idempotent regions. -- version: "1.13.0" - state: frozen - ratification_date: 2023-12 - changes: - - Redefined `misa`.MXL to be read-only, making MXLEN a constant. - - Defined the `misa`.B field to reflect that the B extension has been - implemented. - - Defined the `misa`.V field to reflect that the V extension has been - implemented. - - Defined the RV32-only `medelegh` CSR. - - Defined the misaligned atomicity granule PMA, superseding the proposed Zam - extension. - - Defined hardware error and software check exception codes. - - Specified synchronization requirements when changing the PBMTE fields - in `menvcfg` and `henvcfg`. - - Exposed count-overflow interrupts to VS-mode via the Shlcofideleg extension. - - Relaxed behavior of some HINTs when MXLEN > XLEN. - - Transliterated the document from LaTeX into AsciiDoc. - - Included all ratified extensions through March 2024. - - Clarified that "platform- or custom-use" interrupts are actually - "platform-use interrupts", where the platform can choose to make some custom. - - Clarified semantics of explicit accesses to CSRs wider than XLEN bits. - - Clarified that MXLEN≥SXLEN. - - Clarified that WFI is not a HINT instruction. - - Clarified that, for a given exception cause, `__x__tval` might sometimes - be set to a nonzero value but sometimes not. - - Clarified exception behavior of unimplemented or inaccessible CSRs. - - Replaced the concept of vacant memory regions with inaccessible memory or I/O regions. - - Clarified that timer and count-overflow interrupts' arrival in - interrupt-pending registers is not immediate. - - Clarified that MXR affects only explicit memory accesses. + - version: "1.11.0" + state: ratified + ratification_date: 2019-12 + changes: + - Moved Machine spec to *Ratified* status. + - Improvements to the description and commentary. + - Specified which interrupt sources are reserved for standard use. + - Allocated some synchronous exception causes for custom use. + - Specified the priority ordering of synchronous exceptions. + - Added specification that xRET instructions may, but are not required + to, clear LR reservations if A extension present. + - Made the `mstatus`.MPP field *WARL*, rather than *WLRL*. + - Made the unused `__x__ip` fields *WPRI*, rather than *WIRI*. + - Made the unused `misa` fields *WARL*, rather than *WIRI*. + - Rectified an editing error that misdescribed the mechanism by which + `mstatus.__x__IE` is written upon an exception. + - Described scheme for emulating misaligned AMOs. + - Specified the behavior of the `misa` and `__x__epc` registers in systems + with variable IALIGN. + - Specified the behavior of writing self-contradictory values to the + `misa` register. + - Specified contents of CSRs across XLEN modification. + - Moved PLIC chapter into its own document. + - version: "1.12.0" + state: ratified + ratification_date: 2021-12 + changes: + - Changed MRET to clear `mstatus`.MPRV when leaving M-mode. + - Relaxed I/O regions have been specified to follow RVWMO. The previous + specification implied that PPO rules other than fences and + acquire/release annotations did not apply. + - Constrained the LR/SC reservation set size and shape when using + page-based virtual memory. + - PMP changes require an SFENCE.VMA on any hart that implements + page-based virtual memory, even if VM is not currently enabled. + - Removed the N extension. + - Defined the mandatory RV32-only CSR `mstatush`, which contains most of + the same fields as the upper 32 bits of RV64's `mstatus`. + - Defined the mandatory CSR `mconfigptr`, which if nonzero contains the + address of a configuration data structure. + - Defined optional `mseccfg` and `mseccfgh` CSRs, which control the + machine's security configuration. + - Defined `menvcfg` CSR (and RV32-only `menvcfgh`), which control various characteristics + of the execution environment. + - Designated part of SYSTEM major opcode for custom use. + - Permitted the unconditional delegation of less-privileged interrupts. + - Added optional big-endian and bi-endian support. + - Made priority of load/store/AMO address-misaligned exceptions + implementation-defined relative to load/store/AMO page-fault and + access-fault exceptions. + - Software breakpoint exceptions are permitted to write either 0 or the + `pc` to `__x__tval`. + - Specified relaxed constraints for implicit reads of non-idempotent regions. + - version: "1.13.0" + state: frozen + ratification_date: 2023-12 + changes: + - Redefined `misa`.MXL to be read-only, making MXLEN a constant. + - Defined the `misa`.B field to reflect that the B extension has been + implemented. + - Defined the `misa`.V field to reflect that the V extension has been + implemented. + - Defined the RV32-only `medelegh` CSR. + - Defined the misaligned atomicity granule PMA, superseding the proposed Zam + extension. + - Defined hardware error and software check exception codes. + - Specified synchronization requirements when changing the PBMTE fields + in `menvcfg` and `henvcfg`. + - Exposed count-overflow interrupts to VS-mode via the Shlcofideleg extension. + - Relaxed behavior of some HINTs when MXLEN > XLEN. + - Transliterated the document from LaTeX into AsciiDoc. + - Included all ratified extensions through March 2024. + - Clarified that "platform- or custom-use" interrupts are actually + "platform-use interrupts", where the platform can choose to make some custom. + - Clarified semantics of explicit accesses to CSRs wider than XLEN bits. + - Clarified that MXLEN≥SXLEN. + - Clarified that WFI is not a HINT instruction. + - Clarified that, for a given exception cause, `__x__tval` might sometimes + be set to a nonzero value but sometimes not. + - Clarified exception behavior of unimplemented or inaccessible CSRs. + - Replaced the concept of vacant memory regions with inaccessible memory or I/O regions. + - Clarified that timer and count-overflow interrupts' arrival in + interrupt-pending registers is not immediate. + - Clarified that MXR affects only explicit memory accesses. description: | This chapter describes the machine-level operations available in machine-mode (M-mode), which is the highest privilege mode in a RISC-V hart. M-mode is used for low-level access to a hardware @@ -101,72 +101,72 @@ description: | contains a common core that is used with various supervisor-level address translation and protection schemes. interrupt_codes: -- num: 1 - name: Supervisor software interrupt - var: SupervisorSoftware -- num: 3 - name: Machine software interrupt - var: MachineSoftware -- num: 5 - name: Supervisor timer interrupt - var: SupervisorTimer -- num: 7 - name: Machine timer interrupt - var: MachineTimer -- num: 9 - name: Supervisor external interrupt - var: SupervisorExternal -- num: 11 - name: Machine external interrupt - var: MachineExternal + - num: 1 + name: Supervisor software interrupt + var: SupervisorSoftware + - num: 3 + name: Machine software interrupt + var: MachineSoftware + - num: 5 + name: Supervisor timer interrupt + var: SupervisorTimer + - num: 7 + name: Machine timer interrupt + var: MachineTimer + - num: 9 + name: Supervisor external interrupt + var: SupervisorExternal + - num: 11 + name: Machine external interrupt + var: MachineExternal exception_codes: -- num: 0 - name: Instruction address misaligned - var: InstructionAddressMisaligned -- num: 1 - name: Instruction access fault - var: InstructionAccessFault -- num: 2 - name: Illegal instruction - var: IllegalInstruction -- num: 3 - name: Breakpoint - var: Breakpoint -- num: 4 - name: Load address misaligned - var: LoadAddressMisaligned -- num: 5 - name: Load access fault - var: LoadAccessFault -- num: 6 - name: Store/AMO address misaligned - var: StoreAmoAddressMisaligned -- num: 7 - name: Store/AMO access fault - var: StoreAmoAccessFault -- num: 8 - name: Environment call from <%- if ext?(:H) -%>V<%- end -%>U-mode - var: Ucall -- num: 9 - name: Environment call from <%- if ext?(:H) -%>H<%- end -%>S-mode - var: Scall -- num: 11 - name: Environment call from M-mode - var: Mcall -- num: 12 - name: Instruction page fault - var: InstructionPageFault -- num: 13 - name: Load page fault - var: LoadPageFault -- num: 15 - name: Store/AMO page fault - var: StoreAmoPageFault -- num: 18 - name: Software Check - var: SoftwareCheck - when: - version: ">= 1.13.0" + - num: 0 + name: Instruction address misaligned + var: InstructionAddressMisaligned + - num: 1 + name: Instruction access fault + var: InstructionAccessFault + - num: 2 + name: Illegal instruction + var: IllegalInstruction + - num: 3 + name: Breakpoint + var: Breakpoint + - num: 4 + name: Load address misaligned + var: LoadAddressMisaligned + - num: 5 + name: Load access fault + var: LoadAccessFault + - num: 6 + name: Store/AMO address misaligned + var: StoreAmoAddressMisaligned + - num: 7 + name: Store/AMO access fault + var: StoreAmoAccessFault + - num: 8 + name: Environment call from <%- if ext?(:H) -%>V<%- end -%>U-mode + var: Ucall + - num: 9 + name: Environment call from <%- if ext?(:H) -%>H<%- end -%>S-mode + var: Scall + - num: 11 + name: Environment call from M-mode + var: Mcall + - num: 12 + name: Instruction page fault + var: InstructionPageFault + - num: 13 + name: Load page fault + var: LoadPageFault + - num: 15 + name: Store/AMO page fault + var: StoreAmoPageFault + - num: 18 + name: Software Check + var: SoftwareCheck + when: + version: ">= 1.13.0" params: XLEN: description: | diff --git a/arch/ext/Smaia.yaml b/arch/ext/Smaia.yaml index 5e696ae409..86ec96e02b 100644 --- a/arch/ext/Smaia.yaml +++ b/arch/ext/Smaia.yaml @@ -7,7 +7,7 @@ long_name: Advanced Interrupt Architecture, M-mode extension description: Advanced Interrupt Architecture, M-mode extension type: privileged versions: -- version: "1.0.0" - state: ratified - ratification_date: 2023-06 - url: https://github.com/riscv/riscv-aia/releases/download/1.0/riscv-interrupts-1.0.pdf + - version: "1.0.0" + state: ratified + ratification_date: 2023-06 + url: https://github.com/riscv/riscv-aia/releases/download/1.0/riscv-interrupts-1.0.pdf diff --git a/arch/ext/Smcdeleg.yaml b/arch/ext/Smcdeleg.yaml index 5979178c8a..a1b603acb1 100644 --- a/arch/ext/Smcdeleg.yaml +++ b/arch/ext/Smcdeleg.yaml @@ -14,24 +14,24 @@ doc_license: name: Creative Commons Attribution 4.0 International License (CC-BY 4.0) url: https://creativecommons.org/licenses/by/4.0/ versions: -- version: "1.0.0" - state: ratified - ratification_date: null - repositories: - - url: https://github.com/riscvarchive/riscv-smcdeleg-ssccfg - url: https://github.com/riscvarchive/riscv-smcdeleg-ssccfg/releases/download/v1.0.0/riscv-smcdeleg-ssccfg-v1.0.0.pdf - contributors: - - name: Beeman Strong - email: beeman@rivosinc.com - company: Rivos, Inc. - - name: Atish Patra - email: atishp@rivosinc.com - company: Rivos, Inc. - - name: Allen Baum - email: allen.baum@esperantotech.com - company: Rivos, Inc. - - name: Greg Favor - email: gfavor@ventanamicro.com - company: Ventana Microsystems - - name: John Hauser - email: jh.riscv@jhauser.us + - version: "1.0.0" + state: ratified + ratification_date: null + repositories: + - url: https://github.com/riscvarchive/riscv-smcdeleg-ssccfg + url: https://github.com/riscvarchive/riscv-smcdeleg-ssccfg/releases/download/v1.0.0/riscv-smcdeleg-ssccfg-v1.0.0.pdf + contributors: + - name: Beeman Strong + email: beeman@rivosinc.com + company: Rivos, Inc. + - name: Atish Patra + email: atishp@rivosinc.com + company: Rivos, Inc. + - name: Allen Baum + email: allen.baum@esperantotech.com + company: Rivos, Inc. + - name: Greg Favor + email: gfavor@ventanamicro.com + company: Ventana Microsystems + - name: John Hauser + email: jh.riscv@jhauser.us diff --git a/arch/ext/Smcntrpmf.yaml b/arch/ext/Smcntrpmf.yaml index 174269df0d..a5c5fb5e9f 100644 --- a/arch/ext/Smcntrpmf.yaml +++ b/arch/ext/Smcntrpmf.yaml @@ -7,7 +7,7 @@ long_name: Cycle and Instret Privilege Mode Filtering description: Cycle and Instret Privilege Mode Filtering type: privileged versions: -- version: "1.0.0" - state: ratified - ratification_date: 2023-08 - url: https://github.com/riscv/riscv-smcntrpmf/releases/download/v1.0_rc4-frozen/riscv-smcntrpmf-v1.0_rc4.pdf + - version: "1.0.0" + state: ratified + ratification_date: 2023-08 + url: https://github.com/riscv/riscv-smcntrpmf/releases/download/v1.0_rc4-frozen/riscv-smcntrpmf-v1.0_rc4.pdf diff --git a/arch/ext/Smhpm.yaml b/arch/ext/Smhpm.yaml index fa2d63df3c..6b31da57af 100644 --- a/arch/ext/Smhpm.yaml +++ b/arch/ext/Smhpm.yaml @@ -7,23 +7,23 @@ long_name: M-mode programmable hardware performance counters description: M-mode programmable hardware performance counters type: privileged versions: -- version: "1.11.0" - state: ratified - ratification_date: 2019-12 - changes: - - Defined the `mcountinhibit` CSR, which stops performance counters from - incrementing to reduce energy consumption. -- version: "1.12.0" - state: ratified - ratification_date: 2021-12 - changes: - - PMP changes require an SFENCE.VMA on any hart that implements - page-based virtual memory, even if VM is not currently enabled. - - PMP reset values are now platform-defined. - - An additional 48 optional PMP registers have been defined. -- version: "1.13.0" - state: frozen - ratification_date: 2023-12 + - version: "1.11.0" + state: ratified + ratification_date: 2019-12 + changes: + - Defined the `mcountinhibit` CSR, which stops performance counters from + incrementing to reduce energy consumption. + - version: "1.12.0" + state: ratified + ratification_date: 2021-12 + changes: + - PMP changes require an SFENCE.VMA on any hart that implements + page-based virtual memory, even if VM is not currently enabled. + - PMP reset values are now platform-defined. + - An additional 48 optional PMP registers have been defined. + - version: "1.13.0" + state: frozen + ratification_date: 2023-12 params: HPM_COUNTER_EN: description: | @@ -36,9 +36,9 @@ params: schema: type: array items: - - const: false - - const: false - - const: false + - const: false + - const: false + - const: false additionalItems: type: boolean maxItems: 32 @@ -66,9 +66,9 @@ params: schema: type: array items: - - type: boolean - - const: false - - type: boolean + - type: boolean + - const: false + - type: boolean additionalItems: type: boolean maxItems: 32 diff --git a/arch/ext/Smpmp.yaml b/arch/ext/Smpmp.yaml index 05e0ec6548..5884987c8c 100644 --- a/arch/ext/Smpmp.yaml +++ b/arch/ext/Smpmp.yaml @@ -6,23 +6,23 @@ name: Smpmp type: privileged long_name: Physical Memory Protection versions: -- version: "1.11.0" - state: ratified - ratification_date: 2019-12 - changes: - - Made the unused `pmpaddr` and `pmpcfg` fields *WARL*, rather than *WIRI*. - - Specified semantics for PMP regions coarser than four bytes. -- version: "1.12.0" - state: ratified - ratification_date: 2021-12 - changes: - - PMP changes require an SFENCE.VMA on any hart that implements - page-based virtual memory, even if VM is not currently enabled. - - PMP reset values are now platform-defined. - - An additional 48 optional PMP registers have been defined. -- version: "1.13.0" - state: frozen - ratification_date: 2023-12 + - version: "1.11.0" + state: ratified + ratification_date: 2019-12 + changes: + - Made the unused `pmpaddr` and `pmpcfg` fields *WARL*, rather than *WIRI*. + - Specified semantics for PMP regions coarser than four bytes. + - version: "1.12.0" + state: ratified + ratification_date: 2021-12 + changes: + - PMP changes require an SFENCE.VMA on any hart that implements + page-based virtual memory, even if VM is not currently enabled. + - PMP reset values are now platform-defined. + - An additional 48 optional PMP registers have been defined. + - version: "1.13.0" + state: frozen + ratification_date: 2023-12 description: | To support secure processing and contain faults, it is desirable to limit the physical addresses accessible by software running on a hart. The optional PMP (Physical Memory Protection) unit diff --git a/arch/ext/Ssaia.yaml b/arch/ext/Ssaia.yaml index 09bdfe48d8..028adb0fac 100644 --- a/arch/ext/Ssaia.yaml +++ b/arch/ext/Ssaia.yaml @@ -7,10 +7,10 @@ long_name: Advanced Interrupt Architecture, S-mode extension description: Advanced Interrupt Architecture, S-mode extension type: privileged versions: -- version: "1.0.0" - state: ratified - ratification_date: 2023-06 - url: https://github.com/riscv/riscv-aia/releases/download/1.0/riscv-interrupts-1.0.pdf - requires: - name: S - version: ">= 1.12" + - version: "1.0.0" + state: ratified + ratification_date: 2023-06 + url: https://github.com/riscv/riscv-aia/releases/download/1.0/riscv-interrupts-1.0.pdf + requires: + name: S + version: ">= 1.12" diff --git a/arch/ext/Ssccfg.yaml b/arch/ext/Ssccfg.yaml index b19973dbc8..d6425cc796 100644 --- a/arch/ext/Ssccfg.yaml +++ b/arch/ext/Ssccfg.yaml @@ -7,7 +7,7 @@ long_name: Supervisor-mode counter configuration description: Supervisor-mode counter configuration type: privileged versions: -- version: "1.0.0" - state: ratified - ratification_date: null - url: https://docs.google.com/document/d/1s-GeH5XpHBLzbQZucA8DPA7vvF7Xvf_nrPbrU2YLBcE/edit#heading=h.yyrgtolcaczx + - version: "1.0.0" + state: ratified + ratification_date: null + url: https://docs.google.com/document/d/1s-GeH5XpHBLzbQZucA8DPA7vvF7Xvf_nrPbrU2YLBcE/edit#heading=h.yyrgtolcaczx diff --git a/arch/ext/Ssccptr.yaml b/arch/ext/Ssccptr.yaml index 247dc2b079..03a8ee5a85 100644 --- a/arch/ext/Ssccptr.yaml +++ b/arch/ext/Ssccptr.yaml @@ -11,13 +11,13 @@ description: | This extension was ratified with the RVA20 profiles. type: privileged versions: -- version: "1.0.0" - state: ratified - ratification_date: null - url: https://github.com/riscv/riscv-profiles/releases/tag/v1.0 - repositories: - - url: https://github.com/riscv/riscv-profiles - branch: main - contributors: - - name: Krste Asanovic - company: SiFive, Inc. + - version: "1.0.0" + state: ratified + ratification_date: null + url: https://github.com/riscv/riscv-profiles/releases/tag/v1.0 + repositories: + - url: https://github.com/riscv/riscv-profiles + branch: main + contributors: + - name: Krste Asanovic + company: SiFive, Inc. diff --git a/arch/ext/Sscofpmf.yaml b/arch/ext/Sscofpmf.yaml index 17fc12c9eb..de4584f09d 100644 --- a/arch/ext/Sscofpmf.yaml +++ b/arch/ext/Sscofpmf.yaml @@ -7,9 +7,9 @@ long_name: Counter Overflow and Privilege Mode Filtering description: Counter Overflow and Privilege Mode Filtering type: privileged versions: -- version: "1.0.0" - state: ratified - ratification_date: 2023-08 - url: https://drive.google.com/file/d/1KcjgbLM5L1ZKY8934aJl8aQwGlMz6Cbo/view?usp=drive_link - requires: - name: Smhpm + - version: "1.0.0" + state: ratified + ratification_date: 2023-08 + url: https://drive.google.com/file/d/1KcjgbLM5L1ZKY8934aJl8aQwGlMz6Cbo/view?usp=drive_link + requires: + name: Smhpm diff --git a/arch/ext/Sscounterenw.yaml b/arch/ext/Sscounterenw.yaml index 97f71aa812..b6a4b997a2 100644 --- a/arch/ext/Sscounterenw.yaml +++ b/arch/ext/Sscounterenw.yaml @@ -11,11 +11,11 @@ description: | This extension was ratified with the RVA22 profiles. type: privileged versions: -- version: "1.0.0" - state: ratified - ratification_date: 2023-08 - url: https://drive.google.com/file/d/1KcjgbLM5L1ZKY8934aJl8aQwGlMz6Cbo/view?usp=drive_link - param_constraints: - SCOUNTENABLE_EN: - extra_validation: | - HPM_COUNTER_EN.each_with_index { |hpm_exists, idx| assert(!hpm_exists || SCOUNTENABLE_EN[idx]) } + - version: "1.0.0" + state: ratified + ratification_date: 2023-08 + url: https://drive.google.com/file/d/1KcjgbLM5L1ZKY8934aJl8aQwGlMz6Cbo/view?usp=drive_link + param_constraints: + SCOUNTENABLE_EN: + extra_validation: | + HPM_COUNTER_EN.each_with_index { |hpm_exists, idx| assert(!hpm_exists || SCOUNTENABLE_EN[idx]) } diff --git a/arch/ext/Sstc.yaml b/arch/ext/Sstc.yaml index 435287d68e..03f2b76e75 100644 --- a/arch/ext/Sstc.yaml +++ b/arch/ext/Sstc.yaml @@ -7,7 +7,7 @@ long_name: Superivisor mode timer interrupts description: Superivisor mode timer interrupts type: privileged versions: -- version: "0.9.0" - state: ratified - ratification_date: null - url: https://drive.google.com/file/d/1m84Re2yK8m_vbW7TspvevCDR82MOBaSX/view?usp=drive_link + - version: "0.9.0" + state: ratified + ratification_date: null + url: https://drive.google.com/file/d/1m84Re2yK8m_vbW7TspvevCDR82MOBaSX/view?usp=drive_link diff --git a/arch/ext/Sstvala.yaml b/arch/ext/Sstvala.yaml index 98e5fce73e..66c8a101da 100644 --- a/arch/ext/Sstvala.yaml +++ b/arch/ext/Sstvala.yaml @@ -17,47 +17,47 @@ description: | This extension was ratified with the RVA20 profiles. type: privileged versions: -- version: "1.0.0" - state: ratified - ratification_date: null - url: https://github.com/riscv/riscv-profiles/releases/tag/v1.0 - repositories: - - url: https://github.com/riscv/riscv-profiles - branch: main - contributors: - - name: Krste Asanovic - company: SiFive, Inc. - param_constraints: - REPORT_VA_IN_STVAL_ON_BREAKPOINT: - schema: - const: true - REPORT_VA_IN_STVAL_ON_INSTRUCTION_ACCESS_FAULT: - schema: - const: true - REPORT_VA_IN_STVAL_ON_LOAD_ACCESS_FAULT: - schema: - const: true - REPORT_VA_IN_STVAL_ON_STORE_AMO_ACCESS_FAULT: - schema: - const: true - REPORT_VA_IN_STVAL_ON_INSTRUCTION_PAGE_FAULT: - schema: - const: true - REPORT_VA_IN_STVAL_ON_LOAD_PAGE_FAULT: - schema: - const: true - REPORT_VA_IN_STVAL_ON_STORE_AMO_PAGE_FAULT: - schema: - const: true - REPORT_VA_IN_STVAL_ON_INSTRUCTION_MISALIGNED: - schema: - const: true - REPORT_VA_IN_STVAL_ON_LOAD_MISALIGNED: - schema: - const: true - REPORT_VA_IN_STVAL_ON_STORE_AMO_MISALIGNED: - schema: - const: true - REPORT_ENCODING_IN_STVAL_ON_ILLEGAL_INSTRUCTION: - schema: - const: true + - version: "1.0.0" + state: ratified + ratification_date: null + url: https://github.com/riscv/riscv-profiles/releases/tag/v1.0 + repositories: + - url: https://github.com/riscv/riscv-profiles + branch: main + contributors: + - name: Krste Asanovic + company: SiFive, Inc. + param_constraints: + REPORT_VA_IN_STVAL_ON_BREAKPOINT: + schema: + const: true + REPORT_VA_IN_STVAL_ON_INSTRUCTION_ACCESS_FAULT: + schema: + const: true + REPORT_VA_IN_STVAL_ON_LOAD_ACCESS_FAULT: + schema: + const: true + REPORT_VA_IN_STVAL_ON_STORE_AMO_ACCESS_FAULT: + schema: + const: true + REPORT_VA_IN_STVAL_ON_INSTRUCTION_PAGE_FAULT: + schema: + const: true + REPORT_VA_IN_STVAL_ON_LOAD_PAGE_FAULT: + schema: + const: true + REPORT_VA_IN_STVAL_ON_STORE_AMO_PAGE_FAULT: + schema: + const: true + REPORT_VA_IN_STVAL_ON_INSTRUCTION_MISALIGNED: + schema: + const: true + REPORT_VA_IN_STVAL_ON_LOAD_MISALIGNED: + schema: + const: true + REPORT_VA_IN_STVAL_ON_STORE_AMO_MISALIGNED: + schema: + const: true + REPORT_ENCODING_IN_STVAL_ON_ILLEGAL_INSTRUCTION: + schema: + const: true diff --git a/arch/ext/Sstvecd.yaml b/arch/ext/Sstvecd.yaml index cbe35c0c14..c2a899c2b6 100644 --- a/arch/ext/Sstvecd.yaml +++ b/arch/ext/Sstvecd.yaml @@ -10,17 +10,17 @@ description: | four-byte-aligned address. type: privileged versions: -- version: "1.0.0" - state: ratified - ratification_date: null - url: https://github.com/riscv/riscv-profiles/releases/tag/v1.0 - repositories: - - url: https://github.com/riscv/riscv-profiles - branch: main - contributors: - - name: Krste Asanovic - company: SiFive, Inc. - param_constraints: - STVEC_MODE_DIRECT: - schema: - const: true + - version: "1.0.0" + state: ratified + ratification_date: null + url: https://github.com/riscv/riscv-profiles/releases/tag/v1.0 + repositories: + - url: https://github.com/riscv/riscv-profiles + branch: main + contributors: + - name: Krste Asanovic + company: SiFive, Inc. + param_constraints: + STVEC_MODE_DIRECT: + schema: + const: true diff --git a/arch/ext/Sv32.yaml b/arch/ext/Sv32.yaml index 03ab2a2b19..e638dc9380 100644 --- a/arch/ext/Sv32.yaml +++ b/arch/ext/Sv32.yaml @@ -7,7 +7,7 @@ long_name: 32-bit virtual address translation (3 level) description: 32-bit virtual address translation (3 level) type: privileged versions: -- version: "1.12.0" - state: ratified - ratification_date: unknown - url: https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf + - version: "1.12.0" + state: ratified + ratification_date: unknown + url: https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf diff --git a/arch/ext/Sv39.yaml b/arch/ext/Sv39.yaml index 35a1d74f36..bd54871df4 100644 --- a/arch/ext/Sv39.yaml +++ b/arch/ext/Sv39.yaml @@ -7,7 +7,7 @@ long_name: 39-bit virtual address translation (3 level) description: 39-bit virtual address translation (3 level) type: privileged versions: -- version: "1.12.0" - state: ratified - ratification_date: unknown - url: https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf + - version: "1.12.0" + state: ratified + ratification_date: unknown + url: https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf diff --git a/arch/ext/Sv48.yaml b/arch/ext/Sv48.yaml index ac56935db7..40b6416f6c 100644 --- a/arch/ext/Sv48.yaml +++ b/arch/ext/Sv48.yaml @@ -7,10 +7,10 @@ long_name: 48-bit virtual address translation (4 level) description: 48-bit virtual address translation (4 level) type: privileged versions: -- version: "1.12.0" - state: ratified - ratification_date: unknown - url: https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf - requires: - name: Sv39 - version: ">= 1.12" + - version: "1.12.0" + state: ratified + ratification_date: unknown + url: https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf + requires: + name: Sv39 + version: ">= 1.12" diff --git a/arch/ext/Sv57.yaml b/arch/ext/Sv57.yaml index 49b4447d5e..62f1d82a15 100644 --- a/arch/ext/Sv57.yaml +++ b/arch/ext/Sv57.yaml @@ -7,10 +7,10 @@ long_name: 57-bit virtual address translation (5 level) description: 57-bit virtual address translation (5 level) type: privileged versions: -- version: "1.12.0" - state: ratified - ratification_date: unknown - url: https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf - requires: - name: Sv48 - version: ">= 1.12" + - version: "1.12.0" + state: ratified + ratification_date: unknown + url: https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf + requires: + name: Sv48 + version: ">= 1.12" diff --git a/arch/ext/Svade.yaml b/arch/ext/Svade.yaml index 8dcbf48575..5ea7c4bd98 100644 --- a/arch/ext/Svade.yaml +++ b/arch/ext/Svade.yaml @@ -10,31 +10,31 @@ description: | during a page walk. Rather, encountering a PTE with the A bit clear or the D bit clear when an operation is a write will cause a Page Fault. versions: -- version: "1.0.0" - state: ratified - ratification_date: 2023-11 - url: https://github.com/riscvarchive/riscv-svadu/releases/download/v1.0/riscv-svadu.pdf - repositories: - - url: https://github.com/riscvarchive/riscv-svadu - branch: main - contributors: - - name: Aaron Durbin - company: Rivos, Inc. - - name: Andrew Waterman - company: SiFive - - name: Earl Killian - company: Aril - - name: Greg Favor - company: Ventana - - name: John Ingalls - company: SiFive - - name: Ken Dockser - company: Tenstorrent - - name: Krste Asanovic - company: SiFive - - name: Paul Donahue - - name: Ved Shanbhogue - company: Rivos, Inc. + - version: "1.0.0" + state: ratified + ratification_date: 2023-11 + url: https://github.com/riscvarchive/riscv-svadu/releases/download/v1.0/riscv-svadu.pdf + repositories: + - url: https://github.com/riscvarchive/riscv-svadu + branch: main + contributors: + - name: Aaron Durbin + company: Rivos, Inc. + - name: Andrew Waterman + company: SiFive + - name: Earl Killian + company: Aril + - name: Greg Favor + company: Ventana + - name: John Ingalls + company: SiFive + - name: Ken Dockser + company: Tenstorrent + - name: Krste Asanovic + company: SiFive + - name: Paul Donahue + - name: Ved Shanbhogue + company: Rivos, Inc. conflicts: Svadu doc_license: name: Creative Commons Attribution 4.0 International License (CC-BY 4.0) diff --git a/arch/ext/Svadu.yaml b/arch/ext/Svadu.yaml index 93202f7320..d4fcbfdfab 100644 --- a/arch/ext/Svadu.yaml +++ b/arch/ext/Svadu.yaml @@ -93,31 +93,31 @@ description: | is zero, the implementation behaves as though Svadu were not implemented for VS-stage address translation. versions: -- version: "1.0.0" - state: ratified - ratification_date: 2023-11 - url: https://github.com/riscvarchive/riscv-svadu/releases/download/v1.0/riscv-svadu.pdf - repositories: - - url: https://github.com/riscvarchive/riscv-svadu - branch: main - contributors: - - name: Aaron Durbin - company: Rivos, Inc. - - name: Andrew Waterman - company: SiFive - - name: Earl Killian - company: Aril - - name: Greg Favor - company: Ventana - - name: John Ingalls - company: SiFive - - name: Ken Dockser - company: Tenstorrent - - name: Krste Asanovic - company: SiFive - - name: Paul Donahue - - name: Ved Shanbhogue - company: Rivos, Inc. + - version: "1.0.0" + state: ratified + ratification_date: 2023-11 + url: https://github.com/riscvarchive/riscv-svadu/releases/download/v1.0/riscv-svadu.pdf + repositories: + - url: https://github.com/riscvarchive/riscv-svadu + branch: main + contributors: + - name: Aaron Durbin + company: Rivos, Inc. + - name: Andrew Waterman + company: SiFive + - name: Earl Killian + company: Aril + - name: Greg Favor + company: Ventana + - name: John Ingalls + company: SiFive + - name: Ken Dockser + company: Tenstorrent + - name: Krste Asanovic + company: SiFive + - name: Paul Donahue + - name: Ved Shanbhogue + company: Rivos, Inc. conflicts: Svade doc_license: name: Creative Commons Attribution 4.0 International License (CC-BY 4.0) diff --git a/arch/ext/Svbare.yaml b/arch/ext/Svbare.yaml index afc684ac21..379238fcb8 100644 --- a/arch/ext/Svbare.yaml +++ b/arch/ext/Svbare.yaml @@ -11,12 +11,12 @@ description: | [NOTE] This extension was ratified as part of the RVA22 profile. versions: -- version: "1.0.0" - state: ratified - ratification_date: null - requires: - name: S - param_constraints: - SATP_MODE_BARE: - schema: - const: true + - version: "1.0.0" + state: ratified + ratification_date: null + requires: + name: S + param_constraints: + SATP_MODE_BARE: + schema: + const: true diff --git a/arch/ext/Svinval.yaml b/arch/ext/Svinval.yaml index 1ebb07e061..c208c0adf2 100644 --- a/arch/ext/Svinval.yaml +++ b/arch/ext/Svinval.yaml @@ -73,8 +73,8 @@ description: | `sfence.w.inval` and `sfence.inval.ir` instructions as no-ops. -- versions: -- version: "1.0.0" - state: ratified - ratification_date: 2021-11 - requires: - name: S + - version: "1.0.0" + state: ratified + ratification_date: 2021-11 + requires: + name: S diff --git a/arch/ext/Svnapot.yaml b/arch/ext/Svnapot.yaml index 240f60cf7c..d3fb8c3d51 100644 --- a/arch/ext/Svnapot.yaml +++ b/arch/ext/Svnapot.yaml @@ -168,8 +168,8 @@ description: | first step. ==== versions: -- version: "1.0.0" - state: ratified - ratification_date: 2021-11 - requires: - name: Sv39 + - version: "1.0.0" + state: ratified + ratification_date: 2021-11 + requires: + name: Sv39 diff --git a/arch/ext/Svpbmt.yaml b/arch/ext/Svpbmt.yaml index 43db85e29a..0cbc750e47 100644 --- a/arch/ext/Svpbmt.yaml +++ b/arch/ext/Svpbmt.yaml @@ -12,12 +12,12 @@ description: | This extension was ratified as part of the RVA22 profile. type: privileged versions: -- version: "1.0.0" - state: ratified - ratification_date: null - requires: - name: Sv39 - param_constraints: - SATP_MODE_BARE: - schema: - const: true + - version: "1.0.0" + state: ratified + ratification_date: null + requires: + name: Sv39 + param_constraints: + SATP_MODE_BARE: + schema: + const: true diff --git a/arch/ext/U.yaml b/arch/ext/U.yaml index a3a42d8de3..40a7a06570 100644 --- a/arch/ext/U.yaml +++ b/arch/ext/U.yaml @@ -7,9 +7,9 @@ long_name: User-level privilege mode description: User-level privilege mode type: privileged versions: -- version: "1.12.0" - state: ratified - ratification_date: 2019-12 + - version: "1.12.0" + state: ratified + ratification_date: 2019-12 params: MUTABLE_MISA_U: description: | diff --git a/arch/ext/V.yaml b/arch/ext/V.yaml index 462b12a6dd..de7b3fe6de 100644 --- a/arch/ext/V.yaml +++ b/arch/ext/V.yaml @@ -6,9 +6,9 @@ name: V type: unprivileged long_name: Variable-length vector versions: -- version: "1.0.0" - state: ratified - ratification_date: null + - version: "1.0.0" + state: ratified + ratification_date: null description: | TODO params: @@ -38,7 +38,7 @@ params: type: array items: type: integer - enum: [0,1,2,3] + enum: [0, 1, 2, 3] maxItems: 4 uniqueItems: true also_defined_in: S diff --git a/arch/ext/Za128rs.yaml b/arch/ext/Za128rs.yaml index e78da5e68f..24a2324610 100644 --- a/arch/ext/Za128rs.yaml +++ b/arch/ext/Za128rs.yaml @@ -14,13 +14,13 @@ description: | The minimum reservation set size is effectively determined by the size of atomic accesses in the A extension. versions: -- version: "1.0.0" - state: ratified - ratification_date: null - param_constraints: - LRSC_RESERVATION_STRATEGY: - schema: - oneOf: - - const: reserve exactly enough to cover the access - - const: reserve naturally-aligned 64-byte region - - const: reserve naturally-aligned 128-byte region + - version: "1.0.0" + state: ratified + ratification_date: null + param_constraints: + LRSC_RESERVATION_STRATEGY: + schema: + oneOf: + - const: reserve exactly enough to cover the access + - const: reserve naturally-aligned 64-byte region + - const: reserve naturally-aligned 128-byte region diff --git a/arch/ext/Zaamo.yaml b/arch/ext/Zaamo.yaml index 84722a5665..42966feda5 100644 --- a/arch/ext/Zaamo.yaml +++ b/arch/ext/Zaamo.yaml @@ -6,9 +6,9 @@ name: Zaamo long_name: Load-acquire/Store-release atomic instructions type: unprivileged versions: -- version: "1.0.0" - state: ratified - ratification_date: 2024-04 + - version: "1.0.0" + state: ratified + ratification_date: 2024-04 description: | The atomic memory operation (AMO) instructions perform read-modify-write operations for multiprocessor synchronization and are encoded with an diff --git a/arch/ext/Zalrsc.yaml b/arch/ext/Zalrsc.yaml index 90043522f0..2be66d9821 100644 --- a/arch/ext/Zalrsc.yaml +++ b/arch/ext/Zalrsc.yaml @@ -6,9 +6,9 @@ name: Zalrsc long_name: Atomic read-modify-write instructions type: unprivileged versions: -- version: "1.0.0" - state: ratified - ratification_date: 2024-04 + - version: "1.0.0" + state: ratified + ratification_date: 2024-04 description: | Complex atomic memory operations on a single memory word or doubleword diff --git a/arch/ext/Zba.yaml b/arch/ext/Zba.yaml index 73b1058064..de4642e664 100644 --- a/arch/ext/Zba.yaml +++ b/arch/ext/Zba.yaml @@ -23,41 +23,41 @@ company: name: RISC-V International url: https://riscv.org versions: -- version: "1.0.0" - state: ratified - ratification_date: 2021-06 - repositories: - - url: https://github.com/riscv/riscv-bitmanip - branch: main - contributors: - - name: Jacob Bachmeyer - - name: Allen Baum - - name: Ari Ben - - name: Alex Bradbury - - name: Steven Brager - - name: Rogier Brussee - - name: Michael Clark - - name: Ken Dockser - - name: Paul Donahue - - name: Dennis Ferguson - - name: Fabian Giesen - - name: John Hauser - - name: Robert Henry - - name: Bruce Holt - - name: Po-wei Huang - - name: Ben Marshall - - name: Rex McCrary - - name: Lee Moore - - name: Jiri Moravec - - name: Samuel Neves - - name: Markus Oberhumer - - name: Christopher Olson - - name: Nils Pipenbrinck - - name: Joseph Rahmeh - - name: Xue Saw - - name: Tommy Thorn - - name: Philipp Tomsich - - name: Avishai Tvila - - name: Andrew Waterman - - name: Thomas Wicki - - name: Claire Wolf + - version: "1.0.0" + state: ratified + ratification_date: 2021-06 + repositories: + - url: https://github.com/riscv/riscv-bitmanip + branch: main + contributors: + - name: Jacob Bachmeyer + - name: Allen Baum + - name: Ari Ben + - name: Alex Bradbury + - name: Steven Brager + - name: Rogier Brussee + - name: Michael Clark + - name: Ken Dockser + - name: Paul Donahue + - name: Dennis Ferguson + - name: Fabian Giesen + - name: John Hauser + - name: Robert Henry + - name: Bruce Holt + - name: Po-wei Huang + - name: Ben Marshall + - name: Rex McCrary + - name: Lee Moore + - name: Jiri Moravec + - name: Samuel Neves + - name: Markus Oberhumer + - name: Christopher Olson + - name: Nils Pipenbrinck + - name: Joseph Rahmeh + - name: Xue Saw + - name: Tommy Thorn + - name: Philipp Tomsich + - name: Avishai Tvila + - name: Andrew Waterman + - name: Thomas Wicki + - name: Claire Wolf diff --git a/arch/ext/Zbb.yaml b/arch/ext/Zbb.yaml index 747b4f74ec..dbf92908c6 100644 --- a/arch/ext/Zbb.yaml +++ b/arch/ext/Zbb.yaml @@ -11,41 +11,41 @@ company: name: RISC-V International url: https://riscv.org versions: -- version: "1.0.0" - state: ratified - ratification_date: 2021-06 - repositories: - - url: https://github.com/riscv/riscv-bitmanip - branch: main - contributors: - - name: Jacob Bachmeyer - - name: Allen Baum - - name: Ari Ben - - name: Alex Bradbury - - name: Steven Brager - - name: Rogier Brussee - - name: Michael Clark - - name: Ken Dockser - - name: Paul Donahue - - name: Dennis Ferguson - - name: Fabian Giesen - - name: John Hauser - - name: Robert Henry - - name: Bruce Holt - - name: Po-wei Huang - - name: Ben Marshall - - name: Rex McCrary - - name: Lee Moore - - name: Jiri Moravec - - name: Samuel Neves - - name: Markus Oberhumer - - name: Christopher Olson - - name: Nils Pipenbrinck - - name: Joseph Rahmeh - - name: Xue Saw - - name: Tommy Thorn - - name: Philipp Tomsich - - name: Avishai Tvila - - name: Andrew Waterman - - name: Thomas Wicki - - name: Claire Wolf + - version: "1.0.0" + state: ratified + ratification_date: 2021-06 + repositories: + - url: https://github.com/riscv/riscv-bitmanip + branch: main + contributors: + - name: Jacob Bachmeyer + - name: Allen Baum + - name: Ari Ben + - name: Alex Bradbury + - name: Steven Brager + - name: Rogier Brussee + - name: Michael Clark + - name: Ken Dockser + - name: Paul Donahue + - name: Dennis Ferguson + - name: Fabian Giesen + - name: John Hauser + - name: Robert Henry + - name: Bruce Holt + - name: Po-wei Huang + - name: Ben Marshall + - name: Rex McCrary + - name: Lee Moore + - name: Jiri Moravec + - name: Samuel Neves + - name: Markus Oberhumer + - name: Christopher Olson + - name: Nils Pipenbrinck + - name: Joseph Rahmeh + - name: Xue Saw + - name: Tommy Thorn + - name: Philipp Tomsich + - name: Avishai Tvila + - name: Andrew Waterman + - name: Thomas Wicki + - name: Claire Wolf diff --git a/arch/ext/Zbc.yaml b/arch/ext/Zbc.yaml index 1668b20427..bfcc8e7744 100644 --- a/arch/ext/Zbc.yaml +++ b/arch/ext/Zbc.yaml @@ -11,41 +11,41 @@ company: name: RISC-V International url: https://riscv.org versions: -- version: "1.0.0" - state: ratified - ratification_date: 2021-06 - repositories: - - url: https://github.com/riscv/riscv-bitmanip - branch: main - contributors: - - name: Jacob Bachmeyer - - name: Allen Baum - - name: Ari Ben - - name: Alex Bradbury - - name: Steven Brager - - name: Rogier Brussee - - name: Michael Clark - - name: Ken Dockser - - name: Paul Donahue - - name: Dennis Ferguson - - name: Fabian Giesen - - name: John Hauser - - name: Robert Henry - - name: Bruce Holt - - name: Po-wei Huang - - name: Ben Marshall - - name: Rex McCrary - - name: Lee Moore - - name: Jiri Moravec - - name: Samuel Neves - - name: Markus Oberhumer - - name: Christopher Olson - - name: Nils Pipenbrinck - - name: Joseph Rahmeh - - name: Xue Saw - - name: Tommy Thorn - - name: Philipp Tomsich - - name: Avishai Tvila - - name: Andrew Waterman - - name: Thomas Wicki - - name: Claire Wolf + - version: "1.0.0" + state: ratified + ratification_date: 2021-06 + repositories: + - url: https://github.com/riscv/riscv-bitmanip + branch: main + contributors: + - name: Jacob Bachmeyer + - name: Allen Baum + - name: Ari Ben + - name: Alex Bradbury + - name: Steven Brager + - name: Rogier Brussee + - name: Michael Clark + - name: Ken Dockser + - name: Paul Donahue + - name: Dennis Ferguson + - name: Fabian Giesen + - name: John Hauser + - name: Robert Henry + - name: Bruce Holt + - name: Po-wei Huang + - name: Ben Marshall + - name: Rex McCrary + - name: Lee Moore + - name: Jiri Moravec + - name: Samuel Neves + - name: Markus Oberhumer + - name: Christopher Olson + - name: Nils Pipenbrinck + - name: Joseph Rahmeh + - name: Xue Saw + - name: Tommy Thorn + - name: Philipp Tomsich + - name: Avishai Tvila + - name: Andrew Waterman + - name: Thomas Wicki + - name: Claire Wolf diff --git a/arch/ext/Zbs.yaml b/arch/ext/Zbs.yaml index b7aee60c78..5340c261a9 100644 --- a/arch/ext/Zbs.yaml +++ b/arch/ext/Zbs.yaml @@ -15,42 +15,42 @@ doc_license: name: Creative Commons Attribution 4.0 International License (CC-BY 4.0) url: https://creativecommons.org/licenses/by/4.0/ versions: -- version: "1.0.0" - state: ratified - ratification_date: 2021-06 - url: https://drive.google.com/drive/u/0/folders/1_wqb-rXOVkGa6rqmugN3kwCftWDf1daU - repositories: - - url: https://github.com/riscv/riscv-bitmanip - branch: main - contributors: - - name: Jacob Bachmeyer - - name: Allen Baum - - name: Ari Ben - - name: Alex Bradbury - - name: Steven Brager - - name: Rogier Brussee - - name: Michael Clark - - name: Ken Dockser - - name: Paul Donahue - - name: Dennis Ferguson - - name: Fabian Giesen - - name: John Hauser - - name: Robert Henry - - name: Bruce Holt - - name: Po-wei Huang - - name: Ben Marshall - - name: Rex McCrary - - name: Lee Moore - - name: Jiri Moravec - - name: Samuel Neves - - name: Markus Oberhumer - - name: Christopher Olson - - name: Nils Pipenbrinck - - name: Joseph Rahmeh - - name: Xue Saw - - name: Tommy Thorn - - name: Philipp Tomsich - - name: Avishai Tvila - - name: Andrew Waterman - - name: Thomas Wicki - - name: Claire Wolf + - version: "1.0.0" + state: ratified + ratification_date: 2021-06 + url: https://drive.google.com/drive/u/0/folders/1_wqb-rXOVkGa6rqmugN3kwCftWDf1daU + repositories: + - url: https://github.com/riscv/riscv-bitmanip + branch: main + contributors: + - name: Jacob Bachmeyer + - name: Allen Baum + - name: Ari Ben + - name: Alex Bradbury + - name: Steven Brager + - name: Rogier Brussee + - name: Michael Clark + - name: Ken Dockser + - name: Paul Donahue + - name: Dennis Ferguson + - name: Fabian Giesen + - name: John Hauser + - name: Robert Henry + - name: Bruce Holt + - name: Po-wei Huang + - name: Ben Marshall + - name: Rex McCrary + - name: Lee Moore + - name: Jiri Moravec + - name: Samuel Neves + - name: Markus Oberhumer + - name: Christopher Olson + - name: Nils Pipenbrinck + - name: Joseph Rahmeh + - name: Xue Saw + - name: Tommy Thorn + - name: Philipp Tomsich + - name: Avishai Tvila + - name: Andrew Waterman + - name: Thomas Wicki + - name: Claire Wolf diff --git a/arch/ext/Zcb.yaml b/arch/ext/Zcb.yaml index ccd0012fcb..df46dc60ea 100644 --- a/arch/ext/Zcb.yaml +++ b/arch/ext/Zcb.yaml @@ -18,25 +18,25 @@ company: name: RISC-V International url: https://riscv.org versions: -- version: "1.0.0" - state: ratified - ratification_date: 2023-04 - repositories: - - url: https://github.com/riscv/riscv-code-size-reduction - branch: main - contributors: - - name: Tariq Kurd - - name: Ibrahim Abu Kharmeh - - name: Torbjørn Viem Ness - - name: Matteo Perotti - - name: Nidal Faour - - name: Bill Traynor - - name: Rafael Sene - - name: Xinlong Wu - - name: sinan - - name: Jeremy Bennett - - name: Heda Chen - - name: Alasdair Armstrong - - name: Graeme Smecher - - name: Nicolas Brunie - - name: Jiawei + - version: "1.0.0" + state: ratified + ratification_date: 2023-04 + repositories: + - url: https://github.com/riscv/riscv-code-size-reduction + branch: main + contributors: + - name: Tariq Kurd + - name: Ibrahim Abu Kharmeh + - name: Torbjørn Viem Ness + - name: Matteo Perotti + - name: Nidal Faour + - name: Bill Traynor + - name: Rafael Sene + - name: Xinlong Wu + - name: sinan + - name: Jeremy Bennett + - name: Heda Chen + - name: Alasdair Armstrong + - name: Graeme Smecher + - name: Nicolas Brunie + - name: Jiawei diff --git a/arch/ext/Zfhmin.yaml b/arch/ext/Zfhmin.yaml index 024f43efab..e51b3d1835 100644 --- a/arch/ext/Zfhmin.yaml +++ b/arch/ext/Zfhmin.yaml @@ -44,9 +44,9 @@ description: | ==== type: unprivileged versions: -- version: "1.0.0" - state: ratified - ratification_date: 2021-11 - requires: - name: F - version: ">= 2.2" + - version: "1.0.0" + state: ratified + ratification_date: 2021-11 + requires: + name: F + version: ">= 2.2" diff --git a/arch/ext/Zic64b.yaml b/arch/ext/Zic64b.yaml index 15395d5ec8..3e09eff3ae 100644 --- a/arch/ext/Zic64b.yaml +++ b/arch/ext/Zic64b.yaml @@ -11,22 +11,22 @@ description: | This extension was ratified with the RVA20 profiles. type: privileged versions: -- version: "1.0.0" - state: ratified - ratification_date: null - url: https://github.com/riscv/riscv-profiles/releases/tag/v1.0 - repositories: - - url: https://github.com/riscv/riscv-profiles - branch: main - contributors: - - name: Krste Asanovic - company: SiFive, Inc. - requires: - anyOf: - - name: Zicbom - - name: Zicboz - - name: Zicbop - param_constraints: - CACHE_BLOCK_SIZE: - schema: - const: 64 + - version: "1.0.0" + state: ratified + ratification_date: null + url: https://github.com/riscv/riscv-profiles/releases/tag/v1.0 + repositories: + - url: https://github.com/riscv/riscv-profiles + branch: main + contributors: + - name: Krste Asanovic + company: SiFive, Inc. + requires: + anyOf: + - name: Zicbom + - name: Zicboz + - name: Zicbop + param_constraints: + CACHE_BLOCK_SIZE: + schema: + const: 64 diff --git a/arch/ext/Zicbom.yaml b/arch/ext/Zicbom.yaml index 23206267c2..f874010f7b 100644 --- a/arch/ext/Zicbom.yaml +++ b/arch/ext/Zicbom.yaml @@ -7,9 +7,9 @@ long_name: Cache block management instructions description: Cache block management instructions type: unprivileged versions: -- version: "1.0.1-b34ea8a" - state: ratified - ratification_date: 2022-05 + - version: "1.0.1-b34ea8a" + state: ratified + ratification_date: 2022-05 params: CACHE_BLOCK_SIZE: description: | diff --git a/arch/ext/Zicbop.yaml b/arch/ext/Zicbop.yaml index 3cd9c3d017..50fa8e8622 100644 --- a/arch/ext/Zicbop.yaml +++ b/arch/ext/Zicbop.yaml @@ -7,9 +7,9 @@ long_name: Cache block prefetch description: Cache block prefetch instruction type: unprivileged versions: -- version: 1.0.1-b34ea8a - state: ratified - ratification_date: 2022-05 + - version: 1.0.1-b34ea8a + state: ratified + ratification_date: 2022-05 params: CACHE_BLOCK_SIZE: description: | diff --git a/arch/ext/Zicboz.yaml b/arch/ext/Zicboz.yaml index 343b25bafe..c3ce2ab69f 100644 --- a/arch/ext/Zicboz.yaml +++ b/arch/ext/Zicboz.yaml @@ -7,9 +7,9 @@ long_name: Cache block zero instruction description: Cache block zero instruction type: unprivileged versions: -- version: 1.0.1-b34ea8a - state: ratified - ratification_date: 2022-05 + - version: 1.0.1-b34ea8a + state: ratified + ratification_date: 2022-05 params: CACHE_BLOCK_SIZE: description: | diff --git a/arch/ext/Ziccamoa.yaml b/arch/ext/Ziccamoa.yaml index 838438db1d..ceea8fe110 100644 --- a/arch/ext/Ziccamoa.yaml +++ b/arch/ext/Ziccamoa.yaml @@ -10,6 +10,6 @@ description: | [NOTE] This extension was ratified as part of the RVA20 profile. versions: -- version: "1.0.0" - state: ratified - ratification_date: null + - version: "1.0.0" + state: ratified + ratification_date: null diff --git a/arch/ext/Ziccif.yaml b/arch/ext/Ziccif.yaml index 4a35d7b004..69d7e32403 100644 --- a/arch/ext/Ziccif.yaml +++ b/arch/ext/Ziccif.yaml @@ -12,6 +12,6 @@ description: | [NOTE] This extension was ratified as part of the RVA20 profile. versions: -- version: "1.0.0" - state: ratified - ratification_date: null + - version: "1.0.0" + state: ratified + ratification_date: null diff --git a/arch/ext/Zicclsm.yaml b/arch/ext/Zicclsm.yaml index 835e91223e..9eae9b58a8 100644 --- a/arch/ext/Zicclsm.yaml +++ b/arch/ext/Zicclsm.yaml @@ -18,10 +18,10 @@ description: | Standard software distributions should assume their existence only for correctness, not for performance. versions: -- version: "1.0.0" - state: ratified - ratification_date: null - param_constraints: - MISALIGNED_LDST: - schema: - const: true + - version: "1.0.0" + state: ratified + ratification_date: null + param_constraints: + MISALIGNED_LDST: + schema: + const: true diff --git a/arch/ext/Ziccrse.yaml b/arch/ext/Ziccrse.yaml index 93e7539b82..f73fc4f39c 100644 --- a/arch/ext/Ziccrse.yaml +++ b/arch/ext/Ziccrse.yaml @@ -10,6 +10,6 @@ description: | [NOTE] This extension was ratified as part of the RVA20 profile. versions: -- version: "1.0.0" - state: ratified - ratification_date: null + - version: "1.0.0" + state: ratified + ratification_date: null diff --git a/arch/ext/Zicfilp.yaml b/arch/ext/Zicfilp.yaml index 27613044c2..a137711769 100644 --- a/arch/ext/Zicfilp.yaml +++ b/arch/ext/Zicfilp.yaml @@ -6,9 +6,9 @@ description: | TODO type: unprivileged versions: -- version: "1.0.0" - state: ratified - ratification_date: 2024-07 + - version: "1.0.0" + state: ratified + ratification_date: 2024-07 params: REPORT_CAUSE_IN_MTVAL_ON_LANDING_PAD_SOFTWARE_CHECK: description: | diff --git a/arch/ext/Zicfiss.yaml b/arch/ext/Zicfiss.yaml index 41c0b0e6c4..0bd011bfb2 100644 --- a/arch/ext/Zicfiss.yaml +++ b/arch/ext/Zicfiss.yaml @@ -8,9 +8,9 @@ description: | TODO type: unprivileged versions: -- version: "1.0.0" - state: ratified - ratification_date: 2024-07 + - version: "1.0.0" + state: ratified + ratification_date: 2024-07 params: REPORT_CAUSE_IN_MTVAL_ON_SHADOW_STACK_SOFTWARE_CHECK: description: | diff --git a/arch/ext/Zicntr.yaml b/arch/ext/Zicntr.yaml index 85f2ce5e2e..e709f094e2 100644 --- a/arch/ext/Zicntr.yaml +++ b/arch/ext/Zicntr.yaml @@ -7,12 +7,12 @@ long_name: Architectural performance counters description: Architectural performance counters type: unprivileged versions: -- version: "2.0.0" - state: ratified - ratification_date: 2019-12 - requires: - name: Zicsr - version: ">= 2.0" + - version: "2.0.0" + state: ratified + ratification_date: 2019-12 + requires: + name: Zicsr + version: ">= 2.0" params: TIME_CSR_IMPLEMENTED: description: | diff --git a/arch/ext/Zicsr.yaml b/arch/ext/Zicsr.yaml index 92689331af..1cc2ec2b2b 100644 --- a/arch/ext/Zicsr.yaml +++ b/arch/ext/Zicsr.yaml @@ -7,6 +7,6 @@ long_name: Control and status registers description: Control and status registers type: unprivileged versions: -- version: "2.0.0" - state: ratified - ratification_date: null + - version: "2.0.0" + state: ratified + ratification_date: null diff --git a/arch/ext/Zifencei.yaml b/arch/ext/Zifencei.yaml index 7b661769b3..d134730282 100644 --- a/arch/ext/Zifencei.yaml +++ b/arch/ext/Zifencei.yaml @@ -67,6 +67,6 @@ description: | ==== type: unprivileged versions: -- version: "2.0.0" - state: ratified - ratification_date: null + - version: "2.0.0" + state: ratified + ratification_date: null diff --git a/arch/ext/Zihintpause.yaml b/arch/ext/Zihintpause.yaml index 06db29627f..7bbe10de9c 100644 --- a/arch/ext/Zihintpause.yaml +++ b/arch/ext/Zihintpause.yaml @@ -68,6 +68,6 @@ description: | ==== type: unprivileged versions: -- version: "2.0.0" - state: ratified - ratification_date: null + - version: "2.0.0" + state: ratified + ratification_date: null diff --git a/arch/ext/Zihpm.yaml b/arch/ext/Zihpm.yaml index f7ec3b9baa..c5922e781b 100644 --- a/arch/ext/Zihpm.yaml +++ b/arch/ext/Zihpm.yaml @@ -7,8 +7,8 @@ long_name: Programmable hardware performance counters description: Programmable hardware performance counters type: unprivileged versions: -- version: "2.0.0" - state: ratified - ratification_date: unknown - requires: - name: Smhpm + - version: "2.0.0" + state: ratified + ratification_date: unknown + requires: + name: Smhpm diff --git a/arch/ext/Zkt.yaml b/arch/ext/Zkt.yaml index d5946dd454..4db84b2769 100644 --- a/arch/ext/Zkt.yaml +++ b/arch/ext/Zkt.yaml @@ -335,28 +335,28 @@ description: | type: unprivileged versions: -- version: "1.0.0" - state: ratified - ratification_date: 2021-11 - contributors: - - name: Alexander Zeh - - name: Andy Glew - - name: Barry Spinney - - name: Ben Marshall - email: benmarshall@pqshield.com - - name: Daniel Page - - name: Derek Atkins - - name: Ken Dockser - - name: Markku-Juhani O. Saarinen - - name: Nathan Menhorn - - name: L Peter Deutsch - - name: Richard Newell - - name: Claire Wolf -- version: 1.0.1 - state: ratified - ratification_date: null - changes: - - Fix typos to show that `c.srli`, `c.srai`, and `c.slli` are Zkt instructions in RV64. + - version: "1.0.0" + state: ratified + ratification_date: 2021-11 + contributors: + - name: Alexander Zeh + - name: Andy Glew + - name: Barry Spinney + - name: Ben Marshall + email: benmarshall@pqshield.com + - name: Daniel Page + - name: Derek Atkins + - name: Ken Dockser + - name: Markku-Juhani O. Saarinen + - name: Nathan Menhorn + - name: L Peter Deutsch + - name: Richard Newell + - name: Claire Wolf + - version: 1.0.1 + state: ratified + ratification_date: null + changes: + - Fix typos to show that `c.srli`, `c.srai`, and `c.slli` are Zkt instructions in RV64. company: name: RISC-V International url: https://riscv.org diff --git a/arch/ext/Zmmul.yaml b/arch/ext/Zmmul.yaml index 1d52348e28..aef4c684a1 100644 --- a/arch/ext/Zmmul.yaml +++ b/arch/ext/Zmmul.yaml @@ -20,6 +20,6 @@ description: | implemented in soft logic. type: unprivileged versions: -- version: "1.0.0" - state: ratified - ratification_date: 2022-06 + - version: "1.0.0" + state: ratified + ratification_date: 2022-06 diff --git a/arch/inst/A/amoadd.d.yaml b/arch/inst/A/amoadd.d.yaml index 3d7c6b529e..d0eb0ce3f5 100644 --- a/arch/inst/A/amoadd.d.yaml +++ b/arch/inst/A/amoadd.d.yaml @@ -5,12 +5,12 @@ kind: instruction name: amoadd.d long_name: Atomic fetch-and-add doubleword description: | - Atomically: + Atomically: - * Load the doubleword at address _rs1_ - * Write the loaded value into _rd_ - * Add the value of register _rs2_ to the loaded value - * Write the sum to the address in _rs1_ + * Load the doubleword at address _rs1_ + * Write the loaded value into _rd_ + * Add the value of register _rs2_ to the loaded value + * Write the sum to the address in _rs1_ definedBy: anyOf: [A, Zaamo] base: 64 @@ -18,16 +18,16 @@ assembly: xd, xs2, (xs1) encoding: match: 00000------------011-----0101111 variables: - - name: aq - location: 26 - - name: rl - location: 25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26 + - name: rl + location: 25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -44,8 +44,6 @@ operation(): | X[rd] = amo<64>(virtual_address, X[rs2], AmoOperation::Add, aq, rl, $encoding); - - sail(): | { if extension("A") then { diff --git a/arch/inst/A/amoadd.w.yaml b/arch/inst/A/amoadd.w.yaml index 81938edbd3..f4178c0c0f 100644 --- a/arch/inst/A/amoadd.w.yaml +++ b/arch/inst/A/amoadd.w.yaml @@ -5,28 +5,28 @@ kind: instruction name: amoadd.w long_name: Atomic fetch-and-add word description: | - Atomically: + Atomically: - * Load the word at address _rs1_ - * Write the sign-extended value into _rd_ - * Add the least-significant word of register _rs2_ to the loaded value - * Write the sum to the address in _rs1_ + * Load the word at address _rs1_ + * Write the sign-extended value into _rd_ + * Add the least-significant word of register _rs2_ to the loaded value + * Write the sum to the address in _rs1_ definedBy: anyOf: [A, Zaamo] assembly: xd, xs2, (xrs1) encoding: match: 00000------------010-----0101111 variables: - - name: aq - location: 26 - - name: rl - location: 25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26 + - name: rl + location: 25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -43,8 +43,6 @@ operation(): | X[rd] = amo<32>(virtual_address, X[rs2][31:0], AmoOperation::Add, aq, rl, $encoding); - - sail(): | { if extension("A") then { diff --git a/arch/inst/A/amoand.d.yaml b/arch/inst/A/amoand.d.yaml index 3d12556b34..dd945113d1 100644 --- a/arch/inst/A/amoand.d.yaml +++ b/arch/inst/A/amoand.d.yaml @@ -5,12 +5,12 @@ kind: instruction name: amoand.d long_name: Atomic fetch-and-and doubleword description: | - Atomically: + Atomically: - * Load the doubleword at address _rs1_ - * Write the loaded value into _rd_ - * AND the value of register _rs2_ to the loaded value - * Write the result to the address in _rs1_ + * Load the doubleword at address _rs1_ + * Write the loaded value into _rd_ + * AND the value of register _rs2_ to the loaded value + * Write the result to the address in _rs1_ definedBy: anyOf: [A, Zaamo] base: 64 @@ -18,16 +18,16 @@ assembly: xd, xs2, (xrs1) encoding: match: 01100------------011-----0101111 variables: - - name: aq - location: 26 - - name: rl - location: 25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26 + - name: rl + location: 25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -44,8 +44,6 @@ operation(): | X[rd] = amo<64>(virtual_address, X[rs2], AmoOperation::And, aq, rl, $encoding); - - sail(): | { if extension("A") then { diff --git a/arch/inst/A/amoand.w.yaml b/arch/inst/A/amoand.w.yaml index 5125011312..a941de7bee 100644 --- a/arch/inst/A/amoand.w.yaml +++ b/arch/inst/A/amoand.w.yaml @@ -5,28 +5,28 @@ kind: instruction name: amoand.w long_name: Atomic fetch-and-and word description: | - Atomically: + Atomically: - * Load the word at address _rs1_ - * Write the sign-extended value into _rd_ - * AND the least-significant word of register _rs2_ to the loaded value - * Write the result to the address in _rs1_ + * Load the word at address _rs1_ + * Write the sign-extended value into _rd_ + * AND the least-significant word of register _rs2_ to the loaded value + * Write the result to the address in _rs1_ definedBy: anyOf: [A, Zaamo] assembly: xd, xs2, (xrs1) encoding: match: 01100------------010-----0101111 variables: - - name: aq - location: 26 - - name: rl - location: 25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26 + - name: rl + location: 25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -43,8 +43,6 @@ operation(): | X[rd] = amo<32>(virtual_address, X[rs2][31:0], AmoOperation::And, aq, rl, $encoding); - - sail(): | { if extension("A") then { diff --git a/arch/inst/A/amomax.d.yaml b/arch/inst/A/amomax.d.yaml index c223bf0177..ddc0d12225 100644 --- a/arch/inst/A/amomax.d.yaml +++ b/arch/inst/A/amomax.d.yaml @@ -5,12 +5,12 @@ kind: instruction name: amomax.d long_name: Atomic MAX doubleword description: | - Atomically: + Atomically: - * Load the doubleword at address _rs1_ - * Write the loaded value into _rd_ - * Signed compare the value of register _rs2_ to the loaded value, and select the maximum value - * Write the maximum to the address in _rs1_ + * Load the doubleword at address _rs1_ + * Write the loaded value into _rd_ + * Signed compare the value of register _rs2_ to the loaded value, and select the maximum value + * Write the maximum to the address in _rs1_ definedBy: anyOf: [A, Zaamo] base: 64 @@ -18,16 +18,16 @@ assembly: xd, xs2, (xrs1) encoding: match: 10100------------011-----0101111 variables: - - name: aq - location: 26 - - name: rl - location: 25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26 + - name: rl + location: 25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -44,8 +44,6 @@ operation(): | X[rd] = amo<64>(virtual_address, X[rs2], AmoOperation::Max, aq, rl, $encoding); - - sail(): | { if extension("A") then { diff --git a/arch/inst/A/amomax.w.yaml b/arch/inst/A/amomax.w.yaml index 2f4602c7df..c7a4d71f9c 100644 --- a/arch/inst/A/amomax.w.yaml +++ b/arch/inst/A/amomax.w.yaml @@ -5,28 +5,28 @@ kind: instruction name: amomax.w long_name: Atomic MAX word description: | - Atomically: + Atomically: - * Load the word at address _rs1_ - * Write the sign-extended value into _rd_ - * Signed compare the least-significant word of register _rs2_ to the loaded value, and select the maximum value - * Write the maximum to the address in _rs1_ + * Load the word at address _rs1_ + * Write the sign-extended value into _rd_ + * Signed compare the least-significant word of register _rs2_ to the loaded value, and select the maximum value + * Write the maximum to the address in _rs1_ definedBy: anyOf: [A, Zaamo] assembly: xd, xs2, (xrs1) encoding: match: 10100------------010-----0101111 variables: - - name: aq - location: 26 - - name: rl - location: 25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26 + - name: rl + location: 25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -43,8 +43,6 @@ operation(): | X[rd] = amo<32>(virtual_address, X[rs2][31:0], AmoOperation::Max, aq, rl, $encoding); - - sail(): | { if extension("A") then { diff --git a/arch/inst/A/amomaxu.d.yaml b/arch/inst/A/amomaxu.d.yaml index 821ea8ea74..96ba6b0df9 100644 --- a/arch/inst/A/amomaxu.d.yaml +++ b/arch/inst/A/amomaxu.d.yaml @@ -5,12 +5,12 @@ kind: instruction name: amomaxu.d long_name: Atomic MAX unsigned doubleword description: | - Atomically: + Atomically: - * Load the doubleword at address _rs1_ - * Write the loaded value into _rd_ - * Unsigned compare the value of register _rs2_ to the loaded value, and select the maximum value - * Write the maximum to the address in _rs1_ + * Load the doubleword at address _rs1_ + * Write the loaded value into _rd_ + * Unsigned compare the value of register _rs2_ to the loaded value, and select the maximum value + * Write the maximum to the address in _rs1_ definedBy: anyOf: [A, Zaamo] base: 64 @@ -18,16 +18,16 @@ assembly: xd, xs2, (xrs1) encoding: match: 11100------------011-----0101111 variables: - - name: aq - location: 26 - - name: rl - location: 25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26 + - name: rl + location: 25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -43,8 +43,6 @@ operation(): | X[rd] = amo<64>(virtual_address, X[rs2], AmoOperation::Maxu, aq, rl, $encoding); - - sail(): | { if extension("A") then { diff --git a/arch/inst/A/amomaxu.w.yaml b/arch/inst/A/amomaxu.w.yaml index 268abc22a6..a5e4ab919d 100644 --- a/arch/inst/A/amomaxu.w.yaml +++ b/arch/inst/A/amomaxu.w.yaml @@ -5,28 +5,28 @@ kind: instruction name: amomaxu.w long_name: Atomic MAX unsigned word description: | - Atomically: + Atomically: - * Load the word at address _rs1_ - * Write the sign-extended value into _rd_ - * Unsigned compare the least-significant word of register _rs2_ to the loaded value, and select the maximum value - * Write the maximum to the address in _rs1_ + * Load the word at address _rs1_ + * Write the sign-extended value into _rd_ + * Unsigned compare the least-significant word of register _rs2_ to the loaded value, and select the maximum value + * Write the maximum to the address in _rs1_ definedBy: anyOf: [A, Zaamo] assembly: xd, xs2, (xrs1) encoding: match: 11100------------010-----0101111 variables: - - name: aq - location: 26 - - name: rl - location: 25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26 + - name: rl + location: 25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -43,8 +43,6 @@ operation(): | X[rd] = amo<32>(virtual_address, X[rs2][31:0], AmoOperation::Maxu, aq, rl, $encoding); - - sail(): | { if extension("A") then { diff --git a/arch/inst/A/amomin.d.yaml b/arch/inst/A/amomin.d.yaml index f111b41023..27ab364168 100644 --- a/arch/inst/A/amomin.d.yaml +++ b/arch/inst/A/amomin.d.yaml @@ -5,12 +5,12 @@ kind: instruction name: amomin.d long_name: Atomic MIN doubleword description: | - Atomically: + Atomically: - * Load the doubleword at address _rs1_ - * Write the loaded value into _rd_ - * Signed compare the value of register _rs2_ to the loaded value, and select the mimimum value - * Write the minimum to the address in _rs1_ + * Load the doubleword at address _rs1_ + * Write the loaded value into _rd_ + * Signed compare the value of register _rs2_ to the loaded value, and select the mimimum value + * Write the minimum to the address in _rs1_ definedBy: anyOf: [A, Zaamo] base: 64 @@ -18,16 +18,16 @@ assembly: xd, xs2, (xrs1) encoding: match: 10000------------011-----0101111 variables: - - name: aq - location: 26 - - name: rl - location: 25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26 + - name: rl + location: 25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -44,8 +44,6 @@ operation(): | X[rd] = amo<64>(virtual_address, X[rs2], AmoOperation::Min, aq, rl, $encoding); - - sail(): | { if extension("A") then { diff --git a/arch/inst/A/amomin.w.yaml b/arch/inst/A/amomin.w.yaml index b461a48f85..5b9fc763e5 100644 --- a/arch/inst/A/amomin.w.yaml +++ b/arch/inst/A/amomin.w.yaml @@ -5,28 +5,28 @@ kind: instruction name: amomin.w long_name: Atomic MIN word description: | - Atomically: + Atomically: - * Load the word at address _rs1_ - * Write the sign-extended value into _rd_ - * Signed compare the least-significant word of register _rs2_ to the loaded value, and select the mimimum value - * Write the result to the address in _rs1_ + * Load the word at address _rs1_ + * Write the sign-extended value into _rd_ + * Signed compare the least-significant word of register _rs2_ to the loaded value, and select the mimimum value + * Write the result to the address in _rs1_ definedBy: anyOf: [A, Zaamo] assembly: xd, xs2, (xrs1) encoding: match: 10000------------010-----0101111 variables: - - name: aq - location: 26 - - name: rl - location: 25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26 + - name: rl + location: 25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -43,8 +43,6 @@ operation(): | X[rd] = amo<32>(virtual_address, X[rs2][31:0], AmoOperation::Min, aq, rl, $encoding); - - sail(): | { if extension("A") then { diff --git a/arch/inst/A/amominu.d.yaml b/arch/inst/A/amominu.d.yaml index 3252fe8129..7a1ef98556 100644 --- a/arch/inst/A/amominu.d.yaml +++ b/arch/inst/A/amominu.d.yaml @@ -5,12 +5,12 @@ kind: instruction name: amominu.d long_name: Atomic MIN unsigned doubleword description: | - Atomically: + Atomically: - * Load the doubleword at address _rs1_ - * Write the loaded value into _rd_ - * Unsigned compare the value of register _rs2_ to the loaded value, and select the mimimum value - * Write the minimum to the address in _rs1_ + * Load the doubleword at address _rs1_ + * Write the loaded value into _rd_ + * Unsigned compare the value of register _rs2_ to the loaded value, and select the mimimum value + * Write the minimum to the address in _rs1_ definedBy: anyOf: [A, Zaamo] base: 64 @@ -18,16 +18,16 @@ assembly: xd, xs2, (xrs1) encoding: match: 11000------------011-----0101111 variables: - - name: aq - location: 26 - - name: rl - location: 25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26 + - name: rl + location: 25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -44,8 +44,6 @@ operation(): | X[rd] = amo<64>(virtual_address, X[rs2], AmoOperation::Minu, aq, rl, $encoding); - - sail(): | { if extension("A") then { diff --git a/arch/inst/A/amominu.w.yaml b/arch/inst/A/amominu.w.yaml index c5eba85a8d..7860ced2e9 100644 --- a/arch/inst/A/amominu.w.yaml +++ b/arch/inst/A/amominu.w.yaml @@ -5,28 +5,28 @@ kind: instruction name: amominu.w long_name: Atomic MIN unsigned word description: | - Atomically: + Atomically: - * Load the word at address _rs1_ - * Write the sign-extended value into _rd_ - * Unsigned compare the least-significant word of register _rs2_ to the loaded word, and select the mimimum value - * Write the result to the address in _rs1_ + * Load the word at address _rs1_ + * Write the sign-extended value into _rd_ + * Unsigned compare the least-significant word of register _rs2_ to the loaded word, and select the mimimum value + * Write the result to the address in _rs1_ definedBy: anyOf: [A, Zaamo] assembly: xd, xs2, (xrs1) encoding: match: 11000------------010-----0101111 variables: - - name: aq - location: 26 - - name: rl - location: 25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26 + - name: rl + location: 25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -43,8 +43,6 @@ operation(): | X[rd] = amo<32>(virtual_address, X[rs2][31:0], AmoOperation::Minu, aq, rl, $encoding); - - sail(): | { if extension("A") then { diff --git a/arch/inst/A/amoor.d.yaml b/arch/inst/A/amoor.d.yaml index bb4a019e08..bad4d513d8 100644 --- a/arch/inst/A/amoor.d.yaml +++ b/arch/inst/A/amoor.d.yaml @@ -5,12 +5,12 @@ kind: instruction name: amoor.d long_name: Atomic fetch-and-or doubleword description: | - Atomically: + Atomically: - * Load the doubleword at address _rs1_ - * Write the loaded value into _rd_ - * OR the value of register _rs2_ to the loaded value - * Write the result to the address in _rs1_ + * Load the doubleword at address _rs1_ + * Write the loaded value into _rd_ + * OR the value of register _rs2_ to the loaded value + * Write the result to the address in _rs1_ definedBy: anyOf: [A, Zaamo] base: 64 @@ -18,16 +18,16 @@ assembly: xd, xs2, (xrs1) encoding: match: 01000------------011-----0101111 variables: - - name: aq - location: 26 - - name: rl - location: 25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26 + - name: rl + location: 25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -44,8 +44,6 @@ operation(): | X[rd] = amo<64>(virtual_address, X[rs2], AmoOperation::Or, aq, rl, $encoding); - - sail(): | { if extension("A") then { diff --git a/arch/inst/A/amoor.w.yaml b/arch/inst/A/amoor.w.yaml index bd31b909f8..2791a551f5 100644 --- a/arch/inst/A/amoor.w.yaml +++ b/arch/inst/A/amoor.w.yaml @@ -5,28 +5,28 @@ kind: instruction name: amoor.w long_name: Atomic fetch-and-or word description: | - Atomically: + Atomically: - * Load the word at address _rs1_ - * Write the sign-extended value into _rd_ - * OR the least-significant word of register _rs2_ to the loaded value - * Write the result to the address in _rs1_ + * Load the word at address _rs1_ + * Write the sign-extended value into _rd_ + * OR the least-significant word of register _rs2_ to the loaded value + * Write the result to the address in _rs1_ definedBy: anyOf: [A, Zaamo] assembly: xd, xs2, (xrs1) encoding: match: 01000------------010-----0101111 variables: - - name: aq - location: 26 - - name: rl - location: 25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26 + - name: rl + location: 25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -43,8 +43,6 @@ operation(): | X[rd] = amo<32>(virtual_address, X[rs2][31:0], AmoOperation::Or, aq, rl, $encoding); - - sail(): | { if extension("A") then { diff --git a/arch/inst/A/amoswap.d.yaml b/arch/inst/A/amoswap.d.yaml index e6f065534d..10cccfede2 100644 --- a/arch/inst/A/amoswap.d.yaml +++ b/arch/inst/A/amoswap.d.yaml @@ -5,11 +5,11 @@ kind: instruction name: amoswap.d long_name: Atomic SWAP doubleword description: | - Atomically: + Atomically: - * Load the doubleword at address _rs1_ - * Write the value into _rd_ - * Store the value of register _rs2_ to the address in _rs1_ + * Load the doubleword at address _rs1_ + * Write the value into _rd_ + * Store the value of register _rs2_ to the address in _rs1_ definedBy: anyOf: [A, Zaamo] base: 64 @@ -17,16 +17,16 @@ assembly: xd, xs2, (xrs1) encoding: match: 00001------------011-----0101111 variables: - - name: aq - location: 26 - - name: rl - location: 25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26 + - name: rl + location: 25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -43,8 +43,6 @@ operation(): | X[rd] = amo<64>(virtual_address, X[rs2], AmoOperation::Swap, aq, rl, $encoding); - - sail(): | { if extension("A") then { diff --git a/arch/inst/A/amoswap.w.yaml b/arch/inst/A/amoswap.w.yaml index 152b663b65..5b03197eb4 100644 --- a/arch/inst/A/amoswap.w.yaml +++ b/arch/inst/A/amoswap.w.yaml @@ -5,27 +5,27 @@ kind: instruction name: amoswap.w long_name: Atomic SWAP word description: | - Atomically: + Atomically: - * Load the word at address _rs1_ - * Write the sign-extended value into _rd_ - * Store the least-significant word of register _rs2_ to the address in _rs1_ + * Load the word at address _rs1_ + * Write the sign-extended value into _rd_ + * Store the least-significant word of register _rs2_ to the address in _rs1_ definedBy: anyOf: [A, Zaamo] assembly: xd, xs2, (xrs1) encoding: match: 00001------------010-----0101111 variables: - - name: aq - location: 26 - - name: rl - location: 25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26 + - name: rl + location: 25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -42,8 +42,6 @@ operation(): | X[rd] = amo<32>(virtual_address, X[rs2][31:0], AmoOperation::Swap, aq, rl, $encoding); - - sail(): | { if extension("A") then { diff --git a/arch/inst/A/amoxor.d.yaml b/arch/inst/A/amoxor.d.yaml index a47e9373c6..d9c442659b 100644 --- a/arch/inst/A/amoxor.d.yaml +++ b/arch/inst/A/amoxor.d.yaml @@ -5,12 +5,12 @@ kind: instruction name: amoxor.d long_name: Atomic fetch-and-xor doubleword description: | - Atomically: + Atomically: - * Load the doubleword at address _rs1_ - * Write the loaded value into _rd_ - * XOR the value of register _rs2_ to the loaded value - * Write the result to the address in _rs1_ + * Load the doubleword at address _rs1_ + * Write the loaded value into _rd_ + * XOR the value of register _rs2_ to the loaded value + * Write the result to the address in _rs1_ definedBy: anyOf: [A, Zaamo] base: 64 @@ -18,16 +18,16 @@ assembly: xd, xs2, (xrs1) encoding: match: 00100------------011-----0101111 variables: - - name: aq - location: 26 - - name: rl - location: 25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26 + - name: rl + location: 25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -44,8 +44,6 @@ operation(): | X[rd] = amo<64>(virtual_address, X[rs2], AmoOperation::Xor, aq, rl, $encoding); - - sail(): | { if extension("A") then { diff --git a/arch/inst/A/amoxor.w.yaml b/arch/inst/A/amoxor.w.yaml index 1c262bd09b..e4bf3478ac 100644 --- a/arch/inst/A/amoxor.w.yaml +++ b/arch/inst/A/amoxor.w.yaml @@ -5,28 +5,28 @@ kind: instruction name: amoxor.w long_name: Atomic fetch-and-xor word description: | - Atomically: + Atomically: - * Load the word at address _rs1_ - * Write the sign-extended value into _rd_ - * XOR the least-significant word of register _rs2_ to the loaded value - * Write the result to the address in _rs1_ + * Load the word at address _rs1_ + * Write the sign-extended value into _rd_ + * XOR the least-significant word of register _rs2_ to the loaded value + * Write the result to the address in _rs1_ definedBy: anyOf: [A, Zaamo] assembly: xd, xs2, (xrs1) encoding: match: 00100------------010-----0101111 variables: - - name: aq - location: 26 - - name: rl - location: 25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26 + - name: rl + location: 25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -43,8 +43,6 @@ operation(): | X[rd] = amo<32>(virtual_address, X[rs2][31:0], AmoOperation::Xor, aq, rl, $encoding); - - sail(): | { if extension("A") then { diff --git a/arch/inst/A/lr.d.yaml b/arch/inst/A/lr.d.yaml index 4844143e8b..033d3be647 100644 --- a/arch/inst/A/lr.d.yaml +++ b/arch/inst/A/lr.d.yaml @@ -5,43 +5,43 @@ kind: instruction name: lr.d long_name: Load reserved doubleword description: | - Loads a word from the address in rs1, places the value in rd, - and registers a _reservation set_ -- a set of bytes that subsumes the bytes in the - addressed word. + Loads a word from the address in rs1, places the value in rd, + and registers a _reservation set_ -- a set of bytes that subsumes the bytes in the + addressed word. - The address in rs1 must be 8-byte aligned. + The address in rs1 must be 8-byte aligned. - If the address is not naturally aligned, a `LoadAddressMisaligned` exception or an - `LoadAccessFault` exception will be generated. The access-fault exception can be generated - for a memory access that would otherwise be able to complete except for the misalignment, - if the misaligned access should not be emulated. + If the address is not naturally aligned, a `LoadAddressMisaligned` exception or an + `LoadAccessFault` exception will be generated. The access-fault exception can be generated + for a memory access that would otherwise be able to complete except for the misalignment, + if the misaligned access should not be emulated. - An implementation can register an arbitrarily large reservation set on each LR, provided the - reservation set includes all bytes of the addressed data word or doubleword. - An SC can only pair with the most recent LR in program order. - An SC may succeed only if no store from another hart to the reservation set can be - observed to have occurred between the LR and the SC, and if there is no other SC between the - LR and itself in program order. - An SC may succeed only if no write from a device other than a hart to the bytes accessed by - the LR instruction can be observed to have occurred between the LR and SC. Note this LR - might have had a different effective address and data size, but reserved the SC's - address as part of the reservation set. + An implementation can register an arbitrarily large reservation set on each LR, provided the + reservation set includes all bytes of the addressed data word or doubleword. + An SC can only pair with the most recent LR in program order. + An SC may succeed only if no store from another hart to the reservation set can be + observed to have occurred between the LR and the SC, and if there is no other SC between the + LR and itself in program order. + An SC may succeed only if no write from a device other than a hart to the bytes accessed by + the LR instruction can be observed to have occurred between the LR and SC. Note this LR + might have had a different effective address and data size, but reserved the SC's + address as part of the reservation set. - [NOTE] - ---- - Following this model, in systems with memory translation, an SC is allowed to succeed if the - earlier LR reserved the same location using an alias with a different virtual address, but is - also allowed to fail if the virtual address is different. + [NOTE] + ---- + Following this model, in systems with memory translation, an SC is allowed to succeed if the + earlier LR reserved the same location using an alias with a different virtual address, but is + also allowed to fail if the virtual address is different. - To accommodate legacy devices and buses, writes from devices other than RISC-V harts are only - required to invalidate reservations when they overlap the bytes accessed by the LR. - These writes are not required to invalidate the reservation when they access other bytes in - the reservation set. - ---- + To accommodate legacy devices and buses, writes from devices other than RISC-V harts are only + required to invalidate reservations when they overlap the bytes accessed by the LR. + These writes are not required to invalidate the reservation when they access other bytes in + the reservation set. + ---- - Software should not set the _rl_ bit on an LR instruction unless the _aq_ bit is also set. - LR.rl and SC.aq instructions are not guaranteed to provide any stronger ordering than those - with both bits clear, but may result in lower performance. + Software should not set the _rl_ bit on an LR instruction unless the _aq_ bit is also set. + LR.rl and SC.aq instructions are not guaranteed to provide any stronger ordering than those + with both bits clear, but may result in lower performance. definedBy: anyOf: [A, Zalrsc] base: 64 @@ -49,14 +49,14 @@ assembly: xd, xs1 encoding: match: 00010--00000-----011-----0101111 variables: - - name: aq - location: 26 - - name: rl - location: 25 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26 + - name: rl + location: 25 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -91,8 +91,6 @@ operation(): | X[rd] = load_reserved<32>(virtual_address, aq, rl, $encoding); - - sail(): | { if extension("A") then { diff --git a/arch/inst/A/lr.w.yaml b/arch/inst/A/lr.w.yaml index 883fedf190..ca99cf80c9 100644 --- a/arch/inst/A/lr.w.yaml +++ b/arch/inst/A/lr.w.yaml @@ -5,62 +5,62 @@ kind: instruction name: lr.w long_name: Load reserved word description: | - Loads a word from the address in rs1, places the sign-extended value in rd, - and registers a _reservation set_ -- a set of bytes that subsumes the bytes in the - addressed word. + Loads a word from the address in rs1, places the sign-extended value in rd, + and registers a _reservation set_ -- a set of bytes that subsumes the bytes in the + addressed word. - <%- if XLEN == 64 -%> - The 32-bit load result is sign-extended to 64-bits. - <%- end -%> + <%- if XLEN == 64 -%> + The 32-bit load result is sign-extended to 64-bits. + <%- end -%> - The address in rs1 must be naturally aligned to the size of the operand - (_i.e._, eight-byte aligned for doublewords and four-byte aligned for words). + The address in rs1 must be naturally aligned to the size of the operand + (_i.e._, eight-byte aligned for doublewords and four-byte aligned for words). - If the address is not naturally aligned, a `LoadAddressMisaligned` exception or an - `LoadAccessFault` exception will be generated. The access-fault exception can be generated - for a memory access that would otherwise be able to complete except for the misalignment, - if the misaligned access should not be emulated. + If the address is not naturally aligned, a `LoadAddressMisaligned` exception or an + `LoadAccessFault` exception will be generated. The access-fault exception can be generated + for a memory access that would otherwise be able to complete except for the misalignment, + if the misaligned access should not be emulated. - An implementation can register an arbitrarily large reservation set on each LR, provided the - reservation set includes all bytes of the addressed data word or doubleword. - An SC can only pair with the most recent LR in program order. - An SC may succeed only if no store from another hart to the reservation set can be - observed to have occurred between the LR and the SC, and if there is no other SC between the - LR and itself in program order. - An SC may succeed only if no write from a device other than a hart to the bytes accessed by - the LR instruction can be observed to have occurred between the LR and SC. Note this LR - might have had a different effective address and data size, but reserved the SC's - address as part of the reservation set. + An implementation can register an arbitrarily large reservation set on each LR, provided the + reservation set includes all bytes of the addressed data word or doubleword. + An SC can only pair with the most recent LR in program order. + An SC may succeed only if no store from another hart to the reservation set can be + observed to have occurred between the LR and the SC, and if there is no other SC between the + LR and itself in program order. + An SC may succeed only if no write from a device other than a hart to the bytes accessed by + the LR instruction can be observed to have occurred between the LR and SC. Note this LR + might have had a different effective address and data size, but reserved the SC's + address as part of the reservation set. - [NOTE] - ---- - Following this model, in systems with memory translation, an SC is allowed to succeed if the - earlier LR reserved the same location using an alias with a different virtual address, but is - also allowed to fail if the virtual address is different. + [NOTE] + ---- + Following this model, in systems with memory translation, an SC is allowed to succeed if the + earlier LR reserved the same location using an alias with a different virtual address, but is + also allowed to fail if the virtual address is different. - To accommodate legacy devices and buses, writes from devices other than RISC-V harts are only - required to invalidate reservations when they overlap the bytes accessed by the LR. - These writes are not required to invalidate the reservation when they access other bytes in - the reservation set. - ---- + To accommodate legacy devices and buses, writes from devices other than RISC-V harts are only + required to invalidate reservations when they overlap the bytes accessed by the LR. + These writes are not required to invalidate the reservation when they access other bytes in + the reservation set. + ---- - Software should not set the _rl_ bit on an LR instruction unless the _aq_ bit is also set. - LR.rl and SC.aq instructions are not guaranteed to provide any stronger ordering than those - with both bits clear, but may result in lower performance. + Software should not set the _rl_ bit on an LR instruction unless the _aq_ bit is also set. + LR.rl and SC.aq instructions are not guaranteed to provide any stronger ordering than those + with both bits clear, but may result in lower performance. definedBy: anyOf: [A, Zalrsc] assembly: xd, xs1 encoding: match: 00010--00000-----010-----0101111 variables: - - name: aq - location: 26 - - name: rl - location: 25 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26 + - name: rl + location: 25 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -100,8 +100,6 @@ operation(): | X[rd] = sext(load_value[31:0], 32); } - - sail(): | { if extension("A") then { diff --git a/arch/inst/A/sc.d.yaml b/arch/inst/A/sc.d.yaml index 3f55a4ec77..019117fb87 100644 --- a/arch/inst/A/sc.d.yaml +++ b/arch/inst/A/sc.d.yaml @@ -104,16 +104,16 @@ assembly: xd, xs2, xs1 encoding: match: 00011------------011-----0101111 variables: - - name: aq - location: 26 - - name: rl - location: 25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26 + - name: rl + location: 25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -150,8 +150,6 @@ operation(): | Boolean success = store_conditional<64>(virtual_address, value, aq, rl, $encoding); X[rd] = success ? 0 : 1; - - sail(): | { if speculate_conditional () == false then { diff --git a/arch/inst/A/sc.w.yaml b/arch/inst/A/sc.w.yaml index fc29cbc00d..4519f59fe1 100644 --- a/arch/inst/A/sc.w.yaml +++ b/arch/inst/A/sc.w.yaml @@ -110,16 +110,16 @@ assembly: xd, xs2, xs1 encoding: match: 00011------------010-----0101111 variables: - - name: aq - location: 26 - - name: rl - location: 25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26 + - name: rl + location: 25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -156,8 +156,6 @@ operation(): | Boolean success = store_conditional<32>(virtual_address, value, aq, rl, $encoding); X[rd] = success ? 0 : 1; - - sail(): | { if speculate_conditional () == false then { diff --git a/arch/inst/B/add.uw.yaml b/arch/inst/B/add.uw.yaml index f8aedbf6db..cf0ca7a24b 100644 --- a/arch/inst/B/add.uw.yaml +++ b/arch/inst/B/add.uw.yaml @@ -14,20 +14,20 @@ assembly: xd, xs1, xs2 encoding: match: 0000100----------000-----0111011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always vs: always vu: always pseudoinstructions: -- when: rs2 == 0 - to: zext.w xd, xs1 + - when: rs2 == 0 + to: zext.w xd, xs1 operation(): | if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) { raise (ExceptionCode::IllegalInstruction, mode(), $encoding); @@ -35,8 +35,6 @@ operation(): | X[rd] = X[rs2] + X[rs1][31:0]; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/andn.yaml b/arch/inst/B/andn.yaml index c377ce8a19..0b723e1ad3 100644 --- a/arch/inst/B/andn.yaml +++ b/arch/inst/B/andn.yaml @@ -13,12 +13,12 @@ assembly: xd, xs1, xs2 encoding: match: 0100000----------111-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -32,8 +32,6 @@ operation(): | X[rd] = X[rs2] & ~X[rs1]; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/bclr.yaml b/arch/inst/B/bclr.yaml index 03ebc50ba9..5de87be7a5 100644 --- a/arch/inst/B/bclr.yaml +++ b/arch/inst/B/bclr.yaml @@ -13,12 +13,12 @@ assembly: xd, xs1, xs2 encoding: match: 0100100----------001-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -32,8 +32,6 @@ operation(): | XReg index = X[rs2] & (xlen() - 1); X[rd] = X[rs1] & ~(1 << index); - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/bclri.yaml b/arch/inst/B/bclri.yaml index 7c270a8996..17739413fc 100644 --- a/arch/inst/B/bclri.yaml +++ b/arch/inst/B/bclri.yaml @@ -15,21 +15,21 @@ encoding: RV32: match: 0100100----------001-----0010011 variables: - - name: shamt - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: shamt + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 RV64: match: 010010-----------001-----0010011 variables: - - name: shamt - location: 25-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: shamt + location: 25-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -43,8 +43,6 @@ operation(): | XReg index = shamt & (xlen() - 1); X[rd] = X[rs1] & ~(1 << index); - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/bext.yaml b/arch/inst/B/bext.yaml index 92ea15b8f9..4aafdd2d31 100644 --- a/arch/inst/B/bext.yaml +++ b/arch/inst/B/bext.yaml @@ -13,12 +13,12 @@ assembly: xd, xs1, xs2 encoding: match: 0100100----------101-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -32,8 +32,6 @@ operation(): | XReg index = X[rs2] & (xlen() - 1); X[rd] = (X[rs1] >> index) & 1; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/bexti.yaml b/arch/inst/B/bexti.yaml index 44b5687851..1584b1af7b 100644 --- a/arch/inst/B/bexti.yaml +++ b/arch/inst/B/bexti.yaml @@ -15,21 +15,21 @@ encoding: RV32: match: 0100100----------101-----0010011 variables: - - name: shamt - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: shamt + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 RV64: match: 010010-----------101-----0010011 variables: - - name: shamt - location: 25-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: shamt + location: 25-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -43,8 +43,6 @@ operation(): | XReg index = shamt & (xlen() - 1); X[rd] = (X[rs1] >> index) & 1; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/binv.yaml b/arch/inst/B/binv.yaml index 40262f63b5..4d4af940d2 100644 --- a/arch/inst/B/binv.yaml +++ b/arch/inst/B/binv.yaml @@ -13,12 +13,12 @@ assembly: xd, xs1, xs2 encoding: match: 0110100----------001-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -32,8 +32,6 @@ operation(): | XReg index = X[rs2] & (xlen() - 1); X[rd] = X[rs1] ^ (1 << index); - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/binvi.yaml b/arch/inst/B/binvi.yaml index ac23c57758..6e1edf9bad 100644 --- a/arch/inst/B/binvi.yaml +++ b/arch/inst/B/binvi.yaml @@ -15,21 +15,21 @@ encoding: RV32: match: 0110100----------001-----0010011 variables: - - name: shamt - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: shamt + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 RV64: match: 011010-----------001-----0010011 variables: - - name: shamt - location: 25-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: shamt + location: 25-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -43,8 +43,6 @@ operation(): | XReg index = shamt & (xlen() - 1); X[rd] = X[rs1] ^ (1 << index); - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/bset.yaml b/arch/inst/B/bset.yaml index c0a5e04275..f3004636de 100644 --- a/arch/inst/B/bset.yaml +++ b/arch/inst/B/bset.yaml @@ -13,12 +13,12 @@ assembly: xd, xs1, xs2 encoding: match: 0010100----------001-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -32,8 +32,6 @@ operation(): | XReg index = X[rs2] & (xlen() - 1); X[rd] = X[rs1] | (1 << index); - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/bseti.yaml b/arch/inst/B/bseti.yaml index 9b9e69307f..56693a4a7d 100644 --- a/arch/inst/B/bseti.yaml +++ b/arch/inst/B/bseti.yaml @@ -15,21 +15,21 @@ encoding: RV32: match: 0010100----------001-----0010011 variables: - - name: shamt - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: shamt + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 RV64: match: 001010-----------001-----0010011 variables: - - name: shamt - location: 25-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: shamt + location: 25-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -43,8 +43,6 @@ operation(): | XReg index = shamt & (xlen() - 1); X[rd] = X[rs1] | (1 << index); - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/clmul.yaml b/arch/inst/B/clmul.yaml index 73529d0434..58c5a9fadb 100644 --- a/arch/inst/B/clmul.yaml +++ b/arch/inst/B/clmul.yaml @@ -12,12 +12,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000101----------001-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -41,8 +41,6 @@ operation(): | X[rd] = output; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/clmulh.yaml b/arch/inst/B/clmulh.yaml index 44b695eaf6..adae02b842 100644 --- a/arch/inst/B/clmulh.yaml +++ b/arch/inst/B/clmulh.yaml @@ -12,12 +12,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000101----------011-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -41,8 +41,6 @@ operation(): | X[rd] = output; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/clmulr.yaml b/arch/inst/B/clmulr.yaml index 7a4033f8a2..a56b2b8635 100644 --- a/arch/inst/B/clmulr.yaml +++ b/arch/inst/B/clmulr.yaml @@ -17,12 +17,12 @@ access: encoding: match: 0000101----------010-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 operation(): | if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) { raise (ExceptionCode::IllegalInstruction, mode(), $encoding); @@ -40,8 +40,6 @@ operation(): | X[rd] = output; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/clz.yaml b/arch/inst/B/clz.yaml index 4349b7bdab..38d9a6f3e9 100644 --- a/arch/inst/B/clz.yaml +++ b/arch/inst/B/clz.yaml @@ -15,10 +15,10 @@ assembly: xd, xs1 encoding: match: 011000000000-----001-----0010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -31,8 +31,6 @@ operation(): | X[rd] = (xlen() - 1) - $signed(highest_set_bit(X[rs1])); - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/clzw.yaml b/arch/inst/B/clzw.yaml index d0ede84fc3..8e3b006bda 100644 --- a/arch/inst/B/clzw.yaml +++ b/arch/inst/B/clzw.yaml @@ -15,10 +15,10 @@ assembly: xd, xs1 encoding: match: 011000000000-----001-----0011011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -31,8 +31,6 @@ operation(): | X[rd] = 31 - $signed(highest_set_bit(X[rs1][31:0])); - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/cpop.yaml b/arch/inst/B/cpop.yaml index cb9d5a6fea..6b47180986 100644 --- a/arch/inst/B/cpop.yaml +++ b/arch/inst/B/cpop.yaml @@ -24,10 +24,10 @@ assembly: xd, xs1 encoding: match: 011000000010-----001-----0010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -49,8 +49,6 @@ operation(): | X[rd] = bitcount; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/cpopw.yaml b/arch/inst/B/cpopw.yaml index f061ae07be..94d298d738 100644 --- a/arch/inst/B/cpopw.yaml +++ b/arch/inst/B/cpopw.yaml @@ -25,10 +25,10 @@ assembly: xd, xs1 encoding: match: 011000000010-----001-----0011011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -50,8 +50,6 @@ operation(): | X[rd] = bitcount; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/ctz.yaml b/arch/inst/B/ctz.yaml index d39a0f351f..51305dbdeb 100644 --- a/arch/inst/B/ctz.yaml +++ b/arch/inst/B/ctz.yaml @@ -16,10 +16,10 @@ assembly: xd, xs1 encoding: match: 011000000001-----001-----0010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -32,8 +32,6 @@ operation(): | X[rd] = (xlen() - 1) - $signed(lowest_set_bit(X[rs1])); - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/ctzw.yaml b/arch/inst/B/ctzw.yaml index 97ac4ee965..1db05c84fb 100644 --- a/arch/inst/B/ctzw.yaml +++ b/arch/inst/B/ctzw.yaml @@ -17,10 +17,10 @@ assembly: xd, xs1 encoding: match: 011000000001-----001-----0011011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -33,8 +33,6 @@ operation(): | X[rd] = (xlen() - 1) - $signed(lowest_set_bit(X[rs1][31:0])); - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/max.yaml b/arch/inst/B/max.yaml index aab1741110..e483a3f549 100644 --- a/arch/inst/B/max.yaml +++ b/arch/inst/B/max.yaml @@ -20,12 +20,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000101----------110-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -38,8 +38,6 @@ operation(): | X[rd] = ($signed(X[rs1]) > $signed(X[rs2])) ? X[rs1] : X[rs2]; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/maxu.yaml b/arch/inst/B/maxu.yaml index d2cb26ff25..9bc665aafc 100644 --- a/arch/inst/B/maxu.yaml +++ b/arch/inst/B/maxu.yaml @@ -12,12 +12,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000101----------111-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -30,8 +30,6 @@ operation(): | X[rd] = (X[rs1] > X[rs2]) ? X[rs1] : X[rs2]; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/min.yaml b/arch/inst/B/min.yaml index b7e838fd91..cd5fefc85c 100644 --- a/arch/inst/B/min.yaml +++ b/arch/inst/B/min.yaml @@ -12,12 +12,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000101----------100-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -30,8 +30,6 @@ operation(): | X[rd] = ($signed(X[rs1]) < $signed(X[rs2])) ? X[rs1] : X[rs2]; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/minu.yaml b/arch/inst/B/minu.yaml index 3a0038c2cd..1b6ace4e89 100644 --- a/arch/inst/B/minu.yaml +++ b/arch/inst/B/minu.yaml @@ -12,12 +12,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000101----------101-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -30,8 +30,6 @@ operation(): | X[rd] = (X[rs1] < X[rs2]) ? X[rs1] : X[rs2]; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/orc.b.yaml b/arch/inst/B/orc.b.yaml index 6fdedd6265..52ddd67be9 100644 --- a/arch/inst/B/orc.b.yaml +++ b/arch/inst/B/orc.b.yaml @@ -14,10 +14,10 @@ assembly: xd, xs1, xs2 encoding: match: 001010000111-----101-----0010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -37,8 +37,6 @@ operation(): | X[rd] = output; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/orn.yaml b/arch/inst/B/orn.yaml index 50f45f0c4d..3bd9e8642a 100644 --- a/arch/inst/B/orn.yaml +++ b/arch/inst/B/orn.yaml @@ -12,12 +12,12 @@ assembly: xd, xs1, xs2 encoding: match: 0100000----------110-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -31,8 +31,6 @@ operation(): | X[rd] = X[rs1] | ~X[rs2]; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/rev8.yaml b/arch/inst/B/rev8.yaml index 9506294256..f3a6702d5b 100644 --- a/arch/inst/B/rev8.yaml +++ b/arch/inst/B/rev8.yaml @@ -21,17 +21,17 @@ encoding: RV32: match: 011010011000-----101-----0010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 RV64: match: 011010111000-----101-----0010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -55,8 +55,6 @@ operation(): | X[rd] = output; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/rol.yaml b/arch/inst/B/rol.yaml index 251f039bf2..6f166de0f0 100644 --- a/arch/inst/B/rol.yaml +++ b/arch/inst/B/rol.yaml @@ -12,12 +12,12 @@ assembly: xd, xs1, xs2 encoding: match: 0110000----------001-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -33,8 +33,6 @@ operation(): | X[rd] = (X[rs1] << shamt) | (X[rs1] >> (xlen() - shamt)); - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/rolw.yaml b/arch/inst/B/rolw.yaml index daadd41df7..070c001dcd 100644 --- a/arch/inst/B/rolw.yaml +++ b/arch/inst/B/rolw.yaml @@ -14,12 +14,12 @@ base: 64 encoding: match: 0110000----------001-----0111011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -38,8 +38,6 @@ operation(): | X[rd] = {{32{unextended_result[31]}}, unextended_result}; - - sail(): | { let rs1_val = (X(rs1))[31..0]; diff --git a/arch/inst/B/ror.yaml b/arch/inst/B/ror.yaml index 1d75f3112e..df4dedf74c 100644 --- a/arch/inst/B/ror.yaml +++ b/arch/inst/B/ror.yaml @@ -12,12 +12,12 @@ assembly: xd, xs1, xs2 encoding: match: 0110000----------101-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -33,8 +33,6 @@ operation(): | X[rd] = (X[rs1] >> shamt) | (X[rs1] << (xlen() - shamt)); - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/rori.yaml b/arch/inst/B/rori.yaml index e664533739..b8e7023bc6 100644 --- a/arch/inst/B/rori.yaml +++ b/arch/inst/B/rori.yaml @@ -14,21 +14,21 @@ encoding: RV32: match: 0110000----------101-----0010011 variables: - - name: shamt - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: shamt + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 RV64: match: 011000-----------101-----0010011 variables: - - name: shamt - location: 25-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: shamt + location: 25-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -44,8 +44,6 @@ operation(): | X[rd] = (X[rs1] >> shamt) | (X[rs1] << (xlen() - shamt)); - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/roriw.yaml b/arch/inst/B/roriw.yaml index df7da5ab39..7e23ce7aab 100644 --- a/arch/inst/B/roriw.yaml +++ b/arch/inst/B/roriw.yaml @@ -15,12 +15,12 @@ base: 64 encoding: match: 0110000----------101-----0011011 variables: - - name: shamt - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: shamt + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -37,8 +37,6 @@ operation(): | XReg unextended_result = (X[rs1] >> shamt) | (X[rs1] << (32 - shamt)); X[rd] = {{32{unextended_result[31]}}, unextended_result}; - - sail(): | { let rs1_val = (X(rs1))[31..0]; diff --git a/arch/inst/B/rorw.yaml b/arch/inst/B/rorw.yaml index 62f4036d11..1ef4e63fc6 100644 --- a/arch/inst/B/rorw.yaml +++ b/arch/inst/B/rorw.yaml @@ -15,12 +15,12 @@ base: 64 encoding: match: 0110000----------101-----0111011 variables: - - name: shamt - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: shamt + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -38,8 +38,6 @@ operation(): | XReg unextended_result = (X[rs1] >> shamt) | (X[rs1] << (32 - shamt)); X[rd] = {{32{unextended_result[31]}}, unextended_result}; - - sail(): | { let rs1_val = (X(rs1))[31..0]; diff --git a/arch/inst/B/sext.b.yaml b/arch/inst/B/sext.b.yaml index a4d2a4bd47..84dfd40c4b 100644 --- a/arch/inst/B/sext.b.yaml +++ b/arch/inst/B/sext.b.yaml @@ -13,10 +13,10 @@ assembly: xd, xs1 encoding: match: 011000000100-----001-----0010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -33,8 +33,6 @@ operation(): | X[rd] = {{56{X[rs1][7]}}, X[rs1][7:0]}; } - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/sext.h.yaml b/arch/inst/B/sext.h.yaml index fe2054f4fa..d7a3a59f0c 100644 --- a/arch/inst/B/sext.h.yaml +++ b/arch/inst/B/sext.h.yaml @@ -13,10 +13,10 @@ assembly: xd, xs1 encoding: match: 011000000101-----001-----0010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -33,8 +33,6 @@ operation(): | X[rd] = {{48{X[rs1][15]}}, X[rs1][15:0]}; } - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/sh1add.uw.yaml b/arch/inst/B/sh1add.uw.yaml index 1d5ee52990..8883d4aa4e 100644 --- a/arch/inst/B/sh1add.uw.yaml +++ b/arch/inst/B/sh1add.uw.yaml @@ -14,12 +14,12 @@ base: 64 encoding: match: 0010000----------010-----0111011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 assembly: xd, xs1, xs2 access: s: always @@ -33,8 +33,6 @@ operation(): | X[rd] = X[rs2] + (X[rs1][31:0] << 1); - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/sh1add.yaml b/arch/inst/B/sh1add.yaml index 88c89a1e70..15f1e23d4b 100644 --- a/arch/inst/B/sh1add.yaml +++ b/arch/inst/B/sh1add.yaml @@ -12,12 +12,12 @@ assembly: xd, xs1, xs2 encoding: match: 0010000----------010-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -30,8 +30,6 @@ operation(): | X[rd] = X[rs2] + (X[rs1] << 1); - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/sh2add.uw.yaml b/arch/inst/B/sh2add.uw.yaml index 2256b8ff91..fd29fff5af 100644 --- a/arch/inst/B/sh2add.uw.yaml +++ b/arch/inst/B/sh2add.uw.yaml @@ -15,12 +15,12 @@ assembly: xd, xs1, xs2 encoding: match: 0010000----------100-----0111011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -33,8 +33,6 @@ operation(): | X[rd] = X[rs2] + (X[rs1][31:0] << 2); - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/sh2add.yaml b/arch/inst/B/sh2add.yaml index e0c7e3cc57..02b3905e2e 100644 --- a/arch/inst/B/sh2add.yaml +++ b/arch/inst/B/sh2add.yaml @@ -12,12 +12,12 @@ assembly: xd, xs1, xs2 encoding: match: 0010000----------100-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -30,8 +30,6 @@ operation(): | X[rd] = X[rs2] + (X[rs1] << 2); - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/sh3add.uw.yaml b/arch/inst/B/sh3add.uw.yaml index 9cc2a29a0f..d8b88d16b6 100644 --- a/arch/inst/B/sh3add.uw.yaml +++ b/arch/inst/B/sh3add.uw.yaml @@ -15,12 +15,12 @@ assembly: xd, xs1, xs2 encoding: match: 0010000----------110-----0111011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -33,8 +33,6 @@ operation(): | X[rd] = X[rs2] + (X[rs1][31:0] << 3); - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/sh3add.yaml b/arch/inst/B/sh3add.yaml index ace5749ef6..0ceefa2502 100644 --- a/arch/inst/B/sh3add.yaml +++ b/arch/inst/B/sh3add.yaml @@ -12,12 +12,12 @@ assembly: xd, xs1, xs2 encoding: match: 0010000----------110-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -30,8 +30,6 @@ operation(): | X[rd] = X[rs2] + (X[rs1] << 3); - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/slli.uw.yaml b/arch/inst/B/slli.uw.yaml index 47c9d7d5d4..4b5b11d838 100644 --- a/arch/inst/B/slli.uw.yaml +++ b/arch/inst/B/slli.uw.yaml @@ -16,12 +16,12 @@ base: 64 encoding: match: 000010-----------001-----0011011 variables: - - name: shamt - location: 25-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: shamt + location: 25-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 assembly: xd, xs1, shamt access: s: always @@ -35,8 +35,6 @@ operation(): | X[rd] = X[rs1][31:0] << shamt; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/xnor.yaml b/arch/inst/B/xnor.yaml index fc64d5e2ee..0afd1d30db 100644 --- a/arch/inst/B/xnor.yaml +++ b/arch/inst/B/xnor.yaml @@ -12,12 +12,12 @@ assembly: xd, xs1, xs2 encoding: match: 0100000----------100-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -31,8 +31,6 @@ operation(): | X[rd] = ~(X[rs1] ^ X[rs2]); - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/B/zext.h.yaml b/arch/inst/B/zext.h.yaml index 4e1b492f9f..247db427c5 100644 --- a/arch/inst/B/zext.h.yaml +++ b/arch/inst/B/zext.h.yaml @@ -19,19 +19,19 @@ encoding: RV32: match: 000010000000-----100-----0110011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 RV64: match: 000010000000-----100-----0111011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 excludedBy: - anyOf: [Zk, Zkn, Zks, Zbkb] # zext.h instruction is a pseudo-op for `packw` when `Zbkb` is implemented + anyOf: [Zk, Zkn, Zks, Zbkb] # zext.h instruction is a pseudo-op for `packw` when `Zbkb` is implemented assembly: xd, xs1 access: s: always @@ -45,8 +45,6 @@ operation(): | X[rd] = X[rs1][15:0]; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/C/c.add.yaml b/arch/inst/C/c.add.yaml index 678dfbb14a..c2249358b8 100644 --- a/arch/inst/C/c.add.yaml +++ b/arch/inst/C/c.add.yaml @@ -9,16 +9,16 @@ description: | C.ADD expands into `add rd, rd, rs2`. definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: xd, rs2 encoding: match: 1001----------10 variables: - - name: rs2 - location: 6-2 - - name: rd - location: 11-7 + - name: rs2 + location: 6-2 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/C/c.addi.yaml b/arch/inst/C/c.addi.yaml index 445543b1be..6263e0c8f0 100644 --- a/arch/inst/C/c.addi.yaml +++ b/arch/inst/C/c.addi.yaml @@ -11,18 +11,18 @@ description: | The code points with rd=x0 encode the C.NOP instruction; the remaining code points with imm=0 encode HINTs. definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: xd, imm encoding: match: 000-----------01 variables: - - name: imm - location: 12|6-2 - not: 0 - - name: rd - location: 11-7 - not: 0 + - name: imm + location: 12|6-2 + not: 0 + - name: rd + location: 11-7 + not: 0 access: s: always u: always diff --git a/arch/inst/C/c.addi16sp.yaml b/arch/inst/C/c.addi16sp.yaml index 5b3e531966..78cc3d1968 100644 --- a/arch/inst/C/c.addi16sp.yaml +++ b/arch/inst/C/c.addi16sp.yaml @@ -11,16 +11,16 @@ description: | C.ADDI16SP is only valid when nzimm ≠ 0; the code point with nzimm=0 is reserved. definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: imm encoding: match: 011-00010-----01 variables: - - name: imm - location: 12|4-3|5|2|6 - left_shift: 4 - not: 0 + - name: imm + location: 12|4-3|5|2|6 + left_shift: 4 + not: 0 access: s: always u: always diff --git a/arch/inst/C/c.addi4spn.yaml b/arch/inst/C/c.addi4spn.yaml index d51063be99..3da786baf0 100644 --- a/arch/inst/C/c.addi4spn.yaml +++ b/arch/inst/C/c.addi4spn.yaml @@ -11,18 +11,18 @@ description: | C.ADDI4SPN is only valid when nzuimm ≠ 0; the code points with nzuimm=0 are reserved. definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: xd, imm encoding: match: 000-----------00 variables: - - name: imm - location: 10-7|12-11|5|6 - left_shift: 2 - not: 0 - - name: rd - location: 4-2 + - name: imm + location: 10-7|12-11|5|6 + left_shift: 2 + not: 0 + - name: rd + location: 4-2 access: s: always u: always diff --git a/arch/inst/C/c.addiw.yaml b/arch/inst/C/c.addiw.yaml index a5c8220c9f..d1c409584b 100644 --- a/arch/inst/C/c.addiw.yaml +++ b/arch/inst/C/c.addiw.yaml @@ -11,18 +11,18 @@ description: | C.ADDIW is only valid when rd ≠ x0; the code points with rd=x0 are reserved. definedBy: anyOf: - - C - - Zca + - C + - Zca base: 64 assembly: xd, imm encoding: match: 001-----------01 variables: - - name: imm - location: 12|6-2 - - name: rd - location: 11-7 - not: 0 + - name: imm + location: 12|6-2 + - name: rd + location: 11-7 + not: 0 access: s: always u: always diff --git a/arch/inst/C/c.addw.yaml b/arch/inst/C/c.addw.yaml index 61ba1a41f0..a78674a86a 100644 --- a/arch/inst/C/c.addw.yaml +++ b/arch/inst/C/c.addw.yaml @@ -10,17 +10,17 @@ description: | C.ADDW expands into `addw rd, rd, rs2`. definedBy: anyOf: - - C - - Zca + - C + - Zca base: 64 assembly: xd, rs2 encoding: match: 100111---01---01 variables: - - name: rs2 - location: 4-2 - - name: rd - location: 9-7 + - name: rs2 + location: 4-2 + - name: rd + location: 9-7 access: s: always u: always diff --git a/arch/inst/C/c.and.yaml b/arch/inst/C/c.and.yaml index 6f365559b7..ba2648f0b8 100644 --- a/arch/inst/C/c.and.yaml +++ b/arch/inst/C/c.and.yaml @@ -10,16 +10,16 @@ description: | C.AND expands into `and rd, rd, rs2`. definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: xd, rs2 encoding: match: 100011---11---01 variables: - - name: rs2 - location: 4-2 - - name: rd - location: 9-7 + - name: rs2 + location: 4-2 + - name: rd + location: 9-7 access: s: always u: always diff --git a/arch/inst/C/c.andi.yaml b/arch/inst/C/c.andi.yaml index c32f5f8e70..3ef3ac838b 100644 --- a/arch/inst/C/c.andi.yaml +++ b/arch/inst/C/c.andi.yaml @@ -10,16 +10,16 @@ description: | C.ANDI expands into `andi rd, rd, imm`. definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: xd, imm encoding: match: 100-10--------01 variables: - - name: imm - location: 12|6-2 - - name: rd - location: 9-7 + - name: imm + location: 12|6-2 + - name: rd + location: 9-7 access: s: always u: always diff --git a/arch/inst/C/c.beqz.yaml b/arch/inst/C/c.beqz.yaml index 75d88ee548..b831bdf36d 100644 --- a/arch/inst/C/c.beqz.yaml +++ b/arch/inst/C/c.beqz.yaml @@ -9,17 +9,17 @@ description: | It expands to `beq` `rs1, x0, offset`. definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: xs1, imm encoding: match: 110-----------01 variables: - - name: imm - location: 12|6-5|2|11-10|4-3 - left_shift: 0 - - name: rs1 - location: 9-7 + - name: imm + location: 12|6-5|2|11-10|4-3 + left_shift: 0 + - name: rs1 + location: 9-7 access: s: always u: always diff --git a/arch/inst/C/c.bnez.yaml b/arch/inst/C/c.bnez.yaml index 91ee35e96d..aa4cb97a0f 100644 --- a/arch/inst/C/c.bnez.yaml +++ b/arch/inst/C/c.bnez.yaml @@ -9,17 +9,17 @@ description: | It expands to `beq` `rs1, x0, offset`. definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: xs1, imm encoding: match: 111-----------01 variables: - - name: imm - location: 12|6-5|2|11-10|4-3 - left_shift: 0 - - name: rs1 - location: 9-7 + - name: imm + location: 12|6-5|2|11-10|4-3 + left_shift: 0 + - name: rs1 + location: 9-7 access: s: always u: always diff --git a/arch/inst/C/c.ebreak.yaml b/arch/inst/C/c.ebreak.yaml index cb97f80589..09f19331d9 100644 --- a/arch/inst/C/c.ebreak.yaml +++ b/arch/inst/C/c.ebreak.yaml @@ -19,8 +19,8 @@ description: | and should not increment the `minstret` CSR. definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: " " encoding: match: "1001000000000010" diff --git a/arch/inst/C/c.fld.yaml b/arch/inst/C/c.fld.yaml index 4e2c54bca7..f4672ed0e9 100644 --- a/arch/inst/C/c.fld.yaml +++ b/arch/inst/C/c.fld.yaml @@ -11,19 +11,19 @@ description: | It expands to `fld` `rd, offset(rs1)`. definedBy: allOf: - - C - - D + - C + - D assembly: xd, imm(xs1) encoding: match: 001-----------00 variables: - - name: imm - location: 6-5|12-10 - left_shift: 3 - - name: rd - location: 4-2 - - name: rs1 - location: 9-7 + - name: imm + location: 6-5|12-10 + left_shift: 3 + - name: rd + location: 4-2 + - name: rs1 + location: 9-7 access: s: always u: always diff --git a/arch/inst/C/c.fldsp.yaml b/arch/inst/C/c.fldsp.yaml index da3ef66fa8..beb226b790 100644 --- a/arch/inst/C/c.fldsp.yaml +++ b/arch/inst/C/c.fldsp.yaml @@ -11,17 +11,17 @@ description: | It expands to `fld` `rd, offset(x2)`. definedBy: allOf: - - C - - D + - C + - D assembly: fd, imm(sp) encoding: match: 001-----------10 variables: - - name: imm - location: 4-2|12|6-5 - left_shift: 3 - - name: rd - location: 11-7 + - name: imm + location: 4-2|12|6-5 + left_shift: 3 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/C/c.flw.yaml b/arch/inst/C/c.flw.yaml index e99c975c33..80165e98b1 100644 --- a/arch/inst/C/c.flw.yaml +++ b/arch/inst/C/c.flw.yaml @@ -11,19 +11,19 @@ description: | It expands to `flw` `rd, offset(rs1)`. definedBy: allOf: - - C - - F + - C + - F assembly: xd, imm(xs1) encoding: match: 011-----------00 variables: - - name: imm - location: 5|12-10|6 - left_shift: 2 - - name: rd - location: 4-2 - - name: rs1 - location: 9-7 + - name: imm + location: 5|12-10|6 + left_shift: 2 + - name: rd + location: 4-2 + - name: rs1 + location: 9-7 access: s: always u: always diff --git a/arch/inst/C/c.flwsp.yaml b/arch/inst/C/c.flwsp.yaml index a92007cee3..0e50dbf1b3 100644 --- a/arch/inst/C/c.flwsp.yaml +++ b/arch/inst/C/c.flwsp.yaml @@ -11,17 +11,17 @@ description: | It expands to `flw` `rd, offset(x2)`. definedBy: allOf: - - C - - F + - C + - F assembly: fd, imm(sp) encoding: match: 011-----------10 variables: - - name: imm - location: 3-2|12|6-4 - left_shift: 2 - - name: rd - location: 11-7 + - name: imm + location: 3-2|12|6-4 + left_shift: 2 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/C/c.fsd.yaml b/arch/inst/C/c.fsd.yaml index b16493053c..22a1c37854 100644 --- a/arch/inst/C/c.fsd.yaml +++ b/arch/inst/C/c.fsd.yaml @@ -11,19 +11,19 @@ description: | It expands to `fsd` `rs2, offset(rs1)`. definedBy: allOf: - - C - - D + - C + - D assembly: xs2, imm(xs1) encoding: match: 101-----------00 variables: - - name: imm - location: 6-5|12-10 - left_shift: 3 - - name: rs2 - location: 4-2 - - name: rs1 - location: 9-7 + - name: imm + location: 6-5|12-10 + left_shift: 3 + - name: rs2 + location: 4-2 + - name: rs1 + location: 9-7 access: s: always u: always diff --git a/arch/inst/C/c.fsdsp.yaml b/arch/inst/C/c.fsdsp.yaml index 61c5cb4d32..185240e2c1 100644 --- a/arch/inst/C/c.fsdsp.yaml +++ b/arch/inst/C/c.fsdsp.yaml @@ -11,17 +11,17 @@ description: | It expands to `fsd` `rs2, offset(x2)`. definedBy: allOf: - - C - - D + - C + - D assembly: fs2, imm(sp) encoding: match: 101-----------10 variables: - - name: imm - location: 9-7|12-10 - left_shift: 3 - - name: rs2 - location: 6-2 + - name: imm + location: 9-7|12-10 + left_shift: 3 + - name: rs2 + location: 6-2 access: s: always u: always diff --git a/arch/inst/C/c.fsw.yaml b/arch/inst/C/c.fsw.yaml index b50f1f2574..704652115e 100644 --- a/arch/inst/C/c.fsw.yaml +++ b/arch/inst/C/c.fsw.yaml @@ -11,19 +11,19 @@ description: | It expands to `fsw` `rs2, offset(rs1)`. definedBy: allOf: - - C - - F + - C + - F assembly: xs2, imm(xs1) encoding: match: 111-----------00 variables: - - name: imm - location: 5|12-10|6 - left_shift: 2 - - name: rs2 - location: 4-2 - - name: rs1 - location: 9-7 + - name: imm + location: 5|12-10|6 + left_shift: 2 + - name: rs2 + location: 4-2 + - name: rs1 + location: 9-7 access: s: always u: always diff --git a/arch/inst/C/c.fswsp.yaml b/arch/inst/C/c.fswsp.yaml index e02c29024c..37cca7c629 100644 --- a/arch/inst/C/c.fswsp.yaml +++ b/arch/inst/C/c.fswsp.yaml @@ -11,17 +11,17 @@ description: | It expands to `fsw` `rs2, offset(x2)`. definedBy: allOf: - - C - - F + - C + - F assembly: fs2, imm(sp) encoding: match: 111-----------10 variables: - - name: imm - location: 8-7|12-9 - left_shift: 2 - - name: rs2 - location: 6-2 + - name: imm + location: 8-7|12-9 + left_shift: 2 + - name: rs2 + location: 6-2 access: s: always u: always diff --git a/arch/inst/C/c.j.yaml b/arch/inst/C/c.j.yaml index 1a4ba8a410..d1fb316eee 100644 --- a/arch/inst/C/c.j.yaml +++ b/arch/inst/C/c.j.yaml @@ -9,16 +9,16 @@ description: | It expands to `jal` `x0, offset`. definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: imm encoding: match: 101-----------01 variables: - - name: imm - location: 12|8|10-9|6|7|2|11|5-3 - left_shift: 1 - sign_extend: true + - name: imm + location: 12|8|10-9|6|7|2|11|5-3 + left_shift: 1 + sign_extend: true access: s: always u: always diff --git a/arch/inst/C/c.jal.yaml b/arch/inst/C/c.jal.yaml index 2b168b0018..6d397fcf0a 100644 --- a/arch/inst/C/c.jal.yaml +++ b/arch/inst/C/c.jal.yaml @@ -9,17 +9,17 @@ description: | It expands to `jal` `x1, offset`. definedBy: anyOf: - - C - - Zca + - C + - Zca base: 32 assembly: imm encoding: match: 001-----------01 variables: - - name: imm - location: 12|8|10-9|6|7|2|11|5-3 - left_shift: 1 - sign_extend: true + - name: imm + location: 12|8|10-9|6|7|2|11|5-3 + left_shift: 1 + sign_extend: true access: s: always u: always diff --git a/arch/inst/C/c.jalr.yaml b/arch/inst/C/c.jalr.yaml index 5865fceb4f..a6cd9ada2a 100644 --- a/arch/inst/C/c.jalr.yaml +++ b/arch/inst/C/c.jalr.yaml @@ -9,15 +9,15 @@ description: | C.JALR expands to jalr x1, 0(rs1). definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: xs1 encoding: match: 1001-----0000010 variables: - - name: rs1 - location: 11-7 - not: 0 + - name: rs1 + location: 11-7 + not: 0 access: s: always u: always diff --git a/arch/inst/C/c.jr.yaml b/arch/inst/C/c.jr.yaml index 97ede06383..18701146b7 100644 --- a/arch/inst/C/c.jr.yaml +++ b/arch/inst/C/c.jr.yaml @@ -9,15 +9,15 @@ description: | C.JR expands to jalr x0, 0(rs1). definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: xs1 encoding: match: 1000-----0000010 variables: - - name: rs1 - location: 11-7 - not: 0 + - name: rs1 + location: 11-7 + not: 0 access: s: always u: always diff --git a/arch/inst/C/c.ld.yaml b/arch/inst/C/c.ld.yaml index f34a728b61..b9d05dea03 100644 --- a/arch/inst/C/c.ld.yaml +++ b/arch/inst/C/c.ld.yaml @@ -11,19 +11,19 @@ description: | It expands to `ld` `rd, offset(rs1)`. definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: xd, imm(xs1) encoding: match: 011-----------00 variables: - - name: imm - location: 6-5|12-10 - left_shift: 3 - - name: rd - location: 4-2 - - name: rs1 - location: 9-7 + - name: imm + location: 6-5|12-10 + left_shift: 3 + - name: rd + location: 4-2 + - name: rs1 + location: 9-7 access: s: always u: always diff --git a/arch/inst/C/c.ldsp.yaml b/arch/inst/C/c.ldsp.yaml index 3094c36247..50786f1d7c 100644 --- a/arch/inst/C/c.ldsp.yaml +++ b/arch/inst/C/c.ldsp.yaml @@ -13,19 +13,19 @@ description: | C.LDSP is only valid when rd ≠ x0 the code points with rd=x0 are reserved. definedBy: anyOf: - - C - - Zca + - C + - Zca base: 64 assembly: xd, imm(sp) encoding: match: 011-----------10 variables: - - name: imm - location: 4-2|12|6-5 - left_shift: 3 - - name: rd - location: 11-7 - not: 0 + - name: imm + location: 4-2|12|6-5 + left_shift: 3 + - name: rd + location: 11-7 + not: 0 access: s: always u: always diff --git a/arch/inst/C/c.li.yaml b/arch/inst/C/c.li.yaml index e162bc7fb2..19f3fd4e74 100644 --- a/arch/inst/C/c.li.yaml +++ b/arch/inst/C/c.li.yaml @@ -10,17 +10,17 @@ description: | C.LI is only valid when rd ≠ x0; the code points with rd=x0 encode HINTs. definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: xd, imm encoding: match: 010-----------01 variables: - - name: imm - location: 12|6-2 - - name: rd - location: 11-7 - not: 0 + - name: imm + location: 12|6-2 + - name: rd + location: 11-7 + not: 0 access: s: always u: always diff --git a/arch/inst/C/c.lq.yaml b/arch/inst/C/c.lq.yaml index 12dfd83046..b6d5322982 100644 --- a/arch/inst/C/c.lq.yaml +++ b/arch/inst/C/c.lq.yaml @@ -11,19 +11,19 @@ description: | It expands to `lq` `rd, offset(rs1)`. definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: xd, imm(xs1) encoding: match: 001-----------00 variables: - - name: imm - location: 12-11|6-5|10 - left_shift: 4 - - name: rd - location: 4-2 - - name: rs1 - location: 9-7 + - name: imm + location: 12-11|6-5|10 + left_shift: 4 + - name: rd + location: 4-2 + - name: rs1 + location: 9-7 access: s: always u: always diff --git a/arch/inst/C/c.lqsp.yaml b/arch/inst/C/c.lqsp.yaml index 937857306c..adce782274 100644 --- a/arch/inst/C/c.lqsp.yaml +++ b/arch/inst/C/c.lqsp.yaml @@ -12,19 +12,19 @@ description: | C.LQSP is only valid when rd ≠ x0 the code points with rd=x0 are reserved. definedBy: anyOf: - - C - - Zca + - C + - Zca base: 64 assembly: xd, imm(sp) encoding: match: 001-----------10 variables: - - name: imm - location: 5-2|12|6 - left_shift: 4 - - name: rd - location: 11-7 - not: 0 + - name: imm + location: 5-2|12|6 + left_shift: 4 + - name: rd + location: 11-7 + not: 0 access: s: always u: always diff --git a/arch/inst/C/c.lui.yaml b/arch/inst/C/c.lui.yaml index 85c946574a..bf2cca884f 100644 --- a/arch/inst/C/c.lui.yaml +++ b/arch/inst/C/c.lui.yaml @@ -11,18 +11,18 @@ description: | The code points with imm=0 are reserved; the remaining code points with rd=x0 are HINTs; and the remaining code points with rd=x2 correspond to the C.ADDI16SP instruction definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: xd, imm encoding: match: 011-----------01 variables: - - name: imm - location: 12|6-2 - left_shift: 12 - - name: rd - location: 11-7 - not: [0, 2] + - name: imm + location: 12|6-2 + left_shift: 12 + - name: rd + location: 11-7 + not: [0, 2] access: s: always u: always diff --git a/arch/inst/C/c.lw.yaml b/arch/inst/C/c.lw.yaml index 91c2d3a60f..da6019aa9d 100644 --- a/arch/inst/C/c.lw.yaml +++ b/arch/inst/C/c.lw.yaml @@ -11,19 +11,19 @@ description: | It expands to `lw` `rd, offset(rs1)`. definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: xd, imm(xs1) encoding: match: 010-----------00 variables: - - name: imm - location: 5|12-10|6 - left_shift: 2 - - name: rd - location: 4-2 - - name: rs1 - location: 9-7 + - name: imm + location: 5|12-10|6 + left_shift: 2 + - name: rd + location: 4-2 + - name: rs1 + location: 9-7 access: s: always u: always diff --git a/arch/inst/C/c.lwsp.yaml b/arch/inst/C/c.lwsp.yaml index 93e03f9b15..3c4e820518 100644 --- a/arch/inst/C/c.lwsp.yaml +++ b/arch/inst/C/c.lwsp.yaml @@ -12,18 +12,18 @@ description: | C.LWSP is only valid when rd ≠ x0. The code points with rd=x0 are reserved. definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: xd, imm(sp) encoding: match: 010-----------10 variables: - - name: imm - location: 3-2|12|6-4 - left_shift: 2 - - name: rd - location: 11-7 - not: 0 + - name: imm + location: 3-2|12|6-4 + left_shift: 2 + - name: rd + location: 11-7 + not: 0 access: s: always u: always diff --git a/arch/inst/C/c.mv.yaml b/arch/inst/C/c.mv.yaml index 0bd2a872b8..36e97e4d10 100644 --- a/arch/inst/C/c.mv.yaml +++ b/arch/inst/C/c.mv.yaml @@ -9,18 +9,18 @@ description: | C.MV expands to addi rd, x0, rs2. definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: xd, xs2 encoding: match: 1000----------10 variables: - - name: rd - location: 11-7 - not: 0 - - name: rs2 - location: 6-2 - not: 0 + - name: rd + location: 11-7 + not: 0 + - name: rs2 + location: 6-2 + not: 0 access: s: always u: always diff --git a/arch/inst/C/c.nop.yaml b/arch/inst/C/c.nop.yaml index 804e23ed07..60bdb525ba 100644 --- a/arch/inst/C/c.nop.yaml +++ b/arch/inst/C/c.nop.yaml @@ -8,15 +8,15 @@ description: | C.NOP expands into `addi x0, x0, imm`. definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: imm encoding: match: 000-00000-----01 variables: - - name: imm - location: 12|6-2 - not: 0 + - name: imm + location: 12|6-2 + not: 0 access: s: always u: always diff --git a/arch/inst/C/c.or.yaml b/arch/inst/C/c.or.yaml index 29c2e379af..b14f348c1a 100644 --- a/arch/inst/C/c.or.yaml +++ b/arch/inst/C/c.or.yaml @@ -10,16 +10,16 @@ description: | C.OR expands into `or rd, rd, rs2`. definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: xd, rs2 encoding: match: 100011---10---01 variables: - - name: rs2 - location: 4-2 - - name: rd - location: 9-7 + - name: rs2 + location: 4-2 + - name: rd + location: 9-7 access: s: always u: always diff --git a/arch/inst/C/c.sd.yaml b/arch/inst/C/c.sd.yaml index ccb9b2d841..b44bd27459 100644 --- a/arch/inst/C/c.sd.yaml +++ b/arch/inst/C/c.sd.yaml @@ -11,19 +11,19 @@ description: | It expands to `sd` `rs2, offset(rs1)`. definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: xs2, imm(xs1) encoding: match: 111-----------00 variables: - - name: imm - location: 6-5|12-10 - left_shift: 3 - - name: rs2 - location: 4-2 - - name: rs1 - location: 9-7 + - name: imm + location: 6-5|12-10 + left_shift: 3 + - name: rs2 + location: 4-2 + - name: rs1 + location: 9-7 access: s: always u: always diff --git a/arch/inst/C/c.sdsp.yaml b/arch/inst/C/c.sdsp.yaml index 9c1f3a4cc5..d5d0d1c462 100644 --- a/arch/inst/C/c.sdsp.yaml +++ b/arch/inst/C/c.sdsp.yaml @@ -11,18 +11,18 @@ description: | It expands to `sd` `rs2, offset(x2)`. definedBy: anyOf: - - C - - Zca + - C + - Zca base: 64 assembly: xs2, imm(sp) encoding: match: 111-----------10 variables: - - name: imm - location: 9-7|12-10 - left_shift: 3 - - name: rs2 - location: 6-2 + - name: imm + location: 9-7|12-10 + left_shift: 3 + - name: rs2 + location: 6-2 access: s: always u: always diff --git a/arch/inst/C/c.slli.yaml b/arch/inst/C/c.slli.yaml index 34457091fe..f678469d8f 100644 --- a/arch/inst/C/c.slli.yaml +++ b/arch/inst/C/c.slli.yaml @@ -9,17 +9,17 @@ description: | C.SLLI expands into `slli rd, rd, shamt`. definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: xd, shamt encoding: match: 000-----------10 variables: - - name: shamt - location: 12|6-2 - - name: rd - location: 11-7 - not: 0 + - name: shamt + location: 12|6-2 + - name: rd + location: 11-7 + not: 0 access: s: always u: always diff --git a/arch/inst/C/c.sq.yaml b/arch/inst/C/c.sq.yaml index 7fa5127683..24fb6f1fd5 100644 --- a/arch/inst/C/c.sq.yaml +++ b/arch/inst/C/c.sq.yaml @@ -11,19 +11,19 @@ description: | It expands to `sq` `rs2, offset(rs1)`. definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: xs2, imm(xs1) encoding: match: 101-----------00 variables: - - name: imm - location: 12-11|6-5|10 - left_shift: 4 - - name: rs2 - location: 4-2 - - name: rs1 - location: 9-7 + - name: imm + location: 12-11|6-5|10 + left_shift: 4 + - name: rs2 + location: 4-2 + - name: rs1 + location: 9-7 access: s: always u: always diff --git a/arch/inst/C/c.sqsp.yaml b/arch/inst/C/c.sqsp.yaml index f2f0e486f8..107e1981da 100644 --- a/arch/inst/C/c.sqsp.yaml +++ b/arch/inst/C/c.sqsp.yaml @@ -11,18 +11,18 @@ description: | It expands to `sq` `rs2, offset(x2)`. definedBy: anyOf: - - C - - Zca + - C + - Zca base: 64 assembly: xs2, imm(sp) encoding: match: 101-----------10 variables: - - name: imm - location: 10-7|12-11 - left_shift: 4 - - name: rs2 - location: 6-2 + - name: imm + location: 10-7|12-11 + left_shift: 4 + - name: rs2 + location: 6-2 access: s: always u: always diff --git a/arch/inst/C/c.srai.yaml b/arch/inst/C/c.srai.yaml index 1f3a70b164..eb49c07cf1 100644 --- a/arch/inst/C/c.srai.yaml +++ b/arch/inst/C/c.srai.yaml @@ -10,16 +10,16 @@ description: | C.SRAI expands into `srai rd, rd, shamt`. definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: xd, shamt encoding: match: 100-01--------01 variables: - - name: shamt - location: 12|6-2 - - name: rd - location: 9-7 + - name: shamt + location: 12|6-2 + - name: rd + location: 9-7 access: s: always u: always diff --git a/arch/inst/C/c.srli.yaml b/arch/inst/C/c.srli.yaml index 51b246f48b..cb18fa23c7 100644 --- a/arch/inst/C/c.srli.yaml +++ b/arch/inst/C/c.srli.yaml @@ -10,16 +10,16 @@ description: | C.SRLI expands into `srli rd, rd, shamt`. definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: xd, shamt encoding: match: 100-00--------01 variables: - - name: shamt - location: 12|6-2 - - name: rd - location: 9-7 + - name: shamt + location: 12|6-2 + - name: rd + location: 9-7 access: s: always u: always diff --git a/arch/inst/C/c.sub.yaml b/arch/inst/C/c.sub.yaml index 60af66e88e..32757173a0 100644 --- a/arch/inst/C/c.sub.yaml +++ b/arch/inst/C/c.sub.yaml @@ -10,16 +10,16 @@ description: | C.SUB expands into `sub rd, rd, rs2`. definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: xd, rs2 encoding: match: 100011---00---01 variables: - - name: rs2 - location: 4-2 - - name: rd - location: 9-7 + - name: rs2 + location: 4-2 + - name: rd + location: 9-7 access: s: always u: always diff --git a/arch/inst/C/c.subw.yaml b/arch/inst/C/c.subw.yaml index 2e45ead861..36ecadfe50 100644 --- a/arch/inst/C/c.subw.yaml +++ b/arch/inst/C/c.subw.yaml @@ -10,17 +10,17 @@ description: | C.SUBW expands into `subw rd, rd, rs2`. definedBy: anyOf: - - C - - Zca + - C + - Zca base: 64 assembly: xd, rs2 encoding: match: 100111---00---01 variables: - - name: rs2 - location: 4-2 - - name: rd - location: 9-7 + - name: rs2 + location: 4-2 + - name: rd + location: 9-7 access: s: always u: always diff --git a/arch/inst/C/c.sw.yaml b/arch/inst/C/c.sw.yaml index 2717ce020e..f2ac18a3d1 100644 --- a/arch/inst/C/c.sw.yaml +++ b/arch/inst/C/c.sw.yaml @@ -11,19 +11,19 @@ description: | It expands to `sw` `rs2, offset(rs1)`. definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: xs2, imm(xs1) encoding: match: 110-----------00 variables: - - name: imm - location: 5|12-10|6 - left_shift: 2 - - name: rs2 - location: 4-2 - - name: rs1 - location: 9-7 + - name: imm + location: 5|12-10|6 + left_shift: 2 + - name: rs2 + location: 4-2 + - name: rs1 + location: 9-7 access: s: always u: always diff --git a/arch/inst/C/c.swsp.yaml b/arch/inst/C/c.swsp.yaml index 1327b350f3..dedf9e04cf 100644 --- a/arch/inst/C/c.swsp.yaml +++ b/arch/inst/C/c.swsp.yaml @@ -11,17 +11,17 @@ description: | It expands to `sw` `rs2, offset(x2)`. definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: xs2, imm(sp) encoding: match: 110-----------10 variables: - - name: imm - location: 8-7|12-9 - left_shift: 2 - - name: rs2 - location: 6-2 + - name: imm + location: 8-7|12-9 + left_shift: 2 + - name: rs2 + location: 6-2 access: s: always u: always diff --git a/arch/inst/C/c.xor.yaml b/arch/inst/C/c.xor.yaml index ca04d2a183..5700c7b631 100644 --- a/arch/inst/C/c.xor.yaml +++ b/arch/inst/C/c.xor.yaml @@ -10,16 +10,16 @@ description: | C.XOR expands into `xor rd, rd, rs2`. definedBy: anyOf: - - C - - Zca + - C + - Zca assembly: xd, rs2 encoding: match: 100011---01---01 variables: - - name: rs2 - location: 4-2 - - name: rd - location: 9-7 + - name: rs2 + location: 4-2 + - name: rd + location: 9-7 access: s: always u: always diff --git a/arch/inst/D/fadd.d.yaml b/arch/inst/D/fadd.d.yaml index 78b384072f..2256219feb 100644 --- a/arch/inst/D/fadd.d.yaml +++ b/arch/inst/D/fadd.d.yaml @@ -5,20 +5,20 @@ kind: instruction name: fadd.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1, xs2, rm encoding: match: 0000001------------------1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fclass.d.yaml b/arch/inst/D/fclass.d.yaml index 06bd14a880..81874ef665 100644 --- a/arch/inst/D/fclass.d.yaml +++ b/arch/inst/D/fclass.d.yaml @@ -5,16 +5,16 @@ kind: instruction name: fclass.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1 encoding: match: 111000100000-----001-----1010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fcvt.d.l.yaml b/arch/inst/D/fcvt.d.l.yaml index 1754fe9c3a..e44cff7f88 100644 --- a/arch/inst/D/fcvt.d.l.yaml +++ b/arch/inst/D/fcvt.d.l.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.d.l long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1, rm encoding: match: 110100100010-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fcvt.d.lu.yaml b/arch/inst/D/fcvt.d.lu.yaml index 71cc3e6ecf..d1187f9809 100644 --- a/arch/inst/D/fcvt.d.lu.yaml +++ b/arch/inst/D/fcvt.d.lu.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.d.lu long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1, rm encoding: match: 110100100011-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fcvt.d.s.yaml b/arch/inst/D/fcvt.d.s.yaml index 19fd2e7d7f..933be04fb7 100644 --- a/arch/inst/D/fcvt.d.s.yaml +++ b/arch/inst/D/fcvt.d.s.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.d.s long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1, rm encoding: match: 010000100000-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fcvt.d.w.yaml b/arch/inst/D/fcvt.d.w.yaml index cefecd9309..202fa13708 100644 --- a/arch/inst/D/fcvt.d.w.yaml +++ b/arch/inst/D/fcvt.d.w.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.d.w long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1, rm encoding: match: 110100100000-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fcvt.d.wu.yaml b/arch/inst/D/fcvt.d.wu.yaml index 9a05ce0389..54eed68ce6 100644 --- a/arch/inst/D/fcvt.d.wu.yaml +++ b/arch/inst/D/fcvt.d.wu.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.d.wu long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1, rm encoding: match: 110100100001-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fcvt.l.d.yaml b/arch/inst/D/fcvt.l.d.yaml index 20352af5dc..4460b3ddd9 100644 --- a/arch/inst/D/fcvt.l.d.yaml +++ b/arch/inst/D/fcvt.l.d.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.l.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1, rm encoding: match: 110000100010-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fcvt.lu.d.yaml b/arch/inst/D/fcvt.lu.d.yaml index f2e1f103ef..dd7a24e59d 100644 --- a/arch/inst/D/fcvt.lu.d.yaml +++ b/arch/inst/D/fcvt.lu.d.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.lu.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1, rm encoding: match: 110000100011-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fcvt.s.d.yaml b/arch/inst/D/fcvt.s.d.yaml index 6f69d76383..f76d003e2c 100644 --- a/arch/inst/D/fcvt.s.d.yaml +++ b/arch/inst/D/fcvt.s.d.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.s.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1, rm encoding: match: 010000000001-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fcvt.w.d.yaml b/arch/inst/D/fcvt.w.d.yaml index 243fc56946..076e8900cc 100644 --- a/arch/inst/D/fcvt.w.d.yaml +++ b/arch/inst/D/fcvt.w.d.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.w.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1, rm encoding: match: 110000100000-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fcvt.wu.d.yaml b/arch/inst/D/fcvt.wu.d.yaml index abd390d4d1..2653f58af3 100644 --- a/arch/inst/D/fcvt.wu.d.yaml +++ b/arch/inst/D/fcvt.wu.d.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.wu.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1, rm encoding: match: 110000100001-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fcvtmod.w.d.yaml b/arch/inst/D/fcvtmod.w.d.yaml index d890f78faf..efd9414d18 100644 --- a/arch/inst/D/fcvtmod.w.d.yaml +++ b/arch/inst/D/fcvtmod.w.d.yaml @@ -5,17 +5,17 @@ kind: instruction name: fcvtmod.w.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [D, Zfa] assembly: xd, xs1 encoding: match: 110000101000-----001-----1010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fdiv.d.yaml b/arch/inst/D/fdiv.d.yaml index a3c17b19a3..05c6cbd8e7 100644 --- a/arch/inst/D/fdiv.d.yaml +++ b/arch/inst/D/fdiv.d.yaml @@ -5,20 +5,20 @@ kind: instruction name: fdiv.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1, xs2, rm encoding: match: 0001101------------------1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/feq.d.yaml b/arch/inst/D/feq.d.yaml index e3249eca67..1b008186d2 100644 --- a/arch/inst/D/feq.d.yaml +++ b/arch/inst/D/feq.d.yaml @@ -5,18 +5,18 @@ kind: instruction name: feq.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1, xs2 encoding: match: 1010001----------010-----1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fld.yaml b/arch/inst/D/fld.yaml index cc6a602560..7623d079de 100644 --- a/arch/inst/D/fld.yaml +++ b/arch/inst/D/fld.yaml @@ -5,18 +5,18 @@ kind: instruction name: fld long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1, imm encoding: match: -----------------011-----0000111 variables: - - name: imm - location: 31-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: imm + location: 31-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fle.d.yaml b/arch/inst/D/fle.d.yaml index 149a7ee354..d5cb10f861 100644 --- a/arch/inst/D/fle.d.yaml +++ b/arch/inst/D/fle.d.yaml @@ -5,18 +5,18 @@ kind: instruction name: fle.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1, xs2 encoding: match: 1010001----------000-----1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fleq.d.yaml b/arch/inst/D/fleq.d.yaml index 2046c32a7c..f83760edd7 100644 --- a/arch/inst/D/fleq.d.yaml +++ b/arch/inst/D/fleq.d.yaml @@ -5,19 +5,19 @@ kind: instruction name: fleq.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [D, Zfa] assembly: xd, xs1, xs2 encoding: match: 1010001----------100-----1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fli.d.yaml b/arch/inst/D/fli.d.yaml index 113895fc0c..9e226b79d1 100644 --- a/arch/inst/D/fli.d.yaml +++ b/arch/inst/D/fli.d.yaml @@ -5,17 +5,17 @@ kind: instruction name: fli.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [D, Zfa] assembly: xd, xs1 encoding: match: 111100100001-----000-----1010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/flt.d.yaml b/arch/inst/D/flt.d.yaml index 8ab8d19961..5b37dcb961 100644 --- a/arch/inst/D/flt.d.yaml +++ b/arch/inst/D/flt.d.yaml @@ -5,18 +5,18 @@ kind: instruction name: flt.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1, xs2 encoding: match: 1010001----------001-----1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fltq.d.yaml b/arch/inst/D/fltq.d.yaml index 63b1e93ed1..2e662b2602 100644 --- a/arch/inst/D/fltq.d.yaml +++ b/arch/inst/D/fltq.d.yaml @@ -5,19 +5,19 @@ kind: instruction name: fltq.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [D, Zfa] assembly: xd, xs1, xs2 encoding: match: 1010001----------101-----1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fmadd.d.yaml b/arch/inst/D/fmadd.d.yaml index c269141a7a..3a04f8abfc 100644 --- a/arch/inst/D/fmadd.d.yaml +++ b/arch/inst/D/fmadd.d.yaml @@ -5,22 +5,22 @@ kind: instruction name: fmadd.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1, xs2, xs3, rm encoding: match: -----01------------------1000011 variables: - - name: rs3 - location: 31-27 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs3 + location: 31-27 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fmax.d.yaml b/arch/inst/D/fmax.d.yaml index 4e35cc44ca..33ab9e2a8f 100644 --- a/arch/inst/D/fmax.d.yaml +++ b/arch/inst/D/fmax.d.yaml @@ -5,18 +5,18 @@ kind: instruction name: fmax.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1, xs2 encoding: match: 0010101----------001-----1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fmaxm.d.yaml b/arch/inst/D/fmaxm.d.yaml index 37765a2a53..0cce65dfaf 100644 --- a/arch/inst/D/fmaxm.d.yaml +++ b/arch/inst/D/fmaxm.d.yaml @@ -5,19 +5,19 @@ kind: instruction name: fmaxm.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [D, Zfa] assembly: xd, xs1, xs2 encoding: match: 0010101----------011-----1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fmin.d.yaml b/arch/inst/D/fmin.d.yaml index b918994061..56ab0470c4 100644 --- a/arch/inst/D/fmin.d.yaml +++ b/arch/inst/D/fmin.d.yaml @@ -5,18 +5,18 @@ kind: instruction name: fmin.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1, xs2 encoding: match: 0010101----------000-----1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fminm.d.yaml b/arch/inst/D/fminm.d.yaml index 06ef3eae89..7dc713939d 100644 --- a/arch/inst/D/fminm.d.yaml +++ b/arch/inst/D/fminm.d.yaml @@ -5,19 +5,19 @@ kind: instruction name: fminm.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [D, Zfa] assembly: xd, xs1, xs2 encoding: match: 0010101----------010-----1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fmsub.d.yaml b/arch/inst/D/fmsub.d.yaml index 3d582fdf96..025ebd63aa 100644 --- a/arch/inst/D/fmsub.d.yaml +++ b/arch/inst/D/fmsub.d.yaml @@ -5,22 +5,22 @@ kind: instruction name: fmsub.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1, xs2, xs3, rm encoding: match: -----01------------------1000111 variables: - - name: rs3 - location: 31-27 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs3 + location: 31-27 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fmul.d.yaml b/arch/inst/D/fmul.d.yaml index 5a7d07db6f..9d632cb380 100644 --- a/arch/inst/D/fmul.d.yaml +++ b/arch/inst/D/fmul.d.yaml @@ -5,20 +5,20 @@ kind: instruction name: fmul.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1, xs2, rm encoding: match: 0001001------------------1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fmv.d.x.yaml b/arch/inst/D/fmv.d.x.yaml index 62007aaf2b..a941327983 100644 --- a/arch/inst/D/fmv.d.x.yaml +++ b/arch/inst/D/fmv.d.x.yaml @@ -5,16 +5,16 @@ kind: instruction name: fmv.d.x long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1 encoding: match: 111100100000-----000-----1010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fmv.x.d.yaml b/arch/inst/D/fmv.x.d.yaml index 729fe7dc96..e6880c94a7 100644 --- a/arch/inst/D/fmv.x.d.yaml +++ b/arch/inst/D/fmv.x.d.yaml @@ -5,16 +5,16 @@ kind: instruction name: fmv.x.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1 encoding: match: 111000100000-----000-----1010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fmvh.x.d.yaml b/arch/inst/D/fmvh.x.d.yaml index 86f7d4976b..20ec6fa419 100644 --- a/arch/inst/D/fmvh.x.d.yaml +++ b/arch/inst/D/fmvh.x.d.yaml @@ -5,17 +5,17 @@ kind: instruction name: fmvh.x.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [D, Zfa] assembly: xd, xs1 encoding: match: 111000100001-----000-----1010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fmvp.d.x.yaml b/arch/inst/D/fmvp.d.x.yaml index c44068bb4c..6755e561c7 100644 --- a/arch/inst/D/fmvp.d.x.yaml +++ b/arch/inst/D/fmvp.d.x.yaml @@ -5,19 +5,19 @@ kind: instruction name: fmvp.d.x long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [D, Zfa] assembly: xd, xs1, xs2 encoding: match: 1011001----------000-----1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fnmadd.d.yaml b/arch/inst/D/fnmadd.d.yaml index 6e73fcf6f1..876bf51c5f 100644 --- a/arch/inst/D/fnmadd.d.yaml +++ b/arch/inst/D/fnmadd.d.yaml @@ -5,22 +5,22 @@ kind: instruction name: fnmadd.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1, xs2, xs3, rm encoding: match: -----01------------------1001111 variables: - - name: rs3 - location: 31-27 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs3 + location: 31-27 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fnmsub.d.yaml b/arch/inst/D/fnmsub.d.yaml index f9f49cee5a..d19d53ad41 100644 --- a/arch/inst/D/fnmsub.d.yaml +++ b/arch/inst/D/fnmsub.d.yaml @@ -5,22 +5,22 @@ kind: instruction name: fnmsub.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1, xs2, xs3, rm encoding: match: -----01------------------1001011 variables: - - name: rs3 - location: 31-27 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs3 + location: 31-27 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fround.d.yaml b/arch/inst/D/fround.d.yaml index b67de8da0f..c9cc9d890d 100644 --- a/arch/inst/D/fround.d.yaml +++ b/arch/inst/D/fround.d.yaml @@ -5,19 +5,19 @@ kind: instruction name: fround.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [D, Zfa] assembly: xd, xs1, rm encoding: match: 010000100100-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/froundnx.d.yaml b/arch/inst/D/froundnx.d.yaml index 411f4c8a69..e20c585e8f 100644 --- a/arch/inst/D/froundnx.d.yaml +++ b/arch/inst/D/froundnx.d.yaml @@ -5,19 +5,19 @@ kind: instruction name: froundnx.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [D, Zfa] assembly: xd, xs1, rm encoding: match: 010000100101-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fsd.yaml b/arch/inst/D/fsd.yaml index 989b892002..f5f188def8 100644 --- a/arch/inst/D/fsd.yaml +++ b/arch/inst/D/fsd.yaml @@ -5,18 +5,18 @@ kind: instruction name: fsd long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xs1, xs2, imm encoding: match: -----------------011-----0100111 variables: - - name: imm - location: 31-25|11-7 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 + - name: imm + location: 31-25|11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 access: s: always u: always diff --git a/arch/inst/D/fsgnj.d.yaml b/arch/inst/D/fsgnj.d.yaml index fdab3944f8..6011bc7d83 100644 --- a/arch/inst/D/fsgnj.d.yaml +++ b/arch/inst/D/fsgnj.d.yaml @@ -5,18 +5,18 @@ kind: instruction name: fsgnj.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1, xs2 encoding: match: 0010001----------000-----1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fsgnjn.d.yaml b/arch/inst/D/fsgnjn.d.yaml index 6e7a206f8b..a26814ac5e 100644 --- a/arch/inst/D/fsgnjn.d.yaml +++ b/arch/inst/D/fsgnjn.d.yaml @@ -5,18 +5,18 @@ kind: instruction name: fsgnjn.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1, xs2 encoding: match: 0010001----------001-----1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fsgnjx.d.yaml b/arch/inst/D/fsgnjx.d.yaml index b4e55c47c5..b2ffc31622 100644 --- a/arch/inst/D/fsgnjx.d.yaml +++ b/arch/inst/D/fsgnjx.d.yaml @@ -5,18 +5,18 @@ kind: instruction name: fsgnjx.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1, xs2 encoding: match: 0010001----------010-----1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fsqrt.d.yaml b/arch/inst/D/fsqrt.d.yaml index 657abdfa79..05afdf5837 100644 --- a/arch/inst/D/fsqrt.d.yaml +++ b/arch/inst/D/fsqrt.d.yaml @@ -5,18 +5,18 @@ kind: instruction name: fsqrt.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1, rm encoding: match: 010110100000-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/D/fsub.d.yaml b/arch/inst/D/fsub.d.yaml index 1bddc6665f..5675815fec 100644 --- a/arch/inst/D/fsub.d.yaml +++ b/arch/inst/D/fsub.d.yaml @@ -5,20 +5,20 @@ kind: instruction name: fsub.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: D assembly: xd, xs1, xs2, rm encoding: match: 0000101------------------1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/F/fadd.s.yaml b/arch/inst/F/fadd.s.yaml index fdaa843306..f82a7e2ded 100644 --- a/arch/inst/F/fadd.s.yaml +++ b/arch/inst/F/fadd.s.yaml @@ -5,20 +5,20 @@ kind: instruction name: fadd.s long_name: No synopsis available. description: | - No description available. + No description available. definedBy: F assembly: fd, fs1, fs2, rm encoding: match: 0000000------------------1010011 variables: - - name: fs2 - location: 24-20 - - name: fs1 - location: 19-15 - - name: rm - location: 14-12 - - name: fd - location: 11-7 + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 access: s: always u: always @@ -26,8 +26,6 @@ access: vu: always data_independent_timing: true operation(): | - RoundingMode mode = rm_to_mode(X[rm], $encoding); - X[fd] = f32_add(X[fs1], X[fs2], mode); sail(): | { diff --git a/arch/inst/F/fclass.s.yaml b/arch/inst/F/fclass.s.yaml index 29f391926f..4e559a1d1e 100644 --- a/arch/inst/F/fclass.s.yaml +++ b/arch/inst/F/fclass.s.yaml @@ -5,41 +5,41 @@ kind: instruction name: fclass.s long_name: Single-precision floating-point classify. description: | - The `fclass.s` instruction examines the value in floating-point register - _fs1_ and writes to integer register _rd_ a 10-bit mask that indicates - the class of the floating-point number. - The format of the mask is described in the table below. - The corresponding bit in _rd_ will be set if the property is true and - clear otherwise. - All other bits in _rd_ are cleared. - Note that exactly one bit in rd will be set. - `fclass.s` does not set the floating-point exception flags. + The `fclass.s` instruction examines the value in floating-point register + _fs1_ and writes to integer register _rd_ a 10-bit mask that indicates + the class of the floating-point number. + The format of the mask is described in the table below. + The corresponding bit in _rd_ will be set if the property is true and + clear otherwise. + All other bits in _rd_ are cleared. + Note that exactly one bit in rd will be set. + `fclass.s` does not set the floating-point exception flags. - .Format of result of `fclass` instruction. - [%autowidth,float="center",align="center",cols="^,<",options="header",] - |=== - |_rd_ bit |Meaning - |0 |_rs1_ is latexmath:[$-\infty$]. - |1 |_rs1_ is a negative normal number. - |2 |_rs1_ is a negative subnormal number. - |3 |_rs1_ is latexmath:[$-0$]. - |4 |_rs1_ is latexmath:[$+0$]. - |5 |_rs1_ is a positive subnormal number. - |6 |_rs1_ is a positive normal number. - |7 |_rs1_ is latexmath:[$+\infty$]. - |8 |_rs1_ is a signaling NaN. - |9 |_rs1_ is a quiet NaN. - |=== + .Format of result of `fclass` instruction. + [%autowidth,float="center",align="center",cols="^,<",options="header",] + |=== + |_rd_ bit |Meaning + |0 |_rs1_ is latexmath:[$-\infty$]. + |1 |_rs1_ is a negative normal number. + |2 |_rs1_ is a negative subnormal number. + |3 |_rs1_ is latexmath:[$-0$]. + |4 |_rs1_ is latexmath:[$+0$]. + |5 |_rs1_ is a positive subnormal number. + |6 |_rs1_ is a positive normal number. + |7 |_rs1_ is latexmath:[$+\infty$]. + |8 |_rs1_ is a signaling NaN. + |9 |_rs1_ is a quiet NaN. + |=== definedBy: F assembly: xd, fs1 encoding: match: 111000000000-----001-----1010011 variables: - - name: fs1 - location: 19-15 - - name: rd - location: 11-7 + - name: fs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -74,8 +74,6 @@ operation(): | X[rd] = 1 << 9; } - - sail(): | { let rs1_val_X = X(rs1); diff --git a/arch/inst/F/fcvt.l.s.yaml b/arch/inst/F/fcvt.l.s.yaml index c5d156aa4d..85e56d0def 100644 --- a/arch/inst/F/fcvt.l.s.yaml +++ b/arch/inst/F/fcvt.l.s.yaml @@ -5,19 +5,19 @@ kind: instruction name: fcvt.l.s long_name: No synopsis available. description: | - No description available. + No description available. definedBy: F base: 64 assembly: xd, fs1, rm encoding: match: 110000000010-------------1010011 variables: - - name: fs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always @@ -26,9 +26,6 @@ access: data_independent_timing: true operation(): | - - - sail(): | { assert(sizeof(xlen) >= 64); diff --git a/arch/inst/F/fcvt.lu.s.yaml b/arch/inst/F/fcvt.lu.s.yaml index a77ccfe534..f80fe600a7 100644 --- a/arch/inst/F/fcvt.lu.s.yaml +++ b/arch/inst/F/fcvt.lu.s.yaml @@ -5,19 +5,19 @@ kind: instruction name: fcvt.lu.s long_name: No synopsis available. description: | - No description available. + No description available. definedBy: F base: 64 assembly: xd, fs1, rm encoding: match: 110000000011-------------1010011 variables: - - name: fs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always @@ -26,9 +26,6 @@ access: data_independent_timing: true operation(): | - - - sail(): | { assert(sizeof(xlen) >= 64); diff --git a/arch/inst/F/fcvt.s.l.yaml b/arch/inst/F/fcvt.s.l.yaml index 436bf19060..2893034c63 100644 --- a/arch/inst/F/fcvt.s.l.yaml +++ b/arch/inst/F/fcvt.s.l.yaml @@ -5,19 +5,19 @@ kind: instruction name: fcvt.s.l long_name: No synopsis available. description: | - No description available. + No description available. definedBy: F base: 64 assembly: fd, xs1, rm encoding: match: 110100000010-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: fd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 access: s: always u: always @@ -26,9 +26,6 @@ access: data_independent_timing: true operation(): | - - - sail(): | { assert(sizeof(xlen) >= 64); diff --git a/arch/inst/F/fcvt.s.lu.yaml b/arch/inst/F/fcvt.s.lu.yaml index b999a22966..31dbe48712 100644 --- a/arch/inst/F/fcvt.s.lu.yaml +++ b/arch/inst/F/fcvt.s.lu.yaml @@ -5,19 +5,19 @@ kind: instruction name: fcvt.s.lu long_name: No synopsis available. description: | - No description available. + No description available. definedBy: F base: 64 assembly: fd, xs1, rm encoding: match: 110100000011-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: fd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 access: s: always u: always @@ -26,9 +26,6 @@ access: data_independent_timing: true operation(): | - - - sail(): | { assert(sizeof(xlen) >= 64); diff --git a/arch/inst/F/fcvt.s.w.yaml b/arch/inst/F/fcvt.s.w.yaml index 70074ff6d9..9e0d646c01 100644 --- a/arch/inst/F/fcvt.s.w.yaml +++ b/arch/inst/F/fcvt.s.w.yaml @@ -20,12 +20,12 @@ assembly: fd, xs1 encoding: match: 110100000000-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: fd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 access: s: always u: always @@ -50,9 +50,6 @@ operation(): | mark_f_state_dirty(); - - - sail(): | { assert(sizeof(xlen) >= 64); diff --git a/arch/inst/F/fcvt.s.wu.yaml b/arch/inst/F/fcvt.s.wu.yaml index 783e1a461f..57fab4e22c 100644 --- a/arch/inst/F/fcvt.s.wu.yaml +++ b/arch/inst/F/fcvt.s.wu.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.s.wu long_name: No synopsis available. description: | - No description available. + No description available. definedBy: F assembly: fd, xs1, rm encoding: match: 110100000001-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: fd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: true operation(): | - - - sail(): | { assert(sizeof(xlen) >= 64); diff --git a/arch/inst/F/fcvt.w.s.yaml b/arch/inst/F/fcvt.w.s.yaml index 5693a60463..9921dd935a 100644 --- a/arch/inst/F/fcvt.w.s.yaml +++ b/arch/inst/F/fcvt.w.s.yaml @@ -5,47 +5,47 @@ kind: instruction name: fcvt.w.s long_name: Convert single-precision float to integer word to signed 32-bit integer. description: | - Converts a floating-point number in floating-point register _fs1_ to a signed 32-bit integer indicates - integer register _rd_. + Converts a floating-point number in floating-point register _fs1_ to a signed 32-bit integer indicates + integer register _rd_. - For XLEN >32, `fcvt.w.s` sign-extends the 32-bit result to the destination register width. + For XLEN >32, `fcvt.w.s` sign-extends the 32-bit result to the destination register width. - If the rounded result is not representable as a 32-bit signed integer, it is clipped to the - nearest value and the invalid flag is set. + If the rounded result is not representable as a 32-bit signed integer, it is clipped to the + nearest value and the invalid flag is set. - The range of valid inputs and behavior for invalid inputs are: + The range of valid inputs and behavior for invalid inputs are: - [separator="!"] - !=== - ! ! Value + [separator="!"] + !=== + ! ! Value - h! Minimum valid input (after rounding) ! `-2^31` - h! Maximum valid input (after rounding) ! `2^31 - 1` - h! Output for out-of-range negative input ! `-2^31` - h! Output for `-∞` ! `-2^31` - h! Output for out-of-range positive input ! `2^31 - 1` - h! Output for `+∞` for `NaN` ! `2^31 - 1` - !=== + h! Minimum valid input (after rounding) ! `-2^31` + h! Maximum valid input (after rounding) ! `2^31 - 1` + h! Output for out-of-range negative input ! `-2^31` + h! Output for `-∞` ! `-2^31` + h! Output for out-of-range positive input ! `2^31 - 1` + h! Output for `+∞` for `NaN` ! `2^31 - 1` + !=== - All floating-point to integer and integer to floating-point conversion instructions round - according to the _rm_ field. - A floating-point register can be initialized to floating-point positive zero using - `fcvt.s.w rd, x0`, which will never set any exception flags. + All floating-point to integer and integer to floating-point conversion instructions round + according to the _rm_ field. + A floating-point register can be initialized to floating-point positive zero using + `fcvt.s.w rd, x0`, which will never set any exception flags. - All floating-point conversion instructions set the Inexact exception flag if the rounded - result differs from the operand value and the Invalid exception flag is not set. + All floating-point conversion instructions set the Inexact exception flag if the rounded + result differs from the operand value and the Invalid exception flag is not set. definedBy: F assembly: xd, fs1 encoding: match: 110000000000-------------1010011 variables: - - name: fs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always @@ -53,35 +53,31 @@ access: vu: always data_independent_timing: true operation(): | - check_f_ok($encoding); + check_f_ok($encoding); - Bits<32> sp_value = f[fs1][31:0]; + Bits<32> sp_value = f[fs1][31:0]; - Bits<1> sign = sp_value[31]; - Bits<8> exp = sp_value[30:23]; - Bits<23> sig = sp_value[22:0]; + Bits<1> sign = sp_value[31]; + Bits<8> exp = sp_value[30:23]; + Bits<23> sig = sp_value[22:0]; - RoundingMode rounding_mode = rm_to_mode(rm, $encoding); + RoundingMode rounding_mode = rm_to_mode(rm, $encoding); - if ( (exp == 0xff) && (sig != 0)) { - sign = 0; - set_fp_flag(FpFlag::NV); - X[rd] = SP_CANONICAL_NAN; - } else { - if (exp != 0) { - sig = sig | 0x00800000; - } - Bits<64> sig64 = sig << 32; - Bits<16> shift_dist = 0xAA - exp; - if (0 < shift_dist) { - sig64 = softfloat_shiftRightJam64(sig64, shift_dist ); - } - X[rd] = softfloat_roundToI32( sign, sig64, rounding_mode ); + if ( (exp == 0xff) && (sig != 0)) { + sign = 0; + set_fp_flag(FpFlag::NV); + X[rd] = SP_CANONICAL_NAN; + } else { + if (exp != 0) { + sig = sig | 0x00800000; } - - - - + Bits<64> sig64 = sig << 32; + Bits<16> shift_dist = 0xAA - exp; + if (0 < shift_dist) { + sig64 = softfloat_shiftRightJam64(sig64, shift_dist ); + } + X[rd] = softfloat_roundToI32( sign, sig64, rounding_mode ); + } sail(): | { diff --git a/arch/inst/F/fcvt.wu.s.yaml b/arch/inst/F/fcvt.wu.s.yaml index 62468f5647..6dc4667bc3 100644 --- a/arch/inst/F/fcvt.wu.s.yaml +++ b/arch/inst/F/fcvt.wu.s.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.wu.s long_name: No synopsis available. description: | - No description available. + No description available. definedBy: F assembly: xd, fs1, rm encoding: match: 110000000001-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: true operation(): | - - - sail(): | { assert(sizeof(xlen) >= 64); diff --git a/arch/inst/F/fdiv.s.yaml b/arch/inst/F/fdiv.s.yaml index a022a89652..297533cb99 100644 --- a/arch/inst/F/fdiv.s.yaml +++ b/arch/inst/F/fdiv.s.yaml @@ -5,20 +5,20 @@ kind: instruction name: fdiv.s long_name: No synopsis available. description: | - No description available. + No description available. definedBy: F assembly: fd, fs1, fs2, rm encoding: match: 0001100------------------1010011 variables: - - name: fs2 - location: 24-20 - - name: fs1 - location: 19-15 - - name: rm - location: 14-12 - - name: fd - location: 11-7 + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: true operation(): | - - - sail(): | { let rs1_val_32b = F_or_X_S(rs1); diff --git a/arch/inst/F/feq.s.yaml b/arch/inst/F/feq.s.yaml index 5cb61a47bd..c278a79185 100644 --- a/arch/inst/F/feq.s.yaml +++ b/arch/inst/F/feq.s.yaml @@ -5,23 +5,23 @@ kind: instruction name: feq.s long_name: Single-precision floating-point equal description: | - Writes 1 to _rd_ if _fs1_ and _fs2_ are equal, and 0 otherwise. + Writes 1 to _rd_ if _fs1_ and _fs2_ are equal, and 0 otherwise. - If either operand is NaN, the result is 0 (not equal). If either operand is a signaling NaN, the invalid flag is set. + If either operand is NaN, the result is 0 (not equal). If either operand is a signaling NaN, the invalid flag is set. - Positive zero is considered equal to negative zero. + Positive zero is considered equal to negative zero. definedBy: F assembly: xd, fs1, fs2 encoding: match: 1010000----------010-----1010011 variables: - - name: fs2 - location: 24-20 - - name: fs1 - location: 19-15 - - name: rd - location: 11-7 + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -46,8 +46,6 @@ operation(): | ) ? 1 : 0; } - - sail(): | { let rs1_val_S = F_or_X_S(rs1); diff --git a/arch/inst/F/fle.s.yaml b/arch/inst/F/fle.s.yaml index 23cee21f40..12043cddbf 100644 --- a/arch/inst/F/fle.s.yaml +++ b/arch/inst/F/fle.s.yaml @@ -5,24 +5,24 @@ kind: instruction name: fle.s long_name: Single-precision floating-point less than or equal description: | - Writes 1 to _rd_ if _fs1_ is less than or equal to _fs2_, and 0 otherwise. + Writes 1 to _rd_ if _fs1_ is less than or equal to _fs2_, and 0 otherwise. - If either operand is NaN, the result is 0 (not equal). - If either operand is a NaN (signaling or quiet), the invalid flag is set. + If either operand is NaN, the result is 0 (not equal). + If either operand is a NaN (signaling or quiet), the invalid flag is set. - Positive zero and negative zero are considered equal. + Positive zero and negative zero are considered equal. definedBy: F assembly: xd, fs1, fs2 encoding: match: 1010000----------000-----1010011 variables: - - name: fs2 - location: 24-20 - - name: fs1 - location: 19-15 - - name: rd - location: 11-7 + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -47,8 +47,6 @@ operation(): | ) ? 1 : 0; } - - sail(): | { let rs1_val_S = F_or_X_S(rs1); diff --git a/arch/inst/F/fleq.s.yaml b/arch/inst/F/fleq.s.yaml index b2645b9d83..2d40e3d28d 100644 --- a/arch/inst/F/fleq.s.yaml +++ b/arch/inst/F/fleq.s.yaml @@ -5,18 +5,18 @@ kind: instruction name: fleq.s long_name: No synopsis available. description: | - No description available. + No description available. definedBy: F, Zfa assembly: xd, fs1, fs2 encoding: match: 1010000----------100-----1010011 variables: - - name: fs2 - location: 24-20 - - name: fs1 - location: 19-15 - - name: rd - location: 11-7 + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: true operation(): | - - - sail(): | { let rs1_val_S = F_S(rs1); diff --git a/arch/inst/F/fli.s.yaml b/arch/inst/F/fli.s.yaml index 293103c897..4ddd2390e6 100644 --- a/arch/inst/F/fli.s.yaml +++ b/arch/inst/F/fli.s.yaml @@ -5,16 +5,16 @@ kind: instruction name: fli.s long_name: No synopsis available. description: | - No description available. + No description available. definedBy: F, Zfa assembly: fd, fs1 encoding: match: 111100000001-----000-----1010011 variables: - - name: fs1 - location: 19-15 - - name: fd - location: 11-7 + - name: fs1 + location: 19-15 + - name: fd + location: 11-7 access: s: always u: always @@ -23,9 +23,6 @@ access: data_independent_timing: true operation(): | - - - sail(): | { let bits : bits(32) = match constantidx { diff --git a/arch/inst/F/flt.s.yaml b/arch/inst/F/flt.s.yaml index e6d63d55bb..468aa9d4fa 100644 --- a/arch/inst/F/flt.s.yaml +++ b/arch/inst/F/flt.s.yaml @@ -5,22 +5,22 @@ kind: instruction name: flt.s long_name: Single-precision floating-point less than description: | - Writes 1 to _rd_ if _fs1_ is less than _fs2_, and 0 otherwise. + Writes 1 to _rd_ if _fs1_ is less than _fs2_, and 0 otherwise. - If either operand is NaN, the result is 0 (not equal). - If either operand is a NaN (signaling or quiet), the invalid flag is set. + If either operand is NaN, the result is 0 (not equal). + If either operand is a NaN (signaling or quiet), the invalid flag is set. definedBy: F assembly: xd, fs1, fs2 encoding: match: 1010000----------001-----1010011 variables: - - name: fs2 - location: 24-20 - - name: fs1 - location: 19-15 - - name: rd - location: 11-7 + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -47,10 +47,6 @@ operation(): | X[rd] = a_lt_b ? 1 : 0; } - - - - sail(): | { let rs1_val_S = F_or_X_S(rs1); diff --git a/arch/inst/F/fltq.s.yaml b/arch/inst/F/fltq.s.yaml index 219da4452b..a06e604e73 100644 --- a/arch/inst/F/fltq.s.yaml +++ b/arch/inst/F/fltq.s.yaml @@ -5,18 +5,18 @@ kind: instruction name: fltq.s long_name: No synopsis available. description: | - No description available. + No description available. definedBy: F, Zfa assembly: xd, fs1, fs2 encoding: match: 1010000----------101-----1010011 variables: - - name: fs2 - location: 24-20 - - name: fs1 - location: 19-15 - - name: rd - location: 11-7 + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: true operation(): | - - - sail(): | { let rs1_val_S = F_S(rs1); diff --git a/arch/inst/F/flw.yaml b/arch/inst/F/flw.yaml index 1ca5c69284..948394d82b 100644 --- a/arch/inst/F/flw.yaml +++ b/arch/inst/F/flw.yaml @@ -14,12 +14,12 @@ assembly: fd, xs1, imm encoding: match: -----------------010-----0000111 variables: - - name: imm - location: 31-20 - - name: rs1 - location: 19-15 - - name: fd - location: 11-7 + - name: imm + location: 31-20 + - name: rs1 + location: 19-15 + - name: fd + location: 11-7 access: s: always u: always @@ -41,7 +41,6 @@ operation(): | mark_f_state_dirty(); - sail(): | { let offset : xlenbits = sign_extend(imm); diff --git a/arch/inst/F/fmadd.s.yaml b/arch/inst/F/fmadd.s.yaml index 353d68e44f..84b8138007 100644 --- a/arch/inst/F/fmadd.s.yaml +++ b/arch/inst/F/fmadd.s.yaml @@ -5,22 +5,22 @@ kind: instruction name: fmadd.s long_name: No synopsis available. description: | - No description available. + No description available. definedBy: F assembly: fd, fs1, fs2, fs3, rm encoding: match: -----00------------------1000011 variables: - - name: fs3 - location: 31-27 - - name: fs2 - location: 24-20 - - name: fs1 - location: 19-15 - - name: rm - location: 14-12 - - name: fd - location: 11-7 + - name: fs3 + location: 31-27 + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 access: s: always u: always @@ -29,9 +29,6 @@ access: data_independent_timing: true operation(): | - - - sail(): | { let rs1_val_32b = F_or_X_S(rs1); diff --git a/arch/inst/F/fmax.s.yaml b/arch/inst/F/fmax.s.yaml index c617d75432..4836edacb2 100644 --- a/arch/inst/F/fmax.s.yaml +++ b/arch/inst/F/fmax.s.yaml @@ -5,18 +5,18 @@ kind: instruction name: fmax.s long_name: No synopsis available. description: | - No description available. + No description available. definedBy: F assembly: fd, fs1, fs2 encoding: match: 0010100----------001-----1010011 variables: - - name: fs2 - location: 24-20 - - name: fs1 - location: 19-15 - - name: fd - location: 11-7 + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: fd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: true operation(): | - - - sail(): | { let rs1_val_S = F_or_X_S(rs1); diff --git a/arch/inst/F/fmaxm.s.yaml b/arch/inst/F/fmaxm.s.yaml index 39d20ca1e2..db023f7128 100644 --- a/arch/inst/F/fmaxm.s.yaml +++ b/arch/inst/F/fmaxm.s.yaml @@ -5,18 +5,18 @@ kind: instruction name: fmaxm.s long_name: No synopsis available. description: | - No description available. + No description available. definedBy: F, Zfa assembly: xd, xs1, xs2 encoding: match: 0010100----------011-----1010011 variables: - - name: fs2 - location: 24-20 - - name: fs1 - location: 19-15 - - name: fd - location: 11-7 + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: fd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: true operation(): | - - - sail(): | { let rs1_val_S = F_S(rs1); diff --git a/arch/inst/F/fmin.s.yaml b/arch/inst/F/fmin.s.yaml index 06dd4c629f..fa278a102f 100644 --- a/arch/inst/F/fmin.s.yaml +++ b/arch/inst/F/fmin.s.yaml @@ -5,18 +5,18 @@ kind: instruction name: fmin.s long_name: No synopsis available. description: | - No description available. + No description available. definedBy: F assembly: xd, xs1, xs2 encoding: match: 0010100----------000-----1010011 variables: - - name: fs2 - location: 24-20 - - name: fs1 - location: 19-15 - - name: fd - location: 11-7 + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: fd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: true operation(): | - - - sail(): | { let rs1_val_S = F_or_X_S(rs1); diff --git a/arch/inst/F/fminm.s.yaml b/arch/inst/F/fminm.s.yaml index da71a465cc..aa8d00371f 100644 --- a/arch/inst/F/fminm.s.yaml +++ b/arch/inst/F/fminm.s.yaml @@ -5,18 +5,18 @@ kind: instruction name: fminm.s long_name: No synopsis available. description: | - No description available. + No description available. definedBy: F, Zfa assembly: fd, fs1, fs2 encoding: match: 0010100----------010-----1010011 variables: - - name: fs2 - location: 24-20 - - name: fs1 - location: 19-15 - - name: fd - location: 11-7 + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: fd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: true operation(): | - - - sail(): | { let rs1_val_S = F_S(rs1); diff --git a/arch/inst/F/fmsub.s.yaml b/arch/inst/F/fmsub.s.yaml index 13d2a7f52e..a363361903 100644 --- a/arch/inst/F/fmsub.s.yaml +++ b/arch/inst/F/fmsub.s.yaml @@ -5,22 +5,22 @@ kind: instruction name: fmsub.s long_name: No synopsis available. description: | - No description available. + No description available. definedBy: F assembly: fd, fs1, fs2, fs3, rm encoding: match: -----00------------------1000111 variables: - - name: fs3 - location: 31-27 - - name: fs2 - location: 24-20 - - name: fs1 - location: 19-15 - - name: rm - location: 14-12 - - name: fd - location: 11-7 + - name: fs3 + location: 31-27 + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 access: s: always u: always @@ -29,9 +29,6 @@ access: data_independent_timing: true operation(): | - - - sail(): | { let rs1_val_32b = F_or_X_S(rs1); diff --git a/arch/inst/F/fmul.s.yaml b/arch/inst/F/fmul.s.yaml index 66d5392b79..d64c434d79 100644 --- a/arch/inst/F/fmul.s.yaml +++ b/arch/inst/F/fmul.s.yaml @@ -5,20 +5,20 @@ kind: instruction name: fmul.s long_name: No synopsis available. description: | - No description available. + No description available. definedBy: F assembly: fd, fs1, fs2, rm encoding: match: 0001000------------------1010011 variables: - - name: fs2 - location: 24-20 - - name: fs1 - location: 19-15 - - name: rm - location: 14-12 - - name: fd - location: 11-7 + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: true operation(): | - - - sail(): | { let rs1_val_32b = F_or_X_S(rs1); diff --git a/arch/inst/F/fmv.w.x.yaml b/arch/inst/F/fmv.w.x.yaml index 4b593de630..a3cbe3a5c7 100644 --- a/arch/inst/F/fmv.w.x.yaml +++ b/arch/inst/F/fmv.w.x.yaml @@ -5,19 +5,19 @@ kind: instruction name: fmv.w.x long_name: Single-precision floating-point move from integer description: | - Moves the single-precision value encoded in IEEE 754-2008 standard encoding - from the lower 32 bits of integer register `rs1` to the floating-point - register `fd`. The bits are not modified in the transfer, and in particular, - the payloads of non-canonical NaNs are preserved. + Moves the single-precision value encoded in IEEE 754-2008 standard encoding + from the lower 32 bits of integer register `rs1` to the floating-point + register `fd`. The bits are not modified in the transfer, and in particular, + the payloads of non-canonical NaNs are preserved. definedBy: F assembly: fd, xs1 encoding: match: 111100000000-----000-----1010011 variables: - - name: rs1 - location: 19-15 - - name: fd - location: 11-7 + - name: rs1 + location: 19-15 + - name: fd + location: 11-7 access: s: always u: always @@ -37,8 +37,6 @@ operation(): | mark_f_state_dirty(); - - sail(): | { let rs1_val_X = X(rs1); diff --git a/arch/inst/F/fmv.x.w.yaml b/arch/inst/F/fmv.x.w.yaml index f8887234c9..353ac0f9d9 100644 --- a/arch/inst/F/fmv.x.w.yaml +++ b/arch/inst/F/fmv.x.w.yaml @@ -5,21 +5,21 @@ kind: instruction name: fmv.x.w long_name: Move single-precision value from floating-point to integer register description: | - Moves the single-precision value in floating-point register rs1 represented in IEEE 754-2008 - encoding to the lower 32 bits of integer register rd. - The bits are not modified in the transfer, and in particular, the payloads of non-canonical - NaNs are preserved. - For RV64, the higher 32 bits of the destination register are filled with copies of the - floating-point number's sign bit. + Moves the single-precision value in floating-point register rs1 represented in IEEE 754-2008 + encoding to the lower 32 bits of integer register rd. + The bits are not modified in the transfer, and in particular, the payloads of non-canonical + NaNs are preserved. + For RV64, the higher 32 bits of the destination register are filled with copies of the + floating-point number's sign bit. definedBy: F assembly: xd, fs1 encoding: match: 111000000000-----000-----1010011 variables: - - name: fs1 - location: 19-15 - - name: rd - location: 11-7 + - name: fs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -27,11 +27,9 @@ access: vu: always data_independent_timing: true operation(): | - check_f_ok($encoding); - - X[rd] = sext(f[fs1][31:0], 32); - + check_f_ok($encoding); + X[rd] = sext(f[fs1][31:0], 32); sail(): | { diff --git a/arch/inst/F/fnmadd.s.yaml b/arch/inst/F/fnmadd.s.yaml index 1b0eaecf50..b18f8c6fb5 100644 --- a/arch/inst/F/fnmadd.s.yaml +++ b/arch/inst/F/fnmadd.s.yaml @@ -5,22 +5,22 @@ kind: instruction name: fnmadd.s long_name: No synopsis available. description: | - No description available. + No description available. definedBy: F assembly: fd, fs1, fs2, fs3, rm encoding: match: -----00------------------1001111 variables: - - name: fs3 - location: 31-27 - - name: fs2 - location: 24-20 - - name: fs1 - location: 19-15 - - name: rm - location: 14-12 - - name: fd - location: 11-7 + - name: fs3 + location: 31-27 + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 access: s: always u: always @@ -29,9 +29,6 @@ access: data_independent_timing: true operation(): | - - - sail(): | { let rs1_val_32b = F_or_X_S(rs1); diff --git a/arch/inst/F/fnmsub.s.yaml b/arch/inst/F/fnmsub.s.yaml index c1a1997b81..ee988c4563 100644 --- a/arch/inst/F/fnmsub.s.yaml +++ b/arch/inst/F/fnmsub.s.yaml @@ -5,22 +5,22 @@ kind: instruction name: fnmsub.s long_name: No synopsis available. description: | - No description available. + No description available. definedBy: F assembly: xd, xs1, xs2, xs3, rm encoding: match: -----00------------------1001011 variables: - - name: fs3 - location: 31-27 - - name: fs2 - location: 24-20 - - name: fs1 - location: 19-15 - - name: rm - location: 14-12 - - name: fd - location: 11-7 + - name: fs3 + location: 31-27 + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 access: s: always u: always @@ -29,9 +29,6 @@ access: data_independent_timing: true operation(): | - - - sail(): | { let rs1_val_32b = F_or_X_S(rs1); diff --git a/arch/inst/F/fround.s.yaml b/arch/inst/F/fround.s.yaml index 83753b0a8c..34db217b9e 100644 --- a/arch/inst/F/fround.s.yaml +++ b/arch/inst/F/fround.s.yaml @@ -5,18 +5,18 @@ kind: instruction name: fround.s long_name: No synopsis available. description: | - No description available. + No description available. definedBy: F, Zfa assembly: fd, xs1, rm encoding: match: 010000000100-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: fd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: true operation(): | - - - sail(): | { let rs1_val_S = F_S(rs1); diff --git a/arch/inst/F/froundnx.s.yaml b/arch/inst/F/froundnx.s.yaml index b3d8927e04..8ff644feb0 100644 --- a/arch/inst/F/froundnx.s.yaml +++ b/arch/inst/F/froundnx.s.yaml @@ -5,18 +5,18 @@ kind: instruction name: froundnx.s long_name: No synopsis available. description: | - No description available. + No description available. definedBy: F, Zfa assembly: fd, rs1, rm encoding: match: 010000000101-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: fd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: true operation(): | - - - sail(): | { let rs1_val_S = F_S(rs1); diff --git a/arch/inst/F/fsgnj.s.yaml b/arch/inst/F/fsgnj.s.yaml index 544d564e19..65e1322470 100644 --- a/arch/inst/F/fsgnj.s.yaml +++ b/arch/inst/F/fsgnj.s.yaml @@ -5,21 +5,21 @@ kind: instruction name: fsgnj.s long_name: Single-precision sign inject description: | - Writes _fd_ with sign bit of _fs2_ and the exponent and mantissa of _fs1_. + Writes _fd_ with sign bit of _fs2_ and the exponent and mantissa of _fs1_. - Sign-injection instructions do not set floating-point exception flags, nor do they canonicalize NaNs. + Sign-injection instructions do not set floating-point exception flags, nor do they canonicalize NaNs. definedBy: F assembly: fd, fs1, fs2 encoding: match: 0010000----------000-----1010011 variables: - - name: fs2 - location: 24-20 - - name: fs1 - location: 19-15 - - name: fd - location: 11-7 + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: fd + location: 11-7 access: s: always u: always @@ -27,8 +27,8 @@ access: vu: always data_independent_timing: true pseudoinstructions: -- when: (rs2 == rs1) - to: fmv.s + - when: (rs2 == rs1) + to: fmv.s operation(): | check_f_ok($encoding); @@ -43,8 +43,6 @@ operation(): | mark_f_state_dirty(); - - sail(): | { let rs1_val_S = F_or_X_S(rs1); diff --git a/arch/inst/F/fsgnjn.s.yaml b/arch/inst/F/fsgnjn.s.yaml index 286f7bffd2..d39200cd61 100644 --- a/arch/inst/F/fsgnjn.s.yaml +++ b/arch/inst/F/fsgnjn.s.yaml @@ -5,20 +5,20 @@ kind: instruction name: fsgnjn.s long_name: Single-precision sign inject negate description: | - Writes _fd_ with the opposite of the sign bit of _fs2_ and the exponent and mantissa of _fs1_. + Writes _fd_ with the opposite of the sign bit of _fs2_ and the exponent and mantissa of _fs1_. - Sign-injection instructions do not set floating-point exception flags, nor do they canonicalize NaNs. + Sign-injection instructions do not set floating-point exception flags, nor do they canonicalize NaNs. definedBy: F assembly: fd, fs1, fs2 encoding: match: 0010000----------001-----1010011 variables: - - name: fs2 - location: 24-20 - - name: fs1 - location: 19-15 - - name: fd - location: 11-7 + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: fd + location: 11-7 access: s: always u: always @@ -26,8 +26,8 @@ access: vu: always data_independent_timing: true pseudoinstructions: -- when: (rs2 == rs1) - to: fneg.s + - when: (rs2 == rs1) + to: fneg.s operation(): | check_f_ok($encoding); @@ -42,8 +42,6 @@ operation(): | mark_f_state_dirty(); - - sail(): | { let rs1_val_S = F_or_X_S(rs1); diff --git a/arch/inst/F/fsgnjx.s.yaml b/arch/inst/F/fsgnjx.s.yaml index e6fba22820..50d0f3ef25 100644 --- a/arch/inst/F/fsgnjx.s.yaml +++ b/arch/inst/F/fsgnjx.s.yaml @@ -5,20 +5,20 @@ kind: instruction name: fsgnjx.s long_name: Single-precision sign inject exclusive or description: | - Writes _fd_ with the xor of the sign bits of _fs2_ and _fs1_ and the exponent and mantissa of _fs1_. + Writes _fd_ with the xor of the sign bits of _fs2_ and _fs1_ and the exponent and mantissa of _fs1_. - Sign-injection instructions do not set floating-point exception flags, nor do they canonicalize NaNs. + Sign-injection instructions do not set floating-point exception flags, nor do they canonicalize NaNs. definedBy: F assembly: fd, fs1, fs2 encoding: match: 0010000----------010-----1010011 variables: - - name: fs2 - location: 24-20 - - name: fs1 - location: 19-15 - - name: fd - location: 11-7 + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: fd + location: 11-7 access: s: always u: always @@ -26,8 +26,8 @@ access: vu: always data_independent_timing: true pseudoinstructions: -- when: (rs2 == rs1) - to: fabs.s + - when: (rs2 == rs1) + to: fabs.s operation(): | check_f_ok($encoding); @@ -41,8 +41,6 @@ operation(): | mark_f_state_dirty(); - - sail(): | { let rs1_val_S = F_or_X_S(rs1); diff --git a/arch/inst/F/fsqrt.s.yaml b/arch/inst/F/fsqrt.s.yaml index a869687a29..939cdbac8d 100644 --- a/arch/inst/F/fsqrt.s.yaml +++ b/arch/inst/F/fsqrt.s.yaml @@ -5,18 +5,18 @@ kind: instruction name: fsqrt.s long_name: No synopsis available. description: | - No description available. + No description available. definedBy: F assembly: fd, fs1, rm encoding: match: 010110000000-------------1010011 variables: - - name: fs1 - location: 19-15 - - name: rm - location: 14-12 - - name: fd - location: 11-7 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: true operation(): | - - - sail(): | { assert(sizeof(xlen) >= 64); diff --git a/arch/inst/F/fsub.s.yaml b/arch/inst/F/fsub.s.yaml index ecce09860b..e430701033 100644 --- a/arch/inst/F/fsub.s.yaml +++ b/arch/inst/F/fsub.s.yaml @@ -5,20 +5,20 @@ kind: instruction name: fsub.s long_name: No synopsis available. description: | - No description available. + No description available. definedBy: F assembly: fd, fs1, fs2, rm encoding: match: 0000100------------------1010011 variables: - - name: fs2 - location: 24-20 - - name: fs1 - location: 19-15 - - name: rm - location: 14-12 - - name: fd - location: 11-7 + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: true operation(): | - - - sail(): | { let rs1_val_32b = F_or_X_S(rs1); diff --git a/arch/inst/F/fsw.yaml b/arch/inst/F/fsw.yaml index d2f23782ac..47745eefb6 100644 --- a/arch/inst/F/fsw.yaml +++ b/arch/inst/F/fsw.yaml @@ -14,12 +14,12 @@ assembly: fs2, xs1, imm encoding: match: -----------------010-----0100111 variables: - - name: imm - location: 31-25|11-7 - - name: fs2 - location: 24-20 - - name: rs1 - location: 19-15 + - name: imm + location: 31-25|11-7 + - name: fs2 + location: 24-20 + - name: rs1 + location: 19-15 access: s: always u: always @@ -33,8 +33,6 @@ operation(): | write_memory<32>(virtual_address, f[fs2][31:0], $encoding); - - sail(): | { let offset : xlenbits = sign_extend(imm); diff --git a/arch/inst/H/hfence.gvma.yaml b/arch/inst/H/hfence.gvma.yaml index 4bffc4c604..a06d3c70e0 100644 --- a/arch/inst/H/hfence.gvma.yaml +++ b/arch/inst/H/hfence.gvma.yaml @@ -5,16 +5,16 @@ kind: instruction name: hfence.gvma long_name: No synopsis available. description: | - No description available. + No description available. definedBy: H assembly: xs1, xs2 encoding: match: 0110001----------000000001110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 access: s: always u: always diff --git a/arch/inst/H/hfence.vvma.yaml b/arch/inst/H/hfence.vvma.yaml index dd015039f0..08f1e10c2d 100644 --- a/arch/inst/H/hfence.vvma.yaml +++ b/arch/inst/H/hfence.vvma.yaml @@ -5,16 +5,16 @@ kind: instruction name: hfence.vvma long_name: No synopsis available. description: | - No description available. + No description available. definedBy: H assembly: xs1, xs2 encoding: match: 0010001----------000000001110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 access: s: always u: always diff --git a/arch/inst/H/hlv.b.yaml b/arch/inst/H/hlv.b.yaml index c89ccd5c6d..8704d0fe8c 100644 --- a/arch/inst/H/hlv.b.yaml +++ b/arch/inst/H/hlv.b.yaml @@ -5,16 +5,16 @@ kind: instruction name: hlv.b long_name: No synopsis available. description: | - No description available. + No description available. definedBy: H assembly: xd, xs1 encoding: match: 011000000000-----100-----1110011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/H/hlv.bu.yaml b/arch/inst/H/hlv.bu.yaml index 5938d786a2..44441cafac 100644 --- a/arch/inst/H/hlv.bu.yaml +++ b/arch/inst/H/hlv.bu.yaml @@ -5,16 +5,16 @@ kind: instruction name: hlv.bu long_name: No synopsis available. description: | - No description available. + No description available. definedBy: H assembly: xd, xs1 encoding: match: 011000000001-----100-----1110011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/H/hlv.d.yaml b/arch/inst/H/hlv.d.yaml index 98c27700b9..96683b010c 100644 --- a/arch/inst/H/hlv.d.yaml +++ b/arch/inst/H/hlv.d.yaml @@ -5,16 +5,16 @@ kind: instruction name: hlv.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: H assembly: xd, xs1 encoding: match: 011011000000-----100-----1110011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/H/hlv.h.yaml b/arch/inst/H/hlv.h.yaml index 6abbd7d9b9..ca472fcb14 100644 --- a/arch/inst/H/hlv.h.yaml +++ b/arch/inst/H/hlv.h.yaml @@ -5,16 +5,16 @@ kind: instruction name: hlv.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: H assembly: xd, xs1 encoding: match: 011001000000-----100-----1110011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/H/hlv.hu.yaml b/arch/inst/H/hlv.hu.yaml index 99614784cd..9935245a20 100644 --- a/arch/inst/H/hlv.hu.yaml +++ b/arch/inst/H/hlv.hu.yaml @@ -5,16 +5,16 @@ kind: instruction name: hlv.hu long_name: No synopsis available. description: | - No description available. + No description available. definedBy: H assembly: xd, xs1 encoding: match: 011001000001-----100-----1110011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/H/hlv.w.yaml b/arch/inst/H/hlv.w.yaml index 53d318cad3..d1e9b84052 100644 --- a/arch/inst/H/hlv.w.yaml +++ b/arch/inst/H/hlv.w.yaml @@ -5,16 +5,16 @@ kind: instruction name: hlv.w long_name: No synopsis available. description: | - No description available. + No description available. definedBy: H assembly: xd, xs1 encoding: match: 011010000000-----100-----1110011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/H/hlv.wu.yaml b/arch/inst/H/hlv.wu.yaml index 2b8d652c9a..5957f331da 100644 --- a/arch/inst/H/hlv.wu.yaml +++ b/arch/inst/H/hlv.wu.yaml @@ -5,16 +5,16 @@ kind: instruction name: hlv.wu long_name: No synopsis available. description: | - No description available. + No description available. definedBy: H assembly: xd, xs1 encoding: match: 011010000001-----100-----1110011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/H/hlvx.hu.yaml b/arch/inst/H/hlvx.hu.yaml index b527451cdf..c9ebbca6d8 100644 --- a/arch/inst/H/hlvx.hu.yaml +++ b/arch/inst/H/hlvx.hu.yaml @@ -5,16 +5,16 @@ kind: instruction name: hlvx.hu long_name: No synopsis available. description: | - No description available. + No description available. definedBy: H assembly: xd, xs1 encoding: match: 011001000011-----100-----1110011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/H/hlvx.wu.yaml b/arch/inst/H/hlvx.wu.yaml index d764afeb39..3f2c36976e 100644 --- a/arch/inst/H/hlvx.wu.yaml +++ b/arch/inst/H/hlvx.wu.yaml @@ -5,16 +5,16 @@ kind: instruction name: hlvx.wu long_name: No synopsis available. description: | - No description available. + No description available. definedBy: H assembly: xd, xs1 encoding: match: 011010000011-----100-----1110011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/H/hsv.b.yaml b/arch/inst/H/hsv.b.yaml index 03da5add6b..0e8a8f68c2 100644 --- a/arch/inst/H/hsv.b.yaml +++ b/arch/inst/H/hsv.b.yaml @@ -5,16 +5,16 @@ kind: instruction name: hsv.b long_name: No synopsis available. description: | - No description available. + No description available. definedBy: H assembly: xs1, xs2 encoding: match: 0110001----------100000001110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 access: s: always u: always diff --git a/arch/inst/H/hsv.d.yaml b/arch/inst/H/hsv.d.yaml index cda8a6b5b2..9cf6e2daf3 100644 --- a/arch/inst/H/hsv.d.yaml +++ b/arch/inst/H/hsv.d.yaml @@ -5,16 +5,16 @@ kind: instruction name: hsv.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: H assembly: xs1, xs2 encoding: match: 0110111----------100000001110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 access: s: always u: always diff --git a/arch/inst/H/hsv.h.yaml b/arch/inst/H/hsv.h.yaml index 2ceb5b6b7b..51dd805a13 100644 --- a/arch/inst/H/hsv.h.yaml +++ b/arch/inst/H/hsv.h.yaml @@ -5,16 +5,16 @@ kind: instruction name: hsv.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: H assembly: xs1, xs2 encoding: match: 0110011----------100000001110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 access: s: always u: always diff --git a/arch/inst/H/hsv.w.yaml b/arch/inst/H/hsv.w.yaml index 2379bc83a1..87ccaa132c 100644 --- a/arch/inst/H/hsv.w.yaml +++ b/arch/inst/H/hsv.w.yaml @@ -5,16 +5,16 @@ kind: instruction name: hsv.w long_name: No synopsis available. description: | - No description available. + No description available. definedBy: H assembly: xs1, xs2 encoding: match: 0110101----------100000001110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 access: s: always u: always diff --git a/arch/inst/I/add.yaml b/arch/inst/I/add.yaml index e7038315a8..6466549d44 100644 --- a/arch/inst/I/add.yaml +++ b/arch/inst/I/add.yaml @@ -12,12 +12,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000000----------000-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -26,8 +26,6 @@ access: data_independent_timing: true operation(): X[rd] = X[rs1] + X[rs2]; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/I/addi.yaml b/arch/inst/I/addi.yaml index 74adf7a405..f7c6e5bce1 100644 --- a/arch/inst/I/addi.yaml +++ b/arch/inst/I/addi.yaml @@ -10,12 +10,12 @@ assembly: xd, xs1, imm encoding: match: -----------------000-----0010011 variables: - - name: imm - $inherits: common/inst_variable_types.yaml#/itype_imm - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: imm + $inherits: common/inst_variable_types.yaml#/itype_imm + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -24,8 +24,6 @@ access: data_independent_timing: true operation(): X[rd] = X[rs1] + imm; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/I/addiw.yaml b/arch/inst/I/addiw.yaml index 9060c51ee0..40a71c7535 100644 --- a/arch/inst/I/addiw.yaml +++ b/arch/inst/I/addiw.yaml @@ -11,12 +11,12 @@ assembly: xd, xs1, imm encoding: match: -----------------000-----0011011 variables: - - name: imm - location: 31-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: imm + location: 31-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -27,8 +27,6 @@ operation(): | XReg operand = sext(X[rs1], 31); X[rd] = sext(operand + imm, 31); - - sail(): | { let result : xlenbits = sign_extend(imm) + X(rs1); diff --git a/arch/inst/I/addw.yaml b/arch/inst/I/addw.yaml index 2abb97ed7f..4a87e73c9b 100644 --- a/arch/inst/I/addw.yaml +++ b/arch/inst/I/addw.yaml @@ -13,12 +13,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000000----------000-----0111011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -30,8 +30,6 @@ operation(): | XReg operand2 = sext(X[rs2], 31); X[rd] = sext(operand1 + operand2, 31); - - sail(): | { let rs1_val = (X(rs1))[31..0]; diff --git a/arch/inst/I/and.yaml b/arch/inst/I/and.yaml index 85a3a2022b..7a18927797 100644 --- a/arch/inst/I/and.yaml +++ b/arch/inst/I/and.yaml @@ -10,12 +10,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000000----------111-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -24,8 +24,6 @@ access: data_independent_timing: true operation(): X[rd] = X[rs1] & X[rs2]; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/I/andi.yaml b/arch/inst/I/andi.yaml index 708d67edb3..111918792c 100644 --- a/arch/inst/I/andi.yaml +++ b/arch/inst/I/andi.yaml @@ -10,12 +10,12 @@ assembly: xd, xs1, imm encoding: match: -----------------111-----0010011 variables: - - name: imm - location: 31-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: imm + location: 31-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -24,8 +24,6 @@ access: data_independent_timing: true operation(): X[rd] = X[rs1] & imm; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/I/auipc.yaml b/arch/inst/I/auipc.yaml index 3aa89876ed..df2cac9f31 100644 --- a/arch/inst/I/auipc.yaml +++ b/arch/inst/I/auipc.yaml @@ -10,11 +10,11 @@ assembly: xd, imm encoding: match: -------------------------0010111 variables: - - name: imm - location: 31-12 - left_shift: 12 - - name: rd - location: 11-7 + - name: imm + location: 31-12 + left_shift: 12 + - name: rd + location: 11-7 access: s: always u: always @@ -23,7 +23,6 @@ access: data_independent_timing: true operation(): X[rd] = $pc + imm; - sail(): | { let off : xlenbits = sign_extend(imm @ 0x000); diff --git a/arch/inst/I/beq.yaml b/arch/inst/I/beq.yaml index a58721bb6a..de4b337363 100644 --- a/arch/inst/I/beq.yaml +++ b/arch/inst/I/beq.yaml @@ -14,13 +14,13 @@ assembly: xs1, xs2, imm encoding: match: -----------------000-----1100011 variables: - - name: imm - location: 31|7|30-25|11-8 - left_shift: 1 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 + - name: imm + location: 31|7|30-25|11-8 + left_shift: 1 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 access: s: always u: always @@ -34,7 +34,6 @@ operation(): | jump_halfword($pc + imm); } - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/I/bge.yaml b/arch/inst/I/bge.yaml index 41369cb8ed..d6ed0b2705 100644 --- a/arch/inst/I/bge.yaml +++ b/arch/inst/I/bge.yaml @@ -14,13 +14,13 @@ assembly: xs1, xs2, imm encoding: match: -----------------101-----1100011 variables: - - name: imm - location: 31|7|30-25|11-8 - left_shift: 1 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 + - name: imm + location: 31|7|30-25|11-8 + left_shift: 1 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 access: s: always u: always @@ -34,8 +34,6 @@ operation(): | jump_halfword($pc + imm); } - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/I/bgeu.yaml b/arch/inst/I/bgeu.yaml index daa2a490f5..e2a2a48214 100644 --- a/arch/inst/I/bgeu.yaml +++ b/arch/inst/I/bgeu.yaml @@ -14,13 +14,13 @@ assembly: xs1, xs2, imm encoding: match: -----------------111-----1100011 variables: - - name: imm - location: 31|7|30-25|11-8 - left_shift: 1 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 + - name: imm + location: 31|7|30-25|11-8 + left_shift: 1 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 access: s: always u: always @@ -34,8 +34,6 @@ operation(): | jump_halfword($pc + imm); } - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/I/blt.yaml b/arch/inst/I/blt.yaml index beed9ad248..444d76114d 100644 --- a/arch/inst/I/blt.yaml +++ b/arch/inst/I/blt.yaml @@ -14,13 +14,13 @@ assembly: xs1, xs2, imm encoding: match: -----------------100-----1100011 variables: - - name: imm - location: 31|7|30-25|11-8 - left_shift: 1 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 + - name: imm + location: 31|7|30-25|11-8 + left_shift: 1 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 access: s: always u: always @@ -34,8 +34,6 @@ operation(): | jump_halfword($pc + imm); } - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/I/bltu.yaml b/arch/inst/I/bltu.yaml index bfc1ab77fd..caedfe0483 100644 --- a/arch/inst/I/bltu.yaml +++ b/arch/inst/I/bltu.yaml @@ -14,13 +14,13 @@ assembly: xs1, xs2, imm encoding: match: -----------------110-----1100011 variables: - - name: imm - location: 31|7|30-25|11-8 - left_shift: 1 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 + - name: imm + location: 31|7|30-25|11-8 + left_shift: 1 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 access: s: always u: always @@ -34,8 +34,6 @@ operation(): | jump_halfword($pc + imm); } - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/I/bne.yaml b/arch/inst/I/bne.yaml index 96c72a066e..97f7ed0181 100644 --- a/arch/inst/I/bne.yaml +++ b/arch/inst/I/bne.yaml @@ -14,13 +14,13 @@ assembly: xs1, xs2, imm encoding: match: -----------------001-----1100011 variables: - - name: imm - location: 31|7|30-25|11-8 - left_shift: 1 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 + - name: imm + location: 31|7|30-25|11-8 + left_shift: 1 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 access: s: always u: always @@ -34,8 +34,6 @@ operation(): | jump_halfword($pc + imm); } - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/I/ebreak.yaml b/arch/inst/I/ebreak.yaml index c13b7435fe..918a6f3927 100644 --- a/arch/inst/I/ebreak.yaml +++ b/arch/inst/I/ebreak.yaml @@ -18,9 +18,9 @@ description: | As EBREAK causes a synchronous exception, it is not considered to retire, and should not increment the `minstret` CSR. definedBy: I -assembly: '' +assembly: "" encoding: - match: '00000000000100000000000001110011' + match: "00000000000100000000000001110011" access: s: always u: always @@ -33,8 +33,6 @@ operation(): | eei_ebreak(); } - - sail(): | { handle_mem_exception(PC, E_Breakpoint()); diff --git a/arch/inst/I/ecall.yaml b/arch/inst/I/ecall.yaml index 205b43201b..1c78c49674 100644 --- a/arch/inst/I/ecall.yaml +++ b/arch/inst/I/ecall.yaml @@ -21,9 +21,9 @@ description: | As ECALL causes a synchronous exception, it is not considered to retire, and should not increment the `minstret` CSR. definedBy: I -assembly: '' +assembly: "" encoding: - match: '00000000000000000000000001110011' + match: "00000000000000000000000001110011" access: s: always u: always @@ -56,8 +56,6 @@ operation(): | } } - - sail(): | { let t : sync_exception = diff --git a/arch/inst/I/fence.yaml b/arch/inst/I/fence.yaml index b5173ec686..4302720170 100644 --- a/arch/inst/I/fence.yaml +++ b/arch/inst/I/fence.yaml @@ -125,16 +125,16 @@ assembly: "TODO" encoding: match: -----------------000-----0001111 variables: - - name: fm - location: 31-28 - - name: pred - location: 27-24 - - name: succ - location: 23-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: fm + location: 31-28 + - name: pred + location: 27-24 + - name: succ + location: 23-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -203,12 +203,10 @@ operation(): | ); } pseudoinstructions: -- when: (pred == 0x3) && (succ == 0x3) && (fm == 1) - to: fence.tso -- when: (pred == 1) && (succ == 0) && (fm == 0) && (rd == 0) && (rs1 == 0) - to: pause - - + - when: (pred == 0x3) && (succ == 0x3) && (fm == 1) + to: fence.tso + - when: (pred == 1) && (succ == 0) && (fm == 0) && (rd == 0) && (rs1 == 0) + to: pause sail(): | { diff --git a/arch/inst/I/jal.yaml b/arch/inst/I/jal.yaml index 7c0b299d32..f0db80a912 100644 --- a/arch/inst/I/jal.yaml +++ b/arch/inst/I/jal.yaml @@ -12,12 +12,12 @@ assembly: xd, imm encoding: match: -------------------------1101111 variables: - - name: imm - location: 31|19-12|20|30-21 - left_shift: 1 - sign_extend: true - - name: rd - location: 11-7 + - name: imm + location: 31|19-12|20|30-21 + left_shift: 1 + sign_extend: true + - name: rd + location: 11-7 access: s: always u: always @@ -29,8 +29,6 @@ operation(): | jump_halfword($pc + imm); X[rd] = retrun_addr; - - sail(): | { let t : xlenbits = PC + sign_extend(imm); diff --git a/arch/inst/I/jalr.yaml b/arch/inst/I/jalr.yaml index d3591fd2fc..5ef484c116 100644 --- a/arch/inst/I/jalr.yaml +++ b/arch/inst/I/jalr.yaml @@ -12,12 +12,12 @@ assembly: xd, imm(rs1) encoding: match: -----------------000-----1100111 variables: - - name: imm - location: 31-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: imm + location: 31-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -30,8 +30,6 @@ operation(): | jump(X[rs1] + imm); X[rd] = returnaddr; - - sail(): | { /* For the sequential model, the memory-model definition doesn't work directly diff --git a/arch/inst/I/lb.yaml b/arch/inst/I/lb.yaml index 96c27ead6b..170707be9a 100644 --- a/arch/inst/I/lb.yaml +++ b/arch/inst/I/lb.yaml @@ -13,12 +13,12 @@ assembly: xd, imm(rs1) encoding: match: -----------------000-----0000011 variables: - - name: imm - location: 31-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: imm + location: 31-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -29,8 +29,6 @@ operation(): | X[rd] = sext(read_memory<8>(virtual_address, $encoding), 8); - - sail(): | { let offset : xlenbits = sign_extend(imm); diff --git a/arch/inst/I/lbu.yaml b/arch/inst/I/lbu.yaml index c04ff027f9..efb7d96972 100644 --- a/arch/inst/I/lbu.yaml +++ b/arch/inst/I/lbu.yaml @@ -13,12 +13,12 @@ assembly: xd, imm(rs1) encoding: match: -----------------100-----0000011 variables: - - name: imm - location: 31-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: imm + location: 31-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -29,8 +29,6 @@ operation(): | X[rd] = read_memory<8>(virtual_address, $encoding); - - sail(): | { let offset : xlenbits = sign_extend(imm); diff --git a/arch/inst/I/ld.yaml b/arch/inst/I/ld.yaml index dc00e7d604..e4c39adc06 100644 --- a/arch/inst/I/ld.yaml +++ b/arch/inst/I/ld.yaml @@ -13,12 +13,12 @@ assembly: xd, imm(rs1) encoding: match: -----------------011-----0000011 variables: - - name: imm - location: 31-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: imm + location: 31-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -29,8 +29,6 @@ operation(): | X[rd] = read_memory<64>(virtual_address, $encoding); - - sail(): | { let offset : xlenbits = sign_extend(imm); diff --git a/arch/inst/I/lh.yaml b/arch/inst/I/lh.yaml index 22cfcfc0ed..86b5b95f06 100644 --- a/arch/inst/I/lh.yaml +++ b/arch/inst/I/lh.yaml @@ -13,12 +13,12 @@ assembly: xd, imm(rs1) encoding: match: -----------------001-----0000011 variables: - - name: imm - location: 31-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: imm + location: 31-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -29,8 +29,6 @@ operation(): | X[rd] = sext(read_memory<16>(virtual_address, $encoding), 16); - - sail(): | { let offset : xlenbits = sign_extend(imm); diff --git a/arch/inst/I/lhu.yaml b/arch/inst/I/lhu.yaml index 7c5da33965..95e8a60eec 100644 --- a/arch/inst/I/lhu.yaml +++ b/arch/inst/I/lhu.yaml @@ -13,12 +13,12 @@ assembly: xd, imm(rs1) encoding: match: -----------------101-----0000011 variables: - - name: imm - location: 31-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: imm + location: 31-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -29,8 +29,6 @@ operation(): | X[rd] = read_memory<16>(virtual_address, $encoding); - - sail(): | { let offset : xlenbits = sign_extend(imm); diff --git a/arch/inst/I/lui.yaml b/arch/inst/I/lui.yaml index 2401cf14a3..be47ea173b 100644 --- a/arch/inst/I/lui.yaml +++ b/arch/inst/I/lui.yaml @@ -10,11 +10,11 @@ assembly: xd, imm encoding: match: -------------------------0110111 variables: - - name: imm - location: 31-12 - left_shift: 12 - - name: rd - location: 11-7 + - name: imm + location: 31-12 + left_shift: 12 + - name: rd + location: 11-7 access: s: always u: always @@ -23,8 +23,6 @@ access: data_independent_timing: true operation(): X[rd] = imm; - - sail(): | { let off : xlenbits = sign_extend(imm @ 0x000); diff --git a/arch/inst/I/lw.yaml b/arch/inst/I/lw.yaml index db9e087946..c950ddbdf2 100644 --- a/arch/inst/I/lw.yaml +++ b/arch/inst/I/lw.yaml @@ -13,12 +13,12 @@ assembly: xd, imm(rs1) encoding: match: -----------------010-----0000011 variables: - - name: imm - location: 31-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: imm + location: 31-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -29,8 +29,6 @@ operation(): | X[rd] = read_memory<32>(virtual_address, $encoding); - - sail(): | { let offset : xlenbits = sign_extend(imm); diff --git a/arch/inst/I/lwu.yaml b/arch/inst/I/lwu.yaml index d20029bc58..0c35b3ad94 100644 --- a/arch/inst/I/lwu.yaml +++ b/arch/inst/I/lwu.yaml @@ -14,12 +14,12 @@ assembly: xd, imm(rs1) encoding: match: -----------------110-----0000011 variables: - - name: imm - location: 31-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: imm + location: 31-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -30,8 +30,6 @@ operation(): | X[rd] = read_memory<32>(virtual_address, $encoding); - - sail(): | { let offset : xlenbits = sign_extend(imm); diff --git a/arch/inst/I/mret.yaml b/arch/inst/I/mret.yaml index 114f68c337..f22c58bb49 100644 --- a/arch/inst/I/mret.yaml +++ b/arch/inst/I/mret.yaml @@ -12,7 +12,7 @@ access: vs: never vu: never encoding: - match: '00110000001000000000000001110011' + match: "00110000001000000000000001110011" operation(): | if (implemented?(ExtensionName::S) && CSR[mstatus].MPP != 2'b11) { CSR[mstatus].MPRV = 0; @@ -29,8 +29,6 @@ operation(): | CSR[mstatus].MPP = implemented?(ExtensionName::U) ? 2'b00 : 2'b11; $pc = $bits(CSR[mepc]); - - sail(): | { if cur_privilege != Machine diff --git a/arch/inst/I/or.yaml b/arch/inst/I/or.yaml index 0297a0cceb..0eeee6aecb 100644 --- a/arch/inst/I/or.yaml +++ b/arch/inst/I/or.yaml @@ -10,12 +10,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000000----------110-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -24,8 +24,6 @@ access: data_independent_timing: true operation(): X[rd] = X[rs1] | X[rs2]; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/I/ori.yaml b/arch/inst/I/ori.yaml index 6785c87e3d..d2cc79d298 100644 --- a/arch/inst/I/ori.yaml +++ b/arch/inst/I/ori.yaml @@ -10,12 +10,12 @@ assembly: xd, xs1, imm encoding: match: -----------------110-----0010011 variables: - - name: imm - location: 31-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: imm + location: 31-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -49,8 +49,6 @@ pseudoinstructions: - when: (rd == 0) && (imm[4:0] == 3) to: prefetch.w offset - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/I/sb.yaml b/arch/inst/I/sb.yaml index f0382d77a3..303c435c07 100644 --- a/arch/inst/I/sb.yaml +++ b/arch/inst/I/sb.yaml @@ -12,12 +12,12 @@ assembly: xs2, imm(xs1) encoding: match: -----------------000-----0100011 variables: - - name: imm - location: 31-25|11-7 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 + - name: imm + location: 31-25|11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 access: s: always u: always @@ -28,8 +28,6 @@ operation(): | write_memory<8>(virtual_address, X[rs2][7:0], $encoding); - - sail(): | { let offset : xlenbits = sign_extend(imm); diff --git a/arch/inst/I/sd.yaml b/arch/inst/I/sd.yaml index 0875a49667..8ac4ab4a48 100644 --- a/arch/inst/I/sd.yaml +++ b/arch/inst/I/sd.yaml @@ -13,13 +13,13 @@ assembly: xs2, imm(xs1) encoding: match: -----------------011-----0100011 variables: - - name: imm - location: 31-25|11-7 - sign_extend: true - - name: rs1 - location: 19-15 - - name: rs2 - location: 24-20 + - name: imm + location: 31-25|11-7 + sign_extend: true + - name: rs1 + location: 19-15 + - name: rs2 + location: 24-20 access: s: always u: always @@ -30,8 +30,6 @@ operation(): | write_memory<64>(virtual_address, X[rs2], $encoding); - - sail(): | { let offset : xlenbits = sign_extend(imm); diff --git a/arch/inst/I/sh.yaml b/arch/inst/I/sh.yaml index 8cfee46418..f7fb2db7a5 100644 --- a/arch/inst/I/sh.yaml +++ b/arch/inst/I/sh.yaml @@ -12,12 +12,12 @@ assembly: xs2, imm(xs1) encoding: match: -----------------001-----0100011 variables: - - name: imm - location: 31-25|11-7 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 + - name: imm + location: 31-25|11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 access: s: always u: always @@ -28,8 +28,6 @@ operation(): | write_memory<16>(virtual_address, X[rs2][15:0], $encoding); - - sail(): | { let offset : xlenbits = sign_extend(imm); diff --git a/arch/inst/I/sll.yaml b/arch/inst/I/sll.yaml index 5695aeaf17..53faae3947 100644 --- a/arch/inst/I/sll.yaml +++ b/arch/inst/I/sll.yaml @@ -11,12 +11,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000000----------001-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -30,8 +30,6 @@ operation(): | X[rd] = X[rs1] << X[rs2][4:0]; } - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/I/slli.yaml b/arch/inst/I/slli.yaml index 81a703f002..12c53e32dd 100644 --- a/arch/inst/I/slli.yaml +++ b/arch/inst/I/slli.yaml @@ -11,21 +11,21 @@ encoding: RV32: match: 0000000----------001-----0010011 variables: - - name: shamt - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: shamt + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 RV64: match: 000000-----------001-----0010011 variables: - - name: shamt - location: 25-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: shamt + location: 25-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -36,8 +36,6 @@ operation(): | # shamt is between 0-(XLEN-1) X[rd] = X[rs1] << shamt; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/I/slliw.yaml b/arch/inst/I/slliw.yaml index b8092139fd..b952b97df6 100644 --- a/arch/inst/I/slliw.yaml +++ b/arch/inst/I/slliw.yaml @@ -11,12 +11,12 @@ assembly: xd, xs1, shamt encoding: match: 0000000----------001-----0011011 variables: - - name: shamt - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: shamt + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -27,8 +27,6 @@ operation(): | # shamt is between 0-32 X[rd] = sext(X[rs1] << shamt, 31); - - sail(): | { let rs1_val = (X(rs1))[31..0]; diff --git a/arch/inst/I/sllw.yaml b/arch/inst/I/sllw.yaml index f540ff056d..1e354d13d6 100644 --- a/arch/inst/I/sllw.yaml +++ b/arch/inst/I/sllw.yaml @@ -12,12 +12,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000000----------001-----0111011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -26,8 +26,6 @@ access: data_independent_timing: true operation(): X[rd] = sext(X[rs1] << X[rs2][4:0], 31); - - sail(): | { let rs1_val = (X(rs1))[31..0]; diff --git a/arch/inst/I/slt.yaml b/arch/inst/I/slt.yaml index 1d1db5f428..d24ce3e2d3 100644 --- a/arch/inst/I/slt.yaml +++ b/arch/inst/I/slt.yaml @@ -12,12 +12,12 @@ assembly: xd, xs1, rs2 encoding: match: 0000000----------010-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -30,8 +30,6 @@ operation(): | X[rd] = ($signed(src1) < $signed(src2)) ? '1 : '0; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/I/slti.yaml b/arch/inst/I/slti.yaml index 84fd55a480..9431cca6ea 100644 --- a/arch/inst/I/slti.yaml +++ b/arch/inst/I/slti.yaml @@ -12,12 +12,12 @@ assembly: xd, xs1, imm encoding: match: -----------------010-----0010011 variables: - - name: imm - location: 31-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: imm + location: 31-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -27,8 +27,6 @@ data_independent_timing: true operation(): | X[rd] = ($signed(X[rs1]) < $signed(imm)) ? '1 : '0; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/I/sltiu.yaml b/arch/inst/I/sltiu.yaml index 14af783bbc..33e3c0d88e 100644 --- a/arch/inst/I/sltiu.yaml +++ b/arch/inst/I/sltiu.yaml @@ -16,12 +16,12 @@ assembly: xd, xs1, imm encoding: match: -----------------011-----0010011 variables: - - name: imm - location: 31-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: imm + location: 31-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -31,8 +31,6 @@ data_independent_timing: true operation(): | X[rd] = (X[rs1] < imm) ? 1 : 0; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/I/sltu.yaml b/arch/inst/I/sltu.yaml index b7087619b8..e07da0b3e6 100644 --- a/arch/inst/I/sltu.yaml +++ b/arch/inst/I/sltu.yaml @@ -12,12 +12,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000000----------011-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -27,8 +27,6 @@ data_independent_timing: true operation(): | X[rd] = (X[rs1] < X[rs2]) ? 1 : 0; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/I/sra.yaml b/arch/inst/I/sra.yaml index 55ad5e33fe..855bbc9f16 100644 --- a/arch/inst/I/sra.yaml +++ b/arch/inst/I/sra.yaml @@ -11,12 +11,12 @@ assembly: xd, xs1, xs2 encoding: match: 0100000----------101-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -30,8 +30,6 @@ operation(): | X[rd] = X[rs1] >>> X[rs2][4:0]; } - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/I/srai.yaml b/arch/inst/I/srai.yaml index 862372f2ab..33ae74ee00 100644 --- a/arch/inst/I/srai.yaml +++ b/arch/inst/I/srai.yaml @@ -13,21 +13,21 @@ encoding: RV32: match: 0100000----------101-----0010011 variables: - - name: shamt - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: shamt + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 RV64: match: 010000-----------101-----0010011 variables: - - name: shamt - location: 25-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: shamt + location: 25-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -38,8 +38,6 @@ operation(): | # shamt is between 0-63 X[rd] = X[rs1] >>> shamt; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/I/sraiw.yaml b/arch/inst/I/sraiw.yaml index 42fd48d105..89e413c3d5 100644 --- a/arch/inst/I/sraiw.yaml +++ b/arch/inst/I/sraiw.yaml @@ -13,12 +13,12 @@ assembly: xd, xs1, shamt encoding: match: 0100000----------101-----0011011 variables: - - name: shamt - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: shamt + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -30,8 +30,6 @@ operation(): | XReg operand = sext(X[rs1], 31); X[rd] = sext(operand >>> shamt, 31); - - sail(): | { let rs1_val = (X(rs1))[31..0]; diff --git a/arch/inst/I/sraw.yaml b/arch/inst/I/sraw.yaml index 716fd413d4..46ff0b5cdf 100644 --- a/arch/inst/I/sraw.yaml +++ b/arch/inst/I/sraw.yaml @@ -12,12 +12,12 @@ assembly: xd, xs1, xs2 encoding: match: 0100000----------101-----0111011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -29,8 +29,6 @@ operation(): | X[rd] = sext(operand1 >>> X[rs2][4:0], 31); - - sail(): | { let rs1_val = (X(rs1))[31..0]; diff --git a/arch/inst/I/srl.yaml b/arch/inst/I/srl.yaml index 3219a49abb..aac0008550 100644 --- a/arch/inst/I/srl.yaml +++ b/arch/inst/I/srl.yaml @@ -11,12 +11,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000000----------101-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -30,8 +30,6 @@ operation(): | X[rd] = X[rs1] >> X[rs2][4:0]; } - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/I/srli.yaml b/arch/inst/I/srli.yaml index 376ffc0cce..d0e525725c 100644 --- a/arch/inst/I/srli.yaml +++ b/arch/inst/I/srli.yaml @@ -10,21 +10,21 @@ encoding: RV32: match: 0000000----------101-----0010011 variables: - - name: shamt - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: shamt + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 RV64: match: 000000-----------101-----0010011 variables: - - name: shamt - location: 25-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: shamt + location: 25-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -35,8 +35,6 @@ operation(): | # shamt is between 0-63 X[rd] = X[rs1] >> shamt; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/I/srliw.yaml b/arch/inst/I/srliw.yaml index db87361eaf..b859e0fa49 100644 --- a/arch/inst/I/srliw.yaml +++ b/arch/inst/I/srliw.yaml @@ -11,12 +11,12 @@ assembly: xd, xs1, shamt encoding: match: 0000000----------101-----0011011 variables: - - name: shamt - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: shamt + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -29,8 +29,6 @@ operation(): | X[rd] = sext(operand >> shamt, 31); - - sail(): | { let rs1_val = (X(rs1))[31..0]; diff --git a/arch/inst/I/srlw.yaml b/arch/inst/I/srlw.yaml index 7945a7285f..5e24f68d83 100644 --- a/arch/inst/I/srlw.yaml +++ b/arch/inst/I/srlw.yaml @@ -12,12 +12,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000000----------101-----0111011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -26,8 +26,6 @@ access: data_independent_timing: true operation(): X[rd] = sext(X[rs1][31:0] >> X[rs2][4:0], 31); - - sail(): | { let rs1_val = (X(rs1))[31..0]; diff --git a/arch/inst/I/sub.yaml b/arch/inst/I/sub.yaml index 85c7921595..a4bbb98a7e 100644 --- a/arch/inst/I/sub.yaml +++ b/arch/inst/I/sub.yaml @@ -10,12 +10,12 @@ assembly: xd, xs1, xs2 encoding: match: 0100000----------000-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -27,8 +27,6 @@ operation(): | XReg t1 = X[rs2]; X[rd] = t0 - t1; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/I/subw.yaml b/arch/inst/I/subw.yaml index 8bc7e276f5..d39c1b7e52 100644 --- a/arch/inst/I/subw.yaml +++ b/arch/inst/I/subw.yaml @@ -11,12 +11,12 @@ assembly: xd, xs1, xs2 encoding: match: 0100000----------000-----0111011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -28,8 +28,6 @@ operation(): | Bits<32> t1 = X[rs2][31:0]; X[rd] = sext(t0 - t1, 31); - - sail(): | { let rs1_val = (X(rs1))[31..0]; diff --git a/arch/inst/I/sw.yaml b/arch/inst/I/sw.yaml index 0912e04489..a95dcf3f83 100644 --- a/arch/inst/I/sw.yaml +++ b/arch/inst/I/sw.yaml @@ -12,12 +12,12 @@ assembly: xs2, imm(xs1) encoding: match: -----------------010-----0100011 variables: - - name: imm - location: 31-25|11-7 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 + - name: imm + location: 31-25|11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 access: s: always u: always @@ -28,8 +28,6 @@ operation(): | write_memory<32>(virtual_address, X[rs2][31:0], $encoding); - - sail(): | { let offset : xlenbits = sign_extend(imm); diff --git a/arch/inst/I/wfi.yaml b/arch/inst/I/wfi.yaml index ce574396e6..4c05807ee9 100644 --- a/arch/inst/I/wfi.yaml +++ b/arch/inst/I/wfi.yaml @@ -47,7 +47,7 @@ description: | definedBy: Sm assembly: "" encoding: - match: '00010000010100000000000001110011' + match: "00010000010100000000000001110011" access: s: sometimes u: sometimes @@ -111,8 +111,6 @@ operation(): | # passed, so now do the wait wfi(); - - sail(): | match cur_privilege { Machine => { platform_wfi(); RETIRE_SUCCESS }, diff --git a/arch/inst/I/xor.yaml b/arch/inst/I/xor.yaml index e3438951d3..ba2efc7264 100644 --- a/arch/inst/I/xor.yaml +++ b/arch/inst/I/xor.yaml @@ -10,12 +10,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000000----------100-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -24,8 +24,6 @@ access: data_independent_timing: true operation(): X[rd] = X[rs1] ^ X[rs2]; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/I/xori.yaml b/arch/inst/I/xori.yaml index d92c307423..2a588aa50a 100644 --- a/arch/inst/I/xori.yaml +++ b/arch/inst/I/xori.yaml @@ -10,12 +10,12 @@ assembly: xd, xs1, imm encoding: match: -----------------100-----0010011 variables: - - name: imm - location: 31-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: imm + location: 31-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -24,8 +24,6 @@ access: data_independent_timing: true operation(): X[rd] = X[rs1] ^ imm; - - sail(): | { let rs1_val = X(rs1); diff --git a/arch/inst/M/div.yaml b/arch/inst/M/div.yaml index 32b003a2db..652784552c 100644 --- a/arch/inst/M/div.yaml +++ b/arch/inst/M/div.yaml @@ -16,12 +16,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000001----------100-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -50,7 +50,6 @@ operation(): | X[rd] = $signed(src1) / $signed(src2); } - sail(): | { if extension("M") then { diff --git a/arch/inst/M/divu.yaml b/arch/inst/M/divu.yaml index 75c43ff8d7..71ce0a624a 100644 --- a/arch/inst/M/divu.yaml +++ b/arch/inst/M/divu.yaml @@ -15,12 +15,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000001----------101-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -42,7 +42,6 @@ operation(): | X[rd] = src1 / src2; } - sail(): | { if extension("M") then { diff --git a/arch/inst/M/divuw.yaml b/arch/inst/M/divuw.yaml index 09e928a5b3..d5e22cd257 100644 --- a/arch/inst/M/divuw.yaml +++ b/arch/inst/M/divuw.yaml @@ -15,12 +15,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000001----------101-----0111011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -47,8 +47,6 @@ operation(): | X[rd] = {{32{sign_bit}}, result}; } - - sail(): | { if extension("M") then { diff --git a/arch/inst/M/divw.yaml b/arch/inst/M/divw.yaml index 4a1674859c..13031feb06 100644 --- a/arch/inst/M/divw.yaml +++ b/arch/inst/M/divw.yaml @@ -19,12 +19,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000001----------100-----0111011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -56,8 +56,6 @@ operation(): | X[rd] = {{32{sign_bit}}, result}; } - - sail(): | { if extension("M") then { diff --git a/arch/inst/M/mul.yaml b/arch/inst/M/mul.yaml index 26c440799c..b4187b3685 100644 --- a/arch/inst/M/mul.yaml +++ b/arch/inst/M/mul.yaml @@ -23,12 +23,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000001----------000-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -45,7 +45,6 @@ operation(): | X[rd] = (src1 * src2)[XLEN-1:0]; - sail(): | { if extension("M") | haveZmmul() then { diff --git a/arch/inst/M/mulh.yaml b/arch/inst/M/mulh.yaml index 3bb7d5b0a3..d36c6b79f4 100644 --- a/arch/inst/M/mulh.yaml +++ b/arch/inst/M/mulh.yaml @@ -22,12 +22,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000001----------001-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -49,8 +49,6 @@ operation(): | # grab the high half of the result, and put it in rd X[rd] = (src1 * src2)[(xlen()*8'd2)-1:xlen()]; - - sail(): | { if extension("M") | haveZmmul() then { diff --git a/arch/inst/M/mulhsu.yaml b/arch/inst/M/mulhsu.yaml index 3fc37753b0..7b92c2af5f 100644 --- a/arch/inst/M/mulhsu.yaml +++ b/arch/inst/M/mulhsu.yaml @@ -22,12 +22,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000001----------010-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -46,7 +46,6 @@ operation(): | X[rd] = (src1 * src2)[(XLEN*8'd2)-1:XLEN]; - sail(): | { if extension("M") | haveZmmul() then { diff --git a/arch/inst/M/mulhu.yaml b/arch/inst/M/mulhu.yaml index 436668a0c2..123e089cf1 100644 --- a/arch/inst/M/mulhu.yaml +++ b/arch/inst/M/mulhu.yaml @@ -22,12 +22,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000001----------011-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -45,7 +45,6 @@ operation(): | X[rd] = (src1 * src2)[(XLEN*8'd2)-1:XLEN]; - sail(): | { if extension("M") | haveZmmul() then { diff --git a/arch/inst/M/mulw.yaml b/arch/inst/M/mulw.yaml index bd6573725d..d2a24afee2 100644 --- a/arch/inst/M/mulw.yaml +++ b/arch/inst/M/mulw.yaml @@ -21,12 +21,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000001----------000-----0111011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -47,8 +47,6 @@ operation(): | # return the sign-extended result X[rd] = {{32{sign_bit}}, result}; - - sail(): | { if extension("M") | haveZmmul() then { diff --git a/arch/inst/M/rem.yaml b/arch/inst/M/rem.yaml index 06367f68c8..acd7006742 100644 --- a/arch/inst/M/rem.yaml +++ b/arch/inst/M/rem.yaml @@ -15,12 +15,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000001----------110-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -48,7 +48,6 @@ operation(): | X[rd] = $signed(src1) % $signed(src2); } - sail(): | { if extension("M") then { diff --git a/arch/inst/M/remu.yaml b/arch/inst/M/remu.yaml index c668b94b55..0d00d50051 100644 --- a/arch/inst/M/remu.yaml +++ b/arch/inst/M/remu.yaml @@ -11,12 +11,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000001----------111-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -38,7 +38,6 @@ operation(): | X[rd] = src1 % src2; } - sail(): | { if extension("M") then { diff --git a/arch/inst/M/remuw.yaml b/arch/inst/M/remuw.yaml index 4a4b348fad..c765fa4a6b 100644 --- a/arch/inst/M/remuw.yaml +++ b/arch/inst/M/remuw.yaml @@ -14,12 +14,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000001----------111-----0111011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -49,8 +49,6 @@ operation(): | X[rd] = {{32{sign_bit}}, result}; } - - sail(): | { if extension("M") then { diff --git a/arch/inst/M/remw.yaml b/arch/inst/M/remw.yaml index 2c2a1500a2..f03753412f 100644 --- a/arch/inst/M/remw.yaml +++ b/arch/inst/M/remw.yaml @@ -16,12 +16,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000001----------110-----0111011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -54,7 +54,6 @@ operation(): | X[rd] = {{32{sign_bit}}, result}; } - sail(): | { if extension("M") then { diff --git a/arch/inst/Q/fadd.q.yaml b/arch/inst/Q/fadd.q.yaml index 3c9886e77a..32c561bbb3 100644 --- a/arch/inst/Q/fadd.q.yaml +++ b/arch/inst/Q/fadd.q.yaml @@ -5,20 +5,20 @@ kind: instruction name: fadd.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q assembly: qd, qs1, qs2, rm encoding: match: 0000011------------------1010011 variables: - - name: qs2 - location: 24-20 - - name: qs1 - location: 19-15 - - name: rm - location: 14-12 - - name: qd - location: 11-7 + - name: qs2 + location: 24-20 + - name: qs1 + location: 19-15 + - name: rm + location: 14-12 + - name: qd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fclass.q.yaml b/arch/inst/Q/fclass.q.yaml index 230ff77736..fb099eae8c 100644 --- a/arch/inst/Q/fclass.q.yaml +++ b/arch/inst/Q/fclass.q.yaml @@ -5,16 +5,16 @@ kind: instruction name: fclass.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q assembly: xd, qs1 encoding: match: 111001100000-----001-----1010011 variables: - - name: qs1 - location: 19-15 - - name: rd - location: 11-7 + - name: qs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fcvt.d.q.yaml b/arch/inst/Q/fcvt.d.q.yaml index 899950f8a8..cd88087b8d 100644 --- a/arch/inst/Q/fcvt.d.q.yaml +++ b/arch/inst/Q/fcvt.d.q.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.d.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q assembly: xd, qs1, rm encoding: match: 010000100011-------------1010011 variables: - - name: qs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: qs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fcvt.h.q.yaml b/arch/inst/Q/fcvt.h.q.yaml index 223ed90243..8c56e8f78f 100644 --- a/arch/inst/Q/fcvt.h.q.yaml +++ b/arch/inst/Q/fcvt.h.q.yaml @@ -5,19 +5,19 @@ kind: instruction name: fcvt.h.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Q, Zfh] assembly: xd, qs1, rm encoding: match: 010001000011-------------1010011 variables: - - name: qs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: qs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fcvt.l.q.yaml b/arch/inst/Q/fcvt.l.q.yaml index aae2df1a0a..b417279ee1 100644 --- a/arch/inst/Q/fcvt.l.q.yaml +++ b/arch/inst/Q/fcvt.l.q.yaml @@ -5,19 +5,19 @@ kind: instruction name: fcvt.l.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q base: 64 assembly: xd, qs1, rm encoding: match: 110001100010-------------1010011 variables: - - name: qs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: qs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fcvt.lu.q.yaml b/arch/inst/Q/fcvt.lu.q.yaml index 1c75d28f0d..ef9bcabd28 100644 --- a/arch/inst/Q/fcvt.lu.q.yaml +++ b/arch/inst/Q/fcvt.lu.q.yaml @@ -5,19 +5,19 @@ kind: instruction name: fcvt.lu.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q base: 64 assembly: qd, hs1, rm encoding: match: 110001100011-------------1010011 variables: - - name: hs1 - location: 19-15 - - name: rm - location: 14-12 - - name: qd - location: 11-7 + - name: hs1 + location: 19-15 + - name: rm + location: 14-12 + - name: qd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fcvt.q.d.yaml b/arch/inst/Q/fcvt.q.d.yaml index ce1ae3943b..5272b5d1f3 100644 --- a/arch/inst/Q/fcvt.q.d.yaml +++ b/arch/inst/Q/fcvt.q.d.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.q.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q assembly: dd, fs1, rm encoding: match: 010001100001-------------1010011 variables: - - name: fs1 - location: 19-15 - - name: rm - location: 14-12 - - name: dd - location: 11-7 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: dd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fcvt.q.h.yaml b/arch/inst/Q/fcvt.q.h.yaml index 541f2e10ba..2b7e7fe09d 100644 --- a/arch/inst/Q/fcvt.q.h.yaml +++ b/arch/inst/Q/fcvt.q.h.yaml @@ -5,19 +5,19 @@ kind: instruction name: fcvt.q.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Q, Zfh] assembly: hd, qs1, rm encoding: match: 010001100010-------------1010011 variables: - - name: qs1 - location: 19-15 - - name: rm - location: 14-12 - - name: hd - location: 11-7 + - name: qs1 + location: 19-15 + - name: rm + location: 14-12 + - name: hd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fcvt.q.l.yaml b/arch/inst/Q/fcvt.q.l.yaml index 092d57110b..a9f1b76392 100644 --- a/arch/inst/Q/fcvt.q.l.yaml +++ b/arch/inst/Q/fcvt.q.l.yaml @@ -5,19 +5,19 @@ kind: instruction name: fcvt.q.l long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q base: 64 assembly: qd, xs1, rm encoding: match: 110101100010-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: qd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: qd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fcvt.q.lu.yaml b/arch/inst/Q/fcvt.q.lu.yaml index 01572ba4a2..a3ec07da44 100644 --- a/arch/inst/Q/fcvt.q.lu.yaml +++ b/arch/inst/Q/fcvt.q.lu.yaml @@ -5,19 +5,19 @@ kind: instruction name: fcvt.q.lu long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q base: 64 assembly: qd, xs1, rm encoding: match: 110101100011-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: qd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: qd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fcvt.q.s.yaml b/arch/inst/Q/fcvt.q.s.yaml index 6f4024c5bf..0583e92296 100644 --- a/arch/inst/Q/fcvt.q.s.yaml +++ b/arch/inst/Q/fcvt.q.s.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.q.s long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q assembly: qd, fs1, rm encoding: match: 010001100000-------------1010011 variables: - - name: fs1 - location: 19-15 - - name: rm - location: 14-12 - - name: qd - location: 11-7 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: qd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fcvt.q.w.yaml b/arch/inst/Q/fcvt.q.w.yaml index d92b57d35b..3303a5da4b 100644 --- a/arch/inst/Q/fcvt.q.w.yaml +++ b/arch/inst/Q/fcvt.q.w.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.q.w long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q assembly: fd, xs1, rm encoding: match: 110101100000-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: fd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fcvt.q.wu.yaml b/arch/inst/Q/fcvt.q.wu.yaml index 05c0da5e1c..7a27e4e437 100644 --- a/arch/inst/Q/fcvt.q.wu.yaml +++ b/arch/inst/Q/fcvt.q.wu.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.q.wu long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q assembly: qd, xs1, rm encoding: match: 110101100001-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: qd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: qd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fcvt.s.q.yaml b/arch/inst/Q/fcvt.s.q.yaml index a772446dab..92d0487280 100644 --- a/arch/inst/Q/fcvt.s.q.yaml +++ b/arch/inst/Q/fcvt.s.q.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.s.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q assembly: fd, qs1, rm encoding: match: 010000000011-------------1010011 variables: - - name: qs1 - location: 19-15 - - name: rm - location: 14-12 - - name: fd - location: 11-7 + - name: qs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fcvt.w.q.yaml b/arch/inst/Q/fcvt.w.q.yaml index 93b69f6247..9fb598fbb9 100644 --- a/arch/inst/Q/fcvt.w.q.yaml +++ b/arch/inst/Q/fcvt.w.q.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.w.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q assembly: xd, qs1, rm encoding: match: 110001100000-------------1010011 variables: - - name: qs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: qs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fcvt.wu.q.yaml b/arch/inst/Q/fcvt.wu.q.yaml index 5d66b2af92..688cc1a115 100644 --- a/arch/inst/Q/fcvt.wu.q.yaml +++ b/arch/inst/Q/fcvt.wu.q.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.wu.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q assembly: xd, xs1, rm encoding: match: 110001100001-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fdiv.q.yaml b/arch/inst/Q/fdiv.q.yaml index 63e3fd2f86..2ccbf8dafe 100644 --- a/arch/inst/Q/fdiv.q.yaml +++ b/arch/inst/Q/fdiv.q.yaml @@ -5,20 +5,20 @@ kind: instruction name: fdiv.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q assembly: qd, qs1, qs2, rm encoding: match: 0001111------------------1010011 variables: - - name: qs2 - location: 24-20 - - name: qs1 - location: 19-15 - - name: rm - location: 14-12 - - name: qd - location: 11-7 + - name: qs2 + location: 24-20 + - name: qs1 + location: 19-15 + - name: rm + location: 14-12 + - name: qd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/feq.q.yaml b/arch/inst/Q/feq.q.yaml index 14286fb68a..f792e1e398 100644 --- a/arch/inst/Q/feq.q.yaml +++ b/arch/inst/Q/feq.q.yaml @@ -5,18 +5,18 @@ kind: instruction name: feq.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q assembly: xd, qs1, qs2 encoding: match: 1010011----------010-----1010011 variables: - - name: qs2 - location: 24-20 - - name: qs1 - location: 19-15 - - name: rd - location: 11-7 + - name: qs2 + location: 24-20 + - name: qs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fle.q.yaml b/arch/inst/Q/fle.q.yaml index 9ad903ba24..0c8c441cc8 100644 --- a/arch/inst/Q/fle.q.yaml +++ b/arch/inst/Q/fle.q.yaml @@ -5,18 +5,18 @@ kind: instruction name: fle.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q assembly: xd, qs1, qs2 encoding: match: 1010011----------000-----1010011 variables: - - name: qs2 - location: 24-20 - - name: qs1 - location: 19-15 - - name: rd - location: 11-7 + - name: qs2 + location: 24-20 + - name: qs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fleq.q.yaml b/arch/inst/Q/fleq.q.yaml index 5cb9b831ec..cd6ed983ab 100644 --- a/arch/inst/Q/fleq.q.yaml +++ b/arch/inst/Q/fleq.q.yaml @@ -5,19 +5,19 @@ kind: instruction name: fleq.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Q, Zfa] assembly: xd, qs1, qs2 encoding: match: 1010011----------100-----1010011 variables: - - name: qs2 - location: 24-20 - - name: qs1 - location: 19-15 - - name: rd - location: 11-7 + - name: qs2 + location: 24-20 + - name: qs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fli.q.yaml b/arch/inst/Q/fli.q.yaml index aa72738305..5d8005c9b3 100644 --- a/arch/inst/Q/fli.q.yaml +++ b/arch/inst/Q/fli.q.yaml @@ -5,17 +5,17 @@ kind: instruction name: fli.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Q, Zfa] assembly: fd, qs1 encoding: match: 111101100001-----000-----1010011 variables: - - name: qs1 - location: 19-15 - - name: fd - location: 11-7 + - name: qs1 + location: 19-15 + - name: fd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/flq.yaml b/arch/inst/Q/flq.yaml index d013be44a7..4344671002 100644 --- a/arch/inst/Q/flq.yaml +++ b/arch/inst/Q/flq.yaml @@ -5,18 +5,18 @@ kind: instruction name: flq long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q assembly: qd, xs1, imm encoding: match: -----------------100-----0000111 variables: - - name: imm - location: 31-20 - - name: rs1 - location: 19-15 - - name: qd - location: 11-7 + - name: imm + location: 31-20 + - name: rs1 + location: 19-15 + - name: qd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/flt.q.yaml b/arch/inst/Q/flt.q.yaml index 5a400c7766..ef0ea0ee12 100644 --- a/arch/inst/Q/flt.q.yaml +++ b/arch/inst/Q/flt.q.yaml @@ -5,18 +5,18 @@ kind: instruction name: flt.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q assembly: xd, qs1, qs2 encoding: match: 1010011----------001-----1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fltq.q.yaml b/arch/inst/Q/fltq.q.yaml index b80f30f474..d5a341ff17 100644 --- a/arch/inst/Q/fltq.q.yaml +++ b/arch/inst/Q/fltq.q.yaml @@ -5,19 +5,19 @@ kind: instruction name: fltq.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Q, Zfa] assembly: qd, qs1, qs2 encoding: match: 1010011----------101-----1010011 variables: - - name: qs2 - location: 24-20 - - name: qs1 - location: 19-15 - - name: qd - location: 11-7 + - name: qs2 + location: 24-20 + - name: qs1 + location: 19-15 + - name: qd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fmadd.q.yaml b/arch/inst/Q/fmadd.q.yaml index 7977f8f95c..25a384af80 100644 --- a/arch/inst/Q/fmadd.q.yaml +++ b/arch/inst/Q/fmadd.q.yaml @@ -5,22 +5,22 @@ kind: instruction name: fmadd.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q assembly: qd, qs1, qs2, qs3, rm encoding: match: -----11------------------1000011 variables: - - name: qs3 - location: 31-27 - - name: qs2 - location: 24-20 - - name: qs1 - location: 19-15 - - name: rm - location: 14-12 - - name: qd - location: 11-7 + - name: qs3 + location: 31-27 + - name: qs2 + location: 24-20 + - name: qs1 + location: 19-15 + - name: rm + location: 14-12 + - name: qd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fmax.q.yaml b/arch/inst/Q/fmax.q.yaml index ff2069f090..60ba1c250d 100644 --- a/arch/inst/Q/fmax.q.yaml +++ b/arch/inst/Q/fmax.q.yaml @@ -5,18 +5,18 @@ kind: instruction name: fmax.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q assembly: qd, qs1, qs2 encoding: match: 0010111----------001-----1010011 variables: - - name: qs2 - location: 24-20 - - name: qs1 - location: 19-15 - - name: qd - location: 11-7 + - name: qs2 + location: 24-20 + - name: qs1 + location: 19-15 + - name: qd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fmaxm.q.yaml b/arch/inst/Q/fmaxm.q.yaml index 9ecca0aeca..2cf6296744 100644 --- a/arch/inst/Q/fmaxm.q.yaml +++ b/arch/inst/Q/fmaxm.q.yaml @@ -5,19 +5,19 @@ kind: instruction name: fmaxm.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Q, Zfa] assembly: qd, qs1, qs2 encoding: match: 0010111----------011-----1010011 variables: - - name: qs2 - location: 24-20 - - name: qs1 - location: 19-15 - - name: qd - location: 11-7 + - name: qs2 + location: 24-20 + - name: qs1 + location: 19-15 + - name: qd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fmin.q.yaml b/arch/inst/Q/fmin.q.yaml index 62f30485b0..bf44bb8d12 100644 --- a/arch/inst/Q/fmin.q.yaml +++ b/arch/inst/Q/fmin.q.yaml @@ -5,18 +5,18 @@ kind: instruction name: fmin.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q assembly: xd, xs1, xs2 encoding: match: 0010111----------000-----1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fminm.q.yaml b/arch/inst/Q/fminm.q.yaml index 516edc0bc4..750626e148 100644 --- a/arch/inst/Q/fminm.q.yaml +++ b/arch/inst/Q/fminm.q.yaml @@ -5,19 +5,19 @@ kind: instruction name: fminm.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Q, Zfa] assembly: qd, qs1, qs2 encoding: match: 0010111----------010-----1010011 variables: - - name: qs2 - location: 24-20 - - name: qs1 - location: 19-15 - - name: qd - location: 11-7 + - name: qs2 + location: 24-20 + - name: qs1 + location: 19-15 + - name: qd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fmsub.q.yaml b/arch/inst/Q/fmsub.q.yaml index c92ed5350f..d89c36c474 100644 --- a/arch/inst/Q/fmsub.q.yaml +++ b/arch/inst/Q/fmsub.q.yaml @@ -5,22 +5,22 @@ kind: instruction name: fmsub.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q assembly: qd, qs1, qs2, qs3, rm encoding: match: -----11------------------1000111 variables: - - name: qs3 - location: 31-27 - - name: qs2 - location: 24-20 - - name: qs1 - location: 19-15 - - name: rm - location: 14-12 - - name: qd - location: 11-7 + - name: qs3 + location: 31-27 + - name: qs2 + location: 24-20 + - name: qs1 + location: 19-15 + - name: rm + location: 14-12 + - name: qd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fmul.q.yaml b/arch/inst/Q/fmul.q.yaml index c983cf8fb0..f7088036ac 100644 --- a/arch/inst/Q/fmul.q.yaml +++ b/arch/inst/Q/fmul.q.yaml @@ -5,20 +5,20 @@ kind: instruction name: fmul.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q assembly: qd, qs1, qs2, rm encoding: match: 0001011------------------1010011 variables: - - name: qs2 - location: 24-20 - - name: qs1 - location: 19-15 - - name: rm - location: 14-12 - - name: qd - location: 11-7 + - name: qs2 + location: 24-20 + - name: qs1 + location: 19-15 + - name: rm + location: 14-12 + - name: qd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fmvh.x.q.yaml b/arch/inst/Q/fmvh.x.q.yaml index f067240ac0..4e22012a29 100644 --- a/arch/inst/Q/fmvh.x.q.yaml +++ b/arch/inst/Q/fmvh.x.q.yaml @@ -5,7 +5,7 @@ kind: instruction name: fmvh.x.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Q, Zfa] base: 64 @@ -13,10 +13,10 @@ assembly: xd, qs1 encoding: match: 111001100001-----000-----1010011 variables: - - name: qs1 - location: 19-15 - - name: rd - location: 11-7 + - name: qs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fmvp.q.x.yaml b/arch/inst/Q/fmvp.q.x.yaml index 258e7ccc85..e05d063683 100644 --- a/arch/inst/Q/fmvp.q.x.yaml +++ b/arch/inst/Q/fmvp.q.x.yaml @@ -5,7 +5,7 @@ kind: instruction name: fmvp.q.x long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Q, Zfa] base: 64 @@ -13,12 +13,12 @@ assembly: qd, xs1, xs2 encoding: match: 1011011----------000-----1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fnmadd.q.yaml b/arch/inst/Q/fnmadd.q.yaml index de290b9f3e..5bd3b6d4b3 100644 --- a/arch/inst/Q/fnmadd.q.yaml +++ b/arch/inst/Q/fnmadd.q.yaml @@ -5,22 +5,22 @@ kind: instruction name: fnmadd.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q assembly: qd, qs1, qs2, qs3, rm encoding: match: -----11------------------1001111 variables: - - name: qs3 - location: 31-27 - - name: qs2 - location: 24-20 - - name: qs1 - location: 19-15 - - name: rm - location: 14-12 - - name: qd - location: 11-7 + - name: qs3 + location: 31-27 + - name: qs2 + location: 24-20 + - name: qs1 + location: 19-15 + - name: rm + location: 14-12 + - name: qd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fnmsub.q.yaml b/arch/inst/Q/fnmsub.q.yaml index 805f14c422..8ef81fe0c6 100644 --- a/arch/inst/Q/fnmsub.q.yaml +++ b/arch/inst/Q/fnmsub.q.yaml @@ -5,22 +5,22 @@ kind: instruction name: fnmsub.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q assembly: qd, qs1, qs2, qs3, rm encoding: match: -----11------------------1001011 variables: - - name: qs3 - location: 31-27 - - name: qs2 - location: 24-20 - - name: qs1 - location: 19-15 - - name: rm - location: 14-12 - - name: qd - location: 11-7 + - name: qs3 + location: 31-27 + - name: qs2 + location: 24-20 + - name: qs1 + location: 19-15 + - name: rm + location: 14-12 + - name: qd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fround.q.yaml b/arch/inst/Q/fround.q.yaml index ea1718ab4d..a430445f30 100644 --- a/arch/inst/Q/fround.q.yaml +++ b/arch/inst/Q/fround.q.yaml @@ -5,19 +5,19 @@ kind: instruction name: fround.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Q, Zfa] assembly: qd, qs1, rm encoding: match: 010001100100-------------1010011 variables: - - name: qs1 - location: 19-15 - - name: rm - location: 14-12 - - name: qd - location: 11-7 + - name: qs1 + location: 19-15 + - name: rm + location: 14-12 + - name: qd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/froundnx.q.yaml b/arch/inst/Q/froundnx.q.yaml index ffea7e08cd..360bc9fc25 100644 --- a/arch/inst/Q/froundnx.q.yaml +++ b/arch/inst/Q/froundnx.q.yaml @@ -5,19 +5,19 @@ kind: instruction name: froundnx.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Q, Zfa] assembly: qd, qs1, rm encoding: match: 010001100101-------------1010011 variables: - - name: qs1 - location: 19-15 - - name: rm - location: 14-12 - - name: qd - location: 11-7 + - name: qs1 + location: 19-15 + - name: rm + location: 14-12 + - name: qd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fsgnj.q.yaml b/arch/inst/Q/fsgnj.q.yaml index 489b849900..20dbe8eefe 100644 --- a/arch/inst/Q/fsgnj.q.yaml +++ b/arch/inst/Q/fsgnj.q.yaml @@ -5,18 +5,18 @@ kind: instruction name: fsgnj.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q assembly: qd, qs1, qs2 encoding: match: 0010011----------000-----1010011 variables: - - name: qs2 - location: 24-20 - - name: qs1 - location: 19-15 - - name: qd - location: 11-7 + - name: qs2 + location: 24-20 + - name: qs1 + location: 19-15 + - name: qd + location: 11-7 access: s: always u: always @@ -24,6 +24,6 @@ access: vu: always data_independent_timing: false pseudoinstructions: -- when: (rs2 == rs1) - to: fmv.q + - when: (rs2 == rs1) + to: fmv.q operation(): | diff --git a/arch/inst/Q/fsgnjn.q.yaml b/arch/inst/Q/fsgnjn.q.yaml index 3dc53bba5b..c0e6e2dc4d 100644 --- a/arch/inst/Q/fsgnjn.q.yaml +++ b/arch/inst/Q/fsgnjn.q.yaml @@ -5,18 +5,18 @@ kind: instruction name: fsgnjn.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q assembly: qd, qs1, qs2 encoding: match: 0010011----------001-----1010011 variables: - - name: qs2 - location: 24-20 - - name: qs1 - location: 19-15 - - name: qd - location: 11-7 + - name: qs2 + location: 24-20 + - name: qs1 + location: 19-15 + - name: qd + location: 11-7 access: s: always u: always @@ -24,6 +24,6 @@ access: vu: always data_independent_timing: false pseudoinstructions: -- when: (rs2 == rs1) - to: fneg.q + - when: (rs2 == rs1) + to: fneg.q operation(): | diff --git a/arch/inst/Q/fsgnjx.q.yaml b/arch/inst/Q/fsgnjx.q.yaml index 2cec0796ab..f3f2b13d88 100644 --- a/arch/inst/Q/fsgnjx.q.yaml +++ b/arch/inst/Q/fsgnjx.q.yaml @@ -5,18 +5,18 @@ kind: instruction name: fsgnjx.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q assembly: qd, qs1, qs2 encoding: match: 0010011----------010-----1010011 variables: - - name: qs2 - location: 24-20 - - name: qs1 - location: 19-15 - - name: qd - location: 11-7 + - name: qs2 + location: 24-20 + - name: qs1 + location: 19-15 + - name: qd + location: 11-7 access: s: always u: always @@ -24,6 +24,6 @@ access: vu: always data_independent_timing: false pseudoinstructions: -- when: (rs2 == rs1) - to: fabs.q + - when: (rs2 == rs1) + to: fabs.q operation(): | diff --git a/arch/inst/Q/fsq.yaml b/arch/inst/Q/fsq.yaml index 1b74624a55..dfe6e4ad44 100644 --- a/arch/inst/Q/fsq.yaml +++ b/arch/inst/Q/fsq.yaml @@ -5,18 +5,18 @@ kind: instruction name: fsq long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q assembly: xs1, qs2, imm encoding: match: -----------------100-----0100111 variables: - - name: imm - location: 31-25|11-7 - - name: qs2 - location: 24-20 - - name: rs1 - location: 19-15 + - name: imm + location: 31-25|11-7 + - name: qs2 + location: 24-20 + - name: rs1 + location: 19-15 access: s: always u: always diff --git a/arch/inst/Q/fsqrt.q.yaml b/arch/inst/Q/fsqrt.q.yaml index 9fa9ab3467..9c0e11e530 100644 --- a/arch/inst/Q/fsqrt.q.yaml +++ b/arch/inst/Q/fsqrt.q.yaml @@ -5,18 +5,18 @@ kind: instruction name: fsqrt.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q assembly: qd, qs1, rm encoding: match: 010111100000-------------1010011 variables: - - name: qs1 - location: 19-15 - - name: rm - location: 14-12 - - name: qd - location: 11-7 + - name: qs1 + location: 19-15 + - name: rm + location: 14-12 + - name: qd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Q/fsub.q.yaml b/arch/inst/Q/fsub.q.yaml index 0db8b161c1..554abb1a71 100644 --- a/arch/inst/Q/fsub.q.yaml +++ b/arch/inst/Q/fsub.q.yaml @@ -5,20 +5,20 @@ kind: instruction name: fsub.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Q assembly: qd, qs1, qs2, rm encoding: match: 0000111------------------1010011 variables: - - name: qs2 - location: 24-20 - - name: qs1 - location: 19-15 - - name: rm - location: 14-12 - - name: qd - location: 11-7 + - name: qs2 + location: 24-20 + - name: qs1 + location: 19-15 + - name: rm + location: 14-12 + - name: qd + location: 11-7 access: s: always u: always diff --git a/arch/inst/S/sfence.vma.yaml b/arch/inst/S/sfence.vma.yaml index 8852bf1cfa..ac877929ac 100644 --- a/arch/inst/S/sfence.vma.yaml +++ b/arch/inst/S/sfence.vma.yaml @@ -211,10 +211,10 @@ assembly: xs1, xs2 encoding: match: 0001001----------000000001110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 access: s: always u: never @@ -305,8 +305,6 @@ operation(): | # else, silently do nothing } - - sail(): | { let addr : option(xlenbits) = if rs1 == 0b00000 then None() else Some(X(rs1)); diff --git a/arch/inst/S/sret.yaml b/arch/inst/S/sret.yaml index 3dd2755d14..3f003f3920 100644 --- a/arch/inst/S/sret.yaml +++ b/arch/inst/S/sret.yaml @@ -47,7 +47,7 @@ description: | definedBy: S assembly: "" encoding: - match: '00010000001000000000000001110011' + match: "00010000001000000000000001110011" access: s: sometimes u: never @@ -126,7 +126,6 @@ operation(): | $pc = $bits(CSR[vsepc]); } - sail(): | { let sret_illegal : bool = match cur_privilege { diff --git a/arch/inst/Sdext/dret.yaml b/arch/inst/Sdext/dret.yaml index e8e21a0eab..ee65a75d59 100644 --- a/arch/inst/Sdext/dret.yaml +++ b/arch/inst/Sdext/dret.yaml @@ -5,11 +5,11 @@ kind: instruction name: dret long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Sdext assembly: dret encoding: - match: '01111011001000000000000001110011' + match: "01111011001000000000000001110011" variables: [] access: s: always diff --git a/arch/inst/Smdbltrp/sctrclr.yaml b/arch/inst/Smdbltrp/sctrclr.yaml index f5bd33fb3d..b8f99a943f 100644 --- a/arch/inst/Smdbltrp/sctrclr.yaml +++ b/arch/inst/Smdbltrp/sctrclr.yaml @@ -5,11 +5,11 @@ kind: instruction name: sctrclr long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Smdbltrp assembly: sctrclr encoding: - match: '00010000010000000000000001110011' + match: "00010000010000000000000001110011" variables: [] access: s: always diff --git a/arch/inst/Smrnmi/mnret.yaml b/arch/inst/Smrnmi/mnret.yaml index 5019c47bd6..a91ce53c18 100644 --- a/arch/inst/Smrnmi/mnret.yaml +++ b/arch/inst/Smrnmi/mnret.yaml @@ -5,11 +5,11 @@ kind: instruction name: mnret long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Smrnmi assembly: mnret encoding: - match: '01110000001000000000000001110011' + match: "01110000001000000000000001110011" variables: [] access: s: always diff --git a/arch/inst/Svinval/hinval.gvma.yaml b/arch/inst/Svinval/hinval.gvma.yaml index e53479102d..d8caa76638 100644 --- a/arch/inst/Svinval/hinval.gvma.yaml +++ b/arch/inst/Svinval/hinval.gvma.yaml @@ -6,15 +6,15 @@ name: hinval.gvma long_name: Invalidate cached address translations definedBy: allOf: - - Svinval - - H + - Svinval + - H encoding: match: 0110011----------000000001110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 description: | `hinval.gvma` has the same semantics as `sinval.vma` except that it combines with `sfence.w.inval` and `sfence.inval.ir` to replace `hfence.gvma` and uses VMID instead of ASID. diff --git a/arch/inst/Svinval/hinval.vvma.yaml b/arch/inst/Svinval/hinval.vvma.yaml index 4b65e53c23..5af922825a 100644 --- a/arch/inst/Svinval/hinval.vvma.yaml +++ b/arch/inst/Svinval/hinval.vvma.yaml @@ -6,15 +6,15 @@ name: hinval.vvma long_name: Invalidate cached address translations definedBy: allOf: - - Svinval - - H + - Svinval + - H encoding: match: 0010011----------000000001110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 description: | `hinval.vvma` has the same semantics as `sinval.vma` except that it combines with `sfence.w.inval` and `sfence.inval.ir` to replace `hfence.vvma`. diff --git a/arch/inst/Svinval/sinval.vma.yaml b/arch/inst/Svinval/sinval.vma.yaml index 76f77099ed..8ef06b74f9 100644 --- a/arch/inst/Svinval/sinval.vma.yaml +++ b/arch/inst/Svinval/sinval.vma.yaml @@ -8,10 +8,10 @@ definedBy: Svinval encoding: match: 0001011----------000000001110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 description: The `sinval.vma` instruction invalidates any address-translation cache entries that an `sfence.vma` instruction with the same values of rs1 and rs2 would invalidate. diff --git a/arch/inst/V/vaadd.vv.yaml b/arch/inst/V/vaadd.vv.yaml index 3cbcf12412..0b6966fe7f 100644 --- a/arch/inst/V/vaadd.vv.yaml +++ b/arch/inst/V/vaadd.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vaadd.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 001001-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vaadd.vx.yaml b/arch/inst/V/vaadd.vx.yaml index e806156133..03e13b0d44 100644 --- a/arch/inst/V/vaadd.vx.yaml +++ b/arch/inst/V/vaadd.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vaadd.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 001001-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vaaddu.vv.yaml b/arch/inst/V/vaaddu.vv.yaml index 6c9876175c..3b9c7562fe 100644 --- a/arch/inst/V/vaaddu.vv.yaml +++ b/arch/inst/V/vaaddu.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vaaddu.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 001000-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vaaddu.vx.yaml b/arch/inst/V/vaaddu.vx.yaml index ed14af74b8..90164d1ef1 100644 --- a/arch/inst/V/vaaddu.vx.yaml +++ b/arch/inst/V/vaaddu.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vaaddu.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 001000-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vadc.vim.yaml b/arch/inst/V/vadc.vim.yaml index a071d8dced..fe2eefa6c2 100644 --- a/arch/inst/V/vadc.vim.yaml +++ b/arch/inst/V/vadc.vim.yaml @@ -5,18 +5,18 @@ kind: instruction name: vadc.vim long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, vd, imm encoding: match: 0100000----------011-----1010111 variables: - - name: vs2 - location: 24-20 - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vadc.vvm.yaml b/arch/inst/V/vadc.vvm.yaml index 8d3df8a976..a2049511e6 100644 --- a/arch/inst/V/vadc.vvm.yaml +++ b/arch/inst/V/vadc.vvm.yaml @@ -5,18 +5,18 @@ kind: instruction name: vadc.vvm long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, vs1, vd encoding: match: 0100000----------000-----1010111 variables: - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vadc.vxm.yaml b/arch/inst/V/vadc.vxm.yaml index 5ea996a2a1..b2e2c39789 100644 --- a/arch/inst/V/vadc.vxm.yaml +++ b/arch/inst/V/vadc.vxm.yaml @@ -5,18 +5,18 @@ kind: instruction name: vadc.vxm long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, xs1, vd encoding: match: 0100000----------100-----1010111 variables: - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vadd.vi.yaml b/arch/inst/V/vadd.vi.yaml index d1f92d0019..c12f08144e 100644 --- a/arch/inst/V/vadd.vi.yaml +++ b/arch/inst/V/vadd.vi.yaml @@ -5,20 +5,20 @@ kind: instruction name: vadd.vi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd, imm encoding: match: 000000-----------011-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vadd.vv.yaml b/arch/inst/V/vadd.vv.yaml index 889991a14e..a280ed6b4a 100644 --- a/arch/inst/V/vadd.vv.yaml +++ b/arch/inst/V/vadd.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vadd.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 000000-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW_pow = get_sew_pow(); diff --git a/arch/inst/V/vadd.vx.yaml b/arch/inst/V/vadd.vx.yaml index fde718be15..61127518bc 100644 --- a/arch/inst/V/vadd.vx.yaml +++ b/arch/inst/V/vadd.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vadd.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 000000-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vand.vi.yaml b/arch/inst/V/vand.vi.yaml index fe43e62fdd..d6916defd1 100644 --- a/arch/inst/V/vand.vi.yaml +++ b/arch/inst/V/vand.vi.yaml @@ -5,20 +5,20 @@ kind: instruction name: vand.vi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd, imm encoding: match: 001001-----------011-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vand.vv.yaml b/arch/inst/V/vand.vv.yaml index f016448109..afb8dc2288 100644 --- a/arch/inst/V/vand.vv.yaml +++ b/arch/inst/V/vand.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vand.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 001001-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW_pow = get_sew_pow(); diff --git a/arch/inst/V/vand.vx.yaml b/arch/inst/V/vand.vx.yaml index efeb6977bc..6b6318c25e 100644 --- a/arch/inst/V/vand.vx.yaml +++ b/arch/inst/V/vand.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vand.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 001001-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vasub.vv.yaml b/arch/inst/V/vasub.vv.yaml index 7d1b7c2824..645f2a5894 100644 --- a/arch/inst/V/vasub.vv.yaml +++ b/arch/inst/V/vasub.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vasub.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 001011-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vasub.vx.yaml b/arch/inst/V/vasub.vx.yaml index 54e8f87c6c..d7112c4326 100644 --- a/arch/inst/V/vasub.vx.yaml +++ b/arch/inst/V/vasub.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vasub.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 001011-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vasubu.vv.yaml b/arch/inst/V/vasubu.vv.yaml index bc24e0a97d..c1005068df 100644 --- a/arch/inst/V/vasubu.vv.yaml +++ b/arch/inst/V/vasubu.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vasubu.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 001010-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vasubu.vx.yaml b/arch/inst/V/vasubu.vx.yaml index af8d897ccf..0b21717cd8 100644 --- a/arch/inst/V/vasubu.vx.yaml +++ b/arch/inst/V/vasubu.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vasubu.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 001010-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vcompress.vm.yaml b/arch/inst/V/vcompress.vm.yaml index fd84e7a33f..84653e204f 100644 --- a/arch/inst/V/vcompress.vm.yaml +++ b/arch/inst/V/vcompress.vm.yaml @@ -5,18 +5,18 @@ kind: instruction name: vcompress.vm long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, vs1, vd encoding: match: 0101111----------010-----1010111 variables: - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let start_element = get_start_element(); diff --git a/arch/inst/V/vcpop.m.yaml b/arch/inst/V/vcpop.m.yaml index 19bea2ad8e..b517221880 100644 --- a/arch/inst/V/vcpop.m.yaml +++ b/arch/inst/V/vcpop.m.yaml @@ -5,18 +5,18 @@ kind: instruction name: vcpop.m long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xd encoding: match: 010000------10000010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vdiv.vv.yaml b/arch/inst/V/vdiv.vv.yaml index a11d7fca27..e97abdf49d 100644 --- a/arch/inst/V/vdiv.vv.yaml +++ b/arch/inst/V/vdiv.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vdiv.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 100001-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vdiv.vx.yaml b/arch/inst/V/vdiv.vx.yaml index 88fbb442ab..cc006e8a13 100644 --- a/arch/inst/V/vdiv.vx.yaml +++ b/arch/inst/V/vdiv.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vdiv.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 100001-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vdivu.vv.yaml b/arch/inst/V/vdivu.vv.yaml index c0f330bb16..d7b4d8ea43 100644 --- a/arch/inst/V/vdivu.vv.yaml +++ b/arch/inst/V/vdivu.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vdivu.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 100000-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vdivu.vx.yaml b/arch/inst/V/vdivu.vx.yaml index ebf0b05f13..cbe3bfe308 100644 --- a/arch/inst/V/vdivu.vx.yaml +++ b/arch/inst/V/vdivu.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vdivu.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 100000-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vfadd.vf.yaml b/arch/inst/V/vfadd.vf.yaml index 43a191d645..5aee28612e 100644 --- a/arch/inst/V/vfadd.vf.yaml +++ b/arch/inst/V/vfadd.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfadd.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 000000-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfadd.vv.yaml b/arch/inst/V/vfadd.vv.yaml index e53b9c0306..156a55057e 100644 --- a/arch/inst/V/vfadd.vv.yaml +++ b/arch/inst/V/vfadd.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfadd.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 000000-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfclass.v.yaml b/arch/inst/V/vfclass.v.yaml index 72947448c4..b78b61c397 100644 --- a/arch/inst/V/vfclass.v.yaml +++ b/arch/inst/V/vfclass.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vfclass.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010011------10000001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfcvt.f.x.v.yaml b/arch/inst/V/vfcvt.f.x.v.yaml index c94dd1143f..2a543ff27c 100644 --- a/arch/inst/V/vfcvt.f.x.v.yaml +++ b/arch/inst/V/vfcvt.f.x.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vfcvt.f.x.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010010------00011001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfcvt.f.xu.v.yaml b/arch/inst/V/vfcvt.f.xu.v.yaml index f0b93c8643..78ae990d5d 100644 --- a/arch/inst/V/vfcvt.f.xu.v.yaml +++ b/arch/inst/V/vfcvt.f.xu.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vfcvt.f.xu.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010010------00010001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfcvt.rtz.x.f.v.yaml b/arch/inst/V/vfcvt.rtz.x.f.v.yaml index f2f2d7a34b..1cd3617375 100644 --- a/arch/inst/V/vfcvt.rtz.x.f.v.yaml +++ b/arch/inst/V/vfcvt.rtz.x.f.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vfcvt.rtz.x.f.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010010------00111001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfcvt.rtz.xu.f.v.yaml b/arch/inst/V/vfcvt.rtz.xu.f.v.yaml index 111c599846..44c874e151 100644 --- a/arch/inst/V/vfcvt.rtz.xu.f.v.yaml +++ b/arch/inst/V/vfcvt.rtz.xu.f.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vfcvt.rtz.xu.f.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010010------00110001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfcvt.x.f.v.yaml b/arch/inst/V/vfcvt.x.f.v.yaml index 8cca1f4db3..51af8e423f 100644 --- a/arch/inst/V/vfcvt.x.f.v.yaml +++ b/arch/inst/V/vfcvt.x.f.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vfcvt.x.f.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010010------00001001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfcvt.xu.f.v.yaml b/arch/inst/V/vfcvt.xu.f.v.yaml index 7fa8aae9b0..a411ca3752 100644 --- a/arch/inst/V/vfcvt.xu.f.v.yaml +++ b/arch/inst/V/vfcvt.xu.f.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vfcvt.xu.f.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010010------00000001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfdiv.vf.yaml b/arch/inst/V/vfdiv.vf.yaml index 131540b4e4..2a01a08b64 100644 --- a/arch/inst/V/vfdiv.vf.yaml +++ b/arch/inst/V/vfdiv.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfdiv.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 100000-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfdiv.vv.yaml b/arch/inst/V/vfdiv.vv.yaml index 6590ecbf67..756d7b6865 100644 --- a/arch/inst/V/vfdiv.vv.yaml +++ b/arch/inst/V/vfdiv.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfdiv.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 100000-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfirst.m.yaml b/arch/inst/V/vfirst.m.yaml index c05ebe85ca..32dc051c70 100644 --- a/arch/inst/V/vfirst.m.yaml +++ b/arch/inst/V/vfirst.m.yaml @@ -5,18 +5,18 @@ kind: instruction name: vfirst.m long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xd encoding: match: 010000------10001010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vfmacc.vf.yaml b/arch/inst/V/vfmacc.vf.yaml index 9c6529d0ce..9344bec1f2 100644 --- a/arch/inst/V/vfmacc.vf.yaml +++ b/arch/inst/V/vfmacc.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfmacc.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 101100-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfmacc.vv.yaml b/arch/inst/V/vfmacc.vv.yaml index ae596e3e3b..c47710addc 100644 --- a/arch/inst/V/vfmacc.vv.yaml +++ b/arch/inst/V/vfmacc.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfmacc.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 101100-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfmadd.vf.yaml b/arch/inst/V/vfmadd.vf.yaml index 14d73f06f8..11fc3a7fad 100644 --- a/arch/inst/V/vfmadd.vf.yaml +++ b/arch/inst/V/vfmadd.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfmadd.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 101000-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfmadd.vv.yaml b/arch/inst/V/vfmadd.vv.yaml index 2541125be1..91364916f0 100644 --- a/arch/inst/V/vfmadd.vv.yaml +++ b/arch/inst/V/vfmadd.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfmadd.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 101000-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfmax.vf.yaml b/arch/inst/V/vfmax.vf.yaml index 0cc30b7346..e4ce7d1db7 100644 --- a/arch/inst/V/vfmax.vf.yaml +++ b/arch/inst/V/vfmax.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfmax.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 000110-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfmax.vv.yaml b/arch/inst/V/vfmax.vv.yaml index 743ea0f91f..ade095ba57 100644 --- a/arch/inst/V/vfmax.vv.yaml +++ b/arch/inst/V/vfmax.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfmax.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 000110-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfmerge.vfm.yaml b/arch/inst/V/vfmerge.vfm.yaml index 86dd3a028f..45d2f63d36 100644 --- a/arch/inst/V/vfmerge.vfm.yaml +++ b/arch/inst/V/vfmerge.vfm.yaml @@ -5,18 +5,18 @@ kind: instruction name: vfmerge.vfm long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, xs1, vd encoding: match: 0101110----------101-----1010111 variables: - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfmin.vf.yaml b/arch/inst/V/vfmin.vf.yaml index ab540d32b6..49037450c0 100644 --- a/arch/inst/V/vfmin.vf.yaml +++ b/arch/inst/V/vfmin.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfmin.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 000100-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfmin.vv.yaml b/arch/inst/V/vfmin.vv.yaml index 991efa7e80..5ccf624970 100644 --- a/arch/inst/V/vfmin.vv.yaml +++ b/arch/inst/V/vfmin.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfmin.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 000100-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfmsac.vf.yaml b/arch/inst/V/vfmsac.vf.yaml index 34c3c371b5..401febe42d 100644 --- a/arch/inst/V/vfmsac.vf.yaml +++ b/arch/inst/V/vfmsac.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfmsac.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 101110-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfmsac.vv.yaml b/arch/inst/V/vfmsac.vv.yaml index 1e734383a0..3ff6fb6c0b 100644 --- a/arch/inst/V/vfmsac.vv.yaml +++ b/arch/inst/V/vfmsac.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfmsac.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 101110-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfmsub.vf.yaml b/arch/inst/V/vfmsub.vf.yaml index ced3598cb3..9029bbfe4a 100644 --- a/arch/inst/V/vfmsub.vf.yaml +++ b/arch/inst/V/vfmsub.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfmsub.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 101010-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfmsub.vv.yaml b/arch/inst/V/vfmsub.vv.yaml index e33500bb50..6564812fce 100644 --- a/arch/inst/V/vfmsub.vv.yaml +++ b/arch/inst/V/vfmsub.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfmsub.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 101010-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfmul.vf.yaml b/arch/inst/V/vfmul.vf.yaml index 74a6030002..c12c2b1a4a 100644 --- a/arch/inst/V/vfmul.vf.yaml +++ b/arch/inst/V/vfmul.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfmul.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 100100-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfmul.vv.yaml b/arch/inst/V/vfmul.vv.yaml index f1cb3a8c79..f4a2fc2404 100644 --- a/arch/inst/V/vfmul.vv.yaml +++ b/arch/inst/V/vfmul.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfmul.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 100100-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfmv.f.s.yaml b/arch/inst/V/vfmv.f.s.yaml index c3f72cd968..b1107b27ff 100644 --- a/arch/inst/V/vfmv.f.s.yaml +++ b/arch/inst/V/vfmv.f.s.yaml @@ -5,16 +5,16 @@ kind: instruction name: vfmv.f.s long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, xd encoding: match: 0100001-----00000001-----1010111 variables: - - name: vs2 - location: 24-20 - - name: rd - location: 11-7 + - name: vs2 + location: 24-20 + - name: rd + location: 11-7 access: s: always u: always @@ -23,9 +23,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfmv.s.f.yaml b/arch/inst/V/vfmv.s.f.yaml index 80b57dc40d..37c250ef75 100644 --- a/arch/inst/V/vfmv.s.f.yaml +++ b/arch/inst/V/vfmv.s.f.yaml @@ -5,16 +5,16 @@ kind: instruction name: vfmv.s.f long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: xs1, vd encoding: match: 010000100000-----101-----1010111 variables: - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -23,9 +23,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfmv.v.f.yaml b/arch/inst/V/vfmv.v.f.yaml index e1fe60deb3..28e2405a8f 100644 --- a/arch/inst/V/vfmv.v.f.yaml +++ b/arch/inst/V/vfmv.v.f.yaml @@ -5,16 +5,16 @@ kind: instruction name: vfmv.v.f long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: xs1, vd encoding: match: 010111100000-----101-----1010111 variables: - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -23,9 +23,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfncvt.f.f.w.yaml b/arch/inst/V/vfncvt.f.f.w.yaml index d07719336d..6f3779646b 100644 --- a/arch/inst/V/vfncvt.f.f.w.yaml +++ b/arch/inst/V/vfncvt.f.f.w.yaml @@ -5,18 +5,18 @@ kind: instruction name: vfncvt.f.f.w long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010010------10100001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfncvt.f.x.w.yaml b/arch/inst/V/vfncvt.f.x.w.yaml index 64076200d2..0214617241 100644 --- a/arch/inst/V/vfncvt.f.x.w.yaml +++ b/arch/inst/V/vfncvt.f.x.w.yaml @@ -5,18 +5,18 @@ kind: instruction name: vfncvt.f.x.w long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010010------10011001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfncvt.f.xu.w.yaml b/arch/inst/V/vfncvt.f.xu.w.yaml index 1ffb9a8cb4..46a2663ba8 100644 --- a/arch/inst/V/vfncvt.f.xu.w.yaml +++ b/arch/inst/V/vfncvt.f.xu.w.yaml @@ -5,18 +5,18 @@ kind: instruction name: vfncvt.f.xu.w long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010010------10010001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfncvt.rod.f.f.w.yaml b/arch/inst/V/vfncvt.rod.f.f.w.yaml index 7b5c051c7a..02555f003e 100644 --- a/arch/inst/V/vfncvt.rod.f.f.w.yaml +++ b/arch/inst/V/vfncvt.rod.f.f.w.yaml @@ -5,18 +5,18 @@ kind: instruction name: vfncvt.rod.f.f.w long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010010------10101001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfncvt.rtz.x.f.w.yaml b/arch/inst/V/vfncvt.rtz.x.f.w.yaml index a4537a2e78..ebcbdd4b44 100644 --- a/arch/inst/V/vfncvt.rtz.x.f.w.yaml +++ b/arch/inst/V/vfncvt.rtz.x.f.w.yaml @@ -5,18 +5,18 @@ kind: instruction name: vfncvt.rtz.x.f.w long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010010------10111001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfncvt.rtz.xu.f.w.yaml b/arch/inst/V/vfncvt.rtz.xu.f.w.yaml index 62bede1c42..0b3f874d53 100644 --- a/arch/inst/V/vfncvt.rtz.xu.f.w.yaml +++ b/arch/inst/V/vfncvt.rtz.xu.f.w.yaml @@ -5,18 +5,18 @@ kind: instruction name: vfncvt.rtz.xu.f.w long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010010------10110001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfncvt.x.f.w.yaml b/arch/inst/V/vfncvt.x.f.w.yaml index 75ff14b03d..f0877ef3f9 100644 --- a/arch/inst/V/vfncvt.x.f.w.yaml +++ b/arch/inst/V/vfncvt.x.f.w.yaml @@ -5,18 +5,18 @@ kind: instruction name: vfncvt.x.f.w long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010010------10001001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfncvt.xu.f.w.yaml b/arch/inst/V/vfncvt.xu.f.w.yaml index 37345ccd04..e0560c4dbf 100644 --- a/arch/inst/V/vfncvt.xu.f.w.yaml +++ b/arch/inst/V/vfncvt.xu.f.w.yaml @@ -5,18 +5,18 @@ kind: instruction name: vfncvt.xu.f.w long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010010------10000001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfnmacc.vf.yaml b/arch/inst/V/vfnmacc.vf.yaml index b2c079a45c..a4d07f05d2 100644 --- a/arch/inst/V/vfnmacc.vf.yaml +++ b/arch/inst/V/vfnmacc.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfnmacc.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 101101-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfnmacc.vv.yaml b/arch/inst/V/vfnmacc.vv.yaml index 7d09fa94d6..109d253f26 100644 --- a/arch/inst/V/vfnmacc.vv.yaml +++ b/arch/inst/V/vfnmacc.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfnmacc.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 101101-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfnmadd.vf.yaml b/arch/inst/V/vfnmadd.vf.yaml index 4023db2a30..96b4c2cb50 100644 --- a/arch/inst/V/vfnmadd.vf.yaml +++ b/arch/inst/V/vfnmadd.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfnmadd.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 101001-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfnmadd.vv.yaml b/arch/inst/V/vfnmadd.vv.yaml index 2f25198c45..c180cfa5b1 100644 --- a/arch/inst/V/vfnmadd.vv.yaml +++ b/arch/inst/V/vfnmadd.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfnmadd.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 101001-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfnmsac.vf.yaml b/arch/inst/V/vfnmsac.vf.yaml index 2e2a4c7206..77d9b7fd0f 100644 --- a/arch/inst/V/vfnmsac.vf.yaml +++ b/arch/inst/V/vfnmsac.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfnmsac.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 101111-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfnmsac.vv.yaml b/arch/inst/V/vfnmsac.vv.yaml index 28eddb89cc..8531bcae51 100644 --- a/arch/inst/V/vfnmsac.vv.yaml +++ b/arch/inst/V/vfnmsac.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfnmsac.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 101111-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfnmsub.vf.yaml b/arch/inst/V/vfnmsub.vf.yaml index efab79dae7..61aa40ed2d 100644 --- a/arch/inst/V/vfnmsub.vf.yaml +++ b/arch/inst/V/vfnmsub.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfnmsub.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 101011-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfnmsub.vv.yaml b/arch/inst/V/vfnmsub.vv.yaml index d279ebff9e..fb18f34932 100644 --- a/arch/inst/V/vfnmsub.vv.yaml +++ b/arch/inst/V/vfnmsub.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfnmsub.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 101011-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfrdiv.vf.yaml b/arch/inst/V/vfrdiv.vf.yaml index 78f64d7f1b..2b36ad2c54 100644 --- a/arch/inst/V/vfrdiv.vf.yaml +++ b/arch/inst/V/vfrdiv.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfrdiv.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 100001-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfrec7.v.yaml b/arch/inst/V/vfrec7.v.yaml index 40a7439bd3..e63995f7ec 100644 --- a/arch/inst/V/vfrec7.v.yaml +++ b/arch/inst/V/vfrec7.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vfrec7.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010011------00101001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfredmax.vs.yaml b/arch/inst/V/vfredmax.vs.yaml index 12277a66b9..6473da80f8 100644 --- a/arch/inst/V/vfredmax.vs.yaml +++ b/arch/inst/V/vfredmax.vs.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfredmax.vs long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 000111-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vfredmin.vs.yaml b/arch/inst/V/vfredmin.vs.yaml index b4609fd352..2edeecb2b5 100644 --- a/arch/inst/V/vfredmin.vs.yaml +++ b/arch/inst/V/vfredmin.vs.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfredmin.vs long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 000101-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vfredosum.vs.yaml b/arch/inst/V/vfredosum.vs.yaml index bea668e79e..67d6af8322 100644 --- a/arch/inst/V/vfredosum.vs.yaml +++ b/arch/inst/V/vfredosum.vs.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfredosum.vs long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 000011-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vfredusum.vs.yaml b/arch/inst/V/vfredusum.vs.yaml index b8e38ee7d6..a46ab889d3 100644 --- a/arch/inst/V/vfredusum.vs.yaml +++ b/arch/inst/V/vfredusum.vs.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfredusum.vs long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 000001-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vfrsqrt7.v.yaml b/arch/inst/V/vfrsqrt7.v.yaml index fbbf128cd0..8294f7010f 100644 --- a/arch/inst/V/vfrsqrt7.v.yaml +++ b/arch/inst/V/vfrsqrt7.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vfrsqrt7.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010011------00100001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfrsub.vf.yaml b/arch/inst/V/vfrsub.vf.yaml index 1dea2de7e3..6f9f524654 100644 --- a/arch/inst/V/vfrsub.vf.yaml +++ b/arch/inst/V/vfrsub.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfrsub.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 100111-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfsgnj.vf.yaml b/arch/inst/V/vfsgnj.vf.yaml index b5bad7a7b6..95f9a0483f 100644 --- a/arch/inst/V/vfsgnj.vf.yaml +++ b/arch/inst/V/vfsgnj.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfsgnj.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 001000-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfsgnj.vv.yaml b/arch/inst/V/vfsgnj.vv.yaml index c62ba75b27..58fbf938cc 100644 --- a/arch/inst/V/vfsgnj.vv.yaml +++ b/arch/inst/V/vfsgnj.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfsgnj.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 001000-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfsgnjn.vf.yaml b/arch/inst/V/vfsgnjn.vf.yaml index aadd118eed..1ebc156010 100644 --- a/arch/inst/V/vfsgnjn.vf.yaml +++ b/arch/inst/V/vfsgnjn.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfsgnjn.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 001001-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfsgnjn.vv.yaml b/arch/inst/V/vfsgnjn.vv.yaml index f5e6507af1..e6a04c9536 100644 --- a/arch/inst/V/vfsgnjn.vv.yaml +++ b/arch/inst/V/vfsgnjn.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfsgnjn.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 001001-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfsgnjx.vf.yaml b/arch/inst/V/vfsgnjx.vf.yaml index 39e3e1bcc9..21860c151f 100644 --- a/arch/inst/V/vfsgnjx.vf.yaml +++ b/arch/inst/V/vfsgnjx.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfsgnjx.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 001010-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfsgnjx.vv.yaml b/arch/inst/V/vfsgnjx.vv.yaml index 7f674c9dca..31f6fa429b 100644 --- a/arch/inst/V/vfsgnjx.vv.yaml +++ b/arch/inst/V/vfsgnjx.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfsgnjx.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 001010-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfslide1down.vf.yaml b/arch/inst/V/vfslide1down.vf.yaml index e30cfe155d..988f74f067 100644 --- a/arch/inst/V/vfslide1down.vf.yaml +++ b/arch/inst/V/vfslide1down.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfslide1down.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 001111-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfslide1up.vf.yaml b/arch/inst/V/vfslide1up.vf.yaml index eb6f1da876..2846b287bb 100644 --- a/arch/inst/V/vfslide1up.vf.yaml +++ b/arch/inst/V/vfslide1up.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfslide1up.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 001110-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfsqrt.v.yaml b/arch/inst/V/vfsqrt.v.yaml index 9fa78136e1..fad2f602bb 100644 --- a/arch/inst/V/vfsqrt.v.yaml +++ b/arch/inst/V/vfsqrt.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vfsqrt.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010011------00000001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfsub.vf.yaml b/arch/inst/V/vfsub.vf.yaml index d550048917..319c49e7f8 100644 --- a/arch/inst/V/vfsub.vf.yaml +++ b/arch/inst/V/vfsub.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfsub.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 000010-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfsub.vv.yaml b/arch/inst/V/vfsub.vv.yaml index 099d1ca6e1..e28ca0eafb 100644 --- a/arch/inst/V/vfsub.vv.yaml +++ b/arch/inst/V/vfsub.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfsub.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 000010-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfwadd.vf.yaml b/arch/inst/V/vfwadd.vf.yaml index 8449fafc3c..62ee2ff690 100644 --- a/arch/inst/V/vfwadd.vf.yaml +++ b/arch/inst/V/vfwadd.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfwadd.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 110000-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfwadd.vv.yaml b/arch/inst/V/vfwadd.vv.yaml index fdc57af864..af3c01af87 100644 --- a/arch/inst/V/vfwadd.vv.yaml +++ b/arch/inst/V/vfwadd.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfwadd.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 110000-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfwadd.wf.yaml b/arch/inst/V/vfwadd.wf.yaml index 6a169ba6a0..6e27a8d14e 100644 --- a/arch/inst/V/vfwadd.wf.yaml +++ b/arch/inst/V/vfwadd.wf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfwadd.wf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 110100-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfwadd.wv.yaml b/arch/inst/V/vfwadd.wv.yaml index 668fde5635..a5b5157ae3 100644 --- a/arch/inst/V/vfwadd.wv.yaml +++ b/arch/inst/V/vfwadd.wv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfwadd.wv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 110100-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfwcvt.f.f.v.yaml b/arch/inst/V/vfwcvt.f.f.v.yaml index 13891efc9d..c261e3e3c5 100644 --- a/arch/inst/V/vfwcvt.f.f.v.yaml +++ b/arch/inst/V/vfwcvt.f.f.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vfwcvt.f.f.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010010------01100001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfwcvt.f.x.v.yaml b/arch/inst/V/vfwcvt.f.x.v.yaml index a4cac43c79..2ac1e94018 100644 --- a/arch/inst/V/vfwcvt.f.x.v.yaml +++ b/arch/inst/V/vfwcvt.f.x.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vfwcvt.f.x.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010010------01011001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfwcvt.f.xu.v.yaml b/arch/inst/V/vfwcvt.f.xu.v.yaml index 2451307f09..73bde966ce 100644 --- a/arch/inst/V/vfwcvt.f.xu.v.yaml +++ b/arch/inst/V/vfwcvt.f.xu.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vfwcvt.f.xu.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010010------01010001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfwcvt.rtz.x.f.v.yaml b/arch/inst/V/vfwcvt.rtz.x.f.v.yaml index ccd031fbba..cd30932ab0 100644 --- a/arch/inst/V/vfwcvt.rtz.x.f.v.yaml +++ b/arch/inst/V/vfwcvt.rtz.x.f.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vfwcvt.rtz.x.f.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010010------01111001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfwcvt.rtz.xu.f.v.yaml b/arch/inst/V/vfwcvt.rtz.xu.f.v.yaml index 2df02a61bc..a828b78e56 100644 --- a/arch/inst/V/vfwcvt.rtz.xu.f.v.yaml +++ b/arch/inst/V/vfwcvt.rtz.xu.f.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vfwcvt.rtz.xu.f.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010010------01110001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfwcvt.x.f.v.yaml b/arch/inst/V/vfwcvt.x.f.v.yaml index b6337cd145..4e69948bc8 100644 --- a/arch/inst/V/vfwcvt.x.f.v.yaml +++ b/arch/inst/V/vfwcvt.x.f.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vfwcvt.x.f.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010010------01001001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfwcvt.xu.f.v.yaml b/arch/inst/V/vfwcvt.xu.f.v.yaml index dc47501e7b..a93aef64ef 100644 --- a/arch/inst/V/vfwcvt.xu.f.v.yaml +++ b/arch/inst/V/vfwcvt.xu.f.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vfwcvt.xu.f.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010010------01000001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfwmacc.vf.yaml b/arch/inst/V/vfwmacc.vf.yaml index bb3c336f8d..7baff68b96 100644 --- a/arch/inst/V/vfwmacc.vf.yaml +++ b/arch/inst/V/vfwmacc.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfwmacc.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 111100-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfwmacc.vv.yaml b/arch/inst/V/vfwmacc.vv.yaml index 18452f228f..9e24da41e9 100644 --- a/arch/inst/V/vfwmacc.vv.yaml +++ b/arch/inst/V/vfwmacc.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfwmacc.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 111100-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfwmsac.vf.yaml b/arch/inst/V/vfwmsac.vf.yaml index 2b48219488..e1b5bbab3b 100644 --- a/arch/inst/V/vfwmsac.vf.yaml +++ b/arch/inst/V/vfwmsac.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfwmsac.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 111110-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfwmsac.vv.yaml b/arch/inst/V/vfwmsac.vv.yaml index 06a86bfb54..b2c9e3efda 100644 --- a/arch/inst/V/vfwmsac.vv.yaml +++ b/arch/inst/V/vfwmsac.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfwmsac.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 111110-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfwmul.vf.yaml b/arch/inst/V/vfwmul.vf.yaml index c1b8c8982a..fb34150d37 100644 --- a/arch/inst/V/vfwmul.vf.yaml +++ b/arch/inst/V/vfwmul.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfwmul.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 111000-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfwmul.vv.yaml b/arch/inst/V/vfwmul.vv.yaml index e91a5c378d..874a1c4cf5 100644 --- a/arch/inst/V/vfwmul.vv.yaml +++ b/arch/inst/V/vfwmul.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfwmul.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 111000-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfwnmacc.vf.yaml b/arch/inst/V/vfwnmacc.vf.yaml index 67e5dcfe66..0111d351f0 100644 --- a/arch/inst/V/vfwnmacc.vf.yaml +++ b/arch/inst/V/vfwnmacc.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfwnmacc.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 111101-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfwnmacc.vv.yaml b/arch/inst/V/vfwnmacc.vv.yaml index 3968400265..583c885947 100644 --- a/arch/inst/V/vfwnmacc.vv.yaml +++ b/arch/inst/V/vfwnmacc.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfwnmacc.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 111101-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfwnmsac.vf.yaml b/arch/inst/V/vfwnmsac.vf.yaml index f5dc85df9f..78dfdb8418 100644 --- a/arch/inst/V/vfwnmsac.vf.yaml +++ b/arch/inst/V/vfwnmsac.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfwnmsac.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 111111-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfwnmsac.vv.yaml b/arch/inst/V/vfwnmsac.vv.yaml index 17af8f3393..915aa3aa18 100644 --- a/arch/inst/V/vfwnmsac.vv.yaml +++ b/arch/inst/V/vfwnmsac.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfwnmsac.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 111111-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfwredosum.vs.yaml b/arch/inst/V/vfwredosum.vs.yaml index ea97af98ac..9c8e0d4aa3 100644 --- a/arch/inst/V/vfwredosum.vs.yaml +++ b/arch/inst/V/vfwredosum.vs.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfwredosum.vs long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 110011-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vfwredusum.vs.yaml b/arch/inst/V/vfwredusum.vs.yaml index b0e69de551..e04a02d0f4 100644 --- a/arch/inst/V/vfwredusum.vs.yaml +++ b/arch/inst/V/vfwredusum.vs.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfwredusum.vs long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 110001-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vfwsub.vf.yaml b/arch/inst/V/vfwsub.vf.yaml index d06f57f18e..59a755dc2d 100644 --- a/arch/inst/V/vfwsub.vf.yaml +++ b/arch/inst/V/vfwsub.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfwsub.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 110010-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfwsub.vv.yaml b/arch/inst/V/vfwsub.vv.yaml index 02b06af2f6..06e45d8287 100644 --- a/arch/inst/V/vfwsub.vv.yaml +++ b/arch/inst/V/vfwsub.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfwsub.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 110010-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfwsub.wf.yaml b/arch/inst/V/vfwsub.wf.yaml index 1ec5f744c3..8b49b9772f 100644 --- a/arch/inst/V/vfwsub.wf.yaml +++ b/arch/inst/V/vfwsub.wf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfwsub.wf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 110110-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vfwsub.wv.yaml b/arch/inst/V/vfwsub.wv.yaml index c60ee91d16..8412d8981f 100644 --- a/arch/inst/V/vfwsub.wv.yaml +++ b/arch/inst/V/vfwsub.wv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfwsub.wv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 110110-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vid.v.yaml b/arch/inst/V/vid.v.yaml index b5c27cc73c..509ad1f9ba 100644 --- a/arch/inst/V/vid.v.yaml +++ b/arch/inst/V/vid.v.yaml @@ -5,16 +5,16 @@ kind: instruction name: vid.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vd encoding: match: 010100-0000010001010-----1010111 variables: - - name: vm - location: 25-25 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vd + location: 11-7 access: s: always u: always @@ -23,9 +23,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/viota.m.yaml b/arch/inst/V/viota.m.yaml index 1991cdaa97..312dfe959b 100644 --- a/arch/inst/V/viota.m.yaml +++ b/arch/inst/V/viota.m.yaml @@ -5,18 +5,18 @@ kind: instruction name: viota.m long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010100------10000010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vl1re16.v.yaml b/arch/inst/V/vl1re16.v.yaml index 0a6cb1075c..97c243877b 100644 --- a/arch/inst/V/vl1re16.v.yaml +++ b/arch/inst/V/vl1re16.v.yaml @@ -5,16 +5,16 @@ kind: instruction name: vl1re16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: xs1, vd encoding: match: 000000101000-----101-----0000111 variables: - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vl1re32.v.yaml b/arch/inst/V/vl1re32.v.yaml index 294c7203e2..f2e08f12ba 100644 --- a/arch/inst/V/vl1re32.v.yaml +++ b/arch/inst/V/vl1re32.v.yaml @@ -5,16 +5,16 @@ kind: instruction name: vl1re32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: xs1, vd encoding: match: 000000101000-----110-----0000111 variables: - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vl1re64.v.yaml b/arch/inst/V/vl1re64.v.yaml index 0c1a4e6a39..bd4ab27dc5 100644 --- a/arch/inst/V/vl1re64.v.yaml +++ b/arch/inst/V/vl1re64.v.yaml @@ -5,16 +5,16 @@ kind: instruction name: vl1re64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: xs1, vd encoding: match: 000000101000-----111-----0000111 variables: - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vl1re8.v.yaml b/arch/inst/V/vl1re8.v.yaml index 7997910333..dacab09b31 100644 --- a/arch/inst/V/vl1re8.v.yaml +++ b/arch/inst/V/vl1re8.v.yaml @@ -5,16 +5,16 @@ kind: instruction name: vl1re8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: xs1, vd encoding: match: 000000101000-----000-----0000111 variables: - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vl2re16.v.yaml b/arch/inst/V/vl2re16.v.yaml index e0cab471ff..bc1a676667 100644 --- a/arch/inst/V/vl2re16.v.yaml +++ b/arch/inst/V/vl2re16.v.yaml @@ -5,16 +5,16 @@ kind: instruction name: vl2re16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: xs1, vd encoding: match: 001000101000-----101-----0000111 variables: - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vl2re32.v.yaml b/arch/inst/V/vl2re32.v.yaml index e8e6aeb442..34bbc9537e 100644 --- a/arch/inst/V/vl2re32.v.yaml +++ b/arch/inst/V/vl2re32.v.yaml @@ -5,16 +5,16 @@ kind: instruction name: vl2re32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: xs1, vd encoding: match: 001000101000-----110-----0000111 variables: - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vl2re64.v.yaml b/arch/inst/V/vl2re64.v.yaml index 785489b923..bccb7e19b6 100644 --- a/arch/inst/V/vl2re64.v.yaml +++ b/arch/inst/V/vl2re64.v.yaml @@ -5,16 +5,16 @@ kind: instruction name: vl2re64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: xs1, vd encoding: match: 001000101000-----111-----0000111 variables: - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vl2re8.v.yaml b/arch/inst/V/vl2re8.v.yaml index 70f528b523..bc11729ce0 100644 --- a/arch/inst/V/vl2re8.v.yaml +++ b/arch/inst/V/vl2re8.v.yaml @@ -5,16 +5,16 @@ kind: instruction name: vl2re8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: xs1, vd encoding: match: 001000101000-----000-----0000111 variables: - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vl4re16.v.yaml b/arch/inst/V/vl4re16.v.yaml index 6a8533926f..d3759bed84 100644 --- a/arch/inst/V/vl4re16.v.yaml +++ b/arch/inst/V/vl4re16.v.yaml @@ -5,16 +5,16 @@ kind: instruction name: vl4re16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: xs1, vd encoding: match: 011000101000-----101-----0000111 variables: - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vl4re32.v.yaml b/arch/inst/V/vl4re32.v.yaml index 50ffcb9b74..556b565aa1 100644 --- a/arch/inst/V/vl4re32.v.yaml +++ b/arch/inst/V/vl4re32.v.yaml @@ -5,16 +5,16 @@ kind: instruction name: vl4re32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: xs1, vd encoding: match: 011000101000-----110-----0000111 variables: - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vl4re64.v.yaml b/arch/inst/V/vl4re64.v.yaml index 8db40b0c62..e00f0a8755 100644 --- a/arch/inst/V/vl4re64.v.yaml +++ b/arch/inst/V/vl4re64.v.yaml @@ -5,16 +5,16 @@ kind: instruction name: vl4re64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: xs1, vd encoding: match: 011000101000-----111-----0000111 variables: - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vl4re8.v.yaml b/arch/inst/V/vl4re8.v.yaml index 0361ac50af..78dc9fb41f 100644 --- a/arch/inst/V/vl4re8.v.yaml +++ b/arch/inst/V/vl4re8.v.yaml @@ -5,16 +5,16 @@ kind: instruction name: vl4re8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: xs1, vd encoding: match: 011000101000-----000-----0000111 variables: - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vl8re16.v.yaml b/arch/inst/V/vl8re16.v.yaml index 26214f47d1..aefaacb6aa 100644 --- a/arch/inst/V/vl8re16.v.yaml +++ b/arch/inst/V/vl8re16.v.yaml @@ -5,16 +5,16 @@ kind: instruction name: vl8re16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: xs1, vd encoding: match: 111000101000-----101-----0000111 variables: - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vl8re32.v.yaml b/arch/inst/V/vl8re32.v.yaml index b55e4987ff..f3add1efee 100644 --- a/arch/inst/V/vl8re32.v.yaml +++ b/arch/inst/V/vl8re32.v.yaml @@ -5,16 +5,16 @@ kind: instruction name: vl8re32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: xs1, vd encoding: match: 111000101000-----110-----0000111 variables: - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vl8re64.v.yaml b/arch/inst/V/vl8re64.v.yaml index 1d992927d3..283754478b 100644 --- a/arch/inst/V/vl8re64.v.yaml +++ b/arch/inst/V/vl8re64.v.yaml @@ -5,16 +5,16 @@ kind: instruction name: vl8re64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: xs1, vd encoding: match: 111000101000-----111-----0000111 variables: - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vl8re8.v.yaml b/arch/inst/V/vl8re8.v.yaml index e871bb99d9..fce3b23fb6 100644 --- a/arch/inst/V/vl8re8.v.yaml +++ b/arch/inst/V/vl8re8.v.yaml @@ -5,16 +5,16 @@ kind: instruction name: vl8re8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: xs1, vd encoding: match: 111000101000-----000-----0000111 variables: - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vle16.v.yaml b/arch/inst/V/vle16.v.yaml index b936f52ac0..40884f375d 100644 --- a/arch/inst/V/vle16.v.yaml +++ b/arch/inst/V/vle16.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vle16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 000000-00000-----101-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let load_width_bytes = vlewidth_bytesnumber(width); diff --git a/arch/inst/V/vle16ff.v.yaml b/arch/inst/V/vle16ff.v.yaml index 50b8812278..ec6f9aa68e 100644 --- a/arch/inst/V/vle16ff.v.yaml +++ b/arch/inst/V/vle16ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vle16ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 000000-10000-----101-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let load_width_bytes = vlewidth_bytesnumber(width); diff --git a/arch/inst/V/vle32.v.yaml b/arch/inst/V/vle32.v.yaml index 4925426055..15e973e691 100644 --- a/arch/inst/V/vle32.v.yaml +++ b/arch/inst/V/vle32.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vle32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 000000-00000-----110-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let load_width_bytes = vlewidth_bytesnumber(width); diff --git a/arch/inst/V/vle32ff.v.yaml b/arch/inst/V/vle32ff.v.yaml index 4de0bad438..1203249193 100644 --- a/arch/inst/V/vle32ff.v.yaml +++ b/arch/inst/V/vle32ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vle32ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 000000-10000-----110-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let load_width_bytes = vlewidth_bytesnumber(width); diff --git a/arch/inst/V/vle64.v.yaml b/arch/inst/V/vle64.v.yaml index 75a9f9bb02..aff28632f0 100644 --- a/arch/inst/V/vle64.v.yaml +++ b/arch/inst/V/vle64.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vle64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 000000-00000-----111-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let load_width_bytes = vlewidth_bytesnumber(width); diff --git a/arch/inst/V/vle64ff.v.yaml b/arch/inst/V/vle64ff.v.yaml index d9efeff029..421d1bda8f 100644 --- a/arch/inst/V/vle64ff.v.yaml +++ b/arch/inst/V/vle64ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vle64ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 000000-10000-----111-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let load_width_bytes = vlewidth_bytesnumber(width); diff --git a/arch/inst/V/vle8.v.yaml b/arch/inst/V/vle8.v.yaml index a36a00ac14..68493ddfdb 100644 --- a/arch/inst/V/vle8.v.yaml +++ b/arch/inst/V/vle8.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vle8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 000000-00000-----000-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let load_width_bytes = vlewidth_bytesnumber(width); diff --git a/arch/inst/V/vle8ff.v.yaml b/arch/inst/V/vle8ff.v.yaml index e53ade80db..19bfd6824a 100644 --- a/arch/inst/V/vle8ff.v.yaml +++ b/arch/inst/V/vle8ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vle8ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 000000-10000-----000-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let load_width_bytes = vlewidth_bytesnumber(width); diff --git a/arch/inst/V/vlm.v.yaml b/arch/inst/V/vlm.v.yaml index e7b17a7088..bbcb34dff4 100644 --- a/arch/inst/V/vlm.v.yaml +++ b/arch/inst/V/vlm.v.yaml @@ -5,16 +5,16 @@ kind: instruction name: vlm.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: xs1, vd encoding: match: 000000101011-----000-----0000111 variables: - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -23,9 +23,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let EEW = 8; diff --git a/arch/inst/V/vloxei16.v.yaml b/arch/inst/V/vloxei16.v.yaml index 333150bfcb..fbe93e5355 100644 --- a/arch/inst/V/vloxei16.v.yaml +++ b/arch/inst/V/vloxei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 000011-----------101-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let EEW_index_pow = vlewidth_pow(width); diff --git a/arch/inst/V/vloxei32.v.yaml b/arch/inst/V/vloxei32.v.yaml index 42334c5ef7..0bb146ad4d 100644 --- a/arch/inst/V/vloxei32.v.yaml +++ b/arch/inst/V/vloxei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 000011-----------110-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let EEW_index_pow = vlewidth_pow(width); diff --git a/arch/inst/V/vloxei64.v.yaml b/arch/inst/V/vloxei64.v.yaml index cc45f490e5..0befceaffb 100644 --- a/arch/inst/V/vloxei64.v.yaml +++ b/arch/inst/V/vloxei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 000011-----------111-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let EEW_index_pow = vlewidth_pow(width); diff --git a/arch/inst/V/vloxei8.v.yaml b/arch/inst/V/vloxei8.v.yaml index 3db6d4ebb3..5a3ff0d66e 100644 --- a/arch/inst/V/vloxei8.v.yaml +++ b/arch/inst/V/vloxei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 000011-----------000-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let EEW_index_pow = vlewidth_pow(width); diff --git a/arch/inst/V/vloxseg2ei16.v.yaml b/arch/inst/V/vloxseg2ei16.v.yaml index 8c0275846d..8f50632ea4 100644 --- a/arch/inst/V/vloxseg2ei16.v.yaml +++ b/arch/inst/V/vloxseg2ei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxseg2ei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 001011-----------101-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vloxseg2ei32.v.yaml b/arch/inst/V/vloxseg2ei32.v.yaml index 8cf8eed091..88ffd0171a 100644 --- a/arch/inst/V/vloxseg2ei32.v.yaml +++ b/arch/inst/V/vloxseg2ei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxseg2ei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 001011-----------110-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vloxseg2ei64.v.yaml b/arch/inst/V/vloxseg2ei64.v.yaml index b441647b1a..fdf116edb6 100644 --- a/arch/inst/V/vloxseg2ei64.v.yaml +++ b/arch/inst/V/vloxseg2ei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxseg2ei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 001011-----------111-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vloxseg2ei8.v.yaml b/arch/inst/V/vloxseg2ei8.v.yaml index 507fe4f0ac..19fe4e96d1 100644 --- a/arch/inst/V/vloxseg2ei8.v.yaml +++ b/arch/inst/V/vloxseg2ei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxseg2ei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 001011-----------000-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vloxseg3ei16.v.yaml b/arch/inst/V/vloxseg3ei16.v.yaml index 674b1aa849..f1ae7c255d 100644 --- a/arch/inst/V/vloxseg3ei16.v.yaml +++ b/arch/inst/V/vloxseg3ei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxseg3ei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 010011-----------101-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vloxseg3ei32.v.yaml b/arch/inst/V/vloxseg3ei32.v.yaml index a2a61f851a..628db505cd 100644 --- a/arch/inst/V/vloxseg3ei32.v.yaml +++ b/arch/inst/V/vloxseg3ei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxseg3ei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 010011-----------110-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vloxseg3ei64.v.yaml b/arch/inst/V/vloxseg3ei64.v.yaml index 61cc36c827..1d1237a17d 100644 --- a/arch/inst/V/vloxseg3ei64.v.yaml +++ b/arch/inst/V/vloxseg3ei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxseg3ei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 010011-----------111-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vloxseg3ei8.v.yaml b/arch/inst/V/vloxseg3ei8.v.yaml index cd4398986c..d89edd83c6 100644 --- a/arch/inst/V/vloxseg3ei8.v.yaml +++ b/arch/inst/V/vloxseg3ei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxseg3ei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 010011-----------000-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vloxseg4ei16.v.yaml b/arch/inst/V/vloxseg4ei16.v.yaml index a626500873..26983baed8 100644 --- a/arch/inst/V/vloxseg4ei16.v.yaml +++ b/arch/inst/V/vloxseg4ei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxseg4ei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 011011-----------101-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vloxseg4ei32.v.yaml b/arch/inst/V/vloxseg4ei32.v.yaml index d97c7fb958..796d50b069 100644 --- a/arch/inst/V/vloxseg4ei32.v.yaml +++ b/arch/inst/V/vloxseg4ei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxseg4ei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 011011-----------110-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vloxseg4ei64.v.yaml b/arch/inst/V/vloxseg4ei64.v.yaml index fcfb19b824..95b41eca7a 100644 --- a/arch/inst/V/vloxseg4ei64.v.yaml +++ b/arch/inst/V/vloxseg4ei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxseg4ei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 011011-----------111-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vloxseg4ei8.v.yaml b/arch/inst/V/vloxseg4ei8.v.yaml index d5c0d50545..24dfe586ee 100644 --- a/arch/inst/V/vloxseg4ei8.v.yaml +++ b/arch/inst/V/vloxseg4ei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxseg4ei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 011011-----------000-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vloxseg5ei16.v.yaml b/arch/inst/V/vloxseg5ei16.v.yaml index 3512fb8923..593634d18b 100644 --- a/arch/inst/V/vloxseg5ei16.v.yaml +++ b/arch/inst/V/vloxseg5ei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxseg5ei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 100011-----------101-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vloxseg5ei32.v.yaml b/arch/inst/V/vloxseg5ei32.v.yaml index 3068b99f04..9aae903bcf 100644 --- a/arch/inst/V/vloxseg5ei32.v.yaml +++ b/arch/inst/V/vloxseg5ei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxseg5ei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 100011-----------110-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vloxseg5ei64.v.yaml b/arch/inst/V/vloxseg5ei64.v.yaml index 4a1e73e519..ec8a28854b 100644 --- a/arch/inst/V/vloxseg5ei64.v.yaml +++ b/arch/inst/V/vloxseg5ei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxseg5ei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 100011-----------111-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vloxseg5ei8.v.yaml b/arch/inst/V/vloxseg5ei8.v.yaml index df2afc27a8..7234de35cb 100644 --- a/arch/inst/V/vloxseg5ei8.v.yaml +++ b/arch/inst/V/vloxseg5ei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxseg5ei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 100011-----------000-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vloxseg6ei16.v.yaml b/arch/inst/V/vloxseg6ei16.v.yaml index f7b0fbdcc0..d44349ade9 100644 --- a/arch/inst/V/vloxseg6ei16.v.yaml +++ b/arch/inst/V/vloxseg6ei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxseg6ei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 101011-----------101-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vloxseg6ei32.v.yaml b/arch/inst/V/vloxseg6ei32.v.yaml index a42e7f335e..ae574b966a 100644 --- a/arch/inst/V/vloxseg6ei32.v.yaml +++ b/arch/inst/V/vloxseg6ei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxseg6ei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 101011-----------110-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vloxseg6ei64.v.yaml b/arch/inst/V/vloxseg6ei64.v.yaml index 24c9a89a15..e9f8c1afb2 100644 --- a/arch/inst/V/vloxseg6ei64.v.yaml +++ b/arch/inst/V/vloxseg6ei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxseg6ei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 101011-----------111-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vloxseg6ei8.v.yaml b/arch/inst/V/vloxseg6ei8.v.yaml index af5bc5faa0..8aa0692e58 100644 --- a/arch/inst/V/vloxseg6ei8.v.yaml +++ b/arch/inst/V/vloxseg6ei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxseg6ei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 101011-----------000-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vloxseg7ei16.v.yaml b/arch/inst/V/vloxseg7ei16.v.yaml index 9f113daec8..a2cf87d8ec 100644 --- a/arch/inst/V/vloxseg7ei16.v.yaml +++ b/arch/inst/V/vloxseg7ei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxseg7ei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 110011-----------101-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vloxseg7ei32.v.yaml b/arch/inst/V/vloxseg7ei32.v.yaml index dc92014b14..cdcd71aca5 100644 --- a/arch/inst/V/vloxseg7ei32.v.yaml +++ b/arch/inst/V/vloxseg7ei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxseg7ei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 110011-----------110-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vloxseg7ei64.v.yaml b/arch/inst/V/vloxseg7ei64.v.yaml index 0efc0ce4e0..0c65b7526b 100644 --- a/arch/inst/V/vloxseg7ei64.v.yaml +++ b/arch/inst/V/vloxseg7ei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxseg7ei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 110011-----------111-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vloxseg7ei8.v.yaml b/arch/inst/V/vloxseg7ei8.v.yaml index a87175475d..7fde4e3067 100644 --- a/arch/inst/V/vloxseg7ei8.v.yaml +++ b/arch/inst/V/vloxseg7ei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxseg7ei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 110011-----------000-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vloxseg8ei16.v.yaml b/arch/inst/V/vloxseg8ei16.v.yaml index 820eb7d13c..e2fbc18c93 100644 --- a/arch/inst/V/vloxseg8ei16.v.yaml +++ b/arch/inst/V/vloxseg8ei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxseg8ei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 111011-----------101-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vloxseg8ei32.v.yaml b/arch/inst/V/vloxseg8ei32.v.yaml index 9d733a3e2e..d8ecb7ed47 100644 --- a/arch/inst/V/vloxseg8ei32.v.yaml +++ b/arch/inst/V/vloxseg8ei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxseg8ei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 111011-----------110-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vloxseg8ei64.v.yaml b/arch/inst/V/vloxseg8ei64.v.yaml index ff37314bff..94dd8167d9 100644 --- a/arch/inst/V/vloxseg8ei64.v.yaml +++ b/arch/inst/V/vloxseg8ei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxseg8ei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 111011-----------111-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vloxseg8ei8.v.yaml b/arch/inst/V/vloxseg8ei8.v.yaml index 689a553540..3ceb6da14f 100644 --- a/arch/inst/V/vloxseg8ei8.v.yaml +++ b/arch/inst/V/vloxseg8ei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vloxseg8ei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 111011-----------000-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlse16.v.yaml b/arch/inst/V/vlse16.v.yaml index f82b342534..3741a01bd3 100644 --- a/arch/inst/V/vlse16.v.yaml +++ b/arch/inst/V/vlse16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlse16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 000010-----------101-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let load_width_bytes = vlewidth_bytesnumber(width); diff --git a/arch/inst/V/vlse32.v.yaml b/arch/inst/V/vlse32.v.yaml index 6ba2a8abe7..8fee226d4b 100644 --- a/arch/inst/V/vlse32.v.yaml +++ b/arch/inst/V/vlse32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlse32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 000010-----------110-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let load_width_bytes = vlewidth_bytesnumber(width); diff --git a/arch/inst/V/vlse64.v.yaml b/arch/inst/V/vlse64.v.yaml index 76e1be0642..bfb8bf3b49 100644 --- a/arch/inst/V/vlse64.v.yaml +++ b/arch/inst/V/vlse64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlse64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 000010-----------111-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let load_width_bytes = vlewidth_bytesnumber(width); diff --git a/arch/inst/V/vlse8.v.yaml b/arch/inst/V/vlse8.v.yaml index ad57806cf2..14de61233a 100644 --- a/arch/inst/V/vlse8.v.yaml +++ b/arch/inst/V/vlse8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlse8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 000010-----------000-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let load_width_bytes = vlewidth_bytesnumber(width); diff --git a/arch/inst/V/vlseg2e16.v.yaml b/arch/inst/V/vlseg2e16.v.yaml index fb571d744d..5cb3116252 100644 --- a/arch/inst/V/vlseg2e16.v.yaml +++ b/arch/inst/V/vlseg2e16.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg2e16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 001000-00000-----101-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg2e16ff.v.yaml b/arch/inst/V/vlseg2e16ff.v.yaml index 0bcfe9e14a..fffc3cbeb9 100644 --- a/arch/inst/V/vlseg2e16ff.v.yaml +++ b/arch/inst/V/vlseg2e16ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg2e16ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 001000-10000-----101-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg2e32.v.yaml b/arch/inst/V/vlseg2e32.v.yaml index d81a1047ed..3f8a2133c6 100644 --- a/arch/inst/V/vlseg2e32.v.yaml +++ b/arch/inst/V/vlseg2e32.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg2e32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 001000-00000-----110-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg2e32ff.v.yaml b/arch/inst/V/vlseg2e32ff.v.yaml index d1a6348b5b..614aa1d37c 100644 --- a/arch/inst/V/vlseg2e32ff.v.yaml +++ b/arch/inst/V/vlseg2e32ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg2e32ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 001000-10000-----110-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg2e64.v.yaml b/arch/inst/V/vlseg2e64.v.yaml index 2c93a94423..9abcc5b7a7 100644 --- a/arch/inst/V/vlseg2e64.v.yaml +++ b/arch/inst/V/vlseg2e64.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg2e64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 001000-00000-----111-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg2e64ff.v.yaml b/arch/inst/V/vlseg2e64ff.v.yaml index ca5ad1b9de..01cee8e7af 100644 --- a/arch/inst/V/vlseg2e64ff.v.yaml +++ b/arch/inst/V/vlseg2e64ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg2e64ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 001000-10000-----111-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg2e8.v.yaml b/arch/inst/V/vlseg2e8.v.yaml index 9d80b185b3..ee7d0ee600 100644 --- a/arch/inst/V/vlseg2e8.v.yaml +++ b/arch/inst/V/vlseg2e8.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg2e8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 001000-00000-----000-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg2e8ff.v.yaml b/arch/inst/V/vlseg2e8ff.v.yaml index 427db8eae2..954bbc8dbe 100644 --- a/arch/inst/V/vlseg2e8ff.v.yaml +++ b/arch/inst/V/vlseg2e8ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg2e8ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 001000-10000-----000-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg3e16.v.yaml b/arch/inst/V/vlseg3e16.v.yaml index f5d7e55456..898e2e94e3 100644 --- a/arch/inst/V/vlseg3e16.v.yaml +++ b/arch/inst/V/vlseg3e16.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg3e16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 010000-00000-----101-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg3e16ff.v.yaml b/arch/inst/V/vlseg3e16ff.v.yaml index 76d8d97c4e..b1a040ef09 100644 --- a/arch/inst/V/vlseg3e16ff.v.yaml +++ b/arch/inst/V/vlseg3e16ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg3e16ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 010000-10000-----101-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg3e32.v.yaml b/arch/inst/V/vlseg3e32.v.yaml index d982464fe0..16c93f5be9 100644 --- a/arch/inst/V/vlseg3e32.v.yaml +++ b/arch/inst/V/vlseg3e32.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg3e32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 010000-00000-----110-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg3e32ff.v.yaml b/arch/inst/V/vlseg3e32ff.v.yaml index 1634338f12..419d3d0288 100644 --- a/arch/inst/V/vlseg3e32ff.v.yaml +++ b/arch/inst/V/vlseg3e32ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg3e32ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 010000-10000-----110-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg3e64.v.yaml b/arch/inst/V/vlseg3e64.v.yaml index 4de2fb503d..9e2990a108 100644 --- a/arch/inst/V/vlseg3e64.v.yaml +++ b/arch/inst/V/vlseg3e64.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg3e64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 010000-00000-----111-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg3e64ff.v.yaml b/arch/inst/V/vlseg3e64ff.v.yaml index 0f73b786a8..e6c162a720 100644 --- a/arch/inst/V/vlseg3e64ff.v.yaml +++ b/arch/inst/V/vlseg3e64ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg3e64ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 010000-10000-----111-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg3e8.v.yaml b/arch/inst/V/vlseg3e8.v.yaml index f858ec9c74..d80c4c04e9 100644 --- a/arch/inst/V/vlseg3e8.v.yaml +++ b/arch/inst/V/vlseg3e8.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg3e8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 010000-00000-----000-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg3e8ff.v.yaml b/arch/inst/V/vlseg3e8ff.v.yaml index aeed7424b0..ca25deb265 100644 --- a/arch/inst/V/vlseg3e8ff.v.yaml +++ b/arch/inst/V/vlseg3e8ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg3e8ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 010000-10000-----000-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg4e16.v.yaml b/arch/inst/V/vlseg4e16.v.yaml index e017e09839..5434d4672a 100644 --- a/arch/inst/V/vlseg4e16.v.yaml +++ b/arch/inst/V/vlseg4e16.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg4e16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 011000-00000-----101-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg4e16ff.v.yaml b/arch/inst/V/vlseg4e16ff.v.yaml index 3144cc7771..7b63f6c81d 100644 --- a/arch/inst/V/vlseg4e16ff.v.yaml +++ b/arch/inst/V/vlseg4e16ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg4e16ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 011000-10000-----101-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg4e32.v.yaml b/arch/inst/V/vlseg4e32.v.yaml index eaf5e45e94..8a4c98f823 100644 --- a/arch/inst/V/vlseg4e32.v.yaml +++ b/arch/inst/V/vlseg4e32.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg4e32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 011000-00000-----110-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg4e32ff.v.yaml b/arch/inst/V/vlseg4e32ff.v.yaml index fc92eeb66c..edce5384fc 100644 --- a/arch/inst/V/vlseg4e32ff.v.yaml +++ b/arch/inst/V/vlseg4e32ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg4e32ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 011000-10000-----110-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg4e64.v.yaml b/arch/inst/V/vlseg4e64.v.yaml index e7630b5e65..95d861e702 100644 --- a/arch/inst/V/vlseg4e64.v.yaml +++ b/arch/inst/V/vlseg4e64.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg4e64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 011000-00000-----111-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg4e64ff.v.yaml b/arch/inst/V/vlseg4e64ff.v.yaml index b64e45fa2a..574e0b9341 100644 --- a/arch/inst/V/vlseg4e64ff.v.yaml +++ b/arch/inst/V/vlseg4e64ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg4e64ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 011000-10000-----111-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg4e8.v.yaml b/arch/inst/V/vlseg4e8.v.yaml index 471bcc07d0..72e625c5ff 100644 --- a/arch/inst/V/vlseg4e8.v.yaml +++ b/arch/inst/V/vlseg4e8.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg4e8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 011000-00000-----000-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg4e8ff.v.yaml b/arch/inst/V/vlseg4e8ff.v.yaml index 67165fa3de..bb6104fde3 100644 --- a/arch/inst/V/vlseg4e8ff.v.yaml +++ b/arch/inst/V/vlseg4e8ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg4e8ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 011000-10000-----000-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg5e16.v.yaml b/arch/inst/V/vlseg5e16.v.yaml index 9ba626b4a0..ac5fad6ccd 100644 --- a/arch/inst/V/vlseg5e16.v.yaml +++ b/arch/inst/V/vlseg5e16.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg5e16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 100000-00000-----101-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg5e16ff.v.yaml b/arch/inst/V/vlseg5e16ff.v.yaml index 2f1eaa609e..aea4907b10 100644 --- a/arch/inst/V/vlseg5e16ff.v.yaml +++ b/arch/inst/V/vlseg5e16ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg5e16ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 100000-10000-----101-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg5e32.v.yaml b/arch/inst/V/vlseg5e32.v.yaml index eb45144de7..df90200f68 100644 --- a/arch/inst/V/vlseg5e32.v.yaml +++ b/arch/inst/V/vlseg5e32.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg5e32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 100000-00000-----110-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg5e32ff.v.yaml b/arch/inst/V/vlseg5e32ff.v.yaml index e0cc52c874..8923077d85 100644 --- a/arch/inst/V/vlseg5e32ff.v.yaml +++ b/arch/inst/V/vlseg5e32ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg5e32ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 100000-10000-----110-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg5e64.v.yaml b/arch/inst/V/vlseg5e64.v.yaml index e989cc4a4e..b9295db7db 100644 --- a/arch/inst/V/vlseg5e64.v.yaml +++ b/arch/inst/V/vlseg5e64.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg5e64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 100000-00000-----111-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg5e64ff.v.yaml b/arch/inst/V/vlseg5e64ff.v.yaml index 06440b7923..634ab86b7d 100644 --- a/arch/inst/V/vlseg5e64ff.v.yaml +++ b/arch/inst/V/vlseg5e64ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg5e64ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 100000-10000-----111-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg5e8.v.yaml b/arch/inst/V/vlseg5e8.v.yaml index e853590c04..60bb7affaf 100644 --- a/arch/inst/V/vlseg5e8.v.yaml +++ b/arch/inst/V/vlseg5e8.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg5e8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 100000-00000-----000-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg5e8ff.v.yaml b/arch/inst/V/vlseg5e8ff.v.yaml index e77ecaefe5..42f28df027 100644 --- a/arch/inst/V/vlseg5e8ff.v.yaml +++ b/arch/inst/V/vlseg5e8ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg5e8ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 100000-10000-----000-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg6e16.v.yaml b/arch/inst/V/vlseg6e16.v.yaml index 8f546c7db2..5aa54afe33 100644 --- a/arch/inst/V/vlseg6e16.v.yaml +++ b/arch/inst/V/vlseg6e16.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg6e16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 101000-00000-----101-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg6e16ff.v.yaml b/arch/inst/V/vlseg6e16ff.v.yaml index 352ed94898..60eb36b58c 100644 --- a/arch/inst/V/vlseg6e16ff.v.yaml +++ b/arch/inst/V/vlseg6e16ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg6e16ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 101000-10000-----101-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg6e32.v.yaml b/arch/inst/V/vlseg6e32.v.yaml index 3ec853fd6c..6478c2ea2f 100644 --- a/arch/inst/V/vlseg6e32.v.yaml +++ b/arch/inst/V/vlseg6e32.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg6e32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 101000-00000-----110-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg6e32ff.v.yaml b/arch/inst/V/vlseg6e32ff.v.yaml index e6ee665530..55f0239ec8 100644 --- a/arch/inst/V/vlseg6e32ff.v.yaml +++ b/arch/inst/V/vlseg6e32ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg6e32ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 101000-10000-----110-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg6e64.v.yaml b/arch/inst/V/vlseg6e64.v.yaml index d281c07ea9..c630d640b6 100644 --- a/arch/inst/V/vlseg6e64.v.yaml +++ b/arch/inst/V/vlseg6e64.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg6e64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 101000-00000-----111-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg6e64ff.v.yaml b/arch/inst/V/vlseg6e64ff.v.yaml index 64bccae0b8..7f2d2a1b16 100644 --- a/arch/inst/V/vlseg6e64ff.v.yaml +++ b/arch/inst/V/vlseg6e64ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg6e64ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 101000-10000-----111-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg6e8.v.yaml b/arch/inst/V/vlseg6e8.v.yaml index 6205f7654f..fc071cf6d9 100644 --- a/arch/inst/V/vlseg6e8.v.yaml +++ b/arch/inst/V/vlseg6e8.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg6e8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 101000-00000-----000-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg6e8ff.v.yaml b/arch/inst/V/vlseg6e8ff.v.yaml index 96772b71f8..0d1003c670 100644 --- a/arch/inst/V/vlseg6e8ff.v.yaml +++ b/arch/inst/V/vlseg6e8ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg6e8ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 101000-10000-----000-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg7e16.v.yaml b/arch/inst/V/vlseg7e16.v.yaml index 80608625b1..059b5cb40f 100644 --- a/arch/inst/V/vlseg7e16.v.yaml +++ b/arch/inst/V/vlseg7e16.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg7e16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 110000-00000-----101-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg7e16ff.v.yaml b/arch/inst/V/vlseg7e16ff.v.yaml index ad5a0c8e7b..8a494b3a8f 100644 --- a/arch/inst/V/vlseg7e16ff.v.yaml +++ b/arch/inst/V/vlseg7e16ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg7e16ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 110000-10000-----101-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg7e32.v.yaml b/arch/inst/V/vlseg7e32.v.yaml index c03e22bd00..46144daa25 100644 --- a/arch/inst/V/vlseg7e32.v.yaml +++ b/arch/inst/V/vlseg7e32.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg7e32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 110000-00000-----110-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg7e32ff.v.yaml b/arch/inst/V/vlseg7e32ff.v.yaml index 5022199140..f3b5926baa 100644 --- a/arch/inst/V/vlseg7e32ff.v.yaml +++ b/arch/inst/V/vlseg7e32ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg7e32ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 110000-10000-----110-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg7e64.v.yaml b/arch/inst/V/vlseg7e64.v.yaml index 9198968c59..2bc956014d 100644 --- a/arch/inst/V/vlseg7e64.v.yaml +++ b/arch/inst/V/vlseg7e64.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg7e64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 110000-00000-----111-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg7e64ff.v.yaml b/arch/inst/V/vlseg7e64ff.v.yaml index f19ae2b3d7..55d1919809 100644 --- a/arch/inst/V/vlseg7e64ff.v.yaml +++ b/arch/inst/V/vlseg7e64ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg7e64ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 110000-10000-----111-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg7e8.v.yaml b/arch/inst/V/vlseg7e8.v.yaml index 8d5b005220..b9f55a454a 100644 --- a/arch/inst/V/vlseg7e8.v.yaml +++ b/arch/inst/V/vlseg7e8.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg7e8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 110000-00000-----000-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg7e8ff.v.yaml b/arch/inst/V/vlseg7e8ff.v.yaml index 6b70df5dde..f27a57aecb 100644 --- a/arch/inst/V/vlseg7e8ff.v.yaml +++ b/arch/inst/V/vlseg7e8ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg7e8ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 110000-10000-----000-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg8e16.v.yaml b/arch/inst/V/vlseg8e16.v.yaml index 123b19b579..abb6f90aee 100644 --- a/arch/inst/V/vlseg8e16.v.yaml +++ b/arch/inst/V/vlseg8e16.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg8e16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 111000-00000-----101-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg8e16ff.v.yaml b/arch/inst/V/vlseg8e16ff.v.yaml index 638b68a82e..0fd2a96a7a 100644 --- a/arch/inst/V/vlseg8e16ff.v.yaml +++ b/arch/inst/V/vlseg8e16ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg8e16ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 111000-10000-----101-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg8e32.v.yaml b/arch/inst/V/vlseg8e32.v.yaml index 39b89cdad8..a0abea2d5d 100644 --- a/arch/inst/V/vlseg8e32.v.yaml +++ b/arch/inst/V/vlseg8e32.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg8e32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 111000-00000-----110-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg8e32ff.v.yaml b/arch/inst/V/vlseg8e32ff.v.yaml index a2ab52d771..2d4f2aa7f9 100644 --- a/arch/inst/V/vlseg8e32ff.v.yaml +++ b/arch/inst/V/vlseg8e32ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg8e32ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 111000-10000-----110-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg8e64.v.yaml b/arch/inst/V/vlseg8e64.v.yaml index f7952833be..cd01f7e35a 100644 --- a/arch/inst/V/vlseg8e64.v.yaml +++ b/arch/inst/V/vlseg8e64.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg8e64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 111000-00000-----111-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg8e64ff.v.yaml b/arch/inst/V/vlseg8e64ff.v.yaml index 28c0e9a735..73fe0b9d68 100644 --- a/arch/inst/V/vlseg8e64ff.v.yaml +++ b/arch/inst/V/vlseg8e64ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg8e64ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 111000-10000-----111-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg8e8.v.yaml b/arch/inst/V/vlseg8e8.v.yaml index 7b1c864aeb..1e73f37341 100644 --- a/arch/inst/V/vlseg8e8.v.yaml +++ b/arch/inst/V/vlseg8e8.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg8e8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 111000-00000-----000-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlseg8e8ff.v.yaml b/arch/inst/V/vlseg8e8ff.v.yaml index 503786f11d..c3c5feebde 100644 --- a/arch/inst/V/vlseg8e8ff.v.yaml +++ b/arch/inst/V/vlseg8e8ff.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vlseg8e8ff.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vd encoding: match: 111000-10000-----000-----0000111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlsseg2e16.v.yaml b/arch/inst/V/vlsseg2e16.v.yaml index a8700b96d2..b7d6b5a038 100644 --- a/arch/inst/V/vlsseg2e16.v.yaml +++ b/arch/inst/V/vlsseg2e16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlsseg2e16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 001010-----------101-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlsseg2e32.v.yaml b/arch/inst/V/vlsseg2e32.v.yaml index 06df364b82..80b1db91ff 100644 --- a/arch/inst/V/vlsseg2e32.v.yaml +++ b/arch/inst/V/vlsseg2e32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlsseg2e32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 001010-----------110-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlsseg2e64.v.yaml b/arch/inst/V/vlsseg2e64.v.yaml index ad42e35e3b..e035d8b3de 100644 --- a/arch/inst/V/vlsseg2e64.v.yaml +++ b/arch/inst/V/vlsseg2e64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlsseg2e64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 001010-----------111-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlsseg2e8.v.yaml b/arch/inst/V/vlsseg2e8.v.yaml index f5d11dfacf..5905d81de6 100644 --- a/arch/inst/V/vlsseg2e8.v.yaml +++ b/arch/inst/V/vlsseg2e8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlsseg2e8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 001010-----------000-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlsseg3e16.v.yaml b/arch/inst/V/vlsseg3e16.v.yaml index e56df9143d..a2d5fbef96 100644 --- a/arch/inst/V/vlsseg3e16.v.yaml +++ b/arch/inst/V/vlsseg3e16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlsseg3e16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 010010-----------101-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlsseg3e32.v.yaml b/arch/inst/V/vlsseg3e32.v.yaml index 836a5ccccd..5fca1695d1 100644 --- a/arch/inst/V/vlsseg3e32.v.yaml +++ b/arch/inst/V/vlsseg3e32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlsseg3e32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 010010-----------110-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlsseg3e64.v.yaml b/arch/inst/V/vlsseg3e64.v.yaml index 0fbc2ece18..00ca5c5daa 100644 --- a/arch/inst/V/vlsseg3e64.v.yaml +++ b/arch/inst/V/vlsseg3e64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlsseg3e64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 010010-----------111-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlsseg3e8.v.yaml b/arch/inst/V/vlsseg3e8.v.yaml index d9f2702970..ede6a526bd 100644 --- a/arch/inst/V/vlsseg3e8.v.yaml +++ b/arch/inst/V/vlsseg3e8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlsseg3e8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 010010-----------000-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlsseg4e16.v.yaml b/arch/inst/V/vlsseg4e16.v.yaml index 2946801a27..65a461e235 100644 --- a/arch/inst/V/vlsseg4e16.v.yaml +++ b/arch/inst/V/vlsseg4e16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlsseg4e16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 011010-----------101-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlsseg4e32.v.yaml b/arch/inst/V/vlsseg4e32.v.yaml index f9e9adb8e3..44d11d6620 100644 --- a/arch/inst/V/vlsseg4e32.v.yaml +++ b/arch/inst/V/vlsseg4e32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlsseg4e32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 011010-----------110-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlsseg4e64.v.yaml b/arch/inst/V/vlsseg4e64.v.yaml index 7091310b91..bc10dc6b23 100644 --- a/arch/inst/V/vlsseg4e64.v.yaml +++ b/arch/inst/V/vlsseg4e64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlsseg4e64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 011010-----------111-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlsseg4e8.v.yaml b/arch/inst/V/vlsseg4e8.v.yaml index e7755782f0..e76dfb062c 100644 --- a/arch/inst/V/vlsseg4e8.v.yaml +++ b/arch/inst/V/vlsseg4e8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlsseg4e8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 011010-----------000-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlsseg5e16.v.yaml b/arch/inst/V/vlsseg5e16.v.yaml index d96600999d..3ba3917d91 100644 --- a/arch/inst/V/vlsseg5e16.v.yaml +++ b/arch/inst/V/vlsseg5e16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlsseg5e16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 100010-----------101-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlsseg5e32.v.yaml b/arch/inst/V/vlsseg5e32.v.yaml index 36dcfda260..a0a1700edd 100644 --- a/arch/inst/V/vlsseg5e32.v.yaml +++ b/arch/inst/V/vlsseg5e32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlsseg5e32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 100010-----------110-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlsseg5e64.v.yaml b/arch/inst/V/vlsseg5e64.v.yaml index 43ef731d9c..85a4db7017 100644 --- a/arch/inst/V/vlsseg5e64.v.yaml +++ b/arch/inst/V/vlsseg5e64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlsseg5e64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 100010-----------111-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlsseg5e8.v.yaml b/arch/inst/V/vlsseg5e8.v.yaml index 512237dfc5..958b4ca06c 100644 --- a/arch/inst/V/vlsseg5e8.v.yaml +++ b/arch/inst/V/vlsseg5e8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlsseg5e8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 100010-----------000-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlsseg6e16.v.yaml b/arch/inst/V/vlsseg6e16.v.yaml index fda481b602..657f533878 100644 --- a/arch/inst/V/vlsseg6e16.v.yaml +++ b/arch/inst/V/vlsseg6e16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlsseg6e16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 101010-----------101-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlsseg6e32.v.yaml b/arch/inst/V/vlsseg6e32.v.yaml index 3e4927eb41..c1e5f2ce1c 100644 --- a/arch/inst/V/vlsseg6e32.v.yaml +++ b/arch/inst/V/vlsseg6e32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlsseg6e32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 101010-----------110-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlsseg6e64.v.yaml b/arch/inst/V/vlsseg6e64.v.yaml index 379f481bb4..7fc49445d4 100644 --- a/arch/inst/V/vlsseg6e64.v.yaml +++ b/arch/inst/V/vlsseg6e64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlsseg6e64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 101010-----------111-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlsseg6e8.v.yaml b/arch/inst/V/vlsseg6e8.v.yaml index 16080240a8..b017bc5bca 100644 --- a/arch/inst/V/vlsseg6e8.v.yaml +++ b/arch/inst/V/vlsseg6e8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlsseg6e8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 101010-----------000-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlsseg7e16.v.yaml b/arch/inst/V/vlsseg7e16.v.yaml index 464b1013d0..77d7921dee 100644 --- a/arch/inst/V/vlsseg7e16.v.yaml +++ b/arch/inst/V/vlsseg7e16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlsseg7e16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 110010-----------101-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlsseg7e32.v.yaml b/arch/inst/V/vlsseg7e32.v.yaml index 990fcab164..a186fb6906 100644 --- a/arch/inst/V/vlsseg7e32.v.yaml +++ b/arch/inst/V/vlsseg7e32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlsseg7e32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 110010-----------110-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlsseg7e64.v.yaml b/arch/inst/V/vlsseg7e64.v.yaml index 7dc4459c30..3fe69afff7 100644 --- a/arch/inst/V/vlsseg7e64.v.yaml +++ b/arch/inst/V/vlsseg7e64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlsseg7e64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 110010-----------111-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlsseg7e8.v.yaml b/arch/inst/V/vlsseg7e8.v.yaml index de905eaf9c..f78d539f45 100644 --- a/arch/inst/V/vlsseg7e8.v.yaml +++ b/arch/inst/V/vlsseg7e8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlsseg7e8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 110010-----------000-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlsseg8e16.v.yaml b/arch/inst/V/vlsseg8e16.v.yaml index d563b23877..b2caab9ec7 100644 --- a/arch/inst/V/vlsseg8e16.v.yaml +++ b/arch/inst/V/vlsseg8e16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlsseg8e16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 111010-----------101-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlsseg8e32.v.yaml b/arch/inst/V/vlsseg8e32.v.yaml index a37c82d999..5effd73f64 100644 --- a/arch/inst/V/vlsseg8e32.v.yaml +++ b/arch/inst/V/vlsseg8e32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlsseg8e32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 111010-----------110-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlsseg8e64.v.yaml b/arch/inst/V/vlsseg8e64.v.yaml index c9a6e417cd..6d0fc68ad8 100644 --- a/arch/inst/V/vlsseg8e64.v.yaml +++ b/arch/inst/V/vlsseg8e64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlsseg8e64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 111010-----------111-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vlsseg8e8.v.yaml b/arch/inst/V/vlsseg8e8.v.yaml index 71d8ed23da..84e9028998 100644 --- a/arch/inst/V/vlsseg8e8.v.yaml +++ b/arch/inst/V/vlsseg8e8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vlsseg8e8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vd encoding: match: 111010-----------000-----0000111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vluxei16.v.yaml b/arch/inst/V/vluxei16.v.yaml index 69010d3ea8..268991b9eb 100644 --- a/arch/inst/V/vluxei16.v.yaml +++ b/arch/inst/V/vluxei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 000001-----------101-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let EEW_index_pow = vlewidth_pow(width); diff --git a/arch/inst/V/vluxei32.v.yaml b/arch/inst/V/vluxei32.v.yaml index eee624fabc..49e5eb45bc 100644 --- a/arch/inst/V/vluxei32.v.yaml +++ b/arch/inst/V/vluxei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 000001-----------110-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let EEW_index_pow = vlewidth_pow(width); diff --git a/arch/inst/V/vluxei64.v.yaml b/arch/inst/V/vluxei64.v.yaml index 3429c2c320..4f9b114fac 100644 --- a/arch/inst/V/vluxei64.v.yaml +++ b/arch/inst/V/vluxei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 000001-----------111-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let EEW_index_pow = vlewidth_pow(width); diff --git a/arch/inst/V/vluxei8.v.yaml b/arch/inst/V/vluxei8.v.yaml index 64cffe056a..fd3c8fd00b 100644 --- a/arch/inst/V/vluxei8.v.yaml +++ b/arch/inst/V/vluxei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 000001-----------000-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let EEW_index_pow = vlewidth_pow(width); diff --git a/arch/inst/V/vluxseg2ei16.v.yaml b/arch/inst/V/vluxseg2ei16.v.yaml index fa80ccdc7b..e95d49b1f8 100644 --- a/arch/inst/V/vluxseg2ei16.v.yaml +++ b/arch/inst/V/vluxseg2ei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxseg2ei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 001001-----------101-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vluxseg2ei32.v.yaml b/arch/inst/V/vluxseg2ei32.v.yaml index 9d5656f6eb..31b98fdf5d 100644 --- a/arch/inst/V/vluxseg2ei32.v.yaml +++ b/arch/inst/V/vluxseg2ei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxseg2ei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 001001-----------110-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vluxseg2ei64.v.yaml b/arch/inst/V/vluxseg2ei64.v.yaml index 38996c6230..deef06eee4 100644 --- a/arch/inst/V/vluxseg2ei64.v.yaml +++ b/arch/inst/V/vluxseg2ei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxseg2ei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 001001-----------111-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vluxseg2ei8.v.yaml b/arch/inst/V/vluxseg2ei8.v.yaml index 6c714e5709..f71e23efd3 100644 --- a/arch/inst/V/vluxseg2ei8.v.yaml +++ b/arch/inst/V/vluxseg2ei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxseg2ei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 001001-----------000-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vluxseg3ei16.v.yaml b/arch/inst/V/vluxseg3ei16.v.yaml index 5d4ba029c3..d5c985f7bf 100644 --- a/arch/inst/V/vluxseg3ei16.v.yaml +++ b/arch/inst/V/vluxseg3ei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxseg3ei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 010001-----------101-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vluxseg3ei32.v.yaml b/arch/inst/V/vluxseg3ei32.v.yaml index 6a4ecd4985..3ba831308e 100644 --- a/arch/inst/V/vluxseg3ei32.v.yaml +++ b/arch/inst/V/vluxseg3ei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxseg3ei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 010001-----------110-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vluxseg3ei64.v.yaml b/arch/inst/V/vluxseg3ei64.v.yaml index dad4d516e0..c557efe272 100644 --- a/arch/inst/V/vluxseg3ei64.v.yaml +++ b/arch/inst/V/vluxseg3ei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxseg3ei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 010001-----------111-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vluxseg3ei8.v.yaml b/arch/inst/V/vluxseg3ei8.v.yaml index e162ada5ca..05c53af76e 100644 --- a/arch/inst/V/vluxseg3ei8.v.yaml +++ b/arch/inst/V/vluxseg3ei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxseg3ei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 010001-----------000-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vluxseg4ei16.v.yaml b/arch/inst/V/vluxseg4ei16.v.yaml index e6e85799fa..36541bf078 100644 --- a/arch/inst/V/vluxseg4ei16.v.yaml +++ b/arch/inst/V/vluxseg4ei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxseg4ei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 011001-----------101-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vluxseg4ei32.v.yaml b/arch/inst/V/vluxseg4ei32.v.yaml index 16bfdda268..83a50c046b 100644 --- a/arch/inst/V/vluxseg4ei32.v.yaml +++ b/arch/inst/V/vluxseg4ei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxseg4ei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 011001-----------110-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vluxseg4ei64.v.yaml b/arch/inst/V/vluxseg4ei64.v.yaml index 65de58e161..f2c389394b 100644 --- a/arch/inst/V/vluxseg4ei64.v.yaml +++ b/arch/inst/V/vluxseg4ei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxseg4ei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 011001-----------111-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vluxseg4ei8.v.yaml b/arch/inst/V/vluxseg4ei8.v.yaml index d0ab239540..8d23a879d6 100644 --- a/arch/inst/V/vluxseg4ei8.v.yaml +++ b/arch/inst/V/vluxseg4ei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxseg4ei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 011001-----------000-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vluxseg5ei16.v.yaml b/arch/inst/V/vluxseg5ei16.v.yaml index cb8c43f71a..d8aa2cf59d 100644 --- a/arch/inst/V/vluxseg5ei16.v.yaml +++ b/arch/inst/V/vluxseg5ei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxseg5ei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 100001-----------101-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vluxseg5ei32.v.yaml b/arch/inst/V/vluxseg5ei32.v.yaml index 3bf89d6aff..c43a04e869 100644 --- a/arch/inst/V/vluxseg5ei32.v.yaml +++ b/arch/inst/V/vluxseg5ei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxseg5ei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 100001-----------110-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vluxseg5ei64.v.yaml b/arch/inst/V/vluxseg5ei64.v.yaml index ddb29d4bbe..0e827a3250 100644 --- a/arch/inst/V/vluxseg5ei64.v.yaml +++ b/arch/inst/V/vluxseg5ei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxseg5ei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 100001-----------111-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vluxseg5ei8.v.yaml b/arch/inst/V/vluxseg5ei8.v.yaml index 01870a1c51..40019e9b9a 100644 --- a/arch/inst/V/vluxseg5ei8.v.yaml +++ b/arch/inst/V/vluxseg5ei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxseg5ei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 100001-----------000-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vluxseg6ei16.v.yaml b/arch/inst/V/vluxseg6ei16.v.yaml index 3326c77ff7..1db16ac36e 100644 --- a/arch/inst/V/vluxseg6ei16.v.yaml +++ b/arch/inst/V/vluxseg6ei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxseg6ei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 101001-----------101-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vluxseg6ei32.v.yaml b/arch/inst/V/vluxseg6ei32.v.yaml index 596227162b..e39b63452a 100644 --- a/arch/inst/V/vluxseg6ei32.v.yaml +++ b/arch/inst/V/vluxseg6ei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxseg6ei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 101001-----------110-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vluxseg6ei64.v.yaml b/arch/inst/V/vluxseg6ei64.v.yaml index ef5b21469f..1ec381f089 100644 --- a/arch/inst/V/vluxseg6ei64.v.yaml +++ b/arch/inst/V/vluxseg6ei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxseg6ei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 101001-----------111-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vluxseg6ei8.v.yaml b/arch/inst/V/vluxseg6ei8.v.yaml index 93db5170dc..933ffe429d 100644 --- a/arch/inst/V/vluxseg6ei8.v.yaml +++ b/arch/inst/V/vluxseg6ei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxseg6ei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 101001-----------000-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vluxseg7ei16.v.yaml b/arch/inst/V/vluxseg7ei16.v.yaml index 0d0d1223bf..185db29df8 100644 --- a/arch/inst/V/vluxseg7ei16.v.yaml +++ b/arch/inst/V/vluxseg7ei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxseg7ei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 110001-----------101-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vluxseg7ei32.v.yaml b/arch/inst/V/vluxseg7ei32.v.yaml index 09661bd0da..9f157aecc0 100644 --- a/arch/inst/V/vluxseg7ei32.v.yaml +++ b/arch/inst/V/vluxseg7ei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxseg7ei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 110001-----------110-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vluxseg7ei64.v.yaml b/arch/inst/V/vluxseg7ei64.v.yaml index da5490090f..a163420e59 100644 --- a/arch/inst/V/vluxseg7ei64.v.yaml +++ b/arch/inst/V/vluxseg7ei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxseg7ei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 110001-----------111-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vluxseg7ei8.v.yaml b/arch/inst/V/vluxseg7ei8.v.yaml index 9bf03adc45..e488f9d69f 100644 --- a/arch/inst/V/vluxseg7ei8.v.yaml +++ b/arch/inst/V/vluxseg7ei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxseg7ei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 110001-----------000-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vluxseg8ei16.v.yaml b/arch/inst/V/vluxseg8ei16.v.yaml index b64e783f4f..2b99804c85 100644 --- a/arch/inst/V/vluxseg8ei16.v.yaml +++ b/arch/inst/V/vluxseg8ei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxseg8ei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 111001-----------101-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vluxseg8ei32.v.yaml b/arch/inst/V/vluxseg8ei32.v.yaml index 5f53f3b233..729bcaa03a 100644 --- a/arch/inst/V/vluxseg8ei32.v.yaml +++ b/arch/inst/V/vluxseg8ei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxseg8ei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 111001-----------110-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vluxseg8ei64.v.yaml b/arch/inst/V/vluxseg8ei64.v.yaml index 6a5eaffaad..500087bbe1 100644 --- a/arch/inst/V/vluxseg8ei64.v.yaml +++ b/arch/inst/V/vluxseg8ei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxseg8ei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 111001-----------111-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vluxseg8ei8.v.yaml b/arch/inst/V/vluxseg8ei8.v.yaml index 0775f15d8f..51c5c5e6a6 100644 --- a/arch/inst/V/vluxseg8ei8.v.yaml +++ b/arch/inst/V/vluxseg8ei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vluxseg8ei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 111001-----------000-----0000111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vmacc.vv.yaml b/arch/inst/V/vmacc.vv.yaml index 2cfaba7c9e..5672d0a629 100644 --- a/arch/inst/V/vmacc.vv.yaml +++ b/arch/inst/V/vmacc.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmacc.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 101101-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmacc.vx.yaml b/arch/inst/V/vmacc.vx.yaml index eae6032500..567e470f40 100644 --- a/arch/inst/V/vmacc.vx.yaml +++ b/arch/inst/V/vmacc.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmacc.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 101101-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmadc.vi.yaml b/arch/inst/V/vmadc.vi.yaml index 06f7081b9f..2805add37d 100644 --- a/arch/inst/V/vmadc.vi.yaml +++ b/arch/inst/V/vmadc.vi.yaml @@ -5,18 +5,18 @@ kind: instruction name: vmadc.vi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, vd, imm encoding: match: 0100011----------011-----1010111 variables: - - name: vs2 - location: 24-20 - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmadc.vim.yaml b/arch/inst/V/vmadc.vim.yaml index f7add6ff82..f28cca0d25 100644 --- a/arch/inst/V/vmadc.vim.yaml +++ b/arch/inst/V/vmadc.vim.yaml @@ -5,18 +5,18 @@ kind: instruction name: vmadc.vim long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, vd, imm encoding: match: 0100010----------011-----1010111 variables: - - name: vs2 - location: 24-20 - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmadc.vv.yaml b/arch/inst/V/vmadc.vv.yaml index 18f0baafd0..6cbedeccd1 100644 --- a/arch/inst/V/vmadc.vv.yaml +++ b/arch/inst/V/vmadc.vv.yaml @@ -5,18 +5,18 @@ kind: instruction name: vmadc.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, vs1, vd encoding: match: 0100011----------000-----1010111 variables: - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmadc.vvm.yaml b/arch/inst/V/vmadc.vvm.yaml index a367b3624c..48715e4762 100644 --- a/arch/inst/V/vmadc.vvm.yaml +++ b/arch/inst/V/vmadc.vvm.yaml @@ -5,18 +5,18 @@ kind: instruction name: vmadc.vvm long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, vs1, vd encoding: match: 0100010----------000-----1010111 variables: - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmadc.vx.yaml b/arch/inst/V/vmadc.vx.yaml index e216e96b54..639d677d50 100644 --- a/arch/inst/V/vmadc.vx.yaml +++ b/arch/inst/V/vmadc.vx.yaml @@ -5,18 +5,18 @@ kind: instruction name: vmadc.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, xs1, vd encoding: match: 0100011----------100-----1010111 variables: - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmadc.vxm.yaml b/arch/inst/V/vmadc.vxm.yaml index 42be4e178e..8929778305 100644 --- a/arch/inst/V/vmadc.vxm.yaml +++ b/arch/inst/V/vmadc.vxm.yaml @@ -5,18 +5,18 @@ kind: instruction name: vmadc.vxm long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, xs1, vd encoding: match: 0100010----------100-----1010111 variables: - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmadd.vv.yaml b/arch/inst/V/vmadd.vv.yaml index d126ca055c..3e1b9742c0 100644 --- a/arch/inst/V/vmadd.vv.yaml +++ b/arch/inst/V/vmadd.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmadd.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 101001-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmadd.vx.yaml b/arch/inst/V/vmadd.vx.yaml index 605641cd1f..284c069108 100644 --- a/arch/inst/V/vmadd.vx.yaml +++ b/arch/inst/V/vmadd.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmadd.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 101001-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmand.mm.yaml b/arch/inst/V/vmand.mm.yaml index 71b3d684bf..12c96c2cd2 100644 --- a/arch/inst/V/vmand.mm.yaml +++ b/arch/inst/V/vmand.mm.yaml @@ -5,18 +5,18 @@ kind: instruction name: vmand.mm long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, vs1, vd encoding: match: 0110011----------010-----1010111 variables: - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmandn.mm.yaml b/arch/inst/V/vmandn.mm.yaml index 78e38995c0..f20981b6e5 100644 --- a/arch/inst/V/vmandn.mm.yaml +++ b/arch/inst/V/vmandn.mm.yaml @@ -5,18 +5,18 @@ kind: instruction name: vmandn.mm long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, vs1, vd encoding: match: 0110001----------010-----1010111 variables: - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vmax.vv.yaml b/arch/inst/V/vmax.vv.yaml index c3047be500..d280f75e74 100644 --- a/arch/inst/V/vmax.vv.yaml +++ b/arch/inst/V/vmax.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmax.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 000111-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW_pow = get_sew_pow(); diff --git a/arch/inst/V/vmax.vx.yaml b/arch/inst/V/vmax.vx.yaml index 6766e04533..d46e15dc13 100644 --- a/arch/inst/V/vmax.vx.yaml +++ b/arch/inst/V/vmax.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmax.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 000111-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmaxu.vv.yaml b/arch/inst/V/vmaxu.vv.yaml index 986712f510..cbda877766 100644 --- a/arch/inst/V/vmaxu.vv.yaml +++ b/arch/inst/V/vmaxu.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmaxu.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 000110-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW_pow = get_sew_pow(); diff --git a/arch/inst/V/vmaxu.vx.yaml b/arch/inst/V/vmaxu.vx.yaml index b5c1649621..11ce724d4a 100644 --- a/arch/inst/V/vmaxu.vx.yaml +++ b/arch/inst/V/vmaxu.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmaxu.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 000110-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmerge.vim.yaml b/arch/inst/V/vmerge.vim.yaml index 80a4b3b5f6..9cf80d2296 100644 --- a/arch/inst/V/vmerge.vim.yaml +++ b/arch/inst/V/vmerge.vim.yaml @@ -5,18 +5,18 @@ kind: instruction name: vmerge.vim long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, vd, imm encoding: match: 0101110----------011-----1010111 variables: - - name: vs2 - location: 24-20 - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let start_element = get_start_element(); diff --git a/arch/inst/V/vmerge.vvm.yaml b/arch/inst/V/vmerge.vvm.yaml index ad5f77d978..b697a2f83b 100644 --- a/arch/inst/V/vmerge.vvm.yaml +++ b/arch/inst/V/vmerge.vvm.yaml @@ -5,18 +5,18 @@ kind: instruction name: vmerge.vvm long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, vs1, vd encoding: match: 0101110----------000-----1010111 variables: - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let start_element = get_start_element(); diff --git a/arch/inst/V/vmerge.vxm.yaml b/arch/inst/V/vmerge.vxm.yaml index 1dbddcabab..fab9487e18 100644 --- a/arch/inst/V/vmerge.vxm.yaml +++ b/arch/inst/V/vmerge.vxm.yaml @@ -5,18 +5,18 @@ kind: instruction name: vmerge.vxm long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, xs1, vd encoding: match: 0101110----------100-----1010111 variables: - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let start_element = get_start_element(); diff --git a/arch/inst/V/vmfeq.vf.yaml b/arch/inst/V/vmfeq.vf.yaml index 3e9412057c..2c95068970 100644 --- a/arch/inst/V/vmfeq.vf.yaml +++ b/arch/inst/V/vmfeq.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmfeq.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 011000-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vmfeq.vv.yaml b/arch/inst/V/vmfeq.vv.yaml index 2663d6d031..18585c143b 100644 --- a/arch/inst/V/vmfeq.vv.yaml +++ b/arch/inst/V/vmfeq.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmfeq.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 011000-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vmfge.vf.yaml b/arch/inst/V/vmfge.vf.yaml index 2e7cf5ff3e..02719fdf39 100644 --- a/arch/inst/V/vmfge.vf.yaml +++ b/arch/inst/V/vmfge.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmfge.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 011111-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vmfgt.vf.yaml b/arch/inst/V/vmfgt.vf.yaml index 13197e5704..0a59ae4ff3 100644 --- a/arch/inst/V/vmfgt.vf.yaml +++ b/arch/inst/V/vmfgt.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmfgt.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 011101-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vmfle.vf.yaml b/arch/inst/V/vmfle.vf.yaml index f85b9dbf53..c6cf50f93f 100644 --- a/arch/inst/V/vmfle.vf.yaml +++ b/arch/inst/V/vmfle.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmfle.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 011001-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vmfle.vv.yaml b/arch/inst/V/vmfle.vv.yaml index 318034f107..13a7a16b06 100644 --- a/arch/inst/V/vmfle.vv.yaml +++ b/arch/inst/V/vmfle.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmfle.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 011001-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vmflt.vf.yaml b/arch/inst/V/vmflt.vf.yaml index 77d68c8381..805fce9209 100644 --- a/arch/inst/V/vmflt.vf.yaml +++ b/arch/inst/V/vmflt.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmflt.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 011011-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vmflt.vv.yaml b/arch/inst/V/vmflt.vv.yaml index 676841f717..a5f85749c3 100644 --- a/arch/inst/V/vmflt.vv.yaml +++ b/arch/inst/V/vmflt.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmflt.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 011011-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vmfne.vf.yaml b/arch/inst/V/vmfne.vf.yaml index adf5cd410e..069bb187c5 100644 --- a/arch/inst/V/vmfne.vf.yaml +++ b/arch/inst/V/vmfne.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmfne.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 011100-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vmfne.vv.yaml b/arch/inst/V/vmfne.vv.yaml index a5078c955d..7652613a9f 100644 --- a/arch/inst/V/vmfne.vv.yaml +++ b/arch/inst/V/vmfne.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmfne.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 011100-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let rm_3b = fcsr.FRM(); diff --git a/arch/inst/V/vmin.vv.yaml b/arch/inst/V/vmin.vv.yaml index 4b5c9cad97..1921b1c2e2 100644 --- a/arch/inst/V/vmin.vv.yaml +++ b/arch/inst/V/vmin.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmin.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 000101-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW_pow = get_sew_pow(); diff --git a/arch/inst/V/vmin.vx.yaml b/arch/inst/V/vmin.vx.yaml index 12be058ede..5c1688142e 100644 --- a/arch/inst/V/vmin.vx.yaml +++ b/arch/inst/V/vmin.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmin.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 000101-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vminu.vv.yaml b/arch/inst/V/vminu.vv.yaml index 897d4b1207..5c8ad591c3 100644 --- a/arch/inst/V/vminu.vv.yaml +++ b/arch/inst/V/vminu.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vminu.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 000100-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW_pow = get_sew_pow(); diff --git a/arch/inst/V/vminu.vx.yaml b/arch/inst/V/vminu.vx.yaml index 890b564300..5ad49941a0 100644 --- a/arch/inst/V/vminu.vx.yaml +++ b/arch/inst/V/vminu.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vminu.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 000100-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmnand.mm.yaml b/arch/inst/V/vmnand.mm.yaml index e32a80db47..24ae63b6a0 100644 --- a/arch/inst/V/vmnand.mm.yaml +++ b/arch/inst/V/vmnand.mm.yaml @@ -5,18 +5,18 @@ kind: instruction name: vmnand.mm long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, vs1, vd encoding: match: 0111011----------010-----1010111 variables: - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmnor.mm.yaml b/arch/inst/V/vmnor.mm.yaml index e0ccff3e3f..e0aa1d8fdb 100644 --- a/arch/inst/V/vmnor.mm.yaml +++ b/arch/inst/V/vmnor.mm.yaml @@ -5,18 +5,18 @@ kind: instruction name: vmnor.mm long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, vs1, vd encoding: match: 0111101----------010-----1010111 variables: - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmor.mm.yaml b/arch/inst/V/vmor.mm.yaml index 81e64a938b..6f2c1d91a7 100644 --- a/arch/inst/V/vmor.mm.yaml +++ b/arch/inst/V/vmor.mm.yaml @@ -5,18 +5,18 @@ kind: instruction name: vmor.mm long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, vs1, vd encoding: match: 0110101----------010-----1010111 variables: - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmorn.mm.yaml b/arch/inst/V/vmorn.mm.yaml index 89e53e8fec..754592837d 100644 --- a/arch/inst/V/vmorn.mm.yaml +++ b/arch/inst/V/vmorn.mm.yaml @@ -5,18 +5,18 @@ kind: instruction name: vmorn.mm long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, vs1, vd encoding: match: 0111001----------010-----1010111 variables: - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vmsbc.vv.yaml b/arch/inst/V/vmsbc.vv.yaml index f7fa84ea2b..f0002611b0 100644 --- a/arch/inst/V/vmsbc.vv.yaml +++ b/arch/inst/V/vmsbc.vv.yaml @@ -5,18 +5,18 @@ kind: instruction name: vmsbc.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, vs1, vd encoding: match: 0100111----------000-----1010111 variables: - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmsbc.vvm.yaml b/arch/inst/V/vmsbc.vvm.yaml index c4837da151..53f82a2503 100644 --- a/arch/inst/V/vmsbc.vvm.yaml +++ b/arch/inst/V/vmsbc.vvm.yaml @@ -5,18 +5,18 @@ kind: instruction name: vmsbc.vvm long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, vs1, vd encoding: match: 0100110----------000-----1010111 variables: - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmsbc.vx.yaml b/arch/inst/V/vmsbc.vx.yaml index 2caf127ca2..86ac315ec0 100644 --- a/arch/inst/V/vmsbc.vx.yaml +++ b/arch/inst/V/vmsbc.vx.yaml @@ -5,18 +5,18 @@ kind: instruction name: vmsbc.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, xs1, vd encoding: match: 0100111----------100-----1010111 variables: - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmsbc.vxm.yaml b/arch/inst/V/vmsbc.vxm.yaml index f0865388b0..71e0187653 100644 --- a/arch/inst/V/vmsbc.vxm.yaml +++ b/arch/inst/V/vmsbc.vxm.yaml @@ -5,18 +5,18 @@ kind: instruction name: vmsbc.vxm long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, xs1, vd encoding: match: 0100110----------100-----1010111 variables: - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmsbf.m.yaml b/arch/inst/V/vmsbf.m.yaml index fe85db16a6..9d242a5854 100644 --- a/arch/inst/V/vmsbf.m.yaml +++ b/arch/inst/V/vmsbf.m.yaml @@ -5,18 +5,18 @@ kind: instruction name: vmsbf.m long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010100------00001010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmseq.vi.yaml b/arch/inst/V/vmseq.vi.yaml index fc52fa6a6e..ac5705655f 100644 --- a/arch/inst/V/vmseq.vi.yaml +++ b/arch/inst/V/vmseq.vi.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmseq.vi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd, imm encoding: match: 011000-----------011-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmseq.vv.yaml b/arch/inst/V/vmseq.vv.yaml index cfb1bb786e..7e611a1a3a 100644 --- a/arch/inst/V/vmseq.vv.yaml +++ b/arch/inst/V/vmseq.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmseq.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 011000-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmseq.vx.yaml b/arch/inst/V/vmseq.vx.yaml index 55003e0e7f..eff36fb712 100644 --- a/arch/inst/V/vmseq.vx.yaml +++ b/arch/inst/V/vmseq.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmseq.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 011000-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmsgt.vi.yaml b/arch/inst/V/vmsgt.vi.yaml index 946b787fb8..8536d5c107 100644 --- a/arch/inst/V/vmsgt.vi.yaml +++ b/arch/inst/V/vmsgt.vi.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmsgt.vi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd, imm encoding: match: 011111-----------011-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmsgt.vx.yaml b/arch/inst/V/vmsgt.vx.yaml index fd878324b2..98e1427e23 100644 --- a/arch/inst/V/vmsgt.vx.yaml +++ b/arch/inst/V/vmsgt.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmsgt.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 011111-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmsgtu.vi.yaml b/arch/inst/V/vmsgtu.vi.yaml index 9119f759c2..52f999cd5d 100644 --- a/arch/inst/V/vmsgtu.vi.yaml +++ b/arch/inst/V/vmsgtu.vi.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmsgtu.vi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd, imm encoding: match: 011110-----------011-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmsgtu.vx.yaml b/arch/inst/V/vmsgtu.vx.yaml index 5943925efb..44ebb47f69 100644 --- a/arch/inst/V/vmsgtu.vx.yaml +++ b/arch/inst/V/vmsgtu.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmsgtu.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 011110-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmsif.m.yaml b/arch/inst/V/vmsif.m.yaml index 0082106586..1790f1ef3a 100644 --- a/arch/inst/V/vmsif.m.yaml +++ b/arch/inst/V/vmsif.m.yaml @@ -5,18 +5,18 @@ kind: instruction name: vmsif.m long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010100------00011010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmsle.vi.yaml b/arch/inst/V/vmsle.vi.yaml index a7d5d7367e..1901822f62 100644 --- a/arch/inst/V/vmsle.vi.yaml +++ b/arch/inst/V/vmsle.vi.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmsle.vi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd, imm encoding: match: 011101-----------011-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmsle.vv.yaml b/arch/inst/V/vmsle.vv.yaml index 6a41afaaa1..7d0cbed761 100644 --- a/arch/inst/V/vmsle.vv.yaml +++ b/arch/inst/V/vmsle.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmsle.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 011101-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmsle.vx.yaml b/arch/inst/V/vmsle.vx.yaml index a8474a3889..b6183dd83b 100644 --- a/arch/inst/V/vmsle.vx.yaml +++ b/arch/inst/V/vmsle.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmsle.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 011101-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmsleu.vi.yaml b/arch/inst/V/vmsleu.vi.yaml index 0adb60845b..8e222c8ee2 100644 --- a/arch/inst/V/vmsleu.vi.yaml +++ b/arch/inst/V/vmsleu.vi.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmsleu.vi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd, imm encoding: match: 011100-----------011-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmsleu.vv.yaml b/arch/inst/V/vmsleu.vv.yaml index 953e32a489..45635d6030 100644 --- a/arch/inst/V/vmsleu.vv.yaml +++ b/arch/inst/V/vmsleu.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmsleu.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 011100-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmsleu.vx.yaml b/arch/inst/V/vmsleu.vx.yaml index 7a1122585f..04d5acc736 100644 --- a/arch/inst/V/vmsleu.vx.yaml +++ b/arch/inst/V/vmsleu.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmsleu.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 011100-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmslt.vv.yaml b/arch/inst/V/vmslt.vv.yaml index f275667bd8..82749272f2 100644 --- a/arch/inst/V/vmslt.vv.yaml +++ b/arch/inst/V/vmslt.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmslt.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 011011-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmslt.vx.yaml b/arch/inst/V/vmslt.vx.yaml index b44cd616b7..65b858618b 100644 --- a/arch/inst/V/vmslt.vx.yaml +++ b/arch/inst/V/vmslt.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmslt.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 011011-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmsltu.vv.yaml b/arch/inst/V/vmsltu.vv.yaml index 7da2e1662b..3b3cec1af8 100644 --- a/arch/inst/V/vmsltu.vv.yaml +++ b/arch/inst/V/vmsltu.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmsltu.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 011010-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmsltu.vx.yaml b/arch/inst/V/vmsltu.vx.yaml index 92d8ecbceb..a22e631854 100644 --- a/arch/inst/V/vmsltu.vx.yaml +++ b/arch/inst/V/vmsltu.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmsltu.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 011010-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmsne.vi.yaml b/arch/inst/V/vmsne.vi.yaml index 8f9fe39bbf..f817fb451b 100644 --- a/arch/inst/V/vmsne.vi.yaml +++ b/arch/inst/V/vmsne.vi.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmsne.vi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd, imm encoding: match: 011001-----------011-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmsne.vv.yaml b/arch/inst/V/vmsne.vv.yaml index 69cb50f337..2ac5b85a39 100644 --- a/arch/inst/V/vmsne.vv.yaml +++ b/arch/inst/V/vmsne.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmsne.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 011001-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmsne.vx.yaml b/arch/inst/V/vmsne.vx.yaml index 0e642b27ed..826577646a 100644 --- a/arch/inst/V/vmsne.vx.yaml +++ b/arch/inst/V/vmsne.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmsne.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 011001-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmsof.m.yaml b/arch/inst/V/vmsof.m.yaml index 6d6ff006fe..da6f3d05ba 100644 --- a/arch/inst/V/vmsof.m.yaml +++ b/arch/inst/V/vmsof.m.yaml @@ -5,18 +5,18 @@ kind: instruction name: vmsof.m long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010100------00010010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmul.vv.yaml b/arch/inst/V/vmul.vv.yaml index 7d91cd8a5b..a4210779d8 100644 --- a/arch/inst/V/vmul.vv.yaml +++ b/arch/inst/V/vmul.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmul.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 100101-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmul.vx.yaml b/arch/inst/V/vmul.vx.yaml index e05e8672d2..310e32ebda 100644 --- a/arch/inst/V/vmul.vx.yaml +++ b/arch/inst/V/vmul.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmul.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 100101-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmulh.vv.yaml b/arch/inst/V/vmulh.vv.yaml index e189c650e0..53e4b0cdfe 100644 --- a/arch/inst/V/vmulh.vv.yaml +++ b/arch/inst/V/vmulh.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmulh.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 100111-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmulh.vx.yaml b/arch/inst/V/vmulh.vx.yaml index 4cf640bad2..b3303e0b9a 100644 --- a/arch/inst/V/vmulh.vx.yaml +++ b/arch/inst/V/vmulh.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmulh.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 100111-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmulhsu.vv.yaml b/arch/inst/V/vmulhsu.vv.yaml index bb9a147cf2..5b86934be4 100644 --- a/arch/inst/V/vmulhsu.vv.yaml +++ b/arch/inst/V/vmulhsu.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmulhsu.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 100110-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmulhsu.vx.yaml b/arch/inst/V/vmulhsu.vx.yaml index f81024ed11..133fc39f24 100644 --- a/arch/inst/V/vmulhsu.vx.yaml +++ b/arch/inst/V/vmulhsu.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmulhsu.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 100110-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmulhu.vv.yaml b/arch/inst/V/vmulhu.vv.yaml index a78c29831f..c52e92b956 100644 --- a/arch/inst/V/vmulhu.vv.yaml +++ b/arch/inst/V/vmulhu.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmulhu.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 100100-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmulhu.vx.yaml b/arch/inst/V/vmulhu.vx.yaml index 1ab5613bb2..8997d372f4 100644 --- a/arch/inst/V/vmulhu.vx.yaml +++ b/arch/inst/V/vmulhu.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vmulhu.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 100100-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmv.s.x.yaml b/arch/inst/V/vmv.s.x.yaml index 2d4a355584..668b3eac6f 100644 --- a/arch/inst/V/vmv.s.x.yaml +++ b/arch/inst/V/vmv.s.x.yaml @@ -5,16 +5,16 @@ kind: instruction name: vmv.s.x long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: xs1, vd encoding: match: 010000100000-----110-----1010111 variables: - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -23,9 +23,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmv.v.i.yaml b/arch/inst/V/vmv.v.i.yaml index dee7de9eca..94adc6c7d0 100644 --- a/arch/inst/V/vmv.v.i.yaml +++ b/arch/inst/V/vmv.v.i.yaml @@ -5,16 +5,16 @@ kind: instruction name: vmv.v.i long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vd, imm encoding: match: 010111100000-----011-----1010111 variables: - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -23,9 +23,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmv.v.v.yaml b/arch/inst/V/vmv.v.v.yaml index 29cdff6084..bd4775fc56 100644 --- a/arch/inst/V/vmv.v.v.yaml +++ b/arch/inst/V/vmv.v.v.yaml @@ -5,16 +5,16 @@ kind: instruction name: vmv.v.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs1, vd encoding: match: 010111100000-----000-----1010111 variables: - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -23,9 +23,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmv.v.x.yaml b/arch/inst/V/vmv.v.x.yaml index 5efb079a00..7ddc9569e7 100644 --- a/arch/inst/V/vmv.v.x.yaml +++ b/arch/inst/V/vmv.v.x.yaml @@ -5,16 +5,16 @@ kind: instruction name: vmv.v.x long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: xs1, vd encoding: match: 010111100000-----100-----1010111 variables: - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -23,9 +23,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmv.x.s.yaml b/arch/inst/V/vmv.x.s.yaml index 40aed3db6d..ae424d3dd4 100644 --- a/arch/inst/V/vmv.x.s.yaml +++ b/arch/inst/V/vmv.x.s.yaml @@ -5,16 +5,16 @@ kind: instruction name: vmv.x.s long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, xd encoding: match: 0100001-----00000010-----1010111 variables: - - name: vs2 - location: 24-20 - - name: rd - location: 11-7 + - name: vs2 + location: 24-20 + - name: rd + location: 11-7 access: s: always u: always @@ -23,9 +23,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmv1r.v.yaml b/arch/inst/V/vmv1r.v.yaml index 4d3d470ed3..e6be91c909 100644 --- a/arch/inst/V/vmv1r.v.yaml +++ b/arch/inst/V/vmv1r.v.yaml @@ -5,16 +5,16 @@ kind: instruction name: vmv1r.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, vd encoding: match: 1001111-----00000011-----1010111 variables: - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -23,9 +23,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let start_element = get_start_element(); diff --git a/arch/inst/V/vmv2r.v.yaml b/arch/inst/V/vmv2r.v.yaml index 88b8705a1e..98de56eb60 100644 --- a/arch/inst/V/vmv2r.v.yaml +++ b/arch/inst/V/vmv2r.v.yaml @@ -5,16 +5,16 @@ kind: instruction name: vmv2r.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, vd encoding: match: 1001111-----00001011-----1010111 variables: - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -23,9 +23,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let start_element = get_start_element(); diff --git a/arch/inst/V/vmv4r.v.yaml b/arch/inst/V/vmv4r.v.yaml index 99ac5a720c..525b1e7360 100644 --- a/arch/inst/V/vmv4r.v.yaml +++ b/arch/inst/V/vmv4r.v.yaml @@ -5,16 +5,16 @@ kind: instruction name: vmv4r.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, vd encoding: match: 1001111-----00011011-----1010111 variables: - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -23,9 +23,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let start_element = get_start_element(); diff --git a/arch/inst/V/vmv8r.v.yaml b/arch/inst/V/vmv8r.v.yaml index 66074274c7..d2b6fe8ba7 100644 --- a/arch/inst/V/vmv8r.v.yaml +++ b/arch/inst/V/vmv8r.v.yaml @@ -5,16 +5,16 @@ kind: instruction name: vmv8r.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, vd encoding: match: 1001111-----00111011-----1010111 variables: - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -23,9 +23,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let start_element = get_start_element(); diff --git a/arch/inst/V/vmxnor.mm.yaml b/arch/inst/V/vmxnor.mm.yaml index e4f9dbf04e..426539a0a6 100644 --- a/arch/inst/V/vmxnor.mm.yaml +++ b/arch/inst/V/vmxnor.mm.yaml @@ -5,18 +5,18 @@ kind: instruction name: vmxnor.mm long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, vs1, vd encoding: match: 0111111----------010-----1010111 variables: - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vmxor.mm.yaml b/arch/inst/V/vmxor.mm.yaml index ec0ea44ef2..1e035d0ad5 100644 --- a/arch/inst/V/vmxor.mm.yaml +++ b/arch/inst/V/vmxor.mm.yaml @@ -5,18 +5,18 @@ kind: instruction name: vmxor.mm long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, vs1, vd encoding: match: 0110111----------010-----1010111 variables: - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vnclip.wi.yaml b/arch/inst/V/vnclip.wi.yaml index e231052abb..9effdbccdf 100644 --- a/arch/inst/V/vnclip.wi.yaml +++ b/arch/inst/V/vnclip.wi.yaml @@ -5,20 +5,20 @@ kind: instruction name: vnclip.wi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd, imm encoding: match: 101111-----------011-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vnclip.wv.yaml b/arch/inst/V/vnclip.wv.yaml index faca59c938..bdb5b51274 100644 --- a/arch/inst/V/vnclip.wv.yaml +++ b/arch/inst/V/vnclip.wv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vnclip.wv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 101111-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vnclip.wx.yaml b/arch/inst/V/vnclip.wx.yaml index ee879075e5..ade93bcf00 100644 --- a/arch/inst/V/vnclip.wx.yaml +++ b/arch/inst/V/vnclip.wx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vnclip.wx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 101111-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vnclipu.wi.yaml b/arch/inst/V/vnclipu.wi.yaml index 7cf326ed0c..8ff4cfea1e 100644 --- a/arch/inst/V/vnclipu.wi.yaml +++ b/arch/inst/V/vnclipu.wi.yaml @@ -5,20 +5,20 @@ kind: instruction name: vnclipu.wi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd, imm encoding: match: 101110-----------011-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vnclipu.wv.yaml b/arch/inst/V/vnclipu.wv.yaml index b4a565a40e..286cb1705d 100644 --- a/arch/inst/V/vnclipu.wv.yaml +++ b/arch/inst/V/vnclipu.wv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vnclipu.wv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 101110-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vnclipu.wx.yaml b/arch/inst/V/vnclipu.wx.yaml index af13d2fe96..f25012a8b4 100644 --- a/arch/inst/V/vnclipu.wx.yaml +++ b/arch/inst/V/vnclipu.wx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vnclipu.wx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 101110-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vnmsac.vv.yaml b/arch/inst/V/vnmsac.vv.yaml index f9426f75c8..cc878e7d3c 100644 --- a/arch/inst/V/vnmsac.vv.yaml +++ b/arch/inst/V/vnmsac.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vnmsac.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 101111-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vnmsac.vx.yaml b/arch/inst/V/vnmsac.vx.yaml index 307b1d45a1..17ae1f83a2 100644 --- a/arch/inst/V/vnmsac.vx.yaml +++ b/arch/inst/V/vnmsac.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vnmsac.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 101111-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vnmsub.vv.yaml b/arch/inst/V/vnmsub.vv.yaml index 23c4cfdaf3..57c1ac53c6 100644 --- a/arch/inst/V/vnmsub.vv.yaml +++ b/arch/inst/V/vnmsub.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vnmsub.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 101011-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vnmsub.vx.yaml b/arch/inst/V/vnmsub.vx.yaml index 95270f1a9d..49bb3f4b35 100644 --- a/arch/inst/V/vnmsub.vx.yaml +++ b/arch/inst/V/vnmsub.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vnmsub.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 101011-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vnsra.wi.yaml b/arch/inst/V/vnsra.wi.yaml index 67e6aaa0f9..dd25b26458 100644 --- a/arch/inst/V/vnsra.wi.yaml +++ b/arch/inst/V/vnsra.wi.yaml @@ -5,20 +5,20 @@ kind: instruction name: vnsra.wi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd, imm encoding: match: 101101-----------011-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vnsra.wv.yaml b/arch/inst/V/vnsra.wv.yaml index a9e6be1155..e016d2fef2 100644 --- a/arch/inst/V/vnsra.wv.yaml +++ b/arch/inst/V/vnsra.wv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vnsra.wv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 101101-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vnsra.wx.yaml b/arch/inst/V/vnsra.wx.yaml index f8e6b05597..663fbca1a6 100644 --- a/arch/inst/V/vnsra.wx.yaml +++ b/arch/inst/V/vnsra.wx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vnsra.wx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 101101-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vnsrl.wi.yaml b/arch/inst/V/vnsrl.wi.yaml index 7b35f84f1b..a46b6644bf 100644 --- a/arch/inst/V/vnsrl.wi.yaml +++ b/arch/inst/V/vnsrl.wi.yaml @@ -5,20 +5,20 @@ kind: instruction name: vnsrl.wi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd, imm encoding: match: 101100-----------011-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vnsrl.wv.yaml b/arch/inst/V/vnsrl.wv.yaml index 3c8c95679a..1822c68f80 100644 --- a/arch/inst/V/vnsrl.wv.yaml +++ b/arch/inst/V/vnsrl.wv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vnsrl.wv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 101100-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vnsrl.wx.yaml b/arch/inst/V/vnsrl.wx.yaml index 92b3679cf6..2a65a17df0 100644 --- a/arch/inst/V/vnsrl.wx.yaml +++ b/arch/inst/V/vnsrl.wx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vnsrl.wx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 101100-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vor.vi.yaml b/arch/inst/V/vor.vi.yaml index 99f59df679..a3739c34da 100644 --- a/arch/inst/V/vor.vi.yaml +++ b/arch/inst/V/vor.vi.yaml @@ -5,20 +5,20 @@ kind: instruction name: vor.vi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd, imm encoding: match: 001010-----------011-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vor.vv.yaml b/arch/inst/V/vor.vv.yaml index c832084738..276e2c82e6 100644 --- a/arch/inst/V/vor.vv.yaml +++ b/arch/inst/V/vor.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vor.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 001010-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW_pow = get_sew_pow(); diff --git a/arch/inst/V/vor.vx.yaml b/arch/inst/V/vor.vx.yaml index 9ad6b20d1e..2633fb284f 100644 --- a/arch/inst/V/vor.vx.yaml +++ b/arch/inst/V/vor.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vor.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 001010-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vredand.vs.yaml b/arch/inst/V/vredand.vs.yaml index 135ed6bb39..7679f5f5c5 100644 --- a/arch/inst/V/vredand.vs.yaml +++ b/arch/inst/V/vredand.vs.yaml @@ -5,20 +5,20 @@ kind: instruction name: vredand.vs long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 000001-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vredmax.vs.yaml b/arch/inst/V/vredmax.vs.yaml index 9d1b12a38e..5f69012702 100644 --- a/arch/inst/V/vredmax.vs.yaml +++ b/arch/inst/V/vredmax.vs.yaml @@ -5,20 +5,20 @@ kind: instruction name: vredmax.vs long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 000111-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vredmaxu.vs.yaml b/arch/inst/V/vredmaxu.vs.yaml index 977d71dac4..76c5a03962 100644 --- a/arch/inst/V/vredmaxu.vs.yaml +++ b/arch/inst/V/vredmaxu.vs.yaml @@ -5,20 +5,20 @@ kind: instruction name: vredmaxu.vs long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 000110-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vredmin.vs.yaml b/arch/inst/V/vredmin.vs.yaml index df9b4ba46d..f7e4124412 100644 --- a/arch/inst/V/vredmin.vs.yaml +++ b/arch/inst/V/vredmin.vs.yaml @@ -5,20 +5,20 @@ kind: instruction name: vredmin.vs long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 000101-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vredminu.vs.yaml b/arch/inst/V/vredminu.vs.yaml index f3ee165cb8..b54e850d60 100644 --- a/arch/inst/V/vredminu.vs.yaml +++ b/arch/inst/V/vredminu.vs.yaml @@ -5,20 +5,20 @@ kind: instruction name: vredminu.vs long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 000100-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vredor.vs.yaml b/arch/inst/V/vredor.vs.yaml index 121bee827f..676a9903ec 100644 --- a/arch/inst/V/vredor.vs.yaml +++ b/arch/inst/V/vredor.vs.yaml @@ -5,20 +5,20 @@ kind: instruction name: vredor.vs long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 000010-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vredsum.vs.yaml b/arch/inst/V/vredsum.vs.yaml index be0b41c8b3..42826d911a 100644 --- a/arch/inst/V/vredsum.vs.yaml +++ b/arch/inst/V/vredsum.vs.yaml @@ -5,20 +5,20 @@ kind: instruction name: vredsum.vs long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 000000-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vredxor.vs.yaml b/arch/inst/V/vredxor.vs.yaml index b9500c5acf..5203454a68 100644 --- a/arch/inst/V/vredxor.vs.yaml +++ b/arch/inst/V/vredxor.vs.yaml @@ -5,20 +5,20 @@ kind: instruction name: vredxor.vs long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 000011-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vrem.vv.yaml b/arch/inst/V/vrem.vv.yaml index 54b4458720..39f6b52283 100644 --- a/arch/inst/V/vrem.vv.yaml +++ b/arch/inst/V/vrem.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vrem.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 100011-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vrem.vx.yaml b/arch/inst/V/vrem.vx.yaml index 976f7a73b8..4d487b0b21 100644 --- a/arch/inst/V/vrem.vx.yaml +++ b/arch/inst/V/vrem.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vrem.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 100011-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vremu.vv.yaml b/arch/inst/V/vremu.vv.yaml index 4262b9e292..f166b2c60b 100644 --- a/arch/inst/V/vremu.vv.yaml +++ b/arch/inst/V/vremu.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vremu.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 100010-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vremu.vx.yaml b/arch/inst/V/vremu.vx.yaml index 3709f7afc7..1e80ef3c4c 100644 --- a/arch/inst/V/vremu.vx.yaml +++ b/arch/inst/V/vremu.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vremu.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 100010-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vrgather.vi.yaml b/arch/inst/V/vrgather.vi.yaml index 8f8c6f157c..1e81be3cf7 100644 --- a/arch/inst/V/vrgather.vi.yaml +++ b/arch/inst/V/vrgather.vi.yaml @@ -5,20 +5,20 @@ kind: instruction name: vrgather.vi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd, imm encoding: match: 001100-----------011-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW_pow = get_sew_pow(); diff --git a/arch/inst/V/vrgather.vv.yaml b/arch/inst/V/vrgather.vv.yaml index 17c92e6d44..dd538e277b 100644 --- a/arch/inst/V/vrgather.vv.yaml +++ b/arch/inst/V/vrgather.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vrgather.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 001100-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW_pow = get_sew_pow(); diff --git a/arch/inst/V/vrgather.vx.yaml b/arch/inst/V/vrgather.vx.yaml index 10763af3b6..eae65325dc 100644 --- a/arch/inst/V/vrgather.vx.yaml +++ b/arch/inst/V/vrgather.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vrgather.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 001100-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW_pow = get_sew_pow(); diff --git a/arch/inst/V/vrgatherei16.vv.yaml b/arch/inst/V/vrgatherei16.vv.yaml index 3edfd3f2b3..f823b9ed6e 100644 --- a/arch/inst/V/vrgatherei16.vv.yaml +++ b/arch/inst/V/vrgatherei16.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vrgatherei16.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 001110-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW_pow = get_sew_pow(); diff --git a/arch/inst/V/vrsub.vi.yaml b/arch/inst/V/vrsub.vi.yaml index 5e369d5e16..b5b3327388 100644 --- a/arch/inst/V/vrsub.vi.yaml +++ b/arch/inst/V/vrsub.vi.yaml @@ -5,20 +5,20 @@ kind: instruction name: vrsub.vi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd, imm encoding: match: 000011-----------011-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vrsub.vx.yaml b/arch/inst/V/vrsub.vx.yaml index 2981fdbe07..8891c40313 100644 --- a/arch/inst/V/vrsub.vx.yaml +++ b/arch/inst/V/vrsub.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vrsub.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 000011-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vs1r.v.yaml b/arch/inst/V/vs1r.v.yaml index 16af81c2f4..766dc6573c 100644 --- a/arch/inst/V/vs1r.v.yaml +++ b/arch/inst/V/vs1r.v.yaml @@ -5,16 +5,16 @@ kind: instruction name: vs1r.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: xs1, vs3 encoding: match: 000000101000-----000-----0100111 variables: - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vs2r.v.yaml b/arch/inst/V/vs2r.v.yaml index ca01f05fd9..f9ecdeead0 100644 --- a/arch/inst/V/vs2r.v.yaml +++ b/arch/inst/V/vs2r.v.yaml @@ -5,16 +5,16 @@ kind: instruction name: vs2r.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: xs1, vs3 encoding: match: 001000101000-----000-----0100111 variables: - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vs4r.v.yaml b/arch/inst/V/vs4r.v.yaml index a035f4cc44..57fc54fa55 100644 --- a/arch/inst/V/vs4r.v.yaml +++ b/arch/inst/V/vs4r.v.yaml @@ -5,16 +5,16 @@ kind: instruction name: vs4r.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: xs1, vs3 encoding: match: 011000101000-----000-----0100111 variables: - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vs8r.v.yaml b/arch/inst/V/vs8r.v.yaml index 31126a57fe..e5c66e6179 100644 --- a/arch/inst/V/vs8r.v.yaml +++ b/arch/inst/V/vs8r.v.yaml @@ -5,16 +5,16 @@ kind: instruction name: vs8r.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: xs1, vs3 encoding: match: 111000101000-----000-----0100111 variables: - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsadd.vi.yaml b/arch/inst/V/vsadd.vi.yaml index 59d37d92d3..7a9a80e2a8 100644 --- a/arch/inst/V/vsadd.vi.yaml +++ b/arch/inst/V/vsadd.vi.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsadd.vi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd, imm encoding: match: 100001-----------011-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vsadd.vv.yaml b/arch/inst/V/vsadd.vv.yaml index 6a9e51dc6a..e1a4d0ddab 100644 --- a/arch/inst/V/vsadd.vv.yaml +++ b/arch/inst/V/vsadd.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsadd.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 100001-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW_pow = get_sew_pow(); diff --git a/arch/inst/V/vsadd.vx.yaml b/arch/inst/V/vsadd.vx.yaml index cd4d2f1f53..b4046c81ca 100644 --- a/arch/inst/V/vsadd.vx.yaml +++ b/arch/inst/V/vsadd.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsadd.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 100001-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vsaddu.vi.yaml b/arch/inst/V/vsaddu.vi.yaml index 0aac71bce9..6828c2cda1 100644 --- a/arch/inst/V/vsaddu.vi.yaml +++ b/arch/inst/V/vsaddu.vi.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsaddu.vi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd, imm encoding: match: 100000-----------011-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vsaddu.vv.yaml b/arch/inst/V/vsaddu.vv.yaml index e2514e2c75..3b75a0cb62 100644 --- a/arch/inst/V/vsaddu.vv.yaml +++ b/arch/inst/V/vsaddu.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsaddu.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 100000-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW_pow = get_sew_pow(); diff --git a/arch/inst/V/vsaddu.vx.yaml b/arch/inst/V/vsaddu.vx.yaml index 5cfbc7fc21..9806bcb733 100644 --- a/arch/inst/V/vsaddu.vx.yaml +++ b/arch/inst/V/vsaddu.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsaddu.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 100000-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vsbc.vvm.yaml b/arch/inst/V/vsbc.vvm.yaml index 646653fc54..0c3cd660e6 100644 --- a/arch/inst/V/vsbc.vvm.yaml +++ b/arch/inst/V/vsbc.vvm.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsbc.vvm long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, vs1, vd encoding: match: 0100100----------000-----1010111 variables: - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vsbc.vxm.yaml b/arch/inst/V/vsbc.vxm.yaml index f3a6fabcbe..31b5511dd8 100644 --- a/arch/inst/V/vsbc.vxm.yaml +++ b/arch/inst/V/vsbc.vxm.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsbc.vxm long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vs2, xs1, vd encoding: match: 0100100----------100-----1010111 variables: - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vse16.v.yaml b/arch/inst/V/vse16.v.yaml index 46f1bef23e..97ad5521ea 100644 --- a/arch/inst/V/vse16.v.yaml +++ b/arch/inst/V/vse16.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vse16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 000000-00000-----101-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let load_width_bytes = vlewidth_bytesnumber(width); diff --git a/arch/inst/V/vse32.v.yaml b/arch/inst/V/vse32.v.yaml index 9db60760de..45d3cd35d7 100644 --- a/arch/inst/V/vse32.v.yaml +++ b/arch/inst/V/vse32.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vse32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 000000-00000-----110-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let load_width_bytes = vlewidth_bytesnumber(width); diff --git a/arch/inst/V/vse64.v.yaml b/arch/inst/V/vse64.v.yaml index 3fbfabaedc..3b21d66e4e 100644 --- a/arch/inst/V/vse64.v.yaml +++ b/arch/inst/V/vse64.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vse64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 000000-00000-----111-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let load_width_bytes = vlewidth_bytesnumber(width); diff --git a/arch/inst/V/vse8.v.yaml b/arch/inst/V/vse8.v.yaml index b3be72b1e6..ed2eefef51 100644 --- a/arch/inst/V/vse8.v.yaml +++ b/arch/inst/V/vse8.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vse8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 000000-00000-----000-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let load_width_bytes = vlewidth_bytesnumber(width); diff --git a/arch/inst/V/vsetivli.yaml b/arch/inst/V/vsetivli.yaml index 623b27b242..e45be1043c 100644 --- a/arch/inst/V/vsetivli.yaml +++ b/arch/inst/V/vsetivli.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsetivli long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: xd, imm encoding: match: 11---------------111-----1010111 variables: - - name: zimm10 - location: 29-20 - - name: uimm - location: 19-15 - - name: rd - location: 11-7 + - name: zimm10 + location: 29-20 + - name: uimm + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let VLEN_pow = get_vlen_pow(); diff --git a/arch/inst/V/vsetvl.yaml b/arch/inst/V/vsetvl.yaml index a66a6759f4..ca13695d80 100644 --- a/arch/inst/V/vsetvl.yaml +++ b/arch/inst/V/vsetvl.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsetvl long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: xs2, xs1, xd encoding: match: 1000000----------111-----1010111 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsetvli.yaml b/arch/inst/V/vsetvli.yaml index 93995b7655..aeb3569bb7 100644 --- a/arch/inst/V/vsetvli.yaml +++ b/arch/inst/V/vsetvli.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsetvli long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: xs1, xd, imm encoding: match: 0----------------111-----1010111 variables: - - name: zimm11 - location: 30-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: zimm11 + location: 30-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let VLEN_pow = get_vlen_pow(); diff --git a/arch/inst/V/vsext.vf2.yaml b/arch/inst/V/vsext.vf2.yaml index 2a16a12022..4ad76d17f0 100644 --- a/arch/inst/V/vsext.vf2.yaml +++ b/arch/inst/V/vsext.vf2.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsext.vf2 long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010010------00111010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vsext.vf4.yaml b/arch/inst/V/vsext.vf4.yaml index 430cd84aba..008a0f6293 100644 --- a/arch/inst/V/vsext.vf4.yaml +++ b/arch/inst/V/vsext.vf4.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsext.vf4 long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010010------00101010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vsext.vf8.yaml b/arch/inst/V/vsext.vf8.yaml index 4c1c171a7d..864e4141da 100644 --- a/arch/inst/V/vsext.vf8.yaml +++ b/arch/inst/V/vsext.vf8.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsext.vf8 long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010010------00011010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vslide1down.vx.yaml b/arch/inst/V/vslide1down.vx.yaml index fdf239d02b..47ac7e37b1 100644 --- a/arch/inst/V/vslide1down.vx.yaml +++ b/arch/inst/V/vslide1down.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vslide1down.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 001111-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vslide1up.vx.yaml b/arch/inst/V/vslide1up.vx.yaml index 12201fa9da..05335c0fd6 100644 --- a/arch/inst/V/vslide1up.vx.yaml +++ b/arch/inst/V/vslide1up.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vslide1up.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 001110-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vslidedown.vi.yaml b/arch/inst/V/vslidedown.vi.yaml index 5253fa5aad..dfadb71b66 100644 --- a/arch/inst/V/vslidedown.vi.yaml +++ b/arch/inst/V/vslidedown.vi.yaml @@ -5,20 +5,20 @@ kind: instruction name: vslidedown.vi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd, imm encoding: match: 001111-----------011-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW_pow = get_sew_pow(); diff --git a/arch/inst/V/vslidedown.vx.yaml b/arch/inst/V/vslidedown.vx.yaml index ed5f7b0669..2b73f1063a 100644 --- a/arch/inst/V/vslidedown.vx.yaml +++ b/arch/inst/V/vslidedown.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vslidedown.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 001111-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW_pow = get_sew_pow(); diff --git a/arch/inst/V/vslideup.vi.yaml b/arch/inst/V/vslideup.vi.yaml index cdda8b516b..0a9ce8b467 100644 --- a/arch/inst/V/vslideup.vi.yaml +++ b/arch/inst/V/vslideup.vi.yaml @@ -5,20 +5,20 @@ kind: instruction name: vslideup.vi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd, imm encoding: match: 001110-----------011-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW_pow = get_sew_pow(); diff --git a/arch/inst/V/vslideup.vx.yaml b/arch/inst/V/vslideup.vx.yaml index 4ac68fa347..5f4df3da74 100644 --- a/arch/inst/V/vslideup.vx.yaml +++ b/arch/inst/V/vslideup.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vslideup.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 001110-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW_pow = get_sew_pow(); diff --git a/arch/inst/V/vsll.vi.yaml b/arch/inst/V/vsll.vi.yaml index 317629bf0b..bb7407f04c 100644 --- a/arch/inst/V/vsll.vi.yaml +++ b/arch/inst/V/vsll.vi.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsll.vi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd, imm encoding: match: 100101-----------011-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vsll.vv.yaml b/arch/inst/V/vsll.vv.yaml index 505eb734f7..fcf60a37d2 100644 --- a/arch/inst/V/vsll.vv.yaml +++ b/arch/inst/V/vsll.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsll.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 100101-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW_pow = get_sew_pow(); diff --git a/arch/inst/V/vsll.vx.yaml b/arch/inst/V/vsll.vx.yaml index 7f92227356..2c5f041f7d 100644 --- a/arch/inst/V/vsll.vx.yaml +++ b/arch/inst/V/vsll.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsll.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 100101-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vsm.v.yaml b/arch/inst/V/vsm.v.yaml index a50fe111d8..b8e7ace248 100644 --- a/arch/inst/V/vsm.v.yaml +++ b/arch/inst/V/vsm.v.yaml @@ -5,16 +5,16 @@ kind: instruction name: vsm.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: xs1, vs3 encoding: match: 000000101011-----000-----0100111 variables: - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always @@ -23,9 +23,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let EEW = 8; diff --git a/arch/inst/V/vsmul.vv.yaml b/arch/inst/V/vsmul.vv.yaml index 33a0955db5..856e75f824 100644 --- a/arch/inst/V/vsmul.vv.yaml +++ b/arch/inst/V/vsmul.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsmul.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 100111-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW_pow = get_sew_pow(); diff --git a/arch/inst/V/vsmul.vx.yaml b/arch/inst/V/vsmul.vx.yaml index 8d76ae1ee6..b70c9b089f 100644 --- a/arch/inst/V/vsmul.vx.yaml +++ b/arch/inst/V/vsmul.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsmul.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 100111-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vsoxei16.v.yaml b/arch/inst/V/vsoxei16.v.yaml index ded610f658..c0f6d4b0f8 100644 --- a/arch/inst/V/vsoxei16.v.yaml +++ b/arch/inst/V/vsoxei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 000011-----------101-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let EEW_index_pow = vlewidth_pow(width); diff --git a/arch/inst/V/vsoxei32.v.yaml b/arch/inst/V/vsoxei32.v.yaml index c66fc7baf3..1c14c90dbb 100644 --- a/arch/inst/V/vsoxei32.v.yaml +++ b/arch/inst/V/vsoxei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 000011-----------110-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let EEW_index_pow = vlewidth_pow(width); diff --git a/arch/inst/V/vsoxei64.v.yaml b/arch/inst/V/vsoxei64.v.yaml index 1077b0db43..f7bcf8faf4 100644 --- a/arch/inst/V/vsoxei64.v.yaml +++ b/arch/inst/V/vsoxei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 000011-----------111-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let EEW_index_pow = vlewidth_pow(width); diff --git a/arch/inst/V/vsoxei8.v.yaml b/arch/inst/V/vsoxei8.v.yaml index a45891a501..6b4107b6f6 100644 --- a/arch/inst/V/vsoxei8.v.yaml +++ b/arch/inst/V/vsoxei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 000011-----------000-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let EEW_index_pow = vlewidth_pow(width); diff --git a/arch/inst/V/vsoxseg2ei16.v.yaml b/arch/inst/V/vsoxseg2ei16.v.yaml index e86e45ad30..7809562188 100644 --- a/arch/inst/V/vsoxseg2ei16.v.yaml +++ b/arch/inst/V/vsoxseg2ei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxseg2ei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 001011-----------101-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsoxseg2ei32.v.yaml b/arch/inst/V/vsoxseg2ei32.v.yaml index 9b45cee7a7..6ffd055d24 100644 --- a/arch/inst/V/vsoxseg2ei32.v.yaml +++ b/arch/inst/V/vsoxseg2ei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxseg2ei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 001011-----------110-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsoxseg2ei64.v.yaml b/arch/inst/V/vsoxseg2ei64.v.yaml index 95f803fbf3..f11488f219 100644 --- a/arch/inst/V/vsoxseg2ei64.v.yaml +++ b/arch/inst/V/vsoxseg2ei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxseg2ei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 001011-----------111-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsoxseg2ei8.v.yaml b/arch/inst/V/vsoxseg2ei8.v.yaml index 4234761a3b..48a1b86099 100644 --- a/arch/inst/V/vsoxseg2ei8.v.yaml +++ b/arch/inst/V/vsoxseg2ei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxseg2ei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 001011-----------000-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsoxseg3ei16.v.yaml b/arch/inst/V/vsoxseg3ei16.v.yaml index fe32adab1f..89c24ecbaa 100644 --- a/arch/inst/V/vsoxseg3ei16.v.yaml +++ b/arch/inst/V/vsoxseg3ei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxseg3ei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 010011-----------101-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsoxseg3ei32.v.yaml b/arch/inst/V/vsoxseg3ei32.v.yaml index 3c66f7a410..66d2c99ad9 100644 --- a/arch/inst/V/vsoxseg3ei32.v.yaml +++ b/arch/inst/V/vsoxseg3ei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxseg3ei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 010011-----------110-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsoxseg3ei64.v.yaml b/arch/inst/V/vsoxseg3ei64.v.yaml index ca20fe8fa8..ef6dc0e5c1 100644 --- a/arch/inst/V/vsoxseg3ei64.v.yaml +++ b/arch/inst/V/vsoxseg3ei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxseg3ei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 010011-----------111-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsoxseg3ei8.v.yaml b/arch/inst/V/vsoxseg3ei8.v.yaml index 4df149f008..8b6c8c6647 100644 --- a/arch/inst/V/vsoxseg3ei8.v.yaml +++ b/arch/inst/V/vsoxseg3ei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxseg3ei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 010011-----------000-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsoxseg4ei16.v.yaml b/arch/inst/V/vsoxseg4ei16.v.yaml index 9a386ba92f..9342ab0538 100644 --- a/arch/inst/V/vsoxseg4ei16.v.yaml +++ b/arch/inst/V/vsoxseg4ei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxseg4ei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 011011-----------101-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsoxseg4ei32.v.yaml b/arch/inst/V/vsoxseg4ei32.v.yaml index 9bf3d9447e..dca2a2629a 100644 --- a/arch/inst/V/vsoxseg4ei32.v.yaml +++ b/arch/inst/V/vsoxseg4ei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxseg4ei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 011011-----------110-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsoxseg4ei64.v.yaml b/arch/inst/V/vsoxseg4ei64.v.yaml index 0b1d62d811..d2194a5942 100644 --- a/arch/inst/V/vsoxseg4ei64.v.yaml +++ b/arch/inst/V/vsoxseg4ei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxseg4ei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 011011-----------111-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsoxseg4ei8.v.yaml b/arch/inst/V/vsoxseg4ei8.v.yaml index 078aa7a6c7..81cfe37fff 100644 --- a/arch/inst/V/vsoxseg4ei8.v.yaml +++ b/arch/inst/V/vsoxseg4ei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxseg4ei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 011011-----------000-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsoxseg5ei16.v.yaml b/arch/inst/V/vsoxseg5ei16.v.yaml index 182b82153e..f02483e2c2 100644 --- a/arch/inst/V/vsoxseg5ei16.v.yaml +++ b/arch/inst/V/vsoxseg5ei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxseg5ei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 100011-----------101-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsoxseg5ei32.v.yaml b/arch/inst/V/vsoxseg5ei32.v.yaml index 865cd68d7c..7024201e5e 100644 --- a/arch/inst/V/vsoxseg5ei32.v.yaml +++ b/arch/inst/V/vsoxseg5ei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxseg5ei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 100011-----------110-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsoxseg5ei64.v.yaml b/arch/inst/V/vsoxseg5ei64.v.yaml index ba7330e7b7..1aeac72616 100644 --- a/arch/inst/V/vsoxseg5ei64.v.yaml +++ b/arch/inst/V/vsoxseg5ei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxseg5ei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 100011-----------111-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsoxseg5ei8.v.yaml b/arch/inst/V/vsoxseg5ei8.v.yaml index 85dcb2bb9e..dd72f35f7e 100644 --- a/arch/inst/V/vsoxseg5ei8.v.yaml +++ b/arch/inst/V/vsoxseg5ei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxseg5ei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 100011-----------000-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsoxseg6ei16.v.yaml b/arch/inst/V/vsoxseg6ei16.v.yaml index 6a4630a843..859d840d24 100644 --- a/arch/inst/V/vsoxseg6ei16.v.yaml +++ b/arch/inst/V/vsoxseg6ei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxseg6ei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 101011-----------101-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsoxseg6ei32.v.yaml b/arch/inst/V/vsoxseg6ei32.v.yaml index 1ff23a1325..21ab89a246 100644 --- a/arch/inst/V/vsoxseg6ei32.v.yaml +++ b/arch/inst/V/vsoxseg6ei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxseg6ei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 101011-----------110-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsoxseg6ei64.v.yaml b/arch/inst/V/vsoxseg6ei64.v.yaml index 3ccbd64506..e3128fde82 100644 --- a/arch/inst/V/vsoxseg6ei64.v.yaml +++ b/arch/inst/V/vsoxseg6ei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxseg6ei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 101011-----------111-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsoxseg6ei8.v.yaml b/arch/inst/V/vsoxseg6ei8.v.yaml index a40cae05f9..a76414ef0c 100644 --- a/arch/inst/V/vsoxseg6ei8.v.yaml +++ b/arch/inst/V/vsoxseg6ei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxseg6ei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 101011-----------000-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsoxseg7ei16.v.yaml b/arch/inst/V/vsoxseg7ei16.v.yaml index f6378ac9ce..6b1ea51f0c 100644 --- a/arch/inst/V/vsoxseg7ei16.v.yaml +++ b/arch/inst/V/vsoxseg7ei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxseg7ei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 110011-----------101-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsoxseg7ei32.v.yaml b/arch/inst/V/vsoxseg7ei32.v.yaml index 3359414cda..aa95e5612a 100644 --- a/arch/inst/V/vsoxseg7ei32.v.yaml +++ b/arch/inst/V/vsoxseg7ei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxseg7ei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 110011-----------110-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsoxseg7ei64.v.yaml b/arch/inst/V/vsoxseg7ei64.v.yaml index c92e974315..0d123c019d 100644 --- a/arch/inst/V/vsoxseg7ei64.v.yaml +++ b/arch/inst/V/vsoxseg7ei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxseg7ei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 110011-----------111-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsoxseg7ei8.v.yaml b/arch/inst/V/vsoxseg7ei8.v.yaml index 8be28249c4..61ec4b9eb2 100644 --- a/arch/inst/V/vsoxseg7ei8.v.yaml +++ b/arch/inst/V/vsoxseg7ei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxseg7ei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 110011-----------000-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsoxseg8ei16.v.yaml b/arch/inst/V/vsoxseg8ei16.v.yaml index 7231e6accb..8ad68b5037 100644 --- a/arch/inst/V/vsoxseg8ei16.v.yaml +++ b/arch/inst/V/vsoxseg8ei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxseg8ei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 111011-----------101-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsoxseg8ei32.v.yaml b/arch/inst/V/vsoxseg8ei32.v.yaml index f1b306a0f8..1f9e8ff9f0 100644 --- a/arch/inst/V/vsoxseg8ei32.v.yaml +++ b/arch/inst/V/vsoxseg8ei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxseg8ei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 111011-----------110-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsoxseg8ei64.v.yaml b/arch/inst/V/vsoxseg8ei64.v.yaml index 71e1e6404e..033e7583e1 100644 --- a/arch/inst/V/vsoxseg8ei64.v.yaml +++ b/arch/inst/V/vsoxseg8ei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxseg8ei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 111011-----------111-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsoxseg8ei8.v.yaml b/arch/inst/V/vsoxseg8ei8.v.yaml index f2ae507256..11b3bf923e 100644 --- a/arch/inst/V/vsoxseg8ei8.v.yaml +++ b/arch/inst/V/vsoxseg8ei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsoxseg8ei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 111011-----------000-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsra.vi.yaml b/arch/inst/V/vsra.vi.yaml index 794126b651..077d49bfca 100644 --- a/arch/inst/V/vsra.vi.yaml +++ b/arch/inst/V/vsra.vi.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsra.vi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd, imm encoding: match: 101001-----------011-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vsra.vv.yaml b/arch/inst/V/vsra.vv.yaml index 961684129f..b46265e903 100644 --- a/arch/inst/V/vsra.vv.yaml +++ b/arch/inst/V/vsra.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsra.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 101001-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW_pow = get_sew_pow(); diff --git a/arch/inst/V/vsra.vx.yaml b/arch/inst/V/vsra.vx.yaml index ce374fd8dc..405ab82cfa 100644 --- a/arch/inst/V/vsra.vx.yaml +++ b/arch/inst/V/vsra.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsra.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 101001-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vsrl.vi.yaml b/arch/inst/V/vsrl.vi.yaml index a3186c341e..acdfbc9861 100644 --- a/arch/inst/V/vsrl.vi.yaml +++ b/arch/inst/V/vsrl.vi.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsrl.vi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd, imm encoding: match: 101000-----------011-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vsrl.vv.yaml b/arch/inst/V/vsrl.vv.yaml index 9ab40d6447..a458251a6d 100644 --- a/arch/inst/V/vsrl.vv.yaml +++ b/arch/inst/V/vsrl.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsrl.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 101000-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW_pow = get_sew_pow(); diff --git a/arch/inst/V/vsrl.vx.yaml b/arch/inst/V/vsrl.vx.yaml index dc0fc032f8..33400a4b96 100644 --- a/arch/inst/V/vsrl.vx.yaml +++ b/arch/inst/V/vsrl.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsrl.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 101000-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vsse16.v.yaml b/arch/inst/V/vsse16.v.yaml index 2bfe4dcd69..554f3cbad0 100644 --- a/arch/inst/V/vsse16.v.yaml +++ b/arch/inst/V/vsse16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsse16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 000010-----------101-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let load_width_bytes = vlewidth_bytesnumber(width); diff --git a/arch/inst/V/vsse32.v.yaml b/arch/inst/V/vsse32.v.yaml index 3f543d07eb..790271b4e9 100644 --- a/arch/inst/V/vsse32.v.yaml +++ b/arch/inst/V/vsse32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsse32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 000010-----------110-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let load_width_bytes = vlewidth_bytesnumber(width); diff --git a/arch/inst/V/vsse64.v.yaml b/arch/inst/V/vsse64.v.yaml index dbfba21610..65301a84b8 100644 --- a/arch/inst/V/vsse64.v.yaml +++ b/arch/inst/V/vsse64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsse64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 000010-----------111-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let load_width_bytes = vlewidth_bytesnumber(width); diff --git a/arch/inst/V/vsse8.v.yaml b/arch/inst/V/vsse8.v.yaml index 66257c58e0..3dad5795d9 100644 --- a/arch/inst/V/vsse8.v.yaml +++ b/arch/inst/V/vsse8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsse8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 000010-----------000-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let load_width_bytes = vlewidth_bytesnumber(width); diff --git a/arch/inst/V/vsseg2e16.v.yaml b/arch/inst/V/vsseg2e16.v.yaml index cd4e5be9da..7f3b2e3d30 100644 --- a/arch/inst/V/vsseg2e16.v.yaml +++ b/arch/inst/V/vsseg2e16.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsseg2e16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 001000-00000-----101-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsseg2e32.v.yaml b/arch/inst/V/vsseg2e32.v.yaml index 601e3b9944..96e79cf763 100644 --- a/arch/inst/V/vsseg2e32.v.yaml +++ b/arch/inst/V/vsseg2e32.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsseg2e32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 001000-00000-----110-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsseg2e64.v.yaml b/arch/inst/V/vsseg2e64.v.yaml index 62ed3f80d3..fb88709c7d 100644 --- a/arch/inst/V/vsseg2e64.v.yaml +++ b/arch/inst/V/vsseg2e64.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsseg2e64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 001000-00000-----111-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsseg2e8.v.yaml b/arch/inst/V/vsseg2e8.v.yaml index e66d94ecb4..88d987cee6 100644 --- a/arch/inst/V/vsseg2e8.v.yaml +++ b/arch/inst/V/vsseg2e8.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsseg2e8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 001000-00000-----000-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsseg3e16.v.yaml b/arch/inst/V/vsseg3e16.v.yaml index ffde8ab7e8..6ad7927583 100644 --- a/arch/inst/V/vsseg3e16.v.yaml +++ b/arch/inst/V/vsseg3e16.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsseg3e16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 010000-00000-----101-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsseg3e32.v.yaml b/arch/inst/V/vsseg3e32.v.yaml index 68e204cc68..7f5036f7d6 100644 --- a/arch/inst/V/vsseg3e32.v.yaml +++ b/arch/inst/V/vsseg3e32.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsseg3e32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 010000-00000-----110-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsseg3e64.v.yaml b/arch/inst/V/vsseg3e64.v.yaml index f32e623f2b..6e0821debc 100644 --- a/arch/inst/V/vsseg3e64.v.yaml +++ b/arch/inst/V/vsseg3e64.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsseg3e64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 010000-00000-----111-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsseg3e8.v.yaml b/arch/inst/V/vsseg3e8.v.yaml index 4816d14c4e..314c55bd89 100644 --- a/arch/inst/V/vsseg3e8.v.yaml +++ b/arch/inst/V/vsseg3e8.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsseg3e8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 010000-00000-----000-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsseg4e16.v.yaml b/arch/inst/V/vsseg4e16.v.yaml index 538a9b67df..b319f4e46c 100644 --- a/arch/inst/V/vsseg4e16.v.yaml +++ b/arch/inst/V/vsseg4e16.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsseg4e16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 011000-00000-----101-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsseg4e32.v.yaml b/arch/inst/V/vsseg4e32.v.yaml index 41b149778a..80f857393a 100644 --- a/arch/inst/V/vsseg4e32.v.yaml +++ b/arch/inst/V/vsseg4e32.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsseg4e32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 011000-00000-----110-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsseg4e64.v.yaml b/arch/inst/V/vsseg4e64.v.yaml index 6203e10869..4e3ba8c295 100644 --- a/arch/inst/V/vsseg4e64.v.yaml +++ b/arch/inst/V/vsseg4e64.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsseg4e64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 011000-00000-----111-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsseg4e8.v.yaml b/arch/inst/V/vsseg4e8.v.yaml index 2514dfdbed..b8eb7e45be 100644 --- a/arch/inst/V/vsseg4e8.v.yaml +++ b/arch/inst/V/vsseg4e8.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsseg4e8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 011000-00000-----000-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsseg5e16.v.yaml b/arch/inst/V/vsseg5e16.v.yaml index 100f59fbfa..d7a4f68e5d 100644 --- a/arch/inst/V/vsseg5e16.v.yaml +++ b/arch/inst/V/vsseg5e16.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsseg5e16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 100000-00000-----101-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsseg5e32.v.yaml b/arch/inst/V/vsseg5e32.v.yaml index ad3a2cb19f..3d3158a213 100644 --- a/arch/inst/V/vsseg5e32.v.yaml +++ b/arch/inst/V/vsseg5e32.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsseg5e32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 100000-00000-----110-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsseg5e64.v.yaml b/arch/inst/V/vsseg5e64.v.yaml index ff071f25cf..13a817a588 100644 --- a/arch/inst/V/vsseg5e64.v.yaml +++ b/arch/inst/V/vsseg5e64.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsseg5e64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 100000-00000-----111-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsseg5e8.v.yaml b/arch/inst/V/vsseg5e8.v.yaml index fda9c36a02..73be346340 100644 --- a/arch/inst/V/vsseg5e8.v.yaml +++ b/arch/inst/V/vsseg5e8.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsseg5e8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 100000-00000-----000-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsseg6e16.v.yaml b/arch/inst/V/vsseg6e16.v.yaml index 4b2e5983e5..d0780baf2a 100644 --- a/arch/inst/V/vsseg6e16.v.yaml +++ b/arch/inst/V/vsseg6e16.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsseg6e16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 101000-00000-----101-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsseg6e32.v.yaml b/arch/inst/V/vsseg6e32.v.yaml index 1d08c1db38..54d50abbd1 100644 --- a/arch/inst/V/vsseg6e32.v.yaml +++ b/arch/inst/V/vsseg6e32.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsseg6e32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 101000-00000-----110-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsseg6e64.v.yaml b/arch/inst/V/vsseg6e64.v.yaml index a267cb199a..f6f5dfde56 100644 --- a/arch/inst/V/vsseg6e64.v.yaml +++ b/arch/inst/V/vsseg6e64.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsseg6e64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 101000-00000-----111-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsseg6e8.v.yaml b/arch/inst/V/vsseg6e8.v.yaml index b5e3a702de..5d0c35b2d0 100644 --- a/arch/inst/V/vsseg6e8.v.yaml +++ b/arch/inst/V/vsseg6e8.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsseg6e8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 101000-00000-----000-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsseg7e16.v.yaml b/arch/inst/V/vsseg7e16.v.yaml index e0220080a5..2a5443f0b2 100644 --- a/arch/inst/V/vsseg7e16.v.yaml +++ b/arch/inst/V/vsseg7e16.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsseg7e16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 110000-00000-----101-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsseg7e32.v.yaml b/arch/inst/V/vsseg7e32.v.yaml index 3a6a885287..e23b7ea0a9 100644 --- a/arch/inst/V/vsseg7e32.v.yaml +++ b/arch/inst/V/vsseg7e32.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsseg7e32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 110000-00000-----110-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsseg7e64.v.yaml b/arch/inst/V/vsseg7e64.v.yaml index b2935f7d66..23afb696c8 100644 --- a/arch/inst/V/vsseg7e64.v.yaml +++ b/arch/inst/V/vsseg7e64.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsseg7e64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 110000-00000-----111-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsseg7e8.v.yaml b/arch/inst/V/vsseg7e8.v.yaml index 1851b32c22..8484d868c6 100644 --- a/arch/inst/V/vsseg7e8.v.yaml +++ b/arch/inst/V/vsseg7e8.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsseg7e8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 110000-00000-----000-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsseg8e16.v.yaml b/arch/inst/V/vsseg8e16.v.yaml index 65e45fad95..f0d0524532 100644 --- a/arch/inst/V/vsseg8e16.v.yaml +++ b/arch/inst/V/vsseg8e16.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsseg8e16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 111000-00000-----101-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsseg8e32.v.yaml b/arch/inst/V/vsseg8e32.v.yaml index 46bc8e9c73..ad61206dd6 100644 --- a/arch/inst/V/vsseg8e32.v.yaml +++ b/arch/inst/V/vsseg8e32.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsseg8e32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 111000-00000-----110-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsseg8e64.v.yaml b/arch/inst/V/vsseg8e64.v.yaml index 736480a8cc..fcfed3d012 100644 --- a/arch/inst/V/vsseg8e64.v.yaml +++ b/arch/inst/V/vsseg8e64.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsseg8e64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 111000-00000-----111-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsseg8e8.v.yaml b/arch/inst/V/vsseg8e8.v.yaml index 3903f33c79..4b0f9d1061 100644 --- a/arch/inst/V/vsseg8e8.v.yaml +++ b/arch/inst/V/vsseg8e8.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vsseg8e8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs1, vs3 encoding: match: 111000-00000-----000-----0100111 variables: - - name: vm - location: 25-25 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vssra.vi.yaml b/arch/inst/V/vssra.vi.yaml index d89c9d999e..e3fce2d3b8 100644 --- a/arch/inst/V/vssra.vi.yaml +++ b/arch/inst/V/vssra.vi.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssra.vi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd, imm encoding: match: 101011-----------011-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vssra.vv.yaml b/arch/inst/V/vssra.vv.yaml index 7b8f6aa474..72f82eea9c 100644 --- a/arch/inst/V/vssra.vv.yaml +++ b/arch/inst/V/vssra.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssra.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 101011-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW_pow = get_sew_pow(); diff --git a/arch/inst/V/vssra.vx.yaml b/arch/inst/V/vssra.vx.yaml index 24f3e58212..33f3cd692c 100644 --- a/arch/inst/V/vssra.vx.yaml +++ b/arch/inst/V/vssra.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssra.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 101011-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vssrl.vi.yaml b/arch/inst/V/vssrl.vi.yaml index c763b4663e..49ed2325db 100644 --- a/arch/inst/V/vssrl.vi.yaml +++ b/arch/inst/V/vssrl.vi.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssrl.vi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd, imm encoding: match: 101010-----------011-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vssrl.vv.yaml b/arch/inst/V/vssrl.vv.yaml index abc1547ff7..6538af90aa 100644 --- a/arch/inst/V/vssrl.vv.yaml +++ b/arch/inst/V/vssrl.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssrl.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 101010-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW_pow = get_sew_pow(); diff --git a/arch/inst/V/vssrl.vx.yaml b/arch/inst/V/vssrl.vx.yaml index b5f8e4d92d..e5ef085721 100644 --- a/arch/inst/V/vssrl.vx.yaml +++ b/arch/inst/V/vssrl.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssrl.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 101010-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vssseg2e16.v.yaml b/arch/inst/V/vssseg2e16.v.yaml index 66ef1a90a7..ae2407c8c4 100644 --- a/arch/inst/V/vssseg2e16.v.yaml +++ b/arch/inst/V/vssseg2e16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssseg2e16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 001010-----------101-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vssseg2e32.v.yaml b/arch/inst/V/vssseg2e32.v.yaml index e562929f30..7c2a264b88 100644 --- a/arch/inst/V/vssseg2e32.v.yaml +++ b/arch/inst/V/vssseg2e32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssseg2e32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 001010-----------110-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vssseg2e64.v.yaml b/arch/inst/V/vssseg2e64.v.yaml index a6914aa38e..24379b0d86 100644 --- a/arch/inst/V/vssseg2e64.v.yaml +++ b/arch/inst/V/vssseg2e64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssseg2e64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 001010-----------111-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vssseg2e8.v.yaml b/arch/inst/V/vssseg2e8.v.yaml index 8f70c16480..17159a08ca 100644 --- a/arch/inst/V/vssseg2e8.v.yaml +++ b/arch/inst/V/vssseg2e8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssseg2e8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 001010-----------000-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vssseg3e16.v.yaml b/arch/inst/V/vssseg3e16.v.yaml index 94d3a04196..911a9e9871 100644 --- a/arch/inst/V/vssseg3e16.v.yaml +++ b/arch/inst/V/vssseg3e16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssseg3e16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 010010-----------101-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vssseg3e32.v.yaml b/arch/inst/V/vssseg3e32.v.yaml index 16a6827d1d..8f6b42e64c 100644 --- a/arch/inst/V/vssseg3e32.v.yaml +++ b/arch/inst/V/vssseg3e32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssseg3e32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 010010-----------110-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vssseg3e64.v.yaml b/arch/inst/V/vssseg3e64.v.yaml index 2808af060c..0acc823362 100644 --- a/arch/inst/V/vssseg3e64.v.yaml +++ b/arch/inst/V/vssseg3e64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssseg3e64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 010010-----------111-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vssseg3e8.v.yaml b/arch/inst/V/vssseg3e8.v.yaml index 0a19eeefd5..8bf8e51515 100644 --- a/arch/inst/V/vssseg3e8.v.yaml +++ b/arch/inst/V/vssseg3e8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssseg3e8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 010010-----------000-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vssseg4e16.v.yaml b/arch/inst/V/vssseg4e16.v.yaml index 01bce54ccf..5c44fa0856 100644 --- a/arch/inst/V/vssseg4e16.v.yaml +++ b/arch/inst/V/vssseg4e16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssseg4e16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 011010-----------101-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vssseg4e32.v.yaml b/arch/inst/V/vssseg4e32.v.yaml index f506f43e24..55a124d851 100644 --- a/arch/inst/V/vssseg4e32.v.yaml +++ b/arch/inst/V/vssseg4e32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssseg4e32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 011010-----------110-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vssseg4e64.v.yaml b/arch/inst/V/vssseg4e64.v.yaml index f4206f314d..18d38c2000 100644 --- a/arch/inst/V/vssseg4e64.v.yaml +++ b/arch/inst/V/vssseg4e64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssseg4e64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 011010-----------111-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vssseg4e8.v.yaml b/arch/inst/V/vssseg4e8.v.yaml index ca7215e3b1..d8f5bd9918 100644 --- a/arch/inst/V/vssseg4e8.v.yaml +++ b/arch/inst/V/vssseg4e8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssseg4e8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 011010-----------000-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vssseg5e16.v.yaml b/arch/inst/V/vssseg5e16.v.yaml index 8762c52abf..8da14d4385 100644 --- a/arch/inst/V/vssseg5e16.v.yaml +++ b/arch/inst/V/vssseg5e16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssseg5e16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 100010-----------101-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vssseg5e32.v.yaml b/arch/inst/V/vssseg5e32.v.yaml index 973965755b..21934526bb 100644 --- a/arch/inst/V/vssseg5e32.v.yaml +++ b/arch/inst/V/vssseg5e32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssseg5e32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 100010-----------110-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vssseg5e64.v.yaml b/arch/inst/V/vssseg5e64.v.yaml index 043883ad7b..0448d2752f 100644 --- a/arch/inst/V/vssseg5e64.v.yaml +++ b/arch/inst/V/vssseg5e64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssseg5e64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 100010-----------111-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vssseg5e8.v.yaml b/arch/inst/V/vssseg5e8.v.yaml index 2897b4d342..03ba844dcd 100644 --- a/arch/inst/V/vssseg5e8.v.yaml +++ b/arch/inst/V/vssseg5e8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssseg5e8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 100010-----------000-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vssseg6e16.v.yaml b/arch/inst/V/vssseg6e16.v.yaml index b28278b126..dc7bf73f63 100644 --- a/arch/inst/V/vssseg6e16.v.yaml +++ b/arch/inst/V/vssseg6e16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssseg6e16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 101010-----------101-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vssseg6e32.v.yaml b/arch/inst/V/vssseg6e32.v.yaml index 81bceee89b..42756c8803 100644 --- a/arch/inst/V/vssseg6e32.v.yaml +++ b/arch/inst/V/vssseg6e32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssseg6e32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 101010-----------110-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vssseg6e64.v.yaml b/arch/inst/V/vssseg6e64.v.yaml index aa96b349b1..070db45242 100644 --- a/arch/inst/V/vssseg6e64.v.yaml +++ b/arch/inst/V/vssseg6e64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssseg6e64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 101010-----------111-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vssseg6e8.v.yaml b/arch/inst/V/vssseg6e8.v.yaml index 893688b919..5cd66336de 100644 --- a/arch/inst/V/vssseg6e8.v.yaml +++ b/arch/inst/V/vssseg6e8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssseg6e8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 101010-----------000-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vssseg7e16.v.yaml b/arch/inst/V/vssseg7e16.v.yaml index 4a29f6b368..04ac66fa5e 100644 --- a/arch/inst/V/vssseg7e16.v.yaml +++ b/arch/inst/V/vssseg7e16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssseg7e16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 110010-----------101-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vssseg7e32.v.yaml b/arch/inst/V/vssseg7e32.v.yaml index 9a1c17897f..0e287ce0e8 100644 --- a/arch/inst/V/vssseg7e32.v.yaml +++ b/arch/inst/V/vssseg7e32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssseg7e32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 110010-----------110-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vssseg7e64.v.yaml b/arch/inst/V/vssseg7e64.v.yaml index 682f8ed2ba..06affd3f70 100644 --- a/arch/inst/V/vssseg7e64.v.yaml +++ b/arch/inst/V/vssseg7e64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssseg7e64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 110010-----------111-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vssseg7e8.v.yaml b/arch/inst/V/vssseg7e8.v.yaml index 5be77062c2..83a7070005 100644 --- a/arch/inst/V/vssseg7e8.v.yaml +++ b/arch/inst/V/vssseg7e8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssseg7e8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 110010-----------000-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vssseg8e16.v.yaml b/arch/inst/V/vssseg8e16.v.yaml index bd3acecbbb..72077a6016 100644 --- a/arch/inst/V/vssseg8e16.v.yaml +++ b/arch/inst/V/vssseg8e16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssseg8e16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 111010-----------101-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vssseg8e32.v.yaml b/arch/inst/V/vssseg8e32.v.yaml index 3e43ac8e46..aeeee12b3d 100644 --- a/arch/inst/V/vssseg8e32.v.yaml +++ b/arch/inst/V/vssseg8e32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssseg8e32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 111010-----------110-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vssseg8e64.v.yaml b/arch/inst/V/vssseg8e64.v.yaml index ce587b8a63..1876cf425c 100644 --- a/arch/inst/V/vssseg8e64.v.yaml +++ b/arch/inst/V/vssseg8e64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssseg8e64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 111010-----------111-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vssseg8e8.v.yaml b/arch/inst/V/vssseg8e8.v.yaml index 733f17a9c2..a093b5e0e7 100644 --- a/arch/inst/V/vssseg8e8.v.yaml +++ b/arch/inst/V/vssseg8e8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssseg8e8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, xs2, xs1, vs3 encoding: match: 111010-----------000-----0100111 variables: - - name: vm - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vssub.vv.yaml b/arch/inst/V/vssub.vv.yaml index fe57f480c5..582595e089 100644 --- a/arch/inst/V/vssub.vv.yaml +++ b/arch/inst/V/vssub.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssub.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 100011-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW_pow = get_sew_pow(); diff --git a/arch/inst/V/vssub.vx.yaml b/arch/inst/V/vssub.vx.yaml index ea715dcbd5..e9aa1eafae 100644 --- a/arch/inst/V/vssub.vx.yaml +++ b/arch/inst/V/vssub.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssub.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 100011-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vssubu.vv.yaml b/arch/inst/V/vssubu.vv.yaml index d74a1bbd0f..52630eedee 100644 --- a/arch/inst/V/vssubu.vv.yaml +++ b/arch/inst/V/vssubu.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssubu.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 100010-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW_pow = get_sew_pow(); diff --git a/arch/inst/V/vssubu.vx.yaml b/arch/inst/V/vssubu.vx.yaml index b810030a69..cfd69dcebd 100644 --- a/arch/inst/V/vssubu.vx.yaml +++ b/arch/inst/V/vssubu.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vssubu.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 100010-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vsub.vv.yaml b/arch/inst/V/vsub.vv.yaml index 9df0336ee5..090a043565 100644 --- a/arch/inst/V/vsub.vv.yaml +++ b/arch/inst/V/vsub.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsub.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 000010-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW_pow = get_sew_pow(); diff --git a/arch/inst/V/vsub.vx.yaml b/arch/inst/V/vsub.vx.yaml index 64b3190444..14f33d6aeb 100644 --- a/arch/inst/V/vsub.vx.yaml +++ b/arch/inst/V/vsub.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsub.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 000010-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vsuxei16.v.yaml b/arch/inst/V/vsuxei16.v.yaml index 11de9a7e33..ac763081b0 100644 --- a/arch/inst/V/vsuxei16.v.yaml +++ b/arch/inst/V/vsuxei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 000001-----------101-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let EEW_index_pow = vlewidth_pow(width); diff --git a/arch/inst/V/vsuxei32.v.yaml b/arch/inst/V/vsuxei32.v.yaml index 8e2587fa38..5620ea6e02 100644 --- a/arch/inst/V/vsuxei32.v.yaml +++ b/arch/inst/V/vsuxei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 000001-----------110-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let EEW_index_pow = vlewidth_pow(width); diff --git a/arch/inst/V/vsuxei64.v.yaml b/arch/inst/V/vsuxei64.v.yaml index 690030d766..7a415e73c7 100644 --- a/arch/inst/V/vsuxei64.v.yaml +++ b/arch/inst/V/vsuxei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 000001-----------111-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let EEW_index_pow = vlewidth_pow(width); diff --git a/arch/inst/V/vsuxei8.v.yaml b/arch/inst/V/vsuxei8.v.yaml index 26fd5fd07a..24aa20685b 100644 --- a/arch/inst/V/vsuxei8.v.yaml +++ b/arch/inst/V/vsuxei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 000001-----------000-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let EEW_index_pow = vlewidth_pow(width); diff --git a/arch/inst/V/vsuxseg2ei16.v.yaml b/arch/inst/V/vsuxseg2ei16.v.yaml index c6dd0cc861..959db0af07 100644 --- a/arch/inst/V/vsuxseg2ei16.v.yaml +++ b/arch/inst/V/vsuxseg2ei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxseg2ei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 001001-----------101-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsuxseg2ei32.v.yaml b/arch/inst/V/vsuxseg2ei32.v.yaml index 29c9586941..41b9fb84dd 100644 --- a/arch/inst/V/vsuxseg2ei32.v.yaml +++ b/arch/inst/V/vsuxseg2ei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxseg2ei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 001001-----------110-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsuxseg2ei64.v.yaml b/arch/inst/V/vsuxseg2ei64.v.yaml index 1004b04004..34a918de57 100644 --- a/arch/inst/V/vsuxseg2ei64.v.yaml +++ b/arch/inst/V/vsuxseg2ei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxseg2ei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 001001-----------111-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsuxseg2ei8.v.yaml b/arch/inst/V/vsuxseg2ei8.v.yaml index d17af839eb..a43b5fc914 100644 --- a/arch/inst/V/vsuxseg2ei8.v.yaml +++ b/arch/inst/V/vsuxseg2ei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxseg2ei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 001001-----------000-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsuxseg3ei16.v.yaml b/arch/inst/V/vsuxseg3ei16.v.yaml index f996907a8b..18575b61ae 100644 --- a/arch/inst/V/vsuxseg3ei16.v.yaml +++ b/arch/inst/V/vsuxseg3ei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxseg3ei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 010001-----------101-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsuxseg3ei32.v.yaml b/arch/inst/V/vsuxseg3ei32.v.yaml index fa693dce22..ee3e9934b0 100644 --- a/arch/inst/V/vsuxseg3ei32.v.yaml +++ b/arch/inst/V/vsuxseg3ei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxseg3ei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 010001-----------110-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsuxseg3ei64.v.yaml b/arch/inst/V/vsuxseg3ei64.v.yaml index 9402fb997a..beb4804d5f 100644 --- a/arch/inst/V/vsuxseg3ei64.v.yaml +++ b/arch/inst/V/vsuxseg3ei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxseg3ei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 010001-----------111-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsuxseg3ei8.v.yaml b/arch/inst/V/vsuxseg3ei8.v.yaml index a6df381933..5715a5bb7c 100644 --- a/arch/inst/V/vsuxseg3ei8.v.yaml +++ b/arch/inst/V/vsuxseg3ei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxseg3ei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 010001-----------000-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsuxseg4ei16.v.yaml b/arch/inst/V/vsuxseg4ei16.v.yaml index bf4d87142a..4740814c93 100644 --- a/arch/inst/V/vsuxseg4ei16.v.yaml +++ b/arch/inst/V/vsuxseg4ei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxseg4ei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 011001-----------101-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsuxseg4ei32.v.yaml b/arch/inst/V/vsuxseg4ei32.v.yaml index c730eff6c0..09b1d93ef7 100644 --- a/arch/inst/V/vsuxseg4ei32.v.yaml +++ b/arch/inst/V/vsuxseg4ei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxseg4ei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 011001-----------110-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsuxseg4ei64.v.yaml b/arch/inst/V/vsuxseg4ei64.v.yaml index c263a3317e..661bd38f9e 100644 --- a/arch/inst/V/vsuxseg4ei64.v.yaml +++ b/arch/inst/V/vsuxseg4ei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxseg4ei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 011001-----------111-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsuxseg4ei8.v.yaml b/arch/inst/V/vsuxseg4ei8.v.yaml index 64bbffc451..d6974e55e1 100644 --- a/arch/inst/V/vsuxseg4ei8.v.yaml +++ b/arch/inst/V/vsuxseg4ei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxseg4ei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 011001-----------000-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsuxseg5ei16.v.yaml b/arch/inst/V/vsuxseg5ei16.v.yaml index 6b7ac97eac..784d597469 100644 --- a/arch/inst/V/vsuxseg5ei16.v.yaml +++ b/arch/inst/V/vsuxseg5ei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxseg5ei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 100001-----------101-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsuxseg5ei32.v.yaml b/arch/inst/V/vsuxseg5ei32.v.yaml index a5afbb5972..272af17c6d 100644 --- a/arch/inst/V/vsuxseg5ei32.v.yaml +++ b/arch/inst/V/vsuxseg5ei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxseg5ei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 100001-----------110-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsuxseg5ei64.v.yaml b/arch/inst/V/vsuxseg5ei64.v.yaml index a4c7a1e509..8486d9474a 100644 --- a/arch/inst/V/vsuxseg5ei64.v.yaml +++ b/arch/inst/V/vsuxseg5ei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxseg5ei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 100001-----------111-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsuxseg5ei8.v.yaml b/arch/inst/V/vsuxseg5ei8.v.yaml index 4e3fa113bc..de77fb9d12 100644 --- a/arch/inst/V/vsuxseg5ei8.v.yaml +++ b/arch/inst/V/vsuxseg5ei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxseg5ei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 100001-----------000-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsuxseg6ei16.v.yaml b/arch/inst/V/vsuxseg6ei16.v.yaml index 480cefc65f..91141cc28e 100644 --- a/arch/inst/V/vsuxseg6ei16.v.yaml +++ b/arch/inst/V/vsuxseg6ei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxseg6ei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 101001-----------101-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsuxseg6ei32.v.yaml b/arch/inst/V/vsuxseg6ei32.v.yaml index f504d7402b..60137b99b2 100644 --- a/arch/inst/V/vsuxseg6ei32.v.yaml +++ b/arch/inst/V/vsuxseg6ei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxseg6ei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 101001-----------110-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsuxseg6ei64.v.yaml b/arch/inst/V/vsuxseg6ei64.v.yaml index 3dc2a966e8..ca3498a891 100644 --- a/arch/inst/V/vsuxseg6ei64.v.yaml +++ b/arch/inst/V/vsuxseg6ei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxseg6ei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 101001-----------111-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsuxseg6ei8.v.yaml b/arch/inst/V/vsuxseg6ei8.v.yaml index 2755d986b5..1603d9766c 100644 --- a/arch/inst/V/vsuxseg6ei8.v.yaml +++ b/arch/inst/V/vsuxseg6ei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxseg6ei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 101001-----------000-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsuxseg7ei16.v.yaml b/arch/inst/V/vsuxseg7ei16.v.yaml index b741b04f40..d6054b94b1 100644 --- a/arch/inst/V/vsuxseg7ei16.v.yaml +++ b/arch/inst/V/vsuxseg7ei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxseg7ei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 110001-----------101-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsuxseg7ei32.v.yaml b/arch/inst/V/vsuxseg7ei32.v.yaml index 49ae744ff3..ec5a1165ec 100644 --- a/arch/inst/V/vsuxseg7ei32.v.yaml +++ b/arch/inst/V/vsuxseg7ei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxseg7ei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 110001-----------110-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsuxseg7ei64.v.yaml b/arch/inst/V/vsuxseg7ei64.v.yaml index eb7b21ba38..93b940bfa3 100644 --- a/arch/inst/V/vsuxseg7ei64.v.yaml +++ b/arch/inst/V/vsuxseg7ei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxseg7ei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 110001-----------111-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsuxseg7ei8.v.yaml b/arch/inst/V/vsuxseg7ei8.v.yaml index dd52ac3d75..4f59f1ac9e 100644 --- a/arch/inst/V/vsuxseg7ei8.v.yaml +++ b/arch/inst/V/vsuxseg7ei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxseg7ei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 110001-----------000-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsuxseg8ei16.v.yaml b/arch/inst/V/vsuxseg8ei16.v.yaml index ed979fec2c..bcb839cce2 100644 --- a/arch/inst/V/vsuxseg8ei16.v.yaml +++ b/arch/inst/V/vsuxseg8ei16.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxseg8ei16.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 111001-----------101-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsuxseg8ei32.v.yaml b/arch/inst/V/vsuxseg8ei32.v.yaml index 5ac1dcab0a..187df64d41 100644 --- a/arch/inst/V/vsuxseg8ei32.v.yaml +++ b/arch/inst/V/vsuxseg8ei32.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxseg8ei32.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 111001-----------110-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsuxseg8ei64.v.yaml b/arch/inst/V/vsuxseg8ei64.v.yaml index f7dc31b9ea..6bd7ba19a7 100644 --- a/arch/inst/V/vsuxseg8ei64.v.yaml +++ b/arch/inst/V/vsuxseg8ei64.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxseg8ei64.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 111001-----------111-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vsuxseg8ei8.v.yaml b/arch/inst/V/vsuxseg8ei8.v.yaml index 2099cd741b..fde99e61fa 100644 --- a/arch/inst/V/vsuxseg8ei8.v.yaml +++ b/arch/inst/V/vsuxseg8ei8.v.yaml @@ -5,20 +5,20 @@ kind: instruction name: vsuxseg8ei8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vs3 encoding: match: 111001-----------000-----0100111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vs3 - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vs3 + location: 11-7 access: s: always u: always diff --git a/arch/inst/V/vwadd.vv.yaml b/arch/inst/V/vwadd.vv.yaml index 0203707309..c1e5223c20 100644 --- a/arch/inst/V/vwadd.vv.yaml +++ b/arch/inst/V/vwadd.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwadd.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 110001-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwadd.vx.yaml b/arch/inst/V/vwadd.vx.yaml index 010532791a..1c6d1ea1c0 100644 --- a/arch/inst/V/vwadd.vx.yaml +++ b/arch/inst/V/vwadd.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwadd.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 110001-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwadd.wv.yaml b/arch/inst/V/vwadd.wv.yaml index a6a851919a..9480da43a1 100644 --- a/arch/inst/V/vwadd.wv.yaml +++ b/arch/inst/V/vwadd.wv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwadd.wv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 110101-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwadd.wx.yaml b/arch/inst/V/vwadd.wx.yaml index fd78c086a7..3d7c24bf34 100644 --- a/arch/inst/V/vwadd.wx.yaml +++ b/arch/inst/V/vwadd.wx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwadd.wx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 110101-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwaddu.vv.yaml b/arch/inst/V/vwaddu.vv.yaml index e0e0e20ab2..66235b1d79 100644 --- a/arch/inst/V/vwaddu.vv.yaml +++ b/arch/inst/V/vwaddu.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwaddu.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 110000-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwaddu.vx.yaml b/arch/inst/V/vwaddu.vx.yaml index 87870e44e9..8764aaa6a6 100644 --- a/arch/inst/V/vwaddu.vx.yaml +++ b/arch/inst/V/vwaddu.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwaddu.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 110000-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwaddu.wv.yaml b/arch/inst/V/vwaddu.wv.yaml index 799fd3761d..4b3396bb4b 100644 --- a/arch/inst/V/vwaddu.wv.yaml +++ b/arch/inst/V/vwaddu.wv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwaddu.wv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 110100-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwaddu.wx.yaml b/arch/inst/V/vwaddu.wx.yaml index 8719530b10..8d614a193f 100644 --- a/arch/inst/V/vwaddu.wx.yaml +++ b/arch/inst/V/vwaddu.wx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwaddu.wx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 110100-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwmacc.vv.yaml b/arch/inst/V/vwmacc.vv.yaml index 78246982d7..eaee840040 100644 --- a/arch/inst/V/vwmacc.vv.yaml +++ b/arch/inst/V/vwmacc.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwmacc.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 111101-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwmacc.vx.yaml b/arch/inst/V/vwmacc.vx.yaml index 1faf42a624..0540830fd5 100644 --- a/arch/inst/V/vwmacc.vx.yaml +++ b/arch/inst/V/vwmacc.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwmacc.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 111101-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwmaccsu.vv.yaml b/arch/inst/V/vwmaccsu.vv.yaml index 347cc21ffb..fa51d44a3c 100644 --- a/arch/inst/V/vwmaccsu.vv.yaml +++ b/arch/inst/V/vwmaccsu.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwmaccsu.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 111111-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwmaccsu.vx.yaml b/arch/inst/V/vwmaccsu.vx.yaml index bbb92960c2..7797552f09 100644 --- a/arch/inst/V/vwmaccsu.vx.yaml +++ b/arch/inst/V/vwmaccsu.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwmaccsu.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 111111-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwmaccu.vv.yaml b/arch/inst/V/vwmaccu.vv.yaml index 6b2d0406c4..9a9a0ac2d2 100644 --- a/arch/inst/V/vwmaccu.vv.yaml +++ b/arch/inst/V/vwmaccu.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwmaccu.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 111100-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwmaccu.vx.yaml b/arch/inst/V/vwmaccu.vx.yaml index 0e3537eeeb..70d74dc7d0 100644 --- a/arch/inst/V/vwmaccu.vx.yaml +++ b/arch/inst/V/vwmaccu.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwmaccu.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 111100-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwmaccus.vx.yaml b/arch/inst/V/vwmaccus.vx.yaml index 1704aace52..afa161fa1f 100644 --- a/arch/inst/V/vwmaccus.vx.yaml +++ b/arch/inst/V/vwmaccus.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwmaccus.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 111110-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwmul.vv.yaml b/arch/inst/V/vwmul.vv.yaml index 88ffd777c9..4c33778e70 100644 --- a/arch/inst/V/vwmul.vv.yaml +++ b/arch/inst/V/vwmul.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwmul.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 111011-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwmul.vx.yaml b/arch/inst/V/vwmul.vx.yaml index 56b2fdf908..e4f7060fbd 100644 --- a/arch/inst/V/vwmul.vx.yaml +++ b/arch/inst/V/vwmul.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwmul.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 111011-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwmulsu.vv.yaml b/arch/inst/V/vwmulsu.vv.yaml index 32a53d3af9..d6c385073f 100644 --- a/arch/inst/V/vwmulsu.vv.yaml +++ b/arch/inst/V/vwmulsu.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwmulsu.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 111010-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwmulsu.vx.yaml b/arch/inst/V/vwmulsu.vx.yaml index 6d8b53e9bb..86b26cc94d 100644 --- a/arch/inst/V/vwmulsu.vx.yaml +++ b/arch/inst/V/vwmulsu.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwmulsu.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 111010-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwmulu.vv.yaml b/arch/inst/V/vwmulu.vv.yaml index 8686115d5a..4ec2bdfdc5 100644 --- a/arch/inst/V/vwmulu.vv.yaml +++ b/arch/inst/V/vwmulu.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwmulu.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 111000-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwmulu.vx.yaml b/arch/inst/V/vwmulu.vx.yaml index 8433bb6222..5b71c1ed94 100644 --- a/arch/inst/V/vwmulu.vx.yaml +++ b/arch/inst/V/vwmulu.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwmulu.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 111000-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwredsum.vs.yaml b/arch/inst/V/vwredsum.vs.yaml index 0032bcfd6c..492d0e7a61 100644 --- a/arch/inst/V/vwredsum.vs.yaml +++ b/arch/inst/V/vwredsum.vs.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwredsum.vs long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 110001-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwredsumu.vs.yaml b/arch/inst/V/vwredsumu.vs.yaml index 700f88b76d..6b9bc995c6 100644 --- a/arch/inst/V/vwredsumu.vs.yaml +++ b/arch/inst/V/vwredsumu.vs.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwredsumu.vs long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 110000-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwsub.vv.yaml b/arch/inst/V/vwsub.vv.yaml index 14530949a3..ebeb4d80db 100644 --- a/arch/inst/V/vwsub.vv.yaml +++ b/arch/inst/V/vwsub.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwsub.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 110011-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwsub.vx.yaml b/arch/inst/V/vwsub.vx.yaml index 66a3c69f09..0998ef1951 100644 --- a/arch/inst/V/vwsub.vx.yaml +++ b/arch/inst/V/vwsub.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwsub.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 110011-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwsub.wv.yaml b/arch/inst/V/vwsub.wv.yaml index 8af49ee0a5..644ea22926 100644 --- a/arch/inst/V/vwsub.wv.yaml +++ b/arch/inst/V/vwsub.wv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwsub.wv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 110111-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwsub.wx.yaml b/arch/inst/V/vwsub.wx.yaml index a91894f1b6..e7a6707cda 100644 --- a/arch/inst/V/vwsub.wx.yaml +++ b/arch/inst/V/vwsub.wx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwsub.wx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 110111-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwsubu.vv.yaml b/arch/inst/V/vwsubu.vv.yaml index 2b05bf5121..1fec77e821 100644 --- a/arch/inst/V/vwsubu.vv.yaml +++ b/arch/inst/V/vwsubu.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwsubu.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 110010-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwsubu.vx.yaml b/arch/inst/V/vwsubu.vx.yaml index 0838d847b9..dbdb5dd943 100644 --- a/arch/inst/V/vwsubu.vx.yaml +++ b/arch/inst/V/vwsubu.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwsubu.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 110010-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwsubu.wv.yaml b/arch/inst/V/vwsubu.wv.yaml index dec2d06988..a5f210c2ca 100644 --- a/arch/inst/V/vwsubu.wv.yaml +++ b/arch/inst/V/vwsubu.wv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwsubu.wv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 110110-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vwsubu.wx.yaml b/arch/inst/V/vwsubu.wx.yaml index 84243dc457..d881e60a69 100644 --- a/arch/inst/V/vwsubu.wx.yaml +++ b/arch/inst/V/vwsubu.wx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vwsubu.wx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 110110-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vxor.vi.yaml b/arch/inst/V/vxor.vi.yaml index 40c5570701..4c9ba6b85d 100644 --- a/arch/inst/V/vxor.vi.yaml +++ b/arch/inst/V/vxor.vi.yaml @@ -5,20 +5,20 @@ kind: instruction name: vxor.vi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd, imm encoding: match: 001011-----------011-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: simm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: simm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vxor.vv.yaml b/arch/inst/V/vxor.vv.yaml index 9e3067f6be..dfab9e3671 100644 --- a/arch/inst/V/vxor.vv.yaml +++ b/arch/inst/V/vxor.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vxor.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vs1, vd encoding: match: 001011-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW_pow = get_sew_pow(); diff --git a/arch/inst/V/vxor.vx.yaml b/arch/inst/V/vxor.vx.yaml index 8ed77e0db8..cc3f843664 100644 --- a/arch/inst/V/vxor.vx.yaml +++ b/arch/inst/V/vxor.vx.yaml @@ -5,20 +5,20 @@ kind: instruction name: vxor.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, xs1, vd encoding: match: 001011-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always @@ -27,9 +27,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vzext.vf2.yaml b/arch/inst/V/vzext.vf2.yaml index c978587ca4..0f0409f7ab 100644 --- a/arch/inst/V/vzext.vf2.yaml +++ b/arch/inst/V/vzext.vf2.yaml @@ -5,18 +5,18 @@ kind: instruction name: vzext.vf2 long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010010------00110010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vzext.vf4.yaml b/arch/inst/V/vzext.vf4.yaml index a39b7b8813..8bb5470eaf 100644 --- a/arch/inst/V/vzext.vf4.yaml +++ b/arch/inst/V/vzext.vf4.yaml @@ -5,18 +5,18 @@ kind: instruction name: vzext.vf4 long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010010------00100010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/V/vzext.vf8.yaml b/arch/inst/V/vzext.vf8.yaml index 4fce98f036..9afef2eed2 100644 --- a/arch/inst/V/vzext.vf8.yaml +++ b/arch/inst/V/vzext.vf8.yaml @@ -5,18 +5,18 @@ kind: instruction name: vzext.vf8 long_name: No synopsis available. description: | - No description available. + No description available. definedBy: V assembly: vm, vs2, vd encoding: match: 010010------00010010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let SEW = get_sew(); diff --git a/arch/inst/Zabha/amoadd.b.yaml b/arch/inst/Zabha/amoadd.b.yaml index a88fe6b2ce..f427053e89 100644 --- a/arch/inst/Zabha/amoadd.b.yaml +++ b/arch/inst/Zabha/amoadd.b.yaml @@ -5,22 +5,22 @@ kind: instruction name: amoadd.b long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zabha assembly: xd, xs1, xs2, aq, rl encoding: match: 00000------------000-----0101111 variables: - - name: aq - location: 26-26 - - name: rl - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26-26 + - name: rl + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -29,9 +29,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { if extension("A") then { diff --git a/arch/inst/Zabha/amoadd.h.yaml b/arch/inst/Zabha/amoadd.h.yaml index 5b96e77791..72b6f0a07a 100644 --- a/arch/inst/Zabha/amoadd.h.yaml +++ b/arch/inst/Zabha/amoadd.h.yaml @@ -5,22 +5,22 @@ kind: instruction name: amoadd.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zabha assembly: xd, xs1, xs2, aq, rl encoding: match: 00000------------001-----0101111 variables: - - name: aq - location: 26-26 - - name: rl - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26-26 + - name: rl + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -29,9 +29,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { if extension("A") then { diff --git a/arch/inst/Zabha/amoand.b.yaml b/arch/inst/Zabha/amoand.b.yaml index a8f3e6fc2b..52509d451e 100644 --- a/arch/inst/Zabha/amoand.b.yaml +++ b/arch/inst/Zabha/amoand.b.yaml @@ -5,22 +5,22 @@ kind: instruction name: amoand.b long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zabha assembly: xd, xs1, xs2, aq, rl encoding: match: 01100------------000-----0101111 variables: - - name: aq - location: 26-26 - - name: rl - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26-26 + - name: rl + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -29,9 +29,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { if extension("A") then { diff --git a/arch/inst/Zabha/amoand.h.yaml b/arch/inst/Zabha/amoand.h.yaml index 9be12f7119..21e7fa04b8 100644 --- a/arch/inst/Zabha/amoand.h.yaml +++ b/arch/inst/Zabha/amoand.h.yaml @@ -5,22 +5,22 @@ kind: instruction name: amoand.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zabha assembly: xd, xs1, xs2, aq, rl encoding: match: 01100------------001-----0101111 variables: - - name: aq - location: 26-26 - - name: rl - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26-26 + - name: rl + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -29,9 +29,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { if extension("A") then { diff --git a/arch/inst/Zabha/amocas.b.yaml b/arch/inst/Zabha/amocas.b.yaml index 58be77749b..b7b4ef0049 100644 --- a/arch/inst/Zabha/amocas.b.yaml +++ b/arch/inst/Zabha/amocas.b.yaml @@ -5,22 +5,22 @@ kind: instruction name: amocas.b long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zabha assembly: xd, xs1, xs2, aq, rl encoding: match: 00101------------000-----0101111 variables: - - name: aq - location: 26-26 - - name: rl - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26-26 + - name: rl + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zabha/amocas.h.yaml b/arch/inst/Zabha/amocas.h.yaml index 5ea2e2b728..0a17bfb895 100644 --- a/arch/inst/Zabha/amocas.h.yaml +++ b/arch/inst/Zabha/amocas.h.yaml @@ -5,22 +5,22 @@ kind: instruction name: amocas.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zabha assembly: xd, xs1, xs2, aq, rl encoding: match: 00101------------001-----0101111 variables: - - name: aq - location: 26-26 - - name: rl - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26-26 + - name: rl + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zabha/amomax.b.yaml b/arch/inst/Zabha/amomax.b.yaml index 2ca5f28596..00c77cf2c5 100644 --- a/arch/inst/Zabha/amomax.b.yaml +++ b/arch/inst/Zabha/amomax.b.yaml @@ -5,22 +5,22 @@ kind: instruction name: amomax.b long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zabha assembly: xd, xs1, xs2, aq, rl encoding: match: 10100------------000-----0101111 variables: - - name: aq - location: 26-26 - - name: rl - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26-26 + - name: rl + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -29,9 +29,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { if extension("A") then { diff --git a/arch/inst/Zabha/amomax.h.yaml b/arch/inst/Zabha/amomax.h.yaml index b8ae26f1ae..f3f02354e1 100644 --- a/arch/inst/Zabha/amomax.h.yaml +++ b/arch/inst/Zabha/amomax.h.yaml @@ -5,22 +5,22 @@ kind: instruction name: amomax.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zabha assembly: xd, xs1, xs2, aq, rl encoding: match: 10100------------001-----0101111 variables: - - name: aq - location: 26-26 - - name: rl - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26-26 + - name: rl + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -29,9 +29,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { if extension("A") then { diff --git a/arch/inst/Zabha/amomaxu.b.yaml b/arch/inst/Zabha/amomaxu.b.yaml index 8fad8f562e..cb675e92ef 100644 --- a/arch/inst/Zabha/amomaxu.b.yaml +++ b/arch/inst/Zabha/amomaxu.b.yaml @@ -5,22 +5,22 @@ kind: instruction name: amomaxu.b long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zabha assembly: xd, xs1, xs2, aq, rl encoding: match: 11100------------000-----0101111 variables: - - name: aq - location: 26-26 - - name: rl - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26-26 + - name: rl + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -29,9 +29,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { if extension("A") then { diff --git a/arch/inst/Zabha/amomaxu.h.yaml b/arch/inst/Zabha/amomaxu.h.yaml index 9952ef3566..f65f692229 100644 --- a/arch/inst/Zabha/amomaxu.h.yaml +++ b/arch/inst/Zabha/amomaxu.h.yaml @@ -5,22 +5,22 @@ kind: instruction name: amomaxu.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zabha assembly: xd, xs1, xs2, aq, rl encoding: match: 11100------------001-----0101111 variables: - - name: aq - location: 26-26 - - name: rl - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26-26 + - name: rl + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -29,9 +29,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { if extension("A") then { diff --git a/arch/inst/Zabha/amomin.b.yaml b/arch/inst/Zabha/amomin.b.yaml index 58f898f01e..5d54cf1542 100644 --- a/arch/inst/Zabha/amomin.b.yaml +++ b/arch/inst/Zabha/amomin.b.yaml @@ -5,22 +5,22 @@ kind: instruction name: amomin.b long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zabha assembly: xd, xs1, xs2, aq, rl encoding: match: 10000------------000-----0101111 variables: - - name: aq - location: 26-26 - - name: rl - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26-26 + - name: rl + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -29,9 +29,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { if extension("A") then { diff --git a/arch/inst/Zabha/amomin.h.yaml b/arch/inst/Zabha/amomin.h.yaml index 7cb010ba0d..d003106302 100644 --- a/arch/inst/Zabha/amomin.h.yaml +++ b/arch/inst/Zabha/amomin.h.yaml @@ -5,22 +5,22 @@ kind: instruction name: amomin.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zabha assembly: xd, xs1, xs2, aq, rl encoding: match: 10000------------001-----0101111 variables: - - name: aq - location: 26-26 - - name: rl - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26-26 + - name: rl + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -29,9 +29,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { if extension("A") then { diff --git a/arch/inst/Zabha/amominu.b.yaml b/arch/inst/Zabha/amominu.b.yaml index aaf8204d5f..f781b73cfa 100644 --- a/arch/inst/Zabha/amominu.b.yaml +++ b/arch/inst/Zabha/amominu.b.yaml @@ -5,22 +5,22 @@ kind: instruction name: amominu.b long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zabha assembly: xd, xs1, xs2, aq, rl encoding: match: 11000------------000-----0101111 variables: - - name: aq - location: 26-26 - - name: rl - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26-26 + - name: rl + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -29,9 +29,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { if extension("A") then { diff --git a/arch/inst/Zabha/amominu.h.yaml b/arch/inst/Zabha/amominu.h.yaml index b805456a58..75437ea188 100644 --- a/arch/inst/Zabha/amominu.h.yaml +++ b/arch/inst/Zabha/amominu.h.yaml @@ -5,22 +5,22 @@ kind: instruction name: amominu.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zabha assembly: xd, xs1, xs2, aq, rl encoding: match: 11000------------001-----0101111 variables: - - name: aq - location: 26-26 - - name: rl - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26-26 + - name: rl + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -29,9 +29,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { if extension("A") then { diff --git a/arch/inst/Zabha/amoor.b.yaml b/arch/inst/Zabha/amoor.b.yaml index c339a8c1e2..32a155296c 100644 --- a/arch/inst/Zabha/amoor.b.yaml +++ b/arch/inst/Zabha/amoor.b.yaml @@ -5,22 +5,22 @@ kind: instruction name: amoor.b long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zabha assembly: xd, xs1, xs2, aq, rl encoding: match: 01000------------000-----0101111 variables: - - name: aq - location: 26-26 - - name: rl - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26-26 + - name: rl + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -29,9 +29,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { if extension("A") then { diff --git a/arch/inst/Zabha/amoor.h.yaml b/arch/inst/Zabha/amoor.h.yaml index 5c637e671a..4ef72909e3 100644 --- a/arch/inst/Zabha/amoor.h.yaml +++ b/arch/inst/Zabha/amoor.h.yaml @@ -5,22 +5,22 @@ kind: instruction name: amoor.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zabha assembly: xd, xs1, xs2, aq, rl encoding: match: 01000------------001-----0101111 variables: - - name: aq - location: 26-26 - - name: rl - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26-26 + - name: rl + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -29,9 +29,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { if extension("A") then { diff --git a/arch/inst/Zabha/amoswap.b.yaml b/arch/inst/Zabha/amoswap.b.yaml index e3370fa270..a17173f588 100644 --- a/arch/inst/Zabha/amoswap.b.yaml +++ b/arch/inst/Zabha/amoswap.b.yaml @@ -5,22 +5,22 @@ kind: instruction name: amoswap.b long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zabha assembly: xd, xs1, xs2, aq, rl encoding: match: 00001------------000-----0101111 variables: - - name: aq - location: 26-26 - - name: rl - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26-26 + - name: rl + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -29,9 +29,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { if extension("A") then { diff --git a/arch/inst/Zabha/amoswap.h.yaml b/arch/inst/Zabha/amoswap.h.yaml index 81ad25a56d..47f74a8b84 100644 --- a/arch/inst/Zabha/amoswap.h.yaml +++ b/arch/inst/Zabha/amoswap.h.yaml @@ -5,22 +5,22 @@ kind: instruction name: amoswap.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zabha assembly: xd, xs1, xs2, aq, rl encoding: match: 00001------------001-----0101111 variables: - - name: aq - location: 26-26 - - name: rl - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26-26 + - name: rl + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -29,9 +29,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { if extension("A") then { diff --git a/arch/inst/Zabha/amoxor.b.yaml b/arch/inst/Zabha/amoxor.b.yaml index 6cc6b94082..45ec3ff340 100644 --- a/arch/inst/Zabha/amoxor.b.yaml +++ b/arch/inst/Zabha/amoxor.b.yaml @@ -5,22 +5,22 @@ kind: instruction name: amoxor.b long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zabha assembly: xd, xs1, xs2, aq, rl encoding: match: 00100------------000-----0101111 variables: - - name: aq - location: 26-26 - - name: rl - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26-26 + - name: rl + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -29,9 +29,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { if extension("A") then { diff --git a/arch/inst/Zabha/amoxor.h.yaml b/arch/inst/Zabha/amoxor.h.yaml index a03c9def1c..e3d8799a7c 100644 --- a/arch/inst/Zabha/amoxor.h.yaml +++ b/arch/inst/Zabha/amoxor.h.yaml @@ -5,22 +5,22 @@ kind: instruction name: amoxor.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zabha assembly: xd, xs1, xs2, aq, rl encoding: match: 00100------------001-----0101111 variables: - - name: aq - location: 26-26 - - name: rl - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26-26 + - name: rl + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -29,9 +29,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { if extension("A") then { diff --git a/arch/inst/Zacas/amocas.d.yaml b/arch/inst/Zacas/amocas.d.yaml index d7adbc8fd2..3a73672d24 100644 --- a/arch/inst/Zacas/amocas.d.yaml +++ b/arch/inst/Zacas/amocas.d.yaml @@ -5,22 +5,22 @@ kind: instruction name: amocas.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zacas assembly: xd, xs1, xs2, aq, rl encoding: match: 00101------------011-----0101111 variables: - - name: aq - location: 26-26 - - name: rl - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26-26 + - name: rl + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zacas/amocas.q.yaml b/arch/inst/Zacas/amocas.q.yaml index 7c375ab204..1e5a3b8fc2 100644 --- a/arch/inst/Zacas/amocas.q.yaml +++ b/arch/inst/Zacas/amocas.q.yaml @@ -5,23 +5,23 @@ kind: instruction name: amocas.q long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zacas base: 64 assembly: xd, xs1, xs2, aq, rl encoding: match: 00101------------100-----0101111 variables: - - name: aq - location: 26-26 - - name: rl - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26-26 + - name: rl + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zacas/amocas.w.yaml b/arch/inst/Zacas/amocas.w.yaml index 5cb79b0d6a..0f4d9fd2a8 100644 --- a/arch/inst/Zacas/amocas.w.yaml +++ b/arch/inst/Zacas/amocas.w.yaml @@ -5,22 +5,22 @@ kind: instruction name: amocas.w long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zacas assembly: xd, xs1, xs2, aq, rl encoding: match: 00101------------010-----0101111 variables: - - name: aq - location: 26-26 - - name: rl - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26-26 + - name: rl + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zalasr/lb.aq.yaml b/arch/inst/Zalasr/lb.aq.yaml index c77cff6d42..8c9ce4603c 100644 --- a/arch/inst/Zalasr/lb.aq.yaml +++ b/arch/inst/Zalasr/lb.aq.yaml @@ -5,18 +5,18 @@ kind: instruction name: lb.aq long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zalasr assembly: xd, xs1, rl encoding: match: 001101-00000-----000-----0101111 variables: - - name: rl - location: 25-25 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rl + location: 25-25 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let offset : xlenbits = sign_extend(imm); diff --git a/arch/inst/Zalasr/ld.aq.yaml b/arch/inst/Zalasr/ld.aq.yaml index 227d21844f..ea3e335373 100644 --- a/arch/inst/Zalasr/ld.aq.yaml +++ b/arch/inst/Zalasr/ld.aq.yaml @@ -5,18 +5,18 @@ kind: instruction name: ld.aq long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zalasr assembly: xd, xs1, rl encoding: match: 001101-00000-----011-----0101111 variables: - - name: rl - location: 25-25 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rl + location: 25-25 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let offset : xlenbits = sign_extend(imm); diff --git a/arch/inst/Zalasr/lh.aq.yaml b/arch/inst/Zalasr/lh.aq.yaml index 34542cece4..3811cc3067 100644 --- a/arch/inst/Zalasr/lh.aq.yaml +++ b/arch/inst/Zalasr/lh.aq.yaml @@ -5,18 +5,18 @@ kind: instruction name: lh.aq long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zalasr assembly: xd, xs1, rl encoding: match: 001101-00000-----001-----0101111 variables: - - name: rl - location: 25-25 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rl + location: 25-25 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let offset : xlenbits = sign_extend(imm); diff --git a/arch/inst/Zalasr/lw.aq.yaml b/arch/inst/Zalasr/lw.aq.yaml index b0acbfb8d8..706065daf8 100644 --- a/arch/inst/Zalasr/lw.aq.yaml +++ b/arch/inst/Zalasr/lw.aq.yaml @@ -5,18 +5,18 @@ kind: instruction name: lw.aq long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zalasr assembly: xd, xs1, rl encoding: match: 001101-00000-----010-----0101111 variables: - - name: rl - location: 25-25 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rl + location: 25-25 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let offset : xlenbits = sign_extend(imm); diff --git a/arch/inst/Zalasr/sb.rl.yaml b/arch/inst/Zalasr/sb.rl.yaml index 4f2a76c0ba..038a192d1e 100644 --- a/arch/inst/Zalasr/sb.rl.yaml +++ b/arch/inst/Zalasr/sb.rl.yaml @@ -5,18 +5,18 @@ kind: instruction name: sb.rl long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zalasr assembly: xs1, xs2, aq encoding: match: 00111-1----------000000000101111 variables: - - name: aq - location: 26-26 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 + - name: aq + location: 26-26 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let offset : xlenbits = sign_extend(imm); diff --git a/arch/inst/Zalasr/sd.rl.yaml b/arch/inst/Zalasr/sd.rl.yaml index ea8d449540..e7ba1369e6 100644 --- a/arch/inst/Zalasr/sd.rl.yaml +++ b/arch/inst/Zalasr/sd.rl.yaml @@ -5,18 +5,18 @@ kind: instruction name: sd.rl long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zalasr assembly: xs1, xs2, aq encoding: match: 00111-1----------011000000101111 variables: - - name: aq - location: 26-26 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 + - name: aq + location: 26-26 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let offset : xlenbits = sign_extend(imm); diff --git a/arch/inst/Zalasr/sh.rl.yaml b/arch/inst/Zalasr/sh.rl.yaml index 6265013096..a45c0f3282 100644 --- a/arch/inst/Zalasr/sh.rl.yaml +++ b/arch/inst/Zalasr/sh.rl.yaml @@ -5,18 +5,18 @@ kind: instruction name: sh.rl long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zalasr assembly: xs1, xs2, aq encoding: match: 00111-1----------001000000101111 variables: - - name: aq - location: 26-26 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 + - name: aq + location: 26-26 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let offset : xlenbits = sign_extend(imm); diff --git a/arch/inst/Zalasr/sw.rl.yaml b/arch/inst/Zalasr/sw.rl.yaml index f93fa6709c..a1f2176f68 100644 --- a/arch/inst/Zalasr/sw.rl.yaml +++ b/arch/inst/Zalasr/sw.rl.yaml @@ -5,18 +5,18 @@ kind: instruction name: sw.rl long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zalasr assembly: xs1, xs2, aq encoding: match: 00111-1----------010000000101111 variables: - - name: aq - location: 26-26 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 + - name: aq + location: 26-26 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let offset : xlenbits = sign_extend(imm); diff --git a/arch/inst/Zawrs/wrs.nto.yaml b/arch/inst/Zawrs/wrs.nto.yaml index 8ca9e6479a..e171e412e4 100644 --- a/arch/inst/Zawrs/wrs.nto.yaml +++ b/arch/inst/Zawrs/wrs.nto.yaml @@ -5,11 +5,11 @@ kind: instruction name: wrs.nto long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zawrs assembly: wrs_nto encoding: - match: '00000000110100000000000001110011' + match: "00000000110100000000000001110011" variables: [] access: s: always diff --git a/arch/inst/Zawrs/wrs.sto.yaml b/arch/inst/Zawrs/wrs.sto.yaml index 7052d117c7..835dd8f3c1 100644 --- a/arch/inst/Zawrs/wrs.sto.yaml +++ b/arch/inst/Zawrs/wrs.sto.yaml @@ -5,11 +5,11 @@ kind: instruction name: wrs.sto long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zawrs assembly: wrs_sto encoding: - match: '00000001110100000000000001110011' + match: "00000001110100000000000001110011" variables: [] access: s: always diff --git a/arch/inst/Zbkb/brev8.yaml b/arch/inst/Zbkb/brev8.yaml index 4993648fc4..2f3cea1dfc 100644 --- a/arch/inst/Zbkb/brev8.yaml +++ b/arch/inst/Zbkb/brev8.yaml @@ -5,17 +5,17 @@ kind: instruction name: brev8 long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [B, Zbkb, Zk, Zkn, Zks] assembly: xd, xs1 encoding: match: 011010000111-----101-----0010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zbkb/unzip.yaml b/arch/inst/Zbkb/unzip.yaml index 64bff932a8..ee1346c116 100644 --- a/arch/inst/Zbkb/unzip.yaml +++ b/arch/inst/Zbkb/unzip.yaml @@ -5,17 +5,17 @@ kind: instruction name: unzip long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [B, Zbkb, Zk, Zkn, Zks] assembly: xd, xs1 encoding: match: 000010001111-----101-----0010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zbkb/zip.yaml b/arch/inst/Zbkb/zip.yaml index b5a3b27330..17f309379d 100644 --- a/arch/inst/Zbkb/zip.yaml +++ b/arch/inst/Zbkb/zip.yaml @@ -5,17 +5,17 @@ kind: instruction name: zip long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [B, Zbkb, Zk, Zkn, Zks] assembly: xd, xs1 encoding: match: 000010001111-----001-----0010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zbkx/xperm4.yaml b/arch/inst/Zbkx/xperm4.yaml index 0e1c05fb73..1ff88af984 100644 --- a/arch/inst/Zbkx/xperm4.yaml +++ b/arch/inst/Zbkx/xperm4.yaml @@ -5,19 +5,19 @@ kind: instruction name: xperm4 long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [B, Zbkx, Zk, Zkn, Zks] assembly: xd, xs1, xs2 encoding: match: 0010100----------010-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zbkx/xperm8.yaml b/arch/inst/Zbkx/xperm8.yaml index a0afff2de2..3968dc5f9e 100644 --- a/arch/inst/Zbkx/xperm8.yaml +++ b/arch/inst/Zbkx/xperm8.yaml @@ -5,19 +5,19 @@ kind: instruction name: xperm8 long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [B, Zbkx, Zk, Zkn, Zks] assembly: xd, xs1, xs2 encoding: match: 0010100----------100-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zbp/gorci.yaml b/arch/inst/Zbp/gorci.yaml index 1b7037d2c5..c74ab2a883 100644 --- a/arch/inst/Zbp/gorci.yaml +++ b/arch/inst/Zbp/gorci.yaml @@ -5,19 +5,19 @@ kind: instruction name: gorci long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [B, Zbp] assembly: xd, xs1, shamt encoding: match: 001010-----------101-----0010011 variables: - - name: shamt - location: 25-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: shamt + location: 25-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zbp/grevi.yaml b/arch/inst/Zbp/grevi.yaml index 1fa748351c..2fb9fbac8b 100644 --- a/arch/inst/Zbp/grevi.yaml +++ b/arch/inst/Zbp/grevi.yaml @@ -5,19 +5,19 @@ kind: instruction name: grevi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [B, Zbp] assembly: xd, xs1, shamt encoding: match: 011010-----------101-----0010011 variables: - - name: shamt - location: 25-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: shamt + location: 25-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zbp/shfli.yaml b/arch/inst/Zbp/shfli.yaml index c903c6ae89..ec21d0f74d 100644 --- a/arch/inst/Zbp/shfli.yaml +++ b/arch/inst/Zbp/shfli.yaml @@ -5,19 +5,19 @@ kind: instruction name: shfli long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [B, Zbp] assembly: xd, xs1, shamt encoding: match: 0000100----------001-----0010011 variables: - - name: shamt - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: shamt + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zbp/unshfli.yaml b/arch/inst/Zbp/unshfli.yaml index 0f49c53244..7eab8ae103 100644 --- a/arch/inst/Zbp/unshfli.yaml +++ b/arch/inst/Zbp/unshfli.yaml @@ -5,19 +5,19 @@ kind: instruction name: unshfli long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [B, Zbp] assembly: xd, xs1, shamt encoding: match: 0000100----------101-----0010011 variables: - - name: shamt - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: shamt + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zbp/xperm16.yaml b/arch/inst/Zbp/xperm16.yaml index ad079aadb6..2efc255481 100644 --- a/arch/inst/Zbp/xperm16.yaml +++ b/arch/inst/Zbp/xperm16.yaml @@ -5,19 +5,19 @@ kind: instruction name: xperm16 long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [B, Zbp] assembly: xd, xs1, xs2 encoding: match: 0010100----------110-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zbp/xperm32.yaml b/arch/inst/Zbp/xperm32.yaml index 796b190713..9832c3aa05 100644 --- a/arch/inst/Zbp/xperm32.yaml +++ b/arch/inst/Zbp/xperm32.yaml @@ -5,19 +5,19 @@ kind: instruction name: xperm32 long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [B, Zbp] assembly: xd, xs1, xs2 encoding: match: 0010100----------000-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zcb/c.lbu.yaml b/arch/inst/Zcb/c.lbu.yaml index 0c0a4a0a96..e02c328573 100644 --- a/arch/inst/Zcb/c.lbu.yaml +++ b/arch/inst/Zcb/c.lbu.yaml @@ -10,18 +10,18 @@ description: | It expands to `lbu` `rd, offset(rs1)`. definedBy: anyOf: - - Zcb - - Zce + - Zcb + - Zce assembly: xd, imm(xs1) encoding: match: 100000--------00 variables: - - name: imm - location: 5|6 - - name: rd - location: 4-2 - - name: rs1 - location: 9-7 + - name: imm + location: 5|6 + - name: rd + location: 4-2 + - name: rs1 + location: 9-7 access: s: always u: always diff --git a/arch/inst/Zcb/c.lh.yaml b/arch/inst/Zcb/c.lh.yaml index 2c29ba108b..a96c92ef80 100644 --- a/arch/inst/Zcb/c.lh.yaml +++ b/arch/inst/Zcb/c.lh.yaml @@ -10,19 +10,19 @@ description: | It expands to `lh` `rd, offset(rs1)`. definedBy: anyOf: - - Zcb - - Zce + - Zcb + - Zce assembly: xd, imm(xs1) encoding: match: 100001---1----00 variables: - - name: imm - location: 5 - left_shift: 1 - - name: rd - location: 4-2 - - name: rs1 - location: 9-7 + - name: imm + location: 5 + left_shift: 1 + - name: rd + location: 4-2 + - name: rs1 + location: 9-7 access: s: always u: always diff --git a/arch/inst/Zcb/c.lhu.yaml b/arch/inst/Zcb/c.lhu.yaml index 1d71ead419..6d6e7d819c 100644 --- a/arch/inst/Zcb/c.lhu.yaml +++ b/arch/inst/Zcb/c.lhu.yaml @@ -10,19 +10,19 @@ description: | It expands to `lhu` `rd, offset(rs1)`. definedBy: anyOf: - - Zcb - - Zce + - Zcb + - Zce assembly: xd, imm(xs1) encoding: match: 100001---0----00 variables: - - name: imm - location: 5 - left_shift: 1 - - name: rd - location: 4-2 - - name: rs1 - location: 9-7 + - name: imm + location: 5 + left_shift: 1 + - name: rd + location: 4-2 + - name: rs1 + location: 9-7 access: s: always u: always diff --git a/arch/inst/Zcb/c.mul.yaml b/arch/inst/Zcb/c.mul.yaml index f27561dbb2..f70a887120 100644 --- a/arch/inst/Zcb/c.mul.yaml +++ b/arch/inst/Zcb/c.mul.yaml @@ -9,16 +9,16 @@ description: | definedBy: allOf: - - Zcb - - Zmmul + - Zcb + - Zmmul assembly: xd, xs2 encoding: match: 100111---10---01 variables: - - name: rd - location: 9-7 - - name: rs2 - location: 4-2 + - name: rd + location: 9-7 + - name: rs2 + location: 4-2 access: s: always u: always diff --git a/arch/inst/Zcb/c.not.yaml b/arch/inst/Zcb/c.not.yaml index 8612ca93e4..8841c116ac 100644 --- a/arch/inst/Zcb/c.not.yaml +++ b/arch/inst/Zcb/c.not.yaml @@ -10,14 +10,14 @@ description: | definedBy: anyOf: - - Zcb - - Zce + - Zcb + - Zce assembly: xd encoding: match: 100111---1110101 variables: - - name: rd - location: 9-7 + - name: rd + location: 9-7 access: s: always u: always diff --git a/arch/inst/Zcb/c.sb.yaml b/arch/inst/Zcb/c.sb.yaml index f4dcfa76cb..18ef857322 100644 --- a/arch/inst/Zcb/c.sb.yaml +++ b/arch/inst/Zcb/c.sb.yaml @@ -10,18 +10,18 @@ description: | It expands to `sb` `rs2, offset(rs1)`. definedBy: anyOf: - - Zcb - - Zce + - Zcb + - Zce assembly: xs2, imm(xs1) encoding: match: 100010--------00 variables: - - name: imm - location: 5|6 - - name: rs2 - location: 4-2 - - name: rs1 - location: 9-7 + - name: imm + location: 5|6 + - name: rs2 + location: 4-2 + - name: rs1 + location: 9-7 access: s: always u: always diff --git a/arch/inst/Zcb/c.sext.b.yaml b/arch/inst/Zcb/c.sext.b.yaml index 0bd3c24de8..9dd0dae51f 100644 --- a/arch/inst/Zcb/c.sext.b.yaml +++ b/arch/inst/Zcb/c.sext.b.yaml @@ -11,14 +11,14 @@ description: | definedBy: allOf: - - Zcb - - Zbb + - Zcb + - Zbb assembly: xd encoding: match: 100111---1100101 variables: - - name: rd - location: 9-7 + - name: rd + location: 9-7 access: s: always u: always diff --git a/arch/inst/Zcb/c.sext.h.yaml b/arch/inst/Zcb/c.sext.h.yaml index 8f80616050..734cb8bd35 100644 --- a/arch/inst/Zcb/c.sext.h.yaml +++ b/arch/inst/Zcb/c.sext.h.yaml @@ -11,14 +11,14 @@ description: | definedBy: allOf: - - Zcb - - Zbb + - Zcb + - Zbb assembly: xd encoding: match: 100111---1101101 variables: - - name: rd - location: 9-7 + - name: rd + location: 9-7 access: s: always u: always diff --git a/arch/inst/Zcb/c.sh.yaml b/arch/inst/Zcb/c.sh.yaml index 39d357048f..f4e34aef88 100644 --- a/arch/inst/Zcb/c.sh.yaml +++ b/arch/inst/Zcb/c.sh.yaml @@ -10,19 +10,19 @@ description: | It expands to `sh` `rs2, offset(rs1)`. definedBy: anyOf: - - Zcb - - Zce + - Zcb + - Zce assembly: xs2, imm(xs1) encoding: match: 100011---0----00 variables: - - name: imm - location: 5 - left_shift: 1 - - name: rs2 - location: 4-2 - - name: rs1 - location: 9-7 + - name: imm + location: 5 + left_shift: 1 + - name: rs2 + location: 4-2 + - name: rs1 + location: 9-7 access: s: always u: always diff --git a/arch/inst/Zcb/c.zext.b.yaml b/arch/inst/Zcb/c.zext.b.yaml index 0049b6229d..f048a52c58 100644 --- a/arch/inst/Zcb/c.zext.b.yaml +++ b/arch/inst/Zcb/c.zext.b.yaml @@ -11,14 +11,14 @@ description: | definedBy: allOf: - - Zcb - - Zbb + - Zcb + - Zbb assembly: xd encoding: match: 100111---1100001 variables: - - name: rd - location: 9-7 + - name: rd + location: 9-7 access: s: always u: always diff --git a/arch/inst/Zcb/c.zext.h.yaml b/arch/inst/Zcb/c.zext.h.yaml index aeff66ef03..57fb520e67 100644 --- a/arch/inst/Zcb/c.zext.h.yaml +++ b/arch/inst/Zcb/c.zext.h.yaml @@ -11,14 +11,14 @@ description: | definedBy: allOf: - - Zcb - - Zbb + - Zcb + - Zbb assembly: xd encoding: match: 100111---1101001 variables: - - name: rd - location: 9-7 + - name: rd + location: 9-7 access: s: always u: always diff --git a/arch/inst/Zcb/c.zext.w.yaml b/arch/inst/Zcb/c.zext.w.yaml index ea226cd043..cd6e4526e1 100644 --- a/arch/inst/Zcb/c.zext.w.yaml +++ b/arch/inst/Zcb/c.zext.w.yaml @@ -10,15 +10,15 @@ description: | definedBy: allOf: - - Zcb - - Zbb + - Zcb + - Zbb assembly: xd base: 64 encoding: match: 100111---1110001 variables: - - name: rd - location: 9-7 + - name: rd + location: 9-7 access: s: always u: always diff --git a/arch/inst/Zfbfmin/fcvt.bf16.s.yaml b/arch/inst/Zfbfmin/fcvt.bf16.s.yaml index 50e616b591..1b738d2eb0 100644 --- a/arch/inst/Zfbfmin/fcvt.bf16.s.yaml +++ b/arch/inst/Zfbfmin/fcvt.bf16.s.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.bf16.s long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zfbfmin assembly: xd, xs1, rm encoding: match: 010001001000-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfbfmin/fcvt.s.bf16.yaml b/arch/inst/Zfbfmin/fcvt.s.bf16.yaml index c6d2dcb9c1..147e56587f 100644 --- a/arch/inst/Zfbfmin/fcvt.s.bf16.yaml +++ b/arch/inst/Zfbfmin/fcvt.s.bf16.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.s.bf16 long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zfbfmin assembly: xd, xs1, rm encoding: match: 010000000110-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fadd.h.yaml b/arch/inst/Zfh/fadd.h.yaml index 8ff9819fef..41aee2f97b 100644 --- a/arch/inst/Zfh/fadd.h.yaml +++ b/arch/inst/Zfh/fadd.h.yaml @@ -5,20 +5,20 @@ kind: instruction name: fadd.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zfh assembly: xd, xs1, xs2, rm encoding: match: 0000010------------------1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fclass.h.yaml b/arch/inst/Zfh/fclass.h.yaml index dff44fbda8..2d14f02fb4 100644 --- a/arch/inst/Zfh/fclass.h.yaml +++ b/arch/inst/Zfh/fclass.h.yaml @@ -5,16 +5,16 @@ kind: instruction name: fclass.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zfh assembly: xd, xs1 encoding: match: 111001000000-----001-----1010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fcvt.d.h.yaml b/arch/inst/Zfh/fcvt.d.h.yaml index 5f309dcb2e..dc02cc5a64 100644 --- a/arch/inst/Zfh/fcvt.d.h.yaml +++ b/arch/inst/Zfh/fcvt.d.h.yaml @@ -5,19 +5,19 @@ kind: instruction name: fcvt.d.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [D, Zfh] assembly: xd, xs1, rm encoding: match: 010000100010-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fcvt.h.d.yaml b/arch/inst/Zfh/fcvt.h.d.yaml index 83d8d53ef5..82db22c0e9 100644 --- a/arch/inst/Zfh/fcvt.h.d.yaml +++ b/arch/inst/Zfh/fcvt.h.d.yaml @@ -5,19 +5,19 @@ kind: instruction name: fcvt.h.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [D, Zfh] assembly: xd, xs1, rm encoding: match: 010001000001-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fcvt.h.l.yaml b/arch/inst/Zfh/fcvt.h.l.yaml index a91e39fe6e..30321a088b 100644 --- a/arch/inst/Zfh/fcvt.h.l.yaml +++ b/arch/inst/Zfh/fcvt.h.l.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.h.l long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zfh assembly: xd, xs1, rm encoding: match: 110101000010-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fcvt.h.lu.yaml b/arch/inst/Zfh/fcvt.h.lu.yaml index 8bca318380..62169c9127 100644 --- a/arch/inst/Zfh/fcvt.h.lu.yaml +++ b/arch/inst/Zfh/fcvt.h.lu.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.h.lu long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zfh assembly: xd, xs1, rm encoding: match: 110101000011-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fcvt.h.s.yaml b/arch/inst/Zfh/fcvt.h.s.yaml index 65f87f4e93..8526b9e4a5 100644 --- a/arch/inst/Zfh/fcvt.h.s.yaml +++ b/arch/inst/Zfh/fcvt.h.s.yaml @@ -19,12 +19,12 @@ description: | encoding: match: 010001000000-------------1010011 variables: - - name: fs1 - location: 19-15 - - name: rm - location: 14-12 - - name: fd - location: 11-7 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 access: s: always u: always @@ -65,8 +65,6 @@ operation(): | mark_f_state_dirty(); - - sail(): | { assert(sizeof(xlen) >= 64); diff --git a/arch/inst/Zfh/fcvt.h.w.yaml b/arch/inst/Zfh/fcvt.h.w.yaml index 435226b964..599021ca2d 100644 --- a/arch/inst/Zfh/fcvt.h.w.yaml +++ b/arch/inst/Zfh/fcvt.h.w.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.h.w long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zfh assembly: xd, xs1, rm encoding: match: 110101000000-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fcvt.h.wu.yaml b/arch/inst/Zfh/fcvt.h.wu.yaml index d1e3e0793e..d4b3c68ff4 100644 --- a/arch/inst/Zfh/fcvt.h.wu.yaml +++ b/arch/inst/Zfh/fcvt.h.wu.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.h.wu long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zfh assembly: xd, xs1, rm encoding: match: 110101000001-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fcvt.l.h.yaml b/arch/inst/Zfh/fcvt.l.h.yaml index f024f191d2..835ee0b192 100644 --- a/arch/inst/Zfh/fcvt.l.h.yaml +++ b/arch/inst/Zfh/fcvt.l.h.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.l.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zfh assembly: xd, xs1, rm encoding: match: 110001000010-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fcvt.lu.h.yaml b/arch/inst/Zfh/fcvt.lu.h.yaml index 24adfb47a7..ca97bf3ec4 100644 --- a/arch/inst/Zfh/fcvt.lu.h.yaml +++ b/arch/inst/Zfh/fcvt.lu.h.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.lu.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zfh assembly: xd, xs1, rm encoding: match: 110001000011-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fcvt.s.h.yaml b/arch/inst/Zfh/fcvt.s.h.yaml index dc69ea9fbf..eac044ed32 100644 --- a/arch/inst/Zfh/fcvt.s.h.yaml +++ b/arch/inst/Zfh/fcvt.s.h.yaml @@ -16,12 +16,12 @@ description: | encoding: match: 010000000010-------------1010011 variables: - - name: fs1 - location: 19-15 - - name: rm - location: 14-12 - - name: fd - location: 11-7 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 access: s: always u: always @@ -62,8 +62,6 @@ operation(): | mark_f_state_dirty(); - - sail(): | { assert(sizeof(xlen) >= 64); diff --git a/arch/inst/Zfh/fcvt.w.h.yaml b/arch/inst/Zfh/fcvt.w.h.yaml index 03c31e5e96..489ccaaf4e 100644 --- a/arch/inst/Zfh/fcvt.w.h.yaml +++ b/arch/inst/Zfh/fcvt.w.h.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.w.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zfh assembly: xd, xs1, rm encoding: match: 110001000000-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fcvt.wu.h.yaml b/arch/inst/Zfh/fcvt.wu.h.yaml index 2020304a6b..17358a6de2 100644 --- a/arch/inst/Zfh/fcvt.wu.h.yaml +++ b/arch/inst/Zfh/fcvt.wu.h.yaml @@ -5,18 +5,18 @@ kind: instruction name: fcvt.wu.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zfh assembly: xd, xs1, rm encoding: match: 110001000001-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fdiv.h.yaml b/arch/inst/Zfh/fdiv.h.yaml index ae879ef059..330c795dfb 100644 --- a/arch/inst/Zfh/fdiv.h.yaml +++ b/arch/inst/Zfh/fdiv.h.yaml @@ -5,20 +5,20 @@ kind: instruction name: fdiv.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zfh assembly: xd, xs1, xs2, rm encoding: match: 0001110------------------1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/feq.h.yaml b/arch/inst/Zfh/feq.h.yaml index a2ca9119e9..a33e7bb197 100644 --- a/arch/inst/Zfh/feq.h.yaml +++ b/arch/inst/Zfh/feq.h.yaml @@ -5,18 +5,18 @@ kind: instruction name: feq.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zfh assembly: xd, xs1, xs2 encoding: match: 1010010----------010-----1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fle.h.yaml b/arch/inst/Zfh/fle.h.yaml index 0328f9f524..5860f509f6 100644 --- a/arch/inst/Zfh/fle.h.yaml +++ b/arch/inst/Zfh/fle.h.yaml @@ -5,18 +5,18 @@ kind: instruction name: fle.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zfh assembly: xd, xs1, xs2 encoding: match: 1010010----------000-----1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fleq.h.yaml b/arch/inst/Zfh/fleq.h.yaml index 7a7a35eda5..deb371268b 100644 --- a/arch/inst/Zfh/fleq.h.yaml +++ b/arch/inst/Zfh/fleq.h.yaml @@ -5,19 +5,19 @@ kind: instruction name: fleq.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zfa, Zfh] assembly: xd, xs1, xs2 encoding: match: 1010010----------100-----1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/flh.yaml b/arch/inst/Zfh/flh.yaml index 76b99366e6..7810342f06 100644 --- a/arch/inst/Zfh/flh.yaml +++ b/arch/inst/Zfh/flh.yaml @@ -17,12 +17,12 @@ assembly: fd, imm(xs1) encoding: match: -----------------001-----0000111 variables: - - name: imm - location: 31-20 - - name: rs1 - location: 19-15 - - name: fd - location: 11-7 + - name: imm + location: 31-20 + - name: rs1 + location: 19-15 + - name: fd + location: 11-7 access: s: always u: always @@ -39,8 +39,6 @@ operation(): | mark_f_state_dirty(); - - sail(): | { let offset : xlenbits = sign_extend(imm); diff --git a/arch/inst/Zfh/fli.h.yaml b/arch/inst/Zfh/fli.h.yaml index fb22d80106..1a73648c91 100644 --- a/arch/inst/Zfh/fli.h.yaml +++ b/arch/inst/Zfh/fli.h.yaml @@ -5,17 +5,17 @@ kind: instruction name: fli.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zfa, Zfh] assembly: xd, xs1 encoding: match: 111101000001-----000-----1010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/flt.h.yaml b/arch/inst/Zfh/flt.h.yaml index 6e90a95cab..aba1e18500 100644 --- a/arch/inst/Zfh/flt.h.yaml +++ b/arch/inst/Zfh/flt.h.yaml @@ -5,18 +5,18 @@ kind: instruction name: flt.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zfh assembly: xd, xs1, xs2 encoding: match: 1010010----------001-----1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fltq.h.yaml b/arch/inst/Zfh/fltq.h.yaml index 7b3ce83cbe..852f53de15 100644 --- a/arch/inst/Zfh/fltq.h.yaml +++ b/arch/inst/Zfh/fltq.h.yaml @@ -5,19 +5,19 @@ kind: instruction name: fltq.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zfa, Zfh] assembly: xd, xs1, xs2 encoding: match: 1010010----------101-----1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fmadd.h.yaml b/arch/inst/Zfh/fmadd.h.yaml index 71971aac5e..b56287fedd 100644 --- a/arch/inst/Zfh/fmadd.h.yaml +++ b/arch/inst/Zfh/fmadd.h.yaml @@ -5,22 +5,22 @@ kind: instruction name: fmadd.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zfh assembly: xd, xs1, xs2, xs3, rm encoding: match: -----10------------------1000011 variables: - - name: rs3 - location: 31-27 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs3 + location: 31-27 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fmax.h.yaml b/arch/inst/Zfh/fmax.h.yaml index c4d132a5b2..98a6d10583 100644 --- a/arch/inst/Zfh/fmax.h.yaml +++ b/arch/inst/Zfh/fmax.h.yaml @@ -5,18 +5,18 @@ kind: instruction name: fmax.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zfh assembly: xd, xs1, xs2 encoding: match: 0010110----------001-----1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fmaxm.h.yaml b/arch/inst/Zfh/fmaxm.h.yaml index d75b0d3252..c0939a70e6 100644 --- a/arch/inst/Zfh/fmaxm.h.yaml +++ b/arch/inst/Zfh/fmaxm.h.yaml @@ -5,19 +5,19 @@ kind: instruction name: fmaxm.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zfa, Zfh] assembly: xd, xs1, xs2 encoding: match: 0010110----------011-----1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fmin.h.yaml b/arch/inst/Zfh/fmin.h.yaml index 84699940cd..ef25d24a6f 100644 --- a/arch/inst/Zfh/fmin.h.yaml +++ b/arch/inst/Zfh/fmin.h.yaml @@ -5,18 +5,18 @@ kind: instruction name: fmin.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zfh assembly: xd, xs1, xs2 encoding: match: 0010110----------000-----1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fminm.h.yaml b/arch/inst/Zfh/fminm.h.yaml index 17ed7b705a..72a365d06a 100644 --- a/arch/inst/Zfh/fminm.h.yaml +++ b/arch/inst/Zfh/fminm.h.yaml @@ -5,19 +5,19 @@ kind: instruction name: fminm.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zfa, Zfh] assembly: xd, xs1, xs2 encoding: match: 0010110----------010-----1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fmsub.h.yaml b/arch/inst/Zfh/fmsub.h.yaml index 9b17b7d823..6df211e7b4 100644 --- a/arch/inst/Zfh/fmsub.h.yaml +++ b/arch/inst/Zfh/fmsub.h.yaml @@ -5,22 +5,22 @@ kind: instruction name: fmsub.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zfh assembly: xd, xs1, xs2, xs3, rm encoding: match: -----10------------------1000111 variables: - - name: rs3 - location: 31-27 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs3 + location: 31-27 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fmul.h.yaml b/arch/inst/Zfh/fmul.h.yaml index b6185aa0cd..f2291a64d7 100644 --- a/arch/inst/Zfh/fmul.h.yaml +++ b/arch/inst/Zfh/fmul.h.yaml @@ -5,20 +5,20 @@ kind: instruction name: fmul.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zfh assembly: xd, xs1, xs2, rm encoding: match: 0001010------------------1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fmv.h.x.yaml b/arch/inst/Zfh/fmv.h.x.yaml index e6c8e76481..b179c5df82 100644 --- a/arch/inst/Zfh/fmv.h.x.yaml +++ b/arch/inst/Zfh/fmv.h.x.yaml @@ -14,10 +14,10 @@ assembly: fd, xs1 encoding: match: 111101000000-----000-----1010011 variables: - - name: rs1 - location: 19-15 - - name: fd - location: 11-7 + - name: rs1 + location: 19-15 + - name: fd + location: 11-7 access: s: always u: always @@ -32,7 +32,6 @@ operation(): | mark_f_state_dirty(); - sail(): | { let rs1_val_X = X(rs1); diff --git a/arch/inst/Zfh/fmv.x.h.yaml b/arch/inst/Zfh/fmv.x.h.yaml index ecd3085647..e0afcbcaa1 100644 --- a/arch/inst/Zfh/fmv.x.h.yaml +++ b/arch/inst/Zfh/fmv.x.h.yaml @@ -8,21 +8,21 @@ definedBy: anyOf: [Zfh, Zfhmin] assembly: rd, fs1 description: | - Moves the half-precision value in floating-point register rs1 represented in IEEE 754-2008 - encoding to the lower 16 bits of integer register rd. + Moves the half-precision value in floating-point register rs1 represented in IEEE 754-2008 + encoding to the lower 16 bits of integer register rd. - The bits are not modified in the transfer, and in particular, the payloads of non-canonical - NaNs are preserved. + The bits are not modified in the transfer, and in particular, the payloads of non-canonical + NaNs are preserved. - The highest XLEN-16 bits of the destination register are filled with copies of the - floating-point number's sign bit. + The highest XLEN-16 bits of the destination register are filled with copies of the + floating-point number's sign bit. encoding: match: 111001000000-----000-----1010011 variables: - - name: fs1 - location: 19-15 - - name: rd - location: 11-7 + - name: fs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -33,8 +33,6 @@ operation(): | X[rd] = sext(f[fs1][15:0], 16); - - sail(): | { let rs1_val_X = X(rs1); diff --git a/arch/inst/Zfh/fnmadd.h.yaml b/arch/inst/Zfh/fnmadd.h.yaml index 61b3efbcde..88bdb2feba 100644 --- a/arch/inst/Zfh/fnmadd.h.yaml +++ b/arch/inst/Zfh/fnmadd.h.yaml @@ -5,22 +5,22 @@ kind: instruction name: fnmadd.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zfh assembly: xd, xs1, xs2, xs3, rm encoding: match: -----10------------------1001111 variables: - - name: rs3 - location: 31-27 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs3 + location: 31-27 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fnmsub.h.yaml b/arch/inst/Zfh/fnmsub.h.yaml index 1f59bda402..15be753b79 100644 --- a/arch/inst/Zfh/fnmsub.h.yaml +++ b/arch/inst/Zfh/fnmsub.h.yaml @@ -5,22 +5,22 @@ kind: instruction name: fnmsub.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zfh assembly: xd, xs1, xs2, xs3, rm encoding: match: -----10------------------1001011 variables: - - name: rs3 - location: 31-27 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs3 + location: 31-27 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fround.h.yaml b/arch/inst/Zfh/fround.h.yaml index 0276757155..0cea38f953 100644 --- a/arch/inst/Zfh/fround.h.yaml +++ b/arch/inst/Zfh/fround.h.yaml @@ -5,19 +5,19 @@ kind: instruction name: fround.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zfa, Zfh] assembly: xd, xs1, rm encoding: match: 010001000100-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/froundnx.h.yaml b/arch/inst/Zfh/froundnx.h.yaml index a2477a5042..10babc702f 100644 --- a/arch/inst/Zfh/froundnx.h.yaml +++ b/arch/inst/Zfh/froundnx.h.yaml @@ -5,19 +5,19 @@ kind: instruction name: froundnx.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zfa, Zfh] assembly: xd, xs1, rm encoding: match: 010001000101-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fsgnj.h.yaml b/arch/inst/Zfh/fsgnj.h.yaml index a3a42471d4..f43c6e6ee3 100644 --- a/arch/inst/Zfh/fsgnj.h.yaml +++ b/arch/inst/Zfh/fsgnj.h.yaml @@ -5,18 +5,18 @@ kind: instruction name: fsgnj.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zfh assembly: xd, xs1, xs2 encoding: match: 0010010----------000-----1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fsgnjn.h.yaml b/arch/inst/Zfh/fsgnjn.h.yaml index b6454c3768..2a88a27310 100644 --- a/arch/inst/Zfh/fsgnjn.h.yaml +++ b/arch/inst/Zfh/fsgnjn.h.yaml @@ -5,18 +5,18 @@ kind: instruction name: fsgnjn.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zfh assembly: xd, xs1, xs2 encoding: match: 0010010----------001-----1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fsgnjx.h.yaml b/arch/inst/Zfh/fsgnjx.h.yaml index 8b30873bf1..b16460eff4 100644 --- a/arch/inst/Zfh/fsgnjx.h.yaml +++ b/arch/inst/Zfh/fsgnjx.h.yaml @@ -5,18 +5,18 @@ kind: instruction name: fsgnjx.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zfh assembly: xd, xs1, xs2 encoding: match: 0010010----------010-----1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fsh.yaml b/arch/inst/Zfh/fsh.yaml index 6edc5d18fd..40cc00979e 100644 --- a/arch/inst/Zfh/fsh.yaml +++ b/arch/inst/Zfh/fsh.yaml @@ -20,12 +20,12 @@ assembly: fs2, imm(xs1) encoding: match: -----------------001-----0100111 variables: - - name: imm - location: 31-25|11-7 - - name: rs1 - location: 19-15 - - name: fs2 - location: 24-20 + - name: imm + location: 31-25|11-7 + - name: rs1 + location: 19-15 + - name: fs2 + location: 24-20 access: s: always u: always @@ -40,8 +40,6 @@ operation(): | write_memory<16>(virtual_address, hp_value, $encoding); - - sail(): | { let offset : xlenbits = sign_extend(imm); diff --git a/arch/inst/Zfh/fsqrt.h.yaml b/arch/inst/Zfh/fsqrt.h.yaml index 61d70bfc8e..d869de24bc 100644 --- a/arch/inst/Zfh/fsqrt.h.yaml +++ b/arch/inst/Zfh/fsqrt.h.yaml @@ -5,18 +5,18 @@ kind: instruction name: fsqrt.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zfh assembly: xd, xs1, rm encoding: match: 010111000000-------------1010011 variables: - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zfh/fsub.h.yaml b/arch/inst/Zfh/fsub.h.yaml index a280c6fa52..185a4ba75e 100644 --- a/arch/inst/Zfh/fsub.h.yaml +++ b/arch/inst/Zfh/fsub.h.yaml @@ -5,20 +5,20 @@ kind: instruction name: fsub.h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zfh assembly: xd, xs1, xs2, rm encoding: match: 0000110------------------1010011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rm - location: 14-12 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rm + location: 14-12 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zicbom/cbo.clean.yaml b/arch/inst/Zicbom/cbo.clean.yaml index 04c8461d77..6cc03f317a 100644 --- a/arch/inst/Zicbom/cbo.clean.yaml +++ b/arch/inst/Zicbom/cbo.clean.yaml @@ -40,8 +40,8 @@ assembly: "TODO" encoding: match: 000000000001-----010000000001111 variables: - - name: rs1 - location: 19-15 + - name: rs1 + location: 19-15 access: m: always s: sometimes @@ -65,6 +65,7 @@ access_detail: | ! 1 ! 0 ! 1 ! executes ! `Illegal Instruction` ! executes ! `Virtual Instruction` ! 1 ! 1 ! 1 ! executes ! executes ! executes ! executes !=== + # operation(): | # let cache_block_address = X[rs1] & ~(CACHE_BLOCK_SIZE-1); diff --git a/arch/inst/Zicbom/cbo.flush.yaml b/arch/inst/Zicbom/cbo.flush.yaml index 068a2d2381..d84c793c22 100644 --- a/arch/inst/Zicbom/cbo.flush.yaml +++ b/arch/inst/Zicbom/cbo.flush.yaml @@ -33,8 +33,8 @@ assembly: "TODO" encoding: match: 000000000010-----010000000001111 variables: - - name: rs1 - location: 19-15 + - name: rs1 + location: 19-15 access: m: always s: sometimes @@ -58,6 +58,7 @@ access_detail: | ! 1 ! 0 ! 1 ! executes ! `Illegal Instruction` ! executes ! `Virtual Instruction` ! 1 ! 1 ! 1 ! executes ! executes ! executes ! executes !=== + # operation(): | # XReg cache_block_address = X[rs1] & ~(CACHE_BLOCK_SIZE-1); # Boolean has_fault?; diff --git a/arch/inst/Zicbom/cbo.inval.yaml b/arch/inst/Zicbom/cbo.inval.yaml index f0d1d9ac80..ee9ca695b7 100644 --- a/arch/inst/Zicbom/cbo.inval.yaml +++ b/arch/inst/Zicbom/cbo.inval.yaml @@ -72,8 +72,8 @@ assembly: "TODO" encoding: match: 000000000000-----010000000001111 variables: - - name: rs1 - location: 19-15 + - name: rs1 + location: 19-15 access: m: always s: sometimes @@ -101,6 +101,7 @@ access_detail: | ! 01/11 ! 00 ! 01/11 ! executes ! `Illegal Instruction` ! executes ! `Virtual Instruction` ! 01/11 ! 01/11 ! 01/11 ! executes ! executes ! executes ! executes !=== + # operation(): | # let cache_block_address = X[RS1] & ~(CACHE_BLOCK_SIZE-1); diff --git a/arch/inst/Zicboz/cbo.zero.yaml b/arch/inst/Zicboz/cbo.zero.yaml index 8457260bdb..828f51eef2 100644 --- a/arch/inst/Zicboz/cbo.zero.yaml +++ b/arch/inst/Zicboz/cbo.zero.yaml @@ -35,8 +35,8 @@ assembly: "TODO" encoding: match: 000000000100-----010000000001111 variables: - - name: rs1 - location: 19-15 + - name: rs1 + location: 19-15 access: m: always s: sometimes diff --git a/arch/inst/Zicfilp/lpad.yaml b/arch/inst/Zicfilp/lpad.yaml index d06692598c..603edc4dcd 100644 --- a/arch/inst/Zicfilp/lpad.yaml +++ b/arch/inst/Zicfilp/lpad.yaml @@ -5,15 +5,15 @@ kind: instruction name: lpad long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zicfilp assembly: imm encoding: match: --------------------000000010111 variables: - - name: imm - location: 31-12 - left_shift: 12 + - name: imm + location: 31-12 + left_shift: 12 access: s: always u: always diff --git a/arch/inst/Zicfiss/ssamoswap.d.yaml b/arch/inst/Zicfiss/ssamoswap.d.yaml index 6c6018c080..ddbaddcf14 100644 --- a/arch/inst/Zicfiss/ssamoswap.d.yaml +++ b/arch/inst/Zicfiss/ssamoswap.d.yaml @@ -5,22 +5,22 @@ kind: instruction name: ssamoswap.d long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zicfiss assembly: xd, xs1, xs2, aq, rl encoding: match: 01001------------011-----0101111 variables: - - name: aq - location: 26-26 - - name: rl - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26-26 + - name: rl + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zicfiss/ssamoswap.w.yaml b/arch/inst/Zicfiss/ssamoswap.w.yaml index df5c208cea..0db69e3e20 100644 --- a/arch/inst/Zicfiss/ssamoswap.w.yaml +++ b/arch/inst/Zicfiss/ssamoswap.w.yaml @@ -5,22 +5,22 @@ kind: instruction name: ssamoswap.w long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zicfiss assembly: xd, xs1, xs2, aq, rl encoding: match: 01001------------010-----0101111 variables: - - name: aq - location: 26-26 - - name: rl - location: 25-25 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: aq + location: 26-26 + - name: rl + location: 25-25 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zicfiss/sspopchk.x1.yaml b/arch/inst/Zicfiss/sspopchk.x1.yaml index f81089bca3..c30f485831 100644 --- a/arch/inst/Zicfiss/sspopchk.x1.yaml +++ b/arch/inst/Zicfiss/sspopchk.x1.yaml @@ -5,11 +5,11 @@ kind: instruction name: sspopchk.x1 long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zicfiss assembly: sspopchk_x1 encoding: - match: '11001101110000001100000001110011' + match: "11001101110000001100000001110011" variables: [] access: s: always diff --git a/arch/inst/Zicfiss/sspopchk.x5.yaml b/arch/inst/Zicfiss/sspopchk.x5.yaml index 9fc5f4bfe9..7104847168 100644 --- a/arch/inst/Zicfiss/sspopchk.x5.yaml +++ b/arch/inst/Zicfiss/sspopchk.x5.yaml @@ -5,11 +5,11 @@ kind: instruction name: sspopchk.x5 long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zicfiss assembly: sspopchk_x5 encoding: - match: '11001101110000101100000001110011' + match: "11001101110000101100000001110011" variables: [] access: s: always diff --git a/arch/inst/Zicfiss/sspush.x1.yaml b/arch/inst/Zicfiss/sspush.x1.yaml index bb4361007a..c9f3f95154 100644 --- a/arch/inst/Zicfiss/sspush.x1.yaml +++ b/arch/inst/Zicfiss/sspush.x1.yaml @@ -5,11 +5,11 @@ kind: instruction name: sspush.x1 long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zicfiss assembly: sspush_x1 encoding: - match: '11001110000100000100000001110011' + match: "11001110000100000100000001110011" variables: [] access: s: always diff --git a/arch/inst/Zicfiss/sspush.x5.yaml b/arch/inst/Zicfiss/sspush.x5.yaml index d2c6e13c0a..41d6d52fca 100644 --- a/arch/inst/Zicfiss/sspush.x5.yaml +++ b/arch/inst/Zicfiss/sspush.x5.yaml @@ -5,11 +5,11 @@ kind: instruction name: sspush.x5 long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zicfiss assembly: sspush_x5 encoding: - match: '11001110010100000100000001110011' + match: "11001110010100000100000001110011" variables: [] access: s: always diff --git a/arch/inst/Zicfiss/ssrdp.yaml b/arch/inst/Zicfiss/ssrdp.yaml index 4204bbe1f9..b8efb52ab1 100644 --- a/arch/inst/Zicfiss/ssrdp.yaml +++ b/arch/inst/Zicfiss/ssrdp.yaml @@ -5,15 +5,15 @@ kind: instruction name: ssrdp long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zicfiss assembly: xd encoding: match: 11001101110000000100-----1110011 variables: - - name: rd - location: 11-7 - not: 0 + - name: rd + location: 11-7 + not: 0 access: s: always u: always diff --git a/arch/inst/Zicond/czero.eqz.yaml b/arch/inst/Zicond/czero.eqz.yaml index 539e7e4224..63e65aa533 100644 --- a/arch/inst/Zicond/czero.eqz.yaml +++ b/arch/inst/Zicond/czero.eqz.yaml @@ -5,18 +5,18 @@ kind: instruction name: czero.eqz long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zicond assembly: xd, xs1, xs2 encoding: match: 0000111----------101-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let value = X(rs1); diff --git a/arch/inst/Zicond/czero.nez.yaml b/arch/inst/Zicond/czero.nez.yaml index 5dc0a21024..f3824848a9 100644 --- a/arch/inst/Zicond/czero.nez.yaml +++ b/arch/inst/Zicond/czero.nez.yaml @@ -5,18 +5,18 @@ kind: instruction name: czero.nez long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zicond assembly: xd, xs1, xs2 encoding: match: 0000111----------111-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -25,9 +25,6 @@ access: data_independent_timing: false operation(): | - - - sail(): | { let value = X(rs1); diff --git a/arch/inst/Zicsr/csrrc.yaml b/arch/inst/Zicsr/csrrc.yaml index 283cccab7c..1246882309 100644 --- a/arch/inst/Zicsr/csrrc.yaml +++ b/arch/inst/Zicsr/csrrc.yaml @@ -5,18 +5,18 @@ kind: instruction name: csrrc long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zicsr assembly: xd, xs1, csr encoding: match: -----------------011-----1110011 variables: - - name: csr - location: 31-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: csr + location: 31-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zicsr/csrrci.yaml b/arch/inst/Zicsr/csrrci.yaml index 95b2a16254..52f008dbe3 100644 --- a/arch/inst/Zicsr/csrrci.yaml +++ b/arch/inst/Zicsr/csrrci.yaml @@ -5,18 +5,18 @@ kind: instruction name: csrrci long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zicsr assembly: xd, csr, imm encoding: match: -----------------111-----1110011 variables: - - name: csr - location: 31-20 - - name: uimm - location: 19-15 - - name: rd - location: 11-7 + - name: csr + location: 31-20 + - name: uimm + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zicsr/csrrs.yaml b/arch/inst/Zicsr/csrrs.yaml index 5a5ea9f9cb..a578970d61 100644 --- a/arch/inst/Zicsr/csrrs.yaml +++ b/arch/inst/Zicsr/csrrs.yaml @@ -18,12 +18,12 @@ assembly: xd, xs1, csr encoding: match: -----------------010-----0010011 variables: - - name: csr - location: 31-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: csr + location: 31-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -41,8 +41,6 @@ operation(): | X[rd] = initial_csr_value; - - sail(): | { let rs1_val : xlenbits = if is_imm then zero_extend(rs1) else X(rs1); diff --git a/arch/inst/Zicsr/csrrsi.yaml b/arch/inst/Zicsr/csrrsi.yaml index 67f2cd1717..54ca92ebdc 100644 --- a/arch/inst/Zicsr/csrrsi.yaml +++ b/arch/inst/Zicsr/csrrsi.yaml @@ -5,18 +5,18 @@ kind: instruction name: csrrsi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zicsr assembly: xd, csr, imm encoding: match: -----------------110-----1110011 variables: - - name: csr - location: 31-20 - - name: uimm - location: 19-15 - - name: rd - location: 11-7 + - name: csr + location: 31-20 + - name: uimm + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zicsr/csrrw.yaml b/arch/inst/Zicsr/csrrw.yaml index 9625c3895b..97a98b3433 100644 --- a/arch/inst/Zicsr/csrrw.yaml +++ b/arch/inst/Zicsr/csrrw.yaml @@ -17,12 +17,12 @@ assembly: xd, xs1, csr encoding: match: -----------------001-----1110011 variables: - - name: csr - location: 31-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: csr + location: 31-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -37,8 +37,6 @@ operation(): | # performing any WARL transformations first CSR[csr].sw_write(X[rs1]); - - sail(): | { let rs1_val : xlenbits = if is_imm then zero_extend(rs1) else X(rs1); diff --git a/arch/inst/Zicsr/csrrwi.yaml b/arch/inst/Zicsr/csrrwi.yaml index 1da44ef621..473236a8bc 100644 --- a/arch/inst/Zicsr/csrrwi.yaml +++ b/arch/inst/Zicsr/csrrwi.yaml @@ -17,12 +17,12 @@ assembly: xd, zimm, csr encoding: match: -----------------101-----1110011 variables: - - name: csr - location: 31-20 - - name: imm - location: 19-15 - - name: rd - location: 11-7 + - name: csr + location: 31-20 + - name: imm + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -37,8 +37,6 @@ operation(): | # performing any WARL transformations first CSR[csr].sw_write({{XLEN-5{1'b0}}, imm}); - - sail(): | { let rs1_val : xlenbits = if is_imm then zero_extend(rs1) else X(rs1); diff --git a/arch/inst/Zifencei/fence.i.yaml b/arch/inst/Zifencei/fence.i.yaml index 63793c2f9a..4d5de9c786 100644 --- a/arch/inst/Zifencei/fence.i.yaml +++ b/arch/inst/Zifencei/fence.i.yaml @@ -37,12 +37,12 @@ assembly: "" encoding: match: -----------------001-----0001111 variables: - - name: imm - location: 31-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: imm + location: 31-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zimop/mop.r.n.yaml b/arch/inst/Zimop/mop.r.n.yaml index dcce06e567..6b7ef69541 100644 --- a/arch/inst/Zimop/mop.r.n.yaml +++ b/arch/inst/Zimop/mop.r.n.yaml @@ -5,22 +5,22 @@ kind: instruction name: mop.r.n long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zimop assembly: mop_r_t_30, mop_r_t_27_26, mop_r_t_21_20, xd, xs1 encoding: match: 1-00--0111-------100-----1110011 variables: - - name: mop_r_t_30 - location: 30-30 - - name: mop_r_t_27_26 - location: 27-26 - - name: mop_r_t_21_20 - location: 21-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: mop_r_t_30 + location: 30-30 + - name: mop_r_t_27_26 + location: 27-26 + - name: mop_r_t_21_20 + location: 21-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -28,68 +28,68 @@ access: vu: always data_independent_timing: false pseudoinstructions: -- when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x0) && (mop_r_t_27_26 == 0x0) - to: mop.r.0 -- when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x1) && (mop_r_t_27_26 == 0x0) - to: mop.r.1 -- when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x2) && (mop_r_t_27_26 == 0x0) - to: mop.r.2 -- when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x3) && (mop_r_t_27_26 == 0x0) - to: mop.r.3 -- when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x0) && (mop_r_t_27_26 == 0x1) - to: mop.r.4 -- when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x1) && (mop_r_t_27_26 == 0x1) - to: mop.r.5 -- when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x2) && (mop_r_t_27_26 == 0x1) - to: mop.r.6 -- when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x3) && (mop_r_t_27_26 == 0x1) - to: mop.r.7 -- when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x0) && (mop_r_t_27_26 == 0x2) - to: mop.r.8 -- when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x1) && (mop_r_t_27_26 == 0x2) - to: mop.r.9 -- when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x2) && (mop_r_t_27_26 == 0x2) - to: mop.r.10 -- when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x3) && (mop_r_t_27_26 == 0x2) - to: mop.r.11 -- when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x0) && (mop_r_t_27_26 == 0x3) - to: mop.r.12 -- when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x1) && (mop_r_t_27_26 == 0x3) - to: mop.r.13 -- when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x2) && (mop_r_t_27_26 == 0x3) - to: mop.r.14 -- when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x3) && (mop_r_t_27_26 == 0x3) - to: mop.r.15 -- when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x0) && (mop_r_t_27_26 == 0x0) - to: mop.r.16 -- when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x1) && (mop_r_t_27_26 == 0x0) - to: mop.r.17 -- when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x2) && (mop_r_t_27_26 == 0x0) - to: mop.r.18 -- when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x3) && (mop_r_t_27_26 == 0x0) - to: mop.r.19 -- when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x0) && (mop_r_t_27_26 == 0x1) - to: mop.r.20 -- when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x1) && (mop_r_t_27_26 == 0x1) - to: mop.r.21 -- when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x2) && (mop_r_t_27_26 == 0x1) - to: mop.r.22 -- when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x3) && (mop_r_t_27_26 == 0x1) - to: mop.r.23 -- when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x0) && (mop_r_t_27_26 == 0x2) - to: mop.r.24 -- when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x1) && (mop_r_t_27_26 == 0x2) - to: mop.r.25 -- when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x2) && (mop_r_t_27_26 == 0x2) - to: mop.r.26 -- when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x3) && (mop_r_t_27_26 == 0x2) - to: mop.r.27 -- when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x0) && (mop_r_t_27_26 == 0x3) - to: mop.r.28 -- when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x1) && (mop_r_t_27_26 == 0x3) - to: mop.r.29 -- when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x2) && (mop_r_t_27_26 == 0x3) - to: mop.r.30 -- when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x3) && (mop_r_t_27_26 == 0x3) - to: mop.r.31 + - when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x0) && (mop_r_t_27_26 == 0x0) + to: mop.r.0 + - when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x1) && (mop_r_t_27_26 == 0x0) + to: mop.r.1 + - when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x2) && (mop_r_t_27_26 == 0x0) + to: mop.r.2 + - when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x3) && (mop_r_t_27_26 == 0x0) + to: mop.r.3 + - when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x0) && (mop_r_t_27_26 == 0x1) + to: mop.r.4 + - when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x1) && (mop_r_t_27_26 == 0x1) + to: mop.r.5 + - when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x2) && (mop_r_t_27_26 == 0x1) + to: mop.r.6 + - when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x3) && (mop_r_t_27_26 == 0x1) + to: mop.r.7 + - when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x0) && (mop_r_t_27_26 == 0x2) + to: mop.r.8 + - when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x1) && (mop_r_t_27_26 == 0x2) + to: mop.r.9 + - when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x2) && (mop_r_t_27_26 == 0x2) + to: mop.r.10 + - when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x3) && (mop_r_t_27_26 == 0x2) + to: mop.r.11 + - when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x0) && (mop_r_t_27_26 == 0x3) + to: mop.r.12 + - when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x1) && (mop_r_t_27_26 == 0x3) + to: mop.r.13 + - when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x2) && (mop_r_t_27_26 == 0x3) + to: mop.r.14 + - when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x3) && (mop_r_t_27_26 == 0x3) + to: mop.r.15 + - when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x0) && (mop_r_t_27_26 == 0x0) + to: mop.r.16 + - when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x1) && (mop_r_t_27_26 == 0x0) + to: mop.r.17 + - when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x2) && (mop_r_t_27_26 == 0x0) + to: mop.r.18 + - when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x3) && (mop_r_t_27_26 == 0x0) + to: mop.r.19 + - when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x0) && (mop_r_t_27_26 == 0x1) + to: mop.r.20 + - when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x1) && (mop_r_t_27_26 == 0x1) + to: mop.r.21 + - when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x2) && (mop_r_t_27_26 == 0x1) + to: mop.r.22 + - when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x3) && (mop_r_t_27_26 == 0x1) + to: mop.r.23 + - when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x0) && (mop_r_t_27_26 == 0x2) + to: mop.r.24 + - when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x1) && (mop_r_t_27_26 == 0x2) + to: mop.r.25 + - when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x2) && (mop_r_t_27_26 == 0x2) + to: mop.r.26 + - when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x3) && (mop_r_t_27_26 == 0x2) + to: mop.r.27 + - when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x0) && (mop_r_t_27_26 == 0x3) + to: mop.r.28 + - when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x1) && (mop_r_t_27_26 == 0x3) + to: mop.r.29 + - when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x2) && (mop_r_t_27_26 == 0x3) + to: mop.r.30 + - when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x3) && (mop_r_t_27_26 == 0x3) + to: mop.r.31 operation(): | diff --git a/arch/inst/Zimop/mop.rr.n.yaml b/arch/inst/Zimop/mop.rr.n.yaml index 4681771f11..01aeab425b 100644 --- a/arch/inst/Zimop/mop.rr.n.yaml +++ b/arch/inst/Zimop/mop.rr.n.yaml @@ -5,22 +5,22 @@ kind: instruction name: mop.rr.n long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zimop assembly: mop_rr_t_30, mop_rr_t_27_26, xd, xs1, xs2 encoding: match: 1-00--1----------100-----1110011 variables: - - name: mop_rr_t_30 - location: 30-30 - - name: mop_rr_t_27_26 - location: 27-26 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: mop_rr_t_30 + location: 30-30 + - name: mop_rr_t_27_26 + location: 27-26 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -28,20 +28,20 @@ access: vu: always data_independent_timing: false pseudoinstructions: -- when: (mop_rr_t_30 == 0x0) && (mop_rr_t_27_26 == 0x0) - to: mop.rr.0 -- when: (mop_rr_t_30 == 0x0) && (mop_rr_t_27_26 == 0x1) - to: mop.rr.1 -- when: (mop_rr_t_30 == 0x0) && (mop_rr_t_27_26 == 0x2) - to: mop.rr.2 -- when: (mop_rr_t_30 == 0x0) && (mop_rr_t_27_26 == 0x3) - to: mop.rr.3 -- when: (mop_rr_t_30 == 0x1) && (mop_rr_t_27_26 == 0x0) - to: mop.rr.4 -- when: (mop_rr_t_30 == 0x1) && (mop_rr_t_27_26 == 0x1) - to: mop.rr.5 -- when: (mop_rr_t_30 == 0x1) && (mop_rr_t_27_26 == 0x2) - to: mop.rr.6 -- when: (mop_rr_t_30 == 0x1) && (mop_rr_t_27_26 == 0x3) - to: mop.rr.7 + - when: (mop_rr_t_30 == 0x0) && (mop_rr_t_27_26 == 0x0) + to: mop.rr.0 + - when: (mop_rr_t_30 == 0x0) && (mop_rr_t_27_26 == 0x1) + to: mop.rr.1 + - when: (mop_rr_t_30 == 0x0) && (mop_rr_t_27_26 == 0x2) + to: mop.rr.2 + - when: (mop_rr_t_30 == 0x0) && (mop_rr_t_27_26 == 0x3) + to: mop.rr.3 + - when: (mop_rr_t_30 == 0x1) && (mop_rr_t_27_26 == 0x0) + to: mop.rr.4 + - when: (mop_rr_t_30 == 0x1) && (mop_rr_t_27_26 == 0x1) + to: mop.rr.5 + - when: (mop_rr_t_30 == 0x1) && (mop_rr_t_27_26 == 0x2) + to: mop.rr.6 + - when: (mop_rr_t_30 == 0x1) && (mop_rr_t_27_26 == 0x3) + to: mop.rr.7 operation(): | diff --git a/arch/inst/Zk/aes32dsi.yaml b/arch/inst/Zk/aes32dsi.yaml index e192c720b4..443c1afa0f 100644 --- a/arch/inst/Zk/aes32dsi.yaml +++ b/arch/inst/Zk/aes32dsi.yaml @@ -5,7 +5,7 @@ kind: instruction name: aes32dsi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zk, Zkn, Zknd] base: 32 @@ -13,14 +13,14 @@ assembly: xd, xs1, xs2, bs encoding: match: --10101----------000-----0110011 variables: - - name: bs - location: 31-30 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: bs + location: 31-30 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zk/aes32dsmi.yaml b/arch/inst/Zk/aes32dsmi.yaml index 760aa80561..1f83af5414 100644 --- a/arch/inst/Zk/aes32dsmi.yaml +++ b/arch/inst/Zk/aes32dsmi.yaml @@ -5,7 +5,7 @@ kind: instruction name: aes32dsmi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zk, Zkn, Zknd] base: 32 @@ -13,14 +13,14 @@ assembly: xd, xs1, xs2, bs encoding: match: --10111----------000-----0110011 variables: - - name: bs - location: 31-30 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: bs + location: 31-30 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zk/aes32esi.yaml b/arch/inst/Zk/aes32esi.yaml index dde5813257..e0c5713759 100644 --- a/arch/inst/Zk/aes32esi.yaml +++ b/arch/inst/Zk/aes32esi.yaml @@ -5,7 +5,7 @@ kind: instruction name: aes32esi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zk, Zkn, Zkne] base: 32 @@ -13,14 +13,14 @@ assembly: xd, xs1, xs2, bs encoding: match: --10001----------000-----0110011 variables: - - name: bs - location: 31-30 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: bs + location: 31-30 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zk/aes32esmi.yaml b/arch/inst/Zk/aes32esmi.yaml index 39a54cf930..1b875fbe6a 100644 --- a/arch/inst/Zk/aes32esmi.yaml +++ b/arch/inst/Zk/aes32esmi.yaml @@ -5,7 +5,7 @@ kind: instruction name: aes32esmi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zk, Zkn, Zkne] base: 32 @@ -13,14 +13,14 @@ assembly: xd, xs1, xs2, bs encoding: match: --10011----------000-----0110011 variables: - - name: bs - location: 31-30 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: bs + location: 31-30 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zk/aes64ds.yaml b/arch/inst/Zk/aes64ds.yaml index 61dfb89de8..6248ebfd12 100644 --- a/arch/inst/Zk/aes64ds.yaml +++ b/arch/inst/Zk/aes64ds.yaml @@ -5,7 +5,7 @@ kind: instruction name: aes64ds long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zk, Zkn, Zknd] base: 64 @@ -13,12 +13,12 @@ assembly: xd, xs1, xs2 encoding: match: 0011101----------000-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zk/aes64dsm.yaml b/arch/inst/Zk/aes64dsm.yaml index eef0dbbcba..99c004352d 100644 --- a/arch/inst/Zk/aes64dsm.yaml +++ b/arch/inst/Zk/aes64dsm.yaml @@ -5,7 +5,7 @@ kind: instruction name: aes64dsm long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zk, Zkn, Zknd] base: 64 @@ -13,12 +13,12 @@ assembly: xd, xs1, xs2 encoding: match: 0011111----------000-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zk/aes64es.yaml b/arch/inst/Zk/aes64es.yaml index 5963c7a06f..7f3d1b259d 100644 --- a/arch/inst/Zk/aes64es.yaml +++ b/arch/inst/Zk/aes64es.yaml @@ -5,7 +5,7 @@ kind: instruction name: aes64es long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zk, Zkn, Zkne] base: 64 @@ -13,12 +13,12 @@ assembly: xd, xs1, xs2 encoding: match: 0011001----------000-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zk/aes64esm.yaml b/arch/inst/Zk/aes64esm.yaml index 3013b2a069..d46b1d9cad 100644 --- a/arch/inst/Zk/aes64esm.yaml +++ b/arch/inst/Zk/aes64esm.yaml @@ -5,7 +5,7 @@ kind: instruction name: aes64esm long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zk, Zkn, Zkne] base: 64 @@ -13,12 +13,12 @@ assembly: xd, xs1, xs2 encoding: match: 0011011----------000-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zk/aes64im.yaml b/arch/inst/Zk/aes64im.yaml index 3b5a5388b3..ea3c8050b6 100644 --- a/arch/inst/Zk/aes64im.yaml +++ b/arch/inst/Zk/aes64im.yaml @@ -5,7 +5,7 @@ kind: instruction name: aes64im long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zk, Zkn, Zknd] base: 64 @@ -13,10 +13,10 @@ assembly: xd, xs1 encoding: match: 001100000000-----001-----0010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zk/aes64ks1i.yaml b/arch/inst/Zk/aes64ks1i.yaml index 48520c22dd..d311a22b2c 100644 --- a/arch/inst/Zk/aes64ks1i.yaml +++ b/arch/inst/Zk/aes64ks1i.yaml @@ -5,7 +5,7 @@ kind: instruction name: aes64ks1i long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zk, Zkn, Zknd, Zkne] base: 64 @@ -13,12 +13,12 @@ assembly: xd, xs1, rnum encoding: match: 00110001---------001-----0010011 variables: - - name: rnum - location: 23-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rnum + location: 23-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zk/aes64ks2.yaml b/arch/inst/Zk/aes64ks2.yaml index e2189ca925..686f53dfba 100644 --- a/arch/inst/Zk/aes64ks2.yaml +++ b/arch/inst/Zk/aes64ks2.yaml @@ -5,7 +5,7 @@ kind: instruction name: aes64ks2 long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zk, Zkn, Zknd, Zkne] base: 64 @@ -13,12 +13,12 @@ assembly: xd, xs1, xs2 encoding: match: 0111111----------000-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zk/pack.yaml b/arch/inst/Zk/pack.yaml index 1a4a5d0488..a8b886764c 100644 --- a/arch/inst/Zk/pack.yaml +++ b/arch/inst/Zk/pack.yaml @@ -5,19 +5,19 @@ kind: instruction name: pack long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zbkb, Zk, Zkn, Zks] assembly: xd, xs1, xs2 encoding: match: 0000100----------100-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zk/packh.yaml b/arch/inst/Zk/packh.yaml index 6101e75fc9..a2b058ffda 100644 --- a/arch/inst/Zk/packh.yaml +++ b/arch/inst/Zk/packh.yaml @@ -5,19 +5,19 @@ kind: instruction name: packh long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zbkb, Zk, Zkn, Zks] assembly: xd, xs1, xs2 encoding: match: 0000100----------111-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zk/packw.yaml b/arch/inst/Zk/packw.yaml index b7a986491a..2005a5f04d 100644 --- a/arch/inst/Zk/packw.yaml +++ b/arch/inst/Zk/packw.yaml @@ -5,7 +5,7 @@ kind: instruction name: packw long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zbkb, Zk, Zkn, Zks] base: 64 @@ -13,12 +13,12 @@ assembly: xd, xs1, xs2 encoding: match: 0000100----------100-----0111011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always @@ -26,6 +26,6 @@ access: vu: always data_independent_timing: true pseudoinstructions: -- when: (rs2 == 0x0) - to: zext.h + - when: (rs2 == 0x0) + to: zext.h operation(): | diff --git a/arch/inst/Zk/sha256sig0.yaml b/arch/inst/Zk/sha256sig0.yaml index 2ec32995d2..47d1b88db0 100644 --- a/arch/inst/Zk/sha256sig0.yaml +++ b/arch/inst/Zk/sha256sig0.yaml @@ -5,17 +5,17 @@ kind: instruction name: sha256sig0 long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zk, Zkn, Zknh] assembly: xd, xs1 encoding: match: 000100000010-----001-----0010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zk/sha256sig1.yaml b/arch/inst/Zk/sha256sig1.yaml index 5534e26786..84b3b88275 100644 --- a/arch/inst/Zk/sha256sig1.yaml +++ b/arch/inst/Zk/sha256sig1.yaml @@ -5,17 +5,17 @@ kind: instruction name: sha256sig1 long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zk, Zkn, Zknh] assembly: xd, xs1 encoding: match: 000100000011-----001-----0010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zk/sha256sum0.yaml b/arch/inst/Zk/sha256sum0.yaml index c80507c041..d46b5b9365 100644 --- a/arch/inst/Zk/sha256sum0.yaml +++ b/arch/inst/Zk/sha256sum0.yaml @@ -5,17 +5,17 @@ kind: instruction name: sha256sum0 long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zk, Zkn, Zknh] assembly: xd, xs1 encoding: match: 000100000000-----001-----0010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zk/sha256sum1.yaml b/arch/inst/Zk/sha256sum1.yaml index 94849b65e3..0fa39a82eb 100644 --- a/arch/inst/Zk/sha256sum1.yaml +++ b/arch/inst/Zk/sha256sum1.yaml @@ -5,17 +5,17 @@ kind: instruction name: sha256sum1 long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zk, Zkn, Zknh] assembly: xd, xs1 encoding: match: 000100000001-----001-----0010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zk/sha512sig0.yaml b/arch/inst/Zk/sha512sig0.yaml index 65e4fecdac..231ed7343f 100644 --- a/arch/inst/Zk/sha512sig0.yaml +++ b/arch/inst/Zk/sha512sig0.yaml @@ -5,7 +5,7 @@ kind: instruction name: sha512sig0 long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zk, Zkn, Zknh] base: 64 @@ -13,10 +13,10 @@ assembly: xd, xs1 encoding: match: 000100000110-----001-----0010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zk/sha512sig0h.yaml b/arch/inst/Zk/sha512sig0h.yaml index 36e442d5ec..87afa16555 100644 --- a/arch/inst/Zk/sha512sig0h.yaml +++ b/arch/inst/Zk/sha512sig0h.yaml @@ -5,7 +5,7 @@ kind: instruction name: sha512sig0h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zk, Zkn, Zknh] base: 32 @@ -13,12 +13,12 @@ assembly: xd, xs1, xs2 encoding: match: 0101110----------000-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zk/sha512sig0l.yaml b/arch/inst/Zk/sha512sig0l.yaml index b45759fe5c..334ee2dd4b 100644 --- a/arch/inst/Zk/sha512sig0l.yaml +++ b/arch/inst/Zk/sha512sig0l.yaml @@ -5,7 +5,7 @@ kind: instruction name: sha512sig0l long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zk, Zkn, Zknh] base: 32 @@ -13,12 +13,12 @@ assembly: xd, xs1, xs2 encoding: match: 0101010----------000-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zk/sha512sig1.yaml b/arch/inst/Zk/sha512sig1.yaml index 83965f0fe9..3718f078a2 100644 --- a/arch/inst/Zk/sha512sig1.yaml +++ b/arch/inst/Zk/sha512sig1.yaml @@ -5,7 +5,7 @@ kind: instruction name: sha512sig1 long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zk, Zkn, Zknh] base: 64 @@ -13,10 +13,10 @@ assembly: xd, xs1 encoding: match: 000100000111-----001-----0010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zk/sha512sig1h.yaml b/arch/inst/Zk/sha512sig1h.yaml index 6dacd3aadd..24b35db5f8 100644 --- a/arch/inst/Zk/sha512sig1h.yaml +++ b/arch/inst/Zk/sha512sig1h.yaml @@ -5,7 +5,7 @@ kind: instruction name: sha512sig1h long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zk, Zkn, Zknh] base: 32 @@ -13,12 +13,12 @@ assembly: xd, xs1, xs2 encoding: match: 0101111----------000-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zk/sha512sig1l.yaml b/arch/inst/Zk/sha512sig1l.yaml index e9312f90e4..bc4b7957c7 100644 --- a/arch/inst/Zk/sha512sig1l.yaml +++ b/arch/inst/Zk/sha512sig1l.yaml @@ -5,7 +5,7 @@ kind: instruction name: sha512sig1l long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zk, Zkn, Zknh] base: 32 @@ -13,12 +13,12 @@ assembly: xd, xs1, xs2 encoding: match: 0101011----------000-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zk/sha512sum0.yaml b/arch/inst/Zk/sha512sum0.yaml index 86ab004387..991dd57c4f 100644 --- a/arch/inst/Zk/sha512sum0.yaml +++ b/arch/inst/Zk/sha512sum0.yaml @@ -5,7 +5,7 @@ kind: instruction name: sha512sum0 long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zk, Zkn, Zknh] base: 64 @@ -13,10 +13,10 @@ assembly: xd, xs1 encoding: match: 000100000100-----001-----0010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zk/sha512sum0r.yaml b/arch/inst/Zk/sha512sum0r.yaml index c535ac0919..b73a79036b 100644 --- a/arch/inst/Zk/sha512sum0r.yaml +++ b/arch/inst/Zk/sha512sum0r.yaml @@ -5,7 +5,7 @@ kind: instruction name: sha512sum0r long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zk, Zkn, Zknh] base: 32 @@ -13,12 +13,12 @@ assembly: xd, xs1, xs2 encoding: match: 0101000----------000-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zk/sha512sum1.yaml b/arch/inst/Zk/sha512sum1.yaml index ab6ab69deb..320f1dab51 100644 --- a/arch/inst/Zk/sha512sum1.yaml +++ b/arch/inst/Zk/sha512sum1.yaml @@ -5,7 +5,7 @@ kind: instruction name: sha512sum1 long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zk, Zkn, Zknh] base: 64 @@ -13,10 +13,10 @@ assembly: xd, xs1 encoding: match: 000100000101-----001-----0010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zk/sha512sum1r.yaml b/arch/inst/Zk/sha512sum1r.yaml index e1d04a9ab1..5ecc1074b2 100644 --- a/arch/inst/Zk/sha512sum1r.yaml +++ b/arch/inst/Zk/sha512sum1r.yaml @@ -5,7 +5,7 @@ kind: instruction name: sha512sum1r long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zk, Zkn, Zknh] base: 32 @@ -13,12 +13,12 @@ assembly: xd, xs1, xs2 encoding: match: 0101001----------000-----0110011 variables: - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zks/sm3p0.yaml b/arch/inst/Zks/sm3p0.yaml index b0fbadc4a2..aa903aa056 100644 --- a/arch/inst/Zks/sm3p0.yaml +++ b/arch/inst/Zks/sm3p0.yaml @@ -5,17 +5,17 @@ kind: instruction name: sm3p0 long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zks, Zksh] assembly: xd, xs1 encoding: match: 000100001000-----001-----0010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zks/sm3p1.yaml b/arch/inst/Zks/sm3p1.yaml index 9931846057..8cd4ca416a 100644 --- a/arch/inst/Zks/sm3p1.yaml +++ b/arch/inst/Zks/sm3p1.yaml @@ -5,17 +5,17 @@ kind: instruction name: sm3p1 long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zks, Zksh] assembly: xd, xs1 encoding: match: 000100001001-----001-----0010011 variables: - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zks/sm4ed.yaml b/arch/inst/Zks/sm4ed.yaml index df729eb2f7..991a043a75 100644 --- a/arch/inst/Zks/sm4ed.yaml +++ b/arch/inst/Zks/sm4ed.yaml @@ -5,21 +5,21 @@ kind: instruction name: sm4ed long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zks, Zksed] assembly: xd, xs1, xs2, bs encoding: match: --11000----------000-----0110011 variables: - - name: bs - location: 31-30 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: bs + location: 31-30 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zks/sm4ks.yaml b/arch/inst/Zks/sm4ks.yaml index 6ae18d806f..8f130c1ead 100644 --- a/arch/inst/Zks/sm4ks.yaml +++ b/arch/inst/Zks/sm4ks.yaml @@ -5,21 +5,21 @@ kind: instruction name: sm4ks long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zks, Zksed] assembly: xd, xs1, xs2, bs encoding: match: --11010----------000-----0110011 variables: - - name: bs - location: 31-30 - - name: rs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: rd - location: 11-7 + - name: bs + location: 31-30 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvbb/vandn.vv.yaml b/arch/inst/Zvbb/vandn.vv.yaml index 4da0076e0f..ecf6c738a5 100644 --- a/arch/inst/Zvbb/vandn.vv.yaml +++ b/arch/inst/Zvbb/vandn.vv.yaml @@ -5,21 +5,21 @@ kind: instruction name: vandn.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvbb, Zvkn, Zvks] assembly: vm, vs2, vs1, vd encoding: match: 000001-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvbb/vandn.vx.yaml b/arch/inst/Zvbb/vandn.vx.yaml index 2ffe56347b..d3f99128bf 100644 --- a/arch/inst/Zvbb/vandn.vx.yaml +++ b/arch/inst/Zvbb/vandn.vx.yaml @@ -5,21 +5,21 @@ kind: instruction name: vandn.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvbb, Zvkn, Zvks] assembly: vm, vs2, xs1, vd encoding: match: 000001-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvbb/vbrev.v.yaml b/arch/inst/Zvbb/vbrev.v.yaml index 71cebe3090..d6545977dc 100644 --- a/arch/inst/Zvbb/vbrev.v.yaml +++ b/arch/inst/Zvbb/vbrev.v.yaml @@ -5,19 +5,19 @@ kind: instruction name: vbrev.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvbb, Zvkn, Zvks] assembly: vm, vs2, vd encoding: match: 010010------01010010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvbb/vbrev8.v.yaml b/arch/inst/Zvbb/vbrev8.v.yaml index 4a4007d42b..e148793f41 100644 --- a/arch/inst/Zvbb/vbrev8.v.yaml +++ b/arch/inst/Zvbb/vbrev8.v.yaml @@ -5,19 +5,19 @@ kind: instruction name: vbrev8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvbb, Zvkn, Zvks] assembly: vm, vs2, vd encoding: match: 010010------01000010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvbb/vclz.v.yaml b/arch/inst/Zvbb/vclz.v.yaml index 4365156a78..b8f0efd51c 100644 --- a/arch/inst/Zvbb/vclz.v.yaml +++ b/arch/inst/Zvbb/vclz.v.yaml @@ -5,19 +5,19 @@ kind: instruction name: vclz.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvbb, Zvkn, Zvks] assembly: vm, vs2, vd encoding: match: 010010------01100010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvbb/vcpop.v.yaml b/arch/inst/Zvbb/vcpop.v.yaml index fefb67c383..051a4ae1e1 100644 --- a/arch/inst/Zvbb/vcpop.v.yaml +++ b/arch/inst/Zvbb/vcpop.v.yaml @@ -5,19 +5,19 @@ kind: instruction name: vcpop.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvbb, Zvkn, Zvks] assembly: vm, vs2, vd encoding: match: 010010------01110010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvbb/vctz.v.yaml b/arch/inst/Zvbb/vctz.v.yaml index d059535764..6890a24fae 100644 --- a/arch/inst/Zvbb/vctz.v.yaml +++ b/arch/inst/Zvbb/vctz.v.yaml @@ -5,19 +5,19 @@ kind: instruction name: vctz.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvbb, Zvkn, Zvks] assembly: vm, vs2, vd encoding: match: 010010------01101010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvbb/vrev8.v.yaml b/arch/inst/Zvbb/vrev8.v.yaml index 6fad0de88c..54620007e3 100644 --- a/arch/inst/Zvbb/vrev8.v.yaml +++ b/arch/inst/Zvbb/vrev8.v.yaml @@ -5,19 +5,19 @@ kind: instruction name: vrev8.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvbb, Zvkn, Zvks] assembly: vm, vs2, vd encoding: match: 010010------01001010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvbb/vrol.vv.yaml b/arch/inst/Zvbb/vrol.vv.yaml index cd07d39b11..414334ac9c 100644 --- a/arch/inst/Zvbb/vrol.vv.yaml +++ b/arch/inst/Zvbb/vrol.vv.yaml @@ -5,21 +5,21 @@ kind: instruction name: vrol.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvbb, Zvkn, Zvks] assembly: vm, vs2, vs1, vd encoding: match: 010101-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvbb/vrol.vx.yaml b/arch/inst/Zvbb/vrol.vx.yaml index 1210af58e9..0563a4ac41 100644 --- a/arch/inst/Zvbb/vrol.vx.yaml +++ b/arch/inst/Zvbb/vrol.vx.yaml @@ -5,21 +5,21 @@ kind: instruction name: vrol.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvbb, Zvkn, Zvks] assembly: vm, vs2, xs1, vd encoding: match: 010101-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvbb/vror.vi.yaml b/arch/inst/Zvbb/vror.vi.yaml index 78eebbb5af..e3ee0a6f31 100644 --- a/arch/inst/Zvbb/vror.vi.yaml +++ b/arch/inst/Zvbb/vror.vi.yaml @@ -5,21 +5,21 @@ kind: instruction name: vror.vi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvbb, Zvkn, Zvks] assembly: vm, vs2, vd, imm encoding: match: 01010------------011-----1010111 variables: - - name: imm - location: 26|19-15 - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: imm + location: 26|19-15 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvbb/vror.vv.yaml b/arch/inst/Zvbb/vror.vv.yaml index f2f40fe91a..ac2f5aa2e4 100644 --- a/arch/inst/Zvbb/vror.vv.yaml +++ b/arch/inst/Zvbb/vror.vv.yaml @@ -5,21 +5,21 @@ kind: instruction name: vror.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvbb, Zvkn, Zvks] assembly: vm, vs2, vs1, vd encoding: match: 010100-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvbb/vror.vx.yaml b/arch/inst/Zvbb/vror.vx.yaml index d2a77d6b71..44871c2904 100644 --- a/arch/inst/Zvbb/vror.vx.yaml +++ b/arch/inst/Zvbb/vror.vx.yaml @@ -5,21 +5,21 @@ kind: instruction name: vror.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvbb, Zvkn, Zvks] assembly: vm, vs2, xs1, vd encoding: match: 010100-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvbb/vwsll.vi.yaml b/arch/inst/Zvbb/vwsll.vi.yaml index 591c1bed5f..00dbd0ba28 100644 --- a/arch/inst/Zvbb/vwsll.vi.yaml +++ b/arch/inst/Zvbb/vwsll.vi.yaml @@ -5,21 +5,21 @@ kind: instruction name: vwsll.vi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvbb, Zvkn, Zvks] assembly: vm, vs2, vd, imm encoding: match: 110101-----------011-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: zimm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: zimm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvbb/vwsll.vv.yaml b/arch/inst/Zvbb/vwsll.vv.yaml index 2b3a21c375..0f2b4d1dd7 100644 --- a/arch/inst/Zvbb/vwsll.vv.yaml +++ b/arch/inst/Zvbb/vwsll.vv.yaml @@ -5,21 +5,21 @@ kind: instruction name: vwsll.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvbb, Zvkn, Zvks] assembly: vm, vs2, vs1, vd encoding: match: 110101-----------000-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvbb/vwsll.vx.yaml b/arch/inst/Zvbb/vwsll.vx.yaml index bee40592d9..91c02eb5be 100644 --- a/arch/inst/Zvbb/vwsll.vx.yaml +++ b/arch/inst/Zvbb/vwsll.vx.yaml @@ -5,21 +5,21 @@ kind: instruction name: vwsll.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvbb, Zvkn, Zvks] assembly: vm, vs2, xs1, vd encoding: match: 110101-----------100-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvbc/vclmul.vv.yaml b/arch/inst/Zvbc/vclmul.vv.yaml index 5546905fea..261456a1a3 100644 --- a/arch/inst/Zvbc/vclmul.vv.yaml +++ b/arch/inst/Zvbc/vclmul.vv.yaml @@ -5,21 +5,21 @@ kind: instruction name: vclmul.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvbc, Zvkn, Zvks] assembly: vm, vs2, vs1, vd encoding: match: 001100-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvbc/vclmul.vx.yaml b/arch/inst/Zvbc/vclmul.vx.yaml index 9e965b1be5..e90c8b3f6e 100644 --- a/arch/inst/Zvbc/vclmul.vx.yaml +++ b/arch/inst/Zvbc/vclmul.vx.yaml @@ -5,21 +5,21 @@ kind: instruction name: vclmul.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvbc, Zvkn, Zvks] assembly: vm, vs2, xs1, vd encoding: match: 001100-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvbc/vclmulh.vv.yaml b/arch/inst/Zvbc/vclmulh.vv.yaml index 4a077cfc01..7511606c57 100644 --- a/arch/inst/Zvbc/vclmulh.vv.yaml +++ b/arch/inst/Zvbc/vclmulh.vv.yaml @@ -5,21 +5,21 @@ kind: instruction name: vclmulh.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvbc, Zvkn, Zvks] assembly: vm, vs2, vs1, vd encoding: match: 001101-----------010-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvbc/vclmulh.vx.yaml b/arch/inst/Zvbc/vclmulh.vx.yaml index ff4ed94672..21b7b865e6 100644 --- a/arch/inst/Zvbc/vclmulh.vx.yaml +++ b/arch/inst/Zvbc/vclmulh.vx.yaml @@ -5,21 +5,21 @@ kind: instruction name: vclmulh.vx long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvbc, Zvkn, Zvks] assembly: vm, vs2, xs1, vd encoding: match: 001101-----------110-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvfbfmin/vfncvtbf16.f.f.w.yaml b/arch/inst/Zvfbfmin/vfncvtbf16.f.f.w.yaml index c6e7afbed6..2c6a47f5fc 100644 --- a/arch/inst/Zvfbfmin/vfncvtbf16.f.f.w.yaml +++ b/arch/inst/Zvfbfmin/vfncvtbf16.f.f.w.yaml @@ -5,18 +5,18 @@ kind: instruction name: vfncvtbf16.f.f.w long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zvfbfmin assembly: vm, vs2, vd encoding: match: 010010------11101001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvfbfmin/vfwcvtbf16.f.f.v.yaml b/arch/inst/Zvfbfmin/vfwcvtbf16.f.f.v.yaml index c5300811c6..421c80fc57 100644 --- a/arch/inst/Zvfbfmin/vfwcvtbf16.f.f.v.yaml +++ b/arch/inst/Zvfbfmin/vfwcvtbf16.f.f.v.yaml @@ -5,18 +5,18 @@ kind: instruction name: vfwcvtbf16.f.f.v long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zvfbfmin assembly: vm, vs2, vd encoding: match: 010010------01101001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvfbfwma/vfwmaccbf16.vf.yaml b/arch/inst/Zvfbfwma/vfwmaccbf16.vf.yaml index fa975d1b45..30054ef342 100644 --- a/arch/inst/Zvfbfwma/vfwmaccbf16.vf.yaml +++ b/arch/inst/Zvfbfwma/vfwmaccbf16.vf.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfwmaccbf16.vf long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zvfbfwma assembly: vm, vs2, xs1, vd encoding: match: 111011-----------101-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: rs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: rs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvfbfwma/vfwmaccbf16.vv.yaml b/arch/inst/Zvfbfwma/vfwmaccbf16.vv.yaml index dc775e29b2..09189a2db7 100644 --- a/arch/inst/Zvfbfwma/vfwmaccbf16.vv.yaml +++ b/arch/inst/Zvfbfwma/vfwmaccbf16.vv.yaml @@ -5,20 +5,20 @@ kind: instruction name: vfwmaccbf16.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zvfbfwma assembly: vm, vs2, vs1, vd encoding: match: 111011-----------001-----1010111 variables: - - name: vm - location: 25-25 - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvkg/vghsh.vv.yaml b/arch/inst/Zvkg/vghsh.vv.yaml index 25cf67cf70..a4f20bd162 100644 --- a/arch/inst/Zvkg/vghsh.vv.yaml +++ b/arch/inst/Zvkg/vghsh.vv.yaml @@ -5,18 +5,18 @@ kind: instruction name: vghsh.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zvkg assembly: vs2, vs1, vd encoding: match: 1011001----------010-----1110111 variables: - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvkg/vgmul.vv.yaml b/arch/inst/Zvkg/vgmul.vv.yaml index c4e1a173f7..713f4c9572 100644 --- a/arch/inst/Zvkg/vgmul.vv.yaml +++ b/arch/inst/Zvkg/vgmul.vv.yaml @@ -5,16 +5,16 @@ kind: instruction name: vgmul.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: Zvkg assembly: vs2, vd encoding: match: 1010001-----10001010-----1110111 variables: - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvkn/vaesdf.vs.yaml b/arch/inst/Zvkn/vaesdf.vs.yaml index 9a870b3d77..dfab3452f0 100644 --- a/arch/inst/Zvkn/vaesdf.vs.yaml +++ b/arch/inst/Zvkn/vaesdf.vs.yaml @@ -5,17 +5,17 @@ kind: instruction name: vaesdf.vs long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvkn, Zvkned] assembly: vs2, vd encoding: match: 1010011-----00001010-----1110111 variables: - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvkn/vaesdf.vv.yaml b/arch/inst/Zvkn/vaesdf.vv.yaml index 7ecb3e260b..943a7652c3 100644 --- a/arch/inst/Zvkn/vaesdf.vv.yaml +++ b/arch/inst/Zvkn/vaesdf.vv.yaml @@ -5,17 +5,17 @@ kind: instruction name: vaesdf.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvkn, Zvkned] assembly: vs2, vd encoding: match: 1010001-----00001010-----1110111 variables: - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvkn/vaesdm.vs.yaml b/arch/inst/Zvkn/vaesdm.vs.yaml index 4f6ba265c4..986d97d461 100644 --- a/arch/inst/Zvkn/vaesdm.vs.yaml +++ b/arch/inst/Zvkn/vaesdm.vs.yaml @@ -5,17 +5,17 @@ kind: instruction name: vaesdm.vs long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvkn, Zvkned] assembly: vs2, vd encoding: match: 1010011-----00000010-----1110111 variables: - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvkn/vaesdm.vv.yaml b/arch/inst/Zvkn/vaesdm.vv.yaml index 3fc90fcec7..2585b72b00 100644 --- a/arch/inst/Zvkn/vaesdm.vv.yaml +++ b/arch/inst/Zvkn/vaesdm.vv.yaml @@ -5,17 +5,17 @@ kind: instruction name: vaesdm.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvkn, Zvkned] assembly: vs2, vd encoding: match: 1010001-----00000010-----1110111 variables: - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvkn/vaesef.vs.yaml b/arch/inst/Zvkn/vaesef.vs.yaml index b3d18719d4..490d8b6e15 100644 --- a/arch/inst/Zvkn/vaesef.vs.yaml +++ b/arch/inst/Zvkn/vaesef.vs.yaml @@ -5,17 +5,17 @@ kind: instruction name: vaesef.vs long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvkn, Zvkned] assembly: vs2, vd encoding: match: 1010011-----00011010-----1110111 variables: - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvkn/vaesef.vv.yaml b/arch/inst/Zvkn/vaesef.vv.yaml index 0e692cf83e..3bf5f12c8c 100644 --- a/arch/inst/Zvkn/vaesef.vv.yaml +++ b/arch/inst/Zvkn/vaesef.vv.yaml @@ -5,17 +5,17 @@ kind: instruction name: vaesef.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvkn, Zvkned] assembly: vs2, vd encoding: match: 1010001-----00011010-----1110111 variables: - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvkn/vaesem.vs.yaml b/arch/inst/Zvkn/vaesem.vs.yaml index 7010af1bb2..0a8ea43b3c 100644 --- a/arch/inst/Zvkn/vaesem.vs.yaml +++ b/arch/inst/Zvkn/vaesem.vs.yaml @@ -5,17 +5,17 @@ kind: instruction name: vaesem.vs long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvkn, Zvkned] assembly: vs2, vd encoding: match: 1010011-----00010010-----1110111 variables: - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvkn/vaesem.vv.yaml b/arch/inst/Zvkn/vaesem.vv.yaml index ae5618f1d1..e515036e4e 100644 --- a/arch/inst/Zvkn/vaesem.vv.yaml +++ b/arch/inst/Zvkn/vaesem.vv.yaml @@ -5,17 +5,17 @@ kind: instruction name: vaesem.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvkn, Zvkned] assembly: vs2, vd encoding: match: 1010001-----00010010-----1110111 variables: - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvkn/vaeskf1.vi.yaml b/arch/inst/Zvkn/vaeskf1.vi.yaml index ea88d6459c..e8554288b1 100644 --- a/arch/inst/Zvkn/vaeskf1.vi.yaml +++ b/arch/inst/Zvkn/vaeskf1.vi.yaml @@ -5,19 +5,19 @@ kind: instruction name: vaeskf1.vi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvkn, Zvkned] assembly: vs2, vd, imm encoding: match: 1000101----------010-----1110111 variables: - - name: vs2 - location: 24-20 - - name: zimm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: zimm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvkn/vaeskf2.vi.yaml b/arch/inst/Zvkn/vaeskf2.vi.yaml index c00b3621dc..6c2a566030 100644 --- a/arch/inst/Zvkn/vaeskf2.vi.yaml +++ b/arch/inst/Zvkn/vaeskf2.vi.yaml @@ -5,19 +5,19 @@ kind: instruction name: vaeskf2.vi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvkn, Zvkned] assembly: vs2, vd, imm encoding: match: 1010101----------010-----1110111 variables: - - name: vs2 - location: 24-20 - - name: zimm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: zimm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvkn/vaesz.vs.yaml b/arch/inst/Zvkn/vaesz.vs.yaml index 970a9bae82..8d422dd7c1 100644 --- a/arch/inst/Zvkn/vaesz.vs.yaml +++ b/arch/inst/Zvkn/vaesz.vs.yaml @@ -5,17 +5,17 @@ kind: instruction name: vaesz.vs long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvkn, Zvkned] assembly: vs2, vd encoding: match: 1010011-----00111010-----1110111 variables: - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvkn/vsha2ch.vv.yaml b/arch/inst/Zvkn/vsha2ch.vv.yaml index d29bd4d82e..47b3bdf005 100644 --- a/arch/inst/Zvkn/vsha2ch.vv.yaml +++ b/arch/inst/Zvkn/vsha2ch.vv.yaml @@ -5,19 +5,19 @@ kind: instruction name: vsha2ch.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvkn, Zvknha, Zvknhb] assembly: vs2, vs1, vd encoding: match: 1011101----------010-----1110111 variables: - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvkn/vsha2cl.vv.yaml b/arch/inst/Zvkn/vsha2cl.vv.yaml index 9aa0dd3c20..4d66f76922 100644 --- a/arch/inst/Zvkn/vsha2cl.vv.yaml +++ b/arch/inst/Zvkn/vsha2cl.vv.yaml @@ -5,19 +5,19 @@ kind: instruction name: vsha2cl.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvkn, Zvknha, Zvknhb] assembly: vs2, vs1, vd encoding: match: 1011111----------010-----1110111 variables: - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvkn/vsha2ms.vv.yaml b/arch/inst/Zvkn/vsha2ms.vv.yaml index 57e5cea2c3..d7e30cfd7d 100644 --- a/arch/inst/Zvkn/vsha2ms.vv.yaml +++ b/arch/inst/Zvkn/vsha2ms.vv.yaml @@ -5,19 +5,19 @@ kind: instruction name: vsha2ms.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvkn, Zvknha, Zvknhb] assembly: vs2, vs1, vd encoding: match: 1011011----------010-----1110111 variables: - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvks/vsm3c.vi.yaml b/arch/inst/Zvks/vsm3c.vi.yaml index 03d5de481a..a053310cd2 100644 --- a/arch/inst/Zvks/vsm3c.vi.yaml +++ b/arch/inst/Zvks/vsm3c.vi.yaml @@ -5,19 +5,19 @@ kind: instruction name: vsm3c.vi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvks, Zvksh] assembly: vs2, vd, imm encoding: match: 1010111----------010-----1110111 variables: - - name: vs2 - location: 24-20 - - name: zimm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: zimm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvks/vsm3me.vv.yaml b/arch/inst/Zvks/vsm3me.vv.yaml index 25b76850b5..eb092b573b 100644 --- a/arch/inst/Zvks/vsm3me.vv.yaml +++ b/arch/inst/Zvks/vsm3me.vv.yaml @@ -5,19 +5,19 @@ kind: instruction name: vsm3me.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvks, Zvksh] assembly: vs2, vs1, vd encoding: match: 1000001----------010-----1110111 variables: - - name: vs2 - location: 24-20 - - name: vs1 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvks/vsm4k.vi.yaml b/arch/inst/Zvks/vsm4k.vi.yaml index 14056756f2..cb04d00b0c 100644 --- a/arch/inst/Zvks/vsm4k.vi.yaml +++ b/arch/inst/Zvks/vsm4k.vi.yaml @@ -5,19 +5,19 @@ kind: instruction name: vsm4k.vi long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvks, Zvksed] assembly: vs2, vd, imm encoding: match: 1000011----------010-----1110111 variables: - - name: vs2 - location: 24-20 - - name: zimm5 - location: 19-15 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: zimm5 + location: 19-15 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvks/vsm4r.vs.yaml b/arch/inst/Zvks/vsm4r.vs.yaml index e21b716374..9689032546 100644 --- a/arch/inst/Zvks/vsm4r.vs.yaml +++ b/arch/inst/Zvks/vsm4r.vs.yaml @@ -5,17 +5,17 @@ kind: instruction name: vsm4r.vs long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvks, Zvksed] assembly: vs2, vd encoding: match: 1010011-----10000010-----1110111 variables: - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/inst/Zvks/vsm4r.vv.yaml b/arch/inst/Zvks/vsm4r.vv.yaml index e1d60fd3d8..ec2507b6bc 100644 --- a/arch/inst/Zvks/vsm4r.vv.yaml +++ b/arch/inst/Zvks/vsm4r.vv.yaml @@ -5,17 +5,17 @@ kind: instruction name: vsm4r.vv long_name: No synopsis available. description: | - No description available. + No description available. definedBy: anyOf: [Zvks, Zvksed] assembly: vs2, vd encoding: match: 1010001-----10000010-----1110111 variables: - - name: vs2 - location: 24-20 - - name: vd - location: 11-7 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 access: s: always u: always diff --git a/arch/manual/isa/20240411/contents.yaml b/arch/manual/isa/20240411/contents.yaml index 3ade2dea11..b28f4ce72b 100644 --- a/arch/manual/isa/20240411/contents.yaml +++ b/arch/manual/isa/20240411/contents.yaml @@ -1,5 +1,4 @@ # yaml-language-server: $schema=../../../../schemas/manual_version_schema.json - --- manual: isa version: "4.0.0-pre" @@ -10,212 +9,212 @@ url: https://github.com/riscv/riscv-isa-manual/releases/tag/20240411 uses_isa_manual: true isa_manual_tree: "tags/20240411" volumes: -- title: "RISC-V Instruction Set Manual, Volume I: Unprivileged ISA" - description: "The RISC-V Instruction Set Manual, Volume I: Unprivileged ISA" - authors: - - name: Andrew Waterman - email: awaterman@sifive.com - organization: - name: SiFive, Inc. - url: https://www.sifive.com/ - chapters: - - riscv-isa-manual/src/colophon.adoc - - riscv-isa-manual/src/intro.adoc - - riscv-isa-manual/src/rv32.adoc - - riscv-isa-manual/src/rv32e.adoc - - riscv-isa-manual/src/rv64.adoc - - riscv-isa-manual/src/rv128.adoc - - riscv-isa-manual/src/zifencei.adoc - - riscv-isa-manual/src/zicsr.adoc - - riscv-isa-manual/src/counters.adoc - - riscv-isa-manual/src/zihintntl.adoc - - riscv-isa-manual/src/zihintpause.adoc - - riscv-isa-manual/src/zimop.adoc - - riscv-isa-manual/src/zicond.adoc - - riscv-isa-manual/src/m-st-ext.adoc - - riscv-isa-manual/src/a-st-ext.adoc - - riscv-isa-manual/src/zawrs.adoc - - riscv-isa-manual/src/zacas.adoc - - riscv-isa-manual/src/rvwmo.adoc - - riscv-isa-manual/src/ztso-st-ext.adoc - - riscv-isa-manual/src/cmo.adoc - - riscv-isa-manual/src/f-st-ext.adoc - - riscv-isa-manual/src/d-st-ext.adoc - - riscv-isa-manual/src/q-st-ext.adoc - - riscv-isa-manual/src/zfh.adoc - - riscv-isa-manual/src/zfa.adoc - - riscv-isa-manual/src/zfinx.adoc - - riscv-isa-manual/src/c-st-ext.adoc - - riscv-isa-manual/src/zc.adoc - - riscv-isa-manual/src/b-st-ext.adoc - - riscv-isa-manual/src/j-st-ext.adoc - - riscv-isa-manual/src/p-st-ext.adoc - - riscv-isa-manual/src/v-st-ext.adoc - - riscv-isa-manual/src/scalar-crypto.adoc - - riscv-isa-manual/src/vector-crypto.adoc - - riscv-isa-manual/src/rv-32-64g.adoc - - riscv-isa-manual/src/extending.adoc - - riscv-isa-manual/src/naming.adoc - - riscv-isa-manual/src/history.adoc - - riscv-isa-manual/src/mm-eplan.adoc - - riscv-isa-manual/src/mm-formal.adoc - #Appendices for Vector - - riscv-isa-manual/src/vector-examples.adoc - - riscv-isa-manual/src/calling-convention.adoc - #/End of Vector appendices - - riscv-isa-manual/src/index.adoc - extensions: - - [I, "2.1.0"] - - [U, "1.12.0"] - # - [E, "2.0"] - # - [RVI64, "2.1"] - # - [RVI128, "1.7"] - - [Zifencei, "2.0.0"] - - [Zicsr, "2.0.0"] - - [Zicntr, "2.0.0"] - - [Zihpm, "2.0.0"] - - [Zihintntl, "1.0.0"] - - [Zihintpause, "2.0.0"] - - [Zimop, "2.0.0"] - - [Zicond, "1.0.0"] - - [M, "2.0.0"] - - [A, "2.1.0"] - - [Zawrs, "1.0.1"] - - [Zacas, "1.0.0"] - - [Zabha, "1.0.0"] - # - [RVWMO, "2.0"] - - [Ztso, "1.0.0"] - - [Zicbom, "1.0.0"] - - [Zicboz, "1.0.0"] - - [Zicbop, "1.0.0"] - - [F, "2.2.0"] - - [D, "2.2.0"] - # - [Q, "2.2"] - - [Zfh, "1.0.0"] - - [Zfhmin, "1.0.0"] - - [Zfbfmin, "1.0.0"] - - [Zvfbfmin, "1.0.0"] - - [Zvfbfwma, "1.0.0"] - - [Zfa, "1.0.0"] - - [Zfinx, "1.0.0"] - - [Zdinx, "1.0.0"] - - [Zhinx, "1.0.0"] - - [C, "2.0.0"] - - [Zca, "1.0.0"] - - [Zcf, "1.0.0"] - - [Zcd, "1.0.0"] - - [Zcb, "1.0.0"] - - [Zcmp, "1.0.0"] - - [Zcmt, "1.0.0"] - - [B, "1.0.0"] - - [Zba, "1.0.0"] - - [Zbb, "1.0.0"] - - [Zbc, "1.0.0"] - - [Zbs, "1.0.0"] - - [Zbkb, "1.0.0"] - - [Zbkc, "1.0.0"] - - [Zbkx, "1.0.0"] - # - [J, "0.0"] - # - [P, "0.2"] - - [V, "1.0.0"] - - [Zvl32b, "1.0.0"] - - [Zvl64b, "1.0.0"] - - [Zvl128b, "1.0.0"] - - [Zvl256b, "1.0.0"] - - [Zvl512b, "1.0.0"] - - [Zvl1024b, "1.0.0"] - - [Zve32x, "1.0.0"] - - [Zve32f, "1.0.0"] - - [Zve64x, "1.0.0"] - - [Zve64f, "1.0.0"] - - [Zve64d, "1.0.0"] - - [Zvfhmin, "1.0.0"] - - [Zvfh, "1.0.0"] - - [Zvknha, "1.0.0"] - - [Zvknhb, "1.0.0"] - - [Zbkb, "1.0.0"] - - [Zbkc, "1.0.0"] - - [Zbkx, "1.0.0"] - - [Zknd, "1.0.0"] - - [Zkne, "1.0.0"] - - [Zknh, "1.0.0"] - - [Zksed, "1.0.0"] - - [Zksh, "1.0.0"] - - [Zkr, "1.0.0"] - - [Zkn, "1.0.0"] - - [Zks, "1.0.0"] - - [Zk, "1.0.0"] - - [Zkt, "1.0.0"] - - [Zvbb, "1.0.0"] - - [Zvbc, "1.0.0"] - - [Zvkb, "1.0.0"] - - [Zvkg, "1.0.0"] - - [Zvkned, "1.0.0"] - - [Zvknha, "1.0.0"] - - [Zvknhb, "1.0.0"] - - [Zvksed, "1.0.0"] - - [Zvksh, "1.0.0"] - - [Zvkn, "1.0.0"] - - [Zvknc, "1.0.0"] - - [Zvkng, "1.0.0"] - - [Zvks, "1.0.0"] - - [Zvksc, "1.0.0"] - - [Zvksg, "1.0.0"] - - [Zvkt, "1.0.0"] - - [Zicfilp, "1.0.0"] - - [Zicfiss, "1.0.0"] - # - [Zam, "0.1"] - changes: - - The inclusion of all ratified extensions through March 2024. - - The draft Zam extension has been removed, in favor of the definition of a misaligned atomicity granule PMA. - - The concept of vacant memory regions has been superseded by inaccessible memory or I/O regions. -- title: "RISC-V Instruction Set Manual, Volume II: Privileged ISA" - description: "The RISC-V Instruction Set Manual, Volume II: Privileged ISA" - authors: - - name: Andrew Waterman - email: awaterman@sifive.com - organization: - name: SiFive, Inc. - url: https://www.sifive.com/ - chapters: - - riscv-isa-manual/src/priv-preface.adoc - - riscv-isa-manual/src/priv-intro.adoc - - riscv-isa-manual/src/priv-csrs.adoc - - riscv-isa-manual/src/machine.adoc - - riscv-isa-manual/src/smstateen.adoc - - riscv-isa-manual/src/indirect-csr.adoc - - riscv-isa-manual/src/smepmp.adoc - - riscv-isa-manual/src/smcntrpmf.adoc - - riscv-isa-manual/src/rnmi.adoc - - riscv-isa-manual/src/smcdeleg.adoc - - riscv-isa-manual/src/supervisor.adoc - - riscv-isa-manual/src/sstc.adoc - - riscv-isa-manual/src/sscofpmf.adoc - - riscv-isa-manual/src/hypervisor.adoc - - riscv-isa-manual/src/priv-insns.adoc - - riscv-isa-manual/src/priv-history.adoc - - riscv-isa-manual/src/bibliography.adoc - extensions: - - [Smstateen, "1.0.0"] - - [Smcsrind, "1.0.0"] - - [Sscsrind, "1.0.0"] - - [Smepmp, "1.0.0"] - - [Smcntrpmf, "1.0.0"] - - [Smrnmi, "0.5.0"] - - [Smcdeleg, "1.0.0"] - - [S, "1.12.0"] - - [Sm, "1.12.0"] - - [Smhpm, "1.12.0"] - - [Smpmp, "1.12.0"] - - [Sv32, "1.12.0"] - - [Sv39, "1.12.0"] - - [Sv48, "1.12.0"] - - [Sv57, "1.12.0"] - - [Svnapot, "1.0.0"] - - [Svpbmt, "1.0.0"] - - [Svinval, "1.0.0"] - - [Svadu, "1.0.0"] - - [Svvptc, "1.0.0"] - - [Sstc, "1.0.0"] - - [Sscofpmf, "1.0.0"] - - [H, "1.0.0"] + - title: "RISC-V Instruction Set Manual, Volume I: Unprivileged ISA" + description: "The RISC-V Instruction Set Manual, Volume I: Unprivileged ISA" + authors: + - name: Andrew Waterman + email: awaterman@sifive.com + organization: + name: SiFive, Inc. + url: https://www.sifive.com/ + chapters: + - riscv-isa-manual/src/colophon.adoc + - riscv-isa-manual/src/intro.adoc + - riscv-isa-manual/src/rv32.adoc + - riscv-isa-manual/src/rv32e.adoc + - riscv-isa-manual/src/rv64.adoc + - riscv-isa-manual/src/rv128.adoc + - riscv-isa-manual/src/zifencei.adoc + - riscv-isa-manual/src/zicsr.adoc + - riscv-isa-manual/src/counters.adoc + - riscv-isa-manual/src/zihintntl.adoc + - riscv-isa-manual/src/zihintpause.adoc + - riscv-isa-manual/src/zimop.adoc + - riscv-isa-manual/src/zicond.adoc + - riscv-isa-manual/src/m-st-ext.adoc + - riscv-isa-manual/src/a-st-ext.adoc + - riscv-isa-manual/src/zawrs.adoc + - riscv-isa-manual/src/zacas.adoc + - riscv-isa-manual/src/rvwmo.adoc + - riscv-isa-manual/src/ztso-st-ext.adoc + - riscv-isa-manual/src/cmo.adoc + - riscv-isa-manual/src/f-st-ext.adoc + - riscv-isa-manual/src/d-st-ext.adoc + - riscv-isa-manual/src/q-st-ext.adoc + - riscv-isa-manual/src/zfh.adoc + - riscv-isa-manual/src/zfa.adoc + - riscv-isa-manual/src/zfinx.adoc + - riscv-isa-manual/src/c-st-ext.adoc + - riscv-isa-manual/src/zc.adoc + - riscv-isa-manual/src/b-st-ext.adoc + - riscv-isa-manual/src/j-st-ext.adoc + - riscv-isa-manual/src/p-st-ext.adoc + - riscv-isa-manual/src/v-st-ext.adoc + - riscv-isa-manual/src/scalar-crypto.adoc + - riscv-isa-manual/src/vector-crypto.adoc + - riscv-isa-manual/src/rv-32-64g.adoc + - riscv-isa-manual/src/extending.adoc + - riscv-isa-manual/src/naming.adoc + - riscv-isa-manual/src/history.adoc + - riscv-isa-manual/src/mm-eplan.adoc + - riscv-isa-manual/src/mm-formal.adoc + #Appendices for Vector + - riscv-isa-manual/src/vector-examples.adoc + - riscv-isa-manual/src/calling-convention.adoc + #/End of Vector appendices + - riscv-isa-manual/src/index.adoc + extensions: + - [I, "2.1.0"] + - [U, "1.12.0"] + # - [E, "2.0"] + # - [RVI64, "2.1"] + # - [RVI128, "1.7"] + - [Zifencei, "2.0.0"] + - [Zicsr, "2.0.0"] + - [Zicntr, "2.0.0"] + - [Zihpm, "2.0.0"] + - [Zihintntl, "1.0.0"] + - [Zihintpause, "2.0.0"] + - [Zimop, "2.0.0"] + - [Zicond, "1.0.0"] + - [M, "2.0.0"] + - [A, "2.1.0"] + - [Zawrs, "1.0.1"] + - [Zacas, "1.0.0"] + - [Zabha, "1.0.0"] + # - [RVWMO, "2.0"] + - [Ztso, "1.0.0"] + - [Zicbom, "1.0.0"] + - [Zicboz, "1.0.0"] + - [Zicbop, "1.0.0"] + - [F, "2.2.0"] + - [D, "2.2.0"] + # - [Q, "2.2"] + - [Zfh, "1.0.0"] + - [Zfhmin, "1.0.0"] + - [Zfbfmin, "1.0.0"] + - [Zvfbfmin, "1.0.0"] + - [Zvfbfwma, "1.0.0"] + - [Zfa, "1.0.0"] + - [Zfinx, "1.0.0"] + - [Zdinx, "1.0.0"] + - [Zhinx, "1.0.0"] + - [C, "2.0.0"] + - [Zca, "1.0.0"] + - [Zcf, "1.0.0"] + - [Zcd, "1.0.0"] + - [Zcb, "1.0.0"] + - [Zcmp, "1.0.0"] + - [Zcmt, "1.0.0"] + - [B, "1.0.0"] + - [Zba, "1.0.0"] + - [Zbb, "1.0.0"] + - [Zbc, "1.0.0"] + - [Zbs, "1.0.0"] + - [Zbkb, "1.0.0"] + - [Zbkc, "1.0.0"] + - [Zbkx, "1.0.0"] + # - [J, "0.0"] + # - [P, "0.2"] + - [V, "1.0.0"] + - [Zvl32b, "1.0.0"] + - [Zvl64b, "1.0.0"] + - [Zvl128b, "1.0.0"] + - [Zvl256b, "1.0.0"] + - [Zvl512b, "1.0.0"] + - [Zvl1024b, "1.0.0"] + - [Zve32x, "1.0.0"] + - [Zve32f, "1.0.0"] + - [Zve64x, "1.0.0"] + - [Zve64f, "1.0.0"] + - [Zve64d, "1.0.0"] + - [Zvfhmin, "1.0.0"] + - [Zvfh, "1.0.0"] + - [Zvknha, "1.0.0"] + - [Zvknhb, "1.0.0"] + - [Zbkb, "1.0.0"] + - [Zbkc, "1.0.0"] + - [Zbkx, "1.0.0"] + - [Zknd, "1.0.0"] + - [Zkne, "1.0.0"] + - [Zknh, "1.0.0"] + - [Zksed, "1.0.0"] + - [Zksh, "1.0.0"] + - [Zkr, "1.0.0"] + - [Zkn, "1.0.0"] + - [Zks, "1.0.0"] + - [Zk, "1.0.0"] + - [Zkt, "1.0.0"] + - [Zvbb, "1.0.0"] + - [Zvbc, "1.0.0"] + - [Zvkb, "1.0.0"] + - [Zvkg, "1.0.0"] + - [Zvkned, "1.0.0"] + - [Zvknha, "1.0.0"] + - [Zvknhb, "1.0.0"] + - [Zvksed, "1.0.0"] + - [Zvksh, "1.0.0"] + - [Zvkn, "1.0.0"] + - [Zvknc, "1.0.0"] + - [Zvkng, "1.0.0"] + - [Zvks, "1.0.0"] + - [Zvksc, "1.0.0"] + - [Zvksg, "1.0.0"] + - [Zvkt, "1.0.0"] + - [Zicfilp, "1.0.0"] + - [Zicfiss, "1.0.0"] + # - [Zam, "0.1"] + changes: + - The inclusion of all ratified extensions through March 2024. + - The draft Zam extension has been removed, in favor of the definition of a misaligned atomicity granule PMA. + - The concept of vacant memory regions has been superseded by inaccessible memory or I/O regions. + - title: "RISC-V Instruction Set Manual, Volume II: Privileged ISA" + description: "The RISC-V Instruction Set Manual, Volume II: Privileged ISA" + authors: + - name: Andrew Waterman + email: awaterman@sifive.com + organization: + name: SiFive, Inc. + url: https://www.sifive.com/ + chapters: + - riscv-isa-manual/src/priv-preface.adoc + - riscv-isa-manual/src/priv-intro.adoc + - riscv-isa-manual/src/priv-csrs.adoc + - riscv-isa-manual/src/machine.adoc + - riscv-isa-manual/src/smstateen.adoc + - riscv-isa-manual/src/indirect-csr.adoc + - riscv-isa-manual/src/smepmp.adoc + - riscv-isa-manual/src/smcntrpmf.adoc + - riscv-isa-manual/src/rnmi.adoc + - riscv-isa-manual/src/smcdeleg.adoc + - riscv-isa-manual/src/supervisor.adoc + - riscv-isa-manual/src/sstc.adoc + - riscv-isa-manual/src/sscofpmf.adoc + - riscv-isa-manual/src/hypervisor.adoc + - riscv-isa-manual/src/priv-insns.adoc + - riscv-isa-manual/src/priv-history.adoc + - riscv-isa-manual/src/bibliography.adoc + extensions: + - [Smstateen, "1.0.0"] + - [Smcsrind, "1.0.0"] + - [Sscsrind, "1.0.0"] + - [Smepmp, "1.0.0"] + - [Smcntrpmf, "1.0.0"] + - [Smrnmi, "0.5.0"] + - [Smcdeleg, "1.0.0"] + - [S, "1.12.0"] + - [Sm, "1.12.0"] + - [Smhpm, "1.12.0"] + - [Smpmp, "1.12.0"] + - [Sv32, "1.12.0"] + - [Sv39, "1.12.0"] + - [Sv48, "1.12.0"] + - [Sv57, "1.12.0"] + - [Svnapot, "1.0.0"] + - [Svpbmt, "1.0.0"] + - [Svinval, "1.0.0"] + - [Svadu, "1.0.0"] + - [Svvptc, "1.0.0"] + - [Sstc, "1.0.0"] + - [Sscofpmf, "1.0.0"] + - [H, "1.0.0"] diff --git a/arch/profile_release/MockProfileRelease.yaml b/arch/profile_release/MockProfileRelease.yaml index 6b18b173de..8d75ea6e2e 100644 --- a/arch/profile_release/MockProfileRelease.yaml +++ b/arch/profile_release/MockProfileRelease.yaml @@ -5,19 +5,19 @@ MockProfileRelease: release: 20 state: ratified # current status ["ratified", "development"] versions: - - version: "1.0" + - version: "1.0" ratification_date: "2024-01-01" introduction: Here's the Mock Profile Release introduction. description: | This is the Mock Profile Release description. It can be longer than the introduction since it gets its own sub-heading. contributors: - - name: Joe Blow - email: joe.blow@riscv.org - company: Acme Inc - - name: Jane Doe - email: jane.doe@gmail.com - company: Universal Imports + - name: Joe Blow + email: joe.blow@riscv.org + company: Acme Inc + - name: Jane Doe + email: jane.doe@gmail.com + company: Universal Imports profiles: MP-U-64: marketing_name: MockProfile 64-bit Unpriv @@ -41,9 +41,9 @@ MockProfileRelease: base: 64 release: MockProfileRelease contributors: - - name: Micky Mouse - email: micky@disney.com - company: Disney + - name: Micky Mouse + email: micky@disney.com + company: Disney extensions: $inherits: "#/MockProfileRelease/profiles/MP-U-64/extensions" A: @@ -69,32 +69,32 @@ MockProfileRelease: version: "~> 1.11" note: Made this a transitory option extra_notes: - - presence: mandatory - text: | - Here's the first extra note for the mandatory extensions section. - This note is multiple lines. - - presence: optional - text: | - Here's the first extra note for the optional extensions section. - In this case, we don't differentiate between optional types. - This note is multiple lines. - - presence: - optional: localized - text: Here's the first extra note for the localized optional extensions section. - - presence: - optional: localized - text: Here's the second extra note for the localized optional extensions section. - - presence: - optional: development - text: Here's the first extra note for the development optional extensions section. - - presence: - optional: expansion - text: Here's the first extra note for the expansion optional extensions section. - - presence: - optional: transitory - text: Here's the first extra note for the transitory optional extensions section. + - presence: mandatory + text: | + Here's the first extra note for the mandatory extensions section. + This note is multiple lines. + - presence: optional + text: | + Here's the first extra note for the optional extensions section. + In this case, we don't differentiate between optional types. + This note is multiple lines. + - presence: + optional: localized + text: Here's the first extra note for the localized optional extensions section. + - presence: + optional: localized + text: Here's the second extra note for the localized optional extensions section. + - presence: + optional: development + text: Here's the first extra note for the development optional extensions section. + - presence: + optional: expansion + text: Here's the first extra note for the expansion optional extensions section. + - presence: + optional: transitory + text: Here's the first extra note for the transitory optional extensions section. recommendations: - - text: | - Implementations are strongly recommended to raise illegal-instruction - exceptions on attempts to execute unimplemented opcodes. - - text: Micky should give Pluto an extra treat + - text: | + Implementations are strongly recommended to raise illegal-instruction + exceptions on attempts to execute unimplemented opcodes. + - text: Micky should give Pluto an extra treat diff --git a/arch/profile_release/RVA20.yaml b/arch/profile_release/RVA20.yaml index b920ef7176..162aba9010 100644 --- a/arch/profile_release/RVA20.yaml +++ b/arch/profile_release/RVA20.yaml @@ -8,7 +8,7 @@ RVA20: # Semantic versions within the release versions: - - version: "1.0.0" + - version: "1.0.0" introduction: | This profile release targets 64-bit application processors for markets @@ -28,9 +28,9 @@ RVA20: NOTE: Only XLEN=64 application processor profiles are currently defined. It would be possible to also define very similar XLEN=32 variants. contributors: - - name: Krste Asanovic - email: krste@sifive.com - company: SiFive + - name: Krste Asanovic + email: krste@sifive.com + company: SiFive profiles: RVA20U64: marketing_name: RVA20U64 @@ -44,7 +44,7 @@ RVA20: terms of the amount of software that targets this profile. extensions: $inherits: "profile_release/RVI20.yaml#/RVI20/profiles/RVI20U64/extensions" - $remove: Zifencei # Not allowed as an option for Unpriv ISA (only available in Priv ISA). + $remove: Zifencei # Not allowed as an option for Unpriv ISA (only available in Priv ISA). A: presence: mandatory C: @@ -98,36 +98,36 @@ RVA20: distributions should assume their existence only for correctness, not for performance. extra_notes: - - presence: optional - text: | - The rationale to not make Q an optional extension is that - quad-precision floating-point is unlikely to be implemented in - hardware, and so we do not require or expect A-profile software to - expend effort optimizing use of Q instructions in case they are - present. - - presence: optional - text: | - Zifencei is not classed as a supported option in the user-mode - profile because it is not sufficient by itself to produce the desired - effect in a multiprogrammed multiprocessor environment without OS - support, and so the instruction cache flush should always be performed - using an OS call rather than using the `fence.i` instruction. - `fence.i` semantics can be expensive to implement for some hardware - memory hierarchy designs, and so alternative non-standard - instruction-cache coherence mechanisms can be used behind the OS - abstraction. A separate extension is being developed for more general - and efficient instruction cache coherence. - - presence: optional - text: | - The execution environment must provide a means to synchronize writes to - instruction memory with instruction fetches, the implementation of which - likely relies on the Zifencei extension. - For example, RISC-V Linux supplies the `__riscv_flush_icache` system call and - a corresponding vDSO call. + - presence: optional + text: | + The rationale to not make Q an optional extension is that + quad-precision floating-point is unlikely to be implemented in + hardware, and so we do not require or expect A-profile software to + expend effort optimizing use of Q instructions in case they are + present. + - presence: optional + text: | + Zifencei is not classed as a supported option in the user-mode + profile because it is not sufficient by itself to produce the desired + effect in a multiprogrammed multiprocessor environment without OS + support, and so the instruction cache flush should always be performed + using an OS call rather than using the `fence.i` instruction. + `fence.i` semantics can be expensive to implement for some hardware + memory hierarchy designs, and so alternative non-standard + instruction-cache coherence mechanisms can be used behind the OS + abstraction. A separate extension is being developed for more general + and efficient instruction cache coherence. + - presence: optional + text: | + The execution environment must provide a means to synchronize writes to + instruction memory with instruction fetches, the implementation of which + likely relies on the Zifencei extension. + For example, RISC-V Linux supplies the `__riscv_flush_icache` system call and + a corresponding vDSO call. recommendations: - - text: | - Implementations are strongly recommended to raise illegal-instruction - exceptions on attempts to execute unimplemented opcodes. + - text: | + Implementations are strongly recommended to raise illegal-instruction + exceptions on attempts to execute unimplemented opcodes. RVA20S64: marketing_name: RVA20S64 mode: S diff --git a/arch/profile_release/RVA22.yaml b/arch/profile_release/RVA22.yaml index 3df8200624..045779aef7 100644 --- a/arch/profile_release/RVA22.yaml +++ b/arch/profile_release/RVA22.yaml @@ -8,7 +8,7 @@ RVA22: # Semantic versions within the release versions: - - version: "1.0.0" + - version: "1.0.0" introduction: | This profile release targets 64-bit application processors for markets @@ -28,9 +28,9 @@ RVA22: NOTE: Only XLEN=64 application processor profiles are currently defined. It would be possible to also define very similar XLEN=32 variants. contributors: - - name: Krste Asanovic - email: krste@sifive.com - company: SiFive + - name: Krste Asanovic + email: krste@sifive.com + company: SiFive profiles: RVA22U64: marketing_name: RVA22U64 @@ -133,33 +133,33 @@ RVA22: presence: optional version: "~> 1.0" extra_notes: - - presence: optional - text: | - The scalar crypto extensions are expected to be superseded by - vector crypto standards in future profiles, and the scalar extensions - may be removed as supported options once vector crypto is present. - - presence: optional - text: | - The smaller component scalar crypto extensions (Zbc, Zbkb, Zbkc, - Zbkx, Zknd, Zkne, Zknh, Zksed, Zksh) are not provided as separate - options in the profile. Profile implementers should provide all of - the instructions in a given algorithm suite as part of the Zkn or Zks - supported options. - - presence: optional - text: | - Access to the entropy source (Zkr) in a system is usually - carefully controlled. While the design supports unprivileged access - to the entropy source, this is unlikely to be commonly used in an - application processor, and so Zkr was not added as a profile option. - This also means the roll-up Zk was not added as a profile option. - - presence: optional - text: | - The Zfinx, Zdinx, Zhinx, Zhinxmin extensions are incompatible - with the profile mandates to support the F and D extensions. + - presence: optional + text: | + The scalar crypto extensions are expected to be superseded by + vector crypto standards in future profiles, and the scalar extensions + may be removed as supported options once vector crypto is present. + - presence: optional + text: | + The smaller component scalar crypto extensions (Zbc, Zbkb, Zbkc, + Zbkx, Zknd, Zkne, Zknh, Zksed, Zksh) are not provided as separate + options in the profile. Profile implementers should provide all of + the instructions in a given algorithm suite as part of the Zkn or Zks + supported options. + - presence: optional + text: | + Access to the entropy source (Zkr) in a system is usually + carefully controlled. While the design supports unprivileged access + to the entropy source, this is unlikely to be commonly used in an + application processor, and so Zkr was not added as a profile option. + This also means the roll-up Zk was not added as a profile option. + - presence: optional + text: | + The Zfinx, Zdinx, Zhinx, Zhinxmin extensions are incompatible + with the profile mandates to support the F and D extensions. recommendations: - - text: | - Implementations are strongly recommended to raise illegal-instruction - exceptions on attempts to execute unimplemented opcodes. + - text: | + Implementations are strongly recommended to raise illegal-instruction + exceptions on attempts to execute unimplemented opcodes. RVA22S64: marketing_name: RVA22S64 mode: S @@ -263,6 +263,6 @@ RVA22: * Shvstvecd * Shgatpa recommendations: - - text: | - Implementations are strongly recommended to raise illegal-instruction - exceptions on attempts to execute unimplemented opcodes. + - text: | + Implementations are strongly recommended to raise illegal-instruction + exceptions on attempts to execute unimplemented opcodes. diff --git a/arch/profile_release/RVI20.yaml b/arch/profile_release/RVI20.yaml index 3bd5b67504..3c3b1f63d9 100644 --- a/arch/profile_release/RVI20.yaml +++ b/arch/profile_release/RVI20.yaml @@ -8,14 +8,14 @@ RVI20: # Semantic versions within the release versions: - - version: "1.0.0" + - version: "1.0.0" introduction: | The two profiles RVI20U32 and RVI20U64 correspond to the RV32I and RV64I base ISAs respectively. contributors: - - name: Krste Asanovic - email: krste@sifive.com - company: SiFive + - name: Krste Asanovic + email: krste@sifive.com + company: SiFive profiles: RVI20U32: marketing_name: RVI20U32 @@ -80,9 +80,9 @@ RVI20: presence: optional version: "~> 2.0" recommendations: - - text: | - Implementations are strongly recommended to raise illegal-instruction - exceptions on attempts to execute unimplemented opcodes. + - text: | + Implementations are strongly recommended to raise illegal-instruction + exceptions on attempts to execute unimplemented opcodes. RVI20U64: $inherits: "#/RVI20/profiles/RVI20U32" base: 64 diff --git a/cfgs/generic_rv64/arch_overlay/csr/mcustom0.yaml b/cfgs/generic_rv64/arch_overlay/csr/mcustom0.yaml index f0f01d376a..81aabeed36 100644 --- a/cfgs/generic_rv64/arch_overlay/csr/mcustom0.yaml +++ b/cfgs/generic_rv64/arch_overlay/csr/mcustom0.yaml @@ -1,5 +1,4 @@ # yaml-language-server: $schema=../../../../schemas/csr_schema.json - --- $schema: "csr_schema.json#" kind: csr diff --git a/cfgs/generic_rv64/arch_overlay/ext/Xcustom.yaml b/cfgs/generic_rv64/arch_overlay/ext/Xcustom.yaml index 80aa49d40f..1579a46a64 100644 --- a/cfgs/generic_rv64/arch_overlay/ext/Xcustom.yaml +++ b/cfgs/generic_rv64/arch_overlay/ext/Xcustom.yaml @@ -5,8 +5,8 @@ name: Xcustom long_name: A new custom extension! type: unprivileged versions: -- version: "0.1.0" - ratification_date: null - state: development + - version: "0.1.0" + ratification_date: null + state: development description: | A new custom extension! diff --git a/cfgs/generic_rv64/params.yaml b/cfgs/generic_rv64/params.yaml index ace3ee74d5..b7f97c19fc 100644 --- a/cfgs/generic_rv64/params.yaml +++ b/cfgs/generic_rv64/params.yaml @@ -1,4 +1,3 @@ - --- params: XLEN: 64 @@ -32,43 +31,43 @@ params: MISALIGNED_AMO: false HPM_COUNTER_EN: - - false # CY - - false # empty - - false # IR - - true # HPM3 - - true # HPM4 - - true # HPM5 - - true # HPM6 - - true # HPM7 - - true # HPM8 - - true # HPM9 - - true # HPM10 - - false # HPM11 - - false # HPM12 - - false # HPM13 - - false # HPM14 - - false # HPM15 - - false # HPM16 - - false # HPM17 - - false # HPM18 - - false # HPM19 - - false # HPM20 - - false # HPM21 - - false # HPM22 - - false # HPM23 - - false # HPM24 - - false # HPM25 - - false # HPM26 - - false # HPM27 - - false # HPM28 - - false # HPM29 - - false # HPM30 - - false # HPM31 + - false # CY + - false # empty + - false # IR + - true # HPM3 + - true # HPM4 + - true # HPM5 + - true # HPM6 + - true # HPM7 + - true # HPM8 + - true # HPM9 + - true # HPM10 + - false # HPM11 + - false # HPM12 + - false # HPM13 + - false # HPM14 + - false # HPM15 + - false # HPM16 + - false # HPM17 + - false # HPM18 + - false # HPM19 + - false # HPM20 + - false # HPM21 + - false # HPM22 + - false # HPM23 + - false # HPM24 + - false # HPM25 + - false # HPM26 + - false # HPM27 + - false # HPM28 + - false # HPM29 + - false # HPM30 + - false # HPM31 # list of defined HPM events HPM_EVENTS: - - 0 - - 3 + - 0 + - 3 # Indicates which counters can be disabled from mcountinhibit # @@ -77,38 +76,38 @@ params: # 11 in COUNTINHIBIT_EN since the highest implemented counter # would be at bit 10 COUNTINHIBIT_EN: - - true # CY - - false # empty - - true # IR - - true # HPM3 - - true # HPM4 - - true # HPM5 - - true # HPM6 - - true # HPM7 - - true # HPM8 - - true # HPM9 - - true # HPM10 - - false # HPM11 - - false # HPM12 - - false # HPM13 - - false # HPM14 - - false # HPM15 - - false # HPM16 - - false # HPM17 - - false # HPM18 - - false # HPM19 - - false # HPM20 - - false # HPM21 - - false # HPM22 - - false # HPM23 - - false # HPM24 - - false # HPM25 - - false # HPM26 - - false # HPM27 - - false # HPM28 - - false # HPM29 - - false # HPM30 - - false # HPM31 + - true # CY + - false # empty + - true # IR + - true # HPM3 + - true # HPM4 + - true # HPM5 + - true # HPM6 + - true # HPM7 + - true # HPM8 + - true # HPM9 + - true # HPM10 + - false # HPM11 + - false # HPM12 + - false # HPM13 + - false # HPM14 + - false # HPM15 + - false # HPM16 + - false # HPM17 + - false # HPM18 + - false # HPM19 + - false # HPM20 + - false # HPM21 + - false # HPM22 + - false # HPM23 + - false # HPM24 + - false # HPM25 + - false # HPM26 + - false # HPM27 + - false # HPM28 + - false # HPM29 + - false # HPM30 + - false # HPM31 # Indicates which counters can delegated via mcounteren # @@ -117,38 +116,38 @@ params: # 11 in COUNTEN_EN since the highest implemented counter # would be at bit 10 MCOUNTENABLE_EN: - - true # CY - - false # TM - - true # IR - - true # HPM3 - - true # HPM4 - - true # HPM5 - - true # HPM6 - - true # HPM7 - - true # HPM8 - - true # HPM9 - - true # HPM10 - - false # HPM11 - - false # HPM12 - - false # HPM13 - - false # HPM14 - - false # HPM15 - - false # HPM16 - - false # HPM17 - - false # HPM18 - - false # HPM19 - - false # HPM20 - - false # HPM21 - - false # HPM22 - - false # HPM23 - - false # HPM24 - - false # HPM25 - - false # HPM26 - - false # HPM27 - - false # HPM28 - - false # HPM29 - - false # HPM30 - - false # HPM31 + - true # CY + - false # TM + - true # IR + - true # HPM3 + - true # HPM4 + - true # HPM5 + - true # HPM6 + - true # HPM7 + - true # HPM8 + - true # HPM9 + - true # HPM10 + - false # HPM11 + - false # HPM12 + - false # HPM13 + - false # HPM14 + - false # HPM15 + - false # HPM16 + - false # HPM17 + - false # HPM18 + - false # HPM19 + - false # HPM20 + - false # HPM21 + - false # HPM22 + - false # HPM23 + - false # HPM24 + - false # HPM25 + - false # HPM26 + - false # HPM27 + - false # HPM28 + - false # HPM29 + - false # HPM30 + - false # HPM31 # Indicates which counters can delegated via scounteren # @@ -157,38 +156,38 @@ params: # 11 in COUNTEN_EN since the highest implemented counter # would be at bit 10 SCOUNTENABLE_EN: - - true # CY - - false # TM - - true # IR - - true # HPM3 - - true # HPM4 - - true # HPM5 - - true # HPM6 - - true # HPM7 - - true # HPM8 - - true # HPM9 - - true # HPM10 - - false # HPM11 - - false # HPM12 - - false # HPM13 - - false # HPM14 - - false # HPM15 - - false # HPM16 - - false # HPM17 - - false # HPM18 - - false # HPM19 - - false # HPM20 - - false # HPM21 - - false # HPM22 - - false # HPM23 - - false # HPM24 - - false # HPM25 - - false # HPM26 - - false # HPM27 - - false # HPM28 - - false # HPM29 - - false # HPM30 - - false # HPM31 + - true # CY + - false # TM + - true # IR + - true # HPM3 + - true # HPM4 + - true # HPM5 + - true # HPM6 + - true # HPM7 + - true # HPM8 + - true # HPM9 + - true # HPM10 + - false # HPM11 + - false # HPM12 + - false # HPM13 + - false # HPM14 + - false # HPM15 + - false # HPM16 + - false # HPM17 + - false # HPM18 + - false # HPM19 + - false # HPM20 + - false # HPM21 + - false # HPM22 + - false # HPM23 + - false # HPM24 + - false # HPM25 + - false # HPM26 + - false # HPM27 + - false # HPM28 + - false # HPM29 + - false # HPM30 + - false # HPM31 # Indicates which counters can delegated via hcounteren # @@ -197,38 +196,38 @@ params: # 11 in COUNTEN_EN since the highest implemented counter # would be at bit 10 HCOUNTENABLE_EN: - - true # CY - - false # TM - - true # IR - - true # HPM3 - - true # HPM4 - - true # HPM5 - - true # HPM6 - - true # HPM7 - - true # HPM8 - - true # HPM9 - - true # HPM10 - - false # HPM11 - - false # HPM12 - - false # HPM13 - - false # HPM14 - - false # HPM15 - - false # HPM16 - - false # HPM17 - - false # HPM18 - - false # HPM19 - - false # HPM20 - - false # HPM21 - - false # HPM22 - - false # HPM23 - - false # HPM24 - - false # HPM25 - - false # HPM26 - - false # HPM27 - - false # HPM28 - - false # HPM29 - - false # HPM30 - - false # HPM31 + - true # CY + - false # TM + - true # IR + - true # HPM3 + - true # HPM4 + - true # HPM5 + - true # HPM6 + - true # HPM7 + - true # HPM8 + - true # HPM9 + - true # HPM10 + - false # HPM11 + - false # HPM12 + - false # HPM13 + - false # HPM14 + - false # HPM15 + - false # HPM16 + - false # HPM17 + - false # HPM18 + - false # HPM19 + - false # HPM20 + - false # HPM21 + - false # HPM22 + - false # HPM23 + - false # HPM24 + - false # HPM25 + - false # HPM26 + - false # HPM27 + - false # HPM28 + - false # HPM29 + - false # HPM30 + - false # HPM31 # when true, writing an illegal value to a WLRL CSR field raises an Illegal Instruction exception # when false, writing an illegal value to a WLRL CSR field is ignored @@ -291,7 +290,6 @@ params: # REPORT_CAUSE_IN_VSTVAL_ON_SOFTWARE_CHECK: true # VSTVAL_WIDTH not needed; "vstval is a WARL register that must be able to hold the same set of values that stval can hold" - # address of the unified discovery configuration data structure # this address is reported in the mconfigptr CSR CONFIG_PTR_ADDRESS: 0x1000 @@ -510,11 +508,11 @@ params: TINST_VALUE_ON_LOAD_PAGE_FAULT: "always zero" TINST_VALUE_ON_STORE_AMO_PAGE_FAULT: "always zero" MTVEC_MODES: [0, 1] - MSTATUS_FS_LEGAL_VALUES: [0,1,2,3] + MSTATUS_FS_LEGAL_VALUES: [0, 1, 2, 3] MSTATUS_FS_WRITEABLE: true MSTATUS_TVM_IMPLEMENTED: true HW_MSTATUS_FS_DIRTY_UPDATE: precise MSTATUS_VS_WRITEABLE: true - MSTATUS_VS_LEGAL_VALUES: [0,1,2,3] + MSTATUS_VS_LEGAL_VALUES: [0, 1, 2, 3] HW_MSTATUS_VS_DIRTY_UPDATE: precise FORCE_UPGRADE_CBO_INVAL_TO_FLUSH: true