diff --git a/arch/csr/Smrnmi/mncause.yaml b/arch/csr/Smrnmi/mncause.yaml new file mode 100644 index 0000000000..fa0ad9cd63 --- /dev/null +++ b/arch/csr/Smrnmi/mncause.yaml @@ -0,0 +1,43 @@ +# yaml-language-server: $schema=../../../schemas/csr_schema.json + +$schema: csr_schema.json# +kind: csr +name: mncause +long_name: Resumable NMI cause +address: 0x742 +priv_mode: M +length: MXLEN +definedBy: Smrnmi +description: | + The mncause CSR holds the reason for the NMI. + If the reason is an interrupt, bit MXLEN-1 is set to 1, and the NMI cause is encoded in + the least-significant bits. + If the reason is an interrupt and NMI causes are not supported, + bit MXLEN-1 is set to 1, and zero is written to the least-significant bits. + If the reason is an exception within M-mode that results in a double trap as + specified in the Smdbltrp extension, bit MXLEN-1 is set to 0 and the least-significant + bits are set to the cause code corresponding to the exception that precipitated the + double trap. +fields: + INT: + location_rv32: 31 + location_rv64: 63 + description: | + Written by hardware when a resumable NMI is taken into M-mode. + + When set, the last non-maskable exception was caused by an asynchronous Interrupt. + + [when,"TRAP_ON_ILLEGAL_WLRL == true"] + If `mcause` is written with an undefined cause (combination of `mcause.INT` and `mcause.CODE`), an `Illegal Instruction` exception occurs. + + [when,"TRAP_ON_ILLEGAL_WLRL == false"] + If `mcause` is written with an undefined cause (combination of `mcause.INT` and `mcause.CODE`), neither `mcause.INT` nor `mcause.CODE` are modified. + type: RW-H + reset_value: UNDEFINED_LEGAL + CODE: + location_rv32: 30-0 + location_rv64: 62-0 + description: | + TODO + type: RW-H + reset_value: UNDEFINED_LEGAL diff --git a/backends/common_templates/adoc/csr.adoc.erb b/backends/common_templates/adoc/csr.adoc.erb index 5a082ac1e8..0f9187dede 100644 --- a/backends/common_templates/adoc/csr.adoc.erb +++ b/backends/common_templates/adoc/csr.adoc.erb @@ -67,7 +67,7 @@ This CSR has no fields. However, it must still exist (not cause an `Illegal Inst <%- csr.fields.each do |field| -%> [[<%=csr.name%>-<%=field.name%>-def]] -===== `<%= field.name %>` +=== `<%= field.name %>` [example] **** diff --git a/backends/ext_pdf_doc/tasks.rake b/backends/ext_pdf_doc/tasks.rake index fad64d6fa1..04a4b08569 100644 --- a/backends/ext_pdf_doc/tasks.rake +++ b/backends/ext_pdf_doc/tasks.rake @@ -55,6 +55,7 @@ rule %r{#{$root}/gen/ext_pdf_doc/.*/pdf/.*_extension\.pdf} => proc { |tname| config_name = Pathname.new(tname).relative_path_from("#{$root}/gen/ext_pdf_doc").to_s.split("/")[0] ext_name = Pathname.new(tname).basename(".pdf").to_s.split("_")[0..-2].join("_") [ + ENV["THEME"], "#{$root}/ext/docs-resources/themes/riscv-pdf.yml", "#{$root}/gen/ext_pdf_doc/#{config_name}/adoc/#{ext_name}_extension.adoc" ] @@ -70,7 +71,7 @@ rule %r{#{$root}/gen/ext_pdf_doc/.*/pdf/.*_extension\.pdf} => proc { |tname| "-v", "-a toc", "-a compress", - "-a pdf-theme=#{$root}/ext/docs-resources/themes/riscv-pdf.yml", + "-a pdf-theme=#{ENV['THEME']}", "-a pdf-fontsdir=#{$root}/ext/docs-resources/fonts", "-a imagesdir=#{$root}/ext/docs-resources/images", "-r asciidoctor-diagram", @@ -128,7 +129,7 @@ rule %r{#{$root}/gen/ext_pdf_doc/.*/adoc/.*_extension\.adoc} => proc { |tname| } do |t| config_name = Pathname.new(t.name).relative_path_from("#{$root}/gen/ext_pdf_doc").to_s.split("/")[0] - cfg_arch = cfg_arch_for("_") + cfg_arch = cfg_arch_for(config_name) ext_name = Pathname.new(t.name).basename(".adoc").to_s.split("_")[0..-2].join("_") @@ -143,11 +144,13 @@ rule %r{#{$root}/gen/ext_pdf_doc/.*/adoc/.*_extension\.adoc} => proc { |tname| ext.versions else vs = ext.versions.select do |ext_ver| - version_strs.include?(ext_ver.version_spec.to_s) + version_strs.any? { |v| v != "latest" && ext_ver.version_spec == VersionSpec.new(v) } end vs << ext.max_version if version_strs.include?("latest") vs.uniq end + raise "No version matches #{ENV['VERSION']}" if versions.empty? + max_version = versions.max { |a, b| a.version <=> b.version } FileUtils.mkdir_p File.dirname(t.name) File.write t.name, AsciidocUtils.resolve_links(cfg_arch.find_replace_links(erb.result(binding))) @@ -164,21 +167,28 @@ namespace :gen do * EXT - The extension name * CFG - The config name, required only when an overlay is required * VERSION - A list of versions to include. May also be "all" or "latest". + * THEME - path to an AsciidocPDF theme file. If not set, will use default RVI theme. Examples: - ./do gen:ext_pdf EXT=Xqci CFG=qc_iu VERSION=latest + ./do gen:ext_pdf EXT=Xqci CFG=qc_iu VERSION=latest THEME=cfgs/qc_iu/qc_theme.yaml ./do gen:ext_pdf EXT=B VERSION=all ./do gen:ext_pdf EXT=B VERSION=1.0.0 ./do gen:ext_pdf EXT=B VERSION=1.0.0,1.1.0 DESC - task :ext_pdf, [:extension] do |_t, args| + task :ext_pdf do raise ArgumentError, "Missing required argument EXT" if ENV["EXT"].nil? extension = ENV["EXT"] cfg = ENV["CFG"] version = ENV["VERSION"] + ENV["THEME"] = + if ENV["THEME"].nil? + "#{$root}/ext/docs-resources/themes/riscv-pdf.yml" + else + Pathname.new(ENV["THEME"]).realpath.to_s + end versions = version.split(",") raise ArgumentError, "Nothing else should be specified with 'all'" if versions.include?("all") && versions.size > 1 @@ -186,7 +196,7 @@ namespace :gen do if cfg.nil? Rake::Task[$root / "gen" / "ext_pdf_doc" / "_" / "pdf" / "#{extension}_extension.pdf"].invoke else - Rake::Task[$root / "gen" / "ext_pdf_doc" / cfg / "pdf" / "#{extension}_extension.pdf"].invoke(args) + Rake::Task[$root / "gen" / "ext_pdf_doc" / cfg / "pdf" / "#{extension}_extension.pdf"].invoke end end diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/gen_mcliciX.rb b/cfgs/qc_iu/arch_overlay/csr/Xqci/gen_mcliciX.rb new file mode 100644 index 0000000000..11dd988a75 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/gen_mcliciX.rb @@ -0,0 +1,58 @@ + +require 'erb' + +pend_template = <<~YAML + # yaml-language-server: $schema=../../../../../schemas/csr_schema.json + + qc_mclicip<%= num %>: + long_name: IRQ Pending <%= num %> + address: 0x<%= (0x7f0 + num).to_s(16) %> + length: 32 + priv_mode: M + base: 32 + definedBy: Xqci + description: | + Pending bits for IRQs <%= num*32 %>-<%= (num + 1)*32 - 1 %> + fields: + <%- 32.times do |i| -%> + IRQ<%= num*32 + i %>: + type: RW + reset_value: 0 + location: <%= i %> + description: IRQ<%= num*32 + i %> pending + <%- end -%> +YAML + +en_template = <<~YAML + # yaml-language-server: $schema=../../../../../schemas/csr_schema.json + + qc_mclicie<%= num %>: + long_name: IRQ Enable <%= num %> + address: 0x<%= (0x7f0 + num).to_s(16) %> + length: 32 + base: 32 + priv_mode: M + definedBy: Xqci + description: | + Enable bits for IRQs <%= num*32 %>-<%= (num + 1)*32 - 1 %> + fields: + <%- 32.times do |i| -%> + IRQ<%= num*32 + i %>: + type: RW + reset_value: 0 + location: <%= i %> + description: IRQ<%= num*32 + i %> enabled + <%- end -%> +YAML + +root = File.dirname(__FILE__) + +erb = ERB.new(pend_template, trim_mode: '-') +8.times do |num| + File.write("#{root}/qc_mclicip#{num}.yaml", erb.result(binding)) +end + +erb = ERB.new(en_template, trim_mode: '-') +8.times do |num| + File.write("#{root}/qc_mclicie#{num}.yaml", erb.result(binding)) +end diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_flags.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_flags.yaml new file mode 100644 index 0000000000..0a06f9cfb4 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_flags.yaml @@ -0,0 +1,78 @@ +$schema: csr_schema.json# +kind: csr +name: qc_flags +long_name: Flags register (Condition Code Register + co-processor flags) +address: 0x803 +priv_mode: M +base: 32 +length: 32 +description: | + Condition Code Register with condition codes, plus a co-processor flags (_e.g._, to support floating point) +definedBy: Xqci +fields: + CPFLAGS: + location: 31-16 + description: | + Co-Processor FLAGS: comprocessor-dependednt context (used to support floating point, for example) + type: RW-H + reset_value: 0 + LTU: + location: 9 + description: | + Less Then (Unsigned) flag + type: RW-H + reset_value: 0 + GEU: + location: 8 + description: | + Greater or Equal (Unsigned) flag + type: RW-H + reset_value: 0 + LEU: + location: 7 + description: | + Less or Equal (Unsigned) flag + type: RW-H + reset_value: 0 + GTU: + location: 6 + description: | + Greater Then (Unsigned) flag + type: RW-H + reset_value: 0 + LT: + location: 5 + description: | + Less Then flag + type: RW-H + reset_value: 0 + GE: + location: 4 + description: | + Greater or Equal flag + type: RW-H + reset_value: 0 + LE: + location: 3 + description: | + Less or Equal flag + type: RW-H + reset_value: 0 + GT: + location: 2 + description: | + Greater Than flag + type: RW-H + reset_value: 0 + NE: + location: 1 + description: | + Not Equal flag + type: RW-H + reset_value: 0 + EQ: + location: 0 + description: | + EQual flag + type: RW-H + reset_value: 0 diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie0.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie0.yaml new file mode 100644 index 0000000000..67e1074a4e --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie0.yaml @@ -0,0 +1,174 @@ +# yaml-language-server: $schema=../../../../../schemas/csr_schema.json + +$schema: csr_schema.json# +kind: csr +name: qc_mclicie0 +long_name: IRQ Enable 0 +address: 0x7f0 +length: 32 +base: 32 +priv_mode: M +definedBy: Xqci +description: | + Enable bits for IRQs 0-31 +fields: + IRQ0: + type: RW + reset_value: 0 + location: 0 + description: IRQ0 enabled + IRQ1: + type: RW + reset_value: 0 + location: 1 + description: IRQ1 enabled + IRQ2: + type: RW + reset_value: 0 + location: 2 + description: IRQ2 enabled + IRQ3: + type: RW + reset_value: 0 + location: 3 + description: IRQ3 enabled + IRQ4: + type: RW + reset_value: 0 + location: 4 + description: IRQ4 enabled + IRQ5: + type: RW + reset_value: 0 + location: 5 + description: IRQ5 enabled + IRQ6: + type: RW + reset_value: 0 + location: 6 + description: IRQ6 enabled + IRQ7: + type: RW + reset_value: 0 + location: 7 + description: IRQ7 enabled + IRQ8: + type: RW + reset_value: 0 + location: 8 + description: IRQ8 enabled + IRQ9: + type: RW + reset_value: 0 + location: 9 + description: IRQ9 enabled + IRQ10: + type: RW + reset_value: 0 + location: 10 + description: IRQ10 enabled + IRQ11: + type: RW + reset_value: 0 + location: 11 + description: IRQ11 enabled + IRQ12: + type: RW + reset_value: 0 + location: 12 + description: IRQ12 enabled + IRQ13: + type: RW + reset_value: 0 + location: 13 + description: IRQ13 enabled + IRQ14: + type: RW + reset_value: 0 + location: 14 + description: IRQ14 enabled + IRQ15: + type: RW + reset_value: 0 + location: 15 + description: IRQ15 enabled + IRQ16: + type: RW + reset_value: 0 + location: 16 + description: IRQ16 enabled + IRQ17: + type: RW + reset_value: 0 + location: 17 + description: IRQ17 enabled + IRQ18: + type: RW + reset_value: 0 + location: 18 + description: IRQ18 enabled + IRQ19: + type: RW + reset_value: 0 + location: 19 + description: IRQ19 enabled + IRQ20: + type: RW + reset_value: 0 + location: 20 + description: IRQ20 enabled + IRQ21: + type: RW + reset_value: 0 + location: 21 + description: IRQ21 enabled + IRQ22: + type: RW + reset_value: 0 + location: 22 + description: IRQ22 enabled + IRQ23: + type: RW + reset_value: 0 + location: 23 + description: IRQ23 enabled + IRQ24: + type: RW + reset_value: 0 + location: 24 + description: IRQ24 enabled + IRQ25: + type: RW + reset_value: 0 + location: 25 + description: IRQ25 enabled + IRQ26: + type: RW + reset_value: 0 + location: 26 + description: IRQ26 enabled + IRQ27: + type: RW + reset_value: 0 + location: 27 + description: IRQ27 enabled + IRQ28: + type: RW + reset_value: 0 + location: 28 + description: IRQ28 enabled + IRQ29: + type: RW + reset_value: 0 + location: 29 + description: IRQ29 enabled + IRQ30: + type: RW + reset_value: 0 + location: 30 + description: IRQ30 enabled + IRQ31: + type: RW + reset_value: 0 + location: 31 + description: IRQ31 enabled diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie1.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie1.yaml new file mode 100644 index 0000000000..93310b5a3a --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie1.yaml @@ -0,0 +1,174 @@ +# yaml-language-server: $schema=../../../../../schemas/csr_schema.json + +$schema: csr_schema.json# +kind: csr +name: qc_mclicie1 +long_name: IRQ Enable 1 +address: 0x7f1 +length: 32 +base: 32 +priv_mode: M +definedBy: Xqci +description: | + Enable bits for IRQs 32-63 +fields: + IRQ32: + type: RW + reset_value: 0 + location: 0 + description: IRQ32 enabled + IRQ33: + type: RW + reset_value: 0 + location: 1 + description: IRQ33 enabled + IRQ34: + type: RW + reset_value: 0 + location: 2 + description: IRQ34 enabled + IRQ35: + type: RW + reset_value: 0 + location: 3 + description: IRQ35 enabled + IRQ36: + type: RW + reset_value: 0 + location: 4 + description: IRQ36 enabled + IRQ37: + type: RW + reset_value: 0 + location: 5 + description: IRQ37 enabled + IRQ38: + type: RW + reset_value: 0 + location: 6 + description: IRQ38 enabled + IRQ39: + type: RW + reset_value: 0 + location: 7 + description: IRQ39 enabled + IRQ40: + type: RW + reset_value: 0 + location: 8 + description: IRQ40 enabled + IRQ41: + type: RW + reset_value: 0 + location: 9 + description: IRQ41 enabled + IRQ42: + type: RW + reset_value: 0 + location: 10 + description: IRQ42 enabled + IRQ43: + type: RW + reset_value: 0 + location: 11 + description: IRQ43 enabled + IRQ44: + type: RW + reset_value: 0 + location: 12 + description: IRQ44 enabled + IRQ45: + type: RW + reset_value: 0 + location: 13 + description: IRQ45 enabled + IRQ46: + type: RW + reset_value: 0 + location: 14 + description: IRQ46 enabled + IRQ47: + type: RW + reset_value: 0 + location: 15 + description: IRQ47 enabled + IRQ48: + type: RW + reset_value: 0 + location: 16 + description: IRQ48 enabled + IRQ49: + type: RW + reset_value: 0 + location: 17 + description: IRQ49 enabled + IRQ50: + type: RW + reset_value: 0 + location: 18 + description: IRQ50 enabled + IRQ51: + type: RW + reset_value: 0 + location: 19 + description: IRQ51 enabled + IRQ52: + type: RW + reset_value: 0 + location: 20 + description: IRQ52 enabled + IRQ53: + type: RW + reset_value: 0 + location: 21 + description: IRQ53 enabled + IRQ54: + type: RW + reset_value: 0 + location: 22 + description: IRQ54 enabled + IRQ55: + type: RW + reset_value: 0 + location: 23 + description: IRQ55 enabled + IRQ56: + type: RW + reset_value: 0 + location: 24 + description: IRQ56 enabled + IRQ57: + type: RW + reset_value: 0 + location: 25 + description: IRQ57 enabled + IRQ58: + type: RW + reset_value: 0 + location: 26 + description: IRQ58 enabled + IRQ59: + type: RW + reset_value: 0 + location: 27 + description: IRQ59 enabled + IRQ60: + type: RW + reset_value: 0 + location: 28 + description: IRQ60 enabled + IRQ61: + type: RW + reset_value: 0 + location: 29 + description: IRQ61 enabled + IRQ62: + type: RW + reset_value: 0 + location: 30 + description: IRQ62 enabled + IRQ63: + type: RW + reset_value: 0 + location: 31 + description: IRQ63 enabled diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie2.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie2.yaml new file mode 100644 index 0000000000..d5b0f0420a --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie2.yaml @@ -0,0 +1,174 @@ +# yaml-language-server: $schema=../../../../../schemas/csr_schema.json + +$schema: csr_schema.json# +kind: csr +name: qc_mclicie2 +long_name: IRQ Enable 2 +address: 0x7f2 +length: 32 +base: 32 +priv_mode: M +definedBy: Xqci +description: | + Enable bits for IRQs 64-95 +fields: + IRQ64: + type: RW + reset_value: 0 + location: 0 + description: IRQ64 enabled + IRQ65: + type: RW + reset_value: 0 + location: 1 + description: IRQ65 enabled + IRQ66: + type: RW + reset_value: 0 + location: 2 + description: IRQ66 enabled + IRQ67: + type: RW + reset_value: 0 + location: 3 + description: IRQ67 enabled + IRQ68: + type: RW + reset_value: 0 + location: 4 + description: IRQ68 enabled + IRQ69: + type: RW + reset_value: 0 + location: 5 + description: IRQ69 enabled + IRQ70: + type: RW + reset_value: 0 + location: 6 + description: IRQ70 enabled + IRQ71: + type: RW + reset_value: 0 + location: 7 + description: IRQ71 enabled + IRQ72: + type: RW + reset_value: 0 + location: 8 + description: IRQ72 enabled + IRQ73: + type: RW + reset_value: 0 + location: 9 + description: IRQ73 enabled + IRQ74: + type: RW + reset_value: 0 + location: 10 + description: IRQ74 enabled + IRQ75: + type: RW + reset_value: 0 + location: 11 + description: IRQ75 enabled + IRQ76: + type: RW + reset_value: 0 + location: 12 + description: IRQ76 enabled + IRQ77: + type: RW + reset_value: 0 + location: 13 + description: IRQ77 enabled + IRQ78: + type: RW + reset_value: 0 + location: 14 + description: IRQ78 enabled + IRQ79: + type: RW + reset_value: 0 + location: 15 + description: IRQ79 enabled + IRQ80: + type: RW + reset_value: 0 + location: 16 + description: IRQ80 enabled + IRQ81: + type: RW + reset_value: 0 + location: 17 + description: IRQ81 enabled + IRQ82: + type: RW + reset_value: 0 + location: 18 + description: IRQ82 enabled + IRQ83: + type: RW + reset_value: 0 + location: 19 + description: IRQ83 enabled + IRQ84: + type: RW + reset_value: 0 + location: 20 + description: IRQ84 enabled + IRQ85: + type: RW + reset_value: 0 + location: 21 + description: IRQ85 enabled + IRQ86: + type: RW + reset_value: 0 + location: 22 + description: IRQ86 enabled + IRQ87: + type: RW + reset_value: 0 + location: 23 + description: IRQ87 enabled + IRQ88: + type: RW + reset_value: 0 + location: 24 + description: IRQ88 enabled + IRQ89: + type: RW + reset_value: 0 + location: 25 + description: IRQ89 enabled + IRQ90: + type: RW + reset_value: 0 + location: 26 + description: IRQ90 enabled + IRQ91: + type: RW + reset_value: 0 + location: 27 + description: IRQ91 enabled + IRQ92: + type: RW + reset_value: 0 + location: 28 + description: IRQ92 enabled + IRQ93: + type: RW + reset_value: 0 + location: 29 + description: IRQ93 enabled + IRQ94: + type: RW + reset_value: 0 + location: 30 + description: IRQ94 enabled + IRQ95: + type: RW + reset_value: 0 + location: 31 + description: IRQ95 enabled diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie3.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie3.yaml new file mode 100644 index 0000000000..809335febc --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie3.yaml @@ -0,0 +1,174 @@ +# yaml-language-server: $schema=../../../../../schemas/csr_schema.json + +$schema: csr_schema.json# +kind: csr +name: qc_mclicie3 +long_name: IRQ Enable 3 +address: 0x7f3 +length: 32 +base: 32 +priv_mode: M +definedBy: Xqci +description: | + Enable bits for IRQs 96-127 +fields: + IRQ96: + type: RW + reset_value: 0 + location: 0 + description: IRQ96 enabled + IRQ97: + type: RW + reset_value: 0 + location: 1 + description: IRQ97 enabled + IRQ98: + type: RW + reset_value: 0 + location: 2 + description: IRQ98 enabled + IRQ99: + type: RW + reset_value: 0 + location: 3 + description: IRQ99 enabled + IRQ100: + type: RW + reset_value: 0 + location: 4 + description: IRQ100 enabled + IRQ101: + type: RW + reset_value: 0 + location: 5 + description: IRQ101 enabled + IRQ102: + type: RW + reset_value: 0 + location: 6 + description: IRQ102 enabled + IRQ103: + type: RW + reset_value: 0 + location: 7 + description: IRQ103 enabled + IRQ104: + type: RW + reset_value: 0 + location: 8 + description: IRQ104 enabled + IRQ105: + type: RW + reset_value: 0 + location: 9 + description: IRQ105 enabled + IRQ106: + type: RW + reset_value: 0 + location: 10 + description: IRQ106 enabled + IRQ107: + type: RW + reset_value: 0 + location: 11 + description: IRQ107 enabled + IRQ108: + type: RW + reset_value: 0 + location: 12 + description: IRQ108 enabled + IRQ109: + type: RW + reset_value: 0 + location: 13 + description: IRQ109 enabled + IRQ110: + type: RW + reset_value: 0 + location: 14 + description: IRQ110 enabled + IRQ111: + type: RW + reset_value: 0 + location: 15 + description: IRQ111 enabled + IRQ112: + type: RW + reset_value: 0 + location: 16 + description: IRQ112 enabled + IRQ113: + type: RW + reset_value: 0 + location: 17 + description: IRQ113 enabled + IRQ114: + type: RW + reset_value: 0 + location: 18 + description: IRQ114 enabled + IRQ115: + type: RW + reset_value: 0 + location: 19 + description: IRQ115 enabled + IRQ116: + type: RW + reset_value: 0 + location: 20 + description: IRQ116 enabled + IRQ117: + type: RW + reset_value: 0 + location: 21 + description: IRQ117 enabled + IRQ118: + type: RW + reset_value: 0 + location: 22 + description: IRQ118 enabled + IRQ119: + type: RW + reset_value: 0 + location: 23 + description: IRQ119 enabled + IRQ120: + type: RW + reset_value: 0 + location: 24 + description: IRQ120 enabled + IRQ121: + type: RW + reset_value: 0 + location: 25 + description: IRQ121 enabled + IRQ122: + type: RW + reset_value: 0 + location: 26 + description: IRQ122 enabled + IRQ123: + type: RW + reset_value: 0 + location: 27 + description: IRQ123 enabled + IRQ124: + type: RW + reset_value: 0 + location: 28 + description: IRQ124 enabled + IRQ125: + type: RW + reset_value: 0 + location: 29 + description: IRQ125 enabled + IRQ126: + type: RW + reset_value: 0 + location: 30 + description: IRQ126 enabled + IRQ127: + type: RW + reset_value: 0 + location: 31 + description: IRQ127 enabled diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie4.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie4.yaml new file mode 100644 index 0000000000..ad7b3e806a --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie4.yaml @@ -0,0 +1,174 @@ +# yaml-language-server: $schema=../../../../../schemas/csr_schema.json + +$schema: csr_schema.json# +kind: csr +name: qc_mclicie4 +long_name: IRQ Enable 4 +address: 0x7f4 +length: 32 +base: 32 +priv_mode: M +definedBy: Xqci +description: | + Enable bits for IRQs 128-159 +fields: + IRQ128: + type: RW + reset_value: 0 + location: 0 + description: IRQ128 enabled + IRQ129: + type: RW + reset_value: 0 + location: 1 + description: IRQ129 enabled + IRQ130: + type: RW + reset_value: 0 + location: 2 + description: IRQ130 enabled + IRQ131: + type: RW + reset_value: 0 + location: 3 + description: IRQ131 enabled + IRQ132: + type: RW + reset_value: 0 + location: 4 + description: IRQ132 enabled + IRQ133: + type: RW + reset_value: 0 + location: 5 + description: IRQ133 enabled + IRQ134: + type: RW + reset_value: 0 + location: 6 + description: IRQ134 enabled + IRQ135: + type: RW + reset_value: 0 + location: 7 + description: IRQ135 enabled + IRQ136: + type: RW + reset_value: 0 + location: 8 + description: IRQ136 enabled + IRQ137: + type: RW + reset_value: 0 + location: 9 + description: IRQ137 enabled + IRQ138: + type: RW + reset_value: 0 + location: 10 + description: IRQ138 enabled + IRQ139: + type: RW + reset_value: 0 + location: 11 + description: IRQ139 enabled + IRQ140: + type: RW + reset_value: 0 + location: 12 + description: IRQ140 enabled + IRQ141: + type: RW + reset_value: 0 + location: 13 + description: IRQ141 enabled + IRQ142: + type: RW + reset_value: 0 + location: 14 + description: IRQ142 enabled + IRQ143: + type: RW + reset_value: 0 + location: 15 + description: IRQ143 enabled + IRQ144: + type: RW + reset_value: 0 + location: 16 + description: IRQ144 enabled + IRQ145: + type: RW + reset_value: 0 + location: 17 + description: IRQ145 enabled + IRQ146: + type: RW + reset_value: 0 + location: 18 + description: IRQ146 enabled + IRQ147: + type: RW + reset_value: 0 + location: 19 + description: IRQ147 enabled + IRQ148: + type: RW + reset_value: 0 + location: 20 + description: IRQ148 enabled + IRQ149: + type: RW + reset_value: 0 + location: 21 + description: IRQ149 enabled + IRQ150: + type: RW + reset_value: 0 + location: 22 + description: IRQ150 enabled + IRQ151: + type: RW + reset_value: 0 + location: 23 + description: IRQ151 enabled + IRQ152: + type: RW + reset_value: 0 + location: 24 + description: IRQ152 enabled + IRQ153: + type: RW + reset_value: 0 + location: 25 + description: IRQ153 enabled + IRQ154: + type: RW + reset_value: 0 + location: 26 + description: IRQ154 enabled + IRQ155: + type: RW + reset_value: 0 + location: 27 + description: IRQ155 enabled + IRQ156: + type: RW + reset_value: 0 + location: 28 + description: IRQ156 enabled + IRQ157: + type: RW + reset_value: 0 + location: 29 + description: IRQ157 enabled + IRQ158: + type: RW + reset_value: 0 + location: 30 + description: IRQ158 enabled + IRQ159: + type: RW + reset_value: 0 + location: 31 + description: IRQ159 enabled diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie5.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie5.yaml new file mode 100644 index 0000000000..2c6aaee9f7 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie5.yaml @@ -0,0 +1,174 @@ +# yaml-language-server: $schema=../../../../../schemas/csr_schema.json + +$schema: csr_schema.json# +kind: csr +name: qc_mclicie5 +long_name: IRQ Enable 5 +address: 0x7f5 +length: 32 +base: 32 +priv_mode: M +definedBy: Xqci +description: | + Enable bits for IRQs 160-191 +fields: + IRQ160: + type: RW + reset_value: 0 + location: 0 + description: IRQ160 enabled + IRQ161: + type: RW + reset_value: 0 + location: 1 + description: IRQ161 enabled + IRQ162: + type: RW + reset_value: 0 + location: 2 + description: IRQ162 enabled + IRQ163: + type: RW + reset_value: 0 + location: 3 + description: IRQ163 enabled + IRQ164: + type: RW + reset_value: 0 + location: 4 + description: IRQ164 enabled + IRQ165: + type: RW + reset_value: 0 + location: 5 + description: IRQ165 enabled + IRQ166: + type: RW + reset_value: 0 + location: 6 + description: IRQ166 enabled + IRQ167: + type: RW + reset_value: 0 + location: 7 + description: IRQ167 enabled + IRQ168: + type: RW + reset_value: 0 + location: 8 + description: IRQ168 enabled + IRQ169: + type: RW + reset_value: 0 + location: 9 + description: IRQ169 enabled + IRQ170: + type: RW + reset_value: 0 + location: 10 + description: IRQ170 enabled + IRQ171: + type: RW + reset_value: 0 + location: 11 + description: IRQ171 enabled + IRQ172: + type: RW + reset_value: 0 + location: 12 + description: IRQ172 enabled + IRQ173: + type: RW + reset_value: 0 + location: 13 + description: IRQ173 enabled + IRQ174: + type: RW + reset_value: 0 + location: 14 + description: IRQ174 enabled + IRQ175: + type: RW + reset_value: 0 + location: 15 + description: IRQ175 enabled + IRQ176: + type: RW + reset_value: 0 + location: 16 + description: IRQ176 enabled + IRQ177: + type: RW + reset_value: 0 + location: 17 + description: IRQ177 enabled + IRQ178: + type: RW + reset_value: 0 + location: 18 + description: IRQ178 enabled + IRQ179: + type: RW + reset_value: 0 + location: 19 + description: IRQ179 enabled + IRQ180: + type: RW + reset_value: 0 + location: 20 + description: IRQ180 enabled + IRQ181: + type: RW + reset_value: 0 + location: 21 + description: IRQ181 enabled + IRQ182: + type: RW + reset_value: 0 + location: 22 + description: IRQ182 enabled + IRQ183: + type: RW + reset_value: 0 + location: 23 + description: IRQ183 enabled + IRQ184: + type: RW + reset_value: 0 + location: 24 + description: IRQ184 enabled + IRQ185: + type: RW + reset_value: 0 + location: 25 + description: IRQ185 enabled + IRQ186: + type: RW + reset_value: 0 + location: 26 + description: IRQ186 enabled + IRQ187: + type: RW + reset_value: 0 + location: 27 + description: IRQ187 enabled + IRQ188: + type: RW + reset_value: 0 + location: 28 + description: IRQ188 enabled + IRQ189: + type: RW + reset_value: 0 + location: 29 + description: IRQ189 enabled + IRQ190: + type: RW + reset_value: 0 + location: 30 + description: IRQ190 enabled + IRQ191: + type: RW + reset_value: 0 + location: 31 + description: IRQ191 enabled diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie6.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie6.yaml new file mode 100644 index 0000000000..bffa251af9 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie6.yaml @@ -0,0 +1,174 @@ +# yaml-language-server: $schema=../../../../../schemas/csr_schema.json + +$schema: csr_schema.json# +kind: csr +name: qc_mclicie6 +long_name: IRQ Enable 6 +address: 0x7f6 +length: 32 +base: 32 +priv_mode: M +definedBy: Xqci +description: | + Enable bits for IRQs 192-223 +fields: + IRQ192: + type: RW + reset_value: 0 + location: 0 + description: IRQ192 enabled + IRQ193: + type: RW + reset_value: 0 + location: 1 + description: IRQ193 enabled + IRQ194: + type: RW + reset_value: 0 + location: 2 + description: IRQ194 enabled + IRQ195: + type: RW + reset_value: 0 + location: 3 + description: IRQ195 enabled + IRQ196: + type: RW + reset_value: 0 + location: 4 + description: IRQ196 enabled + IRQ197: + type: RW + reset_value: 0 + location: 5 + description: IRQ197 enabled + IRQ198: + type: RW + reset_value: 0 + location: 6 + description: IRQ198 enabled + IRQ199: + type: RW + reset_value: 0 + location: 7 + description: IRQ199 enabled + IRQ200: + type: RW + reset_value: 0 + location: 8 + description: IRQ200 enabled + IRQ201: + type: RW + reset_value: 0 + location: 9 + description: IRQ201 enabled + IRQ202: + type: RW + reset_value: 0 + location: 10 + description: IRQ202 enabled + IRQ203: + type: RW + reset_value: 0 + location: 11 + description: IRQ203 enabled + IRQ204: + type: RW + reset_value: 0 + location: 12 + description: IRQ204 enabled + IRQ205: + type: RW + reset_value: 0 + location: 13 + description: IRQ205 enabled + IRQ206: + type: RW + reset_value: 0 + location: 14 + description: IRQ206 enabled + IRQ207: + type: RW + reset_value: 0 + location: 15 + description: IRQ207 enabled + IRQ208: + type: RW + reset_value: 0 + location: 16 + description: IRQ208 enabled + IRQ209: + type: RW + reset_value: 0 + location: 17 + description: IRQ209 enabled + IRQ210: + type: RW + reset_value: 0 + location: 18 + description: IRQ210 enabled + IRQ211: + type: RW + reset_value: 0 + location: 19 + description: IRQ211 enabled + IRQ212: + type: RW + reset_value: 0 + location: 20 + description: IRQ212 enabled + IRQ213: + type: RW + reset_value: 0 + location: 21 + description: IRQ213 enabled + IRQ214: + type: RW + reset_value: 0 + location: 22 + description: IRQ214 enabled + IRQ215: + type: RW + reset_value: 0 + location: 23 + description: IRQ215 enabled + IRQ216: + type: RW + reset_value: 0 + location: 24 + description: IRQ216 enabled + IRQ217: + type: RW + reset_value: 0 + location: 25 + description: IRQ217 enabled + IRQ218: + type: RW + reset_value: 0 + location: 26 + description: IRQ218 enabled + IRQ219: + type: RW + reset_value: 0 + location: 27 + description: IRQ219 enabled + IRQ220: + type: RW + reset_value: 0 + location: 28 + description: IRQ220 enabled + IRQ221: + type: RW + reset_value: 0 + location: 29 + description: IRQ221 enabled + IRQ222: + type: RW + reset_value: 0 + location: 30 + description: IRQ222 enabled + IRQ223: + type: RW + reset_value: 0 + location: 31 + description: IRQ223 enabled diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie7.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie7.yaml new file mode 100644 index 0000000000..9898db8b59 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie7.yaml @@ -0,0 +1,174 @@ +# yaml-language-server: $schema=../../../../../schemas/csr_schema.json + +$schema: csr_schema.json# +kind: csr +name: qc_mclicie7 +long_name: IRQ Enable 7 +address: 0x7f7 +length: 32 +base: 32 +priv_mode: M +definedBy: Xqci +description: | + Enable bits for IRQs 224-255 +fields: + IRQ224: + type: RW + reset_value: 0 + location: 0 + description: IRQ224 enabled + IRQ225: + type: RW + reset_value: 0 + location: 1 + description: IRQ225 enabled + IRQ226: + type: RW + reset_value: 0 + location: 2 + description: IRQ226 enabled + IRQ227: + type: RW + reset_value: 0 + location: 3 + description: IRQ227 enabled + IRQ228: + type: RW + reset_value: 0 + location: 4 + description: IRQ228 enabled + IRQ229: + type: RW + reset_value: 0 + location: 5 + description: IRQ229 enabled + IRQ230: + type: RW + reset_value: 0 + location: 6 + description: IRQ230 enabled + IRQ231: + type: RW + reset_value: 0 + location: 7 + description: IRQ231 enabled + IRQ232: + type: RW + reset_value: 0 + location: 8 + description: IRQ232 enabled + IRQ233: + type: RW + reset_value: 0 + location: 9 + description: IRQ233 enabled + IRQ234: + type: RW + reset_value: 0 + location: 10 + description: IRQ234 enabled + IRQ235: + type: RW + reset_value: 0 + location: 11 + description: IRQ235 enabled + IRQ236: + type: RW + reset_value: 0 + location: 12 + description: IRQ236 enabled + IRQ237: + type: RW + reset_value: 0 + location: 13 + description: IRQ237 enabled + IRQ238: + type: RW + reset_value: 0 + location: 14 + description: IRQ238 enabled + IRQ239: + type: RW + reset_value: 0 + location: 15 + description: IRQ239 enabled + IRQ240: + type: RW + reset_value: 0 + location: 16 + description: IRQ240 enabled + IRQ241: + type: RW + reset_value: 0 + location: 17 + description: IRQ241 enabled + IRQ242: + type: RW + reset_value: 0 + location: 18 + description: IRQ242 enabled + IRQ243: + type: RW + reset_value: 0 + location: 19 + description: IRQ243 enabled + IRQ244: + type: RW + reset_value: 0 + location: 20 + description: IRQ244 enabled + IRQ245: + type: RW + reset_value: 0 + location: 21 + description: IRQ245 enabled + IRQ246: + type: RW + reset_value: 0 + location: 22 + description: IRQ246 enabled + IRQ247: + type: RW + reset_value: 0 + location: 23 + description: IRQ247 enabled + IRQ248: + type: RW + reset_value: 0 + location: 24 + description: IRQ248 enabled + IRQ249: + type: RW + reset_value: 0 + location: 25 + description: IRQ249 enabled + IRQ250: + type: RW + reset_value: 0 + location: 26 + description: IRQ250 enabled + IRQ251: + type: RW + reset_value: 0 + location: 27 + description: IRQ251 enabled + IRQ252: + type: RW + reset_value: 0 + location: 28 + description: IRQ252 enabled + IRQ253: + type: RW + reset_value: 0 + location: 29 + description: IRQ253 enabled + IRQ254: + type: RW + reset_value: 0 + location: 30 + description: IRQ254 enabled + IRQ255: + type: RW + reset_value: 0 + location: 31 + description: IRQ255 enabled diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip0.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip0.yaml new file mode 100644 index 0000000000..6dc1fcecf1 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip0.yaml @@ -0,0 +1,174 @@ +# yaml-language-server: $schema=../../../../../schemas/csr_schema.json + +$schema: csr_schema.json# +kind: csr +name: qc_mclicip0 +long_name: IRQ Pending 0 +address: 0x7f0 +length: 32 +priv_mode: M +base: 32 +definedBy: Xqci +description: | + Pending bits for IRQs 0-31 +fields: + IRQ0: + type: RW + reset_value: 0 + location: 0 + description: IRQ0 pending + IRQ1: + type: RW + reset_value: 0 + location: 1 + description: IRQ1 pending + IRQ2: + type: RW + reset_value: 0 + location: 2 + description: IRQ2 pending + IRQ3: + type: RW + reset_value: 0 + location: 3 + description: IRQ3 pending + IRQ4: + type: RW + reset_value: 0 + location: 4 + description: IRQ4 pending + IRQ5: + type: RW + reset_value: 0 + location: 5 + description: IRQ5 pending + IRQ6: + type: RW + reset_value: 0 + location: 6 + description: IRQ6 pending + IRQ7: + type: RW + reset_value: 0 + location: 7 + description: IRQ7 pending + IRQ8: + type: RW + reset_value: 0 + location: 8 + description: IRQ8 pending + IRQ9: + type: RW + reset_value: 0 + location: 9 + description: IRQ9 pending + IRQ10: + type: RW + reset_value: 0 + location: 10 + description: IRQ10 pending + IRQ11: + type: RW + reset_value: 0 + location: 11 + description: IRQ11 pending + IRQ12: + type: RW + reset_value: 0 + location: 12 + description: IRQ12 pending + IRQ13: + type: RW + reset_value: 0 + location: 13 + description: IRQ13 pending + IRQ14: + type: RW + reset_value: 0 + location: 14 + description: IRQ14 pending + IRQ15: + type: RW + reset_value: 0 + location: 15 + description: IRQ15 pending + IRQ16: + type: RW + reset_value: 0 + location: 16 + description: IRQ16 pending + IRQ17: + type: RW + reset_value: 0 + location: 17 + description: IRQ17 pending + IRQ18: + type: RW + reset_value: 0 + location: 18 + description: IRQ18 pending + IRQ19: + type: RW + reset_value: 0 + location: 19 + description: IRQ19 pending + IRQ20: + type: RW + reset_value: 0 + location: 20 + description: IRQ20 pending + IRQ21: + type: RW + reset_value: 0 + location: 21 + description: IRQ21 pending + IRQ22: + type: RW + reset_value: 0 + location: 22 + description: IRQ22 pending + IRQ23: + type: RW + reset_value: 0 + location: 23 + description: IRQ23 pending + IRQ24: + type: RW + reset_value: 0 + location: 24 + description: IRQ24 pending + IRQ25: + type: RW + reset_value: 0 + location: 25 + description: IRQ25 pending + IRQ26: + type: RW + reset_value: 0 + location: 26 + description: IRQ26 pending + IRQ27: + type: RW + reset_value: 0 + location: 27 + description: IRQ27 pending + IRQ28: + type: RW + reset_value: 0 + location: 28 + description: IRQ28 pending + IRQ29: + type: RW + reset_value: 0 + location: 29 + description: IRQ29 pending + IRQ30: + type: RW + reset_value: 0 + location: 30 + description: IRQ30 pending + IRQ31: + type: RW + reset_value: 0 + location: 31 + description: IRQ31 pending diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip1.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip1.yaml new file mode 100644 index 0000000000..a3fe935cc7 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip1.yaml @@ -0,0 +1,174 @@ +# yaml-language-server: $schema=../../../../../schemas/csr_schema.json + +$schema: csr_schema.json# +kind: csr +name: qc_mclicip1 +long_name: IRQ Pending 1 +address: 0x7f1 +length: 32 +priv_mode: M +base: 32 +definedBy: Xqci +description: | + Pending bits for IRQs 32-63 +fields: + IRQ32: + type: RW + reset_value: 0 + location: 0 + description: IRQ32 pending + IRQ33: + type: RW + reset_value: 0 + location: 1 + description: IRQ33 pending + IRQ34: + type: RW + reset_value: 0 + location: 2 + description: IRQ34 pending + IRQ35: + type: RW + reset_value: 0 + location: 3 + description: IRQ35 pending + IRQ36: + type: RW + reset_value: 0 + location: 4 + description: IRQ36 pending + IRQ37: + type: RW + reset_value: 0 + location: 5 + description: IRQ37 pending + IRQ38: + type: RW + reset_value: 0 + location: 6 + description: IRQ38 pending + IRQ39: + type: RW + reset_value: 0 + location: 7 + description: IRQ39 pending + IRQ40: + type: RW + reset_value: 0 + location: 8 + description: IRQ40 pending + IRQ41: + type: RW + reset_value: 0 + location: 9 + description: IRQ41 pending + IRQ42: + type: RW + reset_value: 0 + location: 10 + description: IRQ42 pending + IRQ43: + type: RW + reset_value: 0 + location: 11 + description: IRQ43 pending + IRQ44: + type: RW + reset_value: 0 + location: 12 + description: IRQ44 pending + IRQ45: + type: RW + reset_value: 0 + location: 13 + description: IRQ45 pending + IRQ46: + type: RW + reset_value: 0 + location: 14 + description: IRQ46 pending + IRQ47: + type: RW + reset_value: 0 + location: 15 + description: IRQ47 pending + IRQ48: + type: RW + reset_value: 0 + location: 16 + description: IRQ48 pending + IRQ49: + type: RW + reset_value: 0 + location: 17 + description: IRQ49 pending + IRQ50: + type: RW + reset_value: 0 + location: 18 + description: IRQ50 pending + IRQ51: + type: RW + reset_value: 0 + location: 19 + description: IRQ51 pending + IRQ52: + type: RW + reset_value: 0 + location: 20 + description: IRQ52 pending + IRQ53: + type: RW + reset_value: 0 + location: 21 + description: IRQ53 pending + IRQ54: + type: RW + reset_value: 0 + location: 22 + description: IRQ54 pending + IRQ55: + type: RW + reset_value: 0 + location: 23 + description: IRQ55 pending + IRQ56: + type: RW + reset_value: 0 + location: 24 + description: IRQ56 pending + IRQ57: + type: RW + reset_value: 0 + location: 25 + description: IRQ57 pending + IRQ58: + type: RW + reset_value: 0 + location: 26 + description: IRQ58 pending + IRQ59: + type: RW + reset_value: 0 + location: 27 + description: IRQ59 pending + IRQ60: + type: RW + reset_value: 0 + location: 28 + description: IRQ60 pending + IRQ61: + type: RW + reset_value: 0 + location: 29 + description: IRQ61 pending + IRQ62: + type: RW + reset_value: 0 + location: 30 + description: IRQ62 pending + IRQ63: + type: RW + reset_value: 0 + location: 31 + description: IRQ63 pending diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip2.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip2.yaml new file mode 100644 index 0000000000..f53932a7c5 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip2.yaml @@ -0,0 +1,174 @@ +# yaml-language-server: $schema=../../../../../schemas/csr_schema.json + +$schema: csr_schema.json# +kind: csr +name: qc_mclicip2 +long_name: IRQ Pending 2 +address: 0x7f2 +length: 32 +priv_mode: M +base: 32 +definedBy: Xqci +description: | + Pending bits for IRQs 64-95 +fields: + IRQ64: + type: RW + reset_value: 0 + location: 0 + description: IRQ64 pending + IRQ65: + type: RW + reset_value: 0 + location: 1 + description: IRQ65 pending + IRQ66: + type: RW + reset_value: 0 + location: 2 + description: IRQ66 pending + IRQ67: + type: RW + reset_value: 0 + location: 3 + description: IRQ67 pending + IRQ68: + type: RW + reset_value: 0 + location: 4 + description: IRQ68 pending + IRQ69: + type: RW + reset_value: 0 + location: 5 + description: IRQ69 pending + IRQ70: + type: RW + reset_value: 0 + location: 6 + description: IRQ70 pending + IRQ71: + type: RW + reset_value: 0 + location: 7 + description: IRQ71 pending + IRQ72: + type: RW + reset_value: 0 + location: 8 + description: IRQ72 pending + IRQ73: + type: RW + reset_value: 0 + location: 9 + description: IRQ73 pending + IRQ74: + type: RW + reset_value: 0 + location: 10 + description: IRQ74 pending + IRQ75: + type: RW + reset_value: 0 + location: 11 + description: IRQ75 pending + IRQ76: + type: RW + reset_value: 0 + location: 12 + description: IRQ76 pending + IRQ77: + type: RW + reset_value: 0 + location: 13 + description: IRQ77 pending + IRQ78: + type: RW + reset_value: 0 + location: 14 + description: IRQ78 pending + IRQ79: + type: RW + reset_value: 0 + location: 15 + description: IRQ79 pending + IRQ80: + type: RW + reset_value: 0 + location: 16 + description: IRQ80 pending + IRQ81: + type: RW + reset_value: 0 + location: 17 + description: IRQ81 pending + IRQ82: + type: RW + reset_value: 0 + location: 18 + description: IRQ82 pending + IRQ83: + type: RW + reset_value: 0 + location: 19 + description: IRQ83 pending + IRQ84: + type: RW + reset_value: 0 + location: 20 + description: IRQ84 pending + IRQ85: + type: RW + reset_value: 0 + location: 21 + description: IRQ85 pending + IRQ86: + type: RW + reset_value: 0 + location: 22 + description: IRQ86 pending + IRQ87: + type: RW + reset_value: 0 + location: 23 + description: IRQ87 pending + IRQ88: + type: RW + reset_value: 0 + location: 24 + description: IRQ88 pending + IRQ89: + type: RW + reset_value: 0 + location: 25 + description: IRQ89 pending + IRQ90: + type: RW + reset_value: 0 + location: 26 + description: IRQ90 pending + IRQ91: + type: RW + reset_value: 0 + location: 27 + description: IRQ91 pending + IRQ92: + type: RW + reset_value: 0 + location: 28 + description: IRQ92 pending + IRQ93: + type: RW + reset_value: 0 + location: 29 + description: IRQ93 pending + IRQ94: + type: RW + reset_value: 0 + location: 30 + description: IRQ94 pending + IRQ95: + type: RW + reset_value: 0 + location: 31 + description: IRQ95 pending diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip3.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip3.yaml new file mode 100644 index 0000000000..1726552ee6 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip3.yaml @@ -0,0 +1,174 @@ +# yaml-language-server: $schema=../../../../../schemas/csr_schema.json + +$schema: csr_schema.json# +kind: csr +name: qc_mclicip3 +long_name: IRQ Pending 3 +address: 0x7f3 +length: 32 +priv_mode: M +base: 32 +definedBy: Xqci +description: | + Pending bits for IRQs 96-127 +fields: + IRQ96: + type: RW + reset_value: 0 + location: 0 + description: IRQ96 pending + IRQ97: + type: RW + reset_value: 0 + location: 1 + description: IRQ97 pending + IRQ98: + type: RW + reset_value: 0 + location: 2 + description: IRQ98 pending + IRQ99: + type: RW + reset_value: 0 + location: 3 + description: IRQ99 pending + IRQ100: + type: RW + reset_value: 0 + location: 4 + description: IRQ100 pending + IRQ101: + type: RW + reset_value: 0 + location: 5 + description: IRQ101 pending + IRQ102: + type: RW + reset_value: 0 + location: 6 + description: IRQ102 pending + IRQ103: + type: RW + reset_value: 0 + location: 7 + description: IRQ103 pending + IRQ104: + type: RW + reset_value: 0 + location: 8 + description: IRQ104 pending + IRQ105: + type: RW + reset_value: 0 + location: 9 + description: IRQ105 pending + IRQ106: + type: RW + reset_value: 0 + location: 10 + description: IRQ106 pending + IRQ107: + type: RW + reset_value: 0 + location: 11 + description: IRQ107 pending + IRQ108: + type: RW + reset_value: 0 + location: 12 + description: IRQ108 pending + IRQ109: + type: RW + reset_value: 0 + location: 13 + description: IRQ109 pending + IRQ110: + type: RW + reset_value: 0 + location: 14 + description: IRQ110 pending + IRQ111: + type: RW + reset_value: 0 + location: 15 + description: IRQ111 pending + IRQ112: + type: RW + reset_value: 0 + location: 16 + description: IRQ112 pending + IRQ113: + type: RW + reset_value: 0 + location: 17 + description: IRQ113 pending + IRQ114: + type: RW + reset_value: 0 + location: 18 + description: IRQ114 pending + IRQ115: + type: RW + reset_value: 0 + location: 19 + description: IRQ115 pending + IRQ116: + type: RW + reset_value: 0 + location: 20 + description: IRQ116 pending + IRQ117: + type: RW + reset_value: 0 + location: 21 + description: IRQ117 pending + IRQ118: + type: RW + reset_value: 0 + location: 22 + description: IRQ118 pending + IRQ119: + type: RW + reset_value: 0 + location: 23 + description: IRQ119 pending + IRQ120: + type: RW + reset_value: 0 + location: 24 + description: IRQ120 pending + IRQ121: + type: RW + reset_value: 0 + location: 25 + description: IRQ121 pending + IRQ122: + type: RW + reset_value: 0 + location: 26 + description: IRQ122 pending + IRQ123: + type: RW + reset_value: 0 + location: 27 + description: IRQ123 pending + IRQ124: + type: RW + reset_value: 0 + location: 28 + description: IRQ124 pending + IRQ125: + type: RW + reset_value: 0 + location: 29 + description: IRQ125 pending + IRQ126: + type: RW + reset_value: 0 + location: 30 + description: IRQ126 pending + IRQ127: + type: RW + reset_value: 0 + location: 31 + description: IRQ127 pending diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip4.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip4.yaml new file mode 100644 index 0000000000..40eb770e5f --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip4.yaml @@ -0,0 +1,174 @@ +# yaml-language-server: $schema=../../../../../schemas/csr_schema.json + +$schema: csr_schema.json# +kind: csr +name: qc_mclicip4 +long_name: IRQ Pending 4 +address: 0x7f4 +length: 32 +priv_mode: M +base: 32 +definedBy: Xqci +description: | + Pending bits for IRQs 128-159 +fields: + IRQ128: + type: RW + reset_value: 0 + location: 0 + description: IRQ128 pending + IRQ129: + type: RW + reset_value: 0 + location: 1 + description: IRQ129 pending + IRQ130: + type: RW + reset_value: 0 + location: 2 + description: IRQ130 pending + IRQ131: + type: RW + reset_value: 0 + location: 3 + description: IRQ131 pending + IRQ132: + type: RW + reset_value: 0 + location: 4 + description: IRQ132 pending + IRQ133: + type: RW + reset_value: 0 + location: 5 + description: IRQ133 pending + IRQ134: + type: RW + reset_value: 0 + location: 6 + description: IRQ134 pending + IRQ135: + type: RW + reset_value: 0 + location: 7 + description: IRQ135 pending + IRQ136: + type: RW + reset_value: 0 + location: 8 + description: IRQ136 pending + IRQ137: + type: RW + reset_value: 0 + location: 9 + description: IRQ137 pending + IRQ138: + type: RW + reset_value: 0 + location: 10 + description: IRQ138 pending + IRQ139: + type: RW + reset_value: 0 + location: 11 + description: IRQ139 pending + IRQ140: + type: RW + reset_value: 0 + location: 12 + description: IRQ140 pending + IRQ141: + type: RW + reset_value: 0 + location: 13 + description: IRQ141 pending + IRQ142: + type: RW + reset_value: 0 + location: 14 + description: IRQ142 pending + IRQ143: + type: RW + reset_value: 0 + location: 15 + description: IRQ143 pending + IRQ144: + type: RW + reset_value: 0 + location: 16 + description: IRQ144 pending + IRQ145: + type: RW + reset_value: 0 + location: 17 + description: IRQ145 pending + IRQ146: + type: RW + reset_value: 0 + location: 18 + description: IRQ146 pending + IRQ147: + type: RW + reset_value: 0 + location: 19 + description: IRQ147 pending + IRQ148: + type: RW + reset_value: 0 + location: 20 + description: IRQ148 pending + IRQ149: + type: RW + reset_value: 0 + location: 21 + description: IRQ149 pending + IRQ150: + type: RW + reset_value: 0 + location: 22 + description: IRQ150 pending + IRQ151: + type: RW + reset_value: 0 + location: 23 + description: IRQ151 pending + IRQ152: + type: RW + reset_value: 0 + location: 24 + description: IRQ152 pending + IRQ153: + type: RW + reset_value: 0 + location: 25 + description: IRQ153 pending + IRQ154: + type: RW + reset_value: 0 + location: 26 + description: IRQ154 pending + IRQ155: + type: RW + reset_value: 0 + location: 27 + description: IRQ155 pending + IRQ156: + type: RW + reset_value: 0 + location: 28 + description: IRQ156 pending + IRQ157: + type: RW + reset_value: 0 + location: 29 + description: IRQ157 pending + IRQ158: + type: RW + reset_value: 0 + location: 30 + description: IRQ158 pending + IRQ159: + type: RW + reset_value: 0 + location: 31 + description: IRQ159 pending diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip5.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip5.yaml new file mode 100644 index 0000000000..8482078fb4 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip5.yaml @@ -0,0 +1,174 @@ +# yaml-language-server: $schema=../../../../../schemas/csr_schema.json + +$schema: csr_schema.json# +kind: csr +name: qc_mclicip5 +long_name: IRQ Pending 5 +address: 0x7f5 +length: 32 +priv_mode: M +base: 32 +definedBy: Xqci +description: | + Pending bits for IRQs 160-191 +fields: + IRQ160: + type: RW + reset_value: 0 + location: 0 + description: IRQ160 pending + IRQ161: + type: RW + reset_value: 0 + location: 1 + description: IRQ161 pending + IRQ162: + type: RW + reset_value: 0 + location: 2 + description: IRQ162 pending + IRQ163: + type: RW + reset_value: 0 + location: 3 + description: IRQ163 pending + IRQ164: + type: RW + reset_value: 0 + location: 4 + description: IRQ164 pending + IRQ165: + type: RW + reset_value: 0 + location: 5 + description: IRQ165 pending + IRQ166: + type: RW + reset_value: 0 + location: 6 + description: IRQ166 pending + IRQ167: + type: RW + reset_value: 0 + location: 7 + description: IRQ167 pending + IRQ168: + type: RW + reset_value: 0 + location: 8 + description: IRQ168 pending + IRQ169: + type: RW + reset_value: 0 + location: 9 + description: IRQ169 pending + IRQ170: + type: RW + reset_value: 0 + location: 10 + description: IRQ170 pending + IRQ171: + type: RW + reset_value: 0 + location: 11 + description: IRQ171 pending + IRQ172: + type: RW + reset_value: 0 + location: 12 + description: IRQ172 pending + IRQ173: + type: RW + reset_value: 0 + location: 13 + description: IRQ173 pending + IRQ174: + type: RW + reset_value: 0 + location: 14 + description: IRQ174 pending + IRQ175: + type: RW + reset_value: 0 + location: 15 + description: IRQ175 pending + IRQ176: + type: RW + reset_value: 0 + location: 16 + description: IRQ176 pending + IRQ177: + type: RW + reset_value: 0 + location: 17 + description: IRQ177 pending + IRQ178: + type: RW + reset_value: 0 + location: 18 + description: IRQ178 pending + IRQ179: + type: RW + reset_value: 0 + location: 19 + description: IRQ179 pending + IRQ180: + type: RW + reset_value: 0 + location: 20 + description: IRQ180 pending + IRQ181: + type: RW + reset_value: 0 + location: 21 + description: IRQ181 pending + IRQ182: + type: RW + reset_value: 0 + location: 22 + description: IRQ182 pending + IRQ183: + type: RW + reset_value: 0 + location: 23 + description: IRQ183 pending + IRQ184: + type: RW + reset_value: 0 + location: 24 + description: IRQ184 pending + IRQ185: + type: RW + reset_value: 0 + location: 25 + description: IRQ185 pending + IRQ186: + type: RW + reset_value: 0 + location: 26 + description: IRQ186 pending + IRQ187: + type: RW + reset_value: 0 + location: 27 + description: IRQ187 pending + IRQ188: + type: RW + reset_value: 0 + location: 28 + description: IRQ188 pending + IRQ189: + type: RW + reset_value: 0 + location: 29 + description: IRQ189 pending + IRQ190: + type: RW + reset_value: 0 + location: 30 + description: IRQ190 pending + IRQ191: + type: RW + reset_value: 0 + location: 31 + description: IRQ191 pending diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip6.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip6.yaml new file mode 100644 index 0000000000..a052056919 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip6.yaml @@ -0,0 +1,174 @@ +# yaml-language-server: $schema=../../../../../schemas/csr_schema.json + +$schema: csr_schema.json# +kind: csr +name: qc_mclicip6 +long_name: IRQ Pending 6 +address: 0x7f6 +length: 32 +priv_mode: M +base: 32 +definedBy: Xqci +description: | + Pending bits for IRQs 192-223 +fields: + IRQ192: + type: RW + reset_value: 0 + location: 0 + description: IRQ192 pending + IRQ193: + type: RW + reset_value: 0 + location: 1 + description: IRQ193 pending + IRQ194: + type: RW + reset_value: 0 + location: 2 + description: IRQ194 pending + IRQ195: + type: RW + reset_value: 0 + location: 3 + description: IRQ195 pending + IRQ196: + type: RW + reset_value: 0 + location: 4 + description: IRQ196 pending + IRQ197: + type: RW + reset_value: 0 + location: 5 + description: IRQ197 pending + IRQ198: + type: RW + reset_value: 0 + location: 6 + description: IRQ198 pending + IRQ199: + type: RW + reset_value: 0 + location: 7 + description: IRQ199 pending + IRQ200: + type: RW + reset_value: 0 + location: 8 + description: IRQ200 pending + IRQ201: + type: RW + reset_value: 0 + location: 9 + description: IRQ201 pending + IRQ202: + type: RW + reset_value: 0 + location: 10 + description: IRQ202 pending + IRQ203: + type: RW + reset_value: 0 + location: 11 + description: IRQ203 pending + IRQ204: + type: RW + reset_value: 0 + location: 12 + description: IRQ204 pending + IRQ205: + type: RW + reset_value: 0 + location: 13 + description: IRQ205 pending + IRQ206: + type: RW + reset_value: 0 + location: 14 + description: IRQ206 pending + IRQ207: + type: RW + reset_value: 0 + location: 15 + description: IRQ207 pending + IRQ208: + type: RW + reset_value: 0 + location: 16 + description: IRQ208 pending + IRQ209: + type: RW + reset_value: 0 + location: 17 + description: IRQ209 pending + IRQ210: + type: RW + reset_value: 0 + location: 18 + description: IRQ210 pending + IRQ211: + type: RW + reset_value: 0 + location: 19 + description: IRQ211 pending + IRQ212: + type: RW + reset_value: 0 + location: 20 + description: IRQ212 pending + IRQ213: + type: RW + reset_value: 0 + location: 21 + description: IRQ213 pending + IRQ214: + type: RW + reset_value: 0 + location: 22 + description: IRQ214 pending + IRQ215: + type: RW + reset_value: 0 + location: 23 + description: IRQ215 pending + IRQ216: + type: RW + reset_value: 0 + location: 24 + description: IRQ216 pending + IRQ217: + type: RW + reset_value: 0 + location: 25 + description: IRQ217 pending + IRQ218: + type: RW + reset_value: 0 + location: 26 + description: IRQ218 pending + IRQ219: + type: RW + reset_value: 0 + location: 27 + description: IRQ219 pending + IRQ220: + type: RW + reset_value: 0 + location: 28 + description: IRQ220 pending + IRQ221: + type: RW + reset_value: 0 + location: 29 + description: IRQ221 pending + IRQ222: + type: RW + reset_value: 0 + location: 30 + description: IRQ222 pending + IRQ223: + type: RW + reset_value: 0 + location: 31 + description: IRQ223 pending diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip7.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip7.yaml new file mode 100644 index 0000000000..c9332a57c0 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip7.yaml @@ -0,0 +1,174 @@ +# yaml-language-server: $schema=../../../../../schemas/csr_schema.json + +$schema: csr_schema.json# +kind: csr +name: qc_mclicip7 +long_name: IRQ Pending 7 +address: 0x7f7 +length: 32 +priv_mode: M +base: 32 +definedBy: Xqci +description: | + Pending bits for IRQs 224-255 +fields: + IRQ224: + type: RW + reset_value: 0 + location: 0 + description: IRQ224 pending + IRQ225: + type: RW + reset_value: 0 + location: 1 + description: IRQ225 pending + IRQ226: + type: RW + reset_value: 0 + location: 2 + description: IRQ226 pending + IRQ227: + type: RW + reset_value: 0 + location: 3 + description: IRQ227 pending + IRQ228: + type: RW + reset_value: 0 + location: 4 + description: IRQ228 pending + IRQ229: + type: RW + reset_value: 0 + location: 5 + description: IRQ229 pending + IRQ230: + type: RW + reset_value: 0 + location: 6 + description: IRQ230 pending + IRQ231: + type: RW + reset_value: 0 + location: 7 + description: IRQ231 pending + IRQ232: + type: RW + reset_value: 0 + location: 8 + description: IRQ232 pending + IRQ233: + type: RW + reset_value: 0 + location: 9 + description: IRQ233 pending + IRQ234: + type: RW + reset_value: 0 + location: 10 + description: IRQ234 pending + IRQ235: + type: RW + reset_value: 0 + location: 11 + description: IRQ235 pending + IRQ236: + type: RW + reset_value: 0 + location: 12 + description: IRQ236 pending + IRQ237: + type: RW + reset_value: 0 + location: 13 + description: IRQ237 pending + IRQ238: + type: RW + reset_value: 0 + location: 14 + description: IRQ238 pending + IRQ239: + type: RW + reset_value: 0 + location: 15 + description: IRQ239 pending + IRQ240: + type: RW + reset_value: 0 + location: 16 + description: IRQ240 pending + IRQ241: + type: RW + reset_value: 0 + location: 17 + description: IRQ241 pending + IRQ242: + type: RW + reset_value: 0 + location: 18 + description: IRQ242 pending + IRQ243: + type: RW + reset_value: 0 + location: 19 + description: IRQ243 pending + IRQ244: + type: RW + reset_value: 0 + location: 20 + description: IRQ244 pending + IRQ245: + type: RW + reset_value: 0 + location: 21 + description: IRQ245 pending + IRQ246: + type: RW + reset_value: 0 + location: 22 + description: IRQ246 pending + IRQ247: + type: RW + reset_value: 0 + location: 23 + description: IRQ247 pending + IRQ248: + type: RW + reset_value: 0 + location: 24 + description: IRQ248 pending + IRQ249: + type: RW + reset_value: 0 + location: 25 + description: IRQ249 pending + IRQ250: + type: RW + reset_value: 0 + location: 26 + description: IRQ250 pending + IRQ251: + type: RW + reset_value: 0 + location: 27 + description: IRQ251 pending + IRQ252: + type: RW + reset_value: 0 + location: 28 + description: IRQ252 pending + IRQ253: + type: RW + reset_value: 0 + location: 29 + description: IRQ253 pending + IRQ254: + type: RW + reset_value: 0 + location: 30 + description: IRQ254 pending + IRQ255: + type: RW + reset_value: 0 + location: 31 + description: IRQ255 pending diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mnepc.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mnepc.yaml new file mode 100644 index 0000000000..86a91a3ff5 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mnepc.yaml @@ -0,0 +1,30 @@ +$schema: csr_schema.json# +kind: csr +name: qc_mnepc +long_name: Machine Non-maskable Exception Program Counter +address: 0x7c1 +base: 32 +priv_mode: M +length: MXLEN +description: | + Written with the PC of the next instruction when a non-maskable interrupt taken in M-mode. +definedBy: Xqciint +fields: + PC: + location_rv32: 31-0 + location_rv64: 63-0 + description: | + When a non-maskable interrupt is taken into M-mode, `qc_mnepc.PC` is written with the PC + of the next instruction (_i.e._, the one that would be fetched next if the interrupt did not + occur). Otherwise, `qc_mnepc.PC` is never written by the implementation, though it may be + explicitly written by software. + type: RW-RH + sw_write(csr_value): | + return csr_value.PC & ~64'b1; + reset_value: 0 +sw_read(): | + if (implemented?(ExtensionName::C) && CSR[misa].C == 1'b1) { + return CSR[qc_mnepc].PC & ~64'b1; + } else { + return CSR[qc_mnepc].PC; + } diff --git a/cfgs/qc_iu/arch_overlay/csr/mcause.yaml b/cfgs/qc_iu/arch_overlay/csr/mcause.yaml new file mode 100644 index 0000000000..382bd410da --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/csr/mcause.yaml @@ -0,0 +1,17 @@ +$schema: csr_schema.json# +kind: csr +name: mcause +fields: + NMI: + location_rv32: 30 + location_rv64: 62 + description: | + *Non Maskable Interrupt processing* + + If 1'b1, currently processing NMI. + type: RW-H + reset_value: 0 + CODE: + location_rv32: 29-0 + location_rv64: 61-0 + reset_value: 0 diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqci.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqci.yaml new file mode 100644 index 0000000000..eaa3a15510 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/ext/Xqci.yaml @@ -0,0 +1,389 @@ +# yaml-language-server: $schema=../../../../schemas/ext_schema.json + +$schema: ext_schema.json# +kind: extension +name: Xqci +type: unprivileged +long_name: Qualcomm uC extensions +versions: +- version: "0.1.0" + state: development + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com +- version: "0.2.0" + state: development + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com + changes: + - Splits Xqci into sub-extensions based on instruction type + - Removed shXadd instructions in favor of generic shladd +- version: "0.3.0" + state: development + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com + changes: + - Rename extension and sub extensions to match toolchain guidelines + - Rename mnemonics to match toolchain guidelines + - Ensure every instruction belongs to at least one sub extension + implies: + - [Xqcia, "0.1.0"] + - [Xqciac, "0.1.0"] + - [Xqcibi, "0.1.0"] + - [Xqcibm, "0.1.0"] + - [Xqcicli, "0.1.0"] + - [Xqcicm, "0.1.0"] + - [Xqcics, "0.1.0"] + - [Xqcicsr, "0.1.0"] + - [Xqciint, "0.1.0"] + - [Xqcilb, "0.1.0"] + - [Xqcili, "0.1.0"] + - [Xqcilia, "0.1.0"] + - [Xqcilo, "0.1.0"] + - [Xqcilsm, "0.1.0"] + - [Xqcisls, "0.1.0"] +- version: "0.4.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com + changes: + - Add information about instruction formats of each instruction + - Fix description and functionality of qc.c.extu instruction + - Fix description and functionality of qc.shladd instruction + implies: + - [Xqcia, "0.2.0"] + - [Xqciac, "0.2.0"] + - [Xqcibi, "0.2.0"] + - [Xqcibm, "0.2.0"] + - [Xqcicli, "0.2.0"] + - [Xqcicm, "0.2.0"] + - [Xqcics, "0.2.0"] + - [Xqcicsr, "0.2.0"] + - [Xqciint, "0.2.0"] + - [Xqcilb, "0.2.0"] + - [Xqcili, "0.2.0"] + - [Xqcilia, "0.2.0"] + - [Xqcilo, "0.2.0"] + - [Xqcilsm, "0.2.0"] + - [Xqcisls, "0.2.0"] + requires: + name: Zca + version: ">= 1.0.0" +description: | + The Xqci extension includes a set of instructions that improve RISC-V code density and + performance in microontrollers. It fills several gaps: + + Long immediates:: + -- + This extension provides wide-immediate versions of + loads, stores, branches, jumps, and several arithemtic operations. + -- + + Addressing modes:: + -- + New indexed addressing modes are added for load and store instructions. + -- + + Load/store multiple:: + -- + Xqci adds instructions that load multiple sequential values from memory into multiple registers. + Analogous instructions for stores are also included. + -- + + Branch immediate instructions:: + -- + The base RISC-V ISA provides conditional branches that compare two register values. + Xqci adds conditional branch instructions that compare an immediate value to a register value, + reducing a common code sequence into a single instruction. + -- + + Conditional instructions:: + -- + Xqci includes a variety of conditional select instructions that pick one of two operand values based on the result of a condition + and conditional move instructions that either move a value or retain a value in a destination register based on the result of a condition. + Conditional select and conditional move instructions help reduce code size and avoid branches in common code sequences. + -- + + Extra bit manipulation instructions:: + -- + Xqci expands upon the standard `B` extension by adding instructions for + bit insertion/extraction, bit set/clear, sign and zero extension, and bit counting instructions. + -- + + Fast interrupt instructions:: + -- + Xqci adds instructions to accelerate interrupt handling, including instructions to quickly + enable/disable interrupts and instructions to automatically save an interrupt frame. + -- + + Saturating arithemtic:: + -- + Xqci adds saturating arithmetic instructions to improve performance of fixed-point calculations. + -- + + Xqci adds 16, 32, and 48-bit instruction encodings. The 16 and 32-bit encodings are allocated + in the custom opcode space so as not to conflict with standard RISC-V instructions. The 48-bit instructions + follow the guidance for 48-bit instructions in the RISC-V standard, but are not allocated in reserved custom + space since no such space has been defined by RISC-V International. + + Extension-specific instruction formats :: + -- + QC.EAI format used for 48-bit instructions that operate on 32-bit immediate argument. + -- + + [%autowidth, cols="4*", options="header"] + |=== + ^|Field + ^|Start bit + ^|Width + ^|Description + + |opcode + ^|0 + ^|7 + |Opcode field of 48-bit instructions is 0x1F + + |rd + ^|7 + ^|5 + |Destination register + + |func3 + ^|12 + ^|3 + |Function field identifying instruction group + + |f1 + ^|15 + ^|1 + |Secondary function field + + |imm[31:0] + ^|16 + ^|32 + |Immediate operand of 32 bits + |=== + + -- + QC.EI format used for 48-bit instructions that operate on 26-bit immediate argument, including loads. + -- + + [%autowidth, cols="4*", options="header"] + |=== + ^|Field + ^|Start bit + ^|Width + ^|Description + + |opcode + ^|0 + ^|7 + |Opcode field of 48-bit instructions is 0x1F + + |rd + ^|7 + ^|5 + |Destination register + + |func3 + ^|12 + ^|3 + |Function field identifying instruction group + + |rs1 + ^|15 + ^|5 + |Register argument + + |imm[9:0] + ^|20 + ^|10 + |Immediate operand of 26 bits, the 10 LSBs + + |func2 + ^|30 + ^|2 + |Secondary function field + + |imm[25:10] + ^|32 + ^|16 + |Immediate operand of 26 bits, the 16 MSBs + |=== + + -- + QC.EB format used for 48-bit branch instructions that compare register with 16-bit immediate. + -- + + [%autowidth, cols="4*", options="header"] + |=== + ^|Field + ^|Start bit + ^|Width + ^|Description + + |opcode + ^|0 + ^|7 + |Opcode field of 48-bit instructions is 0x1F + + |imm[4:1,11] + ^|7 + ^|5 + |Bits of immediate value of branch target + + |func3 + ^|12 + ^|3 + |Function field identifying instruction group + + |rs1 + ^|15 + ^|5 + |Register argument + + |func5 + ^|20 + ^|5 + |Secondary function field + + |imm[12,10:5] + ^|25 + ^|7 + |Bits of immediate value of branch target + + |simm[15:0] + ^|32 + ^|16 + |Immediate operand of 16 bits to compare with register + |=== + + -- + QC.EJ format used for 48-bit jump/call instructions with 32-bit immediate target address. + -- + + [%autowidth, cols="4*", options="header"] + |=== + ^|Field + ^|Start bit + ^|Width + ^|Description + + |opcode + ^|0 + ^|7 + |Opcode field of 48-bit instructions is 0x1F + + |imm[4:1,11] + ^|7 + ^|5 + |Bits of immediate value of branch target + + |func3 + ^|12 + ^|3 + |Function field identifying instruction group + + |func2 + ^|15 + ^|2 + |Secondary function field + + |imm[15:13] + ^|17 + ^|3 + |Bits of immediate value of branch target + + |func5 + ^|20 + ^|5 + |Secondary function field + + |imm[12,10:5] + ^|25 + ^|7 + |Bits of immediate value of branch target + + |imm[31:16] + ^|32 + ^|16 + |The 16 MSBs of immediate value of branch target + |=== + + -- + QC.ES format used for 48-bit store instructions with 26-bit immediate offset. + -- + + [%autowidth.stretch] + |=== + |Field|Start bit|Width|Description + + |opcode + ^|0 + ^|7 + |Opcode field of 48-bit instructions is 0x1F + + |imm[4:0] + ^|7 + ^|5 + |Immediate operand of 26 bits offset, the 5 LSBs + + |func3 + ^|12 + ^|3 + |Function field identifying instruction group + + |rs1 + ^|15 + ^|5 + |Register argument used as base address + + |rs2 + ^|20 + ^|5 + |Register argument to be saved + + |imm[9:5] + ^|25 + ^|5 + |Immediate operand of 26 bits offset, the 5 bits + + |func2 + ^|30 + ^|2 + |Secondary function field + + |imm[25:10] + ^|32 + ^|16 + |Immediate operand of 26 bits offset, the 16 MSBs + |=== +doc_license: + name: Creative Commons Attribution 4.0 International License + url: https://creativecommons.org/licenses/by/4.0/ +company: + name: Qualcomm Technologies, Inc. + url: https://qualcomm.com diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqcia.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqcia.yaml new file mode 100644 index 0000000000..951e57af94 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/ext/Xqcia.yaml @@ -0,0 +1,39 @@ +# yaml-language-server: $schema=../../../../schemas/ext_schema.json + +$schema: ext_schema.json# +kind: extension +name: Xqcia +type: unprivileged +long_name: Qualcomm arithmetic +versions: +- version: "0.1.0" + state: development + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com +- version: "0.2.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com + changes: + - Add information about instruction formats of each instruction +description: | + The Xqcia extension includes eleven instructions to perform integer arithmetic. + +doc_license: + name: Creative Commons Attribution 4.0 International License + url: https://creativecommons.org/licenses/by/4.0/ +company: + name: Qualcomm Technologies, Inc. + url: https://qualcomm.com diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqciac.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqciac.yaml new file mode 100644 index 0000000000..deef748aae --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/ext/Xqciac.yaml @@ -0,0 +1,42 @@ +# yaml-language-server: $schema=../../../../schemas/ext_schema.json + +$schema: ext_schema.json# +kind: extension +name: Xqciac +type: unprivileged +long_name: Qualcomm address calculation +versions: +- version: "0.1.0" + state: development + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com +- version: "0.2.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com + changes: + - Add information about instruction formats of each instruction + - Fix description and functionality of qc.shladd instruction + requires: { name: Zca, version: ">= 1.0.0" } +description: | + The Xqciac extension includes three instructions to accelerate common + address calculations. + +doc_license: + name: Creative Commons Attribution 4.0 International License + url: https://creativecommons.org/licenses/by/4.0/ +company: + name: Qualcomm Technologies, Inc. + url: https://qualcomm.com diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqcibi.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqcibi.yaml new file mode 100644 index 0000000000..e425c8bbc6 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/ext/Xqcibi.yaml @@ -0,0 +1,44 @@ +# yaml-language-server: $schema=../../../../schemas/ext_schema.json + +$schema: ext_schema.json# +kind: extension +name: Xqcibi +type: unprivileged +long_name: Qualcomm branch immediate +versions: +- version: "0.1.0" + state: development + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com +- version: "0.2.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com + changes: + - Add information about instruction formats of each instruction + requires: { name: Zca, version: ">= 1.0.0" } +description: | + The Xqcibi extension includes twelve conditional branch instructions that use an immediate + operand for a source. + + All instructions in Xqcibi following the same relocation type as standard RISC-V branches + in the base architecture (e.g., BEQ, BNE, etc.). + +doc_license: + name: Creative Commons Attribution 4.0 International License + url: https://creativecommons.org/licenses/by/4.0/ +company: + name: Qualcomm Technologies, Inc. + url: https://qualcomm.com diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqcibm.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqcibm.yaml new file mode 100644 index 0000000000..61ffca3b02 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/ext/Xqcibm.yaml @@ -0,0 +1,42 @@ +# yaml-language-server: $schema=../../../../schemas/ext_schema.json + +$schema: ext_schema.json# +kind: extension +name: Xqcibm +type: unprivileged +long_name: Qualcomm bit manipulation +versions: +- version: "0.1.0" + state: development + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com +- version: "0.2.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com + changes: + - Add information about instruction formats of each instruction + - Fix description and functionality of qc.c.extu instruction + requires: { name: Zca, version: ">= 1.0.0" } +description: | + The Xqcibm extension includes thirty eight instructions that perform bit manipulation, + include insertion and extraction. + +doc_license: + name: Creative Commons Attribution 4.0 International License + url: https://creativecommons.org/licenses/by/4.0/ +company: + name: Qualcomm Technologies, Inc. + url: https://qualcomm.com diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqcicli.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqcicli.yaml new file mode 100644 index 0000000000..51e965dc4c --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/ext/Xqcicli.yaml @@ -0,0 +1,40 @@ +# yaml-language-server: $schema=../../../../schemas/ext_schema.json + +$schema: ext_schema.json# +kind: extension +name: Xqcicli +type: unprivileged +long_name: Qualcomm conditional load immediate +versions: +- version: "0.1.0" + state: development + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com +- version: "0.2.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com + changes: + - Add information about instruction formats of each instruction +description: | + The Xqcicli extension includes twelve instructions that conditionally + load an immediate value. + +doc_license: + name: Creative Commons Attribution 4.0 International License + url: https://creativecommons.org/licenses/by/4.0/ +company: + name: Qualcomm Technologies, Inc. + url: https://qualcomm.com diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqcicm.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqcicm.yaml new file mode 100644 index 0000000000..a93b092698 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/ext/Xqcicm.yaml @@ -0,0 +1,40 @@ +# yaml-language-server: $schema=../../../../schemas/ext_schema.json + +$schema: ext_schema.json# +kind: extension +name: Xqcicm +type: unprivileged +long_name: Qualcomm conditional move +versions: +- version: "0.1.0" + state: development + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com +- version: "0.2.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com + changes: + - Add information about instruction formats of each instruction + requires: { name: Zca, version: ">= 1.0.0" } +description: | + The Xqcicm extension includes thirteen conditional move instructions. + +doc_license: + name: Creative Commons Attribution 4.0 International License + url: https://creativecommons.org/licenses/by/4.0/ +company: + name: Qualcomm Technologies, Inc. + url: https://qualcomm.com diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqcics.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqcics.yaml new file mode 100644 index 0000000000..78f4631621 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/ext/Xqcics.yaml @@ -0,0 +1,39 @@ +# yaml-language-server: $schema=../../../../schemas/ext_schema.json + +$schema: ext_schema.json# +kind: extension +name: Xqcics +type: unprivileged +long_name: Qualcomm conditional select +versions: +- version: "0.1.0" + state: development + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com +- version: "0.2.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com + changes: + - Add information about instruction formats of each instruction +description: | + The Xqcics extension includes eight conditional select instructions. + +doc_license: + name: Creative Commons Attribution 4.0 International License + url: https://creativecommons.org/licenses/by/4.0/ +company: + name: Qualcomm Technologies, Inc. + url: https://qualcomm.com diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqcicsr.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqcicsr.yaml new file mode 100644 index 0000000000..c49140e2b3 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/ext/Xqcicsr.yaml @@ -0,0 +1,39 @@ +# yaml-language-server: $schema=../../../../schemas/ext_schema.json + +$schema: ext_schema.json# +kind: extension +name: Xqcicsr +type: unprivileged +long_name: Qualcomm CSR instructions +versions: +- version: "0.1.0" + state: development + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com +- version: "0.2.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com + changes: + - Add information about instruction formats of each instruction +description: | + The Xqcicsr extension contains two instructions to read/write CSR which index is in register and not immediate. + +doc_license: + name: Creative Commons Attribution 4.0 International License + url: https://creativecommons.org/licenses/by/4.0/ +company: + name: Qualcomm Technologies, Inc. + url: https://qualcomm.com diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqciint.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqciint.yaml new file mode 100644 index 0000000000..aa00848cb8 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/ext/Xqciint.yaml @@ -0,0 +1,41 @@ +# yaml-language-server: $schema=../../../../schemas/ext_schema.json + +$schema: ext_schema.json# +kind: extension +name: Xqciint +type: unprivileged +long_name: Qualcomm interrupt prologue/epilogue +versions: +- version: "0.1.0" + state: development + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com +- version: "0.2.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com + changes: + - Add information about instruction formats of each instruction + requires: { name: Zca, version: ">= 1.0.0" } +description: | + The Xqciint extension includes eleven instructions to accelerate interrupt + servicing by performing common actions during ISR prologue/epilogue. + +doc_license: + name: Creative Commons Attribution 4.0 International License + url: https://creativecommons.org/licenses/by/4.0/ +company: + name: Qualcomm Technologies, Inc. + url: https://qualcomm.com diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqcilb.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqcilb.yaml new file mode 100644 index 0000000000..b5f8e05ac5 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/ext/Xqcilb.yaml @@ -0,0 +1,40 @@ +# yaml-language-server: $schema=../../../../schemas/ext_schema.json + +$schema: ext_schema.json# +kind: extension +name: Xqcilb +type: unprivileged +long_name: Qualcomm long branch +versions: +- version: "0.1.0" + state: development + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com +- version: "0.2.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com + changes: + - Add information about instruction formats of each instruction + requires: { name: Zca, version: ">= 1.0.0" } +description: | + The Xqcilb extension includes two 48-bit instructions to encode a long branch. + +doc_license: + name: Creative Commons Attribution 4.0 International License + url: https://creativecommons.org/licenses/by/4.0/ +company: + name: Qualcomm Technologies, Inc. + url: https://qualcomm.com diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqcili.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqcili.yaml new file mode 100644 index 0000000000..fa5c702ad6 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/ext/Xqcili.yaml @@ -0,0 +1,40 @@ +# yaml-language-server: $schema=../../../../schemas/ext_schema.json + +$schema: ext_schema.json# +kind: extension +name: Xqcili +type: unprivileged +long_name: Qualcomm long load immediate +versions: +- version: "0.1.0" + state: development + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com +- version: "0.2.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com + changes: + - Add information about instruction formats of each instruction +description: | + The Xqcili extension includes a two instructions that load large immediates than is available + with the base RISC-V ISA. + +doc_license: + name: Creative Commons Attribution 4.0 International License + url: https://creativecommons.org/licenses/by/4.0/ +company: + name: Qualcomm Technologies, Inc. + url: https://qualcomm.com diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqcilia.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqcilia.yaml new file mode 100644 index 0000000000..1ee0829538 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/ext/Xqcilia.yaml @@ -0,0 +1,41 @@ +# yaml-language-server: $schema=../../../../schemas/ext_schema.json + +$schema: ext_schema.json# +kind: extension +name: Xqcilia +type: unprivileged +long_name: Qualcomm long load immediate +versions: +- version: "0.1.0" + state: development + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com +- version: "0.2.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com + changes: + - Add information about instruction formats of each instruction + requires: { name: Zca, version: ">= 1.0.0" } +description: | + The Xqcilia extension includes eight 48-bit instructions that perform arithmetic using + large immediates. + +doc_license: + name: Creative Commons Attribution 4.0 International License + url: https://creativecommons.org/licenses/by/4.0/ +company: + name: Qualcomm Technologies, Inc. + url: https://qualcomm.com diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqcilo.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqcilo.yaml new file mode 100644 index 0000000000..7a7c8c957c --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/ext/Xqcilo.yaml @@ -0,0 +1,41 @@ +# yaml-language-server: $schema=../../../../schemas/ext_schema.json + +$schema: ext_schema.json# +kind: extension +name: Xqcilo +type: unprivileged +long_name: Qualcomm large offset load/store +versions: +- version: "0.1.0" + state: development + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com +- version: "0.2.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com + changes: + - Add information about instruction formats of each instruction + requires: { name: Zca, version: ">= 1.0.0" } +description: | + The Xqcilo extension includes eight 48-bit load/stores instructions that use an offset + larger than can be found in the base RISC-V ISA. + +doc_license: + name: Creative Commons Attribution 4.0 International License + url: https://creativecommons.org/licenses/by/4.0/ +company: + name: Qualcomm Technologies, Inc. + url: https://qualcomm.com diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqcilsm.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqcilsm.yaml new file mode 100644 index 0000000000..dd853b48c4 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/ext/Xqcilsm.yaml @@ -0,0 +1,40 @@ +# yaml-language-server: $schema=../../../../schemas/ext_schema.json + +$schema: ext_schema.json# +kind: extension +name: Xqcilsm +type: unprivileged +long_name: Qualcomm load/store multiple +versions: +- version: "0.1.0" + state: development + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com +- version: "0.2.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com + changes: + - Add information about instruction formats of each instruction +description: | + The Xqcilsm extension includes six instructions that transfer multiple values + between registers and memory. + +doc_license: + name: Creative Commons Attribution 4.0 International License + url: https://creativecommons.org/licenses/by/4.0/ +company: + name: Qualcomm Technologies, Inc. + url: https://qualcomm.com diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqcisls.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqcisls.yaml new file mode 100644 index 0000000000..b80aff96bf --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/ext/Xqcisls.yaml @@ -0,0 +1,39 @@ +# yaml-language-server: $schema=../../../../schemas/ext_schema.json + +$schema: ext_schema.json# +kind: extension +name: Xqcisls +type: unprivileged +long_name: Qualcomm scaled load/store +versions: +- version: "0.1.0" + state: development + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com +- version: "0.2.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com + changes: + - Add information about instruction formats of each instruction +description: | + The Xqcisls extension includes five load and three store instructions with a scaled index addressing mode. + +doc_license: + name: Creative Commons Attribution 4.0 International License + url: https://creativecommons.org/licenses/by/4.0/ +company: + name: Qualcomm Technologies, Inc. + url: https://qualcomm.com diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.addsat.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.addsat.yaml new file mode 100644 index 0000000000..43cfa15661 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.addsat.yaml @@ -0,0 +1,48 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.addsat +long_name: Saturating signed addition +description: | + Add signed values `rs1` and `rs2`, saturate the signed result, and write to `rd`. + Instruction encoded in R instruction format +definedBy: + anyOf: + - Xqci + - Xqcia +base: 32 +encoding: + match: 0001110----------011-----0001011 + variables: + - name: rs1 + location: 19-15 + not: 0 + - name: rs2 + location: 24-20 + not: 0 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1, xs2" +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg sum = X[rs1] + X[rs2]; + XReg most_negative_number = 1 << (xlen() - 1); + XReg most_positive_number = (1 << (xlen() - 1)) - 1; + # overflow occurs if the operands are the same sign and the result is a different sign + if (X[rs1][xlen()-1] == X[rs2][xlen()-1]) { + if (sum[xlen()-1] != X[rs1][xlen()-1]) { + if ($signed(X[rs1]) < 0) { + X[rd] = most_negative_number; + } else { + X[rd] = most_positive_number; + } + } + } + # otherwise, overflow did not occur + X[rd] = sum; diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.addusat.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.addusat.yaml new file mode 100644 index 0000000000..b3f010e60e --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.addusat.yaml @@ -0,0 +1,44 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.addusat +long_name: Saturating unsigned addition +description: | + Add unsigned values `rs1` and `rs2`, saturate the unsigned result, and write to `rd`. + Instruction encoded in R instruction format +definedBy: + anyOf: + - Xqci + - Xqcia +base: 32 +encoding: + match: 0001111----------011-----0001011 + variables: + - name: rs1 + location: 19-15 + not: 0 + - name: rs2 + location: 24-20 + not: 0 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1, xs2" +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg sum = X[rs1] + X[rs2]; + + # overflow occurs if the msb of at least one operand is 1 and the msb of the sum is not + if ((X[rs1][xlen()-1] == 1) || (X[rs2][xlen()-1] == 1)) { + if (sum[xlen()-1] == 0) { + X[rd] = ~{XLEN{1'b0}}; # return largest number + } + } + + # otherwise, overflow did not occur + X[rd] = sum; diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.beqi.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.beqi.yaml new file mode 100644 index 0000000000..18756b2d3c --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.beqi.yaml @@ -0,0 +1,37 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.beqi +long_name: Branch on equal (Immediate) +description: | + Branches to `PC` + `offset` if the value in `rs1` is equal to the signed immediate + Instruction encoded in BI instruction format +definedBy: + anyOf: + - Xqci + - Xqcibi +base: 32 +encoding: + match: -----------------000-----1111011 + variables: + - name: offset + location: 31|7|30-25|11-8 + left_shift: 1 + sign_extend: true + - name: imm + location: 24-20 + not: 0 + - name: rs1 + location: 19-15 + not: 0 +assembly: " xs1, imm, offset" +access: + s: always + u: always + vs: always + vu: always +operation(): | + if ($signed(X[rs1]) == $signed(imm)) { + jump_halfword($pc + $signed(offset)); + } diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.bgei.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.bgei.yaml new file mode 100644 index 0000000000..c008cf494a --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.bgei.yaml @@ -0,0 +1,37 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.bgei +long_name: Branch on greater than or equal (immediate) +description: | + Branches to `PC` + `offset` if the value in `rs1` is greater than or equal to the immediate. + Instruction encoded in BI instruction format +definedBy: + anyOf: + - Xqci + - Xqcibi +base: 32 +encoding: + match: -----------------101-----1111011 + variables: + - name: offset + location: 31|7|30-25|11-8 + left_shift: 1 + sign_extend: true + - name: imm + location: 24-20 + not: 0 + - name: rs1 + location: 19-15 + not: 0 +assembly: " xs1, imm, offset" +access: + s: always + u: always + vs: always + vu: always +operation(): | + if ($signed(X[rs1]) >= $signed(imm)) { + jump_halfword($pc + $signed(offset)); + } diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.bgeui.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.bgeui.yaml new file mode 100644 index 0000000000..cbc89ae338 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.bgeui.yaml @@ -0,0 +1,37 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.bgeui +long_name: Branch on greater than or equal unsigned (immediate) +description: | + Branches to `PC` + `offset` if the unsigned value in `rs1` is greater than or equal to the unsigned immediate. + Instruction encoded in BI instruction format +definedBy: + anyOf: + - Xqci + - Xqcibi +base: 32 +encoding: + match: -----------------111-----1111011 + variables: + - name: offset + location: 31|7|30-25|11-8 + left_shift: 1 + sign_extend: true + - name: imm + location: 24-20 + not: 0 + - name: rs1 + location: 19-15 + not: 0 +assembly: " xs1, imm, offset" +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (X[rs1] >= imm) { + jump_halfword($pc + $signed(offset)); + } diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.blti.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.blti.yaml new file mode 100644 index 0000000000..a11ca62fc1 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.blti.yaml @@ -0,0 +1,37 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.blti +long_name: Branch on less than (immediate) +description: | + Branches to `PC` + `offset` if the value in `rs1` is less than the immediate. + Instruction encoded in BI instruction format +definedBy: + anyOf: + - Xqci + - Xqcibi +base: 32 +encoding: + match: -----------------100-----1111011 + variables: + - name: offset + location: 31|7|30-25|11-8 + left_shift: 1 + sign_extend: true + - name: imm + location: 24-20 + not: 0 + - name: rs1 + location: 19-15 + not: 0 +assembly: " xs1, imm, offset" +access: + s: always + u: always + vs: always + vu: always +operation(): | + if ($signed(X[rs1]) < $signed(imm)) { + jump_halfword($pc + $signed(offset)); + } diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.bltui.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.bltui.yaml new file mode 100644 index 0000000000..9f1c36cba6 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.bltui.yaml @@ -0,0 +1,37 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.bltui +long_name: Branch on less than unsigned (immediate) +description: | + Branches to `PC` + `offset` if the unsigned value in `rs1` is less than the unsigned immediate. + Instruction encoded in BI instruction format +definedBy: + anyOf: + - Xqci + - Xqcibi +base: 32 +encoding: + match: -----------------110-----1111011 + variables: + - name: offset + location: 31|7|30-25|11-8 + left_shift: 1 + sign_extend: true + - name: imm + location: 24-20 + not: 0 + - name: rs1 + location: 19-15 + not: 0 +assembly: " xs1, imm, offset" +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (X[rs1] < imm) { + jump_halfword($pc + $signed(offset)); + } diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.bnei.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.bnei.yaml new file mode 100644 index 0000000000..1a3bb69d3e --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.bnei.yaml @@ -0,0 +1,37 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.bnei +long_name: Branch on not equal (immediate) +description: | + Branches to `PC` + `offset` if the value in `rs1` is not equal to the signed immediate. + Instruction encoded in BI instruction format. +definedBy: + anyOf: + - Xqci + - Xqcibi +base: 32 +encoding: + match: -----------------001-----1111011 + variables: + - name: offset + location: 31|7|30-25|11-8 + left_shift: 1 + sign_extend: true + - name: imm + location: 24-20 + not: 0 + - name: rs1 + location: 19-15 + not: 0 +assembly: " xs1, imm, offset" +access: + s: always + u: always + vs: always + vu: always +operation(): | + if ($signed(X[rs1]) != $signed(imm)) { + jump_halfword($pc + $signed(offset)); + } diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.brev32.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.brev32.yaml new file mode 100644 index 0000000000..e5168d842a --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.brev32.yaml @@ -0,0 +1,38 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.brev32 +long_name: Reverse bit order +description: | + Reverses the bit order of `rs1` and writes the result to `rd`. + Instruction encoded in I instruction format +definedBy: + anyOf: + - Xqci + - Xqcibm +base: 32 +encoding: + match: 000011000000-----011-----0001011 + variables: + - name: rs1 + location: 19-15 + not: 0 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1" +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg orig_val = X[rs1]; + XReg tmp; + + for (U32 i=0; i> index) & 1; diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.bseti.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.bseti.yaml new file mode 100644 index 0000000000..f1bf5140a5 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.bseti.yaml @@ -0,0 +1,33 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.c.bseti +long_name: Single-Bit set (Immediate) +description: | + This instruction returns `rd` with a single bit set at the index specified in shamt. + The index is read from the lower log2(XLEN) bits of `shamt`. + Instruction encoded in CB instruction format. +definedBy: + anyOf: + - Xqci + - Xqcibm +assembly: " xd, shamt" +base: 32 +encoding: + match: 100101--------01 + variables: + - name: shamt + location: 6-2 + not: 0 + - name: rd + location: 9-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg index = shamt & (xlen() - 1); + XReg reg = rd + 8; + X[reg] = X[reg] | (1 << index); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.clrint.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.clrint.yaml new file mode 100644 index 0000000000..1142d4450d --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.clrint.yaml @@ -0,0 +1,33 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.c.clrint +long_name: Clear interrupt (Register) +description: | + Clear interrupt, interrupt number is in `rs1`. + Instruction encoded in CI instruction format. +definedBy: + anyOf: + - Xqci + - Xqciint +assembly: " xs1" +base: 32 +encoding: + match: 0001-----0001110 + variables: + - name: rs1 + location: 11-7 + not: 0 +access: + s: always + u: always + vs: always + vu: always +operation(): | + Bits<12> MCLICIP0_ADDR = CSR[qc_mclicip0].address(); + + XReg idx = rs1 / 32; + XReg bit = rs1 % 32; + XReg pre_csr = CSR[MCLICIP0_ADDR + idx].sw_read(); + CSR[MCLICIP0_ADDR + idx].sw_write(pre_csr & ~(1 << bit)); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.di.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.di.yaml new file mode 100644 index 0000000000..6eddffab0d --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.di.yaml @@ -0,0 +1,26 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.c.di +long_name: Disable interrupts +description: | + Globally disable interrupts. + Equivalent to "csrrci `zero`, `mstatus`, 8". + Instruction encoded in CI instruction format. +definedBy: + anyOf: + - Xqci + - Xqciint +assembly: "" +base: 32 +encoding: + match: "0001101100010010" +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg pre_mstatus = CSR[mstatus].sw_read(); + CSR[mstatus].sw_write(pre_mstatus & ~8); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.dir.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.dir.yaml new file mode 100644 index 0000000000..f60856cf68 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.dir.yaml @@ -0,0 +1,31 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.c.dir +long_name: Disable interrupts (Register) +description: | + Globally disable interrupts, write previous value of `mstatus` to `rd`. + Equivalent to "csrrci `rd`, `mstatus`, 8". + Instruction encoded in CI instruction format. +definedBy: + anyOf: + - Xqci + - Xqciint +assembly: " xd" +base: 32 +encoding: + match: 0001-----0000010 + variables: + - name: rd + location: 11-7 + not: 0 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg pre_mstatus = CSR[mstatus].sw_read(); + CSR[mstatus].sw_write(pre_mstatus & ~8); + X[rd] = pre_mstatus; diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.ei.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.ei.yaml new file mode 100644 index 0000000000..c5bf324d40 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.ei.yaml @@ -0,0 +1,26 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.c.ei +long_name: Enable interrupts +description: | + Globally enable interrupts. + Equivalent to "csrrsi `zero`, `mstatus`, 8". + Instruction encoded in CI instruction format. +definedBy: + anyOf: + - Xqci + - Xqciint +assembly: "" +base: 32 +encoding: + match: "0001101110010010" +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg pre_mstatus = CSR[mstatus].sw_read(); + CSR[mstatus].sw_write(pre_mstatus | 8); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.eir.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.eir.yaml new file mode 100644 index 0000000000..55ae2d87fd --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.eir.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.c.eir +long_name: Restore interrupts (Register) +description: | + Globally restore interrupts, write `rs1` to `mstatus`. + Equivalent to "csrrs `zero`, `mstatus`, `rs1`". + Instruction encoded in CI instruction format. +definedBy: + anyOf: + - Xqci + - Xqciint +assembly: " xs1" +base: 32 +encoding: + match: 0001-----0000110 + variables: + - name: rs1 + location: 11-7 + not: 0 +access: + s: always + u: always + vs: always + vu: always +operation(): | + CSR[mstatus].sw_write(X[rs1]); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.extu.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.extu.yaml new file mode 100644 index 0000000000..e73a915ee5 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.extu.yaml @@ -0,0 +1,32 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.c.extu +long_name: Extract bits unsigned +description: | + Extract a subset of bits from `rd` starting from LSB. + The width of the subset is determined by (`width_minus1`[4:0] + 1) (1..32). + Instruction encoded in CI instruction format. +definedBy: + anyOf: + - Xqci + - Xqcibm +assembly: " xd, width" +base: 32 +encoding: + match: 0001----------10 + variables: + - name: width_minus1 + location: 6-2 + not: [0, 1, 2, 3, 4] + - name: rd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg width = width_minus1 + 1; + X[rd] = (X[rd] >> 0) & ((1 << width) - 1); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mienter.nest.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mienter.nest.yaml new file mode 100644 index 0000000000..6b9baf3513 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mienter.nest.yaml @@ -0,0 +1,54 @@ +$schema: inst_schema.json# +kind: instruction +name: qc.c.mienter.nest +long_name: Machine mode interrupt enter +description: | + Machine mode interrupt enter, interrupt nesting is enabled. + Interrupt frame is saved in the stack. + Interrupts are enabled. + Instruction encoded in CI instruction format. +assembly: "" +definedBy: + anyOf: + - Xqci + - Xqciint +access: + s: never + u: never + vs: never + vu: never +base: 32 +encoding: + match: "0001100010010010" +operation(): | + XReg virtual_address = X[2]; + XReg mepc_val = CSR[mepc].sw_read(); + XReg mnepc_val = CSR[qc_mnepc].sw_read(); + XReg mcause_val = CSR[mcause].sw_read(); + XReg flags_val = CSR[qc_flags].sw_read(); + if (CSR[mcause].NMI != 1'b1) { + write_memory<32>(virtual_address - 4, mepc_val, $encoding); + } else { + write_memory<32>(virtual_address - 4, mnepc_val, $encoding); + } + write_memory<32>(virtual_address - 8, X[ 8][31:0], $encoding); + write_memory<32>(virtual_address - 12, mcause_val, $encoding); + write_memory<32>(virtual_address - 16, X[ 1][31:0], $encoding); + write_memory<32>(virtual_address - 20, flags_val, $encoding); + write_memory<32>(virtual_address - 24, X[ 5][31:0], $encoding); + write_memory<32>(virtual_address - 28, X[ 6][31:0], $encoding); + write_memory<32>(virtual_address - 32, X[ 7][31:0], $encoding); + write_memory<32>(virtual_address - 36, X[10][31:0], $encoding); + write_memory<32>(virtual_address - 40, X[11][31:0], $encoding); + write_memory<32>(virtual_address - 44, X[12][31:0], $encoding); + write_memory<32>(virtual_address - 48, X[13][31:0], $encoding); + write_memory<32>(virtual_address - 52, X[14][31:0], $encoding); + write_memory<32>(virtual_address - 56, X[15][31:0], $encoding); + write_memory<32>(virtual_address - 60, X[16][31:0], $encoding); + write_memory<32>(virtual_address - 64, X[17][31:0], $encoding); + write_memory<32>(virtual_address - 68, X[28][31:0], $encoding); + write_memory<32>(virtual_address - 72, X[29][31:0], $encoding); + write_memory<32>(virtual_address - 76, X[30][31:0], $encoding); + write_memory<32>(virtual_address - 80, X[31][31:0], $encoding); + X[2] = X[2] - 96; + CSR[mstatus].MIE = 1'b1; diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mienter.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mienter.yaml new file mode 100644 index 0000000000..ac4ffd7401 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mienter.yaml @@ -0,0 +1,55 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.c.mienter +long_name: Machine mode interrupt enter +description: | + Machine mode interrupt enter, interrupt nesting is disabled. + Interrupt frame is saved in the stack. + Interrupts are disabled. + Instruction encoded in CI instruction format. +assembly: "" +definedBy: + anyOf: + - Xqci + - Xqciint +access: + s: never + u: never + vs: never + vu: never +base: 32 +encoding: + match: "0001100000010010" +operation(): | + XReg virtual_address = X[2]; + XReg mepc_val = CSR[mepc].sw_read(); + XReg mnepc_val = CSR[qc_mnepc].sw_read(); + XReg mcause_val = CSR[mcause].sw_read(); + XReg flags_val = CSR[qc_flags].sw_read(); + if (CSR[mcause].NMI != 1'b1) { + write_memory<32>(virtual_address - 4, mepc_val, $encoding); + } else { + write_memory<32>(virtual_address - 4, mnepc_val, $encoding); + } + write_memory<32>(virtual_address - 8, X[ 8][31:0], $encoding); + write_memory<32>(virtual_address - 12, mcause_val, $encoding); + write_memory<32>(virtual_address - 16, X[ 1][31:0], $encoding); + write_memory<32>(virtual_address - 20, flags_val, $encoding); + write_memory<32>(virtual_address - 24, X[ 5][31:0], $encoding); + write_memory<32>(virtual_address - 28, X[ 6][31:0], $encoding); + write_memory<32>(virtual_address - 32, X[ 7][31:0], $encoding); + write_memory<32>(virtual_address - 36, X[10][31:0], $encoding); + write_memory<32>(virtual_address - 40, X[11][31:0], $encoding); + write_memory<32>(virtual_address - 44, X[12][31:0], $encoding); + write_memory<32>(virtual_address - 48, X[13][31:0], $encoding); + write_memory<32>(virtual_address - 52, X[14][31:0], $encoding); + write_memory<32>(virtual_address - 56, X[15][31:0], $encoding); + write_memory<32>(virtual_address - 60, X[16][31:0], $encoding); + write_memory<32>(virtual_address - 64, X[17][31:0], $encoding); + write_memory<32>(virtual_address - 68, X[28][31:0], $encoding); + write_memory<32>(virtual_address - 72, X[29][31:0], $encoding); + write_memory<32>(virtual_address - 76, X[30][31:0], $encoding); + write_memory<32>(virtual_address - 80, X[31][31:0], $encoding); + X[2] = X[2] - 96; diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mileaveret.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mileaveret.yaml new file mode 100644 index 0000000000..ab7a650b7f --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mileaveret.yaml @@ -0,0 +1,53 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.c.mileaveret +long_name: Machine mode interrupt exit +description: | + Machine mode interrupt exit. + Interrupt frame is restored from the stack. + Instruction encoded in CI instruction format. +assembly: "" +definedBy: + anyOf: + - Xqci + - Xqciint +access: + s: never + u: never + vs: never + vu: never +base: 32 +encoding: + match: "0001101000010010" +operation(): | + XReg virtual_address = X[2] + 96; + XReg prev_retpc = read_memory<32>(virtual_address - 4, $encoding); + XReg curr_retpc = (CSR[mcause].NMI == 1) ? CSR[qc_mnepc].sw_read() : CSR[mepc].sw_read(); + if (CSR[mcause].NMI != 1'b1) { + CSR[mepc].sw_write(prev_retpc); + } else { + CSR[qc_mnepc].sw_write(prev_retpc); + } + X[ 8] = read_memory<32>(virtual_address - 8, $encoding); + CSR[mcause].sw_write(read_memory<32>(virtual_address - 12, $encoding)); + X[ 1] = read_memory<32>(virtual_address - 16, $encoding); + CSR[qc_flags].sw_write(read_memory<32>(virtual_address - 20, $encoding)); + X[ 5] = read_memory<32>(virtual_address - 24, $encoding); + X[ 6] = read_memory<32>(virtual_address - 28, $encoding); + X[ 7] = read_memory<32>(virtual_address - 32, $encoding); + X[10] = read_memory<32>(virtual_address - 36, $encoding); + X[11] = read_memory<32>(virtual_address - 40, $encoding); + X[12] = read_memory<32>(virtual_address - 44, $encoding); + X[13] = read_memory<32>(virtual_address - 48, $encoding); + X[14] = read_memory<32>(virtual_address - 52, $encoding); + X[15] = read_memory<32>(virtual_address - 56, $encoding); + X[16] = read_memory<32>(virtual_address - 60, $encoding); + X[17] = read_memory<32>(virtual_address - 64, $encoding); + X[28] = read_memory<32>(virtual_address - 68, $encoding); + X[29] = read_memory<32>(virtual_address - 72, $encoding); + X[30] = read_memory<32>(virtual_address - 76, $encoding); + X[31] = read_memory<32>(virtual_address - 80, $encoding); + X[2] = X[2] + 96; + $pc = curr_retpc; diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mnret.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mnret.yaml new file mode 100644 index 0000000000..4116c16a06 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mnret.yaml @@ -0,0 +1,32 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.c.mnret +long_name: Machine NMI Return +description: | + Returns from an NMI in M-mode. + Instruction encoded in CI instruction format. +assembly: "" +definedBy: Xqciint +access: + s: never + u: never + vs: never + vu: never +base: 32 +encoding: + match: "0001100110010010" +operation(): | + CSR[mncause].MIE = CSR[mncause].MPIE; + CSR[mncause].MPIE = 1; + if (CSR[mncause].MPP == 2'b00) { + set_mode(PrivilegeMode::U); + } else if (CSR[mncause].MPP == 2'b01) { + set_mode(PrivilegeMode::S); + } else if (CSR[mncause].MPP == 2'b11) { + set_mode(PrivilegeMode::M); + } + CSR[mncause].MPP = implemented?(ExtensionName::U) ? 2'b00 : 2'b11; + CSR[mcause].NMI = 0; + $pc = CSR[qc_mnepc].sw_read(); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mret.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mret.yaml new file mode 100644 index 0000000000..0e07908d6e --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mret.yaml @@ -0,0 +1,34 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.c.mret +long_name: Machine Exception Return +description: | + Returns from an exception in M-mode. + Instruction encoded in CI instruction format. +assembly: "" +definedBy: Xqciint +access: + s: never + u: never + vs: never + vu: never +base: 32 +encoding: + match: "0001100100010010" +operation(): | + if (implemented?(ExtensionName::S) && CSR[mstatus].MPP != 2'b11) { + CSR[mstatus].MPRV = 0; + } + CSR[mstatus].MIE = CSR[mstatus].MPIE; + CSR[mstatus].MPIE = 1; + if (CSR[mstatus].MPP == 2'b00) { + set_mode(PrivilegeMode::U); + } else if (CSR[mstatus].MPP == 2'b01) { + set_mode(PrivilegeMode::S); + } else if (CSR[mstatus].MPP == 2'b11) { + set_mode(PrivilegeMode::M); + } + CSR[mstatus].MPP = implemented?(ExtensionName::U) ? 2'b00 : 2'b11; + $pc = CSR[mepc].sw_read(); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.muladdi.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.muladdi.yaml new file mode 100644 index 0000000000..32b847c805 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.muladdi.yaml @@ -0,0 +1,32 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.c.muladdi +long_name: Multiply and accumulate (Immediate) +description: | + Increments `rd` by the multiplication of `rs1` and an unsigned immediate + Instruction encoded in CL instruction format. +definedBy: + anyOf: + - Xqci + - Xqciac +base: 32 +encoding: + match: 001-----------10 + variables: + - name: uimm + location: 5|12-10|6 + - name: rs1 + location: 9-7 + - name: rd + location: 4-2 +assembly: " xd, xs1, uimm" +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg orig_val = X[rd+8]; + X[rd+8] = orig_val + (X[rs1+8] * uimm); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mveqz.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mveqz.yaml new file mode 100644 index 0000000000..054f50ac27 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mveqz.yaml @@ -0,0 +1,30 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.c.mveqz +long_name: Conditional Move if equal to zero +description: | + Move `rs1` to `rd` if `rd` == 0, keep `rd` value otherwise + Instruction encoded in CL instruction format. +definedBy: + anyOf: + - Xqci + - Xqcicm +base: 32 +encoding: + match: 101011---00---10 + variables: + - name: rs1 + location: 9-7 + - name: rd + location: 4-2 +assembly: " xd, xs1" +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg orig_val = X[rd+8]; + X[rd+8] = (orig_val == 0) ? X[rs1+8] : orig_val; diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.setint.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.setint.yaml new file mode 100644 index 0000000000..73ee255164 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.setint.yaml @@ -0,0 +1,33 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.c.setint +long_name: Set interrupt (Register) +description: | + Set interrupt, interrupt number is in `rs1`. + Instruction encoded in CI instruction format. +definedBy: + anyOf: + - Xqci + - Xqciint +assembly: " xs1" +base: 32 +encoding: + match: 0001-----0001010 + variables: + - name: rs1 + location: 11-7 + not: 0 +access: + s: always + u: always + vs: always + vu: always +operation(): | + Bits<12> MCLICIP0_ADDR = CSR[qc_mclicip0].address(); + + XReg idx = rs1 / 32; + XReg bit = rs1 % 32; + XReg pre_csr = CSR[MCLICIP0_ADDR + idx].sw_read(); + CSR[MCLICIP0_ADDR + idx].sw_write(pre_csr | (1 << bit)); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.clo.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.clo.yaml new file mode 100644 index 0000000000..72bc46245f --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.clo.yaml @@ -0,0 +1,35 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.clo +long_name: Count leading ones +description: | + Count the number of ones before the first zero in `rs1`, starting from the MSB + and progressing to the LSB. + Accordingly, if the input is ~0, the output is XLEN, and if the most-significant + bit of the input is a 0, the output is 0. + output written to the `rd` + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcibm +base: 32 +encoding: + match: 000010000000-----011-----0001011 + variables: + - name: rs1 + location: 19-15 + not: 0 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1" +access: + s: always + u: always + vs: always + vu: always +operation(): | + X[rd] = (xlen() - 1) - $signed(highest_set_bit(~X[rs1])); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.clrinti.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.clrinti.yaml new file mode 100644 index 0000000000..e70fcc8cf9 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.clrinti.yaml @@ -0,0 +1,32 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.clrinti +long_name: Clear interrupt (Immediate) +description: | + Clear interrupt, interrupt number is in `imm` (0 - 1023). + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqciint +assembly: " imm" +base: 32 +encoding: + match: 1100111----------000000001110011 + variables: + - name: imm + location: 24-15 +access: + s: always + u: always + vs: always + vu: always +operation(): | + Bits<12> MCLICIP0_ADDR = CSR[qc_mclicip0].address(); + + XReg idx = imm / 32; + XReg bit = imm % 32; + XReg pre_csr = CSR[MCLICIP0_ADDR + idx].sw_read(); + CSR[MCLICIP0_ADDR + idx].sw_write(pre_csr & ~(1 << bit)); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.compress2.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.compress2.yaml new file mode 100644 index 0000000000..d66e9a95ee --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.compress2.yaml @@ -0,0 +1,34 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.compress2 +long_name: Bit compression (every 2nd bit) +description: | + Bit compression (every 2nd bit) of `rs1`, zero-pad bits [31:16] of the result. + Write result to `rd`. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcibm +base: 32 +encoding: + match: 000000000000-----011-----0001011 + variables: + - name: rs1 + location: 19-15 + not: 0 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1" +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg b0 = {X[rs1][14],X[rs1][12],X[rs1][10],X[rs1][8],X[rs1][6],X[rs1][4],X[rs1][2],X[rs1][0]}; + XReg b1 = {X[rs1][30],X[rs1][28],X[rs1][26],X[rs1][24],X[rs1][22],X[rs1][20],X[rs1][18],X[rs1][16]}; + X[rd] = {16'b0,b1[7:0],b0[7:0]}; diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.compress3.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.compress3.yaml new file mode 100644 index 0000000000..bbc45aaf27 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.compress3.yaml @@ -0,0 +1,34 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.compress3 +long_name: Bit compression (every 3rd bit) +description: | + Bit compression (every 3rd bit) of `rs1`, zero-pad bits [31:11] of the result. + Write result to `rd`. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcibm +base: 32 +encoding: + match: 000000100000-----011-----0001011 + variables: + - name: rs1 + location: 19-15 + not: 0 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1" +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg b0 = {X[rs1][21],X[rs1][18],X[rs1][15],X[rs1][12],X[rs1][9],X[rs1][6],X[rs1][3],X[rs1][0]}; + XReg b1 = {5'b0,X[rs1][30],X[rs1][27],X[rs1][24]}; + X[rd] = {21'b0,b1[2:0],b0[7:0]}; diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.csrrwr.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.csrrwr.yaml new file mode 100644 index 0000000000..47c7a9a49f --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.csrrwr.yaml @@ -0,0 +1,44 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.csrrwr +long_name: Atomic Read/Write CSR (Register) +description: | + Atomically swap values in the CSRs and integer registers. + Read the old value of the CSR, zero-extends the value to `XLEN` bits, + and then write it to integer register `rd`. + The CSR number is in `rs2` register. + The initial value in `rs1` is written to the CSR. + If `rd`=`x0`, then the instruction shall not read the CSR and shall not + cause any of the side effects that might occur on a CSR read. + Instruction encoded in R instruction format. +definedBy: + anyOf: + - Xqci + - Xqcicsr +assembly: xd, xs1, xs2 +base: 32 +encoding: + match: 1000110----------000-----1110011 + variables: + - name: rs2 + location: 24-20 + not: 0 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg csr = X[rs2]; + if (rd != 0) { + X[rd] = CSR[csr].sw_read(); + } + # writes the value in X[rs1] to the CSR, + # performing any WARL transformations first + CSR[csr].sw_write(X[rs1]); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.csrrwri.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.csrrwri.yaml new file mode 100644 index 0000000000..94c7df3741 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.csrrwri.yaml @@ -0,0 +1,44 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.csrrwri +long_name: Atomic Read/Write CSR (Register) Immediate +description: | + Atomically write CSR using a 5-bit immediate `imm`, and load the previous value into `rd`. + Read the old value of the CSR, zero-extends the value to `XLEN` bits, + and then write it to integer register `rd`. + The CSR number is in `rs2` register. + The 5-bit uimm field is zero-extended and written to the CSR. + If `rd`=`x0`, then the instruction shall not read the CSR and shall not + cause any of the side effects that might occur on a CSR read. + Instruction encoded in R instruction format. +definedBy: + anyOf: + - Xqci + - Xqcicsr +assembly: " xd, imm, xs2" +base: 32 +encoding: + match: 1000111----------000-----1110011 + variables: + - name: rs2 + location: 24-20 + not: 0 + - name: imm + location: 19-15 + - name: rd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg csr = X[rs2]; + if (rd != 0) { + X[rd] = CSR[csr].sw_read(); + } + # writes the zero-extended immediate to the CSR, + # performing any WARL transformations first + CSR[csr].sw_write({{XLEN-5{1'b0}}, imm}); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.cto.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.cto.yaml new file mode 100644 index 0000000000..8f5e3a628d --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.cto.yaml @@ -0,0 +1,35 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.cto +long_name: Count trailing ones +description: | + Count the number of ones before the first zero in `rs1`, starting from the LSB + and progressing to the MSB. + Accordingly, if the input is ~0, the output is XLEN, and if the least-significant + bit of the input is a 0, the output is 0. + Output written to `rd`. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcibm +base: 32 +encoding: + match: 000010100000-----011-----0001011 + variables: + - name: rs1 + location: 19-15 + not: 0 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1" +access: + s: always + u: always + vs: always + vu: always +operation(): | + X[rd] = (xlen() - 1) - $signed(lowest_set_bit(~X[rs1])); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.addai.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.addai.yaml new file mode 100644 index 0000000000..5da57ef1ee --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.addai.yaml @@ -0,0 +1,30 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.e.addai +long_name: Add immediate +description: | + Add a 32-bit immediate `imm` to the value in `rd`, and store the result back in `rd`. + Instruction encoded in QC.EAI instruction format. +definedBy: + anyOf: + - Xqci + - Xqcilia +base: 32 +encoding: + match: --------------------------------0010-----0011111 + variables: + - name: imm + location: 47-16 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, imm" +access: + s: always + u: always + vs: always + vu: always +operation(): | + X[rd] = X[rd] + imm; diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.addi.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.addi.yaml new file mode 100644 index 0000000000..adaec663f5 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.addi.yaml @@ -0,0 +1,34 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.e.addi +long_name: Add immediate +description: | + Add a sign-extended 26-bit immediate `imm` to the value in `rs1`, + and store the result in `rd`. + Instruction encoded in QC.EI instruction format. +definedBy: + anyOf: + - Xqci + - Xqcilia +base: 32 +encoding: + match: ----------------10---------------011-----0011111 + variables: + - name: imm + location: 47-32|29-20 + - name: rs1 + location: 19-15 + not: 0 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1, imm" +access: + s: always + u: always + vs: always + vu: always +operation(): | + X[rd] = X[rs1] + sext(imm,26); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.andai.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.andai.yaml new file mode 100644 index 0000000000..c66dfeda44 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.andai.yaml @@ -0,0 +1,30 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.e.andai +long_name: And immediate +description: | + And a 32-bit immediate `imm` to the value in `rd`, and store the result back in `rd`. + Instruction encoded in QC.EAI instruction format. +definedBy: + anyOf: + - Xqci + - Xqcilia +base: 32 +encoding: + match: --------------------------------1010-----0011111 + variables: + - name: imm + location: 47-16 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, imm" +access: + s: always + u: always + vs: always + vu: always +operation(): | + X[rd] = X[rd] & imm; diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.andi.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.andi.yaml new file mode 100644 index 0000000000..0c245632b7 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.andi.yaml @@ -0,0 +1,34 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.e.andi +long_name: Add immediate +description: | + And a sign-extended 26-bit immediate `imm` to the value in `rs1`, + and store the result in `rd`. + Instruction encoded in QC.EI instruction format. +definedBy: + anyOf: + - Xqci + - Xqcilia +base: 32 +encoding: + match: ----------------11---------------011-----0011111 + variables: + - name: imm + location: 47-32|29-20 + - name: rs1 + location: 19-15 + not: 0 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1, imm" +access: + s: always + u: always + vs: always + vu: always +operation(): | + X[rd] = X[rs1] & sext(imm,26); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.beqi.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.beqi.yaml new file mode 100644 index 0000000000..f7a3fa722e --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.beqi.yaml @@ -0,0 +1,37 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.e.beqi +long_name: Branch on equal (immediate) +description: | + Branches to `PC` + `offset` if the value in `rs1` is equal to the signed immediate `imm` + Instruction encoded in QC.EB instruction format. +definedBy: + anyOf: + - Xqci + - Xqcibi +base: 32 +encoding: + match: -----------------------11000-----100-----0011111 + variables: + - name: offset + location: 31|7|30-25|11-8 + left_shift: 1 + sign_extend: true + - name: imm + location: 47-32 + not: 0 + - name: rs1 + location: 19-15 + not: 0 +assembly: " xs1, imm, offset" +access: + s: always + u: always + vs: always + vu: always +operation(): | + if ($signed(X[rs1]) == $signed(imm)) { + jump_halfword($pc + $signed(offset)); + } diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.bgei.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.bgei.yaml new file mode 100644 index 0000000000..83acc9e282 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.bgei.yaml @@ -0,0 +1,37 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.e.bgei +long_name: Branch on greater than or equal (immediate) +description: | + Branches to `PC` + `offset` if the value in `rs1` is greater than or equal to the immediate `imm`. + Instruction encoded in QC.EB instruction format. +definedBy: + anyOf: + - Xqci + - Xqcibi +base: 32 +encoding: + match: -----------------------11101-----100-----0011111 + variables: + - name: offset + location: 31|7|30-25|11-8 + left_shift: 1 + sign_extend: true + - name: imm + location: 47-32 + not: 0 + - name: rs1 + location: 19-15 + not: 0 +assembly: " xs1, imm, offset" +access: + s: always + u: always + vs: always + vu: always +operation(): | + if ($signed(X[rs1]) >= $signed(imm)) { + jump_halfword($pc + $signed(offset)); + } diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.bgeui.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.bgeui.yaml new file mode 100644 index 0000000000..fd04139e9c --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.bgeui.yaml @@ -0,0 +1,37 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.e.bgeui +long_name: Branch on greater than or equal unsigned (immediate) +description: | + Branches to `PC` + `offset` if the unsigned value in `rs1` is greater than or equal to the unsigned immediate `imm`. + Instruction encoded in QC.EB instruction format. +definedBy: + anyOf: + - Xqci + - Xqcibi +base: 32 +encoding: + match: -----------------------11111-----100-----0011111 + variables: + - name: offset + location: 31|7|30-25|11-8 + left_shift: 1 + sign_extend: true + - name: imm + location: 47-32 + not: 0 + - name: rs1 + location: 19-15 + not: 0 +assembly: " xs1, imm, offset" +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (X[rs1] >= imm) { + jump_halfword($pc + $signed(offset)); + } diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.blti.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.blti.yaml new file mode 100644 index 0000000000..20715bc179 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.blti.yaml @@ -0,0 +1,37 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.e.blti +long_name: Branch on less than (immediate) +description: | + Branches to `PC` + `offset` if the value in `rs1` is less than the immediate `imm`. + Instruction encoded in QC.EB instruction format. +definedBy: + anyOf: + - Xqci + - Xqcibi +base: 32 +encoding: + match: -----------------------11100-----100-----0011111 + variables: + - name: offset + location: 31|7|30-25|11-8 + left_shift: 1 + sign_extend: true + - name: imm + location: 47-32 + not: 0 + - name: rs1 + location: 19-15 + not: 0 +assembly: " xs1, imm, offset" +access: + s: always + u: always + vs: always + vu: always +operation(): | + if ($signed(X[rs1]) < $signed(imm)) { + jump_halfword($pc + $signed(offset)); + } diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.bltui.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.bltui.yaml new file mode 100644 index 0000000000..e79b216520 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.bltui.yaml @@ -0,0 +1,37 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.e.bltui +long_name: Branch on less than unsigned (immediate) +description: | + Branches to `PC` + `offset` if the unsigned value in `rs1` is less than the unsigned immediate `imm`. + Instruction encoded in QC.EB instruction format. +definedBy: + anyOf: + - Xqci + - Xqcibi +base: 32 +encoding: + match: -----------------------11110-----100-----0011111 + variables: + - name: offset + location: 31|7|30-25|11-8 + left_shift: 1 + sign_extend: true + - name: imm + location: 47-32 + not: 0 + - name: rs1 + location: 19-15 + not: 0 +assembly: " xs1, imm, offset" +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (X[rs1] < imm) { + jump_halfword($pc + $signed(offset)); + } diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.bnei.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.bnei.yaml new file mode 100644 index 0000000000..12b9be58e3 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.bnei.yaml @@ -0,0 +1,37 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.e.bnei +long_name: Branch on not equal (immediate) +description: | + Branches to `PC` + `offset` if the value in `rs1` is not equal to the signed immediate `imm`. + Instruction encoded in QC.EB instruction format. +definedBy: + anyOf: + - Xqci + - Xqcibi +base: 32 +encoding: + match: -----------------------11001-----100-----0011111 + variables: + - name: offset + location: 31|7|30-25|11-8 + left_shift: 1 + sign_extend: true + - name: imm + location: 47-32 + not: 0 + - name: rs1 + location: 19-15 + not: 0 +assembly: " xs1, imm, offset" +access: + s: always + u: always + vs: always + vu: always +operation(): | + if ($signed(X[rs1]) != $signed(imm)) { + jump_halfword($pc + $signed(offset)); + } diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.j.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.j.yaml new file mode 100644 index 0000000000..8399b3c067 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.j.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.e.j +long_name: Jump +description: | + Jump to a PC-relative offset. + Instruction encoded in QC.EJ instruction format. +definedBy: + anyOf: + - Xqci + - Xqcilb +assembly: " imm" +base: 32 +encoding: + match: -----------------------00000---00100-----0011111 + variables: + - name: imm + location: 47-32|19-17|31|7|30-25|11-8 + left_shift: 1 + sign_extend: true +access: + s: always + u: always + vs: always + vu: always +operation(): | + jump_halfword($pc + imm); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.jal.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.jal.yaml new file mode 100644 index 0000000000..b59337d4ed --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.jal.yaml @@ -0,0 +1,32 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.e.jal +long_name: Jump and link +description: | + Jump to a PC-relative offset and store the return. + Instruction encoded in QC.EJ instruction format. + address in x1. +definedBy: + anyOf: + - Xqci + - Xqcilb +assembly: " imm" +base: 32 +encoding: + match: -----------------------00000---01100-----0011111 + variables: + - name: imm + location: 47-32|19-17|31|7|30-25|11-8 + left_shift: 1 + sign_extend: true +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg retrun_addr = $pc + 6; + jump_halfword($pc + imm); + X[1] = retrun_addr; diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.lb.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.lb.yaml new file mode 100644 index 0000000000..68d42dbd57 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.lb.yaml @@ -0,0 +1,34 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.e.lb +long_name: Load byte +description: | + Load 8 bits of data into register `rd` from an + address formed by adding `rs1` to a signed offset `imm`. + Sign extend the result. + Instruction encoded in QC.EI instruction format. +definedBy: + anyOf: + - Xqci + - Xqcilo +assembly: " xd, imm(xs1)" +base: 32 +encoding: + match: ----------------00---------------101-----0011111 + variables: + - name: imm + location: 47-32|29-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg virtual_address = X[rs1] + imm; + X[rd] = sext(read_memory<8>(virtual_address, $encoding), 7); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.lbu.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.lbu.yaml new file mode 100644 index 0000000000..5d47a619fc --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.lbu.yaml @@ -0,0 +1,34 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.e.lbu +long_name: Load byte unsigned +description: | + Load 8 bits of data into register `rd` from an + address formed by adding `rs1` to a signed offset `imm`. + Zero extend the result. + Instruction encoded in QC.EI instruction format. +definedBy: + anyOf: + - Xqci + - Xqcilo +assembly: " xd, imm(xs1)" +base: 32 +encoding: + match: ----------------01---------------101-----0011111 + variables: + - name: imm + location: 47-32|29-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg virtual_address = X[rs1] + imm; + X[rd] = read_memory<8>(virtual_address, $encoding); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.lh.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.lh.yaml new file mode 100644 index 0000000000..08cb7cc4ed --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.lh.yaml @@ -0,0 +1,34 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.e.lh +long_name: Load halfword +description: | + Load 16 bits of data into register `rd` from an + address formed by adding `rs1` to a signed offset `imm`. + Sign extend the result. + Instruction encoded in QC.EI instruction format. +definedBy: + anyOf: + - Xqci + - Xqcilo +assembly: " xd, imm(xs1)" +base: 32 +encoding: + match: ----------------10---------------101-----0011111 + variables: + - name: imm + location: 47-32|29-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg virtual_address = X[rs1] + imm; + X[rd] = sext(read_memory<16>(virtual_address, $encoding), 15); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.lhu.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.lhu.yaml new file mode 100644 index 0000000000..717261c246 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.lhu.yaml @@ -0,0 +1,34 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.e.lhu +long_name: Load halfword unsigned +description: | + Load 16 bits of data into register `rd` from an + address formed by adding `rs1` to a signed offset `imm`. + Zero extend the result. + Instruction encoded in QC.EI instruction format. +definedBy: + anyOf: + - Xqci + - Xqcilo +assembly: " xd, imm(xs1)" +base: 32 +encoding: + match: ----------------11---------------101-----0011111 + variables: + - name: imm + location: 47-32|29-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg virtual_address = X[rs1] + imm; + X[rd] = read_memory<16>(virtual_address, $encoding); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.li.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.li.yaml new file mode 100644 index 0000000000..33c0a1ab55 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.li.yaml @@ -0,0 +1,30 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.e.li +long_name: Load immediate large +description: | + Loads the 32-bit immediate `imm` into `rd`. + Instruction encoded in QC.EAI instruction format. +definedBy: + anyOf: + - Xqci + - Xqcili +base: 32 +encoding: + match: --------------------------------0000-----0011111 + variables: + - name: imm + location: 47-16 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, imm" +access: + s: always + u: always + vs: always + vu: always +operation(): | + X[rd] = imm; diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.lw.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.lw.yaml new file mode 100644 index 0000000000..12fb70dfab --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.lw.yaml @@ -0,0 +1,34 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.e.lw +long_name: Load word +description: | + Load 32 bits of data into register `rd` from an + address formed by adding `rs1` to a signed offset `imm`. + Sign extend the result. + Instruction encoded in QC.EI instruction format. +definedBy: + anyOf: + - Xqci + - Xqcilo +assembly: " xd, imm(xs1)" +base: 32 +encoding: + match: ----------------00---------------110-----0011111 + variables: + - name: imm + location: 47-32|29-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg virtual_address = X[rs1] + imm; + X[rd] = read_memory<32>(virtual_address, $encoding); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.orai.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.orai.yaml new file mode 100644 index 0000000000..7425dbcb00 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.orai.yaml @@ -0,0 +1,30 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.e.orai +long_name: Or immediate +description: | + Or a 32-bit immediate `imm` to the value in `rd`, and store the result back in `rd`. + Instruction encoded in QC.EAI instruction format. +definedBy: + anyOf: + - Xqci + - Xqcilia +base: 32 +encoding: + match: --------------------------------1001-----0011111 + variables: + - name: imm + location: 47-16 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, imm" +access: + s: always + u: always + vs: always + vu: always +operation(): | + X[rd] = X[rd] | imm; diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.ori.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.ori.yaml new file mode 100644 index 0000000000..45204d9d3a --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.ori.yaml @@ -0,0 +1,34 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.e.ori +long_name: Or immediate +description: | + Or a sign-extended 26-bit immediate `imm` to the value in `rs1`, + and store the result in `rd`. + Instruction encoded in QC.EI instruction format. +definedBy: + anyOf: + - Xqci + - Xqcilia +base: 32 +encoding: + match: ----------------01---------------011-----0011111 + variables: + - name: imm + location: 47-32|29-20 + - name: rs1 + location: 19-15 + not: 0 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1, imm" +access: + s: always + u: always + vs: always + vu: always +operation(): | + X[rd] = X[rs1] | sext(imm,26); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.sb.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.sb.yaml new file mode 100644 index 0000000000..b8f3e713de --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.sb.yaml @@ -0,0 +1,33 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.e.sb +long_name: Store byte +description: | + Store 8 bits of data from register `rs2` to an + address formed by adding `rs1` to a signed offset `imm`. + Instruction encoded in QC.ES instruction format. +definedBy: + anyOf: + - Xqci + - Xqcilo +assembly: " xs2, imm(xs1)" +base: 32 +encoding: + match: ----------------01---------------110-----0011111 + variables: + - name: imm + location: 47-32|29-25|11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg virtual_address = X[rs1] + $signed(imm); + write_memory<8>(virtual_address, X[rs2][7:0], $encoding); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.sh.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.sh.yaml new file mode 100644 index 0000000000..dbb1db3948 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.sh.yaml @@ -0,0 +1,33 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.e.sh +long_name: Store halfword +description: | + Store 16 bits of data from register `rs2` to an + address formed by adding `rs1` to a signed offset `imm`. + Instruction encoded in QC.ES instruction format. +definedBy: + anyOf: + - Xqci + - Xqcilo +assembly: " xs2, imm(xs1)" +base: 32 +encoding: + match: ----------------10---------------110-----0011111 + variables: + - name: imm + location: 47-32|29-25|11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg virtual_address = X[rs1] + $signed(imm); + write_memory<16>(virtual_address, X[rs2][15:0], $encoding); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.sw.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.sw.yaml new file mode 100644 index 0000000000..30f97f14f2 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.sw.yaml @@ -0,0 +1,33 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.e.sw +long_name: Store word +description: | + Store 32 bits of data from register `rs2` to an + address formed by adding `rs1` to a signed offset `imm`. + Instruction encoded in QC.ES instruction format. +definedBy: + anyOf: + - Xqci + - Xqcilo +assembly: " xs2, imm(xs1)" +base: 32 +encoding: + match: ----------------11---------------110-----0011111 + variables: + - name: imm + location: 47-32|29-25|11-7 + - name: rs2 + location: 24-20 + - name: rs1 + location: 19-15 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg virtual_address = X[rs1] + $signed(imm); + write_memory<32>(virtual_address, X[rs2][31:0], $encoding); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.xorai.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.xorai.yaml new file mode 100644 index 0000000000..67e93d2be9 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.xorai.yaml @@ -0,0 +1,30 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.e.xorai +long_name: Exclusive Or immediate +description: | + Exclusive or a 32-bit immediate `imm` to the value in `rd`, and store the result back in `rd`. + Instruction encoded in QC.EAI instruction format. +definedBy: + anyOf: + - Xqci + - Xqcilia +base: 32 +encoding: + match: --------------------------------0001-----0011111 + variables: + - name: imm + location: 47-16 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, imm" +access: + s: always + u: always + vs: always + vu: always +operation(): | + X[rd] = X[rd] ^ imm; diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.xori.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.xori.yaml new file mode 100644 index 0000000000..a38d5d70e2 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.e.xori.yaml @@ -0,0 +1,34 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.e.xori +long_name: Exclusive Or immediate +description: | + Exclusive or a sign-extended 26-bit immediate `imm` to the value in `rs1`, + and store the result in `rd`. + Instruction encoded in QC.EI instruction format. +definedBy: + anyOf: + - Xqci + - Xqcilia +base: 32 +encoding: + match: ----------------00---------------011-----0011111 + variables: + - name: imm + location: 47-32|29-20 + - name: rs1 + location: 19-15 + not: 0 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1, imm" +access: + s: always + u: always + vs: always + vu: always +operation(): | + X[rd] = X[rs1] ^ sext(imm,26); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.expand2.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.expand2.yaml new file mode 100644 index 0000000000..c33425a48d --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.expand2.yaml @@ -0,0 +1,36 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.expand2 +long_name: Bit expansion (every 2nd bit) +description: | + Bit expansion (every 2nd bit) of `rs1`, bits [31:16] of `rs1` are ignored. + Write result to `rd`. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcibm +base: 32 +encoding: + match: 000001000000-----011-----0001011 + variables: + - name: rs1 + location: 19-15 + not: 0 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1" +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg b0 = {X[rs1][3],X[rs1][3],X[rs1][2],X[rs1][2],X[rs1][1],X[rs1][1],X[rs1][0],X[rs1][0]}; + XReg b1 = {X[rs1][7],X[rs1][7],X[rs1][6],X[rs1][6],X[rs1][5],X[rs1][5],X[rs1][4],X[rs1][4]}; + XReg b2 = {X[rs1][11],X[rs1][11],X[rs1][10],X[rs1][10],X[rs1][9],X[rs1][9],X[rs1][8],X[rs1][8]}; + XReg b3 = {X[rs1][15],X[rs1][15],X[rs1][14],X[rs1][14],X[rs1][13],X[rs1][13],X[rs1][12],X[rs1][12]}; + X[rd] = {b3[7:0],b2[7:0],b1[7:0],b0[7:0]}; diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.expand3.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.expand3.yaml new file mode 100644 index 0000000000..70e8059cf2 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.expand3.yaml @@ -0,0 +1,36 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.expand3 +long_name: Bit expansion (every 3rd bit) +description: | + Bit expansion (every 3rd bit) of `rs1`, bits [31:11] of `rs1` are ignored. + Write result to `rd`. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcibm +base: 32 +encoding: + match: 000001100000-----011-----0001011 + variables: + - name: rs1 + location: 19-15 + not: 0 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1" +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg b0 = {X[rs1][2],X[rs1][2],X[rs1][1],X[rs1][1],X[rs1][1],X[rs1][0],X[rs1][0],X[rs1][0]}; + XReg b1 = {X[rs1][5],X[rs1][4],X[rs1][4],X[rs1][4],X[rs1][3],X[rs1][3],X[rs1][3],X[rs1][2]}; + XReg b2 = {X[rs1][7],X[rs1][7],X[rs1][7],X[rs1][6],X[rs1][6],X[rs1][6],X[rs1][5],X[rs1][5]}; + XReg b3 = {X[rs1][10],X[rs1][10],X[rs1][9],X[rs1][9],X[rs1][9],X[rs1][8],X[rs1][8],X[rs1][8]}; + X[rd] = {b3[7:0],b2[7:0],b1[7:0],b0[7:0]}; diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.ext.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.ext.yaml new file mode 100644 index 0000000000..ed6679dd3e --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.ext.yaml @@ -0,0 +1,39 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.ext +long_name: Extract bits signed +description: | + Extract a subset of bits from `rs1` into `rd`, and sign-extend the result. + The width of the subset is determined by (`width_minus1` + 1) (1..32), + and the offset of the subset is determined by `shamt`. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcibm +base: 32 +encoding: + match: 01---------------010-----0001011 + variables: + - name: width_minus1 + location: 29-25 + - name: shamt + location: 24-20 + - name: rs1 + location: 19-15 + not: 0 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1, width, shamt" +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg width = width_minus1 + 1; + XReg unsigned_extraction = (X[rs1] >> shamt) & ((1 << width) - 1); + X[rd] = sext(unsigned_extraction, width_minus1); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extd.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extd.yaml new file mode 100644 index 0000000000..55de009194 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extd.yaml @@ -0,0 +1,38 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.extd +long_name: Extract bits from pair signed (Immediate) +description: | + Extract a subset of bits from the register pair [`rs1`, `rs1`+1] into `rd`, and sign extend the result. + The width of the subset is determined by (`width_minus1` + 1) (1..32), + and the offset (into the pair) of the subset is determined by `shamt`. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcibm +base: 32 +encoding: + match: 11---------------010-----0001011 + variables: + - name: width_minus1 + location: 29-25 + - name: shamt + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1, width, shamt" +access: + s: always + u: always + vs: always + vu: always +operation(): | + Bits<{1'b0, XLEN}*2> pair = {X[rs1 + 1], X[rs1]}; + XReg width = width_minus1 + 1; + X[rd] = sext((pair >> shamt) & ((1 << width) - 1), width_minus1); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extdpr.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extdpr.yaml new file mode 100644 index 0000000000..601156bfac --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extdpr.yaml @@ -0,0 +1,38 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.extdpr +long_name: Extract bits from pair signed, packed descriptor (Register) +description: | + Extract a subset of bits from the register pair [`rs1`, `rs1`+1] into `rd`, and sign extend the result. + The width of the subset is determined by `rs2` bits [15:8] + 1 (1..32), + and the offset of the subset is determined by `rs2` bits [7:0]. + Instruction encoded in R instruction format. +definedBy: + anyOf: + - Xqci + - Xqcibm +base: 32 +encoding: + match: 0001000----------011-----0001011 + variables: + - name: rs2 + location: 24-20 + not: 0 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1, xs2" +access: + s: always + u: always + vs: always + vu: always +operation(): | + Bits<{1'b0, XLEN}*2> pair = {X[rs1 + 1], X[rs1]}; + XReg width = X[rs2][15:8] + 1; + XReg shamt = X[rs2][7:0]; + X[rd] = sext((pair >> shamt) & ((1 << width) - 1), (width - 1)); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extdprh.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extdprh.yaml new file mode 100644 index 0000000000..01c29bfe4e --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extdprh.yaml @@ -0,0 +1,38 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.extdprh +long_name: Extract bits from pair signed, packed descriptor high part (Register) +description: | + Extract a subset of bits from the register pair [`rs1`, `rs1`+1] into `rd`, and sign extend the result. + The width of the subset is determined by `rs2` bits [31:24] + 1 (1..32), + and the offset of the subset is determined by `rs2` bits [23:16]. + Instruction encoded in R instruction format. +definedBy: + anyOf: + - Xqci + - Xqcibm +base: 32 +encoding: + match: 0001001----------011-----0001011 + variables: + - name: rs2 + location: 24-20 + not: 0 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1, xs2" +access: + s: always + u: always + vs: always + vu: always +operation(): | + Bits<{1'b0, XLEN}*2> pair = {X[rs1 + 1], X[rs1]}; + XReg width = X[rs2][31:24] + 1; + XReg shamt = X[rs2][23:16]; + X[rd] = sext((pair >> shamt) & ((1 << width) - 1), (width - 1)); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extdr.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extdr.yaml new file mode 100644 index 0000000000..e96b90f879 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extdr.yaml @@ -0,0 +1,38 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.extdr +long_name: Extract bits from pair signed (Register) +description: | + Extract a subset of bits from the register pair [`rs1`, `rs1`+1] into `rd`, and sign extend the result. + The width of the subset is determined by `rs2` bits [31:16] + 1 (1..32), + and the offset of the subset is determined by `rs2` bits [15:0]. + Instruction encoded in R instruction format. +definedBy: + anyOf: + - Xqci + - Xqcibm +base: 32 +encoding: + match: 0000101----------011-----0001011 + variables: + - name: rs2 + location: 24-20 + not: 0 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1, xs2" +access: + s: always + u: always + vs: always + vu: always +operation(): | + Bits<{1'b0, XLEN}*2> pair = {X[rs1 + 1], X[rs1]}; + XReg width = X[rs2][31:16] + 1; + XReg shamt = X[rs2][15:0]; + X[rd] = sext((pair >> shamt) & ((1 << width) - 1), (width - 1)); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extdu.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extdu.yaml new file mode 100644 index 0000000000..57f0ea22ee --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extdu.yaml @@ -0,0 +1,38 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.extdu +long_name: Extract bits from pair unsigned (Immediate) +description: | + Extract a subset of bits from the register pair [`rs1`, `rs1`+1] into `rd`. + The width of the subset is determined by (`width_minus1` + 1) (1..32), + and the offset (into the pair) of the subset is determined by `shamt`. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcibm +base: 32 +encoding: + match: 10---------------010-----0001011 + variables: + - name: width_minus1 + location: 29-25 + - name: shamt + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1, width, shamt" +access: + s: always + u: always + vs: always + vu: always +operation(): | + Bits<{1'b0, XLEN}*2> pair = {X[rs1 + 1], X[rs1]}; + XReg width = width_minus1 + 1; + X[rd] = (pair >> shamt) & ((1 << width) - 1); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extdupr.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extdupr.yaml new file mode 100644 index 0000000000..24ae8003fa --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extdupr.yaml @@ -0,0 +1,38 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.extdupr +long_name: Extract bits from pair unsigned, packed descriptor (Register) +description: | + Extract a subset of bits from the register pair [`rs1`, `rs1`+1] into `rd`. + The width of the subset is determined by `rs2` bits [15:8] + 1 (1..32), + and the offset of the subset is determined by `rs2` bits [7:0]. + Instruction encoded in R instruction format. +definedBy: + anyOf: + - Xqci + - Xqcibm +base: 32 +encoding: + match: 0000110----------011-----0001011 + variables: + - name: rs2 + location: 24-20 + not: 0 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1, xs2" +access: + s: always + u: always + vs: always + vu: always +operation(): | + Bits<{1'b0, XLEN}*2> pair = {X[rs1 + 1], X[rs1]}; + XReg width = X[rs2][15:8] + 1; + XReg shamt = X[rs2][7:0]; + X[rd] = (pair >> shamt) & ((1 << width) - 1); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extduprh.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extduprh.yaml new file mode 100644 index 0000000000..7e8e8ccd6c --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extduprh.yaml @@ -0,0 +1,38 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.extduprh +long_name: Extract bits from pair unsigned, packed descriptor high part (Register) +description: | + Extract a subset of bits from the register pair [`rs1`, `rs1`+1] into `rd`. + The width of the subset is determined by `rs2` bits [31:24] + 1 (1..32), + and the offset of the subset is determined by `rs2` bits [23:16]. + Instruction encoded in R instruction format. +definedBy: + anyOf: + - Xqci + - Xqcibm +base: 32 +encoding: + match: 0000111----------011-----0001011 + variables: + - name: rs2 + location: 24-20 + not: 0 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1, xs2" +access: + s: always + u: always + vs: always + vu: always +operation(): | + Bits<{1'b0, XLEN}*2> pair = {X[rs1 + 1], X[rs1]}; + XReg width = X[rs2][31:24] + 1; + XReg shamt = X[rs2][23:16]; + X[rd] = (pair >> shamt) & ((1 << width) - 1); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extdur.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extdur.yaml new file mode 100644 index 0000000000..80803b300b --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extdur.yaml @@ -0,0 +1,38 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.extdur +long_name: Extract bits from pair unsigned (Register) +description: | + Extract a subset of bits from the register pair [`rs1`, `rs1`+1] into `rd`. + The width of the subset is determined by `rs2` bits [31:16] + 1 (1..32), + and the offset of the subset is determined by `rs2` bits [15:0]. + Instruction encoded in R instruction format. +definedBy: + anyOf: + - Xqci + - Xqcibm +base: 32 +encoding: + match: 0000100----------011-----0001011 + variables: + - name: rs2 + location: 24-20 + not: 0 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1, xs2" +access: + s: always + u: always + vs: always + vu: always +operation(): | + Bits<{1'b0, XLEN}*2> pair = {X[rs1 + 1], X[rs1]}; + XReg width = X[rs2][31:16] + 1; + XReg shamt = X[rs2][15:0]; + X[rd] = (pair >> shamt) & ((1 << width) - 1); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extu.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extu.yaml new file mode 100644 index 0000000000..279c7d4386 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.extu.yaml @@ -0,0 +1,38 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.extu +long_name: Extract bits unsigned +description: | + Extract a subset of bits from `rs1` into `rd`. + The width of the subset is determined by (`width_minus1` + 1) (1..32), + and the offset of the subset is determined by `shamt`. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcibm +base: 32 +encoding: + match: 00---------------010-----0001011 + variables: + - name: width_minus1 + location: 29-25 + - name: shamt + location: 24-20 + - name: rs1 + location: 19-15 + not: 0 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1, width, shamt" +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg width = width_minus1 + 1; + X[rd] = (X[rs1] >> shamt) & ((1 << width) - 1); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.insb.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.insb.yaml new file mode 100644 index 0000000000..4b4f56ee93 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.insb.yaml @@ -0,0 +1,39 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.insb +long_name: Insert bits (Register) +description: | + Insertion of a subset of bits from `rs1` into `rd`. + The width of the subset is determined by (`width_minus1` + 1) (1..32), + and the offset of the subset is determined by `shamt`. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcibm +base: 32 +encoding: + match: 01---------------001-----0001011 + variables: + - name: width_minus1 + location: 29-25 + - name: shamt + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1, width, shamt" +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg width = width_minus1 + 1; + XReg mask = ((1 << width) - 1) << shamt; + XReg orig_val = X[rd]; + X[rd] = (orig_val & ~mask) | ((X[rs1] << shamt) & mask); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.insbh.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.insbh.yaml new file mode 100644 index 0000000000..38782be7f8 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.insbh.yaml @@ -0,0 +1,46 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.insbh +long_name: Insert bits in 64-bit higher part (Register) +description: | + Insertion of a subset of bits from `rs1` into `rd`. + Instruction intended for insertion bits into bitfield within 64-bits, + when bitfield crosses 32-bit bundary. + Lower part of 64-bit destination is inserted using QC32.INSB, + higher part using QC32.INSBH. + The width of the subset is determined by (`width_minus1` + 1) (1..32), + and the offset of the subset is determined by `shamt`. + In case when width + offset <= 32, the destination register is left unchanged. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcibm +base: 32 +encoding: + match: 10---------------001-----0001011 + variables: + - name: width_minus1 + location: 29-25 + - name: shamt + location: 24-20 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1, width, shamt" +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg width = width_minus1 + 1; + if (width + shamt > 32) { + XReg mask = ((1 << (width + shamt - 32)) - 1); + XReg orig_val = X[rd]; + X[rd] = (orig_val & ~mask) | ((X[rs1] >> (32 - shamt)) & mask); + } diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.insbhr.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.insbhr.yaml new file mode 100644 index 0000000000..98f5a22bc4 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.insbhr.yaml @@ -0,0 +1,46 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.insbhr +long_name: Insert bits in 64-bit higher part (Register) +description: | + Insertion of a subset of bits from `rs1` into `rd`. + Instruction intended for insertion bits into bitfield within 64-bits, + when bitfield crosses 32-bit bundary. + Lower part of 64-bit destination is inserted using QC32.INSB, + higher part using QC32.INSBH. + The width of the subset is determined by `rs2` bits [31:16] + 1 (1..32), + and the offset of the subset is determined by `rs2` bits [15:0]. + In case when width + offset <= 32, the destination register is left unchanged. + Instruction encoded in R instruction format. +definedBy: + anyOf: + - Xqci + - Xqcibm +base: 32 +encoding: + match: 0000001----------011-----0001011 + variables: + - name: rs2 + location: 24-20 + not: 0 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1, xs2" +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg width = X[rs2][31:16] + 1; + XReg shamt = X[rs2][15:0]; + if (width + shamt > 32) { + XReg mask = ((1 << (width + shamt - 32)) - 1); + XReg orig_val = X[rd]; + X[rd] = (orig_val & ~mask) | ((X[rs1] >> (32 - shamt)) & mask); + } diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.insbi.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.insbi.yaml new file mode 100644 index 0000000000..38f30b9aed --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.insbi.yaml @@ -0,0 +1,39 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.insbi +long_name: Insert bits (Immediate) +description: | + Insertion of a subset of bits of an `imm` into `rd`. + The width of the subset is determined by (`width_minus1` + 1) (1..32), + and the offset of the subset is determined by `shamt`. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcibm +base: 32 +encoding: + match: 00---------------001-----0001011 + variables: + - name: width_minus1 + location: 29-25 + - name: shamt + location: 24-20 + - name: imm + location: 19-15 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, imm, width, shamt" +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg width = width_minus1 + 1; + XReg mask = ((1 << width) - 1) << shamt; + XReg orig_val = X[rd]; + X[rd] = (orig_val & ~mask) | ((imm << shamt) & mask); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.insbpr.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.insbpr.yaml new file mode 100644 index 0000000000..860f7b1960 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.insbpr.yaml @@ -0,0 +1,39 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.insbpr +long_name: Insert bits, packed descriptor (Register) +description: | + Insertion of a subset of bits from `rs1` into `rd`. + The width of the subset is determined by `rs2` bits [15:8] + 1 (1..32), + and the offset of the subset is determined by `rs2` bits [7:0]. + Instruction encoded in R instruction format. +definedBy: + anyOf: + - Xqci + - Xqcibm +base: 32 +encoding: + match: 0000010----------011-----0001011 + variables: + - name: rs2 + location: 24-20 + not: 0 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1, xs2" +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg width = X[rs2][15:8] + 1; + XReg shamt = X[rs2][7:0]; + XReg mask = ((1 << width) - 1) << shamt; + XReg orig_val = X[rd]; + X[rd] = (orig_val & ~mask) | ((X[rs1] << shamt) & mask); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.insbprh.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.insbprh.yaml new file mode 100644 index 0000000000..3fa4e99520 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.insbprh.yaml @@ -0,0 +1,39 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.insbprh +long_name: Insert bits, packed descriptor high part (Register) +description: | + Insertion of a subset of bits from `rs1` into `rd`. + The width of the subset is determined by `rs2` bits [31:24] + 1 (1..32), + and the offset of the subset is determined by `rs2` bits [23:15]. + Instruction encoded in R instruction format. +definedBy: + anyOf: + - Xqci + - Xqcibm +base: 32 +encoding: + match: 0000011----------011-----0001011 + variables: + - name: rs2 + location: 24-20 + not: 0 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1, xs2" +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg width = X[rs2][31:24] + 1; + XReg shamt = X[rs2][23:16]; + XReg mask = ((1 << width) - 1) << shamt; + XReg orig_val = X[rd]; + X[rd] = (orig_val & ~mask) | ((X[rs1] << shamt) & mask); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.insbr.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.insbr.yaml new file mode 100644 index 0000000000..b92863dcdd --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.insbr.yaml @@ -0,0 +1,39 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.insbr +long_name: Insert bits (Register) +description: | + Insertion of a subset of bits from `rs1` into `rd`. + The width of the subset is determined by `rs2` bits [31:16] + 1 (1..32), + and the offset of the subset is determined by `rs2` bits [15:0]. + Instruction encoded in R instruction format. +definedBy: + anyOf: + - Xqci + - Xqcibm +base: 32 +encoding: + match: 0000000----------011-----0001011 + variables: + - name: rs2 + location: 24-20 + not: 0 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1, xs2" +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg width = X[rs2][31:16] + 1; + XReg shamt = X[rs2][15:0]; + XReg mask = ((1 << width) - 1) << shamt; + XReg orig_val = X[rd]; + X[rd] = (orig_val & ~mask) | ((X[rs1] << shamt) & mask); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.insbri.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.insbri.yaml new file mode 100644 index 0000000000..7b1e2d7189 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.insbri.yaml @@ -0,0 +1,39 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.insbri +long_name: Insert bits (Immediate) +description: | + Insertion of a subset of bits of an `imm` into `rd`. + The width of the subset is determined by `rs1` bits [31:16] + 1, + and the offset of the subset is determined by `rs1` bits [15:0]. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcibm +base: 32 +encoding: + match: 1----------------000-----0001011 + variables: + - name: imm + location: 30-20 + - name: rs1 + location: 19-15 + not: 0 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1, imm" +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg width = X[rs1][31:16] + 1; + XReg shamt = X[rs1][15:0]; + XReg mask = ((1 << width) - 1) << shamt; + XReg orig_val = X[rd]; + X[rd] = (orig_val & ~mask) | ((imm << shamt) & mask); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.li.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.li.yaml new file mode 100644 index 0000000000..71029438d1 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.li.yaml @@ -0,0 +1,30 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.li +long_name: Load immediate large +description: | + Loads the 20-bit immediate `imm` into `rd`. + Instruction encoded in U instruction format. +definedBy: + anyOf: + - Xqci + - Xqcili +base: 32 +encoding: + match: -------------------------0011011 + variables: + - name: imm + location: 31|15-12|30-16 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, imm" +access: + s: always + u: always + vs: always + vu: always +operation(): | + X[rd] = sext(imm,20); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lieq.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lieq.yaml new file mode 100644 index 0000000000..53335507d0 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lieq.yaml @@ -0,0 +1,38 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.lieq +long_name: Conditional load immediate if equal (Register) +description: | + Move `simm` to `rd` if the value in `rs1` is equal to value `rs2`. + Instruction encoded in R instruction format. +definedBy: + anyOf: + - Xqci + - Xqcicli +base: 32 +encoding: + match: -----01----------000-----1011011 + variables: + - name: rs1 + location: 19-15 + not: 0 + - name: rs2 + location: 24-20 + not: 0 + - name: simm + location: 31-27 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1, xs2, simm" +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (X[rs1] == X[rs2]) { + X[rd] = sext(simm, 20); + } diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lieqi.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lieqi.yaml new file mode 100644 index 0000000000..b49b8f20ca --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lieqi.yaml @@ -0,0 +1,37 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.lieqi +long_name: Conditional load immediate if equal (Immediate) +description: | + Move `simm` to `rd` if the value in `rs1` is equal to value `imm`. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcicli +base: 32 +encoding: + match: -----11----------000-----1011011 + variables: + - name: rs1 + location: 19-15 + not: 0 + - name: imm + location: 24-20 + - name: simm + location: 31-27 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1, imm, simm" +access: + s: always + u: always + vs: always + vu: always +operation(): | + if ($signed(X[rs1]) == $signed(imm)) { + X[rd] = sext(simm, 5); + } diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lige.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lige.yaml new file mode 100644 index 0000000000..6a8a5a6d46 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lige.yaml @@ -0,0 +1,38 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.lige +long_name: Conditional load immediate if great or equal than (Register) +description: | + Move `simm` to `rd` if the value in `rs1` is great or equal than value `rs2`. + Instruction encoded in R instruction format. +definedBy: + anyOf: + - Xqci + - Xqcicli +base: 32 +encoding: + match: -----01----------101-----1011011 + variables: + - name: rs1 + location: 19-15 + not: 0 + - name: rs2 + location: 24-20 + not: 0 + - name: simm + location: 31-27 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1, xs2, simm" +access: + s: always + u: always + vs: always + vu: always +operation(): | + if ($signed(X[rs1]) >= $signed(X[rs2])) { + X[rd] = sext(simm, 5); + } diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.ligei.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.ligei.yaml new file mode 100644 index 0000000000..8f4a33628e --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.ligei.yaml @@ -0,0 +1,37 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.ligei +long_name: Conditional load immediate if great or equal than (Immediate) +description: | + Move `simm` to `rd` if the value in `rs1` is great or equal than value `imm`. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcicli +base: 32 +encoding: + match: -----11----------101-----1011011 + variables: + - name: rs1 + location: 19-15 + not: 0 + - name: imm + location: 24-20 + - name: simm + location: 31-27 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1, imm, simm" +access: + s: always + u: always + vs: always + vu: always +operation(): | + if ($signed(X[rs1]) >= $signed(imm)) { + X[rd] = sext(simm, 5); + } diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.ligeu.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.ligeu.yaml new file mode 100644 index 0000000000..0b35113c56 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.ligeu.yaml @@ -0,0 +1,38 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.ligeu +long_name: Conditional load immediate if great or equal than unsigned (Register) +description: | + Move `simm` to `rd` if the unsigned value in `rs1` is great or equal than unsigned value `rs2`. + Instruction encoded in R instruction format. +definedBy: + anyOf: + - Xqci + - Xqcicli +base: 32 +encoding: + match: -----01----------111-----1011011 + variables: + - name: rs1 + location: 19-15 + not: 0 + - name: rs2 + location: 24-20 + not: 0 + - name: simm + location: 31-27 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1, xs2, simm" +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (X[rs1] >= X[rs2]) { + X[rd] = sext(simm, 5); + } diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.ligeui.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.ligeui.yaml new file mode 100644 index 0000000000..3d64021464 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.ligeui.yaml @@ -0,0 +1,37 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.ligeui +long_name: Conditional load immediate if great or equal than unsigned (Immediate) +description: | + Move `simm` to `rd` if the unsigned value in `rs1` is great or equal than unsigned value `imm`. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcicli +base: 32 +encoding: + match: -----11----------111-----1011011 + variables: + - name: rs1 + location: 19-15 + not: 0 + - name: imm + location: 24-20 + - name: simm + location: 31-27 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1, imm, simm" +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (X[rs1] >= imm) { + X[rd] = sext(simm, 5); + } diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lilt.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lilt.yaml new file mode 100644 index 0000000000..dda2f5ee2e --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lilt.yaml @@ -0,0 +1,38 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.lilt +long_name: Conditional load immediate if less than (Register) +description: | + Move `simm` to `rd` if the value in `rs1` is less than value `rs2`. + Instruction encoded in R instruction format. +definedBy: + anyOf: + - Xqci + - Xqcicli +base: 32 +encoding: + match: -----01----------100-----1011011 + variables: + - name: rs1 + location: 19-15 + not: 0 + - name: rs2 + location: 24-20 + not: 0 + - name: simm + location: 31-27 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1, xs2, simm" +access: + s: always + u: always + vs: always + vu: always +operation(): | + if ($signed(X[rs1]) < $signed(X[rs2])) { + X[rd] = sext(simm, 5); + } diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lilti.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lilti.yaml new file mode 100644 index 0000000000..6289a3e183 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lilti.yaml @@ -0,0 +1,37 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.lilti +long_name: Conditional load immediate if less than (Immediate) +description: | + Move `simm` to `rd` if the value in `rs1` is less than value `imm`. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcicli +base: 32 +encoding: + match: -----11----------100-----1011011 + variables: + - name: rs1 + location: 19-15 + not: 0 + - name: imm + location: 24-20 + - name: simm + location: 31-27 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1, imm, simm" +access: + s: always + u: always + vs: always + vu: always +operation(): | + if ($signed(X[rs1]) < $signed(imm)) { + X[rd] = sext(simm, 5); + } diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.liltu.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.liltu.yaml new file mode 100644 index 0000000000..78fc5f27ff --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.liltu.yaml @@ -0,0 +1,38 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.liltu +long_name: Conditional load immediate if less than unsigned (Register) +description: | + Move `simm` to `rd` if the unsigned value in `rs1` is less than unsigned value `rs2`. + Instruction encoded in R instruction format. +definedBy: + anyOf: + - Xqci + - Xqcicli +base: 32 +encoding: + match: -----01----------110-----1011011 + variables: + - name: rs1 + location: 19-15 + not: 0 + - name: rs2 + location: 24-20 + not: 0 + - name: simm + location: 31-27 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1, xs2, simm" +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (X[rs1] < X[rs2]) { + X[rd] = sext(simm, 5); + } diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.liltui.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.liltui.yaml new file mode 100644 index 0000000000..eb19e26145 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.liltui.yaml @@ -0,0 +1,37 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.liltui +long_name: Conditional load immediate if less than unsigned (Immediate) +description: | + Move `simm` to `rd` if the unsigned value in `rs1` is less than unsigned value `imm`. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcicli +base: 32 +encoding: + match: -----11----------110-----1011011 + variables: + - name: rs1 + location: 19-15 + not: 0 + - name: imm + location: 24-20 + - name: simm + location: 31-27 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1, imm, simm" +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (X[rs1] < imm) { + X[rd] = sext(simm, 5); + } diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.line.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.line.yaml new file mode 100644 index 0000000000..57575592c2 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.line.yaml @@ -0,0 +1,38 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.line +long_name: Conditional load immediate if not equal (Register) +description: | + Move `simm` to `rd` if the value in `rs1` is not equal to value `rs2`. + Instruction encoded in R instruction format. +definedBy: + anyOf: + - Xqci + - Xqcicli +base: 32 +encoding: + match: -----01----------001-----1011011 + variables: + - name: rs1 + location: 19-15 + not: 0 + - name: rs2 + location: 24-20 + not: 0 + - name: simm + location: 31-27 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1, xs2, simm" +access: + s: always + u: always + vs: always + vu: always +operation(): | + if ($signed(X[rs1]) != $signed(X[rs2])) { + X[rd] = sext(simm, 5); + } diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.linei.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.linei.yaml new file mode 100644 index 0000000000..0e27c15bc7 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.linei.yaml @@ -0,0 +1,37 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.linei +long_name: Conditional load immediate if not equal (Immediate) +description: | + Move `simm` to `rd` if the value in `rs1` is not equal to value `imm`. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcicli +base: 32 +encoding: + match: -----11----------001-----1011011 + variables: + - name: rs1 + location: 19-15 + not: 0 + - name: imm + location: 24-20 + - name: simm + location: 31-27 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1, imm, simm" +access: + s: always + u: always + vs: always + vu: always +operation(): | + if ($signed(X[rs1]) != $signed(imm)) { + X[rd] = sext(simm, 5); + } diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lrb.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lrb.yaml new file mode 100644 index 0000000000..1a62cafe72 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lrb.yaml @@ -0,0 +1,37 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.lrb +long_name: Load indexed byte +description: | + Load 8 bits of data into register `rd` from an + address formed by adding `rs1` to `rs2`, shifted by `shamt`. + Sign extend the result. + Instruction encoded in R instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisls +assembly: " xd, xs1, xs2, shamt" +base: 32 +encoding: + match: 1000-------------111-----0001011 + variables: + - name: shamt + location: 27-25 + - name: rs1 + location: 19-15 + - name: rs2 + location: 24-20 + not: 0 + - name: rd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg virtual_address = X[rs1] + (X[rs2] << shamt); + X[rd] = sext(read_memory<8>(virtual_address, $encoding), 8); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lrbu.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lrbu.yaml new file mode 100644 index 0000000000..a36e6ffcf2 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lrbu.yaml @@ -0,0 +1,36 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.lrbu +long_name: Load indexed unsigned byte +description: | + Load 8 bits of data into register `rd` from an + address formed by adding `rs1` to `rs2`, shifted by `shamt`. + Instruction encoded in R instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisls +assembly: " xd, xs1, xs2, shamt" +base: 32 +encoding: + match: 1011-------------111-----0001011 + variables: + - name: shamt + location: 27-25 + - name: rs1 + location: 19-15 + - name: rs2 + location: 24-20 + not: 0 + - name: rd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg virtual_address = X[rs1] + (X[rs2] << shamt); + X[rd] = read_memory<8>(virtual_address, $encoding); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lrh.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lrh.yaml new file mode 100644 index 0000000000..51c8385c16 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lrh.yaml @@ -0,0 +1,37 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.lrh +long_name: Load indexed halfword +description: | + Load 16 bits of data into register `rd` from an + address formed by adding `rs1` to `rs2`, shifted by `shamt`. + Sign extend the result. + Instruction encoded in R instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisls +assembly: " xd, xs1, xs2, shamt" +base: 32 +encoding: + match: 1001-------------111-----0001011 + variables: + - name: shamt + location: 27-25 + - name: rs1 + location: 19-15 + - name: rs2 + location: 24-20 + not: 0 + - name: rd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg virtual_address = X[rs1] + (X[rs2] << shamt); + X[rd] = sext(read_memory<16>(virtual_address, $encoding), 16); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lrhu.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lrhu.yaml new file mode 100644 index 0000000000..87dc737677 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lrhu.yaml @@ -0,0 +1,36 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.lrhu +long_name: Load indexed unsigned halfword +description: | + Load 16 bits of data into register `rd` from an + address formed by adding `rs1` to `rs2`, shifted by `shamt`. + Instruction encoded in R instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisls +assembly: " xd, xs1, xs2, shamt" +base: 32 +encoding: + match: 1100-------------111-----0001011 + variables: + - name: shamt + location: 27-25 + - name: rs1 + location: 19-15 + - name: rs2 + location: 24-20 + not: 0 + - name: rd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg virtual_address = X[rs1] + (X[rs2] << shamt); + X[rd] = read_memory<16>(virtual_address, $encoding); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lrw.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lrw.yaml new file mode 100644 index 0000000000..a2dd08aeb6 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lrw.yaml @@ -0,0 +1,36 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.lrw +long_name: Load indexed word +description: | + Load 32 bits of data into register `rd` from an + address formed by adding `rs1` to `rs2`, shifted by `shamt`. + Instruction encoded in R instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisls +assembly: xd, xs1, xs2, shamt +base: 32 +encoding: + match: 1010-------------111-----0001011 + variables: + - name: shamt + location: 27-25 + - name: rs1 + location: 19-15 + - name: rs2 + location: 24-20 + not: 0 + - name: rd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg virtual_address = X[rs1] + (X[rs2] << shamt); + X[rd] = read_memory<32>(virtual_address, $encoding); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lwm.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lwm.yaml new file mode 100644 index 0000000000..1ce3f6aa20 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lwm.yaml @@ -0,0 +1,43 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.lwm +long_name: Load word multiple +description: | + Loads multiple words starting from address (`rs1` + `imm`) to registers, starting from `rd`. + The number of words is in `rs2`. + Instruction encoded in R instruction format. +definedBy: + anyOf: + - Xqci + - Xqcilsm +base: 32 +encoding: + match: 00---------------111-----0001011 + variables: + - name: imm + location: 29-25 + left_shift: 2 + - name: rs1 + location: 19-15 + - name: rs2 + location: 24-20 + not: 0 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs2, imm(xs1)" +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg vaddr = X[rs1] + imm; + XReg num_words = X[rs2]; + raise (ExceptionCode::IllegalInstruction, effective_ldst_mode(), $encoding) if ((rd + num_words) > 32); + for (U32 i = 0; i < num_words; i++) { + X[rd + i] = read_memory<32>(vaddr, $encoding); + vaddr = vaddr + 4; + } diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lwmi.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lwmi.yaml new file mode 100644 index 0000000000..2fbc7ef37d --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lwmi.yaml @@ -0,0 +1,42 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.lwmi +long_name: Load word multiple (Immediate) +description: | + Loads multiple words starting from address (`rs1` + `imm`) to registers, starting from `rd`. + The number of words is in the `length` immediate. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcilsm +base: 32 +encoding: + match: 01---------------111-----0001011 + variables: + - name: imm + location: 29-25 + left_shift: 2 + - name: rs1 + location: 19-15 + - name: length + location: 24-20 + not: 0 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, length, imm(xs1)" +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg vaddr = X[rs1] + imm; + raise (ExceptionCode::IllegalInstruction, effective_ldst_mode(), $encoding) if ((rd + length) > 32); + for (U32 i = 0; i < length; i++) { + X[rd + i] = read_memory<32>(vaddr, $encoding); + vaddr = vaddr + 4; + } diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.muladdi.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.muladdi.yaml new file mode 100644 index 0000000000..4c92acdf23 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.muladdi.yaml @@ -0,0 +1,34 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.muladdi +long_name: Multiply and accumulate (Immediate) +description: | + Increments `rd` by the multiplication of `rs1` and a signed immediate `imm`. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqciac +base: 32 +encoding: + match: -----------------110-----0001011 + variables: + - name: imm + location: 31-20 + - name: rs1 + location: 19-15 + not: 0 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1, imm" +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg orig_val = X[rd]; + X[rd] = orig_val + (X[rs1] * sext(imm,12)); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mveq.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mveq.yaml new file mode 100644 index 0000000000..930a0b350b --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mveq.yaml @@ -0,0 +1,39 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.mveq +long_name: Conditional move if equal (Register) +description: | + Move `rs3` to `rd` if the value in `rs1` is equal to value `rs2`. + Instruction encoded in R4 instruction format. +definedBy: + anyOf: + - Xqci + - Xqcicm +base: 32 +encoding: + match: -----00----------000-----1011011 + variables: + - name: rs1 + location: 19-15 + not: 0 + - name: rs2 + location: 24-20 + not: 0 + - name: rs3 + location: 31-27 + not: 0 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1, xs2, xs3" +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (X[rs1] == X[rs2]) { + X[rd] = X[rs3]; + } diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mveqi.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mveqi.yaml new file mode 100644 index 0000000000..3f201f269a --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mveqi.yaml @@ -0,0 +1,38 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.mveqi +long_name: Conditional move if equal (Immediate) +description: | + Move `rs3` to `rd` if the value in `rs1` is equal to value of `imm`. + Instruction encoded in R4 instruction format. +definedBy: + anyOf: + - Xqci + - Xqcicm +base: 32 +encoding: + match: -----10----------000-----1011011 + variables: + - name: rs1 + location: 19-15 + not: 0 + - name: imm + location: 24-20 + - name: rs3 + location: 31-27 + not: 0 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1, imm, xs3" +access: + s: always + u: always + vs: always + vu: always +operation(): | + if ($signed(X[rs1]) == $signed(imm)) { + X[rd] = X[rs3]; + } diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvge.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvge.yaml new file mode 100644 index 0000000000..bf519fb4f5 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvge.yaml @@ -0,0 +1,39 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.mvge +long_name: Conditional move if great or equal than (Register) +description: | + Move `rs3` to `rd` if the value in `rs1` is great or equal than value `rs2`. + Instruction encoded in R4 instruction format. +definedBy: + anyOf: + - Xqci + - Xqcicm +base: 32 +encoding: + match: -----00----------101-----1011011 + variables: + - name: rs1 + location: 19-15 + not: 0 + - name: rs2 + location: 24-20 + not: 0 + - name: rs3 + location: 31-27 + not: 0 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1, xs2, xs3" +access: + s: always + u: always + vs: always + vu: always +operation(): | + if ($signed(X[rs1]) >= $signed(X[rs2])) { + X[rd] = X[rs3]; + } diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvgei.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvgei.yaml new file mode 100644 index 0000000000..8af121d122 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvgei.yaml @@ -0,0 +1,38 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.mvgei +long_name: Conditional move if great or equal than (Immediate) +description: | + Move `rs3` to `rd` if the value in `rs1` is great or equal than value of `imm`. + Instruction encoded in R4 instruction format. +definedBy: + anyOf: + - Xqci + - Xqcicm +base: 32 +encoding: + match: -----10----------101-----1011011 + variables: + - name: rs1 + location: 19-15 + not: 0 + - name: imm + location: 24-20 + - name: rs3 + location: 31-27 + not: 0 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1, imm, xs3" +access: + s: always + u: always + vs: always + vu: always +operation(): | + if ($signed(X[rs1]) >= $signed(imm)) { + X[rd] = X[rs3]; + } diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvgeu.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvgeu.yaml new file mode 100644 index 0000000000..95d07d14c6 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvgeu.yaml @@ -0,0 +1,39 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.mvgeu +long_name: Conditional move if great or equal than unsigned (Register) +description: | + Move `rs3` to `rd` if the unsigned value in `rs1` is great or equal than unsigned value `rs2`. + Instruction encoded in R4 instruction format. +definedBy: + anyOf: + - Xqci + - Xqcicm +base: 32 +encoding: + match: -----00----------111-----1011011 + variables: + - name: rs1 + location: 19-15 + not: 0 + - name: rs2 + location: 24-20 + not: 0 + - name: rs3 + location: 31-27 + not: 0 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1, xs2, xs3" +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (X[rs1] >= X[rs2]) { + X[rd] = X[rs3]; + } diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvgeui.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvgeui.yaml new file mode 100644 index 0000000000..64179fadcc --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvgeui.yaml @@ -0,0 +1,38 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.mvgeui +long_name: Conditional move if great or equal than unsigned (Immediate) +description: | + Move `rs3` to `rd` if the unsigned value in `rs1` is great or equal than unsigned value of `imm`. + Instruction encoded in R4 instruction format. +definedBy: + anyOf: + - Xqci + - Xqcicm +base: 32 +encoding: + match: -----10----------111-----1011011 + variables: + - name: rs1 + location: 19-15 + not: 0 + - name: imm + location: 24-20 + - name: rs3 + location: 31-27 + not: 0 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1, imm, xs3" +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (X[rs1] >= imm) { + X[rd] = X[rs3]; + } diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvlt.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvlt.yaml new file mode 100644 index 0000000000..44f1249cfb --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvlt.yaml @@ -0,0 +1,39 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.mvlt +long_name: Conditional move if less than (Register) +description: | + Move `rs3` to `rd` if the value in `rs1` is less than value `rs2`. + Instruction encoded in R4 instruction format. +definedBy: + anyOf: + - Xqci + - Xqcicm +base: 32 +encoding: + match: -----00----------100-----1011011 + variables: + - name: rs1 + location: 19-15 + not: 0 + - name: rs2 + location: 24-20 + not: 0 + - name: rs3 + location: 31-27 + not: 0 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1, xs2, xs3" +access: + s: always + u: always + vs: always + vu: always +operation(): | + if ($signed(X[rs1]) < $signed(X[rs2])) { + X[rd] = X[rs3]; + } diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvlti.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvlti.yaml new file mode 100644 index 0000000000..4b3913b90f --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvlti.yaml @@ -0,0 +1,38 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.mvlti +long_name: Conditional move if less than (Immediate) +description: | + Move `rs3` to `rd` if the value in `rs1` is less than value of `imm`. + Instruction encoded in R4 instruction format. +definedBy: + anyOf: + - Xqci + - Xqcicm +base: 32 +encoding: + match: -----10----------100-----1011011 + variables: + - name: rs1 + location: 19-15 + not: 0 + - name: imm + location: 24-20 + - name: rs3 + location: 31-27 + not: 0 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1, imm, xs3" +access: + s: always + u: always + vs: always + vu: always +operation(): | + if ($signed(X[rs1]) < $signed(imm)) { + X[rd] = X[rs3]; + } diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvltu.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvltu.yaml new file mode 100644 index 0000000000..cce9dd740d --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvltu.yaml @@ -0,0 +1,39 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.mvltu +long_name: Conditional move if less than unsigned (Register) +description: | + Move `rs3` to `rd` if the unsigned value in `rs1` is less than unsigned value `rs2`. + Instruction encoded in R4 instruction format. +definedBy: + anyOf: + - Xqci + - Xqcicm +base: 32 +encoding: + match: -----00----------110-----1011011 + variables: + - name: rs1 + location: 19-15 + not: 0 + - name: rs2 + location: 24-20 + not: 0 + - name: rs3 + location: 31-27 + not: 0 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1, xs2, xs3" +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (X[rs1] < X[rs2]) { + X[rd] = X[rs3]; + } diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvltui.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvltui.yaml new file mode 100644 index 0000000000..b08fe09d84 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvltui.yaml @@ -0,0 +1,38 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.mvltui +long_name: Conditional move if less than unsigned (Immediate) +description: | + Move `rs3` to `rd` if the unsigned value in `rs1` is less than unsigned value of `imm`. + Instruction encoded in R4 instruction format. +definedBy: + anyOf: + - Xqci + - Xqcicm +base: 32 +encoding: + match: -----10----------110-----1011011 + variables: + - name: rs1 + location: 19-15 + not: 0 + - name: imm + location: 24-20 + - name: rs3 + location: 31-27 + not: 0 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1, imm, xs3" +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (X[rs1] < imm) { + X[rd] = X[rs3]; + } diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvne.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvne.yaml new file mode 100644 index 0000000000..ed2d2848f8 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvne.yaml @@ -0,0 +1,39 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.mvne +long_name: Conditional move if not equal (Register) +description: | + Move `rs3` to `rd` if the value in `rs1` is not equal to value `rs2`. + Instruction encoded in R4 instruction format. +definedBy: + anyOf: + - Xqci + - Xqcicm +base: 32 +encoding: + match: -----00----------001-----1011011 + variables: + - name: rs1 + location: 19-15 + not: 0 + - name: rs2 + location: 24-20 + not: 0 + - name: rs3 + location: 31-27 + not: 0 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1, xs2, xs3" +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (X[rs1] != X[rs2]) { + X[rd] = X[rs3]; + } diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvnei.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvnei.yaml new file mode 100644 index 0000000000..9015012b23 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.mvnei.yaml @@ -0,0 +1,38 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.mvnei +long_name: Conditional move if not equal (Immediate) +description: | + Move `rs3` to `rd` if the value in `rs1` is not equal to value `imm`. + Instruction encoded in R4 instruction format. +definedBy: + anyOf: + - Xqci + - Xqcicm +base: 32 +encoding: + match: -----10----------001-----1011011 + variables: + - name: rs1 + location: 19-15 + not: 0 + - name: imm + location: 24-20 + - name: rs3 + location: 31-27 + not: 0 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1, imm, xs3" +access: + s: always + u: always + vs: always + vu: always +operation(): | + if ($signed(X[rs1]) != $signed(imm)) { + X[rd] = X[rs3]; + } diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.norm.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.norm.yaml new file mode 100644 index 0000000000..8fe5c096ce --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.norm.yaml @@ -0,0 +1,38 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.norm +long_name: Signed Normalization +description: | + Signed normalization of `rs1`. + Exponent written in bits[7:0] of the result. + Mantissa written in bits[31:8] of the result. + Write result to `rd`. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcia +base: 32 +encoding: + match: 000011100000-----011-----0001011 + variables: + - name: rs1 + location: 19-15 + not: 0 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1" +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg clz = (xlen() - 1) - $signed(highest_set_bit(X[rs1])); + XReg clo = (xlen() - 1) - $signed(highest_set_bit(~X[rs1])); + XReg exp = (X[rs1][31] == 1) ? (X[rs1] << (clo - 1)) : (X[rs1] << (clz - 1)); + XReg mnt = (X[rs1][31] == 1) ? (-(clo - 1)) : (-(clz - 1)); + X[rd] = {mnt[23:0],exp[7:0]}; diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.normeu.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.normeu.yaml new file mode 100644 index 0000000000..ed1192add6 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.normeu.yaml @@ -0,0 +1,37 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.normeu +long_name: Unsigned Even Normalization +description: | + Unsigned even normalization of `rs1` (exponent is even). + Even exponent written in bits[7:0] of the result. + Mantissa (based on even exponent) written in bits[31:8] of the result. + Write result to `rd`. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcia +base: 32 +encoding: + match: 000100100000-----011-----0001011 + variables: + - name: rs1 + location: 19-15 + not: 0 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1" +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg clz = ((xlen() - 1) - $signed(highest_set_bit(X[rs1]))) & ~1; + XReg exp = (X[rs1] << clz); + XReg mnt = (-clz); + X[rd] = {mnt[23:0],exp[7:0]}; diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.normu.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.normu.yaml new file mode 100644 index 0000000000..ff9b5b5690 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.normu.yaml @@ -0,0 +1,37 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.normu +long_name: Unsigned Normalization +description: | + Unsigned normalization of `rs1`. + Exponent written in bits[7:0] of the result. + Mantissa written in bits[31:8] of the result. + Write result to `rd`. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcia +base: 32 +encoding: + match: 000100000000-----011-----0001011 + variables: + - name: rs1 + location: 19-15 + not: 0 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1" +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg clz = (xlen() - 1) - $signed(highest_set_bit(X[rs1])); + XReg exp = (X[rs1] << clz); + XReg mnt = (-clz); + X[rd] = {mnt[23:0],exp[7:0]}; diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.selecteqi.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.selecteqi.yaml new file mode 100644 index 0000000000..3a86c8dbfc --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.selecteqi.yaml @@ -0,0 +1,41 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.selecteqi +long_name: Select load immediate or register if equal (Immediate) +description: | + Move `rs2` to `rd` if the value in `rd` is equal to value `imm`, + move `rs3` to `rd` otherwise. + Instruction encoded in R4 instruction format. +definedBy: + anyOf: + - Xqci + - Xqcics +base: 32 +encoding: + match: -----10----------010-----1011011 + variables: + - name: imm + location: 19-15 + - name: rs2 + location: 24-20 + not: 0 + - name: rs3 + location: 31-27 + not: 0 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, imm, xs2, xs3" +access: + s: always + u: always + vs: always + vu: always +operation(): | + if ($signed(X[rd]) == $signed(imm)) { + X[rd] = X[rs2]; + } else { + X[rd] = X[rs3]; + } diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.selectieq.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.selectieq.yaml new file mode 100644 index 0000000000..765f5195cc --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.selectieq.yaml @@ -0,0 +1,41 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.selectieq +long_name: Select load immediate or register if equal (Register) +description: | + Move `rs2` to `rd` if the value in `rd` is equal to value `rs1`, + move `simm2` to `rd` otherwise. + Instruction encoded in R4 instruction format. +definedBy: + anyOf: + - Xqci + - Xqcics +base: 32 +encoding: + match: -----01----------010-----1011011 + variables: + - name: rs1 + location: 19-15 + not: 0 + - name: rs2 + location: 24-20 + not: 0 + - name: simm2 + location: 31-27 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1, xs2, simm2" +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (X[rd] == X[rs1]) { + X[rd] = X[rs2]; + } else { + X[rd] = sext(simm2, 5); + } diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.selectieqi.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.selectieqi.yaml new file mode 100644 index 0000000000..0f35918737 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.selectieqi.yaml @@ -0,0 +1,40 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.selectieqi +long_name: Select load immediate or register if equal (Immediate) +description: | + Move `rs2` to `rd` if the value in `rd` is equal to value `imm`, + move `simm2` to `rd` otherwise. + Instruction encoded in R4 instruction format. +definedBy: + anyOf: + - Xqci + - Xqcics +base: 32 +encoding: + match: -----11----------010-----1011011 + variables: + - name: imm + location: 19-15 + - name: rs2 + location: 24-20 + not: 0 + - name: simm2 + location: 31-27 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, imm, xs2, simm2" +access: + s: always + u: always + vs: always + vu: always +operation(): | + if ($signed(X[rd]) == $signed(imm)) { + X[rd] = X[rs2]; + } else { + X[rd] = sext(simm2, 5); + } diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.selectiieq.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.selectiieq.yaml new file mode 100644 index 0000000000..72af39eb71 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.selectiieq.yaml @@ -0,0 +1,40 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.selectiieq +long_name: Select load immediate if equal (Register) +description: | + Move `simm1` to `rd` if the value in `rd` is equal to value `rs1`, + move `simm2` to `rd` otherwise. + Instruction encoded in R4 instruction format. +definedBy: + anyOf: + - Xqci + - Xqcics +base: 32 +encoding: + match: -----00----------010-----1011011 + variables: + - name: rs1 + location: 19-15 + not: 0 + - name: simm1 + location: 24-20 + - name: simm2 + location: 31-27 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1, simm1, simm2" +access: + s: always + u: always + vs: always + vu: always +operation(): | + if ($signed(X[rd]) == $signed(X[rs1])) { + X[rd] = sext(simm1, 5); + } else { + X[rd] = sext(simm2, 5); + } diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.selectiine.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.selectiine.yaml new file mode 100644 index 0000000000..65e341fe4a --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.selectiine.yaml @@ -0,0 +1,40 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.selectiine +long_name: Select load immediate if not equal (Register) +description: | + Move `simm1` to `rd` if the value in `rd` is not equal to value `rs1`, + move `simm2` to `rd` otherwise. + Instruction encoded in R4 instruction format. +definedBy: + anyOf: + - Xqci + - Xqcics +base: 32 +encoding: + match: -----00----------011-----1011011 + variables: + - name: rs1 + location: 19-15 + not: 0 + - name: simm1 + location: 24-20 + - name: simm2 + location: 31-27 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1, simm1, simm2" +access: + s: always + u: always + vs: always + vu: always +operation(): | + if ($signed(X[rd]) != $signed(X[rs1])) { + X[rd] = sext(simm1, 5); + } else { + X[rd] = sext(simm2, 5); + } diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.selectine.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.selectine.yaml new file mode 100644 index 0000000000..139b71385a --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.selectine.yaml @@ -0,0 +1,41 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.selectine +long_name: Select load immediate or register if not equal (Register) +description: | + Move `rs2` to `rd` if the value in `rd` is not equal to value `rs1`, + move `simm2` to `rd` otherwise. + Instruction encoded in R4 instruction format. +definedBy: + anyOf: + - Xqci + - Xqcics +base: 32 +encoding: + match: -----01----------011-----1011011 + variables: + - name: rs1 + location: 19-15 + not: 0 + - name: rs2 + location: 24-20 + not: 0 + - name: simm2 + location: 31-27 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1, xs2, simm2" +access: + s: always + u: always + vs: always + vu: always +operation(): | + if ($signed(X[rd]) != $signed(X[rs1])) { + X[rd] = X[rs2]; + } else { + X[rd] = sext(simm2, 5); + } diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.selectinei.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.selectinei.yaml new file mode 100644 index 0000000000..48107bd6e2 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.selectinei.yaml @@ -0,0 +1,40 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.selectinei +long_name: Select load immediate or register if not equal (Immediate) +description: | + Move `rs2` to `rd` if the value in `rd` is not equal to value `imm`, + move `simm2` to `rd` otherwise. + Instruction encoded in R4 instruction format. +definedBy: + anyOf: + - Xqci + - Xqcics +base: 32 +encoding: + match: -----11----------011-----1011011 + variables: + - name: imm + location: 19-15 + - name: rs2 + location: 24-20 + not: 0 + - name: simm2 + location: 31-27 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, imm, xs2, simm2" +access: + s: always + u: always + vs: always + vu: always +operation(): | + if ($signed(X[rd]) != $signed(imm)) { + X[rd] = X[rs2]; + } else { + X[rd] = sext(simm2, 5); + } diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.selectnei.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.selectnei.yaml new file mode 100644 index 0000000000..1cd63c9fbd --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.selectnei.yaml @@ -0,0 +1,41 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.selectnei +long_name: Select load immediate or register if not equal (Immediate) +description: | + Move `rs2` to `rd` if the value in `rd` is not equal to value `imm`, + move `rs3` to `rd` otherwise. + Instruction encoded in R4 instruction format. +definedBy: + anyOf: + - Xqci + - Xqcics +base: 32 +encoding: + match: -----10----------011-----1011011 + variables: + - name: imm + location: 19-15 + - name: rs2 + location: 24-20 + not: 0 + - name: rs3 + location: 31-27 + not: 0 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, imm, xs2, xs3" +access: + s: always + u: always + vs: always + vu: always +operation(): | + if ($signed(X[rd]) != $signed(imm)) { + X[rd] = X[rs2]; + } else { + X[rd] = X[rs3]; + } diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.setinti.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.setinti.yaml new file mode 100644 index 0000000000..a620f66043 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.setinti.yaml @@ -0,0 +1,32 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.setinti +long_name: Set interrupt (Immediate) +description: | + Set interrupt, interrupt number is in `imm` (0 - 1023). + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqciint +assembly: " imm" +base: 32 +encoding: + match: 1100110----------000000001110011 + variables: + - name: imm + location: 24-15 +access: + s: always + u: always + vs: always + vu: always +operation(): | + Bits<12> MCLICIP0_ADDR = CSR[qc_mclicip0].address(); + + XReg idx = imm / 32; + XReg bit = imm % 32; + XReg pre_csr = CSR[MCLICIP0_ADDR + idx].sw_read(); + CSR[MCLICIP0_ADDR + idx].sw_write(pre_csr | (1 << bit)); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.setwm.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.setwm.yaml new file mode 100644 index 0000000000..7b6dec12f5 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.setwm.yaml @@ -0,0 +1,42 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.setwm +long_name: Set word multiple (Register) +description: | + Stores the value of `rs3` multiple times into the address starting at (`rs1` + `imm`). + The number of writes is in `rs2`. + Instruction encoded in R instruction format. +definedBy: + anyOf: + - Xqci + - Xqcilsm +base: 32 +encoding: + match: 10---------------111-----0101011 + variables: + - name: imm + location: 29-25 + left_shift: 2 + - name: rs1 + location: 19-15 + - name: rs2 + location: 24-20 + not: 0 + - name: rs3 + location: 11-7 +assembly: " xs3, xs2, imm(xs1)" +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg vaddr = X[rs1] + imm; + Bits<32> write_value = X[rs3][31:0]; + XReg num_words = X[rs2]; + for (U32 i = 0; i < num_words; i++) { + write_memory<32>(vaddr, write_value, $encoding); + vaddr = vaddr + 4; + } diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.setwmi.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.setwmi.yaml new file mode 100644 index 0000000000..750c3fd251 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.setwmi.yaml @@ -0,0 +1,41 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.setwmi +long_name: Set word multiple (Immediate) +description: | + Stores the value of `rs3` multiple times into the address starting at (`rs1` + `imm`). + The number of writes is in length. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcilsm +base: 32 +encoding: + match: 11---------------111-----0101011 + variables: + - name: imm + location: 29-25 + left_shift: 2 + - name: rs1 + location: 19-15 + - name: length + location: 24-20 + not: 0 + - name: rs3 + location: 11-7 +assembly: xs3, length, imm(xs1) +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg vaddr = X[rs1] + imm; + Bits<32> write_value = X[rs3][31:0]; + for (U32 i = 0; i < length; i++) { + write_memory<32>(vaddr, write_value, $encoding); + vaddr = vaddr + 4; + } diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.shladd.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.shladd.yaml new file mode 100644 index 0000000000..026f521f44 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.shladd.yaml @@ -0,0 +1,38 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.shladd +long_name: Shift left and add (immediate) +description: | + Left shift _rs1_ by _shamt_ and add the value in _rs2_. + Instruction encoded in R instruction format. +definedBy: + anyOf: + - name: Xqci + version: ">= 0.2" + - Xqciac +base: 32 +encoding: + match: 01---------------011-----0001011 + variables: + - name: shamt + location: 29-25 + not: [0, 1, 2, 3] + - name: rs2 + location: 24-20 + not: 0 + - name: rs1 + location: 19-15 + not: 0 + - name: rd + location: 11-7 + not: 0 +assembly: " xs1, xs2, shamt" +access: + s: always + u: always + vs: always + vu: always +operation(): | + X[rd] = (X[rs1] << shamt) + X[rs2]; diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.slasat.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.slasat.yaml new file mode 100644 index 0000000000..3d4bc09ed9 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.slasat.yaml @@ -0,0 +1,45 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.slasat +long_name: Saturating arithmetic left shift +description: | + Left shift `rs1` by the value of `rs2`, and saturate the signed result. + The number of words is in `length`. + Instruction encoded in R instruction format. +definedBy: + anyOf: + - Xqci + - Xqcia +base: 32 +encoding: + match: 0001010----------011-----0001011 + variables: + - name: rs1 + location: 19-15 + not: 0 + - name: rs2 + location: 24-20 + not: 0 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1, xs2" +access: + s: always + u: always + vs: always + vu: always +operation(): | + Bits<{1'b0, XLEN}*2> shifted_value = X[rs1] << X[rs2][4:0]; + XReg most_negative_number = 1 << (xlen() - 1); + XReg most_positive_number = (1 << (xlen() - 1) - 1); + + if ($signed(shifted_value) < $signed(most_negative_number)) { + X[rd] = most_negative_number; + } else if ($signed(shifted_value) > $signed(most_positive_number)) { + X[rd] = most_positive_number; + } else { + X[rd] = shifted_value; + } diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.sllsat.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.sllsat.yaml new file mode 100644 index 0000000000..6c033af65d --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.sllsat.yaml @@ -0,0 +1,43 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.sllsat +long_name: Saturating logical left shift +description: | + Left shift `rs1` by the value of `rs2`, and saturate the unsigned result. + The number of words is in `length`. + Instruction encoded in R instruction format. +definedBy: + anyOf: + - Xqci + - Xqcia +base: 32 +encoding: + match: 0001100----------011-----0001011 + variables: + - name: rs1 + location: 19-15 + not: 0 + - name: rs2 + location: 24-20 + not: 0 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1, xs2" +access: + s: always + u: always + vs: always + vu: always +operation(): | + Bits<{1'b0, XLEN}*2> sext_double_width_rs1 = {{XLEN{X[rs1][xlen()-1]}}, X[rs1]}; + Bits<{1'b0, XLEN}*2> shifted_value = sext_double_width_rs1 << X[rs2][4:0]; + XReg largest_unsigned_value = {XLEN{1'b1}}; + + if (shifted_value > largest_unsigned_value) { + X[rd] = largest_unsigned_value; + } else { + X[rd] = shifted_value; + } diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.srb.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.srb.yaml new file mode 100644 index 0000000000..bb8a7648ad --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.srb.yaml @@ -0,0 +1,36 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.srb +long_name: Store indexed byte +description: | + Store 8 bits of data from register `rs3` to an + address formed by adding `rs1` to `rs2`, shifted by `shamt`. + Instruction encoded in R instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisls +assembly: " xs3, xs1, xs2, shamt" +base: 32 +encoding: + match: 1101-------------110-----0101011 + variables: + - name: shamt + location: 27-25 + - name: rs1 + location: 19-15 + - name: rs2 + location: 24-20 + not: 0 + - name: rs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg virtual_address = X[rs1] + (X[rs2] << shamt); + write_memory<8>(virtual_address, X[rs3][7:0], $encoding); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.srh.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.srh.yaml new file mode 100644 index 0000000000..7cbc102e65 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.srh.yaml @@ -0,0 +1,36 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.srh +long_name: Store indexed halfword +description: | + Store 16 bits of data from register `rs3` to an + address formed by adding `rs1` to `rs2`, shifted by `shamt`. + Instruction encoded in R instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisls +assembly: " xs3, xs1, xs2, shamt" +base: 32 +encoding: + match: 1110-------------110-----0101011 + variables: + - name: shamt + location: 27-25 + - name: rs1 + location: 19-15 + - name: rs2 + location: 24-20 + not: 0 + - name: rs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg virtual_address = X[rs1] + (X[rs2] << shamt); + write_memory<16>(virtual_address, X[rs3][15:0], $encoding); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.srw.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.srw.yaml new file mode 100644 index 0000000000..1d60fac67b --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.srw.yaml @@ -0,0 +1,36 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.srw +long_name: Store indexed word +description: | + Store 32 bits of data from register `rs3` to an + address formed by adding `rs1` to `rs2`, shifted by `shamt`. + Instruction encoded in R instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisls +assembly: " xs3, xs1, xs2, shamt" +base: 32 +encoding: + match: 1111-------------110-----0101011 + variables: + - name: shamt + location: 27-25 + - name: rs1 + location: 19-15 + - name: rs2 + location: 24-20 + not: 0 + - name: rs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg virtual_address = X[rs1] + (X[rs2] << shamt); + write_memory<32>(virtual_address, X[rs3][31:0], $encoding); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.subsat.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.subsat.yaml new file mode 100644 index 0000000000..ed9ae5e22e --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.subsat.yaml @@ -0,0 +1,50 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.subsat +long_name: Saturating signed subtraction +description: | + Subtract signed values `rs1` and `rs2`, saturate the signed result, and write to `rd`. + Instruction encoded in R instruction format. +definedBy: + anyOf: + - Xqci + - Xqcia +base: 32 +encoding: + match: 0010000----------011-----0001011 + variables: + - name: rs1 + location: 19-15 + not: 0 + - name: rs2 + location: 24-20 + not: 0 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1, xs2" +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg result = X[rs1] - X[rs2]; + XReg most_negative_number = 1 << (xlen() - 1); + XReg most_positive_number = (1 << (xlen() - 1)) - 1; + + # overflow occurs if the operands have different signs and the result is a different sign than the first operand + if (X[rs1][xlen()-1] != X[rs2][xlen()-1]) { + if (result[xlen()-1] != X[rs1][xlen()-1]) { + if ($signed(X[rs1]) < 0) { + X[rd] = most_negative_number; + } else { + X[rd] = most_positive_number; + } + } + } + + # otherwise, overflow did not occur + X[rd] = result; diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.subusat.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.subusat.yaml new file mode 100644 index 0000000000..a3a51e7c89 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.subusat.yaml @@ -0,0 +1,34 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.subusat +long_name: Saturating unsigned subtraction +description: | + Subtract unsigned values `rs1` and `rs2`, saturate the unsigned result, and write to `rd`. + Instruction encoded in R instruction format. +definedBy: + anyOf: + - Xqci + - Xqcia +base: 32 +encoding: + match: 0010001----------011-----0001011 + variables: + - name: rs1 + location: 19-15 + not: 0 + - name: rs2 + location: 24-20 + not: 0 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1, xs2" +access: + s: always + u: always + vs: always + vu: always +operation(): | + X[rd] = (X[rs1] < X[rs2]) ? 0 : X[rs1] - X[rs2]; diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.swm.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.swm.yaml new file mode 100644 index 0000000000..ec1bf9430a --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.swm.yaml @@ -0,0 +1,42 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.swm +long_name: Store word multiple +description: | + Stores multiple words from the registers starting at `rs3` to the address starting at (`rs1` + `imm`). + The number of words is in `rs2`. + Instruction encoded in R instruction format. +definedBy: + anyOf: + - Xqci + - Xqcilsm +base: 32 +encoding: + match: 00---------------111-----0101011 + variables: + - name: imm + location: 29-25 + left_shift: 2 + - name: rs1 + location: 19-15 + - name: rs2 + location: 24-20 + not: 0 + - name: rs3 + location: 11-7 +assembly: " xs3, xs2, imm(xs1)" +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg vaddr = X[rs1] + imm; + XReg num_words = X[rs2]; + raise (ExceptionCode::IllegalInstruction, effective_ldst_mode(), $encoding) if ((rs3 + num_words) > 32); + for (U32 i = 0; i < num_words; i++) { + write_memory<32>(vaddr, X[rs3 + i], $encoding); + vaddr = vaddr + 4; + } diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.swmi.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.swmi.yaml new file mode 100644 index 0000000000..bdbaca6452 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.swmi.yaml @@ -0,0 +1,41 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.swmi +long_name: Store word multiple (immediate) +description: | + Stores multiple words from the registers starting at `rs3` to the address starting at (`rs1` + `imm`). + The number of words is in `length` immediate. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcilsm +base: 32 +encoding: + match: 00---------------111-----0101011 + variables: + - name: imm + location: 29-25 + left_shift: 2 + - name: rs1 + location: 19-15 + - name: length + location: 24-20 + not: 0 + - name: rs3 + location: 11-7 +assembly: " xs3, length, imm(xs1)" +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg vaddr = X[rs1] + imm; + raise (ExceptionCode::IllegalInstruction, effective_ldst_mode(), $encoding) if ((rs3 + length) > 32); + for (U32 i = 0; i < length; i++) { + write_memory<32>(vaddr, X[rs3 + i], $encoding); + vaddr = vaddr + 4; + } diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.wrap.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.wrap.yaml new file mode 100644 index 0000000000..e14f43f3cf --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.wrap.yaml @@ -0,0 +1,40 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.wrap +long_name: Wraparound (Register) +description: | + If `rs1` >= `rs2` perform subtraction between `rs1` and `rs2`. + If `rs1` < 0, perform addition between `rs1` and `rs2`, + else, select `rs1`. The result is stored in `rd`. + Instruction encoded in R instruction format. +definedBy: + anyOf: + - Xqci + - Xqcia +base: 32 +encoding: + match: 0010010----------011-----0001011 + variables: + - name: rs1 + location: 19-15 + - name: rs2 + location: 24-20 + not: 0 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1, xs2" +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg rs1_value = X[rs1]; + X[rd] = ($signed(rs1_value) >= $signed(X[rs2])) + ? rs1_value - X[rs2] + : (($signed(rs1_value) < 0) + ? (rs1_value + X[rs2]) + : rs1_value); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.wrapi.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.wrapi.yaml new file mode 100644 index 0000000000..e35eb20470 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.wrapi.yaml @@ -0,0 +1,40 @@ +# yaml-language-server: $schema=../../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.wrapi +long_name: Wraparound (Immediate) +description: | + If `rs1` >= `imm` perform subtraction between `rs1` and `imm`. + If `rs1` < 0, perform addition between `rs1` and `imm`, + else, select `rs1`. The result is stored in `rd`. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcia +base: 32 +encoding: + match: 0----------------000-----0001011 + variables: + - name: imm + location: 30-20 + - name: rs1 + location: 19-15 + not: 0 + - name: rd + location: 11-7 + not: 0 +assembly: " xd, xs1, imm" +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg rs1_value = X[rs1]; + X[rd] = ($signed(rs1_value) >= $signed(imm)) + ? rs1_value - imm + : (($signed(rs1_value) < 0) + ? (rs1_value + imm) + : rs1_value); diff --git a/cfgs/qc_iu/arch_overlay/isa/globals.isa b/cfgs/qc_iu/arch_overlay/isa/globals.isa new file mode 100644 index 0000000000..5d363ac0c4 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/isa/globals.isa @@ -0,0 +1,10 @@ +%version: 1.0 + +include "../../../../arch/isa/globals.isa" + +builtin function delay { + arguments XReg cycles + description { + Delay the processor by +cycles+ cycles. + } +} diff --git a/cfgs/qc_iu/cfg.yaml b/cfgs/qc_iu/cfg.yaml new file mode 100644 index 0000000000..3e26c94455 --- /dev/null +++ b/cfgs/qc_iu/cfg.yaml @@ -0,0 +1,13 @@ +# yaml-language-server: $schema=../../schemas/config_schema.json +--- +$schema: config_schema.json# +kind: architecture configuration +type: partially configured +name: qc_iu +description: Configuration with the Xqci custom extension. +mandatory_extensions: + - { name: Sm } + - { name: I } + - { name: Xqci, version: "~> 0.4" } +params: + XLEN: 32 diff --git a/cfgs/qc_iu/qc_theme.yml b/cfgs/qc_iu/qc_theme.yml new file mode 100644 index 0000000000..f1913727f8 --- /dev/null +++ b/cfgs/qc_iu/qc_theme.yml @@ -0,0 +1,330 @@ +extends: default +font: + catalog: + merge: true + sans-serif: GEM_FONTS_DIR/mplus1p-regular-fallback.ttf + #Petrona + body: + normal: QualcommNext-Regular.ttf + bold: QualcommNext-Medium.ttf + italic: QualcommNext-Italic.ttf + bold_italic: QualcommNext-MediumItalic.ttf + header_thin: QualcommNext-Thin.ttf + #Montserrat + headings: + normal: QualcommNext-Medium.ttf + italic: QualcommNext-Italic.ttf + bold: QualcommNext-Medium.ttf + light: QualcommNext-Thin.ttf + code: + normal: cmunbtl.ttf + bold: cmunbtl.ttf + italic: cmunbto.ttf + bold_italic: cmunbto.ttf + # M+ 1mn supports ASCII and the circled numbers used for conums + M+ 1mn: + normal: mplus-1mn-regular.ttf + bold: mplus-1mn-bold.ttf + italic: mplus-1mn-light.ttf + bold_italic: mplus-1mn-medium.ttf + M+ 1p Fallback: + normal: mplus-1p-regular-fallback.ttf + bold: mplus-1p-regular-fallback.ttf + italic: mplus-1p-regular-fallback.ttf + bold_italic: mplus-1p-regular-fallback.ttf + Droid Fallback: + normal: droid-sans-fallback.ttf + italic: droid-sans-fallback.ttf + bold: droid-sans-fallback.ttf + bold_italic: droid-sans-fallback.ttf + # M+ 1p supports Latin, Latin-1 Supplement, Latin Extended, Greek, Cyrillic, Vietnamese, Japanese & an assortment of symbols + # It also provides arrows for ->, <-, => and <= replacements in case these glyphs are missing from font + fallbacks: + - M+ 1p Fallback + - Droid Fallback + svg: + fallback-font-family: M+ 1mn +page: + background_color: ffffff + layout: portrait + margin: [0.5in, 0.67in, 0.67in, 0.67in] + # margin_inner and margin_outer keys are used for recto/verso print margins when media=prepress + margin_inner: 0.75in + margin_outer: 0.59in + size: A4 +base: + font-family: body + font_size: 11.5 + line_height_length: 12 + font_style: normal + font_size_large: round($base_font_size * 1.25) + font_size_small: round($base_font_size * 0.85) + font_size_min: $base_font_size * 0.75 + border_radius: 3 + border_width: 0.25 + border_color: EEEEEE +vertical_rhythm: $base_line_height_length +horizontal_rhythm: + $base_line_height_length + # QUESTION should vertical_spacing be block_spacing instead? +vertical_spacing: $vertical_rhythm +link: + font_color: 428bca + # codespan is currently used for inline monospaced in prose and table cells +codespan: + font-color: 000000 + # font_family: code + font_family: M+ 1mn + #font_family: Droid Fallback + font_style: normal +menu_caret_content: " \u203a " +heading: + align: left + margin_bottom: $block_margin_bottom + margin_top: $block_margin_bottom + min_height_after: 0.25in + font_color: 000000 + font_family: headings + font_style: bold + h1_font_size: floor($base_font_size * 2.8) + # h2 is used for chapter titles (book doctype only) + h2_font_size: 11.5 + h3_font_size: 11.5 + h4_font_size: 11.5 + h5_font_size: 11.5 + h6_font_size: $base_font_size_small +title_page: + align: center + logo: + top: 10% + title: + font_family: headings + font_style: light + font_size: floor($base_font_size * 2.8) + top: 55% + font_color: 3e058e + subtitle: + font_family: headings + font_style: light + font_size: floor($base_font_size * 1.2) + margin-top: 25 + authors: + font_family: headings + font_color: 3e058e + font_style: light + font_size: floor($base_font_size * .8) + revision: + margin_top: $base_font_size * 1.25 +block: + margin_top: 0 + margin_bottom: $vertical_rhythm +caption: + align: left + font_size: $base_font_size * 0.95 + font_style: italic + # FIXME perhaps set line_height instead of / in addition to margins? + margin_inside: $vertical_rhythm / 3 + #margin_inside: $vertical_rhythm / 4 + margin_outside: 0 +lead: + font_size: $base_font_size_large + line_height: 1.4 +abstract: + font_color: 5c6266 + font_size: $lead_font_size + line_height: $lead_line_height + font_style: italic + first_line_font_style: bold + title: + align: left + font_color: $heading_font_color + font_family: $heading_font_family + font_size: $heading_h4_font_size + font_style: $heading_font_style +sidebar: + font-style: italic + background-color: f5f5fc + border-color: 8d81b8 + border-radius: 3 + border-width: 0.2 +sidebar-title: + font_family: $heading_font_family + font-style: light + font-color: $heading-font-color + font-size: 11 + align: left +admonition: + font-style: italic + column_rule_color: $base_border_color + column_rule_width: $base_border_width + padding: [0, $horizontal_rhythm, 0, $horizontal_rhythm] + icon: + note: + # name: pencil-square-o + name: fas-info-circle + stroke_color: 6489b3 + tip: + # name: comments-o + name: far-comments + stroke_color: 646b74 + size: 24 + important: + # name: info + name: fas-info-circle + stroke_color: 5f8c8b + warning: + stroke_color: 9c4d4b + caution: + stroke_color: c99a2c + label: + text_transform: uppercase + font_style: bold +#blockquote: +# font_color: $base_font_color +# font_size: $base_font_size_large +# border_color: $base_border_color +# border_width: 2 +# FIXME disable negative padding bottom once margin collapsing is implemented +# padding: [0, $horizontal_rhythm, $block_margin_bottom * -0.75, $horizontal_rhythm + $blockquote_border_width / 2] +# cite_font_size: $base_font_size_small +# cite_font_color: 51278d +# code is used for source blocks (perhaps change to source or listing?) +code: + #font_color: $base_font_color + font-color: 000000 + font_family: $codespan_font_family + #font_size: ceil($base_font_size) + font-size: 11 + padding: $code_font_size + line_height: 1.15 + # line_gap is an experimental property to control how a background color is applied to an inline block element + line_gap: 3.8 + #background_color: f4f4fb + background_color: ffffff + #border_color: cccccc + #border_radius: $base_border_radius + #border_width: 0.2 + caption: + end: bottom +conum: + font_family: M+ 1mn + font_color: $codespan_font_color + font_size: $base_font_size + line_height: 4 / 3 +example: + border_color: $base_border_color + border_radius: $base_border_radius + border_width: 0.2 + background_color: ffffff + # FIXME reenable padding bottom once margin collapsing is implemented + padding: [$vertical_rhythm, $horizontal_rhythm, 0, $horizontal_rhythm] +image: + align: left + caption: + align: center +prose: + margin_top: $block_margin_top + margin_bottom: $block_margin_bottom +thematic_break: + border_color: $base_border_color + border_style: solid + border_width: $base_border_width + margin_top: $vertical_rhythm * 0.5 + margin_bottom: $vertical_rhythm * 1.5 +description_list: + term_font_style: bold + term_spacing: $vertical_rhythm / 4 + description_indent: $horizontal_rhythm * 1.25 +list: + indent: $horizontal_rhythm * 1.5 + #marker_font_color: 404040 + # NOTE outline_list_item_spacing applies to list items that do not have complex content + item_spacing: $vertical_rhythm / 2 +figure: + caption: + end: bottom + align: center +table: + background_color: $page_background_color + #head_background_color: #2596be + #head_font_color: $base_font_color + head_font_style: bold + #body_background_color: + body_stripe_background_color: d7d7d7 + foot_background_color: f0f0f0 + border_color: dddddd + border_width: $base_border_width + cell_padding: 3 + caption: + end: bottom + align: center + text-align: center + max-width: none +toc: + indent: $horizontal_rhythm + line_height: 1.4 + dot_leader: + #content: ". " + font_color: a9a9a9 + #levels: 2 3 +# NOTE in addition to footer, header is also supported +header: + font_size: $base_font_size_small + # NOTE if background_color is set, background and border will span width of page + border_color: dddddd + border_width: 0.35 + height: $base_line_height_length * 2.6 + line_height: 1 + padding: [$base_line_height_length / 1, 1, 0, 1] + vertical_align: margin_inside + #image_vertical_align: or + # additional attributes for content: + # * {page-count} + # * {page-number} + # * {document-title} + # * {document-subtitle} + # * {chapter-title} + # * {section-title} + # * {section-or-chapter-title} + recto: + right: + content: "{section-or-chapter-title} | Page {page-number}" + verso: + left: + content: "{section-or-chapter-title} | Page {page-number}" + # left: 'Page {page-number} | {section-or-chapter-title}' +footer: + font_size: $base_font_size_small + # NOTE if background_color is set, background and border will span width of page + border_color: dddddd + border_width: 0.35 + height: $base_line_height_length * 2.6 + line_height: 1 + padding: [$base_line_height_length / 1, 1, .5, 1] + vertical_align: top + #image_vertical_align: or + # additional attributes for content: + # content: '{company}' + # * {page-count} + # * {page-number} + #center: + #content: '{document-title}' + # * {document-subtitle} + # * {chapter-title} + # * {section-title} + # * {section-or-chapter-title} + recto: + #columns: "<50% =0% >50%" + right: + #content: '{page-number}' + # content: 'Confidential - © Qualcomm Technologies, Inc. and/or its affiliated companies. May contain trade secrets.' + #content: '{document-title} | © RISC-V' + content: "{document-title}" + #center: '{page-number}' + #content: '{revdate}' + verso: + #columns: $footer_recto_columns + left: + content: $footer_recto_right_content + #center: '{page-number}' + #content: '{page-number}' diff --git a/lib/arch_obj_models/extension.rb b/lib/arch_obj_models/extension.rb index 9d02b671a8..54d4d23faf 100644 --- a/lib/arch_obj_models/extension.rb +++ b/lib/arch_obj_models/extension.rb @@ -398,7 +398,7 @@ def requirement_condition if @data.key?("implies") rs = [r] + implications.map(&:requirement_condition) rs = rs.reject(&:empty?) - r = SchemaCondition.all_of(*rs.map(&:to_h)) unless rs.empty? + r = SchemaCondition.all_of(*rs.map(&:to_h), cfg_arch: @cfg_arch) unless rs.empty? end r end diff --git a/lib/idl/symbol_table.rb b/lib/idl/symbol_table.rb index 32aee4199f..5237ffe32f 100644 --- a/lib/idl/symbol_table.rb +++ b/lib/idl/symbol_table.rb @@ -91,6 +91,7 @@ def hash def initialize(cfg_arch) raise if cfg_arch.nil? + @cfg_arch = cfg_arch @mxlen = cfg_arch.unconfigured? ? nil : cfg_arch.mxlen @callstack = [nil] diff --git a/schemas/csr_schema.json b/schemas/csr_schema.json index 8110e61e1a..e32cb20dbc 100644 --- a/schemas/csr_schema.json +++ b/schemas/csr_schema.json @@ -189,7 +189,7 @@ }, "name": { "type": "string", - "pattern": "^[a-z][a-z0-9]+$", + "pattern": "^[a-z][a-z0-9_.]+$", "description": "CSR name" }, "base": { diff --git a/schemas/schema_defs.json b/schemas/schema_defs.json index b4d7a22ad1..a5ee77adc9 100644 --- a/schemas/schema_defs.json +++ b/schemas/schema_defs.json @@ -13,6 +13,10 @@ "type": "string", "pattern": "^(0|[1-9]\\d*)\\.(0|[1-9]\\d*)\\.(0|[1-9]\\d*)(?:-((?:0|[1-9]\\d*|\\d*[a-zA-Z-][0-9a-zA-Z-]*)(?:\\.(?:0|[1-9]\\d*|\\d*[a-zA-Z-][0-9a-zA-Z-]*))*))?(?:\\+([0-9a-zA-Z-]+(?:\\.[0-9a-zA-Z-]+)*))?$" }, + "rvi_version": { + "type": "string", + "pattern": "^[0-9]+(\\.[0-9]+(\\.[0-9]+(-pre)?)?)?$" + }, "field_location": { "oneOf": [ { "type": "number", "description": "Location of a single bit" }, @@ -128,7 +132,7 @@ "pattern": "^(([A-WY])|([SXZ][a-z0-9]+))$" }, "extension_version": { - "$ref": "#/$defs/semantic_version" + "$ref": "#/$defs/rvi_version" }, "requirement_string": { "type": "string",