diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_flags.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_flags.yaml index 0a06f9cfb4..7ee6a34ac2 100644 --- a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_flags.yaml +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_flags.yaml @@ -8,7 +8,10 @@ base: 32 length: 32 description: | Condition Code Register with condition codes, plus a co-processor flags (_e.g._, to support floating point) -definedBy: Xqci +definedBy: + anyOf: + - Xqci + - Xqciint fields: CPFLAGS: location: 31-16 diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie0.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie0.yaml index 67e1074a4e..04d4431e2c 100644 --- a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie0.yaml +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie0.yaml @@ -8,7 +8,10 @@ address: 0x7f0 length: 32 base: 32 priv_mode: M -definedBy: Xqci +definedBy: + anyOf: + - Xqci + - Xqciint description: | Enable bits for IRQs 0-31 fields: diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie1.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie1.yaml index 93310b5a3a..0282d05aba 100644 --- a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie1.yaml +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie1.yaml @@ -8,7 +8,10 @@ address: 0x7f1 length: 32 base: 32 priv_mode: M -definedBy: Xqci +definedBy: + anyOf: + - Xqci + - Xqciint description: | Enable bits for IRQs 32-63 fields: diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie2.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie2.yaml index d5b0f0420a..8d94f4f210 100644 --- a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie2.yaml +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie2.yaml @@ -8,7 +8,10 @@ address: 0x7f2 length: 32 base: 32 priv_mode: M -definedBy: Xqci +definedBy: + anyOf: + - Xqci + - Xqciint description: | Enable bits for IRQs 64-95 fields: diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie3.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie3.yaml index 809335febc..f98e158172 100644 --- a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie3.yaml +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie3.yaml @@ -8,7 +8,10 @@ address: 0x7f3 length: 32 base: 32 priv_mode: M -definedBy: Xqci +definedBy: + anyOf: + - Xqci + - Xqciint description: | Enable bits for IRQs 96-127 fields: diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie4.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie4.yaml index ad7b3e806a..21c6423240 100644 --- a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie4.yaml +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie4.yaml @@ -8,7 +8,10 @@ address: 0x7f4 length: 32 base: 32 priv_mode: M -definedBy: Xqci +definedBy: + anyOf: + - Xqci + - Xqciint description: | Enable bits for IRQs 128-159 fields: diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie5.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie5.yaml index 2c6aaee9f7..1bab8f05db 100644 --- a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie5.yaml +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie5.yaml @@ -8,7 +8,10 @@ address: 0x7f5 length: 32 base: 32 priv_mode: M -definedBy: Xqci +definedBy: + anyOf: + - Xqci + - Xqciint description: | Enable bits for IRQs 160-191 fields: diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie6.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie6.yaml index bffa251af9..7a25830b12 100644 --- a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie6.yaml +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie6.yaml @@ -8,7 +8,10 @@ address: 0x7f6 length: 32 base: 32 priv_mode: M -definedBy: Xqci +definedBy: + anyOf: + - Xqci + - Xqciint description: | Enable bits for IRQs 192-223 fields: diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie7.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie7.yaml index 9898db8b59..c8e816eb05 100644 --- a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie7.yaml +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie7.yaml @@ -8,7 +8,10 @@ address: 0x7f7 length: 32 base: 32 priv_mode: M -definedBy: Xqci +definedBy: + anyOf: + - Xqci + - Xqciint description: | Enable bits for IRQs 224-255 fields: diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip0.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip0.yaml index 6dc1fcecf1..a89cbd333a 100644 --- a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip0.yaml +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip0.yaml @@ -8,7 +8,10 @@ address: 0x7f0 length: 32 priv_mode: M base: 32 -definedBy: Xqci +definedBy: + anyOf: + - Xqci + - Xqciint description: | Pending bits for IRQs 0-31 fields: diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip1.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip1.yaml index a3fe935cc7..5f00b2e09d 100644 --- a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip1.yaml +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip1.yaml @@ -8,7 +8,10 @@ address: 0x7f1 length: 32 priv_mode: M base: 32 -definedBy: Xqci +definedBy: + anyOf: + - Xqci + - Xqciint description: | Pending bits for IRQs 32-63 fields: diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip2.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip2.yaml index f53932a7c5..01ec079504 100644 --- a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip2.yaml +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip2.yaml @@ -8,7 +8,10 @@ address: 0x7f2 length: 32 priv_mode: M base: 32 -definedBy: Xqci +definedBy: + anyOf: + - Xqci + - Xqciint description: | Pending bits for IRQs 64-95 fields: diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip3.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip3.yaml index 1726552ee6..70f8f0067c 100644 --- a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip3.yaml +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip3.yaml @@ -8,7 +8,10 @@ address: 0x7f3 length: 32 priv_mode: M base: 32 -definedBy: Xqci +definedBy: + anyOf: + - Xqci + - Xqciint description: | Pending bits for IRQs 96-127 fields: diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip4.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip4.yaml index 40eb770e5f..a8266fd36f 100644 --- a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip4.yaml +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip4.yaml @@ -8,7 +8,10 @@ address: 0x7f4 length: 32 priv_mode: M base: 32 -definedBy: Xqci +definedBy: + anyOf: + - Xqci + - Xqciint description: | Pending bits for IRQs 128-159 fields: diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip5.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip5.yaml index 8482078fb4..3985e0f402 100644 --- a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip5.yaml +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip5.yaml @@ -8,7 +8,10 @@ address: 0x7f5 length: 32 priv_mode: M base: 32 -definedBy: Xqci +definedBy: + anyOf: + - Xqci + - Xqciint description: | Pending bits for IRQs 160-191 fields: diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip6.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip6.yaml index a052056919..987bb95eb8 100644 --- a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip6.yaml +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip6.yaml @@ -8,7 +8,10 @@ address: 0x7f6 length: 32 priv_mode: M base: 32 -definedBy: Xqci +definedBy: + anyOf: + - Xqci + - Xqciint description: | Pending bits for IRQs 192-223 fields: diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip7.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip7.yaml index c9332a57c0..f50fc8131b 100644 --- a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip7.yaml +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip7.yaml @@ -8,7 +8,10 @@ address: 0x7f7 length: 32 priv_mode: M base: 32 -definedBy: Xqci +definedBy: + anyOf: + - Xqci + - Xqciint description: | Pending bits for IRQs 224-255 fields: diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mncause.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mncause.yaml new file mode 100644 index 0000000000..a92325d86e --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mncause.yaml @@ -0,0 +1,65 @@ +$schema: csr_schema.json# +kind: csr +name: qc_mncause +long_name: Machine NMI Cause +address: 0x7c2 +base: 32 +priv_mode: M +length: MXLEN +description: | + Reports the cause of the latest non-maskable interrupt. +definedBy: + anyOf: + - Xqci + - Xqciint +fields: + INT: + type: RW-H + reset_value: 0 + location: 31 + description: Interrupt bit copied from mcause.INT at the moment of NMI + NMI: + type: RW-H + reset_value: 0 + location: 30 + description: If 1'b1, currently processing NMI. + MPP: + type: RW-H + reset_value: 3 + location: 29-28 + description: M-mode Previous Privilege. + MPIE: + type: RW-H + reset_value: 0 + location: 27 + description: M-mode Previous Interrupt Enable. + MIE: + type: RW-H + reset_value: 0 + location: 26 + description: M-mode Interrupt Enable. + EXCP: + type: RW-H + reset_value: 0 + location: 25 + description: Exception Pending Bit. + RESP: + type: RW-H + reset_value: 0 + location: 24 + description: Resume Pending Bit. + MPIL: + type: RW-H + reset_value: 0 + location: 19-16 + description: M-mode Previous Interrupt Level. + MIL: + type: RW-H + reset_value: 15 + location: 15-12 + description: M-mode Interrupt Level. + NMICODE: + type: RW-H + reset_value: 0 + location: 11-0 + description: NMI code ID. diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqci.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqci.yaml index 8a3b94702f..5be2cfc144 100644 --- a/cfgs/qc_iu/arch_overlay/ext/Xqci.yaml +++ b/cfgs/qc_iu/arch_overlay/ext/Xqci.yaml @@ -92,6 +92,48 @@ versions: requires: name: Zca version: ">= 1.0.0" +- version: "0.5.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com + changes: + - Added Xqciio sub-extension + - Added Xqcisim sub-extension + - Added Xqcisync sub-extension + - Fix description of qc.shladd instruction + - Fix description and functionality of qc.c.extu instruction + - Fix description and functionality of qc.wrapi instruction + - Fix description of qc.swmi, qc.lwmi and qc.setwmi instructions + - Fix description of qc.mclici* CSRs to reflect being part of Xqciint custom extension + - Fix description of qc.setinti and qc.clrinti instructions + implies: + - [Xqcia, "0.3.0"] + - [Xqciac, "0.3.0"] + - [Xqcibi, "0.2.0"] + - [Xqcibm, "0.3.0"] + - [Xqcicli, "0.2.0"] + - [Xqcicm, "0.2.0"] + - [Xqcics, "0.2.0"] + - [Xqcicsr, "0.2.0"] + - [Xqciint, "0.3.0"] + - [Xqciio, "0.1.0"] + - [Xqcilb, "0.2.0"] + - [Xqcili, "0.2.0"] + - [Xqcilia, "0.2.0"] + - [Xqcilo, "0.2.0"] + - [Xqcilsm, "0.3.0"] + - [Xqcisim, "0.1.0"] + - [Xqcisls, "0.2.0"] + - [Xqcisync, "0.1.0"] + requires: + name: Zca + version: ">= 1.0.0" description: | The Xqci extension includes a set of instructions that improve RISC-V code density and performance in microontrollers. It fills several gaps: diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqcia.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqcia.yaml index 951e57af94..c098ca7ffa 100644 --- a/cfgs/qc_iu/arch_overlay/ext/Xqcia.yaml +++ b/cfgs/qc_iu/arch_overlay/ext/Xqcia.yaml @@ -28,6 +28,18 @@ versions: email: dhower@qti.qualcomm.com changes: - Add information about instruction formats of each instruction +- version: "0.3.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com + changes: + - Fix description and functionality of qc.wrapi instruction description: | The Xqcia extension includes eleven instructions to perform integer arithmetic. diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqciac.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqciac.yaml index deef748aae..f1c0791a16 100644 --- a/cfgs/qc_iu/arch_overlay/ext/Xqciac.yaml +++ b/cfgs/qc_iu/arch_overlay/ext/Xqciac.yaml @@ -30,6 +30,20 @@ versions: - Add information about instruction formats of each instruction - Fix description and functionality of qc.shladd instruction requires: { name: Zca, version: ">= 1.0.0" } +- version: "0.3.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com + changes: + - Fix description and functionality of qc.shladd instruction + - Renaming instructions qc.muladdi to qc.muliadd and qc.c.muladdi to qc.c.muliadd + requires: { name: Zca, version: ">= 1.0.0" } description: | The Xqciac extension includes three instructions to accelerate common address calculations. diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqcibm.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqcibm.yaml index 61ffca3b02..1f64d90b03 100644 --- a/cfgs/qc_iu/arch_overlay/ext/Xqcibm.yaml +++ b/cfgs/qc_iu/arch_overlay/ext/Xqcibm.yaml @@ -30,6 +30,19 @@ versions: - Add information about instruction formats of each instruction - Fix description and functionality of qc.c.extu instruction requires: { name: Zca, version: ">= 1.0.0" } +- version: "0.3.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com + changes: + - Fix description and functionality of qc.c.extu instruction + requires: { name: Zca, version: ">= 1.0.0" } description: | The Xqcibm extension includes thirty eight instructions that perform bit manipulation, include insertion and extraction. diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqciint.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqciint.yaml index aa00848cb8..89617e7202 100644 --- a/cfgs/qc_iu/arch_overlay/ext/Xqciint.yaml +++ b/cfgs/qc_iu/arch_overlay/ext/Xqciint.yaml @@ -29,6 +29,20 @@ versions: changes: - Add information about instruction formats of each instruction requires: { name: Zca, version: ">= 1.0.0" } +- version: "0.3.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com + changes: + - Fix description of qc.mclici* CSRs to reflect being part of Xqciint custom extension + - Fix description of qc.setinti and qc.clrinti instructions + requires: { name: Zca, version: ">= 1.0.0" } description: | The Xqciint extension includes eleven instructions to accelerate interrupt servicing by performing common actions during ISR prologue/epilogue. diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqciio.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqciio.yaml new file mode 100644 index 0000000000..7546a1e02c --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/ext/Xqciio.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../../schemas/ext_schema.json + +$schema: ext_schema.json# +kind: extension +name: Xqciio +type: privileged +long_name: Qualcomm Input/Output device support +versions: +- version: "0.1.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com +description: | + The Xqciio extension includes two instructions to access external non-memory-mapped devices for input and output + +doc_license: + name: Creative Commons Attribution 4.0 International License + url: https://creativecommons.org/licenses/by/4.0/ +company: + name: Qualcomm Technologies, Inc. + url: https://qualcomm.com diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqcilsm.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqcilsm.yaml index dd853b48c4..9a97f0ed6e 100644 --- a/cfgs/qc_iu/arch_overlay/ext/Xqcilsm.yaml +++ b/cfgs/qc_iu/arch_overlay/ext/Xqcilsm.yaml @@ -28,6 +28,18 @@ versions: email: dhower@qti.qualcomm.com changes: - Add information about instruction formats of each instruction +- version: "0.3.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com + changes: + - Fix description of qc.swmi, qc.lwmi and qc.setwmi instructions description: | The Xqcilsm extension includes six instructions that transfer multiple values between registers and memory. diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqcisim.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqcisim.yaml new file mode 100644 index 0000000000..da15d48925 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/ext/Xqcisim.yaml @@ -0,0 +1,28 @@ +# yaml-language-server: $schema=../../../../schemas/ext_schema.json + +$schema: ext_schema.json# +kind: extension +name: Xqcisim +type: unprivileged +long_name: Qualcomm simulator support hints +versions: +- version: "0.1.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com +description: | + The Xqcisim extension includes ten hint instructions to interface simulation environment. + On real target any instruction from this extension executed as "no-operation" and have no effect. + +doc_license: + name: Creative Commons Attribution 4.0 International License + url: https://creativecommons.org/licenses/by/4.0/ +company: + name: Qualcomm Technologies, Inc. + url: https://qualcomm.com diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqcisync.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqcisync.yaml new file mode 100644 index 0000000000..832dbbc004 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/ext/Xqcisync.yaml @@ -0,0 +1,28 @@ +# yaml-language-server: $schema=../../../../schemas/ext_schema.json + +$schema: ext_schema.json# +kind: extension +name: Xqcisync +type: unprivileged +long_name: Qualcomm non-memory-mapped devices synchronization and delay +versions: +- version: "0.1.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com +description: | + The Xqcisync extension includes nine instructions, eight for non-memory-mapped devices synchronization and delay instruction. + Synchronization instructions are kind of IO fences that work with special devices synchronization signals. + +doc_license: + name: Creative Commons Attribution 4.0 International License + url: https://creativecommons.org/licenses/by/4.0/ +company: + name: Qualcomm Technologies, Inc. + url: https://qualcomm.com diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.delay.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.delay.yaml new file mode 100644 index 0000000000..32d2a8479a --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.delay.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.c.delay +long_name: Delay execution for immediate amount of cycles +description: | + Delay execution for amount of cycles provided as immediate argument + Instruction encoded in CI instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisync +assembly: "" +base: 32 +encoding: + match: "000000000-----10" + variables: + - name: imm + location: 6-2 +access: + s: always + u: always + vs: always + vu: always +operation(): | + delay(imm); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mnret.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mnret.yaml index 4116c16a06..7c60949b84 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mnret.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mnret.yaml @@ -8,7 +8,10 @@ description: | Returns from an NMI in M-mode. Instruction encoded in CI instruction format. assembly: "" -definedBy: Xqciint +definedBy: + anyOf: + - Xqci + - Xqciint access: s: never u: never @@ -18,15 +21,18 @@ base: 32 encoding: match: "0001100110010010" operation(): | - CSR[mncause].MIE = CSR[mncause].MPIE; - CSR[mncause].MPIE = 1; - if (CSR[mncause].MPP == 2'b00) { + if (implemented?(ExtensionName::S) && CSR[mstatus].MPP != 2'b11) { + CSR[mstatus].MPRV = 0; + } + CSR[mstatus].MIE = CSR[mstatus].MPIE; + CSR[mstatus].MPIE = 1; + if (CSR[mstatus].MPP == 2'b00) { set_mode(PrivilegeMode::U); - } else if (CSR[mncause].MPP == 2'b01) { + } else if (CSR[mstatus].MPP == 2'b01) { set_mode(PrivilegeMode::S); - } else if (CSR[mncause].MPP == 2'b11) { + } else if (CSR[mstatus].MPP == 2'b11) { set_mode(PrivilegeMode::M); } - CSR[mncause].MPP = implemented?(ExtensionName::U) ? 2'b00 : 2'b11; + CSR[mstatus].MPP = implemented?(ExtensionName::U) ? 2'b00 : 2'b11; CSR[mcause].NMI = 0; $pc = CSR[qc_mnepc].sw_read(); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mret.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mret.yaml index 0e07908d6e..f6221f4b48 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mret.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mret.yaml @@ -8,7 +8,10 @@ description: | Returns from an exception in M-mode. Instruction encoded in CI instruction format. assembly: "" -definedBy: Xqciint +definedBy: + anyOf: + - Xqci + - Xqciint access: s: never u: never diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.muladdi.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.muliadd.yaml similarity index 97% rename from cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.muladdi.yaml rename to cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.muliadd.yaml index 32b847c805..da1af4692a 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.muladdi.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.muliadd.yaml @@ -2,7 +2,7 @@ $schema: inst_schema.json# kind: instruction -name: qc.c.muladdi +name: qc.c.muliadd long_name: Multiply and accumulate (Immediate) description: | Increments `rd` by the multiplication of `rs1` and an unsigned immediate diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.ptrace.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.ptrace.yaml new file mode 100644 index 0000000000..58363c5180 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.ptrace.yaml @@ -0,0 +1,28 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.c.ptrace +long_name: Tracing pseudo-instruction (hint) working only in simulation environment +description: | + The tracing instruction have no explicit arguments. + Implicit arguments defined by simulation environment implementation. + Instruction is used to signal simulator to collect some tracing information. + Instruction encoded in CI instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisim +assembly: "" +base: 32 +encoding: + match: "0000000000000010" +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg func = 9; + XReg arg = 0; + iss_syscall(func,arg); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.sync.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.sync.yaml new file mode 100644 index 0000000000..69bc4fd8b9 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.sync.yaml @@ -0,0 +1,43 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.c.sync +long_name: Non-memory-mapped device read-after-write synchronization to completion +description: | + This synchronization instruction delays execution till last read (input) + from non-memory-mapped device transactions are completed for specified devices. + As well, instruction implies fence.tso functionality for all memory accesses. + Immediate argument is 3-bit encoding of 5-bit bitmask field + that specifies up to five pre-defined devices. + Values of bitmask encoding supported: 0,1,2,4,8,16,15,31 + Instruction encoded in CB instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisync +assembly: " slist" +base: 32 +encoding: + match: "100000---0000001" + variables: + - name: slist + location: 9-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + Bits<5> bitmask; + if (slist == 0) { + bitmask = 0; + } else if (slist < 6) { + XReg shift = slist - 1; + bitmask = (1 << shift); + } else { + XReg shift = slist - 2; + bitmask = (1 << shift) - 1; + } + fence_tso(); + sync_read_after_write_device(true,bitmask); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.syncr.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.syncr.yaml new file mode 100644 index 0000000000..1a50be78bb --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.syncr.yaml @@ -0,0 +1,43 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.c.syncr +long_name: Non-memory-mapped device read-after-write synchronization +description: | + This synchronization instruction delays execution till last read (input) + from non-memory-mapped device transactions are started for specified devices. + As well, instruction implies fence.tso functionality for all memory accesses. + Immediate argument is 3-bit encoding of 5-bit bitmask field + that specifies up to five pre-defined devices. + Values of bitmask encoding supported: 0,1,2,4,8,16,15,31 + Instruction encoded in CB instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisync +assembly: " slist" +base: 32 +encoding: + match: "100001---0000001" + variables: + - name: slist + location: 9-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + Bits<5> bitmask; + if (slist == 0) { + bitmask = 0; + } else if (slist < 6) { + XReg shift = slist - 1; + bitmask = (1 << shift); + } else { + XReg shift = slist - 2; + bitmask = (1 << shift) - 1; + } + fence_tso(); + sync_read_after_write_device(false,bitmask); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.syncwf.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.syncwf.yaml new file mode 100644 index 0000000000..b6da8a8b2c --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.syncwf.yaml @@ -0,0 +1,43 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.c.syncwf +long_name: Non-memory-mapped device write-after-read synchronization +description: | + This synchronization instruction delays execution till last write (output) + to non-memory-mapped device transactions are started for specified devices. + As well, instruction implies fence.tso functionality for all memory accesses. + Immediate argument is 3-bit encoding of 5-bit bitmask field + that specifies up to five pre-defined devices. + Values of bitmask encoding supported: 0,1,2,4,8,16,15,31 + Instruction encoded in CB instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisync +assembly: " slist" +base: 32 +encoding: + match: "100100---0000001" + variables: + - name: slist + location: 9-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + Bits<5> bitmask; + if (slist == 0) { + bitmask = 0; + } else if (slist < 6) { + XReg shift = slist - 1; + bitmask = (1 << shift); + } else { + XReg shift = slist - 2; + bitmask = (1 << shift) - 1; + } + fence_tso(); + sync_write_after_read_device(false,bitmask); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.syncwl.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.syncwl.yaml new file mode 100644 index 0000000000..4462e593b1 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.syncwl.yaml @@ -0,0 +1,43 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.c.syncwl +long_name: Non-memory-mapped device write-after-read synchronization to completion +description: | + This synchronization instruction delays execution till last write (output) + to non-memory-mapped device transactions are completed for specified devices. + As well, instruction implies fence.tso functionality for all memory accesses. + Immediate argument is 3-bit encoding of 5-bit bitmask field + that specifies up to five pre-defined devices. + Values of bitmask encoding supported: 0,1,2,4,8,16,15,31 + Instruction encoded in CB instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisync +assembly: " slist" +base: 32 +encoding: + match: "100101---0000001" + variables: + - name: slist + location: 9-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + Bits<5> bitmask; + if (slist == 0) { + bitmask = 0; + } else if (slist < 6) { + XReg shift = slist - 1; + bitmask = (1 << shift); + } else { + XReg shift = slist - 2; + bitmask = (1 << shift) - 1; + } + fence_tso(); + sync_write_after_read_device(true,bitmask); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.clrinti.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.clrinti.yaml index e70fcc8cf9..96238d5217 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.clrinti.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.clrinti.yaml @@ -6,7 +6,7 @@ name: qc.clrinti long_name: Clear interrupt (Immediate) description: | Clear interrupt, interrupt number is in `imm` (0 - 1023). - Instruction encoded in I instruction format. + Instruction encoded in R instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.inw.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.inw.yaml new file mode 100644 index 0000000000..f782005207 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.inw.yaml @@ -0,0 +1,35 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.inw +long_name: Input word from non-memory-mapped device +description: | + Input 32 bits of data into register `rd` from a non-memory-mapped device. + Such devices have own address space, unrelated to memory map. + Device space address formed by adding `rs1` to to a unsigned offset `imm`. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqciio +assembly: xd, imm(xs1) +base: 32 +encoding: + match: -----------------101-----0001011 + variables: + - name: imm + location: 31-20 + left_shift: 2 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg device_address = X[rs1] + imm; + X[rd] = read_device<32>(device_address); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lwmi.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lwmi.yaml index 2fbc7ef37d..efb6d76a48 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lwmi.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lwmi.yaml @@ -7,7 +7,7 @@ long_name: Load word multiple (Immediate) description: | Loads multiple words starting from address (`rs1` + `imm`) to registers, starting from `rd`. The number of words is in the `length` immediate. - Instruction encoded in I instruction format. + Instruction encoded in R instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.muladdi.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.muliadd.yaml similarity index 97% rename from cfgs/qc_iu/arch_overlay/inst/Xqci/qc.muladdi.yaml rename to cfgs/qc_iu/arch_overlay/inst/Xqci/qc.muliadd.yaml index 4c92acdf23..3815398b77 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.muladdi.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.muliadd.yaml @@ -2,7 +2,7 @@ $schema: inst_schema.json# kind: instruction -name: qc.muladdi +name: qc.muliadd long_name: Multiply and accumulate (Immediate) description: | Increments `rd` by the multiplication of `rs1` and a signed immediate `imm`. diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.norm.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.norm.yaml index 8fe5c096ce..8d25c140eb 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.norm.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.norm.yaml @@ -33,6 +33,6 @@ access: operation(): | XReg clz = (xlen() - 1) - $signed(highest_set_bit(X[rs1])); XReg clo = (xlen() - 1) - $signed(highest_set_bit(~X[rs1])); - XReg exp = (X[rs1][31] == 1) ? (X[rs1] << (clo - 1)) : (X[rs1] << (clz - 1)); - XReg mnt = (X[rs1][31] == 1) ? (-(clo - 1)) : (-(clz - 1)); + XReg mnt = (X[rs1][31] == 1) ? (X[rs1] << (clo - 1)) : (X[rs1] << (clz - 1)); + XReg exp = (X[rs1][31] == 1) ? (-(clo - 1)) : (-(clz - 1)); X[rd] = {mnt[23:0],exp[7:0]}; diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.normeu.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.normeu.yaml index ed1192add6..aed59d633a 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.normeu.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.normeu.yaml @@ -32,6 +32,6 @@ access: vu: always operation(): | XReg clz = ((xlen() - 1) - $signed(highest_set_bit(X[rs1]))) & ~1; - XReg exp = (X[rs1] << clz); - XReg mnt = (-clz); + XReg mnt = (X[rs1] << (clz & ~1)); + XReg exp = ((-clz) & ~1); X[rd] = {mnt[23:0],exp[7:0]}; diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.normu.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.normu.yaml index ff9b5b5690..18e5ef70c9 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.normu.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.normu.yaml @@ -32,6 +32,6 @@ access: vu: always operation(): | XReg clz = (xlen() - 1) - $signed(highest_set_bit(X[rs1])); - XReg exp = (X[rs1] << clz); - XReg mnt = (-clz); + XReg mnt = (X[rs1] << clz); + XReg exp = (-clz); X[rd] = {mnt[23:0],exp[7:0]}; diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.outw.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.outw.yaml new file mode 100644 index 0000000000..aab60cca76 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.outw.yaml @@ -0,0 +1,35 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.outw +long_name: Output word to non-memory-mapped device +description: | + Output 32 bits of data from register `rs2` to a non-memory-mapped device. + Such devices have own address space, unrelated to memory map. + Device space address formed by adding `rs1` to to a unsigned offset `imm`. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqciio +assembly: xs2, imm(xs1) +base: 32 +encoding: + match: -----------------100-----0001011 + variables: + - name: imm + location: 31-20 + left_shift: 2 + - name: rs1 + location: 19-15 + - name: rs2 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg device_address = X[rs1] + imm; + write_device<32>(device_address, X[rs2]); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.pcoredump.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.pcoredump.yaml new file mode 100644 index 0000000000..32235017e0 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.pcoredump.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.pcoredump +long_name: Print core dump pseudo-instruction (hint) working only in simulation environment +description: | + The print core dump instruction calls simulation environment with no explicit arguments. + Implicit arguments are all general purpose registers and CSRs. + Simulation environment expected to print the core dump on its console or standard output. + The core dump format and content are defined by simulation environment. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisim +assembly: "" +base: 32 +encoding: + match: "01100000000000000010000000010011" +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg func = 8; + XReg arg = 0; + iss_syscall(func,arg); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.pexit.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.pexit.yaml new file mode 100644 index 0000000000..ab737086b9 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.pexit.yaml @@ -0,0 +1,30 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.pexit +long_name: Exit call with register argument pseudo-instruction (hint) working only in simulation environment +description: | + The Exit call instruction calls simulation environment with unsigned `rs1` explicit argument. + Simulation environment is expected to complete its execution and return to the system with exit code provided in `rs1`. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisim +assembly: " xs1" +base: 32 +encoding: + match: 101100000000-----010000000010011 + variables: + - name: rs1 + location: 19-15 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg func = 12; + XReg arg = X[rs1]; + iss_syscall(func,arg); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.ppreg.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.ppreg.yaml new file mode 100644 index 0000000000..e34c63720d --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.ppreg.yaml @@ -0,0 +1,30 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.ppreg +long_name: Print register pseudo-instruction (hint) working only in simulation environment +description: | + The print register instruction calls simulation environment with `rs1` explicit argument. + Simulation environment expected to print the register value on its console or standard output. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisim +assembly: " xs1" +base: 32 +encoding: + match: 100000000000-----010000000010011 + variables: + - name: rs1 + location: 19-15 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg func = 2; + XReg arg = X[rs1]; + iss_syscall(func,arg); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.ppregs.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.ppregs.yaml new file mode 100644 index 0000000000..c6cc98f6f4 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.ppregs.yaml @@ -0,0 +1,28 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.ppregs +long_name: Print all registers pseudo-instruction (hint) working only in simulation environment +description: | + The print registers instruction calls simulation environment with no explicit arguments. + Implicit arguments are all general purpose registers. + Simulation environment expected to print the all registers value on its console or standard output. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisim +assembly: "" +base: 32 +encoding: + match: "01110000000000000010000000010011" +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg func = 3; + XReg arg = 0; + iss_syscall(func,arg); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.pputc.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.pputc.yaml new file mode 100644 index 0000000000..1fe99fb415 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.pputc.yaml @@ -0,0 +1,30 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.pputc +long_name: Print character passed in register argument pseudo-instruction (hint) working only in simulation environment +description: | + The print character instruction calls simulation environment with `rs1` explicit argument. + Simulation environment expected to print the character on its console or standard output. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisim +assembly: " xs1" +base: 32 +encoding: + match: 100100000000-----010000000010011 + variables: + - name: rs1 + location: 19-15 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg func = 4; + XReg arg = X[rs1]; + iss_syscall(func,arg); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.pputci.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.pputci.yaml new file mode 100644 index 0000000000..3dc97c52d3 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.pputci.yaml @@ -0,0 +1,30 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.pputci +long_name: Print character passed in the immediate argument pseudo-instruction (hint) working only in simulation environment +description: | + The print character instruction calls simulation environment with unsigned `imm` explicit argument. + Simulation environment expected to print the 8-bit character on its console or standard output. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisim +assembly: " imm" +base: 32 +encoding: + match: 0100--------00000010000000010011 + variables: + - name: imm + location: 29-20 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg func = 5; + XReg arg = imm; + iss_syscall(func,arg); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.pputs.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.pputs.yaml new file mode 100644 index 0000000000..9cba2dbd37 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.pputs.yaml @@ -0,0 +1,31 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.pputs +long_name: Print string pseudo-instruction (hint) working only in simulation environment +description: | + The print string instruction calls simulation environment with `rs1` explicit argument. + The argument assumed to be pointer to the string in target simulated memory. + Simulation environment expected to print the string on its console or standard output. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisim +assembly: " xs1" +base: 32 +encoding: + match: 101000000000-----010000000010011 + variables: + - name: rs1 + location: 19-15 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg func = 6; + XReg arg = X[rs1]; + iss_syscall(func,arg); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.psyscall.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.psyscall.yaml new file mode 100644 index 0000000000..ce78769508 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.psyscall.yaml @@ -0,0 +1,31 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.psyscall +long_name: System call with register argument pseudo-instruction (hint) working only in simulation environment +description: | + The System call instruction calls simulation environment with unsigned `rs1` explicit argument. + Additional implicit arguments defined by simulation environment implementation. + Instruction is used to call simulator to execute function according to the argument. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisim +assembly: " xs1" +base: 32 +encoding: + match: 110000000000-----010000000010011 + variables: + - name: rs1 + location: 19-15 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg func = 10; + XReg arg = X[rs1]; + iss_syscall(func,arg); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.psyscalli.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.psyscalli.yaml new file mode 100644 index 0000000000..2ad8ba4453 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.psyscalli.yaml @@ -0,0 +1,31 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.psyscalli +long_name: System call with immediate argument pseudo-instruction (hint) working only in simulation environment +description: | + The System call instruction calls simulation environment with unsigned `imm` explicit argument. + Additional implicit arguments defined by simulation environment implementation. + Instruction is used to call simulator to execute function according to the argument. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisim +assembly: " imm" +base: 32 +encoding: + match: 00----------00000010000000010011 + variables: + - name: imm + location: 29-20 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg func = 11; + XReg arg = imm; + iss_syscall(func,arg); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.setinti.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.setinti.yaml index a620f66043..241f4ddbc1 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.setinti.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.setinti.yaml @@ -6,7 +6,7 @@ name: qc.setinti long_name: Set interrupt (Immediate) description: | Set interrupt, interrupt number is in `imm` (0 - 1023). - Instruction encoded in I instruction format. + Instruction encoded in R instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.setwmi.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.setwmi.yaml index 750c3fd251..37afc0393e 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.setwmi.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.setwmi.yaml @@ -7,7 +7,7 @@ long_name: Set word multiple (Immediate) description: | Stores the value of `rs3` multiple times into the address starting at (`rs1` + `imm`). The number of writes is in length. - Instruction encoded in I instruction format. + Instruction encoded in R instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.shladd.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.shladd.yaml index 026f521f44..0b54322c27 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.shladd.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.shladd.yaml @@ -28,7 +28,7 @@ encoding: - name: rd location: 11-7 not: 0 -assembly: " xs1, xs2, shamt" +assembly: " xd, xs1, xs2, shamt" access: s: always u: always diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.swmi.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.swmi.yaml index bdbaca6452..b7dbc428cd 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.swmi.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.swmi.yaml @@ -7,7 +7,7 @@ long_name: Store word multiple (immediate) description: | Stores multiple words from the registers starting at `rs3` to the address starting at (`rs1` + `imm`). The number of words is in `length` immediate. - Instruction encoded in I instruction format. + Instruction encoded in R instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.sync.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.sync.yaml new file mode 100644 index 0000000000..b1b4723c61 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.sync.yaml @@ -0,0 +1,31 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.sync +long_name: Non-memory-mapped device read-after-write synchronization to completion +description: | + This synchronization instruction delays execution till last read (input) + from non-memory-mapped device transactions are completed for specified devices. + As well, instruction implies fence.tso functionality for all memory accesses. + Immediate argument is 5-bit bitmask field that specifies up to five pre-defined devices. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisync +assembly: " imm" +base: 32 +encoding: + match: 0001000-----00000011000000010011 + variables: + - name: imm + location: 24-20 +access: + s: always + u: always + vs: always + vu: always +operation(): | + fence_tso(); + sync_read_after_write_device(true,imm); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.syncr.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.syncr.yaml new file mode 100644 index 0000000000..e94dc14675 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.syncr.yaml @@ -0,0 +1,31 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.syncr +long_name: Non-memory-mapped device read-after-write synchronization +description: | + This synchronization instruction delays execution till last read (input) + from non-memory-mapped device transactions are started for specified devices. + As well, instruction implies fence.tso functionality for all memory accesses. + Immediate argument is 5-bit bitmask field that specifies up to five pre-defined devices. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisync +assembly: " imm" +base: 32 +encoding: + match: 0010000-----00000011000000010011 + variables: + - name: imm + location: 24-20 +access: + s: always + u: always + vs: always + vu: always +operation(): | + fence_tso(); + sync_read_after_write_device(false,imm); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.syncwf.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.syncwf.yaml new file mode 100644 index 0000000000..fc51bd96c6 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.syncwf.yaml @@ -0,0 +1,31 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.syncwf +long_name: Non-memory-mapped device write-after-read synchronization +description: | + This synchronization instruction delays execution till last write (output) + to non-memory-mapped device transactions are started for specified devices. + As well, instruction implies fence.tso functionality for all memory accesses. + Immediate argument is 5-bit bitmask field that specifies up to five pre-defined devices. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisync +assembly: " imm" +base: 32 +encoding: + match: 0100000-----00000011000000010011 + variables: + - name: imm + location: 24-20 +access: + s: always + u: always + vs: always + vu: always +operation(): | + fence_tso(); + sync_write_after_read_device(false,imm); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.syncwl.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.syncwl.yaml new file mode 100644 index 0000000000..b9c486b7e1 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.syncwl.yaml @@ -0,0 +1,31 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.syncwl +long_name: Non-memory-mapped device write-after-read synchronization to completion +description: | + This synchronization instruction delays execution till last write (output) + to non-memory-mapped device transactions are completed for specified devices. + As well, instruction implies fence.tso functionality for all memory accesses. + Immediate argument is 5-bit bitmask field that specifies up to five pre-defined devices. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisync +assembly: " imm" +base: 32 +encoding: + match: 1000000-----00000011000000010011 + variables: + - name: imm + location: 24-20 +access: + s: always + u: always + vs: always + vu: always +operation(): | + fence_tso(); + sync_write_after_read_device(true,imm); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.wrapi.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.wrapi.yaml index e35eb20470..8d4949afce 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.wrapi.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.wrapi.yaml @@ -3,12 +3,13 @@ $schema: inst_schema.json# kind: instruction name: qc.wrapi -long_name: Wraparound (Immediate) +long_name: Wraparound (Unsigned Immediate) description: | If `rs1` >= `imm` perform subtraction between `rs1` and `imm`. If `rs1` < 0, perform addition between `rs1` and `imm`, else, select `rs1`. The result is stored in `rd`. Instruction encoded in I instruction format. + The `imm` is an unsigned immediate. definedBy: anyOf: - Xqci @@ -33,8 +34,8 @@ access: vu: always operation(): | XReg rs1_value = X[rs1]; - X[rd] = ($signed(rs1_value) >= $signed(imm)) + X[rd] = ($signed(rs1_value) >= imm) ? rs1_value - imm : (($signed(rs1_value) < 0) - ? (rs1_value + imm) + ? ($signed(rs1_value) + imm) : rs1_value); diff --git a/cfgs/qc_iu/arch_overlay/isa/globals.isa b/cfgs/qc_iu/arch_overlay/isa/globals.isa index 5d363ac0c4..6566048105 100644 --- a/cfgs/qc_iu/arch_overlay/isa/globals.isa +++ b/cfgs/qc_iu/arch_overlay/isa/globals.isa @@ -8,3 +8,51 @@ builtin function delay { Delay the processor by +cycles+ cycles. } } + +builtin function iss_syscall { + arguments XReg id, XReg arg + description { + Instruction set simulator system call. + } +} + +builtin function read_device { + template U32 len + returns Bits + arguments XReg dev_addr + description { + Read from non-memory-mapped device. + Such devices have own addresses not related to memory map. + } +} + +builtin function write_device { + template U32 len + arguments XReg dev_addr, Bits value + description { + Write to non-memory-mapped device. + Such devices have own addresses not related to memory map. + } +} + +builtin function sync_read_after_write_device { + arguments Boolean completed, Bits<5> device_bitmask + description { + Synchronize non-memory-mapped device read-after-write. + Such devices have own addresses not related to memory map. + Devices specified by device bitmask (up to 5 devices). + Stalls processor till condtions met. + Conditions are that last device output started or completed (depends on argument). + } +} + +builtin function sync_write_after_read_device { + arguments Boolean completed, Bits<5> device_bitmask + description { + Synchronize non-memory-mapped device write-after-read. + Such devices have own addresses not related to memory map. + Devices specified by device bitmask (up to 5 devices). + Stalls processor till condtions met. + Conditions are that last device input started or completed (depends on argument). + } +} diff --git a/cfgs/qc_iu/cfg.yaml b/cfgs/qc_iu/cfg.yaml index 3e26c94455..a28bdd53a7 100644 --- a/cfgs/qc_iu/cfg.yaml +++ b/cfgs/qc_iu/cfg.yaml @@ -8,6 +8,6 @@ description: Configuration with the Xqci custom extension. mandatory_extensions: - { name: Sm } - { name: I } - - { name: Xqci, version: "~> 0.4" } + - { name: Xqci, version: "~> 0.5" } params: XLEN: 32