From 1c85e3db490b920a3120f4c68c1cfa7041f7c211 Mon Sep 17 00:00:00 2001 From: Albert Yosher Date: Mon, 30 Dec 2024 17:48:17 +0200 Subject: [PATCH 01/11] Add fixes for reported issues, update version to 0.5.0 Signed-off-by: Albert Yosher --- .../qc_iu/arch_overlay/csr/Xqci/qc_flags.yaml | 5 ++- .../arch_overlay/csr/Xqci/qc_mclicie0.yaml | 5 ++- .../arch_overlay/csr/Xqci/qc_mclicie1.yaml | 5 ++- .../arch_overlay/csr/Xqci/qc_mclicie2.yaml | 5 ++- .../arch_overlay/csr/Xqci/qc_mclicie3.yaml | 5 ++- .../arch_overlay/csr/Xqci/qc_mclicie4.yaml | 5 ++- .../arch_overlay/csr/Xqci/qc_mclicie5.yaml | 5 ++- .../arch_overlay/csr/Xqci/qc_mclicie6.yaml | 5 ++- .../arch_overlay/csr/Xqci/qc_mclicie7.yaml | 5 ++- .../arch_overlay/csr/Xqci/qc_mclicip0.yaml | 5 ++- .../arch_overlay/csr/Xqci/qc_mclicip1.yaml | 5 ++- .../arch_overlay/csr/Xqci/qc_mclicip2.yaml | 5 ++- .../arch_overlay/csr/Xqci/qc_mclicip3.yaml | 5 ++- .../arch_overlay/csr/Xqci/qc_mclicip4.yaml | 5 ++- .../arch_overlay/csr/Xqci/qc_mclicip5.yaml | 5 ++- .../arch_overlay/csr/Xqci/qc_mclicip6.yaml | 5 ++- .../arch_overlay/csr/Xqci/qc_mclicip7.yaml | 5 ++- cfgs/qc_iu/arch_overlay/ext/Xqci.yaml | 36 +++++++++++++++++++ cfgs/qc_iu/arch_overlay/ext/Xqcia.yaml | 12 +++++++ cfgs/qc_iu/arch_overlay/ext/Xqciac.yaml | 13 +++++++ cfgs/qc_iu/arch_overlay/ext/Xqcibm.yaml | 13 +++++++ cfgs/qc_iu/arch_overlay/ext/Xqciint.yaml | 14 ++++++++ cfgs/qc_iu/arch_overlay/ext/Xqcilsm.yaml | 12 +++++++ .../arch_overlay/inst/Xqci/qc.clrinti.yaml | 2 +- .../qc_iu/arch_overlay/inst/Xqci/qc.lwmi.yaml | 2 +- .../qc_iu/arch_overlay/inst/Xqci/qc.norm.yaml | 4 +-- .../arch_overlay/inst/Xqci/qc.normeu.yaml | 4 +-- .../arch_overlay/inst/Xqci/qc.normu.yaml | 4 +-- .../arch_overlay/inst/Xqci/qc.setinti.yaml | 2 +- .../arch_overlay/inst/Xqci/qc.setwmi.yaml | 2 +- .../arch_overlay/inst/Xqci/qc.shladd.yaml | 2 +- .../qc_iu/arch_overlay/inst/Xqci/qc.swmi.yaml | 2 +- .../arch_overlay/inst/Xqci/qc.wrapi.yaml | 7 ++-- cfgs/qc_iu/cfg.yaml | 2 +- 34 files changed, 185 insertions(+), 33 deletions(-) diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_flags.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_flags.yaml index 0a06f9cfb4..7ee6a34ac2 100644 --- a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_flags.yaml +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_flags.yaml @@ -8,7 +8,10 @@ base: 32 length: 32 description: | Condition Code Register with condition codes, plus a co-processor flags (_e.g._, to support floating point) -definedBy: Xqci +definedBy: + anyOf: + - Xqci + - Xqciint fields: CPFLAGS: location: 31-16 diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie0.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie0.yaml index 67e1074a4e..04d4431e2c 100644 --- a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie0.yaml +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie0.yaml @@ -8,7 +8,10 @@ address: 0x7f0 length: 32 base: 32 priv_mode: M -definedBy: Xqci +definedBy: + anyOf: + - Xqci + - Xqciint description: | Enable bits for IRQs 0-31 fields: diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie1.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie1.yaml index 93310b5a3a..0282d05aba 100644 --- a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie1.yaml +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie1.yaml @@ -8,7 +8,10 @@ address: 0x7f1 length: 32 base: 32 priv_mode: M -definedBy: Xqci +definedBy: + anyOf: + - Xqci + - Xqciint description: | Enable bits for IRQs 32-63 fields: diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie2.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie2.yaml index d5b0f0420a..8d94f4f210 100644 --- a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie2.yaml +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie2.yaml @@ -8,7 +8,10 @@ address: 0x7f2 length: 32 base: 32 priv_mode: M -definedBy: Xqci +definedBy: + anyOf: + - Xqci + - Xqciint description: | Enable bits for IRQs 64-95 fields: diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie3.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie3.yaml index 809335febc..f98e158172 100644 --- a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie3.yaml +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie3.yaml @@ -8,7 +8,10 @@ address: 0x7f3 length: 32 base: 32 priv_mode: M -definedBy: Xqci +definedBy: + anyOf: + - Xqci + - Xqciint description: | Enable bits for IRQs 96-127 fields: diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie4.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie4.yaml index ad7b3e806a..21c6423240 100644 --- a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie4.yaml +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie4.yaml @@ -8,7 +8,10 @@ address: 0x7f4 length: 32 base: 32 priv_mode: M -definedBy: Xqci +definedBy: + anyOf: + - Xqci + - Xqciint description: | Enable bits for IRQs 128-159 fields: diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie5.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie5.yaml index 2c6aaee9f7..1bab8f05db 100644 --- a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie5.yaml +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie5.yaml @@ -8,7 +8,10 @@ address: 0x7f5 length: 32 base: 32 priv_mode: M -definedBy: Xqci +definedBy: + anyOf: + - Xqci + - Xqciint description: | Enable bits for IRQs 160-191 fields: diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie6.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie6.yaml index bffa251af9..7a25830b12 100644 --- a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie6.yaml +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie6.yaml @@ -8,7 +8,10 @@ address: 0x7f6 length: 32 base: 32 priv_mode: M -definedBy: Xqci +definedBy: + anyOf: + - Xqci + - Xqciint description: | Enable bits for IRQs 192-223 fields: diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie7.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie7.yaml index 9898db8b59..c8e816eb05 100644 --- a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie7.yaml +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie7.yaml @@ -8,7 +8,10 @@ address: 0x7f7 length: 32 base: 32 priv_mode: M -definedBy: Xqci +definedBy: + anyOf: + - Xqci + - Xqciint description: | Enable bits for IRQs 224-255 fields: diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip0.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip0.yaml index 6dc1fcecf1..a89cbd333a 100644 --- a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip0.yaml +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip0.yaml @@ -8,7 +8,10 @@ address: 0x7f0 length: 32 priv_mode: M base: 32 -definedBy: Xqci +definedBy: + anyOf: + - Xqci + - Xqciint description: | Pending bits for IRQs 0-31 fields: diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip1.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip1.yaml index a3fe935cc7..5f00b2e09d 100644 --- a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip1.yaml +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip1.yaml @@ -8,7 +8,10 @@ address: 0x7f1 length: 32 priv_mode: M base: 32 -definedBy: Xqci +definedBy: + anyOf: + - Xqci + - Xqciint description: | Pending bits for IRQs 32-63 fields: diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip2.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip2.yaml index f53932a7c5..01ec079504 100644 --- a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip2.yaml +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip2.yaml @@ -8,7 +8,10 @@ address: 0x7f2 length: 32 priv_mode: M base: 32 -definedBy: Xqci +definedBy: + anyOf: + - Xqci + - Xqciint description: | Pending bits for IRQs 64-95 fields: diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip3.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip3.yaml index 1726552ee6..70f8f0067c 100644 --- a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip3.yaml +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip3.yaml @@ -8,7 +8,10 @@ address: 0x7f3 length: 32 priv_mode: M base: 32 -definedBy: Xqci +definedBy: + anyOf: + - Xqci + - Xqciint description: | Pending bits for IRQs 96-127 fields: diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip4.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip4.yaml index 40eb770e5f..a8266fd36f 100644 --- a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip4.yaml +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip4.yaml @@ -8,7 +8,10 @@ address: 0x7f4 length: 32 priv_mode: M base: 32 -definedBy: Xqci +definedBy: + anyOf: + - Xqci + - Xqciint description: | Pending bits for IRQs 128-159 fields: diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip5.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip5.yaml index 8482078fb4..3985e0f402 100644 --- a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip5.yaml +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip5.yaml @@ -8,7 +8,10 @@ address: 0x7f5 length: 32 priv_mode: M base: 32 -definedBy: Xqci +definedBy: + anyOf: + - Xqci + - Xqciint description: | Pending bits for IRQs 160-191 fields: diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip6.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip6.yaml index a052056919..987bb95eb8 100644 --- a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip6.yaml +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip6.yaml @@ -8,7 +8,10 @@ address: 0x7f6 length: 32 priv_mode: M base: 32 -definedBy: Xqci +definedBy: + anyOf: + - Xqci + - Xqciint description: | Pending bits for IRQs 192-223 fields: diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip7.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip7.yaml index c9332a57c0..f50fc8131b 100644 --- a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip7.yaml +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip7.yaml @@ -8,7 +8,10 @@ address: 0x7f7 length: 32 priv_mode: M base: 32 -definedBy: Xqci +definedBy: + anyOf: + - Xqci + - Xqciint description: | Pending bits for IRQs 224-255 fields: diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqci.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqci.yaml index eaa3a15510..c01049b064 100644 --- a/cfgs/qc_iu/arch_overlay/ext/Xqci.yaml +++ b/cfgs/qc_iu/arch_overlay/ext/Xqci.yaml @@ -92,6 +92,42 @@ versions: requires: name: Zca version: ">= 1.0.0" +- version: "0.5.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com + changes: + - Fix description of qc.shladd instruction + - Fix description and functionality of qc.c.extu instruction + - Fix description and functionality of qc.wrapi instruction + - Fix description of qc.swmi, qc.lwmi and qc.setwmi instructions + - Fix description of qc.mclici* CSRs to reflect being part of Xqciint custom extension + - Fix description of qc.setinti and qc.clrinti instructions + implies: + - [Xqcia, "0.3.0"] + - [Xqciac, "0.3.0"] + - [Xqcibi, "0.2.0"] + - [Xqcibm, "0.3.0"] + - [Xqcicli, "0.2.0"] + - [Xqcicm, "0.2.0"] + - [Xqcics, "0.2.0"] + - [Xqcicsr, "0.2.0"] + - [Xqciint, "0.3.0"] + - [Xqcilb, "0.2.0"] + - [Xqcili, "0.2.0"] + - [Xqcilia, "0.2.0"] + - [Xqcilo, "0.2.0"] + - [Xqcilsm, "0.3.0"] + - [Xqcisls, "0.2.0"] + requires: + name: Zca + version: ">= 1.0.0" description: | The Xqci extension includes a set of instructions that improve RISC-V code density and performance in microontrollers. It fills several gaps: diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqcia.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqcia.yaml index 951e57af94..c098ca7ffa 100644 --- a/cfgs/qc_iu/arch_overlay/ext/Xqcia.yaml +++ b/cfgs/qc_iu/arch_overlay/ext/Xqcia.yaml @@ -28,6 +28,18 @@ versions: email: dhower@qti.qualcomm.com changes: - Add information about instruction formats of each instruction +- version: "0.3.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com + changes: + - Fix description and functionality of qc.wrapi instruction description: | The Xqcia extension includes eleven instructions to perform integer arithmetic. diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqciac.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqciac.yaml index deef748aae..698def9ba1 100644 --- a/cfgs/qc_iu/arch_overlay/ext/Xqciac.yaml +++ b/cfgs/qc_iu/arch_overlay/ext/Xqciac.yaml @@ -30,6 +30,19 @@ versions: - Add information about instruction formats of each instruction - Fix description and functionality of qc.shladd instruction requires: { name: Zca, version: ">= 1.0.0" } +- version: "0.3.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com + changes: + - Fix description and functionality of qc.shladd instruction + requires: { name: Zca, version: ">= 1.0.0" } description: | The Xqciac extension includes three instructions to accelerate common address calculations. diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqcibm.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqcibm.yaml index 61ffca3b02..1f64d90b03 100644 --- a/cfgs/qc_iu/arch_overlay/ext/Xqcibm.yaml +++ b/cfgs/qc_iu/arch_overlay/ext/Xqcibm.yaml @@ -30,6 +30,19 @@ versions: - Add information about instruction formats of each instruction - Fix description and functionality of qc.c.extu instruction requires: { name: Zca, version: ">= 1.0.0" } +- version: "0.3.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com + changes: + - Fix description and functionality of qc.c.extu instruction + requires: { name: Zca, version: ">= 1.0.0" } description: | The Xqcibm extension includes thirty eight instructions that perform bit manipulation, include insertion and extraction. diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqciint.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqciint.yaml index aa00848cb8..89617e7202 100644 --- a/cfgs/qc_iu/arch_overlay/ext/Xqciint.yaml +++ b/cfgs/qc_iu/arch_overlay/ext/Xqciint.yaml @@ -29,6 +29,20 @@ versions: changes: - Add information about instruction formats of each instruction requires: { name: Zca, version: ">= 1.0.0" } +- version: "0.3.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com + changes: + - Fix description of qc.mclici* CSRs to reflect being part of Xqciint custom extension + - Fix description of qc.setinti and qc.clrinti instructions + requires: { name: Zca, version: ">= 1.0.0" } description: | The Xqciint extension includes eleven instructions to accelerate interrupt servicing by performing common actions during ISR prologue/epilogue. diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqcilsm.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqcilsm.yaml index dd853b48c4..9a97f0ed6e 100644 --- a/cfgs/qc_iu/arch_overlay/ext/Xqcilsm.yaml +++ b/cfgs/qc_iu/arch_overlay/ext/Xqcilsm.yaml @@ -28,6 +28,18 @@ versions: email: dhower@qti.qualcomm.com changes: - Add information about instruction formats of each instruction +- version: "0.3.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com + changes: + - Fix description of qc.swmi, qc.lwmi and qc.setwmi instructions description: | The Xqcilsm extension includes six instructions that transfer multiple values between registers and memory. diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.clrinti.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.clrinti.yaml index e70fcc8cf9..96238d5217 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.clrinti.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.clrinti.yaml @@ -6,7 +6,7 @@ name: qc.clrinti long_name: Clear interrupt (Immediate) description: | Clear interrupt, interrupt number is in `imm` (0 - 1023). - Instruction encoded in I instruction format. + Instruction encoded in R instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lwmi.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lwmi.yaml index 2fbc7ef37d..efb6d76a48 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lwmi.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lwmi.yaml @@ -7,7 +7,7 @@ long_name: Load word multiple (Immediate) description: | Loads multiple words starting from address (`rs1` + `imm`) to registers, starting from `rd`. The number of words is in the `length` immediate. - Instruction encoded in I instruction format. + Instruction encoded in R instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.norm.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.norm.yaml index 8fe5c096ce..8d25c140eb 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.norm.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.norm.yaml @@ -33,6 +33,6 @@ access: operation(): | XReg clz = (xlen() - 1) - $signed(highest_set_bit(X[rs1])); XReg clo = (xlen() - 1) - $signed(highest_set_bit(~X[rs1])); - XReg exp = (X[rs1][31] == 1) ? (X[rs1] << (clo - 1)) : (X[rs1] << (clz - 1)); - XReg mnt = (X[rs1][31] == 1) ? (-(clo - 1)) : (-(clz - 1)); + XReg mnt = (X[rs1][31] == 1) ? (X[rs1] << (clo - 1)) : (X[rs1] << (clz - 1)); + XReg exp = (X[rs1][31] == 1) ? (-(clo - 1)) : (-(clz - 1)); X[rd] = {mnt[23:0],exp[7:0]}; diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.normeu.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.normeu.yaml index ed1192add6..aed59d633a 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.normeu.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.normeu.yaml @@ -32,6 +32,6 @@ access: vu: always operation(): | XReg clz = ((xlen() - 1) - $signed(highest_set_bit(X[rs1]))) & ~1; - XReg exp = (X[rs1] << clz); - XReg mnt = (-clz); + XReg mnt = (X[rs1] << (clz & ~1)); + XReg exp = ((-clz) & ~1); X[rd] = {mnt[23:0],exp[7:0]}; diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.normu.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.normu.yaml index ff9b5b5690..18e5ef70c9 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.normu.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.normu.yaml @@ -32,6 +32,6 @@ access: vu: always operation(): | XReg clz = (xlen() - 1) - $signed(highest_set_bit(X[rs1])); - XReg exp = (X[rs1] << clz); - XReg mnt = (-clz); + XReg mnt = (X[rs1] << clz); + XReg exp = (-clz); X[rd] = {mnt[23:0],exp[7:0]}; diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.setinti.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.setinti.yaml index a620f66043..241f4ddbc1 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.setinti.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.setinti.yaml @@ -6,7 +6,7 @@ name: qc.setinti long_name: Set interrupt (Immediate) description: | Set interrupt, interrupt number is in `imm` (0 - 1023). - Instruction encoded in I instruction format. + Instruction encoded in R instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.setwmi.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.setwmi.yaml index 750c3fd251..37afc0393e 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.setwmi.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.setwmi.yaml @@ -7,7 +7,7 @@ long_name: Set word multiple (Immediate) description: | Stores the value of `rs3` multiple times into the address starting at (`rs1` + `imm`). The number of writes is in length. - Instruction encoded in I instruction format. + Instruction encoded in R instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.shladd.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.shladd.yaml index 026f521f44..0b54322c27 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.shladd.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.shladd.yaml @@ -28,7 +28,7 @@ encoding: - name: rd location: 11-7 not: 0 -assembly: " xs1, xs2, shamt" +assembly: " xd, xs1, xs2, shamt" access: s: always u: always diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.swmi.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.swmi.yaml index bdbaca6452..b7dbc428cd 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.swmi.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.swmi.yaml @@ -7,7 +7,7 @@ long_name: Store word multiple (immediate) description: | Stores multiple words from the registers starting at `rs3` to the address starting at (`rs1` + `imm`). The number of words is in `length` immediate. - Instruction encoded in I instruction format. + Instruction encoded in R instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.wrapi.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.wrapi.yaml index e35eb20470..8d4949afce 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.wrapi.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.wrapi.yaml @@ -3,12 +3,13 @@ $schema: inst_schema.json# kind: instruction name: qc.wrapi -long_name: Wraparound (Immediate) +long_name: Wraparound (Unsigned Immediate) description: | If `rs1` >= `imm` perform subtraction between `rs1` and `imm`. If `rs1` < 0, perform addition between `rs1` and `imm`, else, select `rs1`. The result is stored in `rd`. Instruction encoded in I instruction format. + The `imm` is an unsigned immediate. definedBy: anyOf: - Xqci @@ -33,8 +34,8 @@ access: vu: always operation(): | XReg rs1_value = X[rs1]; - X[rd] = ($signed(rs1_value) >= $signed(imm)) + X[rd] = ($signed(rs1_value) >= imm) ? rs1_value - imm : (($signed(rs1_value) < 0) - ? (rs1_value + imm) + ? ($signed(rs1_value) + imm) : rs1_value); diff --git a/cfgs/qc_iu/cfg.yaml b/cfgs/qc_iu/cfg.yaml index 3e26c94455..a28bdd53a7 100644 --- a/cfgs/qc_iu/cfg.yaml +++ b/cfgs/qc_iu/cfg.yaml @@ -8,6 +8,6 @@ description: Configuration with the Xqci custom extension. mandatory_extensions: - { name: Sm } - { name: I } - - { name: Xqci, version: "~> 0.4" } + - { name: Xqci, version: "~> 0.5" } params: XLEN: 32 From 981c5ddcab3b9bac54f47d0d227b98f6a9ca7f00 Mon Sep 17 00:00:00 2001 From: Albert Yosher Date: Tue, 7 Jan 2025 11:40:09 +0200 Subject: [PATCH 02/11] Fix name of instructions qc.c.muladdi -> qc.c.muliadd, qc.muladdi -> qc.muliadd Signed-off-by: Albert Yosher --- cfgs/qc_iu/arch_overlay/ext/Xqciac.yaml | 1 + .../inst/Xqci/{qc.c.muladdi.yaml => qc.c.muliadd.yaml} | 2 +- .../arch_overlay/inst/Xqci/{qc.muladdi.yaml => qc.muliadd.yaml} | 2 +- 3 files changed, 3 insertions(+), 2 deletions(-) rename cfgs/qc_iu/arch_overlay/inst/Xqci/{qc.c.muladdi.yaml => qc.c.muliadd.yaml} (97%) rename cfgs/qc_iu/arch_overlay/inst/Xqci/{qc.muladdi.yaml => qc.muliadd.yaml} (97%) diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqciac.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqciac.yaml index 698def9ba1..f1c0791a16 100644 --- a/cfgs/qc_iu/arch_overlay/ext/Xqciac.yaml +++ b/cfgs/qc_iu/arch_overlay/ext/Xqciac.yaml @@ -42,6 +42,7 @@ versions: email: dhower@qti.qualcomm.com changes: - Fix description and functionality of qc.shladd instruction + - Renaming instructions qc.muladdi to qc.muliadd and qc.c.muladdi to qc.c.muliadd requires: { name: Zca, version: ">= 1.0.0" } description: | The Xqciac extension includes three instructions to accelerate common diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.muladdi.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.muliadd.yaml similarity index 97% rename from cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.muladdi.yaml rename to cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.muliadd.yaml index 32b847c805..da1af4692a 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.muladdi.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.muliadd.yaml @@ -2,7 +2,7 @@ $schema: inst_schema.json# kind: instruction -name: qc.c.muladdi +name: qc.c.muliadd long_name: Multiply and accumulate (Immediate) description: | Increments `rd` by the multiplication of `rs1` and an unsigned immediate diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.muladdi.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.muliadd.yaml similarity index 97% rename from cfgs/qc_iu/arch_overlay/inst/Xqci/qc.muladdi.yaml rename to cfgs/qc_iu/arch_overlay/inst/Xqci/qc.muliadd.yaml index 4c92acdf23..3815398b77 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.muladdi.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.muliadd.yaml @@ -2,7 +2,7 @@ $schema: inst_schema.json# kind: instruction -name: qc.muladdi +name: qc.muliadd long_name: Multiply and accumulate (Immediate) description: | Increments `rd` by the multiplication of `rs1` and a signed immediate `imm`. From a5dd820d42fc799752d1a74292c976597cab43b6 Mon Sep 17 00:00:00 2001 From: James Ball Date: Tue, 7 Jan 2025 00:45:25 +0000 Subject: [PATCH 03/11] Removed arch_gen (no longer required) --- backends/arch_gen/lib/arch_gen.rb | 937 ------------------------------ lib/cfg_arch.rb | 13 +- 2 files changed, 6 insertions(+), 944 deletions(-) delete mode 100644 backends/arch_gen/lib/arch_gen.rb diff --git a/backends/arch_gen/lib/arch_gen.rb b/backends/arch_gen/lib/arch_gen.rb deleted file mode 100644 index cea28daf9d..0000000000 --- a/backends/arch_gen/lib/arch_gen.rb +++ /dev/null @@ -1,937 +0,0 @@ -# frozen_string_literal: true - -require "English" -require "erb" -require "pathname" -require "rake/application" -require "rubygems/requirement" -require "tilt" - -require_relative "#{$lib}/validate" -require_relative "#{$lib}/cfg_arch" - -$root = Pathname.new(__FILE__).dirname.dirname.realpath if $root.nil? - -# Class to help parse parameterized arch definitions and generate a unified configuration -# -# ArchGen is initialized with a config name, which *must* be the name of a -# directory under cfgs/ -# -class ArchGen - # configuration name - attr_reader :name - - # path where the result will be written - attr_reader :gen_dir - - # trace a message if Rake's tracing is turned on - def trace(msg) - Rake.application.trace msg if Rake.application.options.trace - end - private :trace - - def gen_params_schema - return if @gen_params_schema_complete == true - - schema = { - "type" => "object", - "required" => ["params"], - "properties" => { - "params" => { - "type" => "object", - "required" => ["NAME"], - "properties" => { - "NAME" => { "type" => "string", "enum" => [@name] }, - "XLEN" => { "type" => "intger", "enum" => [32, 64] } - }, - "additionalProperties" => false - } - }, - "additionalProperties" => false - } - @implemented_extensions.each do |ext| - ext_name = ext["name"] - gen_ext_path = @gen_dir / "arch" / "ext" / "#{ext_name}.yaml" - ext_yaml = YAML.load_file gen_ext_path.to_s - unless ext_yaml["params"].nil? - ext_yaml["params"].each do |param_name, param_data| - schema["properties"]["params"]["required"] << param_name - schema["properties"]["params"]["properties"][param_name] = { - "description" => param_data["description"] - }.merge(param_data["schema"]) - end - end - end - schema["properties"]["params"]["required"].uniq! - - FileUtils.mkdir_p @params_schema_path.dirname - @params_schema_path.write JSON.dump(schema) - @gen_params_schema_complete = true - end - - # Initialize an Architecture Generator - # - # @param config_name [#to_s] The name of config located in the cfgs/ directory, - def initialize(config_name) - @validator = Validator.instance - - @name = config_name.to_s - @cfg_dir = $root / "cfgs" / @name - @gen_dir = $root / "gen" / @name - - raise "No config named '#{@name}'" unless File.exist?(@cfg_dir) - - @cfg_params_path = @cfg_dir / "params.yaml" - raise "No params.yaml file in #{@cfg_dir}" unless @cfg_params_path.exist? - - cfg_impl_ext_path = @cfg_dir / "implemented_exts.yaml" - raise "No implemented_exts.yaml file in #{@cfg_dir}" unless cfg_impl_ext_path.exist? - - @cfg_impl_ext = @validator.validate(cfg_impl_ext_path)["implemented_extensions"] - raise "Validation failed" if @cfg_impl_ext.nil? - - cfg_opts_path = @cfg_dir / "cfg.yaml" - @cfg_opts = YamlLoader.load(cfg_opts_path, permitted_classes:[Date]) - raise "Validation failed" if @cfg_opts.nil? - raise "Validation failed: bad type" unless ["partially configured", "fully configured"].include?(@cfg_opts["type"]) - - - @params_schema_path = @gen_dir / "schemas" / "params_schema.json" - - @ext_gen_complete = false - - end - - # @return [Hash] Hash of parameter names to values - def params - return @params unless @params.nil? - - gen_params_schema - - # use validator to pick up defaults - @params = - Validator.instance.validate_str( - File.read(@cfg_params_path), - schema_path: @params_schema_path - )["params"] - end - - def assert(cond) - raise "Assertion Failed" unless cond - end - private :assert - - def ext?(name) - @implemented_extensions.any? { |ext| ext["name"] == name.to_s } - end - private :ext? - - # checks any "extra_validation" given by parameter definitions - def params_extra_validation - - agen = self - - eval_context = Class.new do - end - - eval_context.class.define_method(:ext?) { |name| agen.send(:ext?, name) } - eval_context.class.define_method(:assert) { |cond| agen.send(:assert, cond) } - - # add parameters as a constant - params.each do |key, value| - eval_context.const_set(key, value) - end - - - @implemented_extensions.each do |ext| - ext_name = ext["name"] - gen_ext_path = @gen_dir / "arch" / "ext" / "#{ext_name}.yaml" - ext_yaml = YAML.load_file gen_ext_path.to_s - unless ext_yaml["params"].nil? - ext_yaml["params"].each do |param_name, param_data| - next unless param_data.key?("extra_validation") - begin - eval_context.class_eval param_data["extra_validation"] - rescue StandardError => e - warn "While checking extension parameter #{ext_name}::#{param_name}.extra_validation" - warn param_data["extra_validation"] - warn e - exit 1 - end - end - end - end - end - private :params_extra_validation - - # validate the params.yaml file of a config. - # - # This does several things: - # - # * Generates a config-specific schmea based on: - # ** the extensions a config implements - # ** the parameters an implemented extension requires - # * Validates params.yaml against that configuration-specific schema - # * Checks any extra validation specified by 'extra_validation' - def validate_params - gen_ext_def - add_implied_extensions - check_extension_dependencies - - gen_params_schema - @validator.validate @cfg_params_path - - params_extra_validation - end - - # generate the architecture definition into the gen directory - # - # After calling this, gen/CFG_NAME/arch will be populated with up-to-date - # parsed (with ERB) and merged (with overlay) architecture files. - def generate - # extensions need to be parsed first since we pull, e.g., exception codes from them - gen_ext_def - add_implied_extensions - check_extension_dependencies - - gen_params_schema - validate_params - - gen_csr_def - - gen_inst_def - - gen_cfg_arch - - @generate_done = true - end - - def check_extension_dependencies - @implemented_extensions.each do |ext| - requirements = @required_ext_map[[ext["name"], ext["version"]]] - satisfied = requirements.satisfied_by? do |req| - @implemented_extensions.any? do |ext2| - (ext2["name"] == req.name) && Gem::Requirement.new(req.version_requirement).satisfied_by?(Gem::Version.new(ext2["version"])) - end - end - unless satisfied - warn "Extension '#{ext}' requires extension '#{r}'; it must also be implemented" - exit 1 - end - end - end - - # transitively adds any implied extensions to the @implemented_extensions list - def add_implied_extensions - return if @add_implied_extensions_complete == true - - @implemented_extensions.each do |ext| - extras = @implied_ext_map[[ext["name"], ext["version"]]] - next if extras.nil? || extras.empty? - - # turn it into an array if it isn't already - extras = [extras] unless extras[0].is_a?(Array) - extras.each do |extra_ext| - unless all_known_exts.include?(extra_ext[0]) - raise "Implied extension '#{extra_ext}' for '#{ext}' is not defined" - end - - next if @implemented_extensions.include?({ - "name" => extra_ext[0], - "version" => extra_ext[1] - }) - - @implemented_extensions << { - "name" => extra_ext[0], - "version" => extra_ext[1] - } - end - end - - @add_implied_extensions_complete = true - end - private :add_implied_extensions - - # @return [Array] List of all implemented CSRs - def implemented_csrs - generate unless @generate_done - @implemented_csrs - end - - # @return [Array] List of all implemented instructions - def implemented_instructions - generate unless @generate_done - @implemented_instructions - end - - # @return [Array] List of all implemented extensions - def implemented_extensions - generate unless @generate_done - @implemented_extensions - end - - # Generate the config-specific, unified architecture spec data structure - # - def gen_cfg_arch - csr_ary = Dir.glob(@gen_dir / "arch" / "csr" / "**" / "*.yaml").map do |f| - YamlLoader.load(f, permitted_classes:[Date]) - end - inst_ary = Dir.glob(@gen_dir / "arch" / "inst" / "**" / "*.yaml").map do |f| - YamlLoader.load(f, permitted_classes:[Date]) - end - ext_ary = Dir.glob(@gen_dir / "arch" / "ext" / "**" / "*.yaml").map do |f| - YamlLoader.load(f, permitted_classes:[Date]) - end - profile_class_hash = Dir.glob($root / "arch" / "profile_class" / "**" / "*.yaml").map do |f| - profile_class_obj = YamlLoader.load(f, permitted_classes:[Date]) - profile_class_name = profile_class_obj.keys[0] - profile_class_obj[profile_class_name]["name"] = profile_class_name - profile_class_obj[profile_class_name]["$source"] = f - [profile_class_name, profile_class_obj[profile_class_name]] - end.to_h - profile_release_hash = Dir.glob($root / "arch" / "profile_release" / "**" / "*.yaml").map do |f| - profile_release_obj = YamlLoader.load(f, permitted_classes:[Date]) - profile_release_name = profile_release_obj.keys[0] - profile_release_obj[profile_release_name]["name"] = profile_release_name - profile_release_obj[profile_release_name]["$source"] = f - [profile_release_name, profile_release_obj[profile_release_name]] - end.to_h - cert_class_ary = Dir.glob($root / "arch" / "certificate_class" / "**" / "*.yaml").map do |f| - cert_class_obj = YamlLoader.load(f, permitted_classes:[Date]) - cert_class_obj["$source"] = f - cert_class_obj - end - cert_model_ary = Dir.glob($root / "arch" / "certificate_model" / "**" / "*.yaml").map do |f| - cert_model_obj = YamlLoader.load(f, permitted_classes:[Date]) - cert_model_obj["$source"] = f - cert_model_obj - end - manual_hash = {} - Dir.glob($root / "arch" / "manual" / "**" / "contents.yaml").map do |f| - manual_version = YamlLoader.load(f, permitted_classes:[Date]) - manual_id = manual_version["manual"] - unless manual_hash.key?(manual_id) - manual_info_files = Dir.glob($root / "arch" / "manual" / "**" / "#{manual_id}.yaml") - raise "Could not find manual info '#{manual_id}'.yaml, needed by #{f}" if manual_info_files.empty? - raise "Found multiple manual infos '#{manual_id}'.yaml, needed by #{f}" if manual_info_files.size > 1 - - manual_info_file = manual_info_files.first - manual_hash[manual_id] = YamlLoader.load(manual_info_file, permitted_classes:[Date]) - manual_hash[manual_id]["$source"] = manual_info_file - # TODO: schema validation - end - - manual_hash[manual_id]["versions"] ||= [] - manual_hash[manual_id]["versions"] << YamlLoader.load(f, permitted_classes:[Date]) - # TODO: schema validation - manual_hash[manual_id]["versions"].last["$source"] = f - end - - cfg_arch = { - "type" => @cfg_opts["type"], - "params" => params, - "instructions" => inst_ary, - "implemented_instructions" => @implemented_instructions, - "extensions" => ext_ary, - "implemented_extensions" => @implemented_extensions, - "csrs" => csr_ary, - "implemented_csrs" => @implemented_csrs, - "profile_classes" => profile_class_hash, - "profile_releases" => profile_release_hash, - "certificate_classes" => cert_class_ary, - "certificate_models" => cert_model_ary, - "manuals" => manual_hash - } - - yaml = YAML.dump(cfg_arch) - cfg_arch_yaml = "# yaml-language-server: $schema=../../../arch/arch_schema.json\n\n#{yaml}" - abs_cfg_arch_path = @gen_dir / "arch" / "cfg_arch.yaml" - - # return early if this cfg_arch hasn't changed - # return if abs_cfg_arch_path.exist? && (abs_cfg_arch_path.read == cfg_arch_yaml) - - File.write(abs_cfg_arch_path, cfg_arch_yaml) - - # make sure it passes validation - # begin - # @validator.validate_str(YAML.dump(cfg_arch), type: :arch) - # rescue Validator::SchemaValidationError => e - # warn "While validating the unified architecture defintion at #{abs_cfg_arch_path}" - # raise e - # end - end - private :gen_cfg_arch - - # @return [Object] An object that has a method (lowercase) or constant (uppercase) for every config option - # so that obj.param_name or obj.PARAM_NAME gets you the value - def env - return @env unless @env.nil? - - @env = Class.new - @env.instance_variable_set(:@cfg, @cfg) - @env.instance_variable_set(:@params, @params) - @env.instance_variable_set(:@arch_gen, self) - - # add each parameter, either as a method (lowercase) or constant (uppercase) - @params.each do |key, value| - if key[0].upcase == key[0] - @env.const_set(key, value) - else - @env.class.define_method(key) { value } - end - end - - @cfg.each do |key, value| - next if key == "params" - - if key[0].upcase == key[0] - @env.const_set(key, value) - else - @env.class.define_method(key) { value } - end - end - - # add an asset_map function to get access to the artifact mapper - @env.class.define_method(:asset_map) do - return @asset_map unless @asset_map.nil? - - @asset_map = Class.new { extend AssetMap } - @asset_map - end - - @env.instance_exec do - # method to check if a given extension (with an optional version number) is present - # - # @param ext_name [String,#to_s] Name of the extension - # @param ext_requirement [String, #to_s] Version string, as a Gem Requirement (https://guides.rubygems.org/patterns/#pessimistic-version-constraint) - # @return [Boolean] whether or not extension +ext_name+ meeting +ext_requirement+ is implemented in the config - def ext?(ext_name, ext_requirement = ">= 0") - if ext_requirement.nil? - @cfg_impl_ext.any? do |e| - e[0] == ext_name.to_s - end - else - requirement = Gem::Requirement.create(ext_requirement.to_s) - @cfg_impl_ext.any? do |e| - e[0] == ext_name.to_s && requirement.satisfied_by?(Gem::Version.new(e[1])) - end - end - end - - # @return [Array] List of possible XLENs for any implemented mode - def possible_xlens - possible = [@params["XLEN"]] - possible << 32 if ext?('S') && [32, 3264].include?(@params["SXLEN"]) - possible << 64 if ext?('S') && [32, 3264].include?(@params["SXLEN"]) - possible << 32 if ext?('U') && [32, 3264].include?(@params["UXLEN"]) - possible << 64 if ext?('U') && [32, 3264].include?(@params["UXLEN"]) - possible << 32 if ext?('H') && [32, 3264].include?(@params["VSXLEN"]) - possible << 64 if ext?('H') && [32, 3264].include?(@params["VSXLEN"]) - possible << 32 if ext?('H') && [32, 3264].include?(@params["VUXLEN"]) - possible << 64 if ext?('H') && [32, 3264].include?(@params["VUXLEN"]) - possible.uniq - end - - # insert a hyperlink to an object - # At this point, we insert a placeholder since it will be up - # to the backend to create a specific link - # - # @params type [Symbol] Type (:section, :csr, :inst, :ext) - # @params name [#to_s] Name of the object - def link_to(type, name) - "%%LINK%#{type};#{name}%%" - end - - # info on interrupt and exception codes - - # @returns [Hash] architecturally-defined exception codes and their names - def exception_codes - @arch_gen.exception_codes - end - - # returns [Hash] architecturally-defined interrupt codes and their names - def interrupt_codes - @arch_gen.interrupt_codes - end - end - - @env - end - private :env - - # merges patch into base_obj based on JSON Merge Patch (RFC 7386) - # - # @param base_obj [Hash] base object to merge into - # @param patch [Hash] patch to merge into base_obj - # @param path_so_far [Array] path into the current object. Shouldn't be set by user (used during recursion) - # @return [Hash] merged object - def merge_patch(base, patch, path_so_far = []) - patch_obj = path_so_far.empty? ? patch : patch.dig(*path_so_far) - patch_obj.each do |key, patch_value| - if patch_value.is_a?(Hash) - # continue to dig - merge_patch(base, patch, (path_so_far + [key])) - else - base_ptr = base.dig(*path_so_far) - base_value = base_ptr&.dig(key) - case patch_value - when nil - # remove from base, if it exists - unless base_value.nil? - base_ptr[key] = nil - end - else - # add or overwrite value in base - if base_ptr.nil? - # need to create intermediate nodes, too - base_ptr = base - path_so_far.each do |k| - base_ptr[k] = {} unless base_ptr.key?(k) - base_ptr = base_ptr[k] - end - base_ptr = base.dig(*path_so_far) - end - base_ptr[key] = patch_value - end - end - end - end - private :merge_patch - - # overwrites base_obj with any data in update - # - # @param base_obj [Hash] Base object - # @param updates [Hash] Object with overlays - # @return [Hash] Updated object - def merge(base_obj, updates) = merge_patch(base_obj, updates, []) - private :merge - - # @param type [Symbol] Type of the object (@see Validator::SCHEMA_PATHS) - # @param name [#to_s] Name of the object - # @return [Pathname,nil] Path to architecture definition template for a given type:name, or nil if none exists - def arch_path_for(type, name) - source_matches = Dir.glob($root / "arch" / type.to_s / "**" / "#{name}.yaml") - raise "Multiple source matches: #{source_matches} for #{type}:#{name}" if source_matches.size > 1 - return nil if source_matches.empty? # not an error, might be a full overlay - - Pathname.new(source_matches[0]) - end - private :arch_path_for - - # @param type [Symbol] Type of the object (@see Validator::SCHEMA_PATHS) - # @param name [#to_s] Name of the object - # @return [Pathname,nil] Path to architecture overlay for a given type:name, or nil if none exists - def arch_overlay_path_for(type, name) - source_matches = Dir.glob(@cfg_dir / "arch_overlay" / type.to_s / "**" / "#{name}.yaml") - raise "Multiple source matches in overlay: #{source_matches} for #{type}:#{name}" if source_matches.size > 1 - return nil if source_matches.empty? # not an error, might be a full overlay - - Pathname.new(source_matches[0]) - end - private :arch_overlay_path_for - - # @param type [Symbol] Type of the object (@see Validator::SCHEMA_PATHS) - # @return [Pathname,nil] Path to schema for type - def schema_path_for(type) = Validator::SCHEMA_PATHS[type] - private :schema_path_for - - # generate a merged definition from rendered arch and overlay, and write it to gen / .merged_arch - # - # Skips if gen file already exists and sources are older - # - # @param type [Symbol] Type of the object (@see Validator::SCHEMA_PATHS) - # @param arch_path [Pathname,nil] Path to rendered arch defintion, or nil if none - # @param overlay_path [Pathname,nil] Path to rendered overlay, or nil if none - # @return [Pathname] Path to generated merged definition - def gen_merged_def(type, arch_path, overlay_path) - raise "Must have at least one of arch_path or overlay_path" if arch_path.nil? && overlay_path.nil? - - name = arch_path.nil? ? overlay_path.basename(".yaml") : arch_path.basename(".yaml") - - merged_path = @gen_dir / ".merged_arch" / type.to_s / "#{name}.yaml" - - if merged_path.exist? - arch_time = arch_path.nil? ? Time.new(0) : arch_path.mtime - overlay_time = overlay_path.nil? ? Time.new(0) : overlay_path.mtime - dep_mtime = [arch_time, overlay_time].max - return merged_path if merged_path.mtime >= dep_mtime - end - - trace "Rendering merged file for #{type}:#{name}" - - FileUtils.mkdir_p merged_path.dirname - if overlay_path.nil? - # no overlay, just copy arch - merged_path.write YAML.dump(YamlLoader.load(arch_path)) - # FileUtils.cp arch_path, merged_path - elsif arch_path.nil? - # no arch, overlay is arch - merged_path.write YAML.dump(YamlLoader.load(overlay_path)) - # FileUtils.cp overlay_path, merged_path - else - # arch and overlay, do the merge - arch_obj = YamlLoader.load(arch_path) - overlay_obj = YamlLoader.load(overlay_path) - - merge(arch_obj, overlay_obj) - merged_path.write YAML.dump(arch_obj) - end - - begin - @validator.validate_str(merged_path.read, type:) - rescue Validator::SchemaValidationError => e - warn "Merged #{type} definition in #{merged_path} did not validate" - raise e - end - - merged_path - end - private :gen_merged_def - - # given a CSR name, determine if it is supposed to exist in the config, and, if so, - # render the result and add it to the running list of extant CSRs - # - # @param csr_name [#to_s] CSR name - # @param extra_env [Hash] Extra enviornment variables to be used when parsing the CSR definition template - def maybe_add_csr(csr_name, extra_env = {}) - arch_path = arch_path_for(:csr, csr_name) - arch_overlay_path = arch_overlay_path_for(:csr, csr_name) - - # return immediately if this CSR isn't defined in this config - raise "No arch or overlay for sr #{csr_name}" if arch_path.nil? && arch_overlay_path.nil? - - merged_path = gen_merged_def(:csr, arch_path, arch_overlay_path) - - merged_content = File.read(merged_path) - arch_content = arch_path.nil? ? "" : File.read(arch_path) - arch_overlay_content = arch_path.nil? ? "" : File.read(arch_path) - - # figure out where the original file can be found: - # * arch_path if there is no contribution from arch_overlay - # * arch_overlay_path if there is no contribution from arch (i.e., a custom instruction) - # * merged_path if there are contributions from both - og_path = - if arch_content == merged_content - arch_path_for(:csr, csr_name) - elsif arch_overlay_content == merged_content - arch_overlay_path_for(:csr, csr_name) - else - merged_path - end - - # get the csr data (not including the name key), which is redundant at this point - csr_data = YAML.load_file(merged_path) - csr_data["fields"].each { |n, f| f["name"] = n } - csr_data["$source"] = og_path.to_s - - csr_yaml = YAML.dump(csr_data) - begin - csr_data = @validator.validate_str(csr_yaml, type: :csr) - rescue Validator::SchemaValidationError => e - warn "Instruction definition in #{merged_path} did not validate" - raise e - end - - csr_obj = Csr.new(csr_data) - cfg_arch_mock = Object.new - cfg_arch_mock.define_singleton_method(:fully_configured?) { true } - pos_xlen_local = possible_xlens - cfg_arch_mock.define_singleton_method(:possible_xlens) do - pos_xlen_local - end - impl_ext = @cfg_impl_ext.map { |e| ExtensionVersion.new(e[0], e[1], nil) } - cfg_arch_mock.define_singleton_method(:implemented_extensions) do - impl_ext - end - belongs = - csr_obj.exists_in_cfg?(cfg_arch_mock) - - - @implemented_csrs ||= [] - @implemented_csrs << csr_name if belongs - - gen_csr_path = @gen_dir / "arch" / "csr" / csr_obj.primary_defined_by / "#{csr_name}.yaml" - FileUtils.mkdir_p gen_csr_path.dirname - gen_csr_path.write csr_yaml - end - private :maybe_add_csr - - # return list of all known CSR names, even those not part of this config - # Includes both CSRs defined in arch/ and those added through an overlay of the config - # - # @return [Array] List of all known CSR names - def all_known_csrs - ( - Dir.glob($root / "arch" / "csr" / "**" / "*.yaml") + # CSRs in arch/ - Dir.glob(@cfg_dir / "arch_overlay" / "csr" / "**" / "*.yaml") # CSRs in cfg/arch_overlay/ - ).map do |f| - File.basename(f, ".yaml") - end - end - private :all_known_csrs - - # generate all CSR definitions for the config - def gen_csr_def - csr_list = all_known_csrs - - csr_list.each do |csr_name| - maybe_add_csr(csr_name) - end - end - private :gen_csr_def - - # return list of all known extension names, even those not part of this config - # Includes both extensions defined in arch/ and those added through an overlay of the config - # - # @return [Array] List of all known extension names - def all_known_exts - ( - Dir.glob($root / "arch" / "ext" / "**" / "*.yaml") + # exts in arch/ - Dir.glob(@cfg_dir / "arch_overlay" / "ext" / "**" / "*.yaml") # exts in cfg/arch_overlay/ - ).map do |f| - File.basename(f, ".yaml") - end - end - - def maybe_add_ext(ext_name) - arch_path = arch_path_for(:ext, ext_name) - arch_overlay_path = arch_overlay_path_for(:ext, ext_name) - - # return immediately if this ext isn't defined - return if arch_path.nil? && arch_overlay_path.nil? - - merged_path = gen_merged_def(:ext, arch_path, arch_overlay_path) - - yaml_contents = YAML.load_file(merged_path) - raise "In #{merged_path}, key does not match file name" unless yaml_contents["name"] == ext_name - - ext_obj = yaml_contents - - @implied_ext_map ||= {} - @required_ext_map ||= {} - - ext_obj["versions"].each do |v| - implies = case v["implies"] - when nil - [] - when Array - v["implies"][0].is_a?(Array) ? v["implies"] : [v["implies"]] - end - requires = case v["requires"] - when nil - AlwaysTrueSchemaCondition.new - when Hash - SchemaCondition.new(v["requires"]) - else - SchemaCondition.new({"oneOf" => [v["requires"]]}) - end - raise "Bad condition" if requires.nil? - - @implied_ext_map[[ext_name, v["version"].to_s]] = implies.map { |i| [i[0], i[1].to_s] } - @required_ext_map[[ext_name, v["version"].to_s]] = requires - end - - belongs = - @cfg_impl_ext.any? { |e| e[0] == ext_name } - @implemented_extensions ||= [] - if belongs - @implemented_extensions << { - "name" => ext_name, - "version" => @cfg_impl_ext.select { |e| e[0] == ext_name }[0][1].to_s - } - end - - if belongs - # check that the version number exists, too - cfg_ext = @cfg_impl_ext.select { |e| e[0] == ext_name }[0] - - if ext_obj["versions"].select { |v| v["version"] == cfg_ext[1] }.empty? - raise "Configured version for extension #{extension_name} not defined" - end - end - - gen_ext_path = @gen_dir / "arch" / "ext" / "#{ext_name}.yaml" - FileUtils.mkdir_p gen_ext_path.dirname - gen_ext_path.write YAML.dump(ext_obj) - end - private :maybe_add_ext - - # generate parsed and merged definitions for all extensions - def gen_ext_def - return if @ext_gen_complete == true - - ext_list = all_known_exts - - ext_list.each do |ext_name| - maybe_add_ext(ext_name) - end - - @ext_gen_complete = true - end - private :gen_ext_def - - # Returns mapping of exception codes to text name. - # - # @return [Hash] Mapping of exception code number to text name - def exception_codes - return @exception_codes unless @exception_codes.nil? - - gen_ext_def unless @ext_gen_complete - - @exception_codes = {} - Dir.glob(@gen_dir / "arch" / "ext" / "*.yaml") do |ext_path| - ext_obj = YamlLoader.load(ext_path, permitted_classes:[Date]) - ext_obj = ext_obj[ext_obj.keys[0]] - if ext_obj.key?("exception_codes") - ext_obj["exception_codes"].each do |exception_code| - @exception_codes[exception_code["num"]] = exception_code["name"] - end - end - end - @exception_codes - end - - # Returns mapping of interrupt codes to text name. - # - # @return [Hash] Mapping of interrupt code number to text name - def interrupt_codes - return @interrupt_codes unless @interrupt_codes.nil? - - gen_ext_def unless @ext_gen_complete - - @interrupt_codes = {} - Dir.glob(@gen_dir / "arch" / "ext" / "*.yaml") do |ext_path| - ext_obj = YamlLoader.load(ext_path, permitted_classes:[Date]) - ext_obj = ext_obj[ext_obj.keys[0]] - if ext_obj.key?("interrupt_codes") - ext_obj["interrupt_codes"].each do |interrupt_code| - @interrupt_codes[interrupt_code["num"]] = interrupt_code["name"] - end - end - end - @interrupt_codes - end - - def possible_xlens - possible_xlens = [params["XLEN"]] - if @cfg_impl_ext.any? { |e| e[0] == "S" } - possible_xlens << 32 if [32, 3264].include?(params["SXLEN"]) - possible_xlens << 64 if [64, 3264].include?(params["SXLEN"]) - end - if @cfg_impl_ext.any? { |e| e[0] == "U" } - possible_xlens << 32 if [32, 3264].include?(params["UXLEN"]) - possible_xlens << 64 if [64, 3264].include?(params["UXLEN"]) - end - if @cfg_impl_ext.any? { |e| e[0] == "H" } - possible_xlens << 32 if [32, 3264].include?(params["VSXLEN"]) - possible_xlens << 32 if [32, 3264].include?(params["VUXLEN"]) - possible_xlens << 64 if [64, 3264].include?(params["VSXLEN"]) - possible_xlens << 64 if [64, 3264].include?(params["VUXLEN"]) - end - possible_xlens - end - private :possible_xlens - - # add an instruction to the running list of instructions for this config if it should be included - # - # @param inst_name [#to_s] instruction name - # @param extra_env [Hash] Extra options to add into the rendering enviornment - def maybe_add_inst(inst_name, extra_env = {}) - arch_path = arch_path_for(:inst, inst_name) - arch_overlay_path = arch_overlay_path_for(:inst, inst_name) - - # return immediately if inst isn't defined in this config - raise "No arch or overlay for instruction #{inst_name}" if arch_path.nil? && arch_overlay_path.nil? - - merged_path = gen_merged_def(:inst, arch_path, arch_overlay_path) - - merged_content = File.read(merged_path) - arch_content = arch_path.nil? ? "" : File.read(arch_path) - arch_overlay_content = arch_path.nil? ? "" : File.read(arch_path) - - # figure out where the original file can be found: - # * arch_path if there is no contribution from arch_overlay - # * arch_overlay_path if there is no contribution from arch (i.e., a custom instruction) - # * merged_path if there are contributions from both - og_path = - if arch_content == merged_content - arch_path_for(:inst, inst_name) - elsif arch_overlay_content == merged_content - arch_overlay_path_for(:inst, inst_name) - else - merged_path - end - - # get the inst data (not including the name key), which is redundant at this point - inst_data = YAML.load_file(merged_path) - inst_data["$source"] = og_path.to_s - - inst_yaml = YAML.dump(inst_data) - begin - inst_data = @validator.validate_str(inst_yaml, type: :inst) - rescue Validator::SchemaValidationError => e - warn "Instruction definition in #{gen_inst_path} did not validate" - raise e - end - - inst_obj = Instruction.new(inst_data, nil) - possible_xlens = [params["XLEN"]] - if @cfg_impl_ext.any? { |e| e[0] == "S" } - possible_xlens << 32 if [32, 3264].include?(params["SXLEN"]) - possible_xlens << 64 if [64, 3264].include?(params["SXLEN"]) - end - if @cfg_impl_ext.any? { |e| e[0] == "U" } - possible_xlens << 32 if [32, 3264].include?(params["UXLEN"]) - possible_xlens << 64 if [64, 3264].include?(params["UXLEN"]) - end - if @cfg_impl_ext.any? { |e| e[0] == "H" } - possible_xlens << 32 if [32, 3264].include?(params["VSXLEN"]) - possible_xlens << 32 if [32, 3264].include?(params["VUXLEN"]) - possible_xlens << 64 if [64, 3264].include?(params["VSXLEN"]) - possible_xlens << 64 if [64, 3264].include?(params["VUXLEN"]) - end - cfg_arch_mock = Object.new - cfg_arch_mock.define_singleton_method(:fully_configured?) { true } - cfg_arch_mock.define_singleton_method(:possible_xlens) { possible_xlens } - impl_ext = @cfg_impl_ext.map { |e| ExtensionVersion.new(e[0], e[1], nil) } - cfg_arch_mock.define_singleton_method(:implemented_extensions) do - impl_ext - end - belongs = - inst_obj.exists_in_cfg?(cfg_arch_mock) - - @implemented_instructions ||= [] - @implemented_instructions << inst_name if belongs - - raise "?" if inst_obj.primary_defined_by.nil? - gen_inst_path = @gen_dir / "arch" / "inst" / inst_obj.primary_defined_by / "#{inst_name}.yaml" - FileUtils.mkdir_p gen_inst_path.dirname - gen_inst_path.write inst_yaml - end - private :maybe_add_inst - - # return list of all known instruction names, even those not part of this config - # Includes both instructionss defined in arch/ and those added through an overlay of the config - # - # @return [Array] List of all known instruction names - def all_known_insts - ( - Dir.glob($root / "arch" / "inst" / "**" / "*.yaml") + # instructions in arch/ - Dir.glob(@cfg_dir / "arch_overlay" / "inst" / "**" / "*.yaml") # instructions in cfg/arch_overlay/ - ).map do |f| - File.basename(f, ".yaml") - end - end - private :all_known_insts - - # generate all parsed / merged instruction definitions - def gen_inst_def - inst_list = all_known_insts - - inst_list.each do |inst_name| - maybe_add_inst(inst_name) - end - end - private :gen_inst_def - -end diff --git a/lib/cfg_arch.rb b/lib/cfg_arch.rb index f86df3dad1..3a66918ed1 100644 --- a/lib/cfg_arch.rb +++ b/lib/cfg_arch.rb @@ -639,7 +639,6 @@ def erb_env @env = Class.new @env.instance_variable_set(:@cfg, @cfg) @env.instance_variable_set(:@params, @params) - @env.instance_variable_set(:@arch_gen, self) # add each parameter, either as a method (lowercase) or constant (uppercase) params_with_value.each do |param| @@ -657,12 +656,12 @@ def erb_env # @param ext_requirement [String, #to_s] Version string, as a Gem Requirement (https://guides.rubygems.org/patterns/#pessimistic-version-constraint) # @return [Boolean] whether or not extension +ext_name+ meeting +ext_requirement+ is implemented in the config def ext?(ext_name, ext_requirement = ">= 0") - @arch_gen.ext?(ext_name.to_s, ext_requirement) + @cfg_arch.ext?(ext_name.to_s, ext_requirement) end # @return [Array] List of possible XLENs for any implemented mode def possible_xlens - @arch_gen.possible_xlens + @cfg_arch.possible_xlens end # insert a hyperlink to an object @@ -679,22 +678,22 @@ def link_to(type, name) # @returns [Hash] architecturally-defined exception codes and their names def exception_codes - @arch_gen.exception_codes + @cfg_arch.exception_codes end # returns [Hash] architecturally-defined interrupt codes and their names def interrupt_codes - @arch_gen.interrupt_codes + @cfg_arch.interrupt_codes end # @returns [Hash] architecturally-defined exception codes and their names def implemented_exception_codes - @arch_gen.implemented_exception_codes + @cfg_arch.implemented_exception_codes end # returns [Hash] architecturally-defined interrupt codes and their names def implemented_interrupt_codes - @arch_gen.implemented_interrupt_codes + @cfg_arch.implemented_interrupt_codes end end From 8d2b83faae45068b3884d9aa82d2a61cf10c64dc Mon Sep 17 00:00:00 2001 From: Derek Hower <134728312+dhower-qc@users.noreply.github.com> Date: Tue, 7 Jan 2025 11:45:22 -0500 Subject: [PATCH 04/11] Fix regression test, caused by Ubuntu 24.04 namespace change (#393) --- bin/build_container | 5 +++++ bin/setup | 48 ++++++++++++++++++++++++++------------------- 2 files changed, 33 insertions(+), 20 deletions(-) diff --git a/bin/build_container b/bin/build_container index 0e87290574..02588f5bad 100755 --- a/bin/build_container +++ b/bin/build_container @@ -9,6 +9,11 @@ if [ -v GITHUB_ACTIONS ]; then CONTAINER_PATH=${ROOT}/.singularity/image.sif HOME_PATH=${GITHUB_WORKSPACE} SINGULARITY_CACHE=--disable-cache + + # needed to get singularity working on Ubuntu 24.04 + # see https://github.com/lima-vm/lima/issues/2319 + sudo /bin/bash -c "echo \"kernel.apparmor_restrict_unprivileged_userns = 0\" >/etc/sysctl.d/99-userns.conf" + sudo sysctl --system else CONTAINER_PATH=${ROOT}/.singularity/image-$CONTAINER_TAG.sif HOME_PATH=${HOME} diff --git a/bin/setup b/bin/setup index 934c8033ac..f0a46655b2 100755 --- a/bin/setup +++ b/bin/setup @@ -22,17 +22,17 @@ CONTAINER_TAG=`cat ${ROOT}/bin/.container-tag` # An apptainer/singularity container. All commands on the host (using ./do or ./bin/*) are run in the context of an Apptainer/Singularity image. # # -# ALL THREE CONTAINERS ARE IDENTICAL. Which one you use is a preference of your setup and installed +# ALL THREE CONTAINERS ARE (in theory) IDENTICAL. Which one you use is a preference of your setup and installed # software. # get the container type # # use, in priority order: -# 1. devcontainer, if DEVCONTAINER_ENV is set in the enviornment +# 1. devcontainer, if DEVCONTAINER_ENV is set in the environment # 2. the type stored in .container-type -# 3. Docker, if DOCKER is set in the enviornment -# 4. Singularity, if SINGULARITY is set in the enviornment +# 3. Docker, if DOCKER is set in the environment +# 4. Singularity, if SINGULARITY is set in the environment # 5. The choice made by the user, which will be cached in .container-type if [ -v DEVCONTAINER_ENV ]; then CONTAINER_TYPE=devcontainer @@ -55,7 +55,7 @@ else done fi -if [ "${CONTAINER_TYPE}" != "docker" -a "${CONTAINER_TYPE}" != "singularity" ]; then +if [ "${CONTAINER_TYPE}" != "docker" -a "${CONTAINER_TYPE}" != "singularity" -a "${CONTAINER_TYPE}" != "devcontainer" ]; then echo "BAD CONTAINER TYPE: ${CONTAINER_TYPE}" fi @@ -63,22 +63,20 @@ if [ ! -f ${ROOT}/.container-type ]; then echo ${CONTAINER_TYPE} > ${ROOT}/.container-type fi -print_env() { - if [ "${CONTAINER_TYPE}" == "docker" ]; then - echo "Using Docker environment" - else - echo "Using Singularity environment" - fi -} +echo "Using ${CONTAINER_TYPE} environment" if [ -v GITHUB_ACTIONS ]; then - echo "ACTIONS" + echo "Running in a GitHub Action" CONTAINER_PATH=${ROOT}/.singularity/image.sif HOME_PATH=${GITHUB_WORKSPACE} HOME_OPT="--home ${ROOT}/.home" SINGULARITY_CACHE=--disable-cache + + # needed to get singularity working on Ubuntu 24.04 + # see https://github.com/lima-vm/lima/issues/2319 + sudo /bin/bash -c "echo \"kernel.apparmor_restrict_unprivileged_userns = 0\" >/etc/sysctl.d/99-userns.conf" + sudo sysctl --system elif [ "${CONTAINER_TYPE}" == "docker" ]; then - print_env if ! docker images riscvintl/udb:${CONTAINER_TAG} | grep -q udb ; then # TODO: pull the image if it can be found echo "Building Docker image..." @@ -90,8 +88,7 @@ elif [ "${CONTAINER_TYPE}" == "docker" ]; then DOCKER_BASE="docker run -v $(ROOT):$(ROOT) -w $(ROOT) riscvintl/udb:${CONTAINER_TAG}" fi RUN="${DOCKER_BASE}" -else - print_env +elif [ "${CONTAINER_TYPE}" == "singularity" ]; then CONTAINER_PATH=${ROOT}/.singularity/image-$CONTAINER_TAG.sif HOME_PATH=${HOME} HOME_OPT="--bind ${ROOT}/.home:${HOME_PATH}" @@ -103,6 +100,11 @@ else fi singularity pull ${SINGULARITY_CACHE} ${CONTAINER_PATH} oras://docker.io/riscvintl/spec-generator:$CONTAINER_TAG fi +elif [ "${CONTAINER_TYPE}" == "devcontainer" ]; then + HOME_PATH=${HOME} +else + echo "Bad container type: ${CONTAINER_TYPE}" 1>&2 + exit 1 fi if [ -f $ROOT/.git ]; then @@ -111,12 +113,15 @@ if [ -f $ROOT/.git ]; then HOME_OPT="${HOME_OPT} --bind ${GIT_PATH}:${GIT_PATH}" fi -if [ -v DEVCONTAINER_ENV ]; then +if [ "${CONTAINER_TYPE}" == "devcontainer" ]; then RUN="" elif [ "${CONTAINER_TYPE}" == "docker" ]; then RUN="${DOCKER_BASE}" -else +elif [ "${CONTAINER_TYPE}" == "singularity" ]; then RUN="singularity run ${HOME_OPT} ${CONTAINER_PATH}" +else + echo "Bad container type: ${CONTAINER_TYPE}" 1>&2 + exit 1 fi if [ ! -d $ROOT/.home ]; then @@ -164,7 +169,7 @@ if [ ! -d ${ROOT}/node_modules ]; then ${RUN} npm i fi -if [ -v DEVCONTAINER_ENV ]; then +if [ "${CONTAINER_TYPE}" == "devcontainer" ]; then BUNDLE="bundle" RUBY="bundle exec ruby" RAKE="bundle exec rake" @@ -184,7 +189,7 @@ elif [ "${CONTAINER_TYPE}" == "docker" ]; then PYTHON="${DOCKER_BASE} ${ROOT}/.home/.venv/bin/python3" PIP="${DOCKER_BASE} ${ROOT}/.home/.venv/bin/pip" BASH="${DOCKER_BASE} bash" -else +elif [ "${CONTAINER_TYPE}" == "singularity" ]; then BUNDLE="singularity run ${HOME_OPT} ${CONTAINER_PATH} bundle" RUBY="singularity run ${HOME_OPT} ${CONTAINER_PATH} bundle exec ruby" RAKE="singularity run ${HOME_OPT} ${CONTAINER_PATH} bundle exec rake" @@ -194,6 +199,9 @@ else PYTHON="singularity run ${HOME_OPT} ${CONTAINER_PATH} ${ROOT}/.home/.venv/bin/python3" PIP="singularity run ${HOME_OPT} ${CONTAINER_PATH} ${ROOT}/.home/.venv/bin/pip" BASH="singularity run ${HOME_OPT} ${CONTAINER_PATH} bash" +else + echo "Bad container type: ${CONTAINER_TYPE}" 1>&2 + exit 1 fi if [ ! -f $ROOT/.git/hooks/pre-commit ]; then From e78114f323375531f0f5a81321cd65c82cdd264c Mon Sep 17 00:00:00 2001 From: Albert Yosher Date: Wed, 8 Jan 2025 22:29:24 +0200 Subject: [PATCH 05/11] Xqci extension: add Xqciio and Xqcisim sub-extensions, initial spec addition Signed-off-by: Albert Yosher --- cfgs/qc_iu/arch_overlay/ext/Xqci.yaml | 4 +++ cfgs/qc_iu/arch_overlay/ext/Xqciio.yaml | 27 ++++++++++++++ cfgs/qc_iu/arch_overlay/ext/Xqcisim.yaml | 28 +++++++++++++++ .../arch_overlay/inst/Xqci/qc.c.ptrace.yaml | 28 +++++++++++++++ cfgs/qc_iu/arch_overlay/inst/Xqci/qc.inw.yaml | 35 +++++++++++++++++++ .../qc_iu/arch_overlay/inst/Xqci/qc.outw.yaml | 35 +++++++++++++++++++ .../arch_overlay/inst/Xqci/qc.pcoredump.yaml | 29 +++++++++++++++ .../arch_overlay/inst/Xqci/qc.pexit.yaml | 30 ++++++++++++++++ .../arch_overlay/inst/Xqci/qc.ppreg.yaml | 30 ++++++++++++++++ .../arch_overlay/inst/Xqci/qc.ppregs.yaml | 28 +++++++++++++++ .../arch_overlay/inst/Xqci/qc.pputc.yaml | 30 ++++++++++++++++ .../arch_overlay/inst/Xqci/qc.pputci.yaml | 30 ++++++++++++++++ .../arch_overlay/inst/Xqci/qc.pputs.yaml | 31 ++++++++++++++++ .../arch_overlay/inst/Xqci/qc.psyscall.yaml | 31 ++++++++++++++++ .../arch_overlay/inst/Xqci/qc.psyscalli.yaml | 31 ++++++++++++++++ cfgs/qc_iu/arch_overlay/isa/globals.isa | 26 ++++++++++++++ 16 files changed, 453 insertions(+) create mode 100644 cfgs/qc_iu/arch_overlay/ext/Xqciio.yaml create mode 100644 cfgs/qc_iu/arch_overlay/ext/Xqcisim.yaml create mode 100644 cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.ptrace.yaml create mode 100644 cfgs/qc_iu/arch_overlay/inst/Xqci/qc.inw.yaml create mode 100644 cfgs/qc_iu/arch_overlay/inst/Xqci/qc.outw.yaml create mode 100644 cfgs/qc_iu/arch_overlay/inst/Xqci/qc.pcoredump.yaml create mode 100644 cfgs/qc_iu/arch_overlay/inst/Xqci/qc.pexit.yaml create mode 100644 cfgs/qc_iu/arch_overlay/inst/Xqci/qc.ppreg.yaml create mode 100644 cfgs/qc_iu/arch_overlay/inst/Xqci/qc.ppregs.yaml create mode 100644 cfgs/qc_iu/arch_overlay/inst/Xqci/qc.pputc.yaml create mode 100644 cfgs/qc_iu/arch_overlay/inst/Xqci/qc.pputci.yaml create mode 100644 cfgs/qc_iu/arch_overlay/inst/Xqci/qc.pputs.yaml create mode 100644 cfgs/qc_iu/arch_overlay/inst/Xqci/qc.psyscall.yaml create mode 100644 cfgs/qc_iu/arch_overlay/inst/Xqci/qc.psyscalli.yaml diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqci.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqci.yaml index 384f714be8..4fa8192815 100644 --- a/cfgs/qc_iu/arch_overlay/ext/Xqci.yaml +++ b/cfgs/qc_iu/arch_overlay/ext/Xqci.yaml @@ -103,6 +103,8 @@ versions: company: Qualcomm Technologies, Inc. email: dhower@qti.qualcomm.com changes: + - Added Xqciio sub-extension + - Added Xqcisim sub-extension - Fix description of qc.shladd instruction - Fix description and functionality of qc.c.extu instruction - Fix description and functionality of qc.wrapi instruction @@ -119,11 +121,13 @@ versions: - [Xqcics, "0.2.0"] - [Xqcicsr, "0.2.0"] - [Xqciint, "0.3.0"] + - [Xqciio, "0.1.0"] - [Xqcilb, "0.2.0"] - [Xqcili, "0.2.0"] - [Xqcilia, "0.2.0"] - [Xqcilo, "0.2.0"] - [Xqcilsm, "0.3.0"] + - [Xqcisim, "0.1.0"] - [Xqcisls, "0.2.0"] requires: name: Zca diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqciio.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqciio.yaml new file mode 100644 index 0000000000..7546a1e02c --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/ext/Xqciio.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../../schemas/ext_schema.json + +$schema: ext_schema.json# +kind: extension +name: Xqciio +type: privileged +long_name: Qualcomm Input/Output device support +versions: +- version: "0.1.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com +description: | + The Xqciio extension includes two instructions to access external non-memory-mapped devices for input and output + +doc_license: + name: Creative Commons Attribution 4.0 International License + url: https://creativecommons.org/licenses/by/4.0/ +company: + name: Qualcomm Technologies, Inc. + url: https://qualcomm.com diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqcisim.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqcisim.yaml new file mode 100644 index 0000000000..da15d48925 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/ext/Xqcisim.yaml @@ -0,0 +1,28 @@ +# yaml-language-server: $schema=../../../../schemas/ext_schema.json + +$schema: ext_schema.json# +kind: extension +name: Xqcisim +type: unprivileged +long_name: Qualcomm simulator support hints +versions: +- version: "0.1.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com +description: | + The Xqcisim extension includes ten hint instructions to interface simulation environment. + On real target any instruction from this extension executed as "no-operation" and have no effect. + +doc_license: + name: Creative Commons Attribution 4.0 International License + url: https://creativecommons.org/licenses/by/4.0/ +company: + name: Qualcomm Technologies, Inc. + url: https://qualcomm.com diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.ptrace.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.ptrace.yaml new file mode 100644 index 0000000000..58363c5180 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.ptrace.yaml @@ -0,0 +1,28 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.c.ptrace +long_name: Tracing pseudo-instruction (hint) working only in simulation environment +description: | + The tracing instruction have no explicit arguments. + Implicit arguments defined by simulation environment implementation. + Instruction is used to signal simulator to collect some tracing information. + Instruction encoded in CI instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisim +assembly: "" +base: 32 +encoding: + match: "0000000000000010" +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg func = 9; + XReg arg = 0; + iss_syscall(func,arg); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.inw.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.inw.yaml new file mode 100644 index 0000000000..f782005207 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.inw.yaml @@ -0,0 +1,35 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.inw +long_name: Input word from non-memory-mapped device +description: | + Input 32 bits of data into register `rd` from a non-memory-mapped device. + Such devices have own address space, unrelated to memory map. + Device space address formed by adding `rs1` to to a unsigned offset `imm`. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqciio +assembly: xd, imm(xs1) +base: 32 +encoding: + match: -----------------101-----0001011 + variables: + - name: imm + location: 31-20 + left_shift: 2 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg device_address = X[rs1] + imm; + X[rd] = read_device<32>(device_address); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.outw.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.outw.yaml new file mode 100644 index 0000000000..aab60cca76 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.outw.yaml @@ -0,0 +1,35 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.outw +long_name: Output word to non-memory-mapped device +description: | + Output 32 bits of data from register `rs2` to a non-memory-mapped device. + Such devices have own address space, unrelated to memory map. + Device space address formed by adding `rs1` to to a unsigned offset `imm`. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqciio +assembly: xs2, imm(xs1) +base: 32 +encoding: + match: -----------------100-----0001011 + variables: + - name: imm + location: 31-20 + left_shift: 2 + - name: rs1 + location: 19-15 + - name: rs2 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg device_address = X[rs1] + imm; + write_device<32>(device_address, X[rs2]); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.pcoredump.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.pcoredump.yaml new file mode 100644 index 0000000000..32235017e0 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.pcoredump.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.pcoredump +long_name: Print core dump pseudo-instruction (hint) working only in simulation environment +description: | + The print core dump instruction calls simulation environment with no explicit arguments. + Implicit arguments are all general purpose registers and CSRs. + Simulation environment expected to print the core dump on its console or standard output. + The core dump format and content are defined by simulation environment. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisim +assembly: "" +base: 32 +encoding: + match: "01100000000000000010000000010011" +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg func = 8; + XReg arg = 0; + iss_syscall(func,arg); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.pexit.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.pexit.yaml new file mode 100644 index 0000000000..ab737086b9 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.pexit.yaml @@ -0,0 +1,30 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.pexit +long_name: Exit call with register argument pseudo-instruction (hint) working only in simulation environment +description: | + The Exit call instruction calls simulation environment with unsigned `rs1` explicit argument. + Simulation environment is expected to complete its execution and return to the system with exit code provided in `rs1`. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisim +assembly: " xs1" +base: 32 +encoding: + match: 101100000000-----010000000010011 + variables: + - name: rs1 + location: 19-15 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg func = 12; + XReg arg = X[rs1]; + iss_syscall(func,arg); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.ppreg.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.ppreg.yaml new file mode 100644 index 0000000000..e34c63720d --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.ppreg.yaml @@ -0,0 +1,30 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.ppreg +long_name: Print register pseudo-instruction (hint) working only in simulation environment +description: | + The print register instruction calls simulation environment with `rs1` explicit argument. + Simulation environment expected to print the register value on its console or standard output. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisim +assembly: " xs1" +base: 32 +encoding: + match: 100000000000-----010000000010011 + variables: + - name: rs1 + location: 19-15 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg func = 2; + XReg arg = X[rs1]; + iss_syscall(func,arg); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.ppregs.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.ppregs.yaml new file mode 100644 index 0000000000..c6cc98f6f4 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.ppregs.yaml @@ -0,0 +1,28 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.ppregs +long_name: Print all registers pseudo-instruction (hint) working only in simulation environment +description: | + The print registers instruction calls simulation environment with no explicit arguments. + Implicit arguments are all general purpose registers. + Simulation environment expected to print the all registers value on its console or standard output. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisim +assembly: "" +base: 32 +encoding: + match: "01110000000000000010000000010011" +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg func = 3; + XReg arg = 0; + iss_syscall(func,arg); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.pputc.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.pputc.yaml new file mode 100644 index 0000000000..1fe99fb415 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.pputc.yaml @@ -0,0 +1,30 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.pputc +long_name: Print character passed in register argument pseudo-instruction (hint) working only in simulation environment +description: | + The print character instruction calls simulation environment with `rs1` explicit argument. + Simulation environment expected to print the character on its console or standard output. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisim +assembly: " xs1" +base: 32 +encoding: + match: 100100000000-----010000000010011 + variables: + - name: rs1 + location: 19-15 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg func = 4; + XReg arg = X[rs1]; + iss_syscall(func,arg); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.pputci.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.pputci.yaml new file mode 100644 index 0000000000..3dc97c52d3 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.pputci.yaml @@ -0,0 +1,30 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.pputci +long_name: Print character passed in the immediate argument pseudo-instruction (hint) working only in simulation environment +description: | + The print character instruction calls simulation environment with unsigned `imm` explicit argument. + Simulation environment expected to print the 8-bit character on its console or standard output. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisim +assembly: " imm" +base: 32 +encoding: + match: 0100--------00000010000000010011 + variables: + - name: imm + location: 29-20 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg func = 5; + XReg arg = imm; + iss_syscall(func,arg); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.pputs.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.pputs.yaml new file mode 100644 index 0000000000..9cba2dbd37 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.pputs.yaml @@ -0,0 +1,31 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.pputs +long_name: Print string pseudo-instruction (hint) working only in simulation environment +description: | + The print string instruction calls simulation environment with `rs1` explicit argument. + The argument assumed to be pointer to the string in target simulated memory. + Simulation environment expected to print the string on its console or standard output. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisim +assembly: " xs1" +base: 32 +encoding: + match: 101000000000-----010000000010011 + variables: + - name: rs1 + location: 19-15 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg func = 6; + XReg arg = X[rs1]; + iss_syscall(func,arg); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.psyscall.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.psyscall.yaml new file mode 100644 index 0000000000..ce78769508 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.psyscall.yaml @@ -0,0 +1,31 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.psyscall +long_name: System call with register argument pseudo-instruction (hint) working only in simulation environment +description: | + The System call instruction calls simulation environment with unsigned `rs1` explicit argument. + Additional implicit arguments defined by simulation environment implementation. + Instruction is used to call simulator to execute function according to the argument. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisim +assembly: " xs1" +base: 32 +encoding: + match: 110000000000-----010000000010011 + variables: + - name: rs1 + location: 19-15 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg func = 10; + XReg arg = X[rs1]; + iss_syscall(func,arg); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.psyscalli.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.psyscalli.yaml new file mode 100644 index 0000000000..2ad8ba4453 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.psyscalli.yaml @@ -0,0 +1,31 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.psyscalli +long_name: System call with immediate argument pseudo-instruction (hint) working only in simulation environment +description: | + The System call instruction calls simulation environment with unsigned `imm` explicit argument. + Additional implicit arguments defined by simulation environment implementation. + Instruction is used to call simulator to execute function according to the argument. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisim +assembly: " imm" +base: 32 +encoding: + match: 00----------00000010000000010011 + variables: + - name: imm + location: 29-20 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg func = 11; + XReg arg = imm; + iss_syscall(func,arg); diff --git a/cfgs/qc_iu/arch_overlay/isa/globals.isa b/cfgs/qc_iu/arch_overlay/isa/globals.isa index 5d363ac0c4..3f815b0d8f 100644 --- a/cfgs/qc_iu/arch_overlay/isa/globals.isa +++ b/cfgs/qc_iu/arch_overlay/isa/globals.isa @@ -8,3 +8,29 @@ builtin function delay { Delay the processor by +cycles+ cycles. } } + +builtin function iss_syscall { + arguments XReg id, XReg arg + description { + Instruction set simulator system call. + } +} + +builtin function read_device { + template U32 len + returns Bits + arguments XReg dev_addr + description { + Read from non-memory-mapped device. + Such devices have own addresses not related to memory map. + } +} + +builtin function write_device { + template U32 len + arguments XReg dev_addr, Bits value + description { + Write to non-memory-mapped device. + Such devices have own addresses not related to memory map. + } +} From 9cd84aab59a122f360cc5743c83052411ddac5a3 Mon Sep 17 00:00:00 2001 From: Albert Yosher Date: Thu, 9 Jan 2025 18:52:48 +0200 Subject: [PATCH 06/11] Xqci extension: adding Xqcisync extension (sync with non-memory-mapped devices and delay) Signed-off-by: Albert Yosher --- cfgs/qc_iu/arch_overlay/ext/Xqci.yaml | 2 + cfgs/qc_iu/arch_overlay/ext/Xqcisync.yaml | 28 ++++++++++++ .../arch_overlay/inst/Xqci/qc.c.delay.yaml | 27 ++++++++++++ .../arch_overlay/inst/Xqci/qc.c.sync.yaml | 43 +++++++++++++++++++ .../arch_overlay/inst/Xqci/qc.c.syncr.yaml | 43 +++++++++++++++++++ .../arch_overlay/inst/Xqci/qc.c.syncwf.yaml | 43 +++++++++++++++++++ .../arch_overlay/inst/Xqci/qc.c.syncwl.yaml | 43 +++++++++++++++++++ .../qc_iu/arch_overlay/inst/Xqci/qc.sync.yaml | 31 +++++++++++++ .../arch_overlay/inst/Xqci/qc.syncr.yaml | 31 +++++++++++++ .../arch_overlay/inst/Xqci/qc.syncwf.yaml | 31 +++++++++++++ .../arch_overlay/inst/Xqci/qc.syncwl.yaml | 31 +++++++++++++ cfgs/qc_iu/arch_overlay/isa/globals.isa | 22 ++++++++++ 12 files changed, 375 insertions(+) create mode 100644 cfgs/qc_iu/arch_overlay/ext/Xqcisync.yaml create mode 100644 cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.delay.yaml create mode 100644 cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.sync.yaml create mode 100644 cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.syncr.yaml create mode 100644 cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.syncwf.yaml create mode 100644 cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.syncwl.yaml create mode 100644 cfgs/qc_iu/arch_overlay/inst/Xqci/qc.sync.yaml create mode 100644 cfgs/qc_iu/arch_overlay/inst/Xqci/qc.syncr.yaml create mode 100644 cfgs/qc_iu/arch_overlay/inst/Xqci/qc.syncwf.yaml create mode 100644 cfgs/qc_iu/arch_overlay/inst/Xqci/qc.syncwl.yaml diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqci.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqci.yaml index 4fa8192815..5be2cfc144 100644 --- a/cfgs/qc_iu/arch_overlay/ext/Xqci.yaml +++ b/cfgs/qc_iu/arch_overlay/ext/Xqci.yaml @@ -105,6 +105,7 @@ versions: changes: - Added Xqciio sub-extension - Added Xqcisim sub-extension + - Added Xqcisync sub-extension - Fix description of qc.shladd instruction - Fix description and functionality of qc.c.extu instruction - Fix description and functionality of qc.wrapi instruction @@ -129,6 +130,7 @@ versions: - [Xqcilsm, "0.3.0"] - [Xqcisim, "0.1.0"] - [Xqcisls, "0.2.0"] + - [Xqcisync, "0.1.0"] requires: name: Zca version: ">= 1.0.0" diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqcisync.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqcisync.yaml new file mode 100644 index 0000000000..832dbbc004 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/ext/Xqcisync.yaml @@ -0,0 +1,28 @@ +# yaml-language-server: $schema=../../../../schemas/ext_schema.json + +$schema: ext_schema.json# +kind: extension +name: Xqcisync +type: unprivileged +long_name: Qualcomm non-memory-mapped devices synchronization and delay +versions: +- version: "0.1.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com +description: | + The Xqcisync extension includes nine instructions, eight for non-memory-mapped devices synchronization and delay instruction. + Synchronization instructions are kind of IO fences that work with special devices synchronization signals. + +doc_license: + name: Creative Commons Attribution 4.0 International License + url: https://creativecommons.org/licenses/by/4.0/ +company: + name: Qualcomm Technologies, Inc. + url: https://qualcomm.com diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.delay.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.delay.yaml new file mode 100644 index 0000000000..32d2a8479a --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.delay.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.c.delay +long_name: Delay execution for immediate amount of cycles +description: | + Delay execution for amount of cycles provided as immediate argument + Instruction encoded in CI instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisync +assembly: "" +base: 32 +encoding: + match: "000000000-----10" + variables: + - name: imm + location: 6-2 +access: + s: always + u: always + vs: always + vu: always +operation(): | + delay(imm); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.sync.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.sync.yaml new file mode 100644 index 0000000000..69bc4fd8b9 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.sync.yaml @@ -0,0 +1,43 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.c.sync +long_name: Non-memory-mapped device read-after-write synchronization to completion +description: | + This synchronization instruction delays execution till last read (input) + from non-memory-mapped device transactions are completed for specified devices. + As well, instruction implies fence.tso functionality for all memory accesses. + Immediate argument is 3-bit encoding of 5-bit bitmask field + that specifies up to five pre-defined devices. + Values of bitmask encoding supported: 0,1,2,4,8,16,15,31 + Instruction encoded in CB instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisync +assembly: " slist" +base: 32 +encoding: + match: "100000---0000001" + variables: + - name: slist + location: 9-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + Bits<5> bitmask; + if (slist == 0) { + bitmask = 0; + } else if (slist < 6) { + XReg shift = slist - 1; + bitmask = (1 << shift); + } else { + XReg shift = slist - 2; + bitmask = (1 << shift) - 1; + } + fence_tso(); + sync_read_after_write_device(true,bitmask); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.syncr.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.syncr.yaml new file mode 100644 index 0000000000..1a50be78bb --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.syncr.yaml @@ -0,0 +1,43 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.c.syncr +long_name: Non-memory-mapped device read-after-write synchronization +description: | + This synchronization instruction delays execution till last read (input) + from non-memory-mapped device transactions are started for specified devices. + As well, instruction implies fence.tso functionality for all memory accesses. + Immediate argument is 3-bit encoding of 5-bit bitmask field + that specifies up to five pre-defined devices. + Values of bitmask encoding supported: 0,1,2,4,8,16,15,31 + Instruction encoded in CB instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisync +assembly: " slist" +base: 32 +encoding: + match: "100001---0000001" + variables: + - name: slist + location: 9-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + Bits<5> bitmask; + if (slist == 0) { + bitmask = 0; + } else if (slist < 6) { + XReg shift = slist - 1; + bitmask = (1 << shift); + } else { + XReg shift = slist - 2; + bitmask = (1 << shift) - 1; + } + fence_tso(); + sync_read_after_write_device(false,bitmask); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.syncwf.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.syncwf.yaml new file mode 100644 index 0000000000..b6da8a8b2c --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.syncwf.yaml @@ -0,0 +1,43 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.c.syncwf +long_name: Non-memory-mapped device write-after-read synchronization +description: | + This synchronization instruction delays execution till last write (output) + to non-memory-mapped device transactions are started for specified devices. + As well, instruction implies fence.tso functionality for all memory accesses. + Immediate argument is 3-bit encoding of 5-bit bitmask field + that specifies up to five pre-defined devices. + Values of bitmask encoding supported: 0,1,2,4,8,16,15,31 + Instruction encoded in CB instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisync +assembly: " slist" +base: 32 +encoding: + match: "100100---0000001" + variables: + - name: slist + location: 9-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + Bits<5> bitmask; + if (slist == 0) { + bitmask = 0; + } else if (slist < 6) { + XReg shift = slist - 1; + bitmask = (1 << shift); + } else { + XReg shift = slist - 2; + bitmask = (1 << shift) - 1; + } + fence_tso(); + sync_write_after_read_device(false,bitmask); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.syncwl.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.syncwl.yaml new file mode 100644 index 0000000000..4462e593b1 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.syncwl.yaml @@ -0,0 +1,43 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.c.syncwl +long_name: Non-memory-mapped device write-after-read synchronization to completion +description: | + This synchronization instruction delays execution till last write (output) + to non-memory-mapped device transactions are completed for specified devices. + As well, instruction implies fence.tso functionality for all memory accesses. + Immediate argument is 3-bit encoding of 5-bit bitmask field + that specifies up to five pre-defined devices. + Values of bitmask encoding supported: 0,1,2,4,8,16,15,31 + Instruction encoded in CB instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisync +assembly: " slist" +base: 32 +encoding: + match: "100101---0000001" + variables: + - name: slist + location: 9-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + Bits<5> bitmask; + if (slist == 0) { + bitmask = 0; + } else if (slist < 6) { + XReg shift = slist - 1; + bitmask = (1 << shift); + } else { + XReg shift = slist - 2; + bitmask = (1 << shift) - 1; + } + fence_tso(); + sync_write_after_read_device(true,bitmask); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.sync.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.sync.yaml new file mode 100644 index 0000000000..b1b4723c61 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.sync.yaml @@ -0,0 +1,31 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.sync +long_name: Non-memory-mapped device read-after-write synchronization to completion +description: | + This synchronization instruction delays execution till last read (input) + from non-memory-mapped device transactions are completed for specified devices. + As well, instruction implies fence.tso functionality for all memory accesses. + Immediate argument is 5-bit bitmask field that specifies up to five pre-defined devices. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisync +assembly: " imm" +base: 32 +encoding: + match: 0001000-----00000011000000010011 + variables: + - name: imm + location: 24-20 +access: + s: always + u: always + vs: always + vu: always +operation(): | + fence_tso(); + sync_read_after_write_device(true,imm); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.syncr.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.syncr.yaml new file mode 100644 index 0000000000..e94dc14675 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.syncr.yaml @@ -0,0 +1,31 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.syncr +long_name: Non-memory-mapped device read-after-write synchronization +description: | + This synchronization instruction delays execution till last read (input) + from non-memory-mapped device transactions are started for specified devices. + As well, instruction implies fence.tso functionality for all memory accesses. + Immediate argument is 5-bit bitmask field that specifies up to five pre-defined devices. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisync +assembly: " imm" +base: 32 +encoding: + match: 0010000-----00000011000000010011 + variables: + - name: imm + location: 24-20 +access: + s: always + u: always + vs: always + vu: always +operation(): | + fence_tso(); + sync_read_after_write_device(false,imm); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.syncwf.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.syncwf.yaml new file mode 100644 index 0000000000..fc51bd96c6 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.syncwf.yaml @@ -0,0 +1,31 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.syncwf +long_name: Non-memory-mapped device write-after-read synchronization +description: | + This synchronization instruction delays execution till last write (output) + to non-memory-mapped device transactions are started for specified devices. + As well, instruction implies fence.tso functionality for all memory accesses. + Immediate argument is 5-bit bitmask field that specifies up to five pre-defined devices. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisync +assembly: " imm" +base: 32 +encoding: + match: 0100000-----00000011000000010011 + variables: + - name: imm + location: 24-20 +access: + s: always + u: always + vs: always + vu: always +operation(): | + fence_tso(); + sync_write_after_read_device(false,imm); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.syncwl.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.syncwl.yaml new file mode 100644 index 0000000000..b9c486b7e1 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.syncwl.yaml @@ -0,0 +1,31 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.syncwl +long_name: Non-memory-mapped device write-after-read synchronization to completion +description: | + This synchronization instruction delays execution till last write (output) + to non-memory-mapped device transactions are completed for specified devices. + As well, instruction implies fence.tso functionality for all memory accesses. + Immediate argument is 5-bit bitmask field that specifies up to five pre-defined devices. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisync +assembly: " imm" +base: 32 +encoding: + match: 1000000-----00000011000000010011 + variables: + - name: imm + location: 24-20 +access: + s: always + u: always + vs: always + vu: always +operation(): | + fence_tso(); + sync_write_after_read_device(true,imm); diff --git a/cfgs/qc_iu/arch_overlay/isa/globals.isa b/cfgs/qc_iu/arch_overlay/isa/globals.isa index 3f815b0d8f..6566048105 100644 --- a/cfgs/qc_iu/arch_overlay/isa/globals.isa +++ b/cfgs/qc_iu/arch_overlay/isa/globals.isa @@ -34,3 +34,25 @@ builtin function write_device { Such devices have own addresses not related to memory map. } } + +builtin function sync_read_after_write_device { + arguments Boolean completed, Bits<5> device_bitmask + description { + Synchronize non-memory-mapped device read-after-write. + Such devices have own addresses not related to memory map. + Devices specified by device bitmask (up to 5 devices). + Stalls processor till condtions met. + Conditions are that last device output started or completed (depends on argument). + } +} + +builtin function sync_write_after_read_device { + arguments Boolean completed, Bits<5> device_bitmask + description { + Synchronize non-memory-mapped device write-after-read. + Such devices have own addresses not related to memory map. + Devices specified by device bitmask (up to 5 devices). + Stalls processor till condtions met. + Conditions are that last device input started or completed (depends on argument). + } +} From d4c6b228f628ade2832c11fbb6df9d9766279eda Mon Sep 17 00:00:00 2001 From: Albert Yosher Date: Mon, 30 Dec 2024 17:48:17 +0200 Subject: [PATCH 07/11] Add fixes for reported issues, update version to 0.5.0 Signed-off-by: Albert Yosher --- .../qc_iu/arch_overlay/csr/Xqci/qc_flags.yaml | 5 ++- .../arch_overlay/csr/Xqci/qc_mclicie0.yaml | 5 ++- .../arch_overlay/csr/Xqci/qc_mclicie1.yaml | 5 ++- .../arch_overlay/csr/Xqci/qc_mclicie2.yaml | 5 ++- .../arch_overlay/csr/Xqci/qc_mclicie3.yaml | 5 ++- .../arch_overlay/csr/Xqci/qc_mclicie4.yaml | 5 ++- .../arch_overlay/csr/Xqci/qc_mclicie5.yaml | 5 ++- .../arch_overlay/csr/Xqci/qc_mclicie6.yaml | 5 ++- .../arch_overlay/csr/Xqci/qc_mclicie7.yaml | 5 ++- .../arch_overlay/csr/Xqci/qc_mclicip0.yaml | 5 ++- .../arch_overlay/csr/Xqci/qc_mclicip1.yaml | 5 ++- .../arch_overlay/csr/Xqci/qc_mclicip2.yaml | 5 ++- .../arch_overlay/csr/Xqci/qc_mclicip3.yaml | 5 ++- .../arch_overlay/csr/Xqci/qc_mclicip4.yaml | 5 ++- .../arch_overlay/csr/Xqci/qc_mclicip5.yaml | 5 ++- .../arch_overlay/csr/Xqci/qc_mclicip6.yaml | 5 ++- .../arch_overlay/csr/Xqci/qc_mclicip7.yaml | 5 ++- cfgs/qc_iu/arch_overlay/ext/Xqci.yaml | 36 +++++++++++++++++++ cfgs/qc_iu/arch_overlay/ext/Xqcia.yaml | 12 +++++++ cfgs/qc_iu/arch_overlay/ext/Xqciac.yaml | 13 +++++++ cfgs/qc_iu/arch_overlay/ext/Xqcibm.yaml | 13 +++++++ cfgs/qc_iu/arch_overlay/ext/Xqciint.yaml | 14 ++++++++ cfgs/qc_iu/arch_overlay/ext/Xqcilsm.yaml | 12 +++++++ .../arch_overlay/inst/Xqci/qc.clrinti.yaml | 2 +- .../qc_iu/arch_overlay/inst/Xqci/qc.lwmi.yaml | 2 +- .../qc_iu/arch_overlay/inst/Xqci/qc.norm.yaml | 4 +-- .../arch_overlay/inst/Xqci/qc.normeu.yaml | 4 +-- .../arch_overlay/inst/Xqci/qc.normu.yaml | 4 +-- .../arch_overlay/inst/Xqci/qc.setinti.yaml | 2 +- .../arch_overlay/inst/Xqci/qc.setwmi.yaml | 2 +- .../arch_overlay/inst/Xqci/qc.shladd.yaml | 2 +- .../qc_iu/arch_overlay/inst/Xqci/qc.swmi.yaml | 2 +- .../arch_overlay/inst/Xqci/qc.wrapi.yaml | 7 ++-- cfgs/qc_iu/cfg.yaml | 2 +- 34 files changed, 185 insertions(+), 33 deletions(-) diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_flags.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_flags.yaml index 0a06f9cfb4..7ee6a34ac2 100644 --- a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_flags.yaml +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_flags.yaml @@ -8,7 +8,10 @@ base: 32 length: 32 description: | Condition Code Register with condition codes, plus a co-processor flags (_e.g._, to support floating point) -definedBy: Xqci +definedBy: + anyOf: + - Xqci + - Xqciint fields: CPFLAGS: location: 31-16 diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie0.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie0.yaml index 67e1074a4e..04d4431e2c 100644 --- a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie0.yaml +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie0.yaml @@ -8,7 +8,10 @@ address: 0x7f0 length: 32 base: 32 priv_mode: M -definedBy: Xqci +definedBy: + anyOf: + - Xqci + - Xqciint description: | Enable bits for IRQs 0-31 fields: diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie1.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie1.yaml index 93310b5a3a..0282d05aba 100644 --- a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie1.yaml +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie1.yaml @@ -8,7 +8,10 @@ address: 0x7f1 length: 32 base: 32 priv_mode: M -definedBy: Xqci +definedBy: + anyOf: + - Xqci + - Xqciint description: | Enable bits for IRQs 32-63 fields: diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie2.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie2.yaml index d5b0f0420a..8d94f4f210 100644 --- a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie2.yaml +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie2.yaml @@ -8,7 +8,10 @@ address: 0x7f2 length: 32 base: 32 priv_mode: M -definedBy: Xqci +definedBy: + anyOf: + - Xqci + - Xqciint description: | Enable bits for IRQs 64-95 fields: diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie3.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie3.yaml index 809335febc..f98e158172 100644 --- a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie3.yaml +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie3.yaml @@ -8,7 +8,10 @@ address: 0x7f3 length: 32 base: 32 priv_mode: M -definedBy: Xqci +definedBy: + anyOf: + - Xqci + - Xqciint description: | Enable bits for IRQs 96-127 fields: diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie4.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie4.yaml index ad7b3e806a..21c6423240 100644 --- a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie4.yaml +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie4.yaml @@ -8,7 +8,10 @@ address: 0x7f4 length: 32 base: 32 priv_mode: M -definedBy: Xqci +definedBy: + anyOf: + - Xqci + - Xqciint description: | Enable bits for IRQs 128-159 fields: diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie5.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie5.yaml index 2c6aaee9f7..1bab8f05db 100644 --- a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie5.yaml +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie5.yaml @@ -8,7 +8,10 @@ address: 0x7f5 length: 32 base: 32 priv_mode: M -definedBy: Xqci +definedBy: + anyOf: + - Xqci + - Xqciint description: | Enable bits for IRQs 160-191 fields: diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie6.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie6.yaml index bffa251af9..7a25830b12 100644 --- a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie6.yaml +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie6.yaml @@ -8,7 +8,10 @@ address: 0x7f6 length: 32 base: 32 priv_mode: M -definedBy: Xqci +definedBy: + anyOf: + - Xqci + - Xqciint description: | Enable bits for IRQs 192-223 fields: diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie7.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie7.yaml index 9898db8b59..c8e816eb05 100644 --- a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie7.yaml +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicie7.yaml @@ -8,7 +8,10 @@ address: 0x7f7 length: 32 base: 32 priv_mode: M -definedBy: Xqci +definedBy: + anyOf: + - Xqci + - Xqciint description: | Enable bits for IRQs 224-255 fields: diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip0.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip0.yaml index 6dc1fcecf1..a89cbd333a 100644 --- a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip0.yaml +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip0.yaml @@ -8,7 +8,10 @@ address: 0x7f0 length: 32 priv_mode: M base: 32 -definedBy: Xqci +definedBy: + anyOf: + - Xqci + - Xqciint description: | Pending bits for IRQs 0-31 fields: diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip1.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip1.yaml index a3fe935cc7..5f00b2e09d 100644 --- a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip1.yaml +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip1.yaml @@ -8,7 +8,10 @@ address: 0x7f1 length: 32 priv_mode: M base: 32 -definedBy: Xqci +definedBy: + anyOf: + - Xqci + - Xqciint description: | Pending bits for IRQs 32-63 fields: diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip2.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip2.yaml index f53932a7c5..01ec079504 100644 --- a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip2.yaml +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip2.yaml @@ -8,7 +8,10 @@ address: 0x7f2 length: 32 priv_mode: M base: 32 -definedBy: Xqci +definedBy: + anyOf: + - Xqci + - Xqciint description: | Pending bits for IRQs 64-95 fields: diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip3.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip3.yaml index 1726552ee6..70f8f0067c 100644 --- a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip3.yaml +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip3.yaml @@ -8,7 +8,10 @@ address: 0x7f3 length: 32 priv_mode: M base: 32 -definedBy: Xqci +definedBy: + anyOf: + - Xqci + - Xqciint description: | Pending bits for IRQs 96-127 fields: diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip4.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip4.yaml index 40eb770e5f..a8266fd36f 100644 --- a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip4.yaml +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip4.yaml @@ -8,7 +8,10 @@ address: 0x7f4 length: 32 priv_mode: M base: 32 -definedBy: Xqci +definedBy: + anyOf: + - Xqci + - Xqciint description: | Pending bits for IRQs 128-159 fields: diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip5.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip5.yaml index 8482078fb4..3985e0f402 100644 --- a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip5.yaml +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip5.yaml @@ -8,7 +8,10 @@ address: 0x7f5 length: 32 priv_mode: M base: 32 -definedBy: Xqci +definedBy: + anyOf: + - Xqci + - Xqciint description: | Pending bits for IRQs 160-191 fields: diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip6.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip6.yaml index a052056919..987bb95eb8 100644 --- a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip6.yaml +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip6.yaml @@ -8,7 +8,10 @@ address: 0x7f6 length: 32 priv_mode: M base: 32 -definedBy: Xqci +definedBy: + anyOf: + - Xqci + - Xqciint description: | Pending bits for IRQs 192-223 fields: diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip7.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip7.yaml index c9332a57c0..f50fc8131b 100644 --- a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip7.yaml +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mclicip7.yaml @@ -8,7 +8,10 @@ address: 0x7f7 length: 32 priv_mode: M base: 32 -definedBy: Xqci +definedBy: + anyOf: + - Xqci + - Xqciint description: | Pending bits for IRQs 224-255 fields: diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqci.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqci.yaml index 8a3b94702f..384f714be8 100644 --- a/cfgs/qc_iu/arch_overlay/ext/Xqci.yaml +++ b/cfgs/qc_iu/arch_overlay/ext/Xqci.yaml @@ -92,6 +92,42 @@ versions: requires: name: Zca version: ">= 1.0.0" +- version: "0.5.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com + changes: + - Fix description of qc.shladd instruction + - Fix description and functionality of qc.c.extu instruction + - Fix description and functionality of qc.wrapi instruction + - Fix description of qc.swmi, qc.lwmi and qc.setwmi instructions + - Fix description of qc.mclici* CSRs to reflect being part of Xqciint custom extension + - Fix description of qc.setinti and qc.clrinti instructions + implies: + - [Xqcia, "0.3.0"] + - [Xqciac, "0.3.0"] + - [Xqcibi, "0.2.0"] + - [Xqcibm, "0.3.0"] + - [Xqcicli, "0.2.0"] + - [Xqcicm, "0.2.0"] + - [Xqcics, "0.2.0"] + - [Xqcicsr, "0.2.0"] + - [Xqciint, "0.3.0"] + - [Xqcilb, "0.2.0"] + - [Xqcili, "0.2.0"] + - [Xqcilia, "0.2.0"] + - [Xqcilo, "0.2.0"] + - [Xqcilsm, "0.3.0"] + - [Xqcisls, "0.2.0"] + requires: + name: Zca + version: ">= 1.0.0" description: | The Xqci extension includes a set of instructions that improve RISC-V code density and performance in microontrollers. It fills several gaps: diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqcia.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqcia.yaml index 951e57af94..c098ca7ffa 100644 --- a/cfgs/qc_iu/arch_overlay/ext/Xqcia.yaml +++ b/cfgs/qc_iu/arch_overlay/ext/Xqcia.yaml @@ -28,6 +28,18 @@ versions: email: dhower@qti.qualcomm.com changes: - Add information about instruction formats of each instruction +- version: "0.3.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com + changes: + - Fix description and functionality of qc.wrapi instruction description: | The Xqcia extension includes eleven instructions to perform integer arithmetic. diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqciac.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqciac.yaml index deef748aae..698def9ba1 100644 --- a/cfgs/qc_iu/arch_overlay/ext/Xqciac.yaml +++ b/cfgs/qc_iu/arch_overlay/ext/Xqciac.yaml @@ -30,6 +30,19 @@ versions: - Add information about instruction formats of each instruction - Fix description and functionality of qc.shladd instruction requires: { name: Zca, version: ">= 1.0.0" } +- version: "0.3.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com + changes: + - Fix description and functionality of qc.shladd instruction + requires: { name: Zca, version: ">= 1.0.0" } description: | The Xqciac extension includes three instructions to accelerate common address calculations. diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqcibm.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqcibm.yaml index 61ffca3b02..1f64d90b03 100644 --- a/cfgs/qc_iu/arch_overlay/ext/Xqcibm.yaml +++ b/cfgs/qc_iu/arch_overlay/ext/Xqcibm.yaml @@ -30,6 +30,19 @@ versions: - Add information about instruction formats of each instruction - Fix description and functionality of qc.c.extu instruction requires: { name: Zca, version: ">= 1.0.0" } +- version: "0.3.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com + changes: + - Fix description and functionality of qc.c.extu instruction + requires: { name: Zca, version: ">= 1.0.0" } description: | The Xqcibm extension includes thirty eight instructions that perform bit manipulation, include insertion and extraction. diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqciint.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqciint.yaml index aa00848cb8..89617e7202 100644 --- a/cfgs/qc_iu/arch_overlay/ext/Xqciint.yaml +++ b/cfgs/qc_iu/arch_overlay/ext/Xqciint.yaml @@ -29,6 +29,20 @@ versions: changes: - Add information about instruction formats of each instruction requires: { name: Zca, version: ">= 1.0.0" } +- version: "0.3.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com + changes: + - Fix description of qc.mclici* CSRs to reflect being part of Xqciint custom extension + - Fix description of qc.setinti and qc.clrinti instructions + requires: { name: Zca, version: ">= 1.0.0" } description: | The Xqciint extension includes eleven instructions to accelerate interrupt servicing by performing common actions during ISR prologue/epilogue. diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqcilsm.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqcilsm.yaml index dd853b48c4..9a97f0ed6e 100644 --- a/cfgs/qc_iu/arch_overlay/ext/Xqcilsm.yaml +++ b/cfgs/qc_iu/arch_overlay/ext/Xqcilsm.yaml @@ -28,6 +28,18 @@ versions: email: dhower@qti.qualcomm.com changes: - Add information about instruction formats of each instruction +- version: "0.3.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com + changes: + - Fix description of qc.swmi, qc.lwmi and qc.setwmi instructions description: | The Xqcilsm extension includes six instructions that transfer multiple values between registers and memory. diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.clrinti.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.clrinti.yaml index e70fcc8cf9..96238d5217 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.clrinti.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.clrinti.yaml @@ -6,7 +6,7 @@ name: qc.clrinti long_name: Clear interrupt (Immediate) description: | Clear interrupt, interrupt number is in `imm` (0 - 1023). - Instruction encoded in I instruction format. + Instruction encoded in R instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lwmi.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lwmi.yaml index 2fbc7ef37d..efb6d76a48 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lwmi.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.lwmi.yaml @@ -7,7 +7,7 @@ long_name: Load word multiple (Immediate) description: | Loads multiple words starting from address (`rs1` + `imm`) to registers, starting from `rd`. The number of words is in the `length` immediate. - Instruction encoded in I instruction format. + Instruction encoded in R instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.norm.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.norm.yaml index 8fe5c096ce..8d25c140eb 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.norm.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.norm.yaml @@ -33,6 +33,6 @@ access: operation(): | XReg clz = (xlen() - 1) - $signed(highest_set_bit(X[rs1])); XReg clo = (xlen() - 1) - $signed(highest_set_bit(~X[rs1])); - XReg exp = (X[rs1][31] == 1) ? (X[rs1] << (clo - 1)) : (X[rs1] << (clz - 1)); - XReg mnt = (X[rs1][31] == 1) ? (-(clo - 1)) : (-(clz - 1)); + XReg mnt = (X[rs1][31] == 1) ? (X[rs1] << (clo - 1)) : (X[rs1] << (clz - 1)); + XReg exp = (X[rs1][31] == 1) ? (-(clo - 1)) : (-(clz - 1)); X[rd] = {mnt[23:0],exp[7:0]}; diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.normeu.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.normeu.yaml index ed1192add6..aed59d633a 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.normeu.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.normeu.yaml @@ -32,6 +32,6 @@ access: vu: always operation(): | XReg clz = ((xlen() - 1) - $signed(highest_set_bit(X[rs1]))) & ~1; - XReg exp = (X[rs1] << clz); - XReg mnt = (-clz); + XReg mnt = (X[rs1] << (clz & ~1)); + XReg exp = ((-clz) & ~1); X[rd] = {mnt[23:0],exp[7:0]}; diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.normu.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.normu.yaml index ff9b5b5690..18e5ef70c9 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.normu.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.normu.yaml @@ -32,6 +32,6 @@ access: vu: always operation(): | XReg clz = (xlen() - 1) - $signed(highest_set_bit(X[rs1])); - XReg exp = (X[rs1] << clz); - XReg mnt = (-clz); + XReg mnt = (X[rs1] << clz); + XReg exp = (-clz); X[rd] = {mnt[23:0],exp[7:0]}; diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.setinti.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.setinti.yaml index a620f66043..241f4ddbc1 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.setinti.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.setinti.yaml @@ -6,7 +6,7 @@ name: qc.setinti long_name: Set interrupt (Immediate) description: | Set interrupt, interrupt number is in `imm` (0 - 1023). - Instruction encoded in I instruction format. + Instruction encoded in R instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.setwmi.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.setwmi.yaml index 750c3fd251..37afc0393e 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.setwmi.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.setwmi.yaml @@ -7,7 +7,7 @@ long_name: Set word multiple (Immediate) description: | Stores the value of `rs3` multiple times into the address starting at (`rs1` + `imm`). The number of writes is in length. - Instruction encoded in I instruction format. + Instruction encoded in R instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.shladd.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.shladd.yaml index 026f521f44..0b54322c27 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.shladd.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.shladd.yaml @@ -28,7 +28,7 @@ encoding: - name: rd location: 11-7 not: 0 -assembly: " xs1, xs2, shamt" +assembly: " xd, xs1, xs2, shamt" access: s: always u: always diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.swmi.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.swmi.yaml index bdbaca6452..b7dbc428cd 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.swmi.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.swmi.yaml @@ -7,7 +7,7 @@ long_name: Store word multiple (immediate) description: | Stores multiple words from the registers starting at `rs3` to the address starting at (`rs1` + `imm`). The number of words is in `length` immediate. - Instruction encoded in I instruction format. + Instruction encoded in R instruction format. definedBy: anyOf: - Xqci diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.wrapi.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.wrapi.yaml index e35eb20470..8d4949afce 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.wrapi.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.wrapi.yaml @@ -3,12 +3,13 @@ $schema: inst_schema.json# kind: instruction name: qc.wrapi -long_name: Wraparound (Immediate) +long_name: Wraparound (Unsigned Immediate) description: | If `rs1` >= `imm` perform subtraction between `rs1` and `imm`. If `rs1` < 0, perform addition between `rs1` and `imm`, else, select `rs1`. The result is stored in `rd`. Instruction encoded in I instruction format. + The `imm` is an unsigned immediate. definedBy: anyOf: - Xqci @@ -33,8 +34,8 @@ access: vu: always operation(): | XReg rs1_value = X[rs1]; - X[rd] = ($signed(rs1_value) >= $signed(imm)) + X[rd] = ($signed(rs1_value) >= imm) ? rs1_value - imm : (($signed(rs1_value) < 0) - ? (rs1_value + imm) + ? ($signed(rs1_value) + imm) : rs1_value); diff --git a/cfgs/qc_iu/cfg.yaml b/cfgs/qc_iu/cfg.yaml index 3e26c94455..a28bdd53a7 100644 --- a/cfgs/qc_iu/cfg.yaml +++ b/cfgs/qc_iu/cfg.yaml @@ -8,6 +8,6 @@ description: Configuration with the Xqci custom extension. mandatory_extensions: - { name: Sm } - { name: I } - - { name: Xqci, version: "~> 0.4" } + - { name: Xqci, version: "~> 0.5" } params: XLEN: 32 From 7d8a70c2f15d46add0f38d95989a3587664773d2 Mon Sep 17 00:00:00 2001 From: Albert Yosher Date: Tue, 7 Jan 2025 11:40:09 +0200 Subject: [PATCH 08/11] Fix name of instructions qc.c.muladdi -> qc.c.muliadd, qc.muladdi -> qc.muliadd Signed-off-by: Albert Yosher --- cfgs/qc_iu/arch_overlay/ext/Xqciac.yaml | 1 + .../inst/Xqci/{qc.c.muladdi.yaml => qc.c.muliadd.yaml} | 2 +- .../arch_overlay/inst/Xqci/{qc.muladdi.yaml => qc.muliadd.yaml} | 2 +- 3 files changed, 3 insertions(+), 2 deletions(-) rename cfgs/qc_iu/arch_overlay/inst/Xqci/{qc.c.muladdi.yaml => qc.c.muliadd.yaml} (97%) rename cfgs/qc_iu/arch_overlay/inst/Xqci/{qc.muladdi.yaml => qc.muliadd.yaml} (97%) diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqciac.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqciac.yaml index 698def9ba1..f1c0791a16 100644 --- a/cfgs/qc_iu/arch_overlay/ext/Xqciac.yaml +++ b/cfgs/qc_iu/arch_overlay/ext/Xqciac.yaml @@ -42,6 +42,7 @@ versions: email: dhower@qti.qualcomm.com changes: - Fix description and functionality of qc.shladd instruction + - Renaming instructions qc.muladdi to qc.muliadd and qc.c.muladdi to qc.c.muliadd requires: { name: Zca, version: ">= 1.0.0" } description: | The Xqciac extension includes three instructions to accelerate common diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.muladdi.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.muliadd.yaml similarity index 97% rename from cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.muladdi.yaml rename to cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.muliadd.yaml index 32b847c805..da1af4692a 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.muladdi.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.muliadd.yaml @@ -2,7 +2,7 @@ $schema: inst_schema.json# kind: instruction -name: qc.c.muladdi +name: qc.c.muliadd long_name: Multiply and accumulate (Immediate) description: | Increments `rd` by the multiplication of `rs1` and an unsigned immediate diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.muladdi.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.muliadd.yaml similarity index 97% rename from cfgs/qc_iu/arch_overlay/inst/Xqci/qc.muladdi.yaml rename to cfgs/qc_iu/arch_overlay/inst/Xqci/qc.muliadd.yaml index 4c92acdf23..3815398b77 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.muladdi.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.muliadd.yaml @@ -2,7 +2,7 @@ $schema: inst_schema.json# kind: instruction -name: qc.muladdi +name: qc.muliadd long_name: Multiply and accumulate (Immediate) description: | Increments `rd` by the multiplication of `rs1` and a signed immediate `imm`. From d18140a49aa5c7fcc2f57f7f91f293ebed488e79 Mon Sep 17 00:00:00 2001 From: Albert Yosher Date: Wed, 8 Jan 2025 22:29:24 +0200 Subject: [PATCH 09/11] Xqci extension: add Xqciio and Xqcisim sub-extensions, initial spec addition Signed-off-by: Albert Yosher --- cfgs/qc_iu/arch_overlay/ext/Xqci.yaml | 4 +++ cfgs/qc_iu/arch_overlay/ext/Xqciio.yaml | 27 ++++++++++++++ cfgs/qc_iu/arch_overlay/ext/Xqcisim.yaml | 28 +++++++++++++++ .../arch_overlay/inst/Xqci/qc.c.ptrace.yaml | 28 +++++++++++++++ cfgs/qc_iu/arch_overlay/inst/Xqci/qc.inw.yaml | 35 +++++++++++++++++++ .../qc_iu/arch_overlay/inst/Xqci/qc.outw.yaml | 35 +++++++++++++++++++ .../arch_overlay/inst/Xqci/qc.pcoredump.yaml | 29 +++++++++++++++ .../arch_overlay/inst/Xqci/qc.pexit.yaml | 30 ++++++++++++++++ .../arch_overlay/inst/Xqci/qc.ppreg.yaml | 30 ++++++++++++++++ .../arch_overlay/inst/Xqci/qc.ppregs.yaml | 28 +++++++++++++++ .../arch_overlay/inst/Xqci/qc.pputc.yaml | 30 ++++++++++++++++ .../arch_overlay/inst/Xqci/qc.pputci.yaml | 30 ++++++++++++++++ .../arch_overlay/inst/Xqci/qc.pputs.yaml | 31 ++++++++++++++++ .../arch_overlay/inst/Xqci/qc.psyscall.yaml | 31 ++++++++++++++++ .../arch_overlay/inst/Xqci/qc.psyscalli.yaml | 31 ++++++++++++++++ cfgs/qc_iu/arch_overlay/isa/globals.isa | 26 ++++++++++++++ 16 files changed, 453 insertions(+) create mode 100644 cfgs/qc_iu/arch_overlay/ext/Xqciio.yaml create mode 100644 cfgs/qc_iu/arch_overlay/ext/Xqcisim.yaml create mode 100644 cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.ptrace.yaml create mode 100644 cfgs/qc_iu/arch_overlay/inst/Xqci/qc.inw.yaml create mode 100644 cfgs/qc_iu/arch_overlay/inst/Xqci/qc.outw.yaml create mode 100644 cfgs/qc_iu/arch_overlay/inst/Xqci/qc.pcoredump.yaml create mode 100644 cfgs/qc_iu/arch_overlay/inst/Xqci/qc.pexit.yaml create mode 100644 cfgs/qc_iu/arch_overlay/inst/Xqci/qc.ppreg.yaml create mode 100644 cfgs/qc_iu/arch_overlay/inst/Xqci/qc.ppregs.yaml create mode 100644 cfgs/qc_iu/arch_overlay/inst/Xqci/qc.pputc.yaml create mode 100644 cfgs/qc_iu/arch_overlay/inst/Xqci/qc.pputci.yaml create mode 100644 cfgs/qc_iu/arch_overlay/inst/Xqci/qc.pputs.yaml create mode 100644 cfgs/qc_iu/arch_overlay/inst/Xqci/qc.psyscall.yaml create mode 100644 cfgs/qc_iu/arch_overlay/inst/Xqci/qc.psyscalli.yaml diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqci.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqci.yaml index 384f714be8..4fa8192815 100644 --- a/cfgs/qc_iu/arch_overlay/ext/Xqci.yaml +++ b/cfgs/qc_iu/arch_overlay/ext/Xqci.yaml @@ -103,6 +103,8 @@ versions: company: Qualcomm Technologies, Inc. email: dhower@qti.qualcomm.com changes: + - Added Xqciio sub-extension + - Added Xqcisim sub-extension - Fix description of qc.shladd instruction - Fix description and functionality of qc.c.extu instruction - Fix description and functionality of qc.wrapi instruction @@ -119,11 +121,13 @@ versions: - [Xqcics, "0.2.0"] - [Xqcicsr, "0.2.0"] - [Xqciint, "0.3.0"] + - [Xqciio, "0.1.0"] - [Xqcilb, "0.2.0"] - [Xqcili, "0.2.0"] - [Xqcilia, "0.2.0"] - [Xqcilo, "0.2.0"] - [Xqcilsm, "0.3.0"] + - [Xqcisim, "0.1.0"] - [Xqcisls, "0.2.0"] requires: name: Zca diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqciio.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqciio.yaml new file mode 100644 index 0000000000..7546a1e02c --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/ext/Xqciio.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../../schemas/ext_schema.json + +$schema: ext_schema.json# +kind: extension +name: Xqciio +type: privileged +long_name: Qualcomm Input/Output device support +versions: +- version: "0.1.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com +description: | + The Xqciio extension includes two instructions to access external non-memory-mapped devices for input and output + +doc_license: + name: Creative Commons Attribution 4.0 International License + url: https://creativecommons.org/licenses/by/4.0/ +company: + name: Qualcomm Technologies, Inc. + url: https://qualcomm.com diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqcisim.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqcisim.yaml new file mode 100644 index 0000000000..da15d48925 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/ext/Xqcisim.yaml @@ -0,0 +1,28 @@ +# yaml-language-server: $schema=../../../../schemas/ext_schema.json + +$schema: ext_schema.json# +kind: extension +name: Xqcisim +type: unprivileged +long_name: Qualcomm simulator support hints +versions: +- version: "0.1.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com +description: | + The Xqcisim extension includes ten hint instructions to interface simulation environment. + On real target any instruction from this extension executed as "no-operation" and have no effect. + +doc_license: + name: Creative Commons Attribution 4.0 International License + url: https://creativecommons.org/licenses/by/4.0/ +company: + name: Qualcomm Technologies, Inc. + url: https://qualcomm.com diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.ptrace.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.ptrace.yaml new file mode 100644 index 0000000000..58363c5180 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.ptrace.yaml @@ -0,0 +1,28 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.c.ptrace +long_name: Tracing pseudo-instruction (hint) working only in simulation environment +description: | + The tracing instruction have no explicit arguments. + Implicit arguments defined by simulation environment implementation. + Instruction is used to signal simulator to collect some tracing information. + Instruction encoded in CI instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisim +assembly: "" +base: 32 +encoding: + match: "0000000000000010" +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg func = 9; + XReg arg = 0; + iss_syscall(func,arg); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.inw.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.inw.yaml new file mode 100644 index 0000000000..f782005207 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.inw.yaml @@ -0,0 +1,35 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.inw +long_name: Input word from non-memory-mapped device +description: | + Input 32 bits of data into register `rd` from a non-memory-mapped device. + Such devices have own address space, unrelated to memory map. + Device space address formed by adding `rs1` to to a unsigned offset `imm`. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqciio +assembly: xd, imm(xs1) +base: 32 +encoding: + match: -----------------101-----0001011 + variables: + - name: imm + location: 31-20 + left_shift: 2 + - name: rs1 + location: 19-15 + - name: rd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg device_address = X[rs1] + imm; + X[rd] = read_device<32>(device_address); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.outw.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.outw.yaml new file mode 100644 index 0000000000..aab60cca76 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.outw.yaml @@ -0,0 +1,35 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.outw +long_name: Output word to non-memory-mapped device +description: | + Output 32 bits of data from register `rs2` to a non-memory-mapped device. + Such devices have own address space, unrelated to memory map. + Device space address formed by adding `rs1` to to a unsigned offset `imm`. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqciio +assembly: xs2, imm(xs1) +base: 32 +encoding: + match: -----------------100-----0001011 + variables: + - name: imm + location: 31-20 + left_shift: 2 + - name: rs1 + location: 19-15 + - name: rs2 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg device_address = X[rs1] + imm; + write_device<32>(device_address, X[rs2]); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.pcoredump.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.pcoredump.yaml new file mode 100644 index 0000000000..32235017e0 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.pcoredump.yaml @@ -0,0 +1,29 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.pcoredump +long_name: Print core dump pseudo-instruction (hint) working only in simulation environment +description: | + The print core dump instruction calls simulation environment with no explicit arguments. + Implicit arguments are all general purpose registers and CSRs. + Simulation environment expected to print the core dump on its console or standard output. + The core dump format and content are defined by simulation environment. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisim +assembly: "" +base: 32 +encoding: + match: "01100000000000000010000000010011" +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg func = 8; + XReg arg = 0; + iss_syscall(func,arg); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.pexit.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.pexit.yaml new file mode 100644 index 0000000000..ab737086b9 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.pexit.yaml @@ -0,0 +1,30 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.pexit +long_name: Exit call with register argument pseudo-instruction (hint) working only in simulation environment +description: | + The Exit call instruction calls simulation environment with unsigned `rs1` explicit argument. + Simulation environment is expected to complete its execution and return to the system with exit code provided in `rs1`. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisim +assembly: " xs1" +base: 32 +encoding: + match: 101100000000-----010000000010011 + variables: + - name: rs1 + location: 19-15 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg func = 12; + XReg arg = X[rs1]; + iss_syscall(func,arg); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.ppreg.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.ppreg.yaml new file mode 100644 index 0000000000..e34c63720d --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.ppreg.yaml @@ -0,0 +1,30 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.ppreg +long_name: Print register pseudo-instruction (hint) working only in simulation environment +description: | + The print register instruction calls simulation environment with `rs1` explicit argument. + Simulation environment expected to print the register value on its console or standard output. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisim +assembly: " xs1" +base: 32 +encoding: + match: 100000000000-----010000000010011 + variables: + - name: rs1 + location: 19-15 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg func = 2; + XReg arg = X[rs1]; + iss_syscall(func,arg); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.ppregs.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.ppregs.yaml new file mode 100644 index 0000000000..c6cc98f6f4 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.ppregs.yaml @@ -0,0 +1,28 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.ppregs +long_name: Print all registers pseudo-instruction (hint) working only in simulation environment +description: | + The print registers instruction calls simulation environment with no explicit arguments. + Implicit arguments are all general purpose registers. + Simulation environment expected to print the all registers value on its console or standard output. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisim +assembly: "" +base: 32 +encoding: + match: "01110000000000000010000000010011" +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg func = 3; + XReg arg = 0; + iss_syscall(func,arg); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.pputc.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.pputc.yaml new file mode 100644 index 0000000000..1fe99fb415 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.pputc.yaml @@ -0,0 +1,30 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.pputc +long_name: Print character passed in register argument pseudo-instruction (hint) working only in simulation environment +description: | + The print character instruction calls simulation environment with `rs1` explicit argument. + Simulation environment expected to print the character on its console or standard output. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisim +assembly: " xs1" +base: 32 +encoding: + match: 100100000000-----010000000010011 + variables: + - name: rs1 + location: 19-15 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg func = 4; + XReg arg = X[rs1]; + iss_syscall(func,arg); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.pputci.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.pputci.yaml new file mode 100644 index 0000000000..3dc97c52d3 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.pputci.yaml @@ -0,0 +1,30 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.pputci +long_name: Print character passed in the immediate argument pseudo-instruction (hint) working only in simulation environment +description: | + The print character instruction calls simulation environment with unsigned `imm` explicit argument. + Simulation environment expected to print the 8-bit character on its console or standard output. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisim +assembly: " imm" +base: 32 +encoding: + match: 0100--------00000010000000010011 + variables: + - name: imm + location: 29-20 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg func = 5; + XReg arg = imm; + iss_syscall(func,arg); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.pputs.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.pputs.yaml new file mode 100644 index 0000000000..9cba2dbd37 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.pputs.yaml @@ -0,0 +1,31 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.pputs +long_name: Print string pseudo-instruction (hint) working only in simulation environment +description: | + The print string instruction calls simulation environment with `rs1` explicit argument. + The argument assumed to be pointer to the string in target simulated memory. + Simulation environment expected to print the string on its console or standard output. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisim +assembly: " xs1" +base: 32 +encoding: + match: 101000000000-----010000000010011 + variables: + - name: rs1 + location: 19-15 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg func = 6; + XReg arg = X[rs1]; + iss_syscall(func,arg); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.psyscall.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.psyscall.yaml new file mode 100644 index 0000000000..ce78769508 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.psyscall.yaml @@ -0,0 +1,31 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.psyscall +long_name: System call with register argument pseudo-instruction (hint) working only in simulation environment +description: | + The System call instruction calls simulation environment with unsigned `rs1` explicit argument. + Additional implicit arguments defined by simulation environment implementation. + Instruction is used to call simulator to execute function according to the argument. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisim +assembly: " xs1" +base: 32 +encoding: + match: 110000000000-----010000000010011 + variables: + - name: rs1 + location: 19-15 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg func = 10; + XReg arg = X[rs1]; + iss_syscall(func,arg); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.psyscalli.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.psyscalli.yaml new file mode 100644 index 0000000000..2ad8ba4453 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.psyscalli.yaml @@ -0,0 +1,31 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.psyscalli +long_name: System call with immediate argument pseudo-instruction (hint) working only in simulation environment +description: | + The System call instruction calls simulation environment with unsigned `imm` explicit argument. + Additional implicit arguments defined by simulation environment implementation. + Instruction is used to call simulator to execute function according to the argument. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisim +assembly: " imm" +base: 32 +encoding: + match: 00----------00000010000000010011 + variables: + - name: imm + location: 29-20 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg func = 11; + XReg arg = imm; + iss_syscall(func,arg); diff --git a/cfgs/qc_iu/arch_overlay/isa/globals.isa b/cfgs/qc_iu/arch_overlay/isa/globals.isa index 5d363ac0c4..3f815b0d8f 100644 --- a/cfgs/qc_iu/arch_overlay/isa/globals.isa +++ b/cfgs/qc_iu/arch_overlay/isa/globals.isa @@ -8,3 +8,29 @@ builtin function delay { Delay the processor by +cycles+ cycles. } } + +builtin function iss_syscall { + arguments XReg id, XReg arg + description { + Instruction set simulator system call. + } +} + +builtin function read_device { + template U32 len + returns Bits + arguments XReg dev_addr + description { + Read from non-memory-mapped device. + Such devices have own addresses not related to memory map. + } +} + +builtin function write_device { + template U32 len + arguments XReg dev_addr, Bits value + description { + Write to non-memory-mapped device. + Such devices have own addresses not related to memory map. + } +} From 28f2377f0ada7de4ceea2e22b0de3316d90ca7fe Mon Sep 17 00:00:00 2001 From: Albert Yosher Date: Thu, 9 Jan 2025 18:52:48 +0200 Subject: [PATCH 10/11] Xqci extension: adding Xqcisync extension (sync with non-memory-mapped devices and delay) Signed-off-by: Albert Yosher --- cfgs/qc_iu/arch_overlay/ext/Xqci.yaml | 2 + cfgs/qc_iu/arch_overlay/ext/Xqcisync.yaml | 28 ++++++++++++ .../arch_overlay/inst/Xqci/qc.c.delay.yaml | 27 ++++++++++++ .../arch_overlay/inst/Xqci/qc.c.sync.yaml | 43 +++++++++++++++++++ .../arch_overlay/inst/Xqci/qc.c.syncr.yaml | 43 +++++++++++++++++++ .../arch_overlay/inst/Xqci/qc.c.syncwf.yaml | 43 +++++++++++++++++++ .../arch_overlay/inst/Xqci/qc.c.syncwl.yaml | 43 +++++++++++++++++++ .../qc_iu/arch_overlay/inst/Xqci/qc.sync.yaml | 31 +++++++++++++ .../arch_overlay/inst/Xqci/qc.syncr.yaml | 31 +++++++++++++ .../arch_overlay/inst/Xqci/qc.syncwf.yaml | 31 +++++++++++++ .../arch_overlay/inst/Xqci/qc.syncwl.yaml | 31 +++++++++++++ cfgs/qc_iu/arch_overlay/isa/globals.isa | 22 ++++++++++ 12 files changed, 375 insertions(+) create mode 100644 cfgs/qc_iu/arch_overlay/ext/Xqcisync.yaml create mode 100644 cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.delay.yaml create mode 100644 cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.sync.yaml create mode 100644 cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.syncr.yaml create mode 100644 cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.syncwf.yaml create mode 100644 cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.syncwl.yaml create mode 100644 cfgs/qc_iu/arch_overlay/inst/Xqci/qc.sync.yaml create mode 100644 cfgs/qc_iu/arch_overlay/inst/Xqci/qc.syncr.yaml create mode 100644 cfgs/qc_iu/arch_overlay/inst/Xqci/qc.syncwf.yaml create mode 100644 cfgs/qc_iu/arch_overlay/inst/Xqci/qc.syncwl.yaml diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqci.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqci.yaml index 4fa8192815..5be2cfc144 100644 --- a/cfgs/qc_iu/arch_overlay/ext/Xqci.yaml +++ b/cfgs/qc_iu/arch_overlay/ext/Xqci.yaml @@ -105,6 +105,7 @@ versions: changes: - Added Xqciio sub-extension - Added Xqcisim sub-extension + - Added Xqcisync sub-extension - Fix description of qc.shladd instruction - Fix description and functionality of qc.c.extu instruction - Fix description and functionality of qc.wrapi instruction @@ -129,6 +130,7 @@ versions: - [Xqcilsm, "0.3.0"] - [Xqcisim, "0.1.0"] - [Xqcisls, "0.2.0"] + - [Xqcisync, "0.1.0"] requires: name: Zca version: ">= 1.0.0" diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqcisync.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqcisync.yaml new file mode 100644 index 0000000000..832dbbc004 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/ext/Xqcisync.yaml @@ -0,0 +1,28 @@ +# yaml-language-server: $schema=../../../../schemas/ext_schema.json + +$schema: ext_schema.json# +kind: extension +name: Xqcisync +type: unprivileged +long_name: Qualcomm non-memory-mapped devices synchronization and delay +versions: +- version: "0.1.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com +description: | + The Xqcisync extension includes nine instructions, eight for non-memory-mapped devices synchronization and delay instruction. + Synchronization instructions are kind of IO fences that work with special devices synchronization signals. + +doc_license: + name: Creative Commons Attribution 4.0 International License + url: https://creativecommons.org/licenses/by/4.0/ +company: + name: Qualcomm Technologies, Inc. + url: https://qualcomm.com diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.delay.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.delay.yaml new file mode 100644 index 0000000000..32d2a8479a --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.delay.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.c.delay +long_name: Delay execution for immediate amount of cycles +description: | + Delay execution for amount of cycles provided as immediate argument + Instruction encoded in CI instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisync +assembly: "" +base: 32 +encoding: + match: "000000000-----10" + variables: + - name: imm + location: 6-2 +access: + s: always + u: always + vs: always + vu: always +operation(): | + delay(imm); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.sync.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.sync.yaml new file mode 100644 index 0000000000..69bc4fd8b9 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.sync.yaml @@ -0,0 +1,43 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.c.sync +long_name: Non-memory-mapped device read-after-write synchronization to completion +description: | + This synchronization instruction delays execution till last read (input) + from non-memory-mapped device transactions are completed for specified devices. + As well, instruction implies fence.tso functionality for all memory accesses. + Immediate argument is 3-bit encoding of 5-bit bitmask field + that specifies up to five pre-defined devices. + Values of bitmask encoding supported: 0,1,2,4,8,16,15,31 + Instruction encoded in CB instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisync +assembly: " slist" +base: 32 +encoding: + match: "100000---0000001" + variables: + - name: slist + location: 9-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + Bits<5> bitmask; + if (slist == 0) { + bitmask = 0; + } else if (slist < 6) { + XReg shift = slist - 1; + bitmask = (1 << shift); + } else { + XReg shift = slist - 2; + bitmask = (1 << shift) - 1; + } + fence_tso(); + sync_read_after_write_device(true,bitmask); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.syncr.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.syncr.yaml new file mode 100644 index 0000000000..1a50be78bb --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.syncr.yaml @@ -0,0 +1,43 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.c.syncr +long_name: Non-memory-mapped device read-after-write synchronization +description: | + This synchronization instruction delays execution till last read (input) + from non-memory-mapped device transactions are started for specified devices. + As well, instruction implies fence.tso functionality for all memory accesses. + Immediate argument is 3-bit encoding of 5-bit bitmask field + that specifies up to five pre-defined devices. + Values of bitmask encoding supported: 0,1,2,4,8,16,15,31 + Instruction encoded in CB instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisync +assembly: " slist" +base: 32 +encoding: + match: "100001---0000001" + variables: + - name: slist + location: 9-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + Bits<5> bitmask; + if (slist == 0) { + bitmask = 0; + } else if (slist < 6) { + XReg shift = slist - 1; + bitmask = (1 << shift); + } else { + XReg shift = slist - 2; + bitmask = (1 << shift) - 1; + } + fence_tso(); + sync_read_after_write_device(false,bitmask); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.syncwf.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.syncwf.yaml new file mode 100644 index 0000000000..b6da8a8b2c --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.syncwf.yaml @@ -0,0 +1,43 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.c.syncwf +long_name: Non-memory-mapped device write-after-read synchronization +description: | + This synchronization instruction delays execution till last write (output) + to non-memory-mapped device transactions are started for specified devices. + As well, instruction implies fence.tso functionality for all memory accesses. + Immediate argument is 3-bit encoding of 5-bit bitmask field + that specifies up to five pre-defined devices. + Values of bitmask encoding supported: 0,1,2,4,8,16,15,31 + Instruction encoded in CB instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisync +assembly: " slist" +base: 32 +encoding: + match: "100100---0000001" + variables: + - name: slist + location: 9-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + Bits<5> bitmask; + if (slist == 0) { + bitmask = 0; + } else if (slist < 6) { + XReg shift = slist - 1; + bitmask = (1 << shift); + } else { + XReg shift = slist - 2; + bitmask = (1 << shift) - 1; + } + fence_tso(); + sync_write_after_read_device(false,bitmask); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.syncwl.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.syncwl.yaml new file mode 100644 index 0000000000..4462e593b1 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.syncwl.yaml @@ -0,0 +1,43 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.c.syncwl +long_name: Non-memory-mapped device write-after-read synchronization to completion +description: | + This synchronization instruction delays execution till last write (output) + to non-memory-mapped device transactions are completed for specified devices. + As well, instruction implies fence.tso functionality for all memory accesses. + Immediate argument is 3-bit encoding of 5-bit bitmask field + that specifies up to five pre-defined devices. + Values of bitmask encoding supported: 0,1,2,4,8,16,15,31 + Instruction encoded in CB instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisync +assembly: " slist" +base: 32 +encoding: + match: "100101---0000001" + variables: + - name: slist + location: 9-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + Bits<5> bitmask; + if (slist == 0) { + bitmask = 0; + } else if (slist < 6) { + XReg shift = slist - 1; + bitmask = (1 << shift); + } else { + XReg shift = slist - 2; + bitmask = (1 << shift) - 1; + } + fence_tso(); + sync_write_after_read_device(true,bitmask); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.sync.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.sync.yaml new file mode 100644 index 0000000000..b1b4723c61 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.sync.yaml @@ -0,0 +1,31 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.sync +long_name: Non-memory-mapped device read-after-write synchronization to completion +description: | + This synchronization instruction delays execution till last read (input) + from non-memory-mapped device transactions are completed for specified devices. + As well, instruction implies fence.tso functionality for all memory accesses. + Immediate argument is 5-bit bitmask field that specifies up to five pre-defined devices. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisync +assembly: " imm" +base: 32 +encoding: + match: 0001000-----00000011000000010011 + variables: + - name: imm + location: 24-20 +access: + s: always + u: always + vs: always + vu: always +operation(): | + fence_tso(); + sync_read_after_write_device(true,imm); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.syncr.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.syncr.yaml new file mode 100644 index 0000000000..e94dc14675 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.syncr.yaml @@ -0,0 +1,31 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.syncr +long_name: Non-memory-mapped device read-after-write synchronization +description: | + This synchronization instruction delays execution till last read (input) + from non-memory-mapped device transactions are started for specified devices. + As well, instruction implies fence.tso functionality for all memory accesses. + Immediate argument is 5-bit bitmask field that specifies up to five pre-defined devices. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisync +assembly: " imm" +base: 32 +encoding: + match: 0010000-----00000011000000010011 + variables: + - name: imm + location: 24-20 +access: + s: always + u: always + vs: always + vu: always +operation(): | + fence_tso(); + sync_read_after_write_device(false,imm); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.syncwf.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.syncwf.yaml new file mode 100644 index 0000000000..fc51bd96c6 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.syncwf.yaml @@ -0,0 +1,31 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.syncwf +long_name: Non-memory-mapped device write-after-read synchronization +description: | + This synchronization instruction delays execution till last write (output) + to non-memory-mapped device transactions are started for specified devices. + As well, instruction implies fence.tso functionality for all memory accesses. + Immediate argument is 5-bit bitmask field that specifies up to five pre-defined devices. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisync +assembly: " imm" +base: 32 +encoding: + match: 0100000-----00000011000000010011 + variables: + - name: imm + location: 24-20 +access: + s: always + u: always + vs: always + vu: always +operation(): | + fence_tso(); + sync_write_after_read_device(false,imm); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.syncwl.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.syncwl.yaml new file mode 100644 index 0000000000..b9c486b7e1 --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.syncwl.yaml @@ -0,0 +1,31 @@ +# yaml-language-server: $schema=../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: qc.syncwl +long_name: Non-memory-mapped device write-after-read synchronization to completion +description: | + This synchronization instruction delays execution till last write (output) + to non-memory-mapped device transactions are completed for specified devices. + As well, instruction implies fence.tso functionality for all memory accesses. + Immediate argument is 5-bit bitmask field that specifies up to five pre-defined devices. + Instruction encoded in I instruction format. +definedBy: + anyOf: + - Xqci + - Xqcisync +assembly: " imm" +base: 32 +encoding: + match: 1000000-----00000011000000010011 + variables: + - name: imm + location: 24-20 +access: + s: always + u: always + vs: always + vu: always +operation(): | + fence_tso(); + sync_write_after_read_device(true,imm); diff --git a/cfgs/qc_iu/arch_overlay/isa/globals.isa b/cfgs/qc_iu/arch_overlay/isa/globals.isa index 3f815b0d8f..6566048105 100644 --- a/cfgs/qc_iu/arch_overlay/isa/globals.isa +++ b/cfgs/qc_iu/arch_overlay/isa/globals.isa @@ -34,3 +34,25 @@ builtin function write_device { Such devices have own addresses not related to memory map. } } + +builtin function sync_read_after_write_device { + arguments Boolean completed, Bits<5> device_bitmask + description { + Synchronize non-memory-mapped device read-after-write. + Such devices have own addresses not related to memory map. + Devices specified by device bitmask (up to 5 devices). + Stalls processor till condtions met. + Conditions are that last device output started or completed (depends on argument). + } +} + +builtin function sync_write_after_read_device { + arguments Boolean completed, Bits<5> device_bitmask + description { + Synchronize non-memory-mapped device write-after-read. + Such devices have own addresses not related to memory map. + Devices specified by device bitmask (up to 5 devices). + Stalls processor till condtions met. + Conditions are that last device input started or completed (depends on argument). + } +} From b34b1ad5a21fb2e32c6095eb24fa99b1c94b4676 Mon Sep 17 00:00:00 2001 From: Albert Yosher Date: Thu, 9 Jan 2025 21:28:39 +0200 Subject: [PATCH 11/11] Xqci extension: fix qc.c.mnret and qc.c.mret instructions Signed-off-by: Albert Yosher --- .../arch_overlay/csr/Xqci/qc_mncause.yaml | 65 +++++++++++++++++++ .../arch_overlay/inst/Xqci/qc.c.mnret.yaml | 20 ++++-- .../arch_overlay/inst/Xqci/qc.c.mret.yaml | 5 +- 3 files changed, 82 insertions(+), 8 deletions(-) create mode 100644 cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mncause.yaml diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mncause.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mncause.yaml new file mode 100644 index 0000000000..a92325d86e --- /dev/null +++ b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_mncause.yaml @@ -0,0 +1,65 @@ +$schema: csr_schema.json# +kind: csr +name: qc_mncause +long_name: Machine NMI Cause +address: 0x7c2 +base: 32 +priv_mode: M +length: MXLEN +description: | + Reports the cause of the latest non-maskable interrupt. +definedBy: + anyOf: + - Xqci + - Xqciint +fields: + INT: + type: RW-H + reset_value: 0 + location: 31 + description: Interrupt bit copied from mcause.INT at the moment of NMI + NMI: + type: RW-H + reset_value: 0 + location: 30 + description: If 1'b1, currently processing NMI. + MPP: + type: RW-H + reset_value: 3 + location: 29-28 + description: M-mode Previous Privilege. + MPIE: + type: RW-H + reset_value: 0 + location: 27 + description: M-mode Previous Interrupt Enable. + MIE: + type: RW-H + reset_value: 0 + location: 26 + description: M-mode Interrupt Enable. + EXCP: + type: RW-H + reset_value: 0 + location: 25 + description: Exception Pending Bit. + RESP: + type: RW-H + reset_value: 0 + location: 24 + description: Resume Pending Bit. + MPIL: + type: RW-H + reset_value: 0 + location: 19-16 + description: M-mode Previous Interrupt Level. + MIL: + type: RW-H + reset_value: 15 + location: 15-12 + description: M-mode Interrupt Level. + NMICODE: + type: RW-H + reset_value: 0 + location: 11-0 + description: NMI code ID. diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mnret.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mnret.yaml index 4116c16a06..7c60949b84 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mnret.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mnret.yaml @@ -8,7 +8,10 @@ description: | Returns from an NMI in M-mode. Instruction encoded in CI instruction format. assembly: "" -definedBy: Xqciint +definedBy: + anyOf: + - Xqci + - Xqciint access: s: never u: never @@ -18,15 +21,18 @@ base: 32 encoding: match: "0001100110010010" operation(): | - CSR[mncause].MIE = CSR[mncause].MPIE; - CSR[mncause].MPIE = 1; - if (CSR[mncause].MPP == 2'b00) { + if (implemented?(ExtensionName::S) && CSR[mstatus].MPP != 2'b11) { + CSR[mstatus].MPRV = 0; + } + CSR[mstatus].MIE = CSR[mstatus].MPIE; + CSR[mstatus].MPIE = 1; + if (CSR[mstatus].MPP == 2'b00) { set_mode(PrivilegeMode::U); - } else if (CSR[mncause].MPP == 2'b01) { + } else if (CSR[mstatus].MPP == 2'b01) { set_mode(PrivilegeMode::S); - } else if (CSR[mncause].MPP == 2'b11) { + } else if (CSR[mstatus].MPP == 2'b11) { set_mode(PrivilegeMode::M); } - CSR[mncause].MPP = implemented?(ExtensionName::U) ? 2'b00 : 2'b11; + CSR[mstatus].MPP = implemented?(ExtensionName::U) ? 2'b00 : 2'b11; CSR[mcause].NMI = 0; $pc = CSR[qc_mnepc].sw_read(); diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mret.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mret.yaml index 0e07908d6e..f6221f4b48 100644 --- a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mret.yaml +++ b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mret.yaml @@ -8,7 +8,10 @@ description: | Returns from an exception in M-mode. Instruction encoded in CI instruction format. assembly: "" -definedBy: Xqciint +definedBy: + anyOf: + - Xqci + - Xqciint access: s: never u: never