From 630f39e8732099e77a7e8c44c34f3592caf03bf0 Mon Sep 17 00:00:00 2001 From: syedowaisalishah Date: Sat, 29 Mar 2025 03:43:26 +0000 Subject: [PATCH 01/29] Add Smcsrind and Sscsrind extensions with YAML data --- arch/ext/Smcsrind.yaml | 37 +++++++++++++++++++++++++++++++++++++ arch/ext/Sscsrind.yaml | 38 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 75 insertions(+) create mode 100644 arch/ext/Smcsrind.yaml create mode 100644 arch/ext/Sscsrind.yaml diff --git a/arch/ext/Smcsrind.yaml b/arch/ext/Smcsrind.yaml new file mode 100644 index 0000000000..bd61edc812 --- /dev/null +++ b/arch/ext/Smcsrind.yaml @@ -0,0 +1,37 @@ +# yaml-language-server: $schema=../../schemas/ext_schema.json + +$schema: "ext_schema.json#" +kind: extension +name: Smcsrind +long_name: Machine Indirect CSR Access (Smcsrind) +description: | + The `Smcsrind` extension defines indirect access to CSRs, allowing registers to be accessed through + an index value (`miselect`) rather than using a fixed CSR number. This reduces the need for allocating + large chunks of CSR address space, making it more scalable and flexible. + + `Smcsrind` enables accessing an array of CSRs by index through dedicated `miselect` and `mireg*` registers + for machine-level access. The supervisor-level counterpart, `Sscsrind`, provides similar functionality but + without machine-level CSRs. + + This extension is beneficial for accessing a set of registers that are not statically defined in the CSR space + and enables more flexible register allocation. + + The machine-level registers are accessed through `miselect` and `mireg*` registers, while supervisor-level + registers are accessed through `siselect` and `sireg*` registers. + +versions: + - version: "1.0.0" + state: ratified + ratification_date: "2024-11" + url: "https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-isa-release-482805d-2025-03-25" + implies: + name: Smcsrind + version: "1.0.0" + requires: + allOf: + - name: S + version: ~> 1.13 + changes: + - Introduced indirect CSR access using `miselect`, `mireg*` for machine-level, and `siselect`, `sireg*` for supervisor-level CSRs. + - Defines the address spaces for indirect access in both machine and supervisor levels. + - Supports custom extension registers for each mode via indirect access diff --git a/arch/ext/Sscsrind.yaml b/arch/ext/Sscsrind.yaml new file mode 100644 index 0000000000..d77280609f --- /dev/null +++ b/arch/ext/Sscsrind.yaml @@ -0,0 +1,38 @@ +# yaml-language-server: $schema=../../schemas/ext_schema.json + +$schema: "ext_schema.json#" +kind: extension +name: Sscsrind +long_name: Supervisor Indirect CSR Access (Sscsrind) +description: | + The `Sscsrind` extension extends the CSR access mechanism for Supervisor mode by enabling indirect + access to a set of registers. Similar to `Smcsrind`, this extension allows registers to be accessed through + an index value (`siselect`) instead of using fixed CSR numbers. This flexibility helps manage the CSR space + efficiently and provides a more scalable mechanism for accessing supervisor-level registers. + + `Sscsrind` registers are accessed indirectly via dedicated `siselect` and `sireg*` registers, providing + software with the ability to access an array of registers by index. This extension is essential for handling + large numbers of registers and reduces the need for allocating large chunks of CSR address space for each + individual register. + + While `Smcsrind` applies to machine-level access, `Sscsrind` targets Supervisor-level registers and behaves + similarly, but with the exclusion of machine-level CSRs. + +versions: + - version: "1.0.0" + state: ratified + ratification_date: "2024-11" + url: "https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-isa-release-482805d-2025-03-25" + implies: + name: Sscsrind + version: "1.0.0" + requires: + allOf: + - name: S + version: ~> 1.13 + - name: Smcsrind + version: ~> 1.0 + changes: + - Introduced indirect CSR access for Supervisor-level using `siselect` and `sireg*` registers. + - Enables access to arrays of registers in Supervisor mode, making it more efficient to handle large numbers of registers. + - Supports custom extensions with indirect access for supervisor-level registers. From 3f936d066ed3450d2d72b0029300cc1c46c2a05b Mon Sep 17 00:00:00 2001 From: syedowaisalishah Date: Tue, 1 Apr 2025 02:27:27 +0000 Subject: [PATCH 02/29] Added CSR YAML files for Smcsrind --- arch/csr/Smcsrind/mireg.yaml | 27 +++++++++++++++++++++++++++ arch/csr/Smcsrind/mireg2.yaml | 27 +++++++++++++++++++++++++++ arch/csr/Smcsrind/mireg3.yaml | 27 +++++++++++++++++++++++++++ arch/csr/Smcsrind/mireg4.yaml | 27 +++++++++++++++++++++++++++ arch/csr/Smcsrind/mireg5yaml | 27 +++++++++++++++++++++++++++ arch/csr/Smcsrind/mireg6.yaml | 27 +++++++++++++++++++++++++++ arch/csr/Smcsrind/miselect.yaml | 33 +++++++++++++++++++++++++++++++++ 7 files changed, 195 insertions(+) create mode 100644 arch/csr/Smcsrind/mireg.yaml create mode 100644 arch/csr/Smcsrind/mireg2.yaml create mode 100644 arch/csr/Smcsrind/mireg3.yaml create mode 100644 arch/csr/Smcsrind/mireg4.yaml create mode 100644 arch/csr/Smcsrind/mireg5yaml create mode 100644 arch/csr/Smcsrind/mireg6.yaml create mode 100644 arch/csr/Smcsrind/miselect.yaml diff --git a/arch/csr/Smcsrind/mireg.yaml b/arch/csr/Smcsrind/mireg.yaml new file mode 100644 index 0000000000..6f264bb697 --- /dev/null +++ b/arch/csr/Smcsrind/mireg.yaml @@ -0,0 +1,27 @@ +--- +# yaml-language-server: $schema=../../../schemas/csr_schema.json +$schema: csr_schema.json# +kind: csr +name: mireg +long_name: Machine Indirect Register Alias 1 +address: 0x351 +priv_mode: M +length: MXLEN +definedBy: Smcsrind +description: | + The `mireg` CSR is an alias register for accessing indirect registers that + are selected by the `miselect` CSR. The value of `miselect` determines which + register is accessed during read or write operations. + + The `mireg` CSR is used for indirect access to machine-level registers. + The access to these registers depends on the value in the `miselect` CSR. + + If `miselect` selects this register, the data can be read or written using this CSR. + +fields: + Count: + location_rv32: 31-0 + location_rv64: 63-0 + type: RW + description: Indirect register data selected by `miselect` value. + reset_value(): return 0x0; diff --git a/arch/csr/Smcsrind/mireg2.yaml b/arch/csr/Smcsrind/mireg2.yaml new file mode 100644 index 0000000000..76d29d79dc --- /dev/null +++ b/arch/csr/Smcsrind/mireg2.yaml @@ -0,0 +1,27 @@ +--- +# yaml-language-server: $schema=../../../schemas/csr_schema.json +$schema: csr_schema.json# +kind: csr +name: mireg2 +long_name: Machine Indirect Register Alias 2 +address: 0x352 +priv_mode: M +length: MXLEN +definedBy: Smcsrind +description: | + The `mireg2` CSR is an alias register for accessing indirect registers that + are selected by the `miselect` CSR. The value of `miselect` determines which + register is accessed during read or write operations. + + The `mireg2` CSR is used for indirect access to machine-level registers. + The access to these registers depends on the value in the `miselect` CSR. + + If `miselect` selects this register, the data can be read or written using this CSR. + +fields: + Count: + location_rv32: 31-0 + location_rv64: 63-0 + type: RW + description: Indirect register data selected by `miselect` value. + reset_value(): return 0x0; diff --git a/arch/csr/Smcsrind/mireg3.yaml b/arch/csr/Smcsrind/mireg3.yaml new file mode 100644 index 0000000000..501ba06ee1 --- /dev/null +++ b/arch/csr/Smcsrind/mireg3.yaml @@ -0,0 +1,27 @@ +--- +# yaml-language-server: $schema=../../../schemas/csr_schema.json +$schema: csr_schema.json# +kind: csr +name: mireg3 +long_name: Machine Indirect Register Alias 3 +address: 0x353 +priv_mode: M +length: MXLEN +definedBy: Smcsrind +description: | + The `mireg3` CSR is an alias register for accessing indirect registers that + are selected by the `miselect` CSR. The value of `miselect` determines which + register is accessed during read or write operations. + + The `mireg3` CSR is used for indirect access to machine-level registers. + The access to these registers depends on the value in the `miselect` CSR. + + If `miselect` selects this register, the data can be read or written using this CSR. + +fields: + Count: + location_rv32: 31-0 + location_rv64: 63-0 + type: RW + description: Indirect register data selected by `miselect` value. + reset_value(): return 0x0; diff --git a/arch/csr/Smcsrind/mireg4.yaml b/arch/csr/Smcsrind/mireg4.yaml new file mode 100644 index 0000000000..addd5facc0 --- /dev/null +++ b/arch/csr/Smcsrind/mireg4.yaml @@ -0,0 +1,27 @@ +--- +# yaml-language-server: $schema=../../../schemas/csr_schema.json +$schema: csr_schema.json# +kind: csr +name: mireg4 +long_name: Machine Indirect Register Alias 4 +address: 0x355 +priv_mode: M +length: MXLEN +definedBy: Smcsrind +description: | + The `mireg4` CSR is an alias register for accessing indirect registers that + are selected by the `miselect` CSR. The value of `miselect` determines which + register is accessed during read or write operations. + + The `mireg4` CSR is used for indirect access to machine-level registers. + The access to these registers depends on the value in the `miselect` CSR. + + If `miselect` selects this register, the data can be read or written using this CSR. + +fields: + Count: + location_rv32: 31-0 + location_rv64: 63-0 + type: RW + description: Indirect register data selected by `miselect` value. + reset_value(): return 0x0; diff --git a/arch/csr/Smcsrind/mireg5yaml b/arch/csr/Smcsrind/mireg5yaml new file mode 100644 index 0000000000..5001c06ee3 --- /dev/null +++ b/arch/csr/Smcsrind/mireg5yaml @@ -0,0 +1,27 @@ +--- +# yaml-language-server: $schema=../../../schemas/csr_schema.json +$schema: csr_schema.json# +kind: csr +name: mireg5 +long_name: Machine Indirect Register Alias 5 +address: 0x356 +priv_mode: M +length: MXLEN +definedBy: Smcsrind +description: | + The `mireg5` CSR is an alias register for accessing indirect registers that + are selected by the `miselect` CSR. The value of `miselect` determines which + register is accessed during read or write operations. + + The `mireg5` CSR is used for indirect access to machine-level registers. + The access to these registers depends on the value in the `miselect` CSR. + + If `miselect` selects this register, the data can be read or written using this CSR. + +fields: + Count: + location_rv32: 31-0 + location_rv64: 63-0 + type: RW + description: Indirect register data selected by `miselect` value. + reset_value(): return 0x0; diff --git a/arch/csr/Smcsrind/mireg6.yaml b/arch/csr/Smcsrind/mireg6.yaml new file mode 100644 index 0000000000..acbf686096 --- /dev/null +++ b/arch/csr/Smcsrind/mireg6.yaml @@ -0,0 +1,27 @@ +--- +# yaml-language-server: $schema=../../../schemas/csr_schema.json +$schema: csr_schema.json# +kind: csr +name: mireg6 +long_name: Machine Indirect Register Alias 6 +address: 0x357 +priv_mode: M +length: MXLEN +definedBy: Smcsrind +description: | + The `mireg6` CSR is an alias register for accessing indirect registers that + are selected by the `miselect` CSR. The value of `miselect` determines which + register is accessed during read or write operations. + + The `mireg6` CSR is used for indirect access to machine-level registers. + The access to these registers depends on the value in the `miselect` CSR. + + If `miselect` selects this register, the data can be read or written using this CSR. + +fields: + Count: + location_rv32: 31-0 + location_rv64: 63-0 + type: RW + description: Indirect register data selected by `miselect` value. + reset_value(): return 0x0; diff --git a/arch/csr/Smcsrind/miselect.yaml b/arch/csr/Smcsrind/miselect.yaml new file mode 100644 index 0000000000..d123eef26e --- /dev/null +++ b/arch/csr/Smcsrind/miselect.yaml @@ -0,0 +1,33 @@ +--- +# yaml-language-server: $schema=../../../schemas/csr_schema.json +$schema: csr_schema.json# +kind: csr +name: miselect +long_name: Machine Indirect Register Select +address: 0x350 +priv_mode: M +length: MXLEN +definedBy: Smcsrind +description: | + The `miselect` CSR is a register used to select the indirect registers that + can be accessed using the `mireg*` aliases. The value of this register + determines which indirect register is accessed during read or write operations. + + The values of `miselect` define the indirect registers accessible via + `mireg*`. The valid values are allocated by the extension that implements + indirect access. The most significant bit is reserved for custom usage. + It is recommended that a value of 0 corresponds to a standard set of + indirect register aliases. + + The indirect access mechanism enables a more efficient method to access + registers without needing to reserve large chunks of CSR address space. + Implementations should ensure that accesses to `miselect` with unsupported + values result in an illegal instruction exception. + +fields: + Select Value: + location_rv32: 31-0 + location_rv64: 63-0 + type: RW + description: Selects which indirect register is accessed via `mireg*`. + reset_value(): return 0x0; From 713eed8048b39aa01662b50eb1a3bd008a6749a4 Mon Sep 17 00:00:00 2001 From: syedowaisalishah Date: Thu, 3 Apr 2025 03:33:14 +0000 Subject: [PATCH 03/29] Rename yaml file mireg5.yaml --- arch/csr/Smcsrind/mireg5.yaml | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 arch/csr/Smcsrind/mireg5.yaml diff --git a/arch/csr/Smcsrind/mireg5.yaml b/arch/csr/Smcsrind/mireg5.yaml new file mode 100644 index 0000000000..5001c06ee3 --- /dev/null +++ b/arch/csr/Smcsrind/mireg5.yaml @@ -0,0 +1,27 @@ +--- +# yaml-language-server: $schema=../../../schemas/csr_schema.json +$schema: csr_schema.json# +kind: csr +name: mireg5 +long_name: Machine Indirect Register Alias 5 +address: 0x356 +priv_mode: M +length: MXLEN +definedBy: Smcsrind +description: | + The `mireg5` CSR is an alias register for accessing indirect registers that + are selected by the `miselect` CSR. The value of `miselect` determines which + register is accessed during read or write operations. + + The `mireg5` CSR is used for indirect access to machine-level registers. + The access to these registers depends on the value in the `miselect` CSR. + + If `miselect` selects this register, the data can be read or written using this CSR. + +fields: + Count: + location_rv32: 31-0 + location_rv64: 63-0 + type: RW + description: Indirect register data selected by `miselect` value. + reset_value(): return 0x0; From 42ef4bda10c1d2b808146ef0f9bf00579a1f02cc Mon Sep 17 00:00:00 2001 From: syedowaisalishah Date: Thu, 3 Apr 2025 03:34:42 +0000 Subject: [PATCH 04/29] =?UTF-8?q?Add=20Sscsrind=20CSR=20YAML=20files:=20si?= =?UTF-8?q?select=20and=20sireg1=E2=80=936?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- arch/csr/Smcsrind/mireg5yaml | 27 ---------------------- arch/csr/Smcsrind/sireg.yaml | 36 +++++++++++++++++++++++++++++ arch/csr/Smcsrind/sireg2.yaml | 36 +++++++++++++++++++++++++++++ arch/csr/Smcsrind/sireg3.yaml | 36 +++++++++++++++++++++++++++++ arch/csr/Smcsrind/sireg4.yaml | 36 +++++++++++++++++++++++++++++ arch/csr/Smcsrind/sireg5.yaml | 36 +++++++++++++++++++++++++++++ arch/csr/Smcsrind/sireg6.yaml | 36 +++++++++++++++++++++++++++++ arch/csr/Smcsrind/siselect.yaml | 40 +++++++++++++++++++++++++++++++++ 8 files changed, 256 insertions(+), 27 deletions(-) delete mode 100644 arch/csr/Smcsrind/mireg5yaml create mode 100644 arch/csr/Smcsrind/sireg.yaml create mode 100644 arch/csr/Smcsrind/sireg2.yaml create mode 100644 arch/csr/Smcsrind/sireg3.yaml create mode 100644 arch/csr/Smcsrind/sireg4.yaml create mode 100644 arch/csr/Smcsrind/sireg5.yaml create mode 100644 arch/csr/Smcsrind/sireg6.yaml create mode 100644 arch/csr/Smcsrind/siselect.yaml diff --git a/arch/csr/Smcsrind/mireg5yaml b/arch/csr/Smcsrind/mireg5yaml deleted file mode 100644 index 5001c06ee3..0000000000 --- a/arch/csr/Smcsrind/mireg5yaml +++ /dev/null @@ -1,27 +0,0 @@ ---- -# yaml-language-server: $schema=../../../schemas/csr_schema.json -$schema: csr_schema.json# -kind: csr -name: mireg5 -long_name: Machine Indirect Register Alias 5 -address: 0x356 -priv_mode: M -length: MXLEN -definedBy: Smcsrind -description: | - The `mireg5` CSR is an alias register for accessing indirect registers that - are selected by the `miselect` CSR. The value of `miselect` determines which - register is accessed during read or write operations. - - The `mireg5` CSR is used for indirect access to machine-level registers. - The access to these registers depends on the value in the `miselect` CSR. - - If `miselect` selects this register, the data can be read or written using this CSR. - -fields: - Count: - location_rv32: 31-0 - location_rv64: 63-0 - type: RW - description: Indirect register data selected by `miselect` value. - reset_value(): return 0x0; diff --git a/arch/csr/Smcsrind/sireg.yaml b/arch/csr/Smcsrind/sireg.yaml new file mode 100644 index 0000000000..a1652649d0 --- /dev/null +++ b/arch/csr/Smcsrind/sireg.yaml @@ -0,0 +1,36 @@ +--- +# yaml-language-server: $schema=../../../schemas/csr_schema.json +$schema: csr_schema.json# +kind: csr +name: sireg +long_name: Supervisor Indirect Register Alias +address: 0x151 +priv_mode: S +length: SXLEN +definedBy: Sscsrind +description: | + The `sireg` CSR is a supervisor-level alias register used to access register state + indirectly based on the value held in the `siselect` CSR. The `sireg` CSR provides + access to a window of indirectly addressed registers. + + The behavior of accesses to `sireg` is determined by the currently selected + `siselect` value, which acts as an index into an alias space defined by the extension + utilizing this access method. This indirect mechanism allows software to access + an array of CSRs without consuming large contiguous blocks of the CSR address space. + + When `siselect` contains a value that is not supported, access to `sireg` is UNSPECIFIED, + and implementations are encouraged to raise an illegal instruction exception to aid in + debugging or software emulation. + + The indirect access mechanism is useful for CSR arrays, such as counters or + performance registers, and ensures a scalable way to interact with dynamically + indexed register sets. + +fields: + Data: + location_rv32: 31-0 + location_rv64: 63-0 + type: RW + description: | + The data read from or written to the register selected by the current `siselect` value. + reset_value(): return 0x0; diff --git a/arch/csr/Smcsrind/sireg2.yaml b/arch/csr/Smcsrind/sireg2.yaml new file mode 100644 index 0000000000..44db745469 --- /dev/null +++ b/arch/csr/Smcsrind/sireg2.yaml @@ -0,0 +1,36 @@ +--- +# yaml-language-server: $schema=../../../schemas/csr_schema.json +$schema: csr_schema.json# +kind: csr +name: sireg2 +long_name: Supervisor Indirect Register Alias 2 +address: 0x152 +priv_mode: S +length: SXLEN +definedBy: Sscsrind +description: | + The `sireg2` CSR is a supervisor-level alias register used to access register state + indirectly based on the value held in the `siselect` CSR. The `sireg2` CSR provides + access to a window of indirectly addressed registers. + + The behavior of accesses to `sireg2` is determined by the currently selected + `siselect` value, which acts as an index into an alias space defined by the extension + utilizing this access method. This indirect mechanism allows software to access + an array of CSRs without consuming large contiguous blocks of the CSR address space. + + When `siselect` contains a value that is not supported, access to `sireg2` is UNSPECIFIED, + and implementations are encouraged to raise an illegal instruction exception to aid in + debugging or software emulation. + + The indirect access mechanism is useful for CSR arrays, such as counters or + performance registers, and ensures a scalable way to interact with dynamically + indexed register sets. + +fields: + Data: + location_rv32: 31-0 + location_rv64: 63-0 + type: RW + description: | + The data read from or written to the register selected by the current `siselect` value. + reset_value(): return 0x0; diff --git a/arch/csr/Smcsrind/sireg3.yaml b/arch/csr/Smcsrind/sireg3.yaml new file mode 100644 index 0000000000..84beeaa0ef --- /dev/null +++ b/arch/csr/Smcsrind/sireg3.yaml @@ -0,0 +1,36 @@ +--- +# yaml-language-server: $schema=../../../schemas/csr_schema.json +$schema: csr_schema.json# +kind: csr +name: sireg3 +long_name: Supervisor Indirect Register Alias 3 +address: 0x153 +priv_mode: S +length: SXLEN +definedBy: Sscsrind +description: | + The `sireg3` CSR is a supervisor-level alias register used to access register state + indirectly based on the value held in the `siselect` CSR. The `sireg3` CSR provides + access to a window of indirectly addressed registers. + + The behavior of accesses to `sireg3` is determined by the currently selected + `siselect` value, which acts as an index into an alias space defined by the extension + utilizing this access method. This indirect mechanism allows software to access + an array of CSRs without consuming large contiguous blocks of the CSR address space. + + When `siselect` contains a value that is not supported, access to `sireg3` is UNSPECIFIED, + and implementations are encouraged to raise an illegal instruction exception to aid in + debugging or software emulation. + + The indirect access mechanism is useful for CSR arrays, such as counters or + performance registers, and ensures a scalable way to interact with dynamically + indexed register sets. + +fields: + Data: + location_rv32: 31-0 + location_rv64: 63-0 + type: RW + description: | + The data read from or written to the register selected by the current `siselect` value. + reset_value(): return 0x0; diff --git a/arch/csr/Smcsrind/sireg4.yaml b/arch/csr/Smcsrind/sireg4.yaml new file mode 100644 index 0000000000..91ce3224c2 --- /dev/null +++ b/arch/csr/Smcsrind/sireg4.yaml @@ -0,0 +1,36 @@ +--- +# yaml-language-server: $schema=../../../schemas/csr_schema.json +$schema: csr_schema.json# +kind: csr +name: sireg4 +long_name: Supervisor Indirect Register Alias 4 +address: 0x155 +priv_mode: S +length: SXLEN +definedBy: Sscsrind +description: | + The `sireg4` CSR is a supervisor-level alias register used to access register state + indirectly based on the value held in the `siselect` CSR. The `sireg4` CSR provides + access to a window of indirectly addressed registers. + + The behavior of accesses to `sireg4` is determined by the currently selected + `siselect` value, which acts as an index into an alias space defined by the extension + utilizing this access method. This indirect mechanism allows software to access + an array of CSRs without consuming large contiguous blocks of the CSR address space. + + When `siselect` contains a value that is not supported, access to `sireg4` is UNSPECIFIED, + and implementations are encouraged to raise an illegal instruction exception to aid in + debugging or software emulation. + + The indirect access mechanism is useful for CSR arrays, such as counters or + performance registers, and ensures a scalable way to interact with dynamically + indexed register sets. + +fields: + Data: + location_rv32: 31-0 + location_rv64: 63-0 + type: RW + description: | + The data read from or written to the register selected by the current `siselect` value. + reset_value(): return 0x0; diff --git a/arch/csr/Smcsrind/sireg5.yaml b/arch/csr/Smcsrind/sireg5.yaml new file mode 100644 index 0000000000..c05374639b --- /dev/null +++ b/arch/csr/Smcsrind/sireg5.yaml @@ -0,0 +1,36 @@ +--- +# yaml-language-server: $schema=../../../schemas/csr_schema.json +$schema: csr_schema.json# +kind: csr +name: sireg5 +long_name: Supervisor Indirect Register Alias 5 +address: 0x156 +priv_mode: S +length: SXLEN +definedBy: Sscsrind +description: | + The `sireg5` CSR is a supervisor-level alias register used to access register state + indirectly based on the value held in the `siselect` CSR. The `sireg5` CSR provides + access to a window of indirectly addressed registers. + + The behavior of accesses to `sireg5` is determined by the currently selected + `siselect` value, which acts as an index into an alias space defined by the extension + utilizing this access method. This indirect mechanism allows software to access + an array of CSRs without consuming large contiguous blocks of the CSR address space. + + When `siselect` contains a value that is not supported, access to `sireg5` is UNSPECIFIED, + and implementations are encouraged to raise an illegal instruction exception to aid in + debugging or software emulation. + + The indirect access mechanism is useful for CSR arrays, such as counters or + performance registers, and ensures a scalable way to interact with dynamically + indexed register sets. + +fields: + Data: + location_rv32: 31-0 + location_rv64: 63-0 + type: RW + description: | + The data read from or written to the register selected by the current `siselect` value. + reset_value(): return 0x0; diff --git a/arch/csr/Smcsrind/sireg6.yaml b/arch/csr/Smcsrind/sireg6.yaml new file mode 100644 index 0000000000..3d020f872a --- /dev/null +++ b/arch/csr/Smcsrind/sireg6.yaml @@ -0,0 +1,36 @@ +--- +# yaml-language-server: $schema=../../../schemas/csr_schema.json +$schema: csr_schema.json# +kind: csr +name: sireg6 +long_name: Supervisor Indirect Register Alias 6 +address: 0x157 +priv_mode: S +length: SXLEN +definedBy: Sscsrind +description: | + The `sireg6` CSR is a supervisor-level alias register used to access register state + indirectly based on the value held in the `siselect` CSR. The `sireg6` CSR provides + access to a window of indirectly addressed registers. + + The behavior of accesses to `sireg6` is determined by the currently selected + `siselect` value, which acts as an index into an alias space defined by the extension + utilizing this access method. This indirect mechanism allows software to access + an array of CSRs without consuming large contiguous blocks of the CSR address space. + + When `siselect` contains a value that is not supported, access to `sireg6` is UNSPECIFIED, + and implementations are encouraged to raise an illegal instruction exception to aid in + debugging or software emulation. + + The indirect access mechanism is useful for CSR arrays, such as counters or + performance registers, and ensures a scalable way to interact with dynamically + indexed register sets. + +fields: + Data: + location_rv32: 31-0 + location_rv64: 63-0 + type: RW + description: | + The data read from or written to the register selected by the current `siselect` value. + reset_value(): return 0x0; diff --git a/arch/csr/Smcsrind/siselect.yaml b/arch/csr/Smcsrind/siselect.yaml new file mode 100644 index 0000000000..0acd9ce369 --- /dev/null +++ b/arch/csr/Smcsrind/siselect.yaml @@ -0,0 +1,40 @@ +--- +# yaml-language-server: $schema=../../../schemas/csr_schema.json +$schema: csr_schema.json# +kind: csr +name: siselect +long_name: Supervisor Indirect Register Select +address: 0x150 +priv_mode: S +length: SXLEN +definedBy: Sscsrind +description: | + The `siselect` CSR is a supervisor-level register used to select which indirectly + accessed register is targeted via the `sireg*` alias CSRs. The `siselect` value acts + as an index into an extension-defined space of registers, enabling access to a wide + range of CSR-like state without consuming contiguous CSR numbers. + + This mechanism allows software to efficiently access arrays of register state + through indexing, removing the need for large blocks of CSR address space and + reducing software complexity. The `siselect` CSR is typically used alongside + `sireg` through `sireg6` to access registers indirectly. + + The minimum supported value range for `siselect` is 0–0xFFF. Future extensions may + define larger ranges. Values with the most significant bit set (bit SXLEN - 1 = 1) + are reserved for custom use, while those with the MSB cleared are designated for + standard usage and should only be used by ratified extensions. + + When `siselect` holds a value that is not implemented, accesses to `sireg*` are + UNSPECIFIED. It is RECOMMENDED that implementations raise an illegal instruction + exception in such cases to support emulation or error detection. Implementations + may make additional behaviors subject to platform or profile specifications. + +fields: + Select Value: + location_rv32: 31-0 + location_rv64: 63-0 + type: RW + description: | + Index value selecting the target register accessed through `sireg*`. + Acts as an indirect register selector. Values are extension-defined. + reset_value(): return 0x0; From 879e88a059edfb2a5a332488e7704e579cf67383 Mon Sep 17 00:00:00 2001 From: syedowaisalishah Date: Thu, 3 Apr 2025 13:46:15 +0000 Subject: [PATCH 05/29] Add Smcsrind CSR YAML files: vsiselect and vsisireg[1-6] --- arch/csr/Smcsrind/vsireg.yaml | 40 ++++++++++++++++++++++++++++++ arch/csr/Smcsrind/vsireg2.yaml | 34 ++++++++++++++++++++++++++ arch/csr/Smcsrind/vsireg3.yaml | 32 ++++++++++++++++++++++++ arch/csr/Smcsrind/vsireg4.yaml | 31 +++++++++++++++++++++++ arch/csr/Smcsrind/vsireg5.yaml | 31 +++++++++++++++++++++++ arch/csr/Smcsrind/vsireg6.yaml | 31 +++++++++++++++++++++++ arch/csr/Smcsrind/vsiselect.yaml | 42 ++++++++++++++++++++++++++++++++ 7 files changed, 241 insertions(+) create mode 100644 arch/csr/Smcsrind/vsireg.yaml create mode 100644 arch/csr/Smcsrind/vsireg2.yaml create mode 100644 arch/csr/Smcsrind/vsireg3.yaml create mode 100644 arch/csr/Smcsrind/vsireg4.yaml create mode 100644 arch/csr/Smcsrind/vsireg5.yaml create mode 100644 arch/csr/Smcsrind/vsireg6.yaml create mode 100644 arch/csr/Smcsrind/vsiselect.yaml diff --git a/arch/csr/Smcsrind/vsireg.yaml b/arch/csr/Smcsrind/vsireg.yaml new file mode 100644 index 0000000000..2edb51c101 --- /dev/null +++ b/arch/csr/Smcsrind/vsireg.yaml @@ -0,0 +1,40 @@ +--- +# yaml-language-server: $schema=../../../schemas/csr_schema.json +$schema: csr_schema.json# +kind: csr +name: vsireg +long_name: Virtual Supervisor Indirect Register Alias +address: 0x251 +virtual_address: 0x251 +priv_mode: VS +length: VSXLEN +definedBy: Sscsrind +description: | + The `vsireg` CSR is one of several alias registers used to indirectly access + virtual supervisor-level register state. Access to a specific target register + is controlled via the value held in the `vsiselect` CSR, which acts as an + index into a virtualized alias space. + + This mechanism enables efficient access to an array of registers without + consuming a large contiguous range in the CSR address space. When `vsiselect` + holds a value allocated and implemented by a specific extension, `vsireg` + provides access to the corresponding register state. + + If the value in `vsiselect` is not implemented, the behavior is UNSPECIFIED. + However, it is RECOMMENDED that implementations raise a virtual instruction + exception for such accesses. This supports correct virtualization behavior + and allows for software emulation or debugging of unsupported accesses. + + The access behavior for each `vsiselect` + `vsireg` pair is defined by the + extension that owns the `vsiselect` value. Ordinarily, each alias register + either accesses architectural state, reads as zero, or triggers an exception. + +fields: + Data: + location_rv32: 31-0 + location_rv64: 63-0 + type: RW + description: | + The data read from or written to the register selected by the current + value of the `vsiselect` CSR. + reset_value(): return 0x0; diff --git a/arch/csr/Smcsrind/vsireg2.yaml b/arch/csr/Smcsrind/vsireg2.yaml new file mode 100644 index 0000000000..2ce32ae19a --- /dev/null +++ b/arch/csr/Smcsrind/vsireg2.yaml @@ -0,0 +1,34 @@ +--- +# yaml-language-server: $schema=../../../schemas/csr_schema.json +$schema: csr_schema.json# +kind: csr +name: vsireg2 +long_name: Virtual Supervisor Indirect Register Alias 2 +address: 0x252 +virtual_address: 0x252 +priv_mode: VS +length: VSXLEN +definedBy: Sscsrind +description: | + The `vsireg2` CSR is one of the virtual supervisor-level alias registers used + to indirectly access register state based on the value held in the `vsiselect` + CSR. This aliasing mechanism provides a means for indexed access to an array + of registers, reducing the need to reserve large, contiguous blocks of CSR + address space. + + The value in `vsiselect` determines the behavior of `vsireg2`, including the + register that is read or written. Each `vsireg*` CSR behaves as a data window + to register state selected by the `vsiselect` index. + + If `vsiselect` holds a value that is not implemented, the behavior of `vsireg2` + is UNSPECIFIED. Implementations are encouraged to raise a virtual instruction + exception to support debugging and potential emulation. + +fields: + Data: + location_rv32: 31-0 + location_rv64: 63-0 + type: RW + description: | + Data read or written based on the currently selected `vsiselect` value. + reset_value(): return 0x0; diff --git a/arch/csr/Smcsrind/vsireg3.yaml b/arch/csr/Smcsrind/vsireg3.yaml new file mode 100644 index 0000000000..c8a5bb7211 --- /dev/null +++ b/arch/csr/Smcsrind/vsireg3.yaml @@ -0,0 +1,32 @@ +--- +# yaml-language-server: $schema=../../../schemas/csr_schema.json +$schema: csr_schema.json# +kind: csr +name: vsireg3 +long_name: Virtual Supervisor Indirect Register Alias 3 +address: 0x253 +virtual_address: 0x253 +priv_mode: VS +length: VSXLEN +definedBy: Smcsrind +description: | + The `vsireg3` CSR is part of the virtual supervisor-level indirect access + mechanism and serves as one of the alias registers indexed by the `vsiselect` + CSR. + + The indirect CSR access model enables software in VS-mode to interact with + register arrays using a select value, improving scalability and reducing CSR + address space consumption. + + When `vsiselect` holds an unimplemented value, accesses to `vsireg3` are + UNSPECIFIED, and it is recommended that implementations raise a virtual + instruction exception to facilitate software emulation or trap-based + handling. + +fields: + Data: + location_rv32: 31-0 + location_rv64: 63-0 + type: RW + description: Data read or written based on the `vsiselect` value. + reset_value(): return 0x0; diff --git a/arch/csr/Smcsrind/vsireg4.yaml b/arch/csr/Smcsrind/vsireg4.yaml new file mode 100644 index 0000000000..5ae8c62b43 --- /dev/null +++ b/arch/csr/Smcsrind/vsireg4.yaml @@ -0,0 +1,31 @@ +--- +# yaml-language-server: $schema=../../../schemas/csr_schema.json +$schema: csr_schema.json# +kind: csr +name: vsireg4 +long_name: Virtual Supervisor Indirect Register Alias 4 +address: 0x255 +virtual_address: 0x255 +priv_mode: VS +length: VSXLEN +definedBy: Smcsrind +description: | + The `vsireg4` CSR is a virtual supervisor-level alias register accessed + indirectly via the `vsiselect` CSR. It is part of a set of CSRs that form a + scalable mechanism for register array access without requiring dedicated + address space for each individual register. + + In RV32 environments where a register may be 64-bit, `vsireg4` can be used + to access the upper 32 bits of a split register, in conjunction with other + alias CSRs such as `vsireg` or `vsireg2` for the lower bits. + + Accesses to `vsireg4` while `vsiselect` holds an unsupported value are + UNSPECIFIED and should raise a virtual instruction exception. + +fields: + Data: + location_rv32: 31-0 + location_rv64: 63-0 + type: RW + description: Data read or written based on the `vsiselect` value. + reset_value(): return 0x0; diff --git a/arch/csr/Smcsrind/vsireg5.yaml b/arch/csr/Smcsrind/vsireg5.yaml new file mode 100644 index 0000000000..7513786357 --- /dev/null +++ b/arch/csr/Smcsrind/vsireg5.yaml @@ -0,0 +1,31 @@ +--- +# yaml-language-server: $schema=../../../schemas/csr_schema.json +$schema: csr_schema.json# +kind: csr +name: vsireg5 +long_name: Virtual Supervisor Indirect Register Alias 5 +address: 0x256 +virtual_address: 0x256 +priv_mode: VS +length: VSXLEN +definedBy: Smcsrind +description: | + The `vsireg5` CSR is an alias used in the virtual supervisor-level indirect + register access model. It provides indexed access to register state based on + the currently selected value in `vsiselect`. + + This CSR, along with other `vsireg*` aliases, helps provide consistent access + patterns to extended register arrays while maintaining efficient usage of the + limited CSR address space. + + If the selected `vsiselect` value is not implemented, behavior is + UNSPECIFIED, and it is recommended that a virtual instruction exception be + raised. + +fields: + Data: + location_rv32: 31-0 + location_rv64: 63-0 + type: RW + description: Data read or written based on the `vsiselect` value. + reset_value(): return 0x0; diff --git a/arch/csr/Smcsrind/vsireg6.yaml b/arch/csr/Smcsrind/vsireg6.yaml new file mode 100644 index 0000000000..97d8e60041 --- /dev/null +++ b/arch/csr/Smcsrind/vsireg6.yaml @@ -0,0 +1,31 @@ +--- +# yaml-language-server: $schema=../../../schemas/csr_schema.json +$schema: csr_schema.json# +kind: csr +name: vsireg6 +long_name: Virtual Supervisor Indirect Register Alias 6 +address: 0x257 +virtual_address: 0x257 +priv_mode: VS +length: VSXLEN +definedBy: Smcsrind +description: | + The `vsireg6` CSR is the final alias in the virtual supervisor-level set of + indirect access CSRs. Like its counterparts, it is accessed indirectly through + the `vsiselect` CSR and provides a data window into a selected register. + + For 64-bit register arrays in RV32 environments, `vsireg6` may be used for + accessing the upper 32 bits, while lower aliases such as `vsireg3` provide the + corresponding lower half. + + Access to `vsireg6` while `vsiselect` holds an unsupported value is + UNSPECIFIED. Virtual instruction exceptions are recommended for unsupported + access cases. + +fields: + Data: + location_rv32: 31-0 + location_rv64: 63-0 + type: RW + description: Data read or written based on the `vsiselect` value. + reset_value(): return 0x0; diff --git a/arch/csr/Smcsrind/vsiselect.yaml b/arch/csr/Smcsrind/vsiselect.yaml new file mode 100644 index 0000000000..0353af62f4 --- /dev/null +++ b/arch/csr/Smcsrind/vsiselect.yaml @@ -0,0 +1,42 @@ +--- +# yaml-language-server: $schema=../../../schemas/csr_schema.json +$schema: csr_schema.json# +kind: csr +name: vsiselect +long_name: Virtual Supervisor Indirect Register Select +address: 0x250 +virtual_address: 0x250 +priv_mode: VS +length: VSXLEN +definedBy: Smcsrind +description: | + The `vsireg` CSR is a virtual supervisor-level alias register used to access + register state indirectly, based on the index specified in the `vsiselect` CSR. + This mechanism provides a scalable and efficient way to expose a large number + of virtual supervisor-level registers without consuming contiguous CSR address + space. + + The value held in `vsiselect` determines which internal register is accessed + via `vsireg`. This allows for software to access register arrays by index rather + than by fixed CSR numbers, enabling more compact and flexible register access + patterns. + + When the value in `vsiselect` corresponds to a defined and implemented select + value, the behavior of read and write accesses to `vsireg` is defined by the + extension to which the `vsiselect` value is allocated. If the value in `vsiselect` + is not supported, the behavior is UNSPECIFIED; however, it is recommended that + implementations raise a virtual instruction exception to facilitate debugging + and enable software emulation. + + This indirect access model helps virtual machines access CSR state without + direct mapping of each CSR, reducing implementation complexity and preserving + CSR encoding space. +fields: + Data: + location_rv32: 31-0 + location_rv64: 63-0 + type: RW + description: | + The data read from or written to the register selected by the current + `vsiselect` value. + reset_value(): return 0x0; From b52410f5832b93ee7cf3a60a2d711133b35c4a5e Mon Sep 17 00:00:00 2001 From: syedowaisalishah Date: Thu, 3 Apr 2025 13:58:06 +0000 Subject: [PATCH 06/29] Add Smcsrind CSR YAML files: miselect and miireg[1-6] --- arch/csr/Smcsrind/mireg.yaml | 15 +++++++++------ arch/csr/Smcsrind/mireg2.yaml | 13 +++++++------ arch/csr/Smcsrind/mireg3.yaml | 13 +++++++------ arch/csr/Smcsrind/mireg4.yaml | 12 ++++++------ arch/csr/Smcsrind/mireg5.yaml | 12 ++++++------ arch/csr/Smcsrind/mireg6.yaml | 12 ++++++------ arch/csr/Smcsrind/miselect.yaml | 25 +++++++++++++------------ 7 files changed, 54 insertions(+), 48 deletions(-) diff --git a/arch/csr/Smcsrind/mireg.yaml b/arch/csr/Smcsrind/mireg.yaml index 6f264bb697..2b6d5db657 100644 --- a/arch/csr/Smcsrind/mireg.yaml +++ b/arch/csr/Smcsrind/mireg.yaml @@ -9,14 +9,17 @@ priv_mode: M length: MXLEN definedBy: Smcsrind description: | - The `mireg` CSR is an alias register for accessing indirect registers that - are selected by the `miselect` CSR. The value of `miselect` determines which - register is accessed during read or write operations. + description: | + The `mireg` CSR is the primary machine-level indirect alias register used to access + register state as determined by the index held in `miselect`. This CSR is typically used + to read or write the full 32-bit or 64-bit value of the indirectly addressed register. - The `mireg` CSR is used for indirect access to machine-level registers. - The access to these registers depends on the value in the `miselect` CSR. + For 64-bit registers in RV32 systems, `mireg` is generally used to access the lower 32 bits. + Combined with higher-indexed aliases (e.g., `mireg4`), this provides full access to 64-bit values + across multiple CSRs. - If `miselect` selects this register, the data can be read or written using this CSR. + If the value in `miselect` is not implemented, access is UNSPECIFIED. Implementations + are encouraged to raise an illegal instruction exception in such cases. fields: Count: diff --git a/arch/csr/Smcsrind/mireg2.yaml b/arch/csr/Smcsrind/mireg2.yaml index 76d29d79dc..0d28c6f105 100644 --- a/arch/csr/Smcsrind/mireg2.yaml +++ b/arch/csr/Smcsrind/mireg2.yaml @@ -9,14 +9,15 @@ priv_mode: M length: MXLEN definedBy: Smcsrind description: | - The `mireg2` CSR is an alias register for accessing indirect registers that - are selected by the `miselect` CSR. The value of `miselect` determines which - register is accessed during read or write operations. + The `mireg2` CSR is an indirect alias register used for machine-level access to register state, + indexed via the value in `miselect`. - The `mireg2` CSR is used for indirect access to machine-level registers. - The access to these registers depends on the value in the `miselect` CSR. + Like `mireg`, this CSR enables flexible access to an array of registers without allocating + dedicated CSR numbers for each. It may be used independently or as part of a split-access + scheme for larger registers in RV32. - If `miselect` selects this register, the data can be read or written using this CSR. + The behavior of `mireg2` is determined by the value of `miselect`. If `miselect` holds + an unsupported value, the behavior is UNSPECIFIED. fields: Count: diff --git a/arch/csr/Smcsrind/mireg3.yaml b/arch/csr/Smcsrind/mireg3.yaml index 501ba06ee1..3d0539a70a 100644 --- a/arch/csr/Smcsrind/mireg3.yaml +++ b/arch/csr/Smcsrind/mireg3.yaml @@ -9,14 +9,15 @@ priv_mode: M length: MXLEN definedBy: Smcsrind description: | - The `mireg3` CSR is an alias register for accessing indirect registers that - are selected by the `miselect` CSR. The value of `miselect` determines which - register is accessed during read or write operations. + The `mireg3` CSR provides an additional machine-level alias for indirect register access via + the `miselect` CSR. This CSR supports cases where multiple register arrays or channels need + to be addressed concurrently. - The `mireg3` CSR is used for indirect access to machine-level registers. - The access to these registers depends on the value in the `miselect` CSR. + In RV32, `mireg3` may be used as part of an array access pattern to read or write lower + segments of a register, or to support separate CSR sets. - If `miselect` selects this register, the data can be read or written using this CSR. + Access behavior is defined by the selected value in `miselect`. Unsupported values result in + UNSPECIFIED behavior and may raise an illegal instruction exception. fields: Count: diff --git a/arch/csr/Smcsrind/mireg4.yaml b/arch/csr/Smcsrind/mireg4.yaml index addd5facc0..8132fdd867 100644 --- a/arch/csr/Smcsrind/mireg4.yaml +++ b/arch/csr/Smcsrind/mireg4.yaml @@ -9,14 +9,14 @@ priv_mode: M length: MXLEN definedBy: Smcsrind description: | - The `mireg4` CSR is an alias register for accessing indirect registers that - are selected by the `miselect` CSR. The value of `miselect` determines which - register is accessed during read or write operations. + The `mireg4` CSR is commonly used to access the upper 32 bits of a 64-bit machine-level + register in RV32 systems when used alongside `mireg`, `mireg2`, or `mireg3`. - The `mireg4` CSR is used for indirect access to machine-level registers. - The access to these registers depends on the value in the `miselect` CSR. + This split-access capability allows for indirect access to full 64-bit values in 32-bit environments + using paired CSRs. The `miselect` value determines the exact register being accessed. - If `miselect` selects this register, the data can be read or written using this CSR. + If `miselect` points to an unimplemented mapping, behavior is UNSPECIFIED. It is + RECOMMENDED to raise an illegal instruction exception. fields: Count: diff --git a/arch/csr/Smcsrind/mireg5.yaml b/arch/csr/Smcsrind/mireg5.yaml index 5001c06ee3..c99588469a 100644 --- a/arch/csr/Smcsrind/mireg5.yaml +++ b/arch/csr/Smcsrind/mireg5.yaml @@ -9,14 +9,14 @@ priv_mode: M length: MXLEN definedBy: Smcsrind description: | - The `mireg5` CSR is an alias register for accessing indirect registers that - are selected by the `miselect` CSR. The value of `miselect` determines which - register is accessed during read or write operations. + The `mireg5` CSR is a machine-level alias register used primarily for accessing the upper half + of a 64-bit register in RV32, complementing `mireg2`. - The `mireg5` CSR is used for indirect access to machine-level registers. - The access to these registers depends on the value in the `miselect` CSR. + When `miselect` is configured to point to a 64-bit register, `mireg2` may provide access + to the lower 32 bits while `mireg5` gives access to the upper 32 bits. - If `miselect` selects this register, the data can be read or written using this CSR. + Behavior is extension-defined and depends on the current `miselect` value. Illegal + or unsupported values yield UNSPECIFIED behavior. fields: Count: diff --git a/arch/csr/Smcsrind/mireg6.yaml b/arch/csr/Smcsrind/mireg6.yaml index acbf686096..9984195a0c 100644 --- a/arch/csr/Smcsrind/mireg6.yaml +++ b/arch/csr/Smcsrind/mireg6.yaml @@ -9,14 +9,14 @@ priv_mode: M length: MXLEN definedBy: Smcsrind description: | - The `mireg6` CSR is an alias register for accessing indirect registers that - are selected by the `miselect` CSR. The value of `miselect` determines which - register is accessed during read or write operations. + The `mireg6` CSR offers the final alias in the machine-level indirect access set, and is typically + used for the upper half of a 64-bit register accessed via `mireg3` in RV32 environments. - The `mireg6` CSR is used for indirect access to machine-level registers. - The access to these registers depends on the value in the `miselect` CSR. + This CSR expands support for multiple register arrays, enabling extensions to define complex + or high-bandwidth access patterns using a compact set of CSRs. - If `miselect` selects this register, the data can be read or written using this CSR. + When `miselect` holds a value not allocated or implemented by an extension, access is + UNSPECIFIED and may raise an exception. fields: Count: diff --git a/arch/csr/Smcsrind/miselect.yaml b/arch/csr/Smcsrind/miselect.yaml index d123eef26e..d3705b047d 100644 --- a/arch/csr/Smcsrind/miselect.yaml +++ b/arch/csr/Smcsrind/miselect.yaml @@ -9,20 +9,21 @@ priv_mode: M length: MXLEN definedBy: Smcsrind description: | - The `miselect` CSR is a register used to select the indirect registers that - can be accessed using the `mireg*` aliases. The value of this register - determines which indirect register is accessed during read or write operations. + The `miselect` CSR is a WARL (Write-Any Read-Legal) register that selects which + indirect register is accessed via the `mireg*` alias CSRs. The value in `miselect` + acts as an index into a space of indirectly addressable machine-level registers. - The values of `miselect` define the indirect registers accessible via - `mireg*`. The valid values are allocated by the extension that implements - indirect access. The most significant bit is reserved for custom usage. - It is recommended that a value of 0 corresponds to a standard set of - indirect register aliases. + Values of `miselect` are allocated by extensions implementing indirect register access. + The most-significant bit (bit MXLEN-1) is reserved for custom use and must be used + only with implementation-specific extensions. Values with this bit clear are reserved + for standard use. - The indirect access mechanism enables a more efficient method to access - registers without needing to reserve large chunks of CSR address space. - Implementations should ensure that accesses to `miselect` with unsupported - values result in an illegal instruction exception. + The indirect access mechanism enabled by `miselect` reduces the need for allocating + large contiguous CSR address ranges by supporting register arrays accessed by index. + + If `miselect` holds an unsupported value, accesses to the corresponding `mireg*` + alias CSR are UNSPECIFIED. Implementations are encouraged to raise an illegal instruction + exception to support robust error handling and software emulation. fields: Select Value: From 6db2f59cd161cc0b395b1b61c9c27511c12142c2 Mon Sep 17 00:00:00 2001 From: syedowaisalishah Date: Sat, 5 Apr 2025 02:34:18 +0000 Subject: [PATCH 07/29] Fix: removed duplicate description line, updated reset_value to UNDEFINED_LEGAL --- arch/csr/Smcsrind/mireg.yaml | 20 ++++++++++---------- arch/csr/Smcsrind/mireg2.yaml | 3 ++- arch/csr/Smcsrind/mireg3.yaml | 3 ++- arch/csr/Smcsrind/mireg4.yaml | 3 ++- arch/csr/Smcsrind/mireg5.yaml | 3 ++- arch/csr/Smcsrind/mireg6.yaml | 3 ++- arch/csr/Smcsrind/miselect.yaml | 3 ++- arch/csr/Smcsrind/sireg.yaml | 3 ++- arch/csr/Smcsrind/sireg2.yaml | 3 ++- arch/csr/Smcsrind/sireg3.yaml | 3 ++- arch/csr/Smcsrind/sireg4.yaml | 3 ++- arch/csr/Smcsrind/sireg5.yaml | 3 ++- arch/csr/Smcsrind/sireg6.yaml | 3 ++- arch/csr/Smcsrind/siselect.yaml | 3 ++- arch/csr/Smcsrind/vsireg.yaml | 3 ++- arch/csr/Smcsrind/vsireg2.yaml | 3 ++- arch/csr/Smcsrind/vsireg3.yaml | 3 ++- arch/csr/Smcsrind/vsireg4.yaml | 3 ++- arch/csr/Smcsrind/vsireg5.yaml | 3 ++- arch/csr/Smcsrind/vsireg6.yaml | 3 ++- arch/csr/Smcsrind/vsiselect.yaml | 3 ++- 21 files changed, 50 insertions(+), 30 deletions(-) diff --git a/arch/csr/Smcsrind/mireg.yaml b/arch/csr/Smcsrind/mireg.yaml index 2b6d5db657..baf268688a 100644 --- a/arch/csr/Smcsrind/mireg.yaml +++ b/arch/csr/Smcsrind/mireg.yaml @@ -9,17 +9,16 @@ priv_mode: M length: MXLEN definedBy: Smcsrind description: | - description: | - The `mireg` CSR is the primary machine-level indirect alias register used to access - register state as determined by the index held in `miselect`. This CSR is typically used - to read or write the full 32-bit or 64-bit value of the indirectly addressed register. + The `mireg` CSR is the primary machine-level indirect alias register used to access + register state as determined by the index held in `miselect`. This CSR is typically used + to read or write the full 32-bit or 64-bit value of the indirectly addressed register. - For 64-bit registers in RV32 systems, `mireg` is generally used to access the lower 32 bits. - Combined with higher-indexed aliases (e.g., `mireg4`), this provides full access to 64-bit values - across multiple CSRs. + For 64-bit registers in RV32 systems, `mireg` is generally used to access the lower 32 bits. + Combined with higher-indexed aliases (e.g., `mireg4`), this provides full access to 64-bit values + across multiple CSRs. - If the value in `miselect` is not implemented, access is UNSPECIFIED. Implementations - are encouraged to raise an illegal instruction exception in such cases. + If the value in `miselect` is not implemented, access is UNSPECIFIED. Implementations + are encouraged to raise an illegal instruction exception in such cases. fields: Count: @@ -27,4 +26,5 @@ fields: location_rv64: 63-0 type: RW description: Indirect register data selected by `miselect` value. - reset_value(): return 0x0; + reset_value: UNDEFINED_LEGAL +sw_read(): | diff --git a/arch/csr/Smcsrind/mireg2.yaml b/arch/csr/Smcsrind/mireg2.yaml index 0d28c6f105..3d62084702 100644 --- a/arch/csr/Smcsrind/mireg2.yaml +++ b/arch/csr/Smcsrind/mireg2.yaml @@ -25,4 +25,5 @@ fields: location_rv64: 63-0 type: RW description: Indirect register data selected by `miselect` value. - reset_value(): return 0x0; + reset_value: UNDEFINED_LEGAL +sw_read(): | diff --git a/arch/csr/Smcsrind/mireg3.yaml b/arch/csr/Smcsrind/mireg3.yaml index 3d0539a70a..c1ebbc6c59 100644 --- a/arch/csr/Smcsrind/mireg3.yaml +++ b/arch/csr/Smcsrind/mireg3.yaml @@ -25,4 +25,5 @@ fields: location_rv64: 63-0 type: RW description: Indirect register data selected by `miselect` value. - reset_value(): return 0x0; + reset_value: UNDEFINED_LEGAL +sw_read(): | diff --git a/arch/csr/Smcsrind/mireg4.yaml b/arch/csr/Smcsrind/mireg4.yaml index 8132fdd867..34fcf9c1e7 100644 --- a/arch/csr/Smcsrind/mireg4.yaml +++ b/arch/csr/Smcsrind/mireg4.yaml @@ -24,4 +24,5 @@ fields: location_rv64: 63-0 type: RW description: Indirect register data selected by `miselect` value. - reset_value(): return 0x0; + reset_value: UNDEFINED_LEGAL +sw_read(): | diff --git a/arch/csr/Smcsrind/mireg5.yaml b/arch/csr/Smcsrind/mireg5.yaml index c99588469a..021175110f 100644 --- a/arch/csr/Smcsrind/mireg5.yaml +++ b/arch/csr/Smcsrind/mireg5.yaml @@ -24,4 +24,5 @@ fields: location_rv64: 63-0 type: RW description: Indirect register data selected by `miselect` value. - reset_value(): return 0x0; + reset_value: UNDEFINED_LEGAL +sw_read(): | diff --git a/arch/csr/Smcsrind/mireg6.yaml b/arch/csr/Smcsrind/mireg6.yaml index 9984195a0c..c8b7a8113c 100644 --- a/arch/csr/Smcsrind/mireg6.yaml +++ b/arch/csr/Smcsrind/mireg6.yaml @@ -24,4 +24,5 @@ fields: location_rv64: 63-0 type: RW description: Indirect register data selected by `miselect` value. - reset_value(): return 0x0; + reset_value: UNDEFINED_LEGAL +sw_read(): | diff --git a/arch/csr/Smcsrind/miselect.yaml b/arch/csr/Smcsrind/miselect.yaml index d3705b047d..9ff439a281 100644 --- a/arch/csr/Smcsrind/miselect.yaml +++ b/arch/csr/Smcsrind/miselect.yaml @@ -31,4 +31,5 @@ fields: location_rv64: 63-0 type: RW description: Selects which indirect register is accessed via `mireg*`. - reset_value(): return 0x0; + reset_value: UNDEFINED_LEGAL +sw_read(): | diff --git a/arch/csr/Smcsrind/sireg.yaml b/arch/csr/Smcsrind/sireg.yaml index a1652649d0..7d6a74f37c 100644 --- a/arch/csr/Smcsrind/sireg.yaml +++ b/arch/csr/Smcsrind/sireg.yaml @@ -33,4 +33,5 @@ fields: type: RW description: | The data read from or written to the register selected by the current `siselect` value. - reset_value(): return 0x0; + reset_value: UNDEFINED_LEGAL +sw_read(): | diff --git a/arch/csr/Smcsrind/sireg2.yaml b/arch/csr/Smcsrind/sireg2.yaml index 44db745469..9451585617 100644 --- a/arch/csr/Smcsrind/sireg2.yaml +++ b/arch/csr/Smcsrind/sireg2.yaml @@ -33,4 +33,5 @@ fields: type: RW description: | The data read from or written to the register selected by the current `siselect` value. - reset_value(): return 0x0; + reset_value: UNDEFINED_LEGAL +sw_read(): | diff --git a/arch/csr/Smcsrind/sireg3.yaml b/arch/csr/Smcsrind/sireg3.yaml index 84beeaa0ef..0d0eb42283 100644 --- a/arch/csr/Smcsrind/sireg3.yaml +++ b/arch/csr/Smcsrind/sireg3.yaml @@ -33,4 +33,5 @@ fields: type: RW description: | The data read from or written to the register selected by the current `siselect` value. - reset_value(): return 0x0; + reset_value: UNDEFINED_LEGAL +sw_read(): | diff --git a/arch/csr/Smcsrind/sireg4.yaml b/arch/csr/Smcsrind/sireg4.yaml index 91ce3224c2..f2586dd8b3 100644 --- a/arch/csr/Smcsrind/sireg4.yaml +++ b/arch/csr/Smcsrind/sireg4.yaml @@ -33,4 +33,5 @@ fields: type: RW description: | The data read from or written to the register selected by the current `siselect` value. - reset_value(): return 0x0; + reset_value: UNDEFINED_LEGAL +sw_read(): | diff --git a/arch/csr/Smcsrind/sireg5.yaml b/arch/csr/Smcsrind/sireg5.yaml index c05374639b..2816a50b5a 100644 --- a/arch/csr/Smcsrind/sireg5.yaml +++ b/arch/csr/Smcsrind/sireg5.yaml @@ -33,4 +33,5 @@ fields: type: RW description: | The data read from or written to the register selected by the current `siselect` value. - reset_value(): return 0x0; + reset_value: UNDEFINED_LEGAL +sw_read(): | diff --git a/arch/csr/Smcsrind/sireg6.yaml b/arch/csr/Smcsrind/sireg6.yaml index 3d020f872a..5ba4cc3309 100644 --- a/arch/csr/Smcsrind/sireg6.yaml +++ b/arch/csr/Smcsrind/sireg6.yaml @@ -33,4 +33,5 @@ fields: type: RW description: | The data read from or written to the register selected by the current `siselect` value. - reset_value(): return 0x0; + reset_value: UNDEFINED_LEGAL +sw_read(): | diff --git a/arch/csr/Smcsrind/siselect.yaml b/arch/csr/Smcsrind/siselect.yaml index 0acd9ce369..7edc3aff9a 100644 --- a/arch/csr/Smcsrind/siselect.yaml +++ b/arch/csr/Smcsrind/siselect.yaml @@ -37,4 +37,5 @@ fields: description: | Index value selecting the target register accessed through `sireg*`. Acts as an indirect register selector. Values are extension-defined. - reset_value(): return 0x0; + reset_value: UNDEFINED_LEGAL +sw_read(): | diff --git a/arch/csr/Smcsrind/vsireg.yaml b/arch/csr/Smcsrind/vsireg.yaml index 2edb51c101..28b6047e14 100644 --- a/arch/csr/Smcsrind/vsireg.yaml +++ b/arch/csr/Smcsrind/vsireg.yaml @@ -37,4 +37,5 @@ fields: description: | The data read from or written to the register selected by the current value of the `vsiselect` CSR. - reset_value(): return 0x0; + reset_value: UNDEFINED_LEGAL +sw_read(): | diff --git a/arch/csr/Smcsrind/vsireg2.yaml b/arch/csr/Smcsrind/vsireg2.yaml index 2ce32ae19a..0c6ccda3b3 100644 --- a/arch/csr/Smcsrind/vsireg2.yaml +++ b/arch/csr/Smcsrind/vsireg2.yaml @@ -31,4 +31,5 @@ fields: type: RW description: | Data read or written based on the currently selected `vsiselect` value. - reset_value(): return 0x0; + reset_value: UNDEFINED_LEGAL +sw_read(): | diff --git a/arch/csr/Smcsrind/vsireg3.yaml b/arch/csr/Smcsrind/vsireg3.yaml index c8a5bb7211..ac428ce0fc 100644 --- a/arch/csr/Smcsrind/vsireg3.yaml +++ b/arch/csr/Smcsrind/vsireg3.yaml @@ -29,4 +29,5 @@ fields: location_rv64: 63-0 type: RW description: Data read or written based on the `vsiselect` value. - reset_value(): return 0x0; + reset_value: UNDEFINED_LEGAL +sw_read(): | diff --git a/arch/csr/Smcsrind/vsireg4.yaml b/arch/csr/Smcsrind/vsireg4.yaml index 5ae8c62b43..37413a8d08 100644 --- a/arch/csr/Smcsrind/vsireg4.yaml +++ b/arch/csr/Smcsrind/vsireg4.yaml @@ -28,4 +28,5 @@ fields: location_rv64: 63-0 type: RW description: Data read or written based on the `vsiselect` value. - reset_value(): return 0x0; + reset_value: UNDEFINED_LEGAL +sw_read(): | diff --git a/arch/csr/Smcsrind/vsireg5.yaml b/arch/csr/Smcsrind/vsireg5.yaml index 7513786357..76e3e112ac 100644 --- a/arch/csr/Smcsrind/vsireg5.yaml +++ b/arch/csr/Smcsrind/vsireg5.yaml @@ -28,4 +28,5 @@ fields: location_rv64: 63-0 type: RW description: Data read or written based on the `vsiselect` value. - reset_value(): return 0x0; + reset_value: UNDEFINED_LEGAL +sw_read(): | diff --git a/arch/csr/Smcsrind/vsireg6.yaml b/arch/csr/Smcsrind/vsireg6.yaml index 97d8e60041..67160e8ef0 100644 --- a/arch/csr/Smcsrind/vsireg6.yaml +++ b/arch/csr/Smcsrind/vsireg6.yaml @@ -28,4 +28,5 @@ fields: location_rv64: 63-0 type: RW description: Data read or written based on the `vsiselect` value. - reset_value(): return 0x0; + reset_value: UNDEFINED_LEGAL +sw_read(): | diff --git a/arch/csr/Smcsrind/vsiselect.yaml b/arch/csr/Smcsrind/vsiselect.yaml index 0353af62f4..aa413c9fda 100644 --- a/arch/csr/Smcsrind/vsiselect.yaml +++ b/arch/csr/Smcsrind/vsiselect.yaml @@ -39,4 +39,5 @@ fields: description: | The data read from or written to the register selected by the current `vsiselect` value. - reset_value(): return 0x0; + reset_value: UNDEFINED_LEGAL +sw_read(): | From 2558427600bbd8de3a125e1e73a9f6378bcb5671 Mon Sep 17 00:00:00 2001 From: syedowaisalishah Date: Thu, 10 Apr 2025 12:30:58 +0000 Subject: [PATCH 08/29] Corrected Smcsrind CSR YAML files for: miselect, mireg[1-6] --- arch/csr/Smcsrind/mireg.yaml | 14 ++++---------- arch/csr/Smcsrind/mireg2.yaml | 18 ++++++++---------- arch/csr/Smcsrind/mireg3.yaml | 18 ++++++++---------- arch/csr/Smcsrind/mireg4.yaml | 17 ++++++++--------- arch/csr/Smcsrind/mireg5.yaml | 17 ++++++++--------- arch/csr/Smcsrind/mireg6.yaml | 17 ++++++++--------- arch/csr/Smcsrind/miselect.yaml | 1 - 7 files changed, 44 insertions(+), 58 deletions(-) diff --git a/arch/csr/Smcsrind/mireg.yaml b/arch/csr/Smcsrind/mireg.yaml index baf268688a..79f60836b8 100644 --- a/arch/csr/Smcsrind/mireg.yaml +++ b/arch/csr/Smcsrind/mireg.yaml @@ -1,30 +1,24 @@ ---- # yaml-language-server: $schema=../../../schemas/csr_schema.json $schema: csr_schema.json# kind: csr name: mireg -long_name: Machine Indirect Register Alias 1 +long_name: Machine Indirect Register Alias address: 0x351 priv_mode: M length: MXLEN definedBy: Smcsrind description: | - The `mireg` CSR is the primary machine-level indirect alias register used to access + The `mireg` CSR is the machine-level indirect alias register used to access register state as determined by the index held in `miselect`. This CSR is typically used - to read or write the full 32-bit or 64-bit value of the indirectly addressed register. - - For 64-bit registers in RV32 systems, `mireg` is generally used to access the lower 32 bits. - Combined with higher-indexed aliases (e.g., `mireg4`), this provides full access to 64-bit values - across multiple CSRs. + to access the register state of a CSR selected by `miselect` value. If the value in `miselect` is not implemented, access is UNSPECIFIED. Implementations are encouraged to raise an illegal instruction exception in such cases. - fields: Count: location_rv32: 31-0 location_rv64: 63-0 type: RW - description: Indirect register data selected by `miselect` value. + description: Register state data of CSR selected by `miselect` value. reset_value: UNDEFINED_LEGAL sw_read(): | diff --git a/arch/csr/Smcsrind/mireg2.yaml b/arch/csr/Smcsrind/mireg2.yaml index 3d62084702..56fec951f7 100644 --- a/arch/csr/Smcsrind/mireg2.yaml +++ b/arch/csr/Smcsrind/mireg2.yaml @@ -1,4 +1,3 @@ ---- # yaml-language-server: $schema=../../../schemas/csr_schema.json $schema: csr_schema.json# kind: csr @@ -9,21 +8,20 @@ priv_mode: M length: MXLEN definedBy: Smcsrind description: | - The `mireg2` CSR is an indirect alias register used for machine-level access to register state, - indexed via the value in `miselect`. + The `mireg2` CSR is a machine-level indirect alias register used to access + register state as determined by the value in `miselect`. This CSR allows + flexible access to an array of registers without requiring dedicated CSR + numbers for each. - Like `mireg`, this CSR enables flexible access to an array of registers without allocating - dedicated CSR numbers for each. It may be used independently or as part of a split-access - scheme for larger registers in RV32. - - The behavior of `mireg2` is determined by the value of `miselect`. If `miselect` holds - an unsupported value, the behavior is UNSPECIFIED. + The behavior of `mireg2` is determined by the value in `miselect`. If the + value in `miselect` is not implemented, access is UNSPECIFIED, and it is + encouraged that implementations raise an illegal instruction exception in such cases. fields: Count: location_rv32: 31-0 location_rv64: 63-0 type: RW - description: Indirect register data selected by `miselect` value. + description: Register state data of CSR selected by `miselect` value. reset_value: UNDEFINED_LEGAL sw_read(): | diff --git a/arch/csr/Smcsrind/mireg3.yaml b/arch/csr/Smcsrind/mireg3.yaml index c1ebbc6c59..e9fe657e10 100644 --- a/arch/csr/Smcsrind/mireg3.yaml +++ b/arch/csr/Smcsrind/mireg3.yaml @@ -1,4 +1,3 @@ ---- # yaml-language-server: $schema=../../../schemas/csr_schema.json $schema: csr_schema.json# kind: csr @@ -9,21 +8,20 @@ priv_mode: M length: MXLEN definedBy: Smcsrind description: | - The `mireg3` CSR provides an additional machine-level alias for indirect register access via - the `miselect` CSR. This CSR supports cases where multiple register arrays or channels need - to be addressed concurrently. + The `mireg3` CSR is a machine-level indirect alias register used to access + register state as determined by the value in `miselect`. This CSR allows + flexible access to an array of registers without requiring dedicated CSR + numbers for each. - In RV32, `mireg3` may be used as part of an array access pattern to read or write lower - segments of a register, or to support separate CSR sets. - - Access behavior is defined by the selected value in `miselect`. Unsupported values result in - UNSPECIFIED behavior and may raise an illegal instruction exception. + The behavior of `mireg3` is determined by the value in `miselect`. If the + value in `miselect` is not implemented, access is UNSPECIFIED, and it is + encouraged that implementations raise an illegal instruction exception in such cases. fields: Count: location_rv32: 31-0 location_rv64: 63-0 type: RW - description: Indirect register data selected by `miselect` value. + description: Register state data of CSR selected by `miselect` value. reset_value: UNDEFINED_LEGAL sw_read(): | diff --git a/arch/csr/Smcsrind/mireg4.yaml b/arch/csr/Smcsrind/mireg4.yaml index 34fcf9c1e7..1556b3573e 100644 --- a/arch/csr/Smcsrind/mireg4.yaml +++ b/arch/csr/Smcsrind/mireg4.yaml @@ -1,4 +1,3 @@ ---- # yaml-language-server: $schema=../../../schemas/csr_schema.json $schema: csr_schema.json# kind: csr @@ -9,20 +8,20 @@ priv_mode: M length: MXLEN definedBy: Smcsrind description: | - The `mireg4` CSR is commonly used to access the upper 32 bits of a 64-bit machine-level - register in RV32 systems when used alongside `mireg`, `mireg2`, or `mireg3`. + The `mireg4` CSR is a machine-level indirect alias register used to access + register state as determined by the value in `miselect`. This CSR provides + access to a range of registers indirectly without requiring dedicated CSR + numbers for each register. - This split-access capability allows for indirect access to full 64-bit values in 32-bit environments - using paired CSRs. The `miselect` value determines the exact register being accessed. - - If `miselect` points to an unimplemented mapping, behavior is UNSPECIFIED. It is - RECOMMENDED to raise an illegal instruction exception. + The behavior of `mireg4` is determined by the value of `miselect`. If the value + in `miselect` is not implemented, access is UNSPECIFIED, and implementations + are encouraged to raise an illegal instruction exception. fields: Count: location_rv32: 31-0 location_rv64: 63-0 type: RW - description: Indirect register data selected by `miselect` value. + description: Register state data of CSR selected by `miselect` value. reset_value: UNDEFINED_LEGAL sw_read(): | diff --git a/arch/csr/Smcsrind/mireg5.yaml b/arch/csr/Smcsrind/mireg5.yaml index 021175110f..71177b3eba 100644 --- a/arch/csr/Smcsrind/mireg5.yaml +++ b/arch/csr/Smcsrind/mireg5.yaml @@ -1,4 +1,3 @@ ---- # yaml-language-server: $schema=../../../schemas/csr_schema.json $schema: csr_schema.json# kind: csr @@ -9,20 +8,20 @@ priv_mode: M length: MXLEN definedBy: Smcsrind description: | - The `mireg5` CSR is a machine-level alias register used primarily for accessing the upper half - of a 64-bit register in RV32, complementing `mireg2`. + The `mireg5` CSR is a machine-level indirect alias register used to access + register state as determined by the value in `miselect`. This CSR provides + access to a range of registers indirectly without requiring dedicated CSR + numbers for each register. - When `miselect` is configured to point to a 64-bit register, `mireg2` may provide access - to the lower 32 bits while `mireg5` gives access to the upper 32 bits. - - Behavior is extension-defined and depends on the current `miselect` value. Illegal - or unsupported values yield UNSPECIFIED behavior. + The behavior of `mireg5` is determined by the value of `miselect`. If the value + in `miselect` is not implemented, access is UNSPECIFIED, and implementations + are encouraged to raise an illegal instruction exception. fields: Count: location_rv32: 31-0 location_rv64: 63-0 type: RW - description: Indirect register data selected by `miselect` value. + description: Register state data of CSR selected by `miselect` value. reset_value: UNDEFINED_LEGAL sw_read(): | diff --git a/arch/csr/Smcsrind/mireg6.yaml b/arch/csr/Smcsrind/mireg6.yaml index c8b7a8113c..b2449abebb 100644 --- a/arch/csr/Smcsrind/mireg6.yaml +++ b/arch/csr/Smcsrind/mireg6.yaml @@ -1,4 +1,3 @@ ---- # yaml-language-server: $schema=../../../schemas/csr_schema.json $schema: csr_schema.json# kind: csr @@ -9,20 +8,20 @@ priv_mode: M length: MXLEN definedBy: Smcsrind description: | - The `mireg6` CSR offers the final alias in the machine-level indirect access set, and is typically - used for the upper half of a 64-bit register accessed via `mireg3` in RV32 environments. + The `mireg6` CSR is a machine-level indirect alias register used to access + register state as determined by the value in `miselect`. This CSR provides + access to a range of registers indirectly without requiring dedicated CSR + numbers for each register. - This CSR expands support for multiple register arrays, enabling extensions to define complex - or high-bandwidth access patterns using a compact set of CSRs. - - When `miselect` holds a value not allocated or implemented by an extension, access is - UNSPECIFIED and may raise an exception. + The behavior of `mireg6` is determined by the value of `miselect`. If the value + in `miselect` is not implemented, access is UNSPECIFIED, and implementations + are encouraged to raise an illegal instruction exception fields: Count: location_rv32: 31-0 location_rv64: 63-0 type: RW - description: Indirect register data selected by `miselect` value. + description: Register state data of CSR selected by `miselect` value. reset_value: UNDEFINED_LEGAL sw_read(): | diff --git a/arch/csr/Smcsrind/miselect.yaml b/arch/csr/Smcsrind/miselect.yaml index 9ff439a281..93101cd283 100644 --- a/arch/csr/Smcsrind/miselect.yaml +++ b/arch/csr/Smcsrind/miselect.yaml @@ -1,4 +1,3 @@ ---- # yaml-language-server: $schema=../../../schemas/csr_schema.json $schema: csr_schema.json# kind: csr From d735d60a9f886aabb7340a227478b575cf8f15f7 Mon Sep 17 00:00:00 2001 From: syedowaisalishah Date: Thu, 10 Apr 2025 13:14:52 +0000 Subject: [PATCH 09/29] Corrected Sscsrind CSR YAML files for: siselect, sireg[1-6] --- arch/csr/Smcsrind/sireg.yaml | 1 - arch/csr/Smcsrind/sireg2.yaml | 20 +++++++++----------- arch/csr/Smcsrind/sireg3.yaml | 20 +++++++++----------- arch/csr/Smcsrind/sireg4.yaml | 20 +++++++++----------- arch/csr/Smcsrind/sireg5.yaml | 20 +++++++++----------- arch/csr/Smcsrind/sireg6.yaml | 20 +++++++++----------- arch/csr/Smcsrind/siselect.yaml | 28 +++++++++++++--------------- 7 files changed, 58 insertions(+), 71 deletions(-) diff --git a/arch/csr/Smcsrind/sireg.yaml b/arch/csr/Smcsrind/sireg.yaml index 7d6a74f37c..6e0972f39f 100644 --- a/arch/csr/Smcsrind/sireg.yaml +++ b/arch/csr/Smcsrind/sireg.yaml @@ -1,4 +1,3 @@ ---- # yaml-language-server: $schema=../../../schemas/csr_schema.json $schema: csr_schema.json# kind: csr diff --git a/arch/csr/Smcsrind/sireg2.yaml b/arch/csr/Smcsrind/sireg2.yaml index 9451585617..863910974f 100644 --- a/arch/csr/Smcsrind/sireg2.yaml +++ b/arch/csr/Smcsrind/sireg2.yaml @@ -1,4 +1,3 @@ ---- # yaml-language-server: $schema=../../../schemas/csr_schema.json $schema: csr_schema.json# kind: csr @@ -13,18 +12,17 @@ description: | indirectly based on the value held in the `siselect` CSR. The `sireg2` CSR provides access to a window of indirectly addressed registers. - The behavior of accesses to `sireg2` is determined by the currently selected - `siselect` value, which acts as an index into an alias space defined by the extension - utilizing this access method. This indirect mechanism allows software to access - an array of CSRs without consuming large contiguous blocks of the CSR address space. + The behavior of accesses to `sireg2` is determined by the value of `siselect`. + If `siselect` holds a value that corresponds to an implemented register, + the register is accessed as determined by the value of `siselect`. - When `siselect` contains a value that is not supported, access to `sireg2` is UNSPECIFIED, - and implementations are encouraged to raise an illegal instruction exception to aid in - debugging or software emulation. + When `siselect` holds an unsupported value, access to `sireg2` is UNSPECIFIED, + and implementations are encouraged to raise an illegal instruction exception + to facilitate debugging or software emulation. - The indirect access mechanism is useful for CSR arrays, such as counters or - performance registers, and ensures a scalable way to interact with dynamically - indexed register sets. + This indirect access mechanism allows efficient access to an array of CSRs + without allocating large contiguous blocks of CSR address space. It is useful + for arrays such as performance counters and other register sets. fields: Data: diff --git a/arch/csr/Smcsrind/sireg3.yaml b/arch/csr/Smcsrind/sireg3.yaml index 0d0eb42283..420801c4b6 100644 --- a/arch/csr/Smcsrind/sireg3.yaml +++ b/arch/csr/Smcsrind/sireg3.yaml @@ -1,4 +1,3 @@ ---- # yaml-language-server: $schema=../../../schemas/csr_schema.json $schema: csr_schema.json# kind: csr @@ -13,18 +12,17 @@ description: | indirectly based on the value held in the `siselect` CSR. The `sireg3` CSR provides access to a window of indirectly addressed registers. - The behavior of accesses to `sireg3` is determined by the currently selected - `siselect` value, which acts as an index into an alias space defined by the extension - utilizing this access method. This indirect mechanism allows software to access - an array of CSRs without consuming large contiguous blocks of the CSR address space. + The behavior of accesses to `sireg3` is determined by the value of `siselect`. + If `siselect` holds a value that corresponds to an implemented register, + the register is accessed as determined by the value of `siselect`. - When `siselect` contains a value that is not supported, access to `sireg3` is UNSPECIFIED, - and implementations are encouraged to raise an illegal instruction exception to aid in - debugging or software emulation. + When `siselect` holds an unsupported value, access to `sireg3` is UNSPECIFIED, + and implementations are encouraged to raise an illegal instruction exception + to facilitate debugging or software emulation. - The indirect access mechanism is useful for CSR arrays, such as counters or - performance registers, and ensures a scalable way to interact with dynamically - indexed register sets. + This indirect access mechanism allows efficient access to an array of CSRs + without allocating large contiguous blocks of CSR address space. It is useful + for arrays such as performance counters and other register sets. fields: Data: diff --git a/arch/csr/Smcsrind/sireg4.yaml b/arch/csr/Smcsrind/sireg4.yaml index f2586dd8b3..3f0484e3a6 100644 --- a/arch/csr/Smcsrind/sireg4.yaml +++ b/arch/csr/Smcsrind/sireg4.yaml @@ -1,4 +1,3 @@ ---- # yaml-language-server: $schema=../../../schemas/csr_schema.json $schema: csr_schema.json# kind: csr @@ -13,18 +12,17 @@ description: | indirectly based on the value held in the `siselect` CSR. The `sireg4` CSR provides access to a window of indirectly addressed registers. - The behavior of accesses to `sireg4` is determined by the currently selected - `siselect` value, which acts as an index into an alias space defined by the extension - utilizing this access method. This indirect mechanism allows software to access - an array of CSRs without consuming large contiguous blocks of the CSR address space. + The behavior of accesses to `sireg4` is determined by the value of `siselect`. + If `siselect` holds a value that corresponds to an implemented register, + the register is accessed as determined by the value of `siselect`. - When `siselect` contains a value that is not supported, access to `sireg4` is UNSPECIFIED, - and implementations are encouraged to raise an illegal instruction exception to aid in - debugging or software emulation. + When `siselect` holds an unsupported value, access to `sireg4` is UNSPECIFIED, + and implementations are encouraged to raise an illegal instruction exception + to facilitate debugging or software emulation. - The indirect access mechanism is useful for CSR arrays, such as counters or - performance registers, and ensures a scalable way to interact with dynamically - indexed register sets. + This indirect access mechanism allows efficient access to an array of CSRs + without allocating large contiguous blocks of CSR address space. It is useful + for arrays such as performance counters and other register sets. fields: Data: diff --git a/arch/csr/Smcsrind/sireg5.yaml b/arch/csr/Smcsrind/sireg5.yaml index 2816a50b5a..7ca1070287 100644 --- a/arch/csr/Smcsrind/sireg5.yaml +++ b/arch/csr/Smcsrind/sireg5.yaml @@ -1,4 +1,3 @@ ---- # yaml-language-server: $schema=../../../schemas/csr_schema.json $schema: csr_schema.json# kind: csr @@ -13,18 +12,17 @@ description: | indirectly based on the value held in the `siselect` CSR. The `sireg5` CSR provides access to a window of indirectly addressed registers. - The behavior of accesses to `sireg5` is determined by the currently selected - `siselect` value, which acts as an index into an alias space defined by the extension - utilizing this access method. This indirect mechanism allows software to access - an array of CSRs without consuming large contiguous blocks of the CSR address space. + The behavior of accesses to `sireg5` is determined by the value of `siselect`. + If `siselect` holds a value that corresponds to an implemented register, + the register is accessed as determined by the value of `siselect`. - When `siselect` contains a value that is not supported, access to `sireg5` is UNSPECIFIED, - and implementations are encouraged to raise an illegal instruction exception to aid in - debugging or software emulation. + When `siselect` holds an unsupported value, access to `sireg5` is UNSPECIFIED, + and implementations are encouraged to raise an illegal instruction exception + to facilitate debugging or software emulation. - The indirect access mechanism is useful for CSR arrays, such as counters or - performance registers, and ensures a scalable way to interact with dynamically - indexed register sets. + This indirect access mechanism allows efficient access to an array of CSRs + without allocating large contiguous blocks of CSR address space. It is useful + for arrays such as performance counters and other register sets. fields: Data: diff --git a/arch/csr/Smcsrind/sireg6.yaml b/arch/csr/Smcsrind/sireg6.yaml index 5ba4cc3309..8189081b30 100644 --- a/arch/csr/Smcsrind/sireg6.yaml +++ b/arch/csr/Smcsrind/sireg6.yaml @@ -1,4 +1,3 @@ ---- # yaml-language-server: $schema=../../../schemas/csr_schema.json $schema: csr_schema.json# kind: csr @@ -13,18 +12,17 @@ description: | indirectly based on the value held in the `siselect` CSR. The `sireg6` CSR provides access to a window of indirectly addressed registers. - The behavior of accesses to `sireg6` is determined by the currently selected - `siselect` value, which acts as an index into an alias space defined by the extension - utilizing this access method. This indirect mechanism allows software to access - an array of CSRs without consuming large contiguous blocks of the CSR address space. + The behavior of accesses to `sireg6` is determined by the value of `siselect`. + If `siselect` holds a value that corresponds to an implemented register, + the register is accessed as determined by the value of `siselect`. - When `siselect` contains a value that is not supported, access to `sireg6` is UNSPECIFIED, - and implementations are encouraged to raise an illegal instruction exception to aid in - debugging or software emulation. + When `siselect` holds an unsupported value, access to `sireg6` is UNSPECIFIED, + and implementations are encouraged to raise an illegal instruction exception + to facilitate debugging or software emulation. - The indirect access mechanism is useful for CSR arrays, such as counters or - performance registers, and ensures a scalable way to interact with dynamically - indexed register sets. + This indirect access mechanism allows efficient access to an array of CSRs + without allocating large contiguous blocks of CSR address space. It is useful + for arrays such as performance counters and other register sets. fields: Data: diff --git a/arch/csr/Smcsrind/siselect.yaml b/arch/csr/Smcsrind/siselect.yaml index 7edc3aff9a..d9c2687666 100644 --- a/arch/csr/Smcsrind/siselect.yaml +++ b/arch/csr/Smcsrind/siselect.yaml @@ -1,4 +1,3 @@ ---- # yaml-language-server: $schema=../../../schemas/csr_schema.json $schema: csr_schema.json# kind: csr @@ -10,24 +9,23 @@ length: SXLEN definedBy: Sscsrind description: | The `siselect` CSR is a supervisor-level register used to select which indirectly - accessed register is targeted via the `sireg*` alias CSRs. The `siselect` value acts - as an index into an extension-defined space of registers, enabling access to a wide - range of CSR-like state without consuming contiguous CSR numbers. + accessed register is targeted via the `sireg*` alias CSRs. The value in `siselect` + acts as an index into an extension-defined space of registers, allowing access to + a wide range of CSR-like state without allocating contiguous CSR numbers. - This mechanism allows software to efficiently access arrays of register state - through indexing, removing the need for large blocks of CSR address space and - reducing software complexity. The `siselect` CSR is typically used alongside - `sireg` through `sireg6` to access registers indirectly. + This indirect access mechanism enables software to efficiently access register arrays + without consuming large chunks of CSR address space. The `siselect` CSR works alongside + the `sireg*` alias CSRs to facilitate this indexing and indirect access method. - The minimum supported value range for `siselect` is 0–0xFFF. Future extensions may - define larger ranges. Values with the most significant bit set (bit SXLEN - 1 = 1) - are reserved for custom use, while those with the MSB cleared are designated for - standard usage and should only be used by ratified extensions. + The minimum supported value range for `siselect` is 0–0xFFF, though future extensions + may define larger ranges. Values with the most-significant bit set (bit SXLEN - 1 = 1) + are reserved for custom use, while values with the most-significant bit cleared are + designated for standard use by ratified extensions. When `siselect` holds a value that is not implemented, accesses to `sireg*` are UNSPECIFIED. It is RECOMMENDED that implementations raise an illegal instruction - exception in such cases to support emulation or error detection. Implementations - may make additional behaviors subject to platform or profile specifications. + exception in such cases to support emulation or error detection. Platforms or profiles + may define additional behaviors. fields: Select Value: @@ -36,6 +34,6 @@ fields: type: RW description: | Index value selecting the target register accessed through `sireg*`. - Acts as an indirect register selector. Values are extension-defined. + It serves as an indirect register selector. Values are defined by the extension. reset_value: UNDEFINED_LEGAL sw_read(): | From f2fa9a443ab59cce35e1b67571fc33b62e31bccc Mon Sep 17 00:00:00 2001 From: syedowaisalishah Date: Thu, 10 Apr 2025 13:38:15 +0000 Subject: [PATCH 10/29] Corrected Smcsrind CSR YAML files for: vsiselect, vsireg[1-6] --- arch/csr/Smcsrind/vsireg.yaml | 3 +-- arch/csr/Smcsrind/vsireg2.yaml | 24 +++++++++++---------- arch/csr/Smcsrind/vsireg3.yaml | 24 ++++++++++----------- arch/csr/Smcsrind/vsireg4.yaml | 23 ++++++++++---------- arch/csr/Smcsrind/vsireg5.yaml | 21 ++++++++----------- arch/csr/Smcsrind/vsireg6.yaml | 23 ++++++++++---------- arch/csr/Smcsrind/vsiselect.yaml | 36 +++++++++++++------------------- 7 files changed, 74 insertions(+), 80 deletions(-) diff --git a/arch/csr/Smcsrind/vsireg.yaml b/arch/csr/Smcsrind/vsireg.yaml index 28b6047e14..ba7ac32bf6 100644 --- a/arch/csr/Smcsrind/vsireg.yaml +++ b/arch/csr/Smcsrind/vsireg.yaml @@ -1,4 +1,3 @@ ---- # yaml-language-server: $schema=../../../schemas/csr_schema.json $schema: csr_schema.json# kind: csr @@ -8,7 +7,7 @@ address: 0x251 virtual_address: 0x251 priv_mode: VS length: VSXLEN -definedBy: Sscsrind +definedBy: Smcsrind description: | The `vsireg` CSR is one of several alias registers used to indirectly access virtual supervisor-level register state. Access to a specific target register diff --git a/arch/csr/Smcsrind/vsireg2.yaml b/arch/csr/Smcsrind/vsireg2.yaml index 0c6ccda3b3..0af14f327b 100644 --- a/arch/csr/Smcsrind/vsireg2.yaml +++ b/arch/csr/Smcsrind/vsireg2.yaml @@ -1,4 +1,3 @@ ---- # yaml-language-server: $schema=../../../schemas/csr_schema.json $schema: csr_schema.json# kind: csr @@ -8,21 +7,24 @@ address: 0x252 virtual_address: 0x252 priv_mode: VS length: VSXLEN -definedBy: Sscsrind +definedBy: Smcsrind description: | - The `vsireg2` CSR is one of the virtual supervisor-level alias registers used + The `vsireg2` CSR is one of several virtual supervisor-level alias registers used to indirectly access register state based on the value held in the `vsiselect` - CSR. This aliasing mechanism provides a means for indexed access to an array - of registers, reducing the need to reserve large, contiguous blocks of CSR - address space. + CSR. This alias mechanism enables efficient access to register state by indexing + into an alias space defined by the extension utilizing this access method. - The value in `vsiselect` determines the behavior of `vsireg2`, including the - register that is read or written. Each `vsireg*` CSR behaves as a data window - to register state selected by the `vsiselect` index. + The value in `vsiselect` determines the register being accessed through `vsireg2`. + The `vsiselect` value serves as an index into a virtualized alias space, providing + access to registers without consuming contiguous CSR address ranges. If `vsiselect` holds a value that is not implemented, the behavior of `vsireg2` - is UNSPECIFIED. Implementations are encouraged to raise a virtual instruction - exception to support debugging and potential emulation. + is UNSPECIFIED. It is RECOMMENDED that implementations raise a virtual instruction + exception for such accesses to facilitate debugging and emulation. + + The access behavior for each `vsiselect` + `vsireg2` pair is defined by the + extension that owns the `vsiselect` value. Ordinarily, the alias register + either accesses architectural state, reads zero, or raises an exception. fields: Data: diff --git a/arch/csr/Smcsrind/vsireg3.yaml b/arch/csr/Smcsrind/vsireg3.yaml index ac428ce0fc..16238c0bb9 100644 --- a/arch/csr/Smcsrind/vsireg3.yaml +++ b/arch/csr/Smcsrind/vsireg3.yaml @@ -1,4 +1,3 @@ ---- # yaml-language-server: $schema=../../../schemas/csr_schema.json $schema: csr_schema.json# kind: csr @@ -10,24 +9,25 @@ priv_mode: VS length: VSXLEN definedBy: Smcsrind description: | - The `vsireg3` CSR is part of the virtual supervisor-level indirect access - mechanism and serves as one of the alias registers indexed by the `vsiselect` - CSR. + The `vsireg3` CSR is a virtual supervisor-level alias register used to indirectly + access register state based on the value held in the `vsiselect` CSR. This CSR + forms part of the virtualized alias register space, enabling efficient access to + register arrays in VS-mode without consuming large contiguous CSR address ranges. - The indirect CSR access model enables software in VS-mode to interact with - register arrays using a select value, improving scalability and reducing CSR - address space consumption. + The value of `vsiselect` determines which register is accessed via `vsireg3`. + The `vsiselect` CSR acts as an index into the alias space, facilitating scalable + access to a range of registers. - When `vsiselect` holds an unimplemented value, accesses to `vsireg3` are - UNSPECIFIED, and it is recommended that implementations raise a virtual - instruction exception to facilitate software emulation or trap-based - handling. + If `vsiselect` holds a value that is not implemented, the behavior of `vsireg3` + is UNSPECIFIED. It is recommended that implementations raise a virtual instruction + exception in such cases to support debugging and software emulation. fields: Data: location_rv32: 31-0 location_rv64: 63-0 type: RW - description: Data read or written based on the `vsiselect` value. + description: | + The data read or written based on the currently selected `vsiselect` value. reset_value: UNDEFINED_LEGAL sw_read(): | diff --git a/arch/csr/Smcsrind/vsireg4.yaml b/arch/csr/Smcsrind/vsireg4.yaml index 37413a8d08..c6b05633bb 100644 --- a/arch/csr/Smcsrind/vsireg4.yaml +++ b/arch/csr/Smcsrind/vsireg4.yaml @@ -1,4 +1,3 @@ ---- # yaml-language-server: $schema=../../../schemas/csr_schema.json $schema: csr_schema.json# kind: csr @@ -10,23 +9,25 @@ priv_mode: VS length: VSXLEN definedBy: Smcsrind description: | - The `vsireg4` CSR is a virtual supervisor-level alias register accessed - indirectly via the `vsiselect` CSR. It is part of a set of CSRs that form a - scalable mechanism for register array access without requiring dedicated - address space for each individual register. + The `vsireg4` CSR is a virtual supervisor-level alias register used for indirect + access to register state based on the value held in the `vsiselect` CSR. It is part of + a set of alias registers that allow efficient access to register arrays in VS-mode without + consuming large contiguous CSR address ranges. - In RV32 environments where a register may be 64-bit, `vsireg4` can be used - to access the upper 32 bits of a split register, in conjunction with other - alias CSRs such as `vsireg` or `vsireg2` for the lower bits. + In RV32 environments, where registers may be 64-bit, `vsireg4` is typically used to + access the upper 32 bits of a 64-bit register, in combination with other alias CSRs like + `vsireg` and `vsireg2`, which handle the lower 32 bits. - Accesses to `vsireg4` while `vsiselect` holds an unsupported value are - UNSPECIFIED and should raise a virtual instruction exception. + If the value in `vsiselect` is unsupported or unimplemented, access to `vsireg4` is + UNSPECIFIED. Implementations are encouraged to raise a virtual instruction exception to + facilitate debugging and software emulation. fields: Data: location_rv32: 31-0 location_rv64: 63-0 type: RW - description: Data read or written based on the `vsiselect` value. + description: | + Data read or written based on the currently selected `vsiselect` value. reset_value: UNDEFINED_LEGAL sw_read(): | diff --git a/arch/csr/Smcsrind/vsireg5.yaml b/arch/csr/Smcsrind/vsireg5.yaml index 76e3e112ac..65fa4f687e 100644 --- a/arch/csr/Smcsrind/vsireg5.yaml +++ b/arch/csr/Smcsrind/vsireg5.yaml @@ -1,4 +1,3 @@ ---- # yaml-language-server: $schema=../../../schemas/csr_schema.json $schema: csr_schema.json# kind: csr @@ -10,23 +9,21 @@ priv_mode: VS length: VSXLEN definedBy: Smcsrind description: | - The `vsireg5` CSR is an alias used in the virtual supervisor-level indirect - register access model. It provides indexed access to register state based on - the currently selected value in `vsiselect`. + The `vsireg5` CSR is part of the virtual supervisor-level indirect register access + mechanism, providing indexed access to register state based on the value held in the + `vsiselect` CSR. It enables software in VS-mode to access register arrays efficiently, + avoiding the need to allocate large, contiguous CSR address ranges. - This CSR, along with other `vsireg*` aliases, helps provide consistent access - patterns to extended register arrays while maintaining efficient usage of the - limited CSR address space. - - If the selected `vsiselect` value is not implemented, behavior is - UNSPECIFIED, and it is recommended that a virtual instruction exception be - raised. + When the `vsiselect` value points to an unimplemented register, access to `vsireg5` + is UNSPECIFIED. Implementations are encouraged to raise a virtual instruction exception + to support software emulation or error handling. fields: Data: location_rv32: 31-0 location_rv64: 63-0 type: RW - description: Data read or written based on the `vsiselect` value. + description: | + The data read or written from the register selected by the value in `vsiselect`. reset_value: UNDEFINED_LEGAL sw_read(): | diff --git a/arch/csr/Smcsrind/vsireg6.yaml b/arch/csr/Smcsrind/vsireg6.yaml index 67160e8ef0..564af70062 100644 --- a/arch/csr/Smcsrind/vsireg6.yaml +++ b/arch/csr/Smcsrind/vsireg6.yaml @@ -1,4 +1,3 @@ ---- # yaml-language-server: $schema=../../../schemas/csr_schema.json $schema: csr_schema.json# kind: csr @@ -10,23 +9,25 @@ priv_mode: VS length: VSXLEN definedBy: Smcsrind description: | - The `vsireg6` CSR is the final alias in the virtual supervisor-level set of - indirect access CSRs. Like its counterparts, it is accessed indirectly through - the `vsiselect` CSR and provides a data window into a selected register. + The `vsireg6` CSR is part of the virtual supervisor-level indirect register access + mechanism. It is used for accessing register state based on the value held in the + `vsiselect` CSR. `vsireg6` acts as one of the alias registers in the system, providing + indirect access to a register selected via `vsiselect`. - For 64-bit register arrays in RV32 environments, `vsireg6` may be used for - accessing the upper 32 bits, while lower aliases such as `vsireg3` provide the - corresponding lower half. + In RV32 environments, `vsireg6` is typically used for accessing the upper 32 bits of + a 64-bit register array, while other aliases, such as `vsireg3`, provide access to + the lower 32 bits. - Access to `vsireg6` while `vsiselect` holds an unsupported value is - UNSPECIFIED. Virtual instruction exceptions are recommended for unsupported - access cases. + When `vsiselect` holds an unimplemented value, the behavior of accesses to `vsireg6` + is UNSPECIFIED. Implementations are encouraged to raise a virtual instruction exception + to support emulation or error handling. fields: Data: location_rv32: 31-0 location_rv64: 63-0 type: RW - description: Data read or written based on the `vsiselect` value. + description: | + The data read or written based on the currently selected `vsiselect` value. reset_value: UNDEFINED_LEGAL sw_read(): | diff --git a/arch/csr/Smcsrind/vsiselect.yaml b/arch/csr/Smcsrind/vsiselect.yaml index aa413c9fda..0eb88bed0d 100644 --- a/arch/csr/Smcsrind/vsiselect.yaml +++ b/arch/csr/Smcsrind/vsiselect.yaml @@ -1,4 +1,3 @@ ---- # yaml-language-server: $schema=../../../schemas/csr_schema.json $schema: csr_schema.json# kind: csr @@ -10,34 +9,29 @@ priv_mode: VS length: VSXLEN definedBy: Smcsrind description: | - The `vsireg` CSR is a virtual supervisor-level alias register used to access - register state indirectly, based on the index specified in the `vsiselect` CSR. - This mechanism provides a scalable and efficient way to expose a large number - of virtual supervisor-level registers without consuming contiguous CSR address - space. + The `vsiselect` CSR is a virtual supervisor-level register that selects which + register is accessed indirectly via the `vsireg*` alias registers. The value + held in `vsiselect` acts as an index into an alias space defined by the + extension utilizing this access method. - The value held in `vsiselect` determines which internal register is accessed - via `vsireg`. This allows for software to access register arrays by index rather - than by fixed CSR numbers, enabling more compact and flexible register access - patterns. + This CSR allows software in VS-mode to access register arrays by index rather + than by fixed CSR numbers, improving scalability and reducing the need for large + contiguous CSR address space. The `vsiselect` CSR is typically used alongside + `vsireg` through `vsireg6` to access virtual supervisor-level registers indirectly. - When the value in `vsiselect` corresponds to a defined and implemented select - value, the behavior of read and write accesses to `vsireg` is defined by the - extension to which the `vsiselect` value is allocated. If the value in `vsiselect` - is not supported, the behavior is UNSPECIFIED; however, it is recommended that - implementations raise a virtual instruction exception to facilitate debugging - and enable software emulation. + When `vsiselect` holds a value that corresponds to an unimplemented register, + the behavior is UNSPECIFIED. Implementations are encouraged to raise a virtual + instruction exception to support software emulation and debugging. + + The indirect access mechanism enables more flexible access patterns for virtual + machines and reduces the complexity of implementing CSR access. - This indirect access model helps virtual machines access CSR state without - direct mapping of each CSR, reducing implementation complexity and preserving - CSR encoding space. fields: Data: location_rv32: 31-0 location_rv64: 63-0 type: RW description: | - The data read from or written to the register selected by the current - `vsiselect` value. + The index value selecting the register accessed through the `vsireg*` alias registers. reset_value: UNDEFINED_LEGAL sw_read(): | From f3539d915060af4e2df8cae8a85f4c06bbfee98f Mon Sep 17 00:00:00 2001 From: syedowaisalishah Date: Thu, 10 Apr 2025 14:41:01 +0000 Subject: [PATCH 11/29] Corrected Smcsrind extesnion and Sscsrind extension yaml --- arch/ext/Smcsrind.yaml | 23 ++++------------------- arch/ext/Sscsrind.yaml | 23 ++++++----------------- 2 files changed, 10 insertions(+), 36 deletions(-) diff --git a/arch/ext/Smcsrind.yaml b/arch/ext/Smcsrind.yaml index bd61edc812..16b3e687d4 100644 --- a/arch/ext/Smcsrind.yaml +++ b/arch/ext/Smcsrind.yaml @@ -6,32 +6,17 @@ name: Smcsrind long_name: Machine Indirect CSR Access (Smcsrind) description: | The `Smcsrind` extension defines indirect access to CSRs, allowing registers to be accessed through - an index value (`miselect`) rather than using a fixed CSR number. This reduces the need for allocating - large chunks of CSR address space, making it more scalable and flexible. - - `Smcsrind` enables accessing an array of CSRs by index through dedicated `miselect` and `mireg*` registers - for machine-level access. The supervisor-level counterpart, `Sscsrind`, provides similar functionality but - without machine-level CSRs. - - This extension is beneficial for accessing a set of registers that are not statically defined in the CSR space - and enables more flexible register allocation. - - The machine-level registers are accessed through `miselect` and `mireg*` registers, while supervisor-level - registers are accessed through `siselect` and `sireg*` registers. + an index value (`miselect`) instead of using fixed CSR numbers. This mechanism reduces the need for + large CSR address space allocation, making it more scalable and flexible. It enables the access of a set + of registers that are not statically defined in the CSR space. Machine-level registers are accessed + through `miselect` and `mireg*`, while supervisor-level registers are accessed through `siselect` and `sireg*`. versions: - version: "1.0.0" state: ratified ratification_date: "2024-11" url: "https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-isa-release-482805d-2025-03-25" - implies: - name: Smcsrind - version: "1.0.0" requires: allOf: - name: S version: ~> 1.13 - changes: - - Introduced indirect CSR access using `miselect`, `mireg*` for machine-level, and `siselect`, `sireg*` for supervisor-level CSRs. - - Defines the address spaces for indirect access in both machine and supervisor levels. - - Supports custom extension registers for each mode via indirect access diff --git a/arch/ext/Sscsrind.yaml b/arch/ext/Sscsrind.yaml index d77280609f..12637d838d 100644 --- a/arch/ext/Sscsrind.yaml +++ b/arch/ext/Sscsrind.yaml @@ -6,33 +6,22 @@ name: Sscsrind long_name: Supervisor Indirect CSR Access (Sscsrind) description: | The `Sscsrind` extension extends the CSR access mechanism for Supervisor mode by enabling indirect - access to a set of registers. Similar to `Smcsrind`, this extension allows registers to be accessed through - an index value (`siselect`) instead of using fixed CSR numbers. This flexibility helps manage the CSR space - efficiently and provides a more scalable mechanism for accessing supervisor-level registers. + access to Supervisor-level registers through the `siselect` CSR. This extension provides efficient access + to an array of registers without allocating large contiguous blocks of CSR address space. Registers are + accessed by index, offering a more scalable approach to managing Supervisor-level registers. - `Sscsrind` registers are accessed indirectly via dedicated `siselect` and `sireg*` registers, providing - software with the ability to access an array of registers by index. This extension is essential for handling - large numbers of registers and reduces the need for allocating large chunks of CSR address space for each - individual register. - - While `Smcsrind` applies to machine-level access, `Sscsrind` targets Supervisor-level registers and behaves - similarly, but with the exclusion of machine-level CSRs. + Similar to the `Smcsrind` extension, this mechanism reduces the need for fixed CSR numbers, supporting + custom extensions that manage Supervisor-level register access through the use of `siselect` and `sireg*` + registers. versions: - version: "1.0.0" state: ratified ratification_date: "2024-11" url: "https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-isa-release-482805d-2025-03-25" - implies: - name: Sscsrind - version: "1.0.0" requires: allOf: - name: S version: ~> 1.13 - name: Smcsrind version: ~> 1.0 - changes: - - Introduced indirect CSR access for Supervisor-level using `siselect` and `sireg*` registers. - - Enables access to arrays of registers in Supervisor mode, making it more efficient to handle large numbers of registers. - - Supports custom extensions with indirect access for supervisor-level registers. From 46ec8b221df894eeb6efc6598d86fbda4f40d3e3 Mon Sep 17 00:00:00 2001 From: syedowaisalishah Date: Sun, 20 Apr 2025 13:43:56 +0000 Subject: [PATCH 12/29] Corrected Smcsrind extesnion and Sscsrind extension yaml and its csr yaml --- arch/csr/Smcsrind/mireg.yaml | 22 ++++++++++++++------- arch/csr/Smcsrind/mireg2.yaml | 2 +- arch/csr/Smcsrind/mireg3.yaml | 2 +- arch/csr/Smcsrind/mireg4.yaml | 2 +- arch/csr/Smcsrind/mireg5.yaml | 2 +- arch/csr/Smcsrind/mireg6.yaml | 2 +- arch/csr/Smcsrind/miselect.yaml | 2 +- arch/csr/Smcsrind/sireg.yaml | 25 ++++++++++++------------ arch/csr/Smcsrind/sireg2.yaml | 33 ++++++++++++++++++++------------ arch/csr/Smcsrind/sireg3.yaml | 8 ++++++++ arch/csr/Smcsrind/sireg4.yaml | 33 ++++++++++++++++++++------------ arch/csr/Smcsrind/sireg5.yaml | 32 +++++++++++++++++++------------ arch/csr/Smcsrind/sireg6.yaml | 33 ++++++++++++++++++++------------ arch/csr/Smcsrind/siselect.yaml | 29 +++++++++++----------------- arch/csr/Smcsrind/vsireg.yaml | 2 +- arch/csr/Smcsrind/vsireg2.yaml | 25 ++++++++++-------------- arch/csr/Smcsrind/vsireg3.yaml | 2 +- arch/csr/Smcsrind/vsireg4.yaml | 2 +- arch/csr/Smcsrind/vsireg5.yaml | 2 +- arch/csr/Smcsrind/vsireg6.yaml | 2 +- arch/csr/Smcsrind/vsiselect.yaml | 2 +- arch/ext/Smcsrind.yaml | 32 ++++++++++++++++++++++++++----- arch/ext/Sscsrind.yaml | 33 ++++++++++++++++++++++++-------- 23 files changed, 203 insertions(+), 126 deletions(-) diff --git a/arch/csr/Smcsrind/mireg.yaml b/arch/csr/Smcsrind/mireg.yaml index 79f60836b8..aa40ca00cc 100644 --- a/arch/csr/Smcsrind/mireg.yaml +++ b/arch/csr/Smcsrind/mireg.yaml @@ -8,17 +8,25 @@ priv_mode: M length: MXLEN definedBy: Smcsrind description: | - The `mireg` CSR is the machine-level indirect alias register used to access - register state as determined by the index held in `miselect`. This CSR is typically used - to access the register state of a CSR selected by `miselect` value. + The `mireg` CSR is the machine-level indirect alias register used to access another + CSR's state indirectly upon a read or write, as determined by the value in `miselect`. - If the value in `miselect` is not implemented, access is UNSPECIFIED. Implementations - are encouraged to raise an illegal instruction exception in such cases. + Accessing `mireg` when `miselect` holds a value that is not implemented results in + UNSPECIFIED behavior. Implementations are encouraged to raise an illegal instruction + exception in such cases, to help detect software bugs. Platform and profile specifications + may impose additional requirements for such cases. + + When `miselect` holds a valid and implemented value, the behavior of `mireg` is defined + by the extension to which that `miselect` value is allocated. Ordinarily, `mireg` will access + register state, return read-only zero, or raise an illegal instruction exception. + + On RV32 systems, if an indirectly addressed register is 64 bits wide, it is recommended that + the lower 32 bits are accessed through `mireg` and the upper 32 bits through `mireg4`. fields: - Count: + VALUE: location_rv32: 31-0 location_rv64: 63-0 type: RW - description: Register state data of CSR selected by `miselect` value. + description: Register state of the CSR selected by the current `miselect` value. reset_value: UNDEFINED_LEGAL sw_read(): | diff --git a/arch/csr/Smcsrind/mireg2.yaml b/arch/csr/Smcsrind/mireg2.yaml index 56fec951f7..ed3f167267 100644 --- a/arch/csr/Smcsrind/mireg2.yaml +++ b/arch/csr/Smcsrind/mireg2.yaml @@ -18,7 +18,7 @@ description: | encouraged that implementations raise an illegal instruction exception in such cases. fields: - Count: + VALUE: location_rv32: 31-0 location_rv64: 63-0 type: RW diff --git a/arch/csr/Smcsrind/mireg3.yaml b/arch/csr/Smcsrind/mireg3.yaml index e9fe657e10..b1174ece3d 100644 --- a/arch/csr/Smcsrind/mireg3.yaml +++ b/arch/csr/Smcsrind/mireg3.yaml @@ -18,7 +18,7 @@ description: | encouraged that implementations raise an illegal instruction exception in such cases. fields: - Count: + VALUE: location_rv32: 31-0 location_rv64: 63-0 type: RW diff --git a/arch/csr/Smcsrind/mireg4.yaml b/arch/csr/Smcsrind/mireg4.yaml index 1556b3573e..ddbcf16a13 100644 --- a/arch/csr/Smcsrind/mireg4.yaml +++ b/arch/csr/Smcsrind/mireg4.yaml @@ -18,7 +18,7 @@ description: | are encouraged to raise an illegal instruction exception. fields: - Count: + VALUE: location_rv32: 31-0 location_rv64: 63-0 type: RW diff --git a/arch/csr/Smcsrind/mireg5.yaml b/arch/csr/Smcsrind/mireg5.yaml index 71177b3eba..cbfaf4cb29 100644 --- a/arch/csr/Smcsrind/mireg5.yaml +++ b/arch/csr/Smcsrind/mireg5.yaml @@ -18,7 +18,7 @@ description: | are encouraged to raise an illegal instruction exception. fields: - Count: + VALUE: location_rv32: 31-0 location_rv64: 63-0 type: RW diff --git a/arch/csr/Smcsrind/mireg6.yaml b/arch/csr/Smcsrind/mireg6.yaml index b2449abebb..6f4a8ec634 100644 --- a/arch/csr/Smcsrind/mireg6.yaml +++ b/arch/csr/Smcsrind/mireg6.yaml @@ -18,7 +18,7 @@ description: | are encouraged to raise an illegal instruction exception fields: - Count: + VALUE: location_rv32: 31-0 location_rv64: 63-0 type: RW diff --git a/arch/csr/Smcsrind/miselect.yaml b/arch/csr/Smcsrind/miselect.yaml index 93101cd283..10026e02a1 100644 --- a/arch/csr/Smcsrind/miselect.yaml +++ b/arch/csr/Smcsrind/miselect.yaml @@ -25,7 +25,7 @@ description: | exception to support robust error handling and software emulation. fields: - Select Value: + Value: location_rv32: 31-0 location_rv64: 63-0 type: RW diff --git a/arch/csr/Smcsrind/sireg.yaml b/arch/csr/Smcsrind/sireg.yaml index 6e0972f39f..4780ea58de 100644 --- a/arch/csr/Smcsrind/sireg.yaml +++ b/arch/csr/Smcsrind/sireg.yaml @@ -8,22 +8,21 @@ priv_mode: S length: SXLEN definedBy: Sscsrind description: | - The `sireg` CSR is a supervisor-level alias register used to access register state - indirectly based on the value held in the `siselect` CSR. The `sireg` CSR provides - access to a window of indirectly addressed registers. + Access to `sireg` from M-mode or S-mode while `siselect` holds a number in a + standard-defined and implemented range results in specific behavior that, for each combination of + `siselect` and `sireg`, is defined by the extension to which the `siselect` value is allocated. - The behavior of accesses to `sireg` is determined by the currently selected - `siselect` value, which acts as an index into an alias space defined by the extension - utilizing this access method. This indirect mechanism allows software to access - an array of CSRs without consuming large contiguous blocks of the CSR address space. + [Note] + Ordinarily, `sireg` will access register state, access read-only 0 state, or, unless + executing in a virtual machine (covered in the next section), raise an illegal instruction + exception. - When `siselect` contains a value that is not supported, access to `sireg` is UNSPECIFIED, - and implementations are encouraged to raise an illegal instruction exception to aid in - debugging or software emulation. + Note that the widths of `siselect` and `sireg` are always the current XLEN rather than SXLEN. Hence, + for example, if MXLEN = 64 and SXLEN = 32, then this register is 64 bits when the current + privilege mode is M (running RV64 code) but 32 bits when the privilege mode is S (RV32 code). - The indirect access mechanism is useful for CSR arrays, such as counters or - performance registers, and ensures a scalable way to interact with dynamically - indexed register sets. + The behavior upon accessing `sireg` from M-mode or S-mode, while `siselect` holds a value that is + not implemented at supervisor level, is UNSPECIFIED. fields: Data: diff --git a/arch/csr/Smcsrind/sireg2.yaml b/arch/csr/Smcsrind/sireg2.yaml index 863910974f..ed287069a9 100644 --- a/arch/csr/Smcsrind/sireg2.yaml +++ b/arch/csr/Smcsrind/sireg2.yaml @@ -8,21 +8,30 @@ priv_mode: S length: SXLEN definedBy: Sscsrind description: | - The `sireg2` CSR is a supervisor-level alias register used to access register state - indirectly based on the value held in the `siselect` CSR. The `sireg2` CSR provides - access to a window of indirectly addressed registers. + Access to `sireg2` from M-mode or S-mode while `siselect` holds a number in a + standard-defined and implemented range results in specific behavior that, for each combination of + `siselect` and `sireg2`, is defined by the extension to which the `siselect` value is allocated. - The behavior of accesses to `sireg2` is determined by the value of `siselect`. - If `siselect` holds a value that corresponds to an implemented register, - the register is accessed as determined by the value of `siselect`. + [Note] + Ordinarily, `sireg2` will access register state, access read-only 0 state, or, unless + executing in a virtual machine (covered in the next section), raise an illegal instruction + exception. - When `siselect` holds an unsupported value, access to `sireg2` is UNSPECIFIED, - and implementations are encouraged to raise an illegal instruction exception - to facilitate debugging or software emulation. + Note that the widths of `siselect` and `sireg2` are always the current XLEN rather than SXLEN. Hence, + for example, if MXLEN = 64 and SXLEN = 32, then this register is 64 bits when the current + privilege mode is M (running RV64 code) but 32 bits when the privilege mode is S (RV32 code). - This indirect access mechanism allows efficient access to an array of CSRs - without allocating large contiguous blocks of CSR address space. It is useful - for arrays such as performance counters and other register sets. + The behavior upon accessing `sireg2` from M-mode or S-mode, while `siselect` holds a value that is + not implemented at supervisor level, is UNSPECIFIED. + + [Note] + It is recommended that implementations raise an illegal instruction exception for such + accesses, to facilitate possible emulation (by M-mode) of these accesses. + + [Note] + An extension is considered not to be implemented at supervisor level if machine level has + disabled the extension for S-mode, such as by the settings of certain fields in CSR + `menvcfg`, for example. fields: Data: diff --git a/arch/csr/Smcsrind/sireg3.yaml b/arch/csr/Smcsrind/sireg3.yaml index 420801c4b6..4fb5178371 100644 --- a/arch/csr/Smcsrind/sireg3.yaml +++ b/arch/csr/Smcsrind/sireg3.yaml @@ -24,6 +24,14 @@ description: | without allocating large contiguous blocks of CSR address space. It is useful for arrays such as performance counters and other register sets. + [Note] + It is recommended that implementations raise an illegal instruction exception for such + accesses, to facilitate possible emulation (by M-mode) of these accesses. + + [Note] + An extension is considered not to be implemented at supervisor level if machine level has + disabled the extension for S-mode, such as by the settings of certain fields in CSR + `menvcfg`, for example. fields: Data: location_rv32: 31-0 diff --git a/arch/csr/Smcsrind/sireg4.yaml b/arch/csr/Smcsrind/sireg4.yaml index 3f0484e3a6..598fb94062 100644 --- a/arch/csr/Smcsrind/sireg4.yaml +++ b/arch/csr/Smcsrind/sireg4.yaml @@ -8,21 +8,30 @@ priv_mode: S length: SXLEN definedBy: Sscsrind description: | - The `sireg4` CSR is a supervisor-level alias register used to access register state - indirectly based on the value held in the `siselect` CSR. The `sireg4` CSR provides - access to a window of indirectly addressed registers. + Access to `sireg4` from M-mode or S-mode while `siselect` holds a number in a + standard-defined and implemented range results in specific behavior that, for each combination of + `siselect` and `sireg4`, is defined by the extension to which the `siselect` value is allocated. - The behavior of accesses to `sireg4` is determined by the value of `siselect`. - If `siselect` holds a value that corresponds to an implemented register, - the register is accessed as determined by the value of `siselect`. + [Note] + Ordinarily, `sireg4` will access register state, access read-only 0 state, or, unless + executing in a virtual machine (covered in the next section), raise an illegal instruction + exception. - When `siselect` holds an unsupported value, access to `sireg4` is UNSPECIFIED, - and implementations are encouraged to raise an illegal instruction exception - to facilitate debugging or software emulation. + Note that the widths of `siselect` and `sireg4` are always the current XLEN rather than SXLEN. Hence, + for example, if MXLEN = 64 and SXLEN = 32, then this register is 64 bits when the current + privilege mode is M (running RV64 code) but 32 bits when the privilege mode is S (RV32 code). - This indirect access mechanism allows efficient access to an array of CSRs - without allocating large contiguous blocks of CSR address space. It is useful - for arrays such as performance counters and other register sets. + The behavior upon accessing `sireg4` from M-mode or S-mode, while `siselect` holds a value that is + not implemented at supervisor level, is UNSPECIFIED. + + [Note] + It is recommended that implementations raise an illegal instruction exception for such + accesses, to facilitate possible emulation (by M-mode) of these accesses. + + [Note] + An extension is considered not to be implemented at supervisor level if machine level has + disabled the extension for S-mode, such as by the settings of certain fields in CSR + `menvcfg`, for example. fields: Data: diff --git a/arch/csr/Smcsrind/sireg5.yaml b/arch/csr/Smcsrind/sireg5.yaml index 7ca1070287..8f258a22ad 100644 --- a/arch/csr/Smcsrind/sireg5.yaml +++ b/arch/csr/Smcsrind/sireg5.yaml @@ -8,22 +8,30 @@ priv_mode: S length: SXLEN definedBy: Sscsrind description: | - The `sireg5` CSR is a supervisor-level alias register used to access register state - indirectly based on the value held in the `siselect` CSR. The `sireg5` CSR provides - access to a window of indirectly addressed registers. + Access to `sireg5` from M-mode or S-mode while `siselect` holds a number in a + standard-defined and implemented range results in specific behavior that, for each combination of + `siselect` and `sireg5`, is defined by the extension to which the `siselect` value is allocated. - The behavior of accesses to `sireg5` is determined by the value of `siselect`. - If `siselect` holds a value that corresponds to an implemented register, - the register is accessed as determined by the value of `siselect`. + [Note] + Ordinarily, `sireg5` will access register state, access read-only 0 state, or, unless + executing in a virtual machine (covered in the next section), raise an illegal instruction + exception. - When `siselect` holds an unsupported value, access to `sireg5` is UNSPECIFIED, - and implementations are encouraged to raise an illegal instruction exception - to facilitate debugging or software emulation. + Note that the widths of `siselect` and `sireg5` are always the current XLEN rather than SXLEN. Hence, + for example, if MXLEN = 64 and SXLEN = 32, then this register is 64 bits when the current + privilege mode is M (running RV64 code) but 32 bits when the privilege mode is S (RV32 code). - This indirect access mechanism allows efficient access to an array of CSRs - without allocating large contiguous blocks of CSR address space. It is useful - for arrays such as performance counters and other register sets. + The behavior upon accessing `sireg5` from M-mode or S-mode, while `siselect` holds a value that is + not implemented at supervisor level, is UNSPECIFIED. + [Note] + It is recommended that implementations raise an illegal instruction exception for such + accesses, to facilitate possible emulation (by M-mode) of these accesses. + + [Note] + An extension is considered not to be implemented at supervisor level if machine level has + disabled the extension for S-mode, such as by the settings of certain fields in CSR + `menvcfg`, for example. fields: Data: location_rv32: 31-0 diff --git a/arch/csr/Smcsrind/sireg6.yaml b/arch/csr/Smcsrind/sireg6.yaml index 8189081b30..ac58da8fd5 100644 --- a/arch/csr/Smcsrind/sireg6.yaml +++ b/arch/csr/Smcsrind/sireg6.yaml @@ -8,21 +8,30 @@ priv_mode: S length: SXLEN definedBy: Sscsrind description: | - The `sireg6` CSR is a supervisor-level alias register used to access register state - indirectly based on the value held in the `siselect` CSR. The `sireg6` CSR provides - access to a window of indirectly addressed registers. + Access to `sireg6` from M-mode or S-mode while `siselect` holds a number in a + standard-defined and implemented range results in specific behavior that, for each combination of + `siselect` and `sireg6`, is defined by the extension to which the `siselect` value is allocated. - The behavior of accesses to `sireg6` is determined by the value of `siselect`. - If `siselect` holds a value that corresponds to an implemented register, - the register is accessed as determined by the value of `siselect`. + [Note] + Ordinarily, `sireg6` will access register state, access read-only 0 state, or, unless + executing in a virtual machine (covered in the next section), raise an illegal instruction + exception. - When `siselect` holds an unsupported value, access to `sireg6` is UNSPECIFIED, - and implementations are encouraged to raise an illegal instruction exception - to facilitate debugging or software emulation. + Note that the widths of `siselect` and `sireg6` are always the current XLEN rather than SXLEN. Hence, + for example, if MXLEN = 64 and SXLEN = 32, then this register is 64 bits when the current + privilege mode is M (running RV64 code) but 32 bits when the privilege mode is S (RV32 code). - This indirect access mechanism allows efficient access to an array of CSRs - without allocating large contiguous blocks of CSR address space. It is useful - for arrays such as performance counters and other register sets. + The behavior upon accessing `sireg6` from M-mode or S-mode, while `siselect` holds a value that is + not implemented at supervisor level, is UNSPECIFIED. + + [Note] + It is recommended that implementations raise an illegal instruction exception for such + accesses, to facilitate possible emulation (by M-mode) of these accesses. + + [Note] + An extension is considered not to be implemented at supervisor level if machine level has + disabled the extension for S-mode, such as by the settings of certain fields in CSR + `menvcfg`, for example. fields: Data: diff --git a/arch/csr/Smcsrind/siselect.yaml b/arch/csr/Smcsrind/siselect.yaml index d9c2687666..487b3965f7 100644 --- a/arch/csr/Smcsrind/siselect.yaml +++ b/arch/csr/Smcsrind/siselect.yaml @@ -8,32 +8,25 @@ priv_mode: S length: SXLEN definedBy: Sscsrind description: | - The `siselect` CSR is a supervisor-level register used to select which indirectly - accessed register is targeted via the `sireg*` alias CSRs. The value in `siselect` - acts as an index into an extension-defined space of registers, allowing access to - a wide range of CSR-like state without allocating contiguous CSR numbers. + The siselect register will support the value range 0..0xFFF at a minimum. + A future extension may define a value range outside of this minimum range. Only if such an extension is implemented will siselect be required to support larger values. - This indirect access mechanism enables software to efficiently access register arrays - without consuming large chunks of CSR address space. The `siselect` CSR works alongside - the `sireg*` alias CSRs to facilitate this indexing and indirect access method. + Requiring a range of 0-0xFFF for siselect, even though most or all of the space may be reserved or inaccessible, permits M-mode to emulate indirectly accessed registers in this implemented range, including registers that may be standardized in the future. - The minimum supported value range for `siselect` is 0–0xFFF, though future extensions - may define larger ranges. Values with the most-significant bit set (bit SXLEN - 1 = 1) - are reserved for custom use, while values with the most-significant bit cleared are - designated for standard use by ratified extensions. + Values of siselect with the most-significant bit set (bit XLEN - 1 = 1) are designated only for custom use, presumably for accessing custom registers through the alias CSRs. + Values of siselect with the most-significant bit clear are designated only for standard use and are reserved until allocated to a standard architecture extension. If XLEN is changed, the most-significant bit of siselect moves to the new position, retaining its value from before. - When `siselect` holds a value that is not implemented, accesses to `sireg*` are - UNSPECIFIED. It is RECOMMENDED that implementations raise an illegal instruction - exception in such cases to support emulation or error detection. Platforms or profiles - may define additional behaviors. + The behavior upon accessing sireg* from M-mode or S-mode, while siselect holds a value that is not implemented at supervisor level, is UNSPECIFIED. + + It is recommended that implementations raise an illegal instruction exception for such accesses, to facilitate possible emulation (by M-mode) of these accesses. fields: - Select Value: + Value: location_rv32: 31-0 location_rv64: 63-0 type: RW description: | - Index value selecting the target register accessed through `sireg*`. - It serves as an indirect register selector. Values are defined by the extension. + Value ranges are allocated to dependent extensions, which specify the + register state accessible via each siregi register, for each siselect value. reset_value: UNDEFINED_LEGAL sw_read(): | diff --git a/arch/csr/Smcsrind/vsireg.yaml b/arch/csr/Smcsrind/vsireg.yaml index ba7ac32bf6..12cfa36db5 100644 --- a/arch/csr/Smcsrind/vsireg.yaml +++ b/arch/csr/Smcsrind/vsireg.yaml @@ -29,7 +29,7 @@ description: | either accesses architectural state, reads as zero, or triggers an exception. fields: - Data: + VALUE: location_rv32: 31-0 location_rv64: 63-0 type: RW diff --git a/arch/csr/Smcsrind/vsireg2.yaml b/arch/csr/Smcsrind/vsireg2.yaml index 0af14f327b..00418a1337 100644 --- a/arch/csr/Smcsrind/vsireg2.yaml +++ b/arch/csr/Smcsrind/vsireg2.yaml @@ -9,25 +9,20 @@ priv_mode: VS length: VSXLEN definedBy: Smcsrind description: | - The `vsireg2` CSR is one of several virtual supervisor-level alias registers used - to indirectly access register state based on the value held in the `vsiselect` - CSR. This alias mechanism enables efficient access to register state by indexing - into an alias space defined by the extension utilizing this access method. + One of the virtual supervisor-level alias CSRs used for indirect register access. + The value of `vsiselect` determines which register is accessed upon read or write + of `vsireg2`. - The value in `vsiselect` determines the register being accessed through `vsireg2`. - The `vsiselect` value serves as an index into a virtualized alias space, providing - access to registers without consuming contiguous CSR address ranges. + Value ranges of `vsiselect` are allocated to dependent extensions, which specify + the register state accessible via each `vsiregi` register, for each `vsiselect` value. - If `vsiselect` holds a value that is not implemented, the behavior of `vsireg2` - is UNSPECIFIED. It is RECOMMENDED that implementations raise a virtual instruction - exception for such accesses to facilitate debugging and emulation. - - The access behavior for each `vsiselect` + `vsireg2` pair is defined by the - extension that owns the `vsiselect` value. Ordinarily, the alias register - either accesses architectural state, reads zero, or raises an exception. + The behavior upon accessing `vsireg2` while `vsiselect` holds a value that is not + implemented at HS level is UNSPECIFIED. It is RECOMMENDED that implementations raise + a virtual instruction exception for such accesses, to facilitate possible emulation + by M-mode or for error detection. fields: - Data: + VALUE: location_rv32: 31-0 location_rv64: 63-0 type: RW diff --git a/arch/csr/Smcsrind/vsireg3.yaml b/arch/csr/Smcsrind/vsireg3.yaml index 16238c0bb9..6f8d1e5a0b 100644 --- a/arch/csr/Smcsrind/vsireg3.yaml +++ b/arch/csr/Smcsrind/vsireg3.yaml @@ -23,7 +23,7 @@ description: | exception in such cases to support debugging and software emulation. fields: - Data: + VALUE: location_rv32: 31-0 location_rv64: 63-0 type: RW diff --git a/arch/csr/Smcsrind/vsireg4.yaml b/arch/csr/Smcsrind/vsireg4.yaml index c6b05633bb..3ae25dd2da 100644 --- a/arch/csr/Smcsrind/vsireg4.yaml +++ b/arch/csr/Smcsrind/vsireg4.yaml @@ -23,7 +23,7 @@ description: | facilitate debugging and software emulation. fields: - Data: + VALUE: location_rv32: 31-0 location_rv64: 63-0 type: RW diff --git a/arch/csr/Smcsrind/vsireg5.yaml b/arch/csr/Smcsrind/vsireg5.yaml index 65fa4f687e..e77f500b0c 100644 --- a/arch/csr/Smcsrind/vsireg5.yaml +++ b/arch/csr/Smcsrind/vsireg5.yaml @@ -19,7 +19,7 @@ description: | to support software emulation or error handling. fields: - Data: + VALUE: location_rv32: 31-0 location_rv64: 63-0 type: RW diff --git a/arch/csr/Smcsrind/vsireg6.yaml b/arch/csr/Smcsrind/vsireg6.yaml index 564af70062..328807c82d 100644 --- a/arch/csr/Smcsrind/vsireg6.yaml +++ b/arch/csr/Smcsrind/vsireg6.yaml @@ -23,7 +23,7 @@ description: | to support emulation or error handling. fields: - Data: + VALUE: location_rv32: 31-0 location_rv64: 63-0 type: RW diff --git a/arch/csr/Smcsrind/vsiselect.yaml b/arch/csr/Smcsrind/vsiselect.yaml index 0eb88bed0d..80f624d0ff 100644 --- a/arch/csr/Smcsrind/vsiselect.yaml +++ b/arch/csr/Smcsrind/vsiselect.yaml @@ -27,7 +27,7 @@ description: | machines and reduces the complexity of implementing CSR access. fields: - Data: + VALUE: location_rv32: 31-0 location_rv64: 63-0 type: RW diff --git a/arch/ext/Smcsrind.yaml b/arch/ext/Smcsrind.yaml index 16b3e687d4..cc21b36aa5 100644 --- a/arch/ext/Smcsrind.yaml +++ b/arch/ext/Smcsrind.yaml @@ -3,13 +3,35 @@ $schema: "ext_schema.json#" kind: extension name: Smcsrind +type: privileged long_name: Machine Indirect CSR Access (Smcsrind) description: | - The `Smcsrind` extension defines indirect access to CSRs, allowing registers to be accessed through - an index value (`miselect`) instead of using fixed CSR numbers. This mechanism reduces the need for - large CSR address space allocation, making it more scalable and flexible. It enables the access of a set - of registers that are not statically defined in the CSR space. Machine-level registers are accessed - through `miselect` and `mireg*`, while supervisor-level registers are accessed through `siselect` and `sireg*`. + Smcsrind/Sscsrind is an ISA extension that extends the indirect CSR access mechanism originally defined as + part of the Smaia/Ssaia extensions, in order to make it available for use by other extensions without creating + an unnecessary dependence on Smaia/Ssaia. + + This extension confers two benefits: + + It provides a means to access an array of registers via CSRs without requiring allocation of large chunks of + the limited CSR address space. + + It enables software to access each of an array of registers by index, without requiring a switch statement + with a case for each register. + + CSRs are accessed indirectly via this extension using select values, in contrast to being accessed directly + using standard CSR numbers. A CSR accessible via one method may or may not be accessible via the other method. + Select values are a separate address space from CSR numbers, and from tselect values in the Sdtrig extension. + If a CSR is both directly and indirectly accessible, the CSR’s select value is unrelated to its CSR number. + + Further, Machine-level and Supervisor-level select values are separate address spaces from each other; + however, Machine-level and Supervisor-level CSRs with the same select value may be defined by an extension + as partial or full aliases with respect to each other. This typically would be done for CSRs that can be + delegated from Machine-level to Supervisor-level. + + The machine-level extension Smcsrind encompasses all added CSRs and all behavior modifications for a hart, + over all privilege levels. For a supervisor-level environment, extension Sscsrind is essentially the same + as Smcsrind except excluding the machine-level CSRs and behavior not directly visible to supervisor level. + versions: - version: "1.0.0" diff --git a/arch/ext/Sscsrind.yaml b/arch/ext/Sscsrind.yaml index 12637d838d..fba0681d91 100644 --- a/arch/ext/Sscsrind.yaml +++ b/arch/ext/Sscsrind.yaml @@ -3,16 +3,33 @@ $schema: "ext_schema.json#" kind: extension name: Sscsrind +type: privileged long_name: Supervisor Indirect CSR Access (Sscsrind) description: | - The `Sscsrind` extension extends the CSR access mechanism for Supervisor mode by enabling indirect - access to Supervisor-level registers through the `siselect` CSR. This extension provides efficient access - to an array of registers without allocating large contiguous blocks of CSR address space. Registers are - accessed by index, offering a more scalable approach to managing Supervisor-level registers. - - Similar to the `Smcsrind` extension, this mechanism reduces the need for fixed CSR numbers, supporting - custom extensions that manage Supervisor-level register access through the use of `siselect` and `sireg*` - registers. + Smcsrind/Sscsrind is an ISA extension that extends the indirect CSR access mechanism originally defined as + part of the Smaia/Ssaia extensions, in order to make it available for use by other extensions without creating + an unnecessary dependence on Smaia/Ssaia. + + This extension confers two benefits: + + It provides a means to access an array of registers via CSRs without requiring allocation of large chunks of + the limited CSR address space. + + It enables software to access each of an array of registers by index, without requiring a switch statement + with a case for each register. + + CSRs are accessed indirectly via this extension using select values, in contrast to being accessed directly + using standard CSR numbers. A CSR accessible via one method may or may not be accessible via the other method. + Select values are a separate address space from CSR numbers, and from tselect values in the Sdtrig extension. + If a CSR is both directly and indirectly accessible, the CSR’s select value is unrelated to its CSR number. + + Further, Machine-level and Supervisor-level select values are separate address spaces from each other; + however, Machine-level and Supervisor-level CSRs with the same select value may be defined by an extension + as partial or full aliases with respect to each other. This typically would be done for CSRs that can be + delegated from Machine-level to Supervisor-level. + + For a supervisor-level environment, extension Sscsrind is essentially the same as Smcsrind except excluding + the machine-level CSRs and behavior not directly visible to supervisor level. versions: - version: "1.0.0" From 66307c2e2fdc80b45e6e9b79e282b3bf6072c928 Mon Sep 17 00:00:00 2001 From: syedowaisalishah Date: Tue, 22 Apr 2025 12:44:56 +0000 Subject: [PATCH 13/29] Corrected Smcsrind CSR YAML files: miselect and mireg[1-6] --- arch/csr/Smcsrind/mireg.yaml | 32 +++++++++++++++++++++----------- arch/csr/Smcsrind/mireg2.yaml | 30 +++++++++++++++++++++++------- arch/csr/Smcsrind/mireg3.yaml | 30 +++++++++++++++++++++++------- arch/csr/Smcsrind/mireg4.yaml | 30 +++++++++++++++++++++++------- arch/csr/Smcsrind/mireg5.yaml | 30 +++++++++++++++++++++++------- arch/csr/Smcsrind/mireg6.yaml | 30 +++++++++++++++++++++++------- arch/csr/Smcsrind/miselect.yaml | 28 +++++++++++++++------------- 7 files changed, 151 insertions(+), 59 deletions(-) diff --git a/arch/csr/Smcsrind/mireg.yaml b/arch/csr/Smcsrind/mireg.yaml index aa40ca00cc..98d1d9ca12 100644 --- a/arch/csr/Smcsrind/mireg.yaml +++ b/arch/csr/Smcsrind/mireg.yaml @@ -8,20 +8,30 @@ priv_mode: M length: MXLEN definedBy: Smcsrind description: | - The `mireg` CSR is the machine-level indirect alias register used to access another - CSR's state indirectly upon a read or write, as determined by the value in `miselect`. + The mireg machine indirect alias CSR is used to access another CSR's state + indirectly upon a read or write, as determined by the value of miselect. - Accessing `mireg` when `miselect` holds a value that is not implemented results in - UNSPECIFIED behavior. Implementations are encouraged to raise an illegal instruction - exception in such cases, to help detect software bugs. Platform and profile specifications - may impose additional requirements for such cases. + The behavior upon accessing mireg from M-mode, while miselect holds a value + that is not implemented, is UNSPECIFIED. - When `miselect` holds a valid and implemented value, the behavior of `mireg` is defined - by the extension to which that `miselect` value is allocated. Ordinarily, `mireg` will access - register state, return read-only zero, or raise an illegal instruction exception. + [Note] + It is expected that implementations will typically raise an illegal instruction exception for + such accesses, so that, for example, they can be identified as software bugs. Platform + specs, profile specs, and/or the Privileged ISA spec may place more restrictions on + behavior for such accesses. - On RV32 systems, if an indirectly addressed register is 64 bits wide, it is recommended that - the lower 32 bits are accessed through `mireg` and the upper 32 bits through `mireg4`. + Attempts to access mireg while miselect holds a number in an allocated and implemented range + results in a specific behavior that, for each combination of miselect and mireg, is defined by the + extension to which the miselect value is allocated. + + [Note] + Ordinarily, mireg will access register state, access read-only 0 state, or raise an + illegal instruction exception. + + [Note] + For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is + recommended that the lower 32 bits of the register are accessed through mireg, + while the upper 32 bits are accessed through mireg4. fields: VALUE: location_rv32: 31-0 diff --git a/arch/csr/Smcsrind/mireg2.yaml b/arch/csr/Smcsrind/mireg2.yaml index ed3f167267..08c2e85e26 100644 --- a/arch/csr/Smcsrind/mireg2.yaml +++ b/arch/csr/Smcsrind/mireg2.yaml @@ -8,14 +8,30 @@ priv_mode: M length: MXLEN definedBy: Smcsrind description: | - The `mireg2` CSR is a machine-level indirect alias register used to access - register state as determined by the value in `miselect`. This CSR allows - flexible access to an array of registers without requiring dedicated CSR - numbers for each. + The `mireg2` machine indirect alias CSR is used to access register state indirectly + upon a read or write, as determined by the value of `miselect`. - The behavior of `mireg2` is determined by the value in `miselect`. If the - value in `miselect` is not implemented, access is UNSPECIFIED, and it is - encouraged that implementations raise an illegal instruction exception in such cases. + The behavior upon accessing `mireg2` from M-mode, while `miselect` holds a value + that is not implemented, is UNSPECIFIED. + + [Note] + It is expected that implementations will typically raise an illegal instruction exception for + such accesses, so that, for example, they can be identified as software bugs. Platform + specs, profile specs, and/or the Privileged ISA spec may place more restrictions on + behavior for such accesses. + + Attempts to access `mireg2` while `miselect` holds a number in an allocated and implemented + range results in a specific behavior that, for each combination of `miselect` and `mireg2`, is + defined by the extension to which the `miselect` value is allocated. + + [Note] + Ordinarily, `mireg2` will access register state, access read-only 0 state, or raise an + illegal instruction exception. + + [Note] + For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is + recommended that the lower 32 bits of the register are accessed through `mireg2`, + while the upper 32 bits are accessed through `mireg5`. fields: VALUE: diff --git a/arch/csr/Smcsrind/mireg3.yaml b/arch/csr/Smcsrind/mireg3.yaml index b1174ece3d..a427ee8cf4 100644 --- a/arch/csr/Smcsrind/mireg3.yaml +++ b/arch/csr/Smcsrind/mireg3.yaml @@ -8,14 +8,30 @@ priv_mode: M length: MXLEN definedBy: Smcsrind description: | - The `mireg3` CSR is a machine-level indirect alias register used to access - register state as determined by the value in `miselect`. This CSR allows - flexible access to an array of registers without requiring dedicated CSR - numbers for each. + The `mireg3` machine indirect alias CSR is used to access register state indirectly + upon a read or write, as determined by the value of `miselect`. - The behavior of `mireg3` is determined by the value in `miselect`. If the - value in `miselect` is not implemented, access is UNSPECIFIED, and it is - encouraged that implementations raise an illegal instruction exception in such cases. + The behavior upon accessing `mireg3` from M-mode, while `miselect` holds a value + that is not implemented, is UNSPECIFIED. + + [Note] + It is expected that implementations will typically raise an illegal instruction exception for + such accesses, so that, for example, they can be identified as software bugs. Platform + specs, profile specs, and/or the Privileged ISA spec may place more restrictions on + behavior for such accesses. + + Attempts to access `mireg3` while `miselect` holds a number in an allocated and implemented + range results in a specific behavior that, for each combination of `miselect` and `mireg3`, is + defined by the extension to which the `miselect` value is allocated. + + [Note] + Ordinarily, `mireg3` will access register state, access read-only 0 state, or raise an + illegal instruction exception. + + [Note] + For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is + recommended that the lower 32 bits of the register are accessed through `mireg3`, + while the upper 32 bits are accessed through `mireg6`. fields: VALUE: diff --git a/arch/csr/Smcsrind/mireg4.yaml b/arch/csr/Smcsrind/mireg4.yaml index ddbcf16a13..9f76e275d3 100644 --- a/arch/csr/Smcsrind/mireg4.yaml +++ b/arch/csr/Smcsrind/mireg4.yaml @@ -8,14 +8,30 @@ priv_mode: M length: MXLEN definedBy: Smcsrind description: | - The `mireg4` CSR is a machine-level indirect alias register used to access - register state as determined by the value in `miselect`. This CSR provides - access to a range of registers indirectly without requiring dedicated CSR - numbers for each register. + The `mireg4` machine indirect alias CSR is used to access register state indirectly + upon a read or write, as determined by the value of `miselect`. - The behavior of `mireg4` is determined by the value of `miselect`. If the value - in `miselect` is not implemented, access is UNSPECIFIED, and implementations - are encouraged to raise an illegal instruction exception. + The behavior upon accessing `mireg4` from M-mode, while `miselect` holds a value + that is not implemented, is UNSPECIFIED. + + [Note] + It is expected that implementations will typically raise an illegal instruction exception for + such accesses, so that, for example, they can be identified as software bugs. Platform + specs, profile specs, and/or the Privileged ISA spec may place more restrictions on + behavior for such accesses. + + Attempts to access `mireg4` while `miselect` holds a number in an allocated and implemented + range results in a specific behavior that, for each combination of `miselect` and `mireg4`, is + defined by the extension to which the `miselect` value is allocated. + + [Note] + Ordinarily, `mireg4` will access register state, access read-only 0 state, or raise an + illegal instruction exception. + + [Note] + For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is + recommended that the upper 32 bits of the register are accessed through `mireg4`, + while the lower 32 bits are accessed through `mireg`, `mireg2`, or `mireg3`. fields: VALUE: diff --git a/arch/csr/Smcsrind/mireg5.yaml b/arch/csr/Smcsrind/mireg5.yaml index cbfaf4cb29..86154c734f 100644 --- a/arch/csr/Smcsrind/mireg5.yaml +++ b/arch/csr/Smcsrind/mireg5.yaml @@ -8,14 +8,30 @@ priv_mode: M length: MXLEN definedBy: Smcsrind description: | - The `mireg5` CSR is a machine-level indirect alias register used to access - register state as determined by the value in `miselect`. This CSR provides - access to a range of registers indirectly without requiring dedicated CSR - numbers for each register. + The `mireg5` machine indirect alias CSR is used to access register state indirectly + upon a read or write, as determined by the value of `miselect`. - The behavior of `mireg5` is determined by the value of `miselect`. If the value - in `miselect` is not implemented, access is UNSPECIFIED, and implementations - are encouraged to raise an illegal instruction exception. + The behavior upon accessing `mireg5` from M-mode, while `miselect` holds a value + that is not implemented, is UNSPECIFIED. + + [Note] + It is expected that implementations will typically raise an illegal instruction exception for + such accesses, so that, for example, they can be identified as software bugs. Platform + specs, profile specs, and/or the Privileged ISA spec may place more restrictions on + behavior for such accesses. + + Attempts to access `mireg5` while `miselect` holds a number in an allocated and implemented + range results in a specific behavior that, for each combination of `miselect` and `mireg5`, is + defined by the extension to which the `miselect` value is allocated. + + [Note] + Ordinarily, `mireg5` will access register state, access read-only 0 state, or raise an + illegal instruction exception. + + [Note] + For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is + recommended that the upper 32 bits of the register are accessed through `mireg5`, + while the lower 32 bits are accessed through `mireg2`. fields: VALUE: diff --git a/arch/csr/Smcsrind/mireg6.yaml b/arch/csr/Smcsrind/mireg6.yaml index 6f4a8ec634..25c6a91628 100644 --- a/arch/csr/Smcsrind/mireg6.yaml +++ b/arch/csr/Smcsrind/mireg6.yaml @@ -8,14 +8,30 @@ priv_mode: M length: MXLEN definedBy: Smcsrind description: | - The `mireg6` CSR is a machine-level indirect alias register used to access - register state as determined by the value in `miselect`. This CSR provides - access to a range of registers indirectly without requiring dedicated CSR - numbers for each register. + The `mireg6` machine indirect alias CSR is used to access register state indirectly + upon a read or write, as determined by the value of `miselect`. - The behavior of `mireg6` is determined by the value of `miselect`. If the value - in `miselect` is not implemented, access is UNSPECIFIED, and implementations - are encouraged to raise an illegal instruction exception + The behavior upon accessing `mireg6` from M-mode, while `miselect` holds a value + that is not implemented, is UNSPECIFIED. + + [Note] + It is expected that implementations will typically raise an illegal instruction exception for + such accesses, so that, for example, they can be identified as software bugs. Platform + specs, profile specs, and/or the Privileged ISA spec may place more restrictions on + behavior for such accesses. + + Attempts to access `mireg6` while `miselect` holds a number in an allocated and implemented + range results in a specific behavior that, for each combination of `miselect` and `mireg6`, is + defined by the extension to which the `miselect` value is allocated. + + [Note] + Ordinarily, `mireg6` will access register state, access read-only 0 state, or raise an + illegal instruction exception. + + [Note] + For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is + recommended that the upper 32 bits of the register are accessed through `mireg6`, + while the lower 32 bits are accessed through `mireg3`. fields: VALUE: diff --git a/arch/csr/Smcsrind/miselect.yaml b/arch/csr/Smcsrind/miselect.yaml index 10026e02a1..4370dffe02 100644 --- a/arch/csr/Smcsrind/miselect.yaml +++ b/arch/csr/Smcsrind/miselect.yaml @@ -8,22 +8,24 @@ priv_mode: M length: MXLEN definedBy: Smcsrind description: | - The `miselect` CSR is a WARL (Write-Any Read-Legal) register that selects which - indirect register is accessed via the `mireg*` alias CSRs. The value in `miselect` - acts as an index into a space of indirectly addressable machine-level registers. + The CSRs listed in the table above provide a window for accessing register state indirectly. The value + of `miselect` determines which register is accessed upon read or write of each of the machine + indirect alias CSRs (`mireg*`). `miselect` value ranges are allocated to dependent extensions, which + specify the register state accessible via each `miregi` register, for each `miselect` value. + `miselect` is a WARL register. - Values of `miselect` are allocated by extensions implementing indirect register access. - The most-significant bit (bit MXLEN-1) is reserved for custom use and must be used - only with implementation-specific extensions. Values with this bit clear are reserved - for standard use. + The `miselect` register implements at least enough bits to support all implemented `miselect` values + (corresponding to the implemented extensions that utilize `miselect`/`mireg*` to indirectly access + register state). The `miselect` register may be read-only zero if there are no extensions implemented + that utilize it. - The indirect access mechanism enabled by `miselect` reduces the need for allocating - large contiguous CSR address ranges by supporting register arrays accessed by index. - - If `miselect` holds an unsupported value, accesses to the corresponding `mireg*` - alias CSR are UNSPECIFIED. Implementations are encouraged to raise an illegal instruction - exception to support robust error handling and software emulation. + Values of `miselect` with the most-significant bit set (bit XLEN - 1 = 1) are designated only for + custom use, presumably for accessing custom registers through the alias CSRs. Values of `miselect` + with the most-significant bit clear are designated only for standard use and are reserved until + allocated to a standard architecture extension. If XLEN is changed, the most-significant bit of + `miselect` moves to the new position, retaining its value from before. + An implementation is not required to support any custom values for `miselect`. fields: Value: location_rv32: 31-0 From 090ce4a6e2234e5079f5fe13bc34144150cd9e0d Mon Sep 17 00:00:00 2001 From: syedowaisalishah Date: Tue, 22 Apr 2025 12:48:08 +0000 Subject: [PATCH 14/29] Corrected Smcsrind CSR YAML files: siselect and sireg[1-6] --- arch/csr/Smcsrind/sireg.yaml | 11 ++++++++++- arch/csr/Smcsrind/sireg2.yaml | 2 +- arch/csr/Smcsrind/sireg3.yaml | 27 ++++++++++++++------------- arch/csr/Smcsrind/sireg4.yaml | 2 +- arch/csr/Smcsrind/sireg5.yaml | 3 ++- arch/csr/Smcsrind/sireg6.yaml | 2 +- arch/csr/Smcsrind/siselect.yaml | 20 +++++++++++--------- 7 files changed, 40 insertions(+), 27 deletions(-) diff --git a/arch/csr/Smcsrind/sireg.yaml b/arch/csr/Smcsrind/sireg.yaml index 4780ea58de..d65cfca874 100644 --- a/arch/csr/Smcsrind/sireg.yaml +++ b/arch/csr/Smcsrind/sireg.yaml @@ -24,8 +24,17 @@ description: | The behavior upon accessing `sireg` from M-mode or S-mode, while `siselect` holds a value that is not implemented at supervisor level, is UNSPECIFIED. + [Note] + It is recommended that implementations raise an illegal instruction exception for such + accesses, to facilitate possible emulation (by M-mode) of these accesses. + + [Note] + An extension is considered not to be implemented at supervisor level if machine level has + disabled the extension for S-mode, such as by the settings of certain fields in CSR + `menvcfg`, for example. + fields: - Data: + VALUE: location_rv32: 31-0 location_rv64: 63-0 type: RW diff --git a/arch/csr/Smcsrind/sireg2.yaml b/arch/csr/Smcsrind/sireg2.yaml index ed287069a9..5ba380bf4c 100644 --- a/arch/csr/Smcsrind/sireg2.yaml +++ b/arch/csr/Smcsrind/sireg2.yaml @@ -34,7 +34,7 @@ description: | `menvcfg`, for example. fields: - Data: + VALUE: location_rv32: 31-0 location_rv64: 63-0 type: RW diff --git a/arch/csr/Smcsrind/sireg3.yaml b/arch/csr/Smcsrind/sireg3.yaml index 4fb5178371..7a4ec67c76 100644 --- a/arch/csr/Smcsrind/sireg3.yaml +++ b/arch/csr/Smcsrind/sireg3.yaml @@ -8,21 +8,21 @@ priv_mode: S length: SXLEN definedBy: Sscsrind description: | - The `sireg3` CSR is a supervisor-level alias register used to access register state - indirectly based on the value held in the `siselect` CSR. The `sireg3` CSR provides - access to a window of indirectly addressed registers. + Access to `sireg3` from M-mode or S-mode while `siselect` holds a number in a + standard-defined and implemented range results in specific behavior that, for each combination of + `siselect` and `sireg3`, is defined by the extension to which the `siselect` value is allocated. - The behavior of accesses to `sireg3` is determined by the value of `siselect`. - If `siselect` holds a value that corresponds to an implemented register, - the register is accessed as determined by the value of `siselect`. + [Note] + Ordinarily, `sireg3` will access register state, access read-only 0 state, or, unless + executing in a virtual machine (covered in the next section), raise an illegal instruction + exception. - When `siselect` holds an unsupported value, access to `sireg3` is UNSPECIFIED, - and implementations are encouraged to raise an illegal instruction exception - to facilitate debugging or software emulation. + Note that the widths of `siselect` and `sireg3` are always the current XLEN rather than SXLEN. Hence, + for example, if MXLEN = 64 and SXLEN = 32, then this register is 64 bits when the current + privilege mode is M (running RV64 code) but 32 bits when the privilege mode is S (RV32 code). - This indirect access mechanism allows efficient access to an array of CSRs - without allocating large contiguous blocks of CSR address space. It is useful - for arrays such as performance counters and other register sets. + The behavior upon accessing `sireg3` from M-mode or S-mode, while `siselect` holds a value that is + not implemented at supervisor level, is UNSPECIFIED. [Note] It is recommended that implementations raise an illegal instruction exception for such @@ -32,8 +32,9 @@ description: | An extension is considered not to be implemented at supervisor level if machine level has disabled the extension for S-mode, such as by the settings of certain fields in CSR `menvcfg`, for example. + fields: - Data: + VALUE: location_rv32: 31-0 location_rv64: 63-0 type: RW diff --git a/arch/csr/Smcsrind/sireg4.yaml b/arch/csr/Smcsrind/sireg4.yaml index 598fb94062..71c7fd2dc1 100644 --- a/arch/csr/Smcsrind/sireg4.yaml +++ b/arch/csr/Smcsrind/sireg4.yaml @@ -34,7 +34,7 @@ description: | `menvcfg`, for example. fields: - Data: + VALUE: location_rv32: 31-0 location_rv64: 63-0 type: RW diff --git a/arch/csr/Smcsrind/sireg5.yaml b/arch/csr/Smcsrind/sireg5.yaml index 8f258a22ad..0e14b544e3 100644 --- a/arch/csr/Smcsrind/sireg5.yaml +++ b/arch/csr/Smcsrind/sireg5.yaml @@ -32,8 +32,9 @@ description: | An extension is considered not to be implemented at supervisor level if machine level has disabled the extension for S-mode, such as by the settings of certain fields in CSR `menvcfg`, for example. + fields: - Data: + VALUE: location_rv32: 31-0 location_rv64: 63-0 type: RW diff --git a/arch/csr/Smcsrind/sireg6.yaml b/arch/csr/Smcsrind/sireg6.yaml index ac58da8fd5..10554d6e74 100644 --- a/arch/csr/Smcsrind/sireg6.yaml +++ b/arch/csr/Smcsrind/sireg6.yaml @@ -34,7 +34,7 @@ description: | `menvcfg`, for example. fields: - Data: + VALUE: location_rv32: 31-0 location_rv64: 63-0 type: RW diff --git a/arch/csr/Smcsrind/siselect.yaml b/arch/csr/Smcsrind/siselect.yaml index 487b3965f7..8f2c5b4796 100644 --- a/arch/csr/Smcsrind/siselect.yaml +++ b/arch/csr/Smcsrind/siselect.yaml @@ -8,17 +8,19 @@ priv_mode: S length: SXLEN definedBy: Sscsrind description: | - The siselect register will support the value range 0..0xFFF at a minimum. - A future extension may define a value range outside of this minimum range. Only if such an extension is implemented will siselect be required to support larger values. + The `siselect` register will support the value range 0..0xFFF at a minimum. A future extension may + define a value range outside of this minimum range. Only if such an extension is implemented will + `siselect` be required to support larger values. - Requiring a range of 0-0xFFF for siselect, even though most or all of the space may be reserved or inaccessible, permits M-mode to emulate indirectly accessed registers in this implemented range, including registers that may be standardized in the future. + Requiring a range of 0-0xFFF for `siselect`, even though most or all of the space may be reserved or + inaccessible, permits M-mode to emulate indirectly accessed registers in this implemented range, + including registers that may be standardized in the future. - Values of siselect with the most-significant bit set (bit XLEN - 1 = 1) are designated only for custom use, presumably for accessing custom registers through the alias CSRs. - Values of siselect with the most-significant bit clear are designated only for standard use and are reserved until allocated to a standard architecture extension. If XLEN is changed, the most-significant bit of siselect moves to the new position, retaining its value from before. - - The behavior upon accessing sireg* from M-mode or S-mode, while siselect holds a value that is not implemented at supervisor level, is UNSPECIFIED. - - It is recommended that implementations raise an illegal instruction exception for such accesses, to facilitate possible emulation (by M-mode) of these accesses. + Values of `siselect` with the most-significant bit set (bit XLEN - 1 = 1) are designated only for + custom use, presumably for accessing custom registers through the alias CSRs. Values of `siselect` + with the most-significant bit clear are designated only for standard use and are reserved until + allocated to a standard architecture extension. If XLEN is changed, the most-significant bit of + `siselect` moves to the new position, retaining its value from before. fields: Value: From 6ecf0a63e582152b374864649bfa80cd783478f5 Mon Sep 17 00:00:00 2001 From: syedowaisalishah Date: Tue, 22 Apr 2025 12:52:29 +0000 Subject: [PATCH 15/29] Corrected Smcsrind CSR YAML files: vsiselect and vsireg[1-6] --- arch/csr/Smcsrind/vsireg.yaml | 28 +++++++++++++--------------- arch/csr/Smcsrind/vsireg2.yaml | 24 +++++++++++++++--------- arch/csr/Smcsrind/vsireg3.yaml | 25 +++++++++++++++---------- arch/csr/Smcsrind/vsireg4.yaml | 25 +++++++++++++++---------- arch/csr/Smcsrind/vsireg5.yaml | 23 ++++++++++++++++------- arch/csr/Smcsrind/vsireg6.yaml | 25 +++++++++++++++---------- arch/csr/Smcsrind/vsiselect.yaml | 27 ++++++++++++++------------- 7 files changed, 103 insertions(+), 74 deletions(-) diff --git a/arch/csr/Smcsrind/vsireg.yaml b/arch/csr/Smcsrind/vsireg.yaml index 12cfa36db5..38d3387c17 100644 --- a/arch/csr/Smcsrind/vsireg.yaml +++ b/arch/csr/Smcsrind/vsireg.yaml @@ -10,24 +10,22 @@ length: VSXLEN definedBy: Smcsrind description: | The `vsireg` CSR is one of several alias registers used to indirectly access - virtual supervisor-level register state. Access to a specific target register - is controlled via the value held in the `vsiselect` CSR, which acts as an - index into a virtualized alias space. + virtual supervisor-level CSRs in VS-mode or VU-mode. The register addressed by + `vsireg` is selected by the current value of the `vsiselect` CSR. The alias + mechanism allows indirect CSR access, which helps in virtualization and future + extensibility. - This mechanism enables efficient access to an array of registers without - consuming a large contiguous range in the CSR address space. When `vsiselect` - holds a value allocated and implemented by a specific extension, `vsireg` - provides access to the corresponding register state. + A virtual instruction exception is raised for attempts from VS-mode or VU-mode + to directly access `vsiselect` or `vsireg`, or from VU-mode to access + `siselect` or `sireg`. - If the value in `vsiselect` is not implemented, the behavior is UNSPECIFIED. - However, it is RECOMMENDED that implementations raise a virtual instruction - exception for such accesses. This supports correct virtualization behavior - and allows for software emulation or debugging of unsupported accesses. - - The access behavior for each `vsiselect` + `vsireg` pair is defined by the - extension that owns the `vsiselect` value. Ordinarily, each alias register - either accesses architectural state, reads as zero, or triggers an exception. + The behavior of accesses to `vsireg` when `vsiselect` holds a value that is + not implemented at the HS level is UNSPECIFIED, but implementations are + recommended to raise an illegal instruction exception for such accesses. + The width of `vsireg` is always the current `XLEN`, not `VSXLEN`. For example, + if `HSXLEN = 64` and `VSXLEN = 32`, then `vsireg` is 64 bits wide when + accessed from HS-mode (RV64), but 32 bits when accessed from VS-mode (RV32). fields: VALUE: location_rv32: 31-0 diff --git a/arch/csr/Smcsrind/vsireg2.yaml b/arch/csr/Smcsrind/vsireg2.yaml index 00418a1337..bbb61a571a 100644 --- a/arch/csr/Smcsrind/vsireg2.yaml +++ b/arch/csr/Smcsrind/vsireg2.yaml @@ -9,17 +9,23 @@ priv_mode: VS length: VSXLEN definedBy: Smcsrind description: | - One of the virtual supervisor-level alias CSRs used for indirect register access. - The value of `vsiselect` determines which register is accessed upon read or write - of `vsireg2`. + The `vsireg2` CSR is one of several alias registers used to indirectly access + virtual supervisor-level CSRs in VS-mode or VU-mode. The register addressed by + `vsireg2` is selected by the current value of the `vsiselect` CSR. The alias + mechanism allows indirect CSR access, which helps in virtualization and future + extensibility. - Value ranges of `vsiselect` are allocated to dependent extensions, which specify - the register state accessible via each `vsiregi` register, for each `vsiselect` value. + A virtual instruction exception is raised for attempts from VS-mode or VU-mode + to directly access `vsiselect` or `vsireg2`, or from VU-mode to access + `siselect` or `siregX`. - The behavior upon accessing `vsireg2` while `vsiselect` holds a value that is not - implemented at HS level is UNSPECIFIED. It is RECOMMENDED that implementations raise - a virtual instruction exception for such accesses, to facilitate possible emulation - by M-mode or for error detection. + The behavior of accesses to `vsireg2` when `vsiselect` holds a value that is + not implemented at the HS level is UNSPECIFIED, but implementations are + recommended to raise an illegal instruction exception for such accesses. + + The width of `vsireg2` is always the current `XLEN`, not `VSXLEN`. For example, + if `HSXLEN = 64` and `VSXLEN = 32`, then `vsireg2` is 64 bits wide when + accessed from HS-mode (RV64), but 32 bits when accessed from VS-mode (RV32). fields: VALUE: diff --git a/arch/csr/Smcsrind/vsireg3.yaml b/arch/csr/Smcsrind/vsireg3.yaml index 6f8d1e5a0b..7f94c46171 100644 --- a/arch/csr/Smcsrind/vsireg3.yaml +++ b/arch/csr/Smcsrind/vsireg3.yaml @@ -9,18 +9,23 @@ priv_mode: VS length: VSXLEN definedBy: Smcsrind description: | - The `vsireg3` CSR is a virtual supervisor-level alias register used to indirectly - access register state based on the value held in the `vsiselect` CSR. This CSR - forms part of the virtualized alias register space, enabling efficient access to - register arrays in VS-mode without consuming large contiguous CSR address ranges. + The `vsireg3` CSR is one of several alias registers used to indirectly access + virtual supervisor-level CSRs in VS-mode or VU-mode. The register addressed by + `vsireg3` is selected by the current value of the `vsiselect` CSR. The alias + mechanism allows indirect CSR access, which helps in virtualization and future + extensibility. - The value of `vsiselect` determines which register is accessed via `vsireg3`. - The `vsiselect` CSR acts as an index into the alias space, facilitating scalable - access to a range of registers. + A virtual instruction exception is raised for attempts from VS-mode or VU-mode + to directly access `vsiselect` or `vsireg3`, or from VU-mode to access + `siselect` or `siregX`. - If `vsiselect` holds a value that is not implemented, the behavior of `vsireg3` - is UNSPECIFIED. It is recommended that implementations raise a virtual instruction - exception in such cases to support debugging and software emulation. + The behavior of accesses to `vsireg3` when `vsiselect` holds a value that is + not implemented at the HS level is UNSPECIFIED, but implementations are + recommended to raise an illegal instruction exception for such accesses. + + The width of `vsireg3` is always the current `XLEN`, not `VSXLEN`. For example, + if `HSXLEN = 64` and `VSXLEN = 32`, then `vsireg3` is 64 bits wide when + accessed from HS-mode (RV64), but 32 bits when accessed from VS-mode (RV32). fields: VALUE: diff --git a/arch/csr/Smcsrind/vsireg4.yaml b/arch/csr/Smcsrind/vsireg4.yaml index 3ae25dd2da..a2e5e9ca46 100644 --- a/arch/csr/Smcsrind/vsireg4.yaml +++ b/arch/csr/Smcsrind/vsireg4.yaml @@ -9,18 +9,23 @@ priv_mode: VS length: VSXLEN definedBy: Smcsrind description: | - The `vsireg4` CSR is a virtual supervisor-level alias register used for indirect - access to register state based on the value held in the `vsiselect` CSR. It is part of - a set of alias registers that allow efficient access to register arrays in VS-mode without - consuming large contiguous CSR address ranges. + The `vsireg4` CSR is one of several alias registers used to indirectly access + virtual supervisor-level CSRs in VS-mode or VU-mode. The register addressed by + `vsireg4` is selected by the current value of the `vsiselect` CSR. The alias + mechanism allows indirect CSR access, which helps in virtualization and future + extensibility. - In RV32 environments, where registers may be 64-bit, `vsireg4` is typically used to - access the upper 32 bits of a 64-bit register, in combination with other alias CSRs like - `vsireg` and `vsireg2`, which handle the lower 32 bits. + A virtual instruction exception is raised for attempts from VS-mode or VU-mode + to directly access `vsiselect` or `vsireg4`, or from VU-mode to access + `siselect` or `siregX`. - If the value in `vsiselect` is unsupported or unimplemented, access to `vsireg4` is - UNSPECIFIED. Implementations are encouraged to raise a virtual instruction exception to - facilitate debugging and software emulation. + The behavior of accesses to `vsireg4` when `vsiselect` holds a value that is + not implemented at the HS level is UNSPECIFIED, but implementations are + recommended to raise an illegal instruction exception for such accesses. + + The width of `vsireg4` is always the current `XLEN`, not `VSXLEN`. For example, + if `HSXLEN = 64` and `VSXLEN = 32`, then `vsireg4` is 64 bits wide when + accessed from HS-mode (RV64), but 32 bits when accessed from VS-mode (RV32). fields: VALUE: diff --git a/arch/csr/Smcsrind/vsireg5.yaml b/arch/csr/Smcsrind/vsireg5.yaml index e77f500b0c..c50606bb78 100644 --- a/arch/csr/Smcsrind/vsireg5.yaml +++ b/arch/csr/Smcsrind/vsireg5.yaml @@ -9,14 +9,23 @@ priv_mode: VS length: VSXLEN definedBy: Smcsrind description: | - The `vsireg5` CSR is part of the virtual supervisor-level indirect register access - mechanism, providing indexed access to register state based on the value held in the - `vsiselect` CSR. It enables software in VS-mode to access register arrays efficiently, - avoiding the need to allocate large, contiguous CSR address ranges. + The `vsireg5` CSR is one of several alias registers used to indirectly access + virtual supervisor-level CSRs in VS-mode or VU-mode. The register addressed by + `vsireg5` is selected by the current value of the `vsiselect` CSR. The alias + mechanism allows indirect CSR access, which helps in virtualization and future + extensibility. - When the `vsiselect` value points to an unimplemented register, access to `vsireg5` - is UNSPECIFIED. Implementations are encouraged to raise a virtual instruction exception - to support software emulation or error handling. + A virtual instruction exception is raised for attempts from VS-mode or VU-mode + to directly access `vsiselect` or `vsireg5`, or from VU-mode to access + `siselect` or `siregX`. + + The behavior of accesses to `vsireg5` when `vsiselect` holds a value that is + not implemented at the HS level is UNSPECIFIED, but implementations are + recommended to raise an illegal instruction exception for such accesses. + + The width of `vsireg5` is always the current `XLEN`, not `VSXLEN`. For example, + if `HSXLEN = 64` and `VSXLEN = 32`, then `vsireg5` is 64 bits wide when + accessed from HS-mode (RV64), but 32 bits when accessed from VS-mode (RV32). fields: VALUE: diff --git a/arch/csr/Smcsrind/vsireg6.yaml b/arch/csr/Smcsrind/vsireg6.yaml index 328807c82d..8ddd49791e 100644 --- a/arch/csr/Smcsrind/vsireg6.yaml +++ b/arch/csr/Smcsrind/vsireg6.yaml @@ -9,18 +9,23 @@ priv_mode: VS length: VSXLEN definedBy: Smcsrind description: | - The `vsireg6` CSR is part of the virtual supervisor-level indirect register access - mechanism. It is used for accessing register state based on the value held in the - `vsiselect` CSR. `vsireg6` acts as one of the alias registers in the system, providing - indirect access to a register selected via `vsiselect`. + The `vsireg6` CSR is one of several alias registers used to indirectly access + virtual supervisor-level CSRs in VS-mode or VU-mode. The register addressed by + `vsireg6` is selected by the current value of the `vsiselect` CSR. The alias + mechanism allows indirect CSR access, which helps in virtualization and future + extensibility. - In RV32 environments, `vsireg6` is typically used for accessing the upper 32 bits of - a 64-bit register array, while other aliases, such as `vsireg3`, provide access to - the lower 32 bits. + A virtual instruction exception is raised for attempts from VS-mode or VU-mode + to directly access `vsiselect` or `vsireg6`, or from VU-mode to access + `siselect` or `siregX`. - When `vsiselect` holds an unimplemented value, the behavior of accesses to `vsireg6` - is UNSPECIFIED. Implementations are encouraged to raise a virtual instruction exception - to support emulation or error handling. + The behavior of accesses to `vsireg6` when `vsiselect` holds a value that is + not implemented at the HS level is UNSPECIFIED, but implementations are + recommended to raise an illegal instruction exception for such accesses. + + The width of `vsireg6` is always the current `XLEN`, not `VSXLEN`. For example, + if `HSXLEN = 64` and `VSXLEN = 32`, then `vsireg6` is 64 bits wide when + accessed from HS-mode (RV64), but 32 bits when accessed from VS-mode (RV32). fields: VALUE: diff --git a/arch/csr/Smcsrind/vsiselect.yaml b/arch/csr/Smcsrind/vsiselect.yaml index 80f624d0ff..b65c585aae 100644 --- a/arch/csr/Smcsrind/vsiselect.yaml +++ b/arch/csr/Smcsrind/vsiselect.yaml @@ -9,22 +9,23 @@ priv_mode: VS length: VSXLEN definedBy: Smcsrind description: | - The `vsiselect` CSR is a virtual supervisor-level register that selects which - register is accessed indirectly via the `vsireg*` alias registers. The value - held in `vsiselect` acts as an index into an alias space defined by the - extension utilizing this access method. + The `vsiselect` register will support the value range 0..0xFFF at a minimum. A future extension may + define a value range outside of this minimum range. Only if such an extension is implemented will + `vsiselect` be required to support larger values. - This CSR allows software in VS-mode to access register arrays by index rather - than by fixed CSR numbers, improving scalability and reducing the need for large - contiguous CSR address space. The `vsiselect` CSR is typically used alongside - `vsireg` through `vsireg6` to access virtual supervisor-level registers indirectly. + Requiring a range of 0-0xFFF for `vsiselect`, even though most or all of the space may be reserved + or inaccessible, permits a hypervisor to emulate indirectly accessed registers in this implemented + range, including registers that may be standardized in the future. - When `vsiselect` holds a value that corresponds to an unimplemented register, - the behavior is UNSPECIFIED. Implementations are encouraged to raise a virtual - instruction exception to support software emulation and debugging. + More generally it is recommended that `vsiselect` and `siselect` be implemented with the same number + of bits. This also avoids creation of a virtualization hole due to observable differences between + `vsiselect` and `siselect` widths. - The indirect access mechanism enables more flexible access patterns for virtual - machines and reduces the complexity of implementing CSR access. + Values of `vsiselect` with the most-significant bit set (bit XLEN - 1 = 1) are designated only for + custom use, presumably for accessing custom registers through the alias CSRs. Values of `vsiselect` + with the most-significant bit clear are designated only for standard use and are reserved until + allocated to a standard architecture extension. If XLEN is changed, the most-significant bit of + `vsiselect` moves to the new position, retaining its value from before. fields: VALUE: From c448c469e0a41fed734686c93f8484a3dd5442d1 Mon Sep 17 00:00:00 2001 From: syedowaisalishah Date: Mon, 28 Apr 2025 07:41:23 +0000 Subject: [PATCH 16/29] Corrected Smcsrind CSR YAML files: mireg[2-6] --- arch/csr/Smcsrind/mireg2.yaml | 2 +- arch/csr/Smcsrind/mireg3.yaml | 2 +- arch/csr/Smcsrind/mireg4.yaml | 2 +- arch/csr/Smcsrind/mireg5.yaml | 2 +- arch/csr/Smcsrind/mireg6.yaml | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/csr/Smcsrind/mireg2.yaml b/arch/csr/Smcsrind/mireg2.yaml index 08c2e85e26..755f7aab1d 100644 --- a/arch/csr/Smcsrind/mireg2.yaml +++ b/arch/csr/Smcsrind/mireg2.yaml @@ -38,6 +38,6 @@ fields: location_rv32: 31-0 location_rv64: 63-0 type: RW - description: Register state data of CSR selected by `miselect` value. + description: Register state of the CSR selected by the current `miselect` value. reset_value: UNDEFINED_LEGAL sw_read(): | diff --git a/arch/csr/Smcsrind/mireg3.yaml b/arch/csr/Smcsrind/mireg3.yaml index a427ee8cf4..25b2d3ca03 100644 --- a/arch/csr/Smcsrind/mireg3.yaml +++ b/arch/csr/Smcsrind/mireg3.yaml @@ -38,6 +38,6 @@ fields: location_rv32: 31-0 location_rv64: 63-0 type: RW - description: Register state data of CSR selected by `miselect` value. + description: Register state of the CSR selected by the current `miselect` value. reset_value: UNDEFINED_LEGAL sw_read(): | diff --git a/arch/csr/Smcsrind/mireg4.yaml b/arch/csr/Smcsrind/mireg4.yaml index 9f76e275d3..074756db49 100644 --- a/arch/csr/Smcsrind/mireg4.yaml +++ b/arch/csr/Smcsrind/mireg4.yaml @@ -38,6 +38,6 @@ fields: location_rv32: 31-0 location_rv64: 63-0 type: RW - description: Register state data of CSR selected by `miselect` value. + description: Register state of the CSR selected by the current `miselect` value. reset_value: UNDEFINED_LEGAL sw_read(): | diff --git a/arch/csr/Smcsrind/mireg5.yaml b/arch/csr/Smcsrind/mireg5.yaml index 86154c734f..465c0ad7e4 100644 --- a/arch/csr/Smcsrind/mireg5.yaml +++ b/arch/csr/Smcsrind/mireg5.yaml @@ -38,6 +38,6 @@ fields: location_rv32: 31-0 location_rv64: 63-0 type: RW - description: Register state data of CSR selected by `miselect` value. + description: Register state of the CSR selected by the current `miselect` value. reset_value: UNDEFINED_LEGAL sw_read(): | diff --git a/arch/csr/Smcsrind/mireg6.yaml b/arch/csr/Smcsrind/mireg6.yaml index 25c6a91628..126b4de7e9 100644 --- a/arch/csr/Smcsrind/mireg6.yaml +++ b/arch/csr/Smcsrind/mireg6.yaml @@ -38,6 +38,6 @@ fields: location_rv32: 31-0 location_rv64: 63-0 type: RW - description: Register state data of CSR selected by `miselect` value. + description: Register state of the CSR selected by the current `miselect` value. reset_value: UNDEFINED_LEGAL sw_read(): | From 99bd63c450db278a893af6d18f4645ad9c3e8fee Mon Sep 17 00:00:00 2001 From: syedowaisalishah Date: Mon, 28 Apr 2025 07:42:53 +0000 Subject: [PATCH 17/29] Corrected Smcsrind extesnion yaml --- arch/ext/Smcsrind.yaml | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/arch/ext/Smcsrind.yaml b/arch/ext/Smcsrind.yaml index cc21b36aa5..1d9dfb873d 100644 --- a/arch/ext/Smcsrind.yaml +++ b/arch/ext/Smcsrind.yaml @@ -38,7 +38,4 @@ versions: state: ratified ratification_date: "2024-11" url: "https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-isa-release-482805d-2025-03-25" - requires: - allOf: - - name: S - version: ~> 1.13 + requires: { name: S, version: "~> 1.13" } From 36cf1f1aa82b3e681b9cbff0ba2deea8f46c5e40 Mon Sep 17 00:00:00 2001 From: syedowaisalishah Date: Mon, 28 Apr 2025 07:42:53 +0000 Subject: [PATCH 18/29] Corrected Smcsrind extesnion yaml --- arch/ext/Smcsrind.yaml | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/arch/ext/Smcsrind.yaml b/arch/ext/Smcsrind.yaml index cc21b36aa5..1d9dfb873d 100644 --- a/arch/ext/Smcsrind.yaml +++ b/arch/ext/Smcsrind.yaml @@ -38,7 +38,4 @@ versions: state: ratified ratification_date: "2024-11" url: "https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-isa-release-482805d-2025-03-25" - requires: - allOf: - - name: S - version: ~> 1.13 + requires: { name: S, version: "~> 1.13" } From b0997d56ecc3be2339c0fb523e6d96f018f6d16c Mon Sep 17 00:00:00 2001 From: syedowaisalishah Date: Mon, 28 Apr 2025 08:29:48 +0000 Subject: [PATCH 19/29] Corrected Smcsrind CSR YAML files: mireg[1-6] --- arch/csr/Smcsrind/mireg.yaml | 2 +- arch/csr/Smcsrind/mireg2.yaml | 2 +- arch/csr/Smcsrind/mireg3.yaml | 2 +- arch/csr/Smcsrind/mireg4.yaml | 2 +- arch/csr/Smcsrind/mireg5.yaml | 2 +- arch/csr/Smcsrind/mireg6.yaml | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/csr/Smcsrind/mireg.yaml b/arch/csr/Smcsrind/mireg.yaml index 98d1d9ca12..4d07bbe9a1 100644 --- a/arch/csr/Smcsrind/mireg.yaml +++ b/arch/csr/Smcsrind/mireg.yaml @@ -37,6 +37,6 @@ fields: location_rv32: 31-0 location_rv64: 63-0 type: RW - description: Register state of the CSR selected by the current `miselect` value. + description: Register state of the CSR selected by the current `miselect` value reset_value: UNDEFINED_LEGAL sw_read(): | diff --git a/arch/csr/Smcsrind/mireg2.yaml b/arch/csr/Smcsrind/mireg2.yaml index 755f7aab1d..659cdcaacf 100644 --- a/arch/csr/Smcsrind/mireg2.yaml +++ b/arch/csr/Smcsrind/mireg2.yaml @@ -38,6 +38,6 @@ fields: location_rv32: 31-0 location_rv64: 63-0 type: RW - description: Register state of the CSR selected by the current `miselect` value. + description: Register state of the CSR selected by the current `miselect` value reset_value: UNDEFINED_LEGAL sw_read(): | diff --git a/arch/csr/Smcsrind/mireg3.yaml b/arch/csr/Smcsrind/mireg3.yaml index 25b2d3ca03..8c77929a91 100644 --- a/arch/csr/Smcsrind/mireg3.yaml +++ b/arch/csr/Smcsrind/mireg3.yaml @@ -38,6 +38,6 @@ fields: location_rv32: 31-0 location_rv64: 63-0 type: RW - description: Register state of the CSR selected by the current `miselect` value. + description: Register state of the CSR selected by the current `miselect` value reset_value: UNDEFINED_LEGAL sw_read(): | diff --git a/arch/csr/Smcsrind/mireg4.yaml b/arch/csr/Smcsrind/mireg4.yaml index 074756db49..389f93a58e 100644 --- a/arch/csr/Smcsrind/mireg4.yaml +++ b/arch/csr/Smcsrind/mireg4.yaml @@ -38,6 +38,6 @@ fields: location_rv32: 31-0 location_rv64: 63-0 type: RW - description: Register state of the CSR selected by the current `miselect` value. + description: Register state of the CSR selected by the current `miselect` value reset_value: UNDEFINED_LEGAL sw_read(): | diff --git a/arch/csr/Smcsrind/mireg5.yaml b/arch/csr/Smcsrind/mireg5.yaml index 465c0ad7e4..71b3dd3e6c 100644 --- a/arch/csr/Smcsrind/mireg5.yaml +++ b/arch/csr/Smcsrind/mireg5.yaml @@ -38,6 +38,6 @@ fields: location_rv32: 31-0 location_rv64: 63-0 type: RW - description: Register state of the CSR selected by the current `miselect` value. + description: Register state of the CSR selected by the current `miselect` value reset_value: UNDEFINED_LEGAL sw_read(): | diff --git a/arch/csr/Smcsrind/mireg6.yaml b/arch/csr/Smcsrind/mireg6.yaml index 126b4de7e9..b963e9f757 100644 --- a/arch/csr/Smcsrind/mireg6.yaml +++ b/arch/csr/Smcsrind/mireg6.yaml @@ -38,6 +38,6 @@ fields: location_rv32: 31-0 location_rv64: 63-0 type: RW - description: Register state of the CSR selected by the current `miselect` value. + description: Register state of the CSR selected by the current `miselect` value reset_value: UNDEFINED_LEGAL sw_read(): | From 8b7cc9358a2dfd7ef9e3207fdb2ac7fc43362f43 Mon Sep 17 00:00:00 2001 From: syedowaisalishah Date: Mon, 28 Apr 2025 08:32:14 +0000 Subject: [PATCH 20/29] Corrected Smcsrind extesnion yaml --- arch/ext/Smcsrind.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/ext/Smcsrind.yaml b/arch/ext/Smcsrind.yaml index 1d9dfb873d..db3201edd5 100644 --- a/arch/ext/Smcsrind.yaml +++ b/arch/ext/Smcsrind.yaml @@ -25,8 +25,8 @@ description: | Further, Machine-level and Supervisor-level select values are separate address spaces from each other; however, Machine-level and Supervisor-level CSRs with the same select value may be defined by an extension - as partial or full aliases with respect to each other. This typically would be done for CSRs that can be - delegated from Machine-level to Supervisor-level. + as partial or full aliases with respect to each other. + This typically would be done for CSRs that can be delegated from Machine-level to Supervisor-level. The machine-level extension Smcsrind encompasses all added CSRs and all behavior modifications for a hart, over all privilege levels. For a supervisor-level environment, extension Sscsrind is essentially the same From 399ce0d98b9bb8f86488d130077e667ed204c275 Mon Sep 17 00:00:00 2001 From: syedowaisalishah Date: Mon, 5 May 2025 09:34:57 +0000 Subject: [PATCH 21/29] docs(smcsrind): correct smcsrind CSR YAML files: mireg[1-6] --- arch/csr/Smcsrind/mireg.yaml | 67 ++++++++++++++++++++------------- arch/csr/Smcsrind/mireg2.yaml | 61 +++++++++++++++++++----------- arch/csr/Smcsrind/mireg3.yaml | 61 +++++++++++++++++++----------- arch/csr/Smcsrind/mireg4.yaml | 61 +++++++++++++++++++----------- arch/csr/Smcsrind/mireg5.yaml | 61 +++++++++++++++++++----------- arch/csr/Smcsrind/mireg6.yaml | 61 +++++++++++++++++++----------- arch/csr/Smcsrind/miselect.yaml | 58 +++++++++++++++++++--------- 7 files changed, 281 insertions(+), 149 deletions(-) diff --git a/arch/csr/Smcsrind/mireg.yaml b/arch/csr/Smcsrind/mireg.yaml index 4d07bbe9a1..3420ff3303 100644 --- a/arch/csr/Smcsrind/mireg.yaml +++ b/arch/csr/Smcsrind/mireg.yaml @@ -7,36 +7,51 @@ address: 0x351 priv_mode: M length: MXLEN definedBy: Smcsrind -description: | - The mireg machine indirect alias CSR is used to access another CSR's state - indirectly upon a read or write, as determined by the value of miselect. - - The behavior upon accessing mireg from M-mode, while miselect holds a value - that is not implemented, is UNSPECIFIED. - - [Note] - It is expected that implementations will typically raise an illegal instruction exception for - such accesses, so that, for example, they can be identified as software bugs. Platform - specs, profile specs, and/or the Privileged ISA spec may place more restrictions on - behavior for such accesses. - - Attempts to access mireg while miselect holds a number in an allocated and implemented range - results in a specific behavior that, for each combination of miselect and mireg, is defined by the - extension to which the miselect value is allocated. - - [Note] - Ordinarily, mireg will access register state, access read-only 0 state, or raise an - illegal instruction exception. - - [Note] - For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is - recommended that the lower 32 bits of the register are accessed through mireg, - while the upper 32 bits are accessed through mireg4. +description: + - id: csr-mireg-purpose + normative: true + text: | + The mireg machine indirect alias CSR is used to access another CSR's state + indirectly upon a read or write, as determined by the value of miselect. + - id: csr-mireg-unimplemented-miselect + normative: true + text: | + The behavior upon accessing mireg from M-mode, while miselect holds a value + that is not implemented, is UNSPECIFIED. + - id: csr-mireg-unimplemented-miselect-note + normative: false + text: | + It is expected that implementations will typically raise an illegal instruction exception for + such accesses, so that, for example, they can be identified as software bugs. Platform + specs, profile specs, and/or the Privileged ISA spec may place more restrictions on + behavior for such accesses. + - id: csr-mireg-implemented-miselect + normative: true + text: | + Attempts to access mireg while miselect holds a number in an allocated and implemented range + results in a specific behavior that, for each combination of miselect and mireg, is defined by the + extension to which the miselect value is allocated. + - id: csr-mireg-implemented-miselect-note + normative: false + text: | + Ordinarily, mireg will access register state, access read-only 0 state, or raise an + illegal instruction exception. + - id: csr-mireg-rv32-64bit-access + normative: false + text: | + For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is + recommended that the lower 32 bits of the register are accessed through mireg, + while the upper 32 bits are accessed through mireg4. fields: VALUE: + long_name: Indirectly Selected Register Value location_rv32: 31-0 location_rv64: 63-0 type: RW - description: Register state of the CSR selected by the current `miselect` value + description: + - id: csr-mireg-value-purpose + normative: true + text: Register state of the CSR selected by the current `miselect` value reset_value: UNDEFINED_LEGAL + sw_read(): | diff --git a/arch/csr/Smcsrind/mireg2.yaml b/arch/csr/Smcsrind/mireg2.yaml index 659cdcaacf..7eef57ad56 100644 --- a/arch/csr/Smcsrind/mireg2.yaml +++ b/arch/csr/Smcsrind/mireg2.yaml @@ -7,37 +7,56 @@ address: 0x352 priv_mode: M length: MXLEN definedBy: Smcsrind -description: | - The `mireg2` machine indirect alias CSR is used to access register state indirectly - upon a read or write, as determined by the value of `miselect`. +description: + - id: csr-mireg2-purpose + normative: true + text: | + The `mireg2` machine indirect alias CSR is used to access register state indirectly + upon a read or write, as determined by the value of `miselect`. - The behavior upon accessing `mireg2` from M-mode, while `miselect` holds a value - that is not implemented, is UNSPECIFIED. + - id: csr-mireg2-unimplemented-miselect + normative: true + text: | + The behavior upon accessing `mireg2` from M-mode, while `miselect` holds a value + that is not implemented, is UNSPECIFIED. - [Note] - It is expected that implementations will typically raise an illegal instruction exception for - such accesses, so that, for example, they can be identified as software bugs. Platform - specs, profile specs, and/or the Privileged ISA spec may place more restrictions on - behavior for such accesses. + - id: csr-mireg2-unimplemented-miselect-typical + normative: false + text: | + It is expected that implementations will typically raise an illegal instruction exception for + such accesses, so that, for example, they can be identified as software bugs. Platform + specs, profile specs, and/or the Privileged ISA spec may place more restrictions on + behavior for such accesses. - Attempts to access `mireg2` while `miselect` holds a number in an allocated and implemented - range results in a specific behavior that, for each combination of `miselect` and `mireg2`, is - defined by the extension to which the `miselect` value is allocated. + - id: csr-mireg2-implemented-miselect + normative: true + text: | + Attempts to access `mireg2` while `miselect` holds a number in an allocated and implemented + range results in a specific behavior that, for each combination of `miselect` and `mireg2`, is + defined by the extension to which the `miselect` value is allocated. - [Note] - Ordinarily, `mireg2` will access register state, access read-only 0 state, or raise an - illegal instruction exception. + - id: csr-mireg2-behavior-typical + normative: false + text: | + Ordinarily, `mireg2` will access register state, access read-only 0 state, or raise an + illegal instruction exception. - [Note] - For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is - recommended that the lower 32 bits of the register are accessed through `mireg2`, - while the upper 32 bits are accessed through `mireg5`. + - id: csr-mireg2-rv32-64bit-access + normative: false + text: | + For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is + recommended that the lower 32 bits of the register are accessed through `mireg2`, + while the upper 32 bits are accessed through `mireg5`. fields: VALUE: + long_name: Indirect Register Value location_rv32: 31-0 location_rv64: 63-0 type: RW - description: Register state of the CSR selected by the current `miselect` value + description: + - id: csr-mireg2-value-purpose + normative: true + text: Register state of the CSR selected by the current `miselect` value reset_value: UNDEFINED_LEGAL sw_read(): | diff --git a/arch/csr/Smcsrind/mireg3.yaml b/arch/csr/Smcsrind/mireg3.yaml index 8c77929a91..4e4de85355 100644 --- a/arch/csr/Smcsrind/mireg3.yaml +++ b/arch/csr/Smcsrind/mireg3.yaml @@ -7,37 +7,56 @@ address: 0x353 priv_mode: M length: MXLEN definedBy: Smcsrind -description: | - The `mireg3` machine indirect alias CSR is used to access register state indirectly - upon a read or write, as determined by the value of `miselect`. +description: + - id: csr-mireg3-purpose + normative: true + text: | + The `mireg3` machine indirect alias CSR is used to access register state indirectly + upon a read or write, as determined by the value of `miselect`. - The behavior upon accessing `mireg3` from M-mode, while `miselect` holds a value - that is not implemented, is UNSPECIFIED. + - id: csr-mireg3-unimplemented-miselect + normative: true + text: | + The behavior upon accessing `mireg3` from M-mode, while `miselect` holds a value + that is not implemented, is UNSPECIFIED. - [Note] - It is expected that implementations will typically raise an illegal instruction exception for - such accesses, so that, for example, they can be identified as software bugs. Platform - specs, profile specs, and/or the Privileged ISA spec may place more restrictions on - behavior for such accesses. + - id: csr-mireg3-unimplemented-miselect-note + normative: false + text: | + It is expected that implementations will typically raise an illegal instruction exception for + such accesses, so that, for example, they can be identified as software bugs. Platform + specs, profile specs, and/or the Privileged ISA spec may place more restrictions on + behavior for such accesses. - Attempts to access `mireg3` while `miselect` holds a number in an allocated and implemented - range results in a specific behavior that, for each combination of `miselect` and `mireg3`, is - defined by the extension to which the `miselect` value is allocated. + - id: csr-mireg3-implemented-miselect + normative: true + text: | + Attempts to access `mireg3` while `miselect` holds a number in an allocated and implemented + range results in a specific behavior that, for each combination of `miselect` and `mireg3`, is + defined by the extension to which the `miselect` value is allocated. - [Note] - Ordinarily, `mireg3` will access register state, access read-only 0 state, or raise an - illegal instruction exception. + - id: csr-mireg3-implemented-miselect-note + normative: false + text: | + Ordinarily, `mireg3` will access register state, access read-only 0 state, or raise an + illegal instruction exception. - [Note] - For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is - recommended that the lower 32 bits of the register are accessed through `mireg3`, - while the upper 32 bits are accessed through `mireg6`. + - id: csr-mireg3-rv32-64bit-access + normative: false + text: | + For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is + recommended that the lower 32 bits of the register are accessed through `mireg3`, + while the upper 32 bits are accessed through `mireg6`. fields: VALUE: + long_name: Indirectly Selected Register Value location_rv32: 31-0 location_rv64: 63-0 type: RW - description: Register state of the CSR selected by the current `miselect` value + description: + - id: csr-mireg3-value-purpose + normative: true + text: Register state of the CSR selected by the current `miselect` value reset_value: UNDEFINED_LEGAL sw_read(): | diff --git a/arch/csr/Smcsrind/mireg4.yaml b/arch/csr/Smcsrind/mireg4.yaml index 389f93a58e..f64d6cc6f5 100644 --- a/arch/csr/Smcsrind/mireg4.yaml +++ b/arch/csr/Smcsrind/mireg4.yaml @@ -7,37 +7,56 @@ address: 0x355 priv_mode: M length: MXLEN definedBy: Smcsrind -description: | - The `mireg4` machine indirect alias CSR is used to access register state indirectly - upon a read or write, as determined by the value of `miselect`. +description: + - id: csr-mireg4-purpose + normative: true + text: | + The `mireg4` machine indirect alias CSR is used to access register state indirectly + upon a read or write, as determined by the value of `miselect`. - The behavior upon accessing `mireg4` from M-mode, while `miselect` holds a value - that is not implemented, is UNSPECIFIED. + - id: csr-mireg4-unimplemented-miselect + normative: true + text: | + The behavior upon accessing `mireg4` from M-mode, while `miselect` holds a value + that is not implemented, is UNSPECIFIED. - [Note] - It is expected that implementations will typically raise an illegal instruction exception for - such accesses, so that, for example, they can be identified as software bugs. Platform - specs, profile specs, and/or the Privileged ISA spec may place more restrictions on - behavior for such accesses. + - id: csr-mireg4-unimplemented-miselect-note + normative: false + text: | + It is expected that implementations will typically raise an illegal instruction exception for + such accesses, so that, for example, they can be identified as software bugs. Platform + specs, profile specs, and/or the Privileged ISA spec may place more restrictions on + behavior for such accesses. - Attempts to access `mireg4` while `miselect` holds a number in an allocated and implemented - range results in a specific behavior that, for each combination of `miselect` and `mireg4`, is - defined by the extension to which the `miselect` value is allocated. + - id: csr-mireg4-implemented-miselect + normative: true + text: | + Attempts to access `mireg4` while `miselect` holds a number in an allocated and implemented + range results in a specific behavior that, for each combination of `miselect` and `mireg4`, is + defined by the extension to which the `miselect` value is allocated. - [Note] - Ordinarily, `mireg4` will access register state, access read-only 0 state, or raise an - illegal instruction exception. + - id: csr-mireg4-implemented-miselect-note + normative: false + text: | + Ordinarily, `mireg4` will access register state, access read-only 0 state, or raise an + illegal instruction exception. - [Note] - For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is - recommended that the upper 32 bits of the register are accessed through `mireg4`, - while the lower 32 bits are accessed through `mireg`, `mireg2`, or `mireg3`. + - id: csr-mireg4-rv32-64bit-access + normative: false + text: | + For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is + recommended that the upper 32 bits of the register are accessed through `mireg4`, + while the lower 32 bits are accessed through `mireg`, `mireg2`, or `mireg3`. fields: VALUE: + long_name: Indirectly Selected Register Value location_rv32: 31-0 location_rv64: 63-0 type: RW - description: Register state of the CSR selected by the current `miselect` value + description: + - id: csr-mireg4-value-purpose + normative: true + text: Register state of the CSR selected by the current `miselect` value reset_value: UNDEFINED_LEGAL sw_read(): | diff --git a/arch/csr/Smcsrind/mireg5.yaml b/arch/csr/Smcsrind/mireg5.yaml index 71b3dd3e6c..0880d900cf 100644 --- a/arch/csr/Smcsrind/mireg5.yaml +++ b/arch/csr/Smcsrind/mireg5.yaml @@ -7,37 +7,56 @@ address: 0x356 priv_mode: M length: MXLEN definedBy: Smcsrind -description: | - The `mireg5` machine indirect alias CSR is used to access register state indirectly - upon a read or write, as determined by the value of `miselect`. +description: + - id: csr-mireg5-purpose + normative: true + text: | + The `mireg5` machine indirect alias CSR is used to access register state indirectly + upon a read or write, as determined by the value of `miselect`. - The behavior upon accessing `mireg5` from M-mode, while `miselect` holds a value - that is not implemented, is UNSPECIFIED. + - id: csr-mireg5-unimplemented-miselect + normative: true + text: | + The behavior upon accessing `mireg5` from M-mode, while `miselect` holds a value + that is not implemented, is UNSPECIFIED. - [Note] - It is expected that implementations will typically raise an illegal instruction exception for - such accesses, so that, for example, they can be identified as software bugs. Platform - specs, profile specs, and/or the Privileged ISA spec may place more restrictions on - behavior for such accesses. + - id: csr-mireg5-unimplemented-miselect-note + normative: false + text: | + It is expected that implementations will typically raise an illegal instruction exception for + such accesses, so that, for example, they can be identified as software bugs. Platform + specs, profile specs, and/or the Privileged ISA spec may place more restrictions on + behavior for such accesses. - Attempts to access `mireg5` while `miselect` holds a number in an allocated and implemented - range results in a specific behavior that, for each combination of `miselect` and `mireg5`, is - defined by the extension to which the `miselect` value is allocated. + - id: csr-mireg5-implemented-miselect + normative: true + text: | + Attempts to access `mireg5` while `miselect` holds a number in an allocated and implemented + range results in a specific behavior that, for each combination of `miselect` and `mireg5`, is + defined by the extension to which the `miselect` value is allocated. - [Note] - Ordinarily, `mireg5` will access register state, access read-only 0 state, or raise an - illegal instruction exception. + - id: csr-mireg5-implemented-miselect-note + normative: false + text: | + Ordinarily, `mireg5` will access register state, access read-only 0 state, or raise an + illegal instruction exception. - [Note] - For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is - recommended that the upper 32 bits of the register are accessed through `mireg5`, - while the lower 32 bits are accessed through `mireg2`. + - id: csr-mireg5-rv32-64bit-access + normative: false + text: | + For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is + recommended that the upper 32 bits of the register are accessed through `mireg5`, + while the lower 32 bits are accessed through `mireg2`. fields: VALUE: + long_name: Indirectly Selected Register Value location_rv32: 31-0 location_rv64: 63-0 type: RW - description: Register state of the CSR selected by the current `miselect` value + description: + - id: csr-mireg5-value-purpose + normative: true + text: Register state of the CSR selected by the current `miselect` value reset_value: UNDEFINED_LEGAL sw_read(): | diff --git a/arch/csr/Smcsrind/mireg6.yaml b/arch/csr/Smcsrind/mireg6.yaml index b963e9f757..4f1c3a2181 100644 --- a/arch/csr/Smcsrind/mireg6.yaml +++ b/arch/csr/Smcsrind/mireg6.yaml @@ -7,37 +7,56 @@ address: 0x357 priv_mode: M length: MXLEN definedBy: Smcsrind -description: | - The `mireg6` machine indirect alias CSR is used to access register state indirectly - upon a read or write, as determined by the value of `miselect`. +description: + - id: csr-mireg6-purpose + normative: true + text: | + The `mireg6` machine indirect alias CSR is used to access register state indirectly + upon a read or write, as determined by the value of `miselect`. - The behavior upon accessing `mireg6` from M-mode, while `miselect` holds a value - that is not implemented, is UNSPECIFIED. + - id: csr-mireg6-unimplemented-miselect + normative: true + text: | + The behavior upon accessing `mireg6` from M-mode, while `miselect` holds a value + that is not implemented, is UNSPECIFIED. - [Note] - It is expected that implementations will typically raise an illegal instruction exception for - such accesses, so that, for example, they can be identified as software bugs. Platform - specs, profile specs, and/or the Privileged ISA spec may place more restrictions on - behavior for such accesses. + - id: csr-mireg6-unimplemented-miselect-note + normative: false + text: | + It is expected that implementations will typically raise an illegal instruction exception for + such accesses, so that, for example, they can be identified as software bugs. Platform + specs, profile specs, and/or the Privileged ISA spec may place more restrictions on + behavior for such accesses. - Attempts to access `mireg6` while `miselect` holds a number in an allocated and implemented - range results in a specific behavior that, for each combination of `miselect` and `mireg6`, is - defined by the extension to which the `miselect` value is allocated. + - id: csr-mireg6-implemented-miselect + normative: true + text: | + Attempts to access `mireg6` while `miselect` holds a number in an allocated and implemented + range results in a specific behavior that, for each combination of `miselect` and `mireg6`, is + defined by the extension to which the `miselect` value is allocated. - [Note] - Ordinarily, `mireg6` will access register state, access read-only 0 state, or raise an - illegal instruction exception. + - id: csr-mireg6-implemented-miselect-note + normative: false + text: | + Ordinarily, `mireg6` will access register state, access read-only 0 state, or raise an + illegal instruction exception. - [Note] - For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is - recommended that the upper 32 bits of the register are accessed through `mireg6`, - while the lower 32 bits are accessed through `mireg3`. + - id: csr-mireg6-rv32-64bit-access + normative: false + text: | + For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is + recommended that the upper 32 bits of the register are accessed through `mireg6`, + while the lower 32 bits are accessed through `mireg3`. fields: VALUE: + long_name: Indirectly Selected Register Value location_rv32: 31-0 location_rv64: 63-0 type: RW - description: Register state of the CSR selected by the current `miselect` value + description: + - id: csr-mireg6-value-purpose + normative: true + text: Register state of the CSR selected by the current `miselect` value reset_value: UNDEFINED_LEGAL sw_read(): | diff --git a/arch/csr/Smcsrind/miselect.yaml b/arch/csr/Smcsrind/miselect.yaml index 4370dffe02..443d3c4bdb 100644 --- a/arch/csr/Smcsrind/miselect.yaml +++ b/arch/csr/Smcsrind/miselect.yaml @@ -7,30 +7,52 @@ address: 0x350 priv_mode: M length: MXLEN definedBy: Smcsrind -description: | - The CSRs listed in the table above provide a window for accessing register state indirectly. The value - of `miselect` determines which register is accessed upon read or write of each of the machine - indirect alias CSRs (`mireg*`). `miselect` value ranges are allocated to dependent extensions, which - specify the register state accessible via each `miregi` register, for each `miselect` value. - `miselect` is a WARL register. +description: + - id: csr-miselect-purpose + normative: true + text: | + The CSRs listed in the table above provide a window for accessing register state indirectly. + The value of `miselect` determines which register is accessed upon read or write of each of + the machine indirect alias CSRs (`mireg*`). `miselect` value ranges are allocated to dependent + extensions, which specify the register state accessible via each `miregi` register, for each + `miselect` value. `miselect` is a WARL register. - The `miselect` register implements at least enough bits to support all implemented `miselect` values - (corresponding to the implemented extensions that utilize `miselect`/`mireg*` to indirectly access - register state). The `miselect` register may be read-only zero if there are no extensions implemented - that utilize it. + - id: csr-miselect-implemented-bits + normative: true + text: | + The `miselect` register implements at least enough bits to support all implemented `miselect` + values (corresponding to the implemented extensions that utilize `miselect`/`mireg*` to + indirectly access register state). The `miselect` register may be read-only zero if there are + no extensions implemented that utilize it. - Values of `miselect` with the most-significant bit set (bit XLEN - 1 = 1) are designated only for - custom use, presumably for accessing custom registers through the alias CSRs. Values of `miselect` - with the most-significant bit clear are designated only for standard use and are reserved until - allocated to a standard architecture extension. If XLEN is changed, the most-significant bit of - `miselect` moves to the new position, retaining its value from before. + - id: csr-miselect-custom-standard-bit + normative: true + text: | + Values of `miselect` with the most-significant bit set (bit XLEN - 1 = 1) are designated only for + custom use, presumably for accessing custom registers through the alias CSRs. Values of + `miselect` with the most-significant bit clear are designated only for standard use and are + reserved until allocated to a standard architecture extension. + + - id: csr-miselect-msb-stability + normative: true + text: | + If XLEN is changed, the most-significant bit of `miselect` moves to the new position, + retaining its value from before. + + - id: csr-miselect-no-custom-support + normative: false + text: | + An implementation is not required to support any custom values for `miselect`. - An implementation is not required to support any custom values for `miselect`. fields: - Value: + VALUE: + long_name: Indirect Register Selector location_rv32: 31-0 location_rv64: 63-0 type: RW - description: Selects which indirect register is accessed via `mireg*`. + description: + - id: csr-miselect-value-purpose + normative: true + text: Selects which indirect register is accessed via `mireg*`. reset_value: UNDEFINED_LEGAL sw_read(): | From 0efc6533d153644d0b83645232a52959b1d9b556 Mon Sep 17 00:00:00 2001 From: syedowaisalishah Date: Mon, 5 May 2025 09:48:31 +0000 Subject: [PATCH 22/29] docs(smcsrind): correct smcsrind CSR YAML files: siselect and sireg[1-6] --- arch/csr/Smcsrind/sireg.yaml | 62 +++++++++++++++++++++------------ arch/csr/Smcsrind/sireg2.yaml | 62 +++++++++++++++++++++------------ arch/csr/Smcsrind/sireg3.yaml | 62 +++++++++++++++++++++------------ arch/csr/Smcsrind/sireg4.yaml | 62 +++++++++++++++++++++------------ arch/csr/Smcsrind/sireg5.yaml | 62 +++++++++++++++++++++------------ arch/csr/Smcsrind/sireg6.yaml | 62 +++++++++++++++++++++------------ arch/csr/Smcsrind/siselect.yaml | 45 +++++++++++++++--------- 7 files changed, 269 insertions(+), 148 deletions(-) diff --git a/arch/csr/Smcsrind/sireg.yaml b/arch/csr/Smcsrind/sireg.yaml index d65cfca874..b59f824511 100644 --- a/arch/csr/Smcsrind/sireg.yaml +++ b/arch/csr/Smcsrind/sireg.yaml @@ -7,38 +7,56 @@ address: 0x151 priv_mode: S length: SXLEN definedBy: Sscsrind -description: | - Access to `sireg` from M-mode or S-mode while `siselect` holds a number in a - standard-defined and implemented range results in specific behavior that, for each combination of - `siselect` and `sireg`, is defined by the extension to which the `siselect` value is allocated. +description: + - id: csr-sireg-behavior-implemented + normative: true + text: | + Access to `sireg` from M-mode or S-mode while `siselect` holds a number in a + standard-defined and implemented range results in specific behavior that, for each combination of + `siselect` and `sireg`, is defined by the extension to which the `siselect` value is allocated. - [Note] - Ordinarily, `sireg` will access register state, access read-only 0 state, or, unless - executing in a virtual machine (covered in the next section), raise an illegal instruction - exception. + - id: csr-sireg-typical-behavior-note + normative: false + text: | + Ordinarily, `sireg` will access register state, access read-only 0 state, or, unless + executing in a virtual machine (covered in the next section), raise an illegal instruction + exception. - Note that the widths of `siselect` and `sireg` are always the current XLEN rather than SXLEN. Hence, - for example, if MXLEN = 64 and SXLEN = 32, then this register is 64 bits when the current - privilege mode is M (running RV64 code) but 32 bits when the privilege mode is S (RV32 code). + - id: csr-sireg-xlens + normative: true + text: | + Note that the widths of `siselect` and `sireg` are always the current XLEN rather than SXLEN. Hence, + for example, if MXLEN = 64 and SXLEN = 32, then this register is 64 bits when the current + privilege mode is M (running RV64 code) but 32 bits when the privilege mode is S (RV32 code). - The behavior upon accessing `sireg` from M-mode or S-mode, while `siselect` holds a value that is - not implemented at supervisor level, is UNSPECIFIED. + - id: csr-sireg-unimplemented + normative: true + text: | + The behavior upon accessing `sireg` from M-mode or S-mode, while `siselect` holds a value that is + not implemented at supervisor level, is UNSPECIFIED. - [Note] - It is recommended that implementations raise an illegal instruction exception for such - accesses, to facilitate possible emulation (by M-mode) of these accesses. + - id: csr-sireg-unimplemented-recommendation + normative: false + text: | + It is recommended that implementations raise an illegal instruction exception for such + accesses, to facilitate possible emulation (by M-mode) of these accesses. - [Note] - An extension is considered not to be implemented at supervisor level if machine level has - disabled the extension for S-mode, such as by the settings of certain fields in CSR - `menvcfg`, for example. + - id: csr-sireg-extension-disabled + normative: false + text: | + An extension is considered not to be implemented at supervisor level if machine level has + disabled the extension for S-mode, such as by the settings of certain fields in CSR + `menvcfg`, for example. fields: VALUE: + long_name: Indirectly Selected Register Value location_rv32: 31-0 location_rv64: 63-0 type: RW - description: | - The data read from or written to the register selected by the current `siselect` value. + description: + - id: csr-sireg-value-desc + normative: true + text: The data read from or written to the register selected by the current `siselect` value. reset_value: UNDEFINED_LEGAL sw_read(): | diff --git a/arch/csr/Smcsrind/sireg2.yaml b/arch/csr/Smcsrind/sireg2.yaml index 5ba380bf4c..921ea21f49 100644 --- a/arch/csr/Smcsrind/sireg2.yaml +++ b/arch/csr/Smcsrind/sireg2.yaml @@ -7,38 +7,56 @@ address: 0x152 priv_mode: S length: SXLEN definedBy: Sscsrind -description: | - Access to `sireg2` from M-mode or S-mode while `siselect` holds a number in a - standard-defined and implemented range results in specific behavior that, for each combination of - `siselect` and `sireg2`, is defined by the extension to which the `siselect` value is allocated. +description: + - id: csr-sireg2-behavior-implemented + normative: true + text: | + Access to `sireg2` from M-mode or S-mode while `siselect` holds a number in a + standard-defined and implemented range results in specific behavior that, for each combination of + `siselect` and `sireg2`, is defined by the extension to which the `siselect` value is allocated. - [Note] - Ordinarily, `sireg2` will access register state, access read-only 0 state, or, unless - executing in a virtual machine (covered in the next section), raise an illegal instruction - exception. + - id: csr-sireg2-typical-behavior-note + normative: false + text: | + Ordinarily, `sireg2` will access register state, access read-only 0 state, or, unless + executing in a virtual machine (covered in the next section), raise an illegal instruction + exception. - Note that the widths of `siselect` and `sireg2` are always the current XLEN rather than SXLEN. Hence, - for example, if MXLEN = 64 and SXLEN = 32, then this register is 64 bits when the current - privilege mode is M (running RV64 code) but 32 bits when the privilege mode is S (RV32 code). + - id: csr-sireg2-xlens + normative: true + text: | + Note that the widths of `siselect` and `sireg2` are always the current XLEN rather than SXLEN. Hence, + for example, if MXLEN = 64 and SXLEN = 32, then this register is 64 bits when the current + privilege mode is M (running RV64 code) but 32 bits when the privilege mode is S (RV32 code). - The behavior upon accessing `sireg2` from M-mode or S-mode, while `siselect` holds a value that is - not implemented at supervisor level, is UNSPECIFIED. + - id: csr-sireg2-unimplemented + normative: true + text: | + The behavior upon accessing `sireg2` from M-mode or S-mode, while `siselect` holds a value that is + not implemented at supervisor level, is UNSPECIFIED. - [Note] - It is recommended that implementations raise an illegal instruction exception for such - accesses, to facilitate possible emulation (by M-mode) of these accesses. + - id: csr-sireg2-unimplemented-recommendation + normative: false + text: | + It is recommended that implementations raise an illegal instruction exception for such + accesses, to facilitate possible emulation (by M-mode) of these accesses. - [Note] - An extension is considered not to be implemented at supervisor level if machine level has - disabled the extension for S-mode, such as by the settings of certain fields in CSR - `menvcfg`, for example. + - id: csr-sireg2-extension-disabled + normative: false + text: | + An extension is considered not to be implemented at supervisor level if machine level has + disabled the extension for S-mode, such as by the settings of certain fields in CSR + `menvcfg`, for example. fields: VALUE: + long_name: Indirectly Selected Register Value location_rv32: 31-0 location_rv64: 63-0 type: RW - description: | - The data read from or written to the register selected by the current `siselect` value. + description: + - id: csr-sireg2-value-desc + normative: true + text: The data read from or written to the register selected by the current `siselect` value. reset_value: UNDEFINED_LEGAL sw_read(): | diff --git a/arch/csr/Smcsrind/sireg3.yaml b/arch/csr/Smcsrind/sireg3.yaml index 7a4ec67c76..fedecd88bb 100644 --- a/arch/csr/Smcsrind/sireg3.yaml +++ b/arch/csr/Smcsrind/sireg3.yaml @@ -7,38 +7,56 @@ address: 0x153 priv_mode: S length: SXLEN definedBy: Sscsrind -description: | - Access to `sireg3` from M-mode or S-mode while `siselect` holds a number in a - standard-defined and implemented range results in specific behavior that, for each combination of - `siselect` and `sireg3`, is defined by the extension to which the `siselect` value is allocated. +description: + - id: csr-sireg3-behavior-implemented + normative: true + text: | + Access to `sireg3` from M-mode or S-mode while `siselect` holds a number in a + standard-defined and implemented range results in specific behavior that, for each combination of + `siselect` and `sireg3`, is defined by the extension to which the `siselect` value is allocated. - [Note] - Ordinarily, `sireg3` will access register state, access read-only 0 state, or, unless - executing in a virtual machine (covered in the next section), raise an illegal instruction - exception. + - id: csr-sireg3-typical-behavior-note + normative: false + text: | + Ordinarily, `sireg3` will access register state, access read-only 0 state, or, unless + executing in a virtual machine (covered in the next section), raise an illegal instruction + exception. - Note that the widths of `siselect` and `sireg3` are always the current XLEN rather than SXLEN. Hence, - for example, if MXLEN = 64 and SXLEN = 32, then this register is 64 bits when the current - privilege mode is M (running RV64 code) but 32 bits when the privilege mode is S (RV32 code). + - id: csr-sireg3-xlens + normative: true + text: | + Note that the widths of `siselect` and `sireg3` are always the current XLEN rather than SXLEN. Hence, + for example, if MXLEN = 64 and SXLEN = 32, then this register is 64 bits when the current + privilege mode is M (running RV64 code) but 32 bits when the privilege mode is S (RV32 code). - The behavior upon accessing `sireg3` from M-mode or S-mode, while `siselect` holds a value that is - not implemented at supervisor level, is UNSPECIFIED. + - id: csr-sireg3-unimplemented + normative: true + text: | + The behavior upon accessing `sireg3` from M-mode or S-mode, while `siselect` holds a value that is + not implemented at supervisor level, is UNSPECIFIED. - [Note] - It is recommended that implementations raise an illegal instruction exception for such - accesses, to facilitate possible emulation (by M-mode) of these accesses. + - id: csr-sireg3-unimplemented-recommendation + normative: false + text: | + It is recommended that implementations raise an illegal instruction exception for such + accesses, to facilitate possible emulation (by M-mode) of these accesses. - [Note] - An extension is considered not to be implemented at supervisor level if machine level has - disabled the extension for S-mode, such as by the settings of certain fields in CSR - `menvcfg`, for example. + - id: csr-sireg3-extension-disabled + normative: false + text: | + An extension is considered not to be implemented at supervisor level if machine level has + disabled the extension for S-mode, such as by the settings of certain fields in CSR + `menvcfg`, for example. fields: VALUE: + long_name: Indirectly Selected Register Value location_rv32: 31-0 location_rv64: 63-0 type: RW - description: | - The data read from or written to the register selected by the current `siselect` value. + description: + - id: csr-sireg3-value-desc + normative: true + text: The data read from or written to the register selected by the current `siselect` value. reset_value: UNDEFINED_LEGAL sw_read(): | diff --git a/arch/csr/Smcsrind/sireg4.yaml b/arch/csr/Smcsrind/sireg4.yaml index 71c7fd2dc1..d42c130968 100644 --- a/arch/csr/Smcsrind/sireg4.yaml +++ b/arch/csr/Smcsrind/sireg4.yaml @@ -7,38 +7,56 @@ address: 0x155 priv_mode: S length: SXLEN definedBy: Sscsrind -description: | - Access to `sireg4` from M-mode or S-mode while `siselect` holds a number in a - standard-defined and implemented range results in specific behavior that, for each combination of - `siselect` and `sireg4`, is defined by the extension to which the `siselect` value is allocated. +description: + - id: csr-sireg4-behavior-implemented + normative: true + text: | + Access to `sireg4` from M-mode or S-mode while `siselect` holds a number in a + standard-defined and implemented range results in specific behavior that, for each combination of + `siselect` and `sireg4`, is defined by the extension to which the `siselect` value is allocated. - [Note] - Ordinarily, `sireg4` will access register state, access read-only 0 state, or, unless - executing in a virtual machine (covered in the next section), raise an illegal instruction - exception. + - id: csr-sireg4-typical-behavior-note + normative: false + text: | + Ordinarily, `sireg4` will access register state, access read-only 0 state, or, unless + executing in a virtual machine (covered in the next section), raise an illegal instruction + exception. - Note that the widths of `siselect` and `sireg4` are always the current XLEN rather than SXLEN. Hence, - for example, if MXLEN = 64 and SXLEN = 32, then this register is 64 bits when the current - privilege mode is M (running RV64 code) but 32 bits when the privilege mode is S (RV32 code). + - id: csr-sireg4-xlens + normative: true + text: | + Note that the widths of `siselect` and `sireg4` are always the current XLEN rather than SXLEN. Hence, + for example, if MXLEN = 64 and SXLEN = 32, then this register is 64 bits when the current + privilege mode is M (running RV64 code) but 32 bits when the privilege mode is S (RV32 code). - The behavior upon accessing `sireg4` from M-mode or S-mode, while `siselect` holds a value that is - not implemented at supervisor level, is UNSPECIFIED. + - id: csr-sireg4-unimplemented + normative: true + text: | + The behavior upon accessing `sireg4` from M-mode or S-mode, while `siselect` holds a value that is + not implemented at supervisor level, is UNSPECIFIED. - [Note] - It is recommended that implementations raise an illegal instruction exception for such - accesses, to facilitate possible emulation (by M-mode) of these accesses. + - id: csr-sireg4-unimplemented-recommendation + normative: false + text: | + It is recommended that implementations raise an illegal instruction exception for such + accesses, to facilitate possible emulation (by M-mode) of these accesses. - [Note] - An extension is considered not to be implemented at supervisor level if machine level has - disabled the extension for S-mode, such as by the settings of certain fields in CSR - `menvcfg`, for example. + - id: csr-sireg4-extension-disabled + normative: false + text: | + An extension is considered not to be implemented at supervisor level if machine level has + disabled the extension for S-mode, such as by the settings of certain fields in CSR + `menvcfg`, for example. fields: VALUE: + long_name: Indirectly Selected Register Value location_rv32: 31-0 location_rv64: 63-0 type: RW - description: | - The data read from or written to the register selected by the current `siselect` value. + description: + - id: csr-sireg4-value-desc + normative: true + text: The data read from or written to the register selected by the current `siselect` value. reset_value: UNDEFINED_LEGAL sw_read(): | diff --git a/arch/csr/Smcsrind/sireg5.yaml b/arch/csr/Smcsrind/sireg5.yaml index 0e14b544e3..55a7170825 100644 --- a/arch/csr/Smcsrind/sireg5.yaml +++ b/arch/csr/Smcsrind/sireg5.yaml @@ -7,38 +7,56 @@ address: 0x156 priv_mode: S length: SXLEN definedBy: Sscsrind -description: | - Access to `sireg5` from M-mode or S-mode while `siselect` holds a number in a - standard-defined and implemented range results in specific behavior that, for each combination of - `siselect` and `sireg5`, is defined by the extension to which the `siselect` value is allocated. +description: + - id: csr-sireg5-behavior-implemented + normative: true + text: | + Access to `sireg5` from M-mode or S-mode while `siselect` holds a number in a + standard-defined and implemented range results in specific behavior that, for each combination of + `siselect` and `sireg5`, is defined by the extension to which the `siselect` value is allocated. - [Note] - Ordinarily, `sireg5` will access register state, access read-only 0 state, or, unless - executing in a virtual machine (covered in the next section), raise an illegal instruction - exception. + - id: csr-sireg5-typical-behavior-note + normative: false + text: | + Ordinarily, `sireg5` will access register state, access read-only 0 state, or, unless + executing in a virtual machine (covered in the next section), raise an illegal instruction + exception. - Note that the widths of `siselect` and `sireg5` are always the current XLEN rather than SXLEN. Hence, - for example, if MXLEN = 64 and SXLEN = 32, then this register is 64 bits when the current - privilege mode is M (running RV64 code) but 32 bits when the privilege mode is S (RV32 code). + - id: csr-sireg5-xlens + normative: true + text: | + Note that the widths of `siselect` and `sireg5` are always the current XLEN rather than SXLEN. Hence, + for example, if MXLEN = 64 and SXLEN = 32, then this register is 64 bits when the current + privilege mode is M (running RV64 code) but 32 bits when the privilege mode is S (RV32 code). - The behavior upon accessing `sireg5` from M-mode or S-mode, while `siselect` holds a value that is - not implemented at supervisor level, is UNSPECIFIED. + - id: csr-sireg5-unimplemented + normative: true + text: | + The behavior upon accessing `sireg5` from M-mode or S-mode, while `siselect` holds a value that is + not implemented at supervisor level, is UNSPECIFIED. - [Note] - It is recommended that implementations raise an illegal instruction exception for such - accesses, to facilitate possible emulation (by M-mode) of these accesses. + - id: csr-sireg5-unimplemented-recommendation + normative: false + text: | + It is recommended that implementations raise an illegal instruction exception for such + accesses, to facilitate possible emulation (by M-mode) of these accesses. - [Note] - An extension is considered not to be implemented at supervisor level if machine level has - disabled the extension for S-mode, such as by the settings of certain fields in CSR - `menvcfg`, for example. + - id: csr-sireg5-extension-disabled + normative: false + text: | + An extension is considered not to be implemented at supervisor level if machine level has + disabled the extension for S-mode, such as by the settings of certain fields in CSR + `menvcfg`, for example. fields: VALUE: + long_name: Indirectly Selected Register Value location_rv32: 31-0 location_rv64: 63-0 type: RW - description: | - The data read from or written to the register selected by the current `siselect` value. + description: + - id: csr-sireg5-value-desc + normative: true + text: The data read from or written to the register selected by the current `siselect` value. reset_value: UNDEFINED_LEGAL sw_read(): | diff --git a/arch/csr/Smcsrind/sireg6.yaml b/arch/csr/Smcsrind/sireg6.yaml index 10554d6e74..d9c5874836 100644 --- a/arch/csr/Smcsrind/sireg6.yaml +++ b/arch/csr/Smcsrind/sireg6.yaml @@ -7,38 +7,56 @@ address: 0x157 priv_mode: S length: SXLEN definedBy: Sscsrind -description: | - Access to `sireg6` from M-mode or S-mode while `siselect` holds a number in a - standard-defined and implemented range results in specific behavior that, for each combination of - `siselect` and `sireg6`, is defined by the extension to which the `siselect` value is allocated. +description: + - id: csr-sireg6-behavior-implemented + normative: true + text: | + Access to `sireg6` from M-mode or S-mode while `siselect` holds a number in a + standard-defined and implemented range results in specific behavior that, for each combination of + `siselect` and `sireg6`, is defined by the extension to which the `siselect` value is allocated. - [Note] - Ordinarily, `sireg6` will access register state, access read-only 0 state, or, unless - executing in a virtual machine (covered in the next section), raise an illegal instruction - exception. + - id: csr-sireg6-typical-behavior-note + normative: false + text: | + Ordinarily, `sireg6` will access register state, access read-only 0 state, or, unless + executing in a virtual machine (covered in the next section), raise an illegal instruction + exception. - Note that the widths of `siselect` and `sireg6` are always the current XLEN rather than SXLEN. Hence, - for example, if MXLEN = 64 and SXLEN = 32, then this register is 64 bits when the current - privilege mode is M (running RV64 code) but 32 bits when the privilege mode is S (RV32 code). + - id: csr-sireg6-xlens + normative: true + text: | + Note that the widths of `siselect` and `sireg6` are always the current XLEN rather than SXLEN. Hence, + for example, if MXLEN = 64 and SXLEN = 32, then this register is 64 bits when the current + privilege mode is M (running RV64 code) but 32 bits when the privilege mode is S (RV32 code). - The behavior upon accessing `sireg6` from M-mode or S-mode, while `siselect` holds a value that is - not implemented at supervisor level, is UNSPECIFIED. + - id: csr-sireg6-unimplemented + normative: true + text: | + The behavior upon accessing `sireg6` from M-mode or S-mode, while `siselect` holds a value that is + not implemented at supervisor level, is UNSPECIFIED. - [Note] - It is recommended that implementations raise an illegal instruction exception for such - accesses, to facilitate possible emulation (by M-mode) of these accesses. + - id: csr-sireg6-unimplemented-recommendation + normative: false + text: | + It is recommended that implementations raise an illegal instruction exception for such + accesses, to facilitate possible emulation (by M-mode) of these accesses. - [Note] - An extension is considered not to be implemented at supervisor level if machine level has - disabled the extension for S-mode, such as by the settings of certain fields in CSR - `menvcfg`, for example. + - id: csr-sireg6-extension-disabled + normative: false + text: | + An extension is considered not to be implemented at supervisor level if machine level has + disabled the extension for S-mode, such as by the settings of certain fields in CSR + `menvcfg`, for example. fields: VALUE: + long_name: Indirectly Selected Register Value location_rv32: 31-0 location_rv64: 63-0 type: RW - description: | - The data read from or written to the register selected by the current `siselect` value. + description: + - id: csr-sireg6-value-desc + normative: true + text: The data read from or written to the register selected by the current `siselect` value. reset_value: UNDEFINED_LEGAL sw_read(): | diff --git a/arch/csr/Smcsrind/siselect.yaml b/arch/csr/Smcsrind/siselect.yaml index 8f2c5b4796..46bd99678f 100644 --- a/arch/csr/Smcsrind/siselect.yaml +++ b/arch/csr/Smcsrind/siselect.yaml @@ -7,28 +7,41 @@ address: 0x150 priv_mode: S length: SXLEN definedBy: Sscsrind -description: | - The `siselect` register will support the value range 0..0xFFF at a minimum. A future extension may - define a value range outside of this minimum range. Only if such an extension is implemented will - `siselect` be required to support larger values. +description: + - id: csr-siselect-value-range + normative: true + text: | + The `siselect` register will support the value range 0..0xFFF at a minimum. A future extension may + define a value range outside of this minimum range. Only if such an extension is implemented will + `siselect` be required to support larger values. - Requiring a range of 0-0xFFF for `siselect`, even though most or all of the space may be reserved or - inaccessible, permits M-mode to emulate indirectly accessed registers in this implemented range, - including registers that may be standardized in the future. + - id: csr-siselect-emulation + normative: false + text: | + Requiring a range of 0-0xFFF for `siselect`, even though most or all of the space may be reserved or + inaccessible, permits M-mode to emulate indirectly accessed registers in this implemented range, + including registers that may be standardized in the future. - Values of `siselect` with the most-significant bit set (bit XLEN - 1 = 1) are designated only for - custom use, presumably for accessing custom registers through the alias CSRs. Values of `siselect` - with the most-significant bit clear are designated only for standard use and are reserved until - allocated to a standard architecture extension. If XLEN is changed, the most-significant bit of - `siselect` moves to the new position, retaining its value from before. + - id: csr-siselect-msb + normative: true + text: | + Values of `siselect` with the most-significant bit set (bit XLEN - 1 = 1) are designated only for + custom use, presumably for accessing custom registers through the alias CSRs. Values of `siselect` + with the most-significant bit clear are designated only for standard use and are reserved until + allocated to a standard architecture extension. If XLEN is changed, the most-significant bit of + `siselect` moves to the new position, retaining its value from before. fields: - Value: + VALUE: + long_name: Indirect Register Select Value location_rv32: 31-0 location_rv64: 63-0 type: RW - description: | - Value ranges are allocated to dependent extensions, which specify the - register state accessible via each siregi register, for each siselect value. + description: + - id: csr-siselect-value-desc + normative: true + text: | + Value ranges are allocated to dependent extensions, which specify the + register state accessible via each `sireg*` register, for each `siselect` value. reset_value: UNDEFINED_LEGAL sw_read(): | From 34a9a1f8350921d52560af791726a512b0bc0fb7 Mon Sep 17 00:00:00 2001 From: syedowaisalishah Date: Mon, 5 May 2025 10:47:20 +0000 Subject: [PATCH 23/29] docs(smcsrind): correct smcsrind CSR YAML files: vsiselect and vsireg[1-6] --- arch/csr/Smcsrind/vsireg.yaml | 71 ++++++++++++++++++++++---------- arch/csr/Smcsrind/vsireg2.yaml | 62 ++++++++++++++++++++-------- arch/csr/Smcsrind/vsireg3.yaml | 62 ++++++++++++++++++++-------- arch/csr/Smcsrind/vsireg4.yaml | 62 ++++++++++++++++++++-------- arch/csr/Smcsrind/vsireg5.yaml | 62 ++++++++++++++++++++-------- arch/csr/Smcsrind/vsireg6.yaml | 62 ++++++++++++++++++++-------- arch/csr/Smcsrind/vsiselect.yaml | 55 +++++++++++++++++-------- 7 files changed, 313 insertions(+), 123 deletions(-) diff --git a/arch/csr/Smcsrind/vsireg.yaml b/arch/csr/Smcsrind/vsireg.yaml index 38d3387c17..c64981f7e1 100644 --- a/arch/csr/Smcsrind/vsireg.yaml +++ b/arch/csr/Smcsrind/vsireg.yaml @@ -8,31 +8,60 @@ virtual_address: 0x251 priv_mode: VS length: VSXLEN definedBy: Smcsrind -description: | - The `vsireg` CSR is one of several alias registers used to indirectly access - virtual supervisor-level CSRs in VS-mode or VU-mode. The register addressed by - `vsireg` is selected by the current value of the `vsiselect` CSR. The alias - mechanism allows indirect CSR access, which helps in virtualization and future - extensibility. - - A virtual instruction exception is raised for attempts from VS-mode or VU-mode - to directly access `vsiselect` or `vsireg`, or from VU-mode to access - `siselect` or `sireg`. - - The behavior of accesses to `vsireg` when `vsiselect` holds a value that is - not implemented at the HS level is UNSPECIFIED, but implementations are - recommended to raise an illegal instruction exception for such accesses. - - The width of `vsireg` is always the current `XLEN`, not `VSXLEN`. For example, - if `HSXLEN = 64` and `VSXLEN = 32`, then `vsireg` is 64 bits wide when - accessed from HS-mode (RV64), but 32 bits when accessed from VS-mode (RV32). +description: + - id: csr-vsireg-purpose + normative: true + text: | + The `vsireg` CSR is one of several alias registers used to indirectly access + virtual supervisor-level CSRs in VS-mode or VU-mode. + + - id: csr-vsireg-selection-mechanism + normative: true + text: | + The register addressed by `vsireg` is selected by the current value of the `vsiselect` CSR. + + - id: csr-vsireg-indirect-access-benefit + normative: false + text: | + The alias mechanism allows indirect CSR access, which helps in virtualization and future extensibility. + + - id: csr-vsireg-access-exception + normative: true + text: | + A virtual instruction exception is raised for attempts from VS-mode or VU-mode + to directly access `vsiselect` or `vsireg`, or from VU-mode to access `siselect` or `sireg`. + + - id: csr-vsireg-unimplemented-target + normative: true + text: | + The behavior of accesses to `vsireg` when `vsiselect` holds a value that is + not implemented at the HS level is UNSPECIFIED. + + - id: csr-vsireg-unimplemented-target-recommendation + normative: false + text: | + Implementations are recommended to raise an illegal instruction exception for + accesses to unimplemented targets via `vsireg`. + + - id: csr-vsireg-width + normative: true + text: | + The width of `vsireg` is always the current `XLEN`, not `VSXLEN`. + For example, if `HSXLEN = 64` and `VSXLEN = 32`, then `vsireg` is 64 bits wide + when accessed from HS-mode (RV64), but 32 bits when accessed from VS-mode (RV32). + fields: VALUE: + long_name: Indirectly Selected Register Value location_rv32: 31-0 location_rv64: 63-0 type: RW - description: | - The data read from or written to the register selected by the current - value of the `vsiselect` CSR. + description: + - id: csr-vsireg-value-indirect-data + normative: true + text: | + The data read from or written to the register selected by the current + value of the `vsiselect` CSR. reset_value: UNDEFINED_LEGAL + sw_read(): | diff --git a/arch/csr/Smcsrind/vsireg2.yaml b/arch/csr/Smcsrind/vsireg2.yaml index bbb61a571a..31fad2da46 100644 --- a/arch/csr/Smcsrind/vsireg2.yaml +++ b/arch/csr/Smcsrind/vsireg2.yaml @@ -8,31 +8,59 @@ virtual_address: 0x252 priv_mode: VS length: VSXLEN definedBy: Smcsrind -description: | - The `vsireg2` CSR is one of several alias registers used to indirectly access - virtual supervisor-level CSRs in VS-mode or VU-mode. The register addressed by - `vsireg2` is selected by the current value of the `vsiselect` CSR. The alias - mechanism allows indirect CSR access, which helps in virtualization and future - extensibility. +description: + - id: csr-vsireg2-purpose + normative: true + text: | + The `vsireg2` CSR is one of several alias registers used to indirectly access + virtual supervisor-level CSRs in VS-mode or VU-mode. - A virtual instruction exception is raised for attempts from VS-mode or VU-mode - to directly access `vsiselect` or `vsireg2`, or from VU-mode to access - `siselect` or `siregX`. + - id: csr-vsireg2-selection-mechanism + normative: true + text: | + The register addressed by `vsireg2` is selected by the current value of the `vsiselect` CSR. - The behavior of accesses to `vsireg2` when `vsiselect` holds a value that is - not implemented at the HS level is UNSPECIFIED, but implementations are - recommended to raise an illegal instruction exception for such accesses. + - id: csr-vsireg2-indirect-access-benefit + normative: false + text: | + The alias mechanism allows indirect CSR access, which helps in virtualization and future extensibility. - The width of `vsireg2` is always the current `XLEN`, not `VSXLEN`. For example, - if `HSXLEN = 64` and `VSXLEN = 32`, then `vsireg2` is 64 bits wide when - accessed from HS-mode (RV64), but 32 bits when accessed from VS-mode (RV32). + - id: csr-vsireg2-access-exception + normative: true + text: | + A virtual instruction exception is raised for attempts from VS-mode or VU-mode + to directly access `vsiselect` or `vsireg2`, or from VU-mode to access `siselect` or `siregX`. + + - id: csr-vsireg2-unimplemented-target + normative: true + text: | + The behavior of accesses to `vsireg2` when `vsiselect` holds a value that is + not implemented at the HS level is UNSPECIFIED. + + - id: csr-vsireg2-unimplemented-target-recommendation + normative: false + text: | + Implementations are recommended to raise an illegal instruction exception for + accesses to unimplemented targets via `vsireg2`. + + - id: csr-vsireg2-width + normative: true + text: | + The width of `vsireg2` is always the current `XLEN`, not `VSXLEN`. + For example, if `HSXLEN = 64` and `VSXLEN = 32`, then `vsireg2` is 64 bits wide + when accessed from HS-mode (RV64), but 32 bits when accessed from VS-mode (RV32). fields: VALUE: + long_name: Indirectly Selected Register Value location_rv32: 31-0 location_rv64: 63-0 type: RW - description: | - Data read or written based on the currently selected `vsiselect` value. + description: + - id: csr-vsireg2-value-indirect-data + normative: true + text: | + Data read or written based on the currently selected `vsiselect` value. reset_value: UNDEFINED_LEGAL + sw_read(): | diff --git a/arch/csr/Smcsrind/vsireg3.yaml b/arch/csr/Smcsrind/vsireg3.yaml index 7f94c46171..86ccb349ab 100644 --- a/arch/csr/Smcsrind/vsireg3.yaml +++ b/arch/csr/Smcsrind/vsireg3.yaml @@ -8,31 +8,59 @@ virtual_address: 0x253 priv_mode: VS length: VSXLEN definedBy: Smcsrind -description: | - The `vsireg3` CSR is one of several alias registers used to indirectly access - virtual supervisor-level CSRs in VS-mode or VU-mode. The register addressed by - `vsireg3` is selected by the current value of the `vsiselect` CSR. The alias - mechanism allows indirect CSR access, which helps in virtualization and future - extensibility. +description: + - id: csr-vsireg3-purpose + normative: true + text: | + The `vsireg3` CSR is one of several alias registers used to indirectly access + virtual supervisor-level CSRs in VS-mode or VU-mode. - A virtual instruction exception is raised for attempts from VS-mode or VU-mode - to directly access `vsiselect` or `vsireg3`, or from VU-mode to access - `siselect` or `siregX`. + - id: csr-vsireg3-selection-mechanism + normative: true + text: | + The register addressed by `vsireg3` is selected by the current value of the `vsiselect` CSR. - The behavior of accesses to `vsireg3` when `vsiselect` holds a value that is - not implemented at the HS level is UNSPECIFIED, but implementations are - recommended to raise an illegal instruction exception for such accesses. + - id: csr-vsireg3-indirect-access-benefit + normative: false + text: | + The alias mechanism allows indirect CSR access, which helps in virtualization and future extensibility. - The width of `vsireg3` is always the current `XLEN`, not `VSXLEN`. For example, - if `HSXLEN = 64` and `VSXLEN = 32`, then `vsireg3` is 64 bits wide when - accessed from HS-mode (RV64), but 32 bits when accessed from VS-mode (RV32). + - id: csr-vsireg3-access-exception + normative: true + text: | + A virtual instruction exception is raised for attempts from VS-mode or VU-mode + to directly access `vsiselect` or `vsireg3`, or from VU-mode to access `siselect` or `siregX`. + + - id: csr-vsireg3-unimplemented-target + normative: true + text: | + The behavior of accesses to `vsireg3` when `vsiselect` holds a value that is + not implemented at the HS level is UNSPECIFIED. + + - id: csr-vsireg3-unimplemented-target-recommendation + normative: false + text: | + Implementations are recommended to raise an illegal instruction exception for + accesses to unimplemented targets via `vsireg3`. + + - id: csr-vsireg3-width + normative: true + text: | + The width of `vsireg3` is always the current `XLEN`, not `VSXLEN`. + For example, if `HSXLEN = 64` and `VSXLEN = 32`, then `vsireg3` is 64 bits wide + when accessed from HS-mode (RV64), but 32 bits when accessed from VS-mode (RV32). fields: VALUE: + long_name: Indirectly Selected Register Value location_rv32: 31-0 location_rv64: 63-0 type: RW - description: | - The data read or written based on the currently selected `vsiselect` value. + description: + - id: csr-vsireg3-value-indirect-data + normative: true + text: | + The data read or written based on the currently selected `vsiselect` value. reset_value: UNDEFINED_LEGAL + sw_read(): | diff --git a/arch/csr/Smcsrind/vsireg4.yaml b/arch/csr/Smcsrind/vsireg4.yaml index a2e5e9ca46..e5f8f56a8c 100644 --- a/arch/csr/Smcsrind/vsireg4.yaml +++ b/arch/csr/Smcsrind/vsireg4.yaml @@ -8,31 +8,59 @@ virtual_address: 0x255 priv_mode: VS length: VSXLEN definedBy: Smcsrind -description: | - The `vsireg4` CSR is one of several alias registers used to indirectly access - virtual supervisor-level CSRs in VS-mode or VU-mode. The register addressed by - `vsireg4` is selected by the current value of the `vsiselect` CSR. The alias - mechanism allows indirect CSR access, which helps in virtualization and future - extensibility. +description: + - id: csr-vsireg4-purpose + normative: true + text: | + The `vsireg4` CSR is one of several alias registers used to indirectly access + virtual supervisor-level CSRs in VS-mode or VU-mode. - A virtual instruction exception is raised for attempts from VS-mode or VU-mode - to directly access `vsiselect` or `vsireg4`, or from VU-mode to access - `siselect` or `siregX`. + - id: csr-vsireg4-selection-mechanism + normative: true + text: | + The register addressed by `vsireg4` is selected by the current value of the `vsiselect` CSR. - The behavior of accesses to `vsireg4` when `vsiselect` holds a value that is - not implemented at the HS level is UNSPECIFIED, but implementations are - recommended to raise an illegal instruction exception for such accesses. + - id: csr-vsireg4-indirect-access-benefit + normative: false + text: | + The alias mechanism allows indirect CSR access, which helps in virtualization and future extensibility. - The width of `vsireg4` is always the current `XLEN`, not `VSXLEN`. For example, - if `HSXLEN = 64` and `VSXLEN = 32`, then `vsireg4` is 64 bits wide when - accessed from HS-mode (RV64), but 32 bits when accessed from VS-mode (RV32). + - id: csr-vsireg4-access-exception + normative: true + text: | + A virtual instruction exception is raised for attempts from VS-mode or VU-mode + to directly access `vsiselect` or `vsireg4`, or from VU-mode to access `siselect` or `siregX`. + + - id: csr-vsireg4-unimplemented-target + normative: true + text: | + The behavior of accesses to `vsireg4` when `vsiselect` holds a value that is + not implemented at the HS level is UNSPECIFIED. + + - id: csr-vsireg4-unimplemented-target-recommendation + normative: false + text: | + Implementations are recommended to raise an illegal instruction exception for + accesses to unimplemented targets via `vsireg4`. + + - id: csr-vsireg4-width + normative: true + text: | + The width of `vsireg4` is always the current `XLEN`, not `VSXLEN`. + For example, if `HSXLEN = 64` and `VSXLEN = 32`, then `vsireg4` is 64 bits wide + when accessed from HS-mode (RV64), but 32 bits when accessed from VS-mode (RV32). fields: VALUE: + long_name: Indirectly Selected Register Value location_rv32: 31-0 location_rv64: 63-0 type: RW - description: | - Data read or written based on the currently selected `vsiselect` value. + description: + - id: csr-vsireg4-value-indirect-data + normative: true + text: | + The data read or written based on the currently selected `vsiselect` value. reset_value: UNDEFINED_LEGAL + sw_read(): | diff --git a/arch/csr/Smcsrind/vsireg5.yaml b/arch/csr/Smcsrind/vsireg5.yaml index c50606bb78..bbd4b19ead 100644 --- a/arch/csr/Smcsrind/vsireg5.yaml +++ b/arch/csr/Smcsrind/vsireg5.yaml @@ -8,31 +8,59 @@ virtual_address: 0x256 priv_mode: VS length: VSXLEN definedBy: Smcsrind -description: | - The `vsireg5` CSR is one of several alias registers used to indirectly access - virtual supervisor-level CSRs in VS-mode or VU-mode. The register addressed by - `vsireg5` is selected by the current value of the `vsiselect` CSR. The alias - mechanism allows indirect CSR access, which helps in virtualization and future - extensibility. +description: + - id: csr-vsireg5-purpose + normative: true + text: | + The `vsireg5` CSR is one of several alias registers used to indirectly access + virtual supervisor-level CSRs in VS-mode or VU-mode. - A virtual instruction exception is raised for attempts from VS-mode or VU-mode - to directly access `vsiselect` or `vsireg5`, or from VU-mode to access - `siselect` or `siregX`. + - id: csr-vsireg5-selection + normative: true + text: | + The register addressed by `vsireg5` is selected by the current value of the `vsiselect` CSR. - The behavior of accesses to `vsireg5` when `vsiselect` holds a value that is - not implemented at the HS level is UNSPECIFIED, but implementations are - recommended to raise an illegal instruction exception for such accesses. + - id: csr-vsireg5-benefits + normative: false + text: | + The alias mechanism allows indirect CSR access, which helps in virtualization and future extensibility. - The width of `vsireg5` is always the current `XLEN`, not `VSXLEN`. For example, - if `HSXLEN = 64` and `VSXLEN = 32`, then `vsireg5` is 64 bits wide when - accessed from HS-mode (RV64), but 32 bits when accessed from VS-mode (RV32). + - id: csr-vsireg5-access-traps + normative: true + text: | + A virtual instruction exception is raised for attempts from VS-mode or VU-mode + to directly access `vsiselect` or `vsireg5`, or from VU-mode to access `siselect` or `siregX`. + + - id: csr-vsireg5-unimplemented + normative: true + text: | + The behavior of accesses to `vsireg5` when `vsiselect` holds a value that is + not implemented at the HS level is UNSPECIFIED. + + - id: csr-vsireg5-recommendation + normative: false + text: | + Implementations are recommended to raise an illegal instruction exception for + such accesses to unimplemented targets. + + - id: csr-vsireg5-width + normative: true + text: | + The width of `vsireg5` is always the current `XLEN`, not `VSXLEN`. + For example, if `HSXLEN = 64` and `VSXLEN = 32`, then `vsireg5` is 64 bits wide + when accessed from HS-mode (RV64), but 32 bits when accessed from VS-mode (RV32). fields: VALUE: + long_name: Indirectly Selected Register Value location_rv32: 31-0 location_rv64: 63-0 type: RW - description: | - The data read or written from the register selected by the value in `vsiselect`. + description: + - id: csr-vsireg5-value + normative: true + text: | + The data read or written from the register selected by the value in `vsiselect`. reset_value: UNDEFINED_LEGAL + sw_read(): | diff --git a/arch/csr/Smcsrind/vsireg6.yaml b/arch/csr/Smcsrind/vsireg6.yaml index 8ddd49791e..0bd5b4ea75 100644 --- a/arch/csr/Smcsrind/vsireg6.yaml +++ b/arch/csr/Smcsrind/vsireg6.yaml @@ -8,31 +8,59 @@ virtual_address: 0x257 priv_mode: VS length: VSXLEN definedBy: Smcsrind -description: | - The `vsireg6` CSR is one of several alias registers used to indirectly access - virtual supervisor-level CSRs in VS-mode or VU-mode. The register addressed by - `vsireg6` is selected by the current value of the `vsiselect` CSR. The alias - mechanism allows indirect CSR access, which helps in virtualization and future - extensibility. +description: + - id: csr-vsireg6-purpose + normative: true + text: | + The `vsireg6` CSR is one of several alias registers used to indirectly access + virtual supervisor-level CSRs in VS-mode or VU-mode. - A virtual instruction exception is raised for attempts from VS-mode or VU-mode - to directly access `vsiselect` or `vsireg6`, or from VU-mode to access - `siselect` or `siregX`. + - id: csr-vsireg6-selection + normative: true + text: | + The register addressed by `vsireg6` is selected by the current value of the `vsiselect` CSR. - The behavior of accesses to `vsireg6` when `vsiselect` holds a value that is - not implemented at the HS level is UNSPECIFIED, but implementations are - recommended to raise an illegal instruction exception for such accesses. + - id: csr-vsireg6-benefits + normative: false + text: | + The alias mechanism allows indirect CSR access, which helps in virtualization and future extensibility. - The width of `vsireg6` is always the current `XLEN`, not `VSXLEN`. For example, - if `HSXLEN = 64` and `VSXLEN = 32`, then `vsireg6` is 64 bits wide when - accessed from HS-mode (RV64), but 32 bits when accessed from VS-mode (RV32). + - id: csr-vsireg6-access-traps + normative: true + text: | + A virtual instruction exception is raised for attempts from VS-mode or VU-mode + to directly access `vsiselect` or `vsireg6`, or from VU-mode to access `siselect` or `siregX`. + + - id: csr-vsireg6-unimplemented + normative: true + text: | + The behavior of accesses to `vsireg6` when `vsiselect` holds a value that is + not implemented at the HS level is UNSPECIFIED. + + - id: csr-vsireg6-recommendation + normative: false + text: | + Implementations are recommended to raise an illegal instruction exception for + such accesses to unimplemented targets. + + - id: csr-vsireg6-width + normative: true + text: | + The width of `vsireg6` is always the current `XLEN`, not `VSXLEN`. + For example, if `HSXLEN = 64` and `VSXLEN = 32`, then `vsireg6` is 64 bits wide + when accessed from HS-mode (RV64), but 32 bits when accessed from VS-mode (RV32). fields: VALUE: + long_name: Indirectly Selected Register Value location_rv32: 31-0 location_rv64: 63-0 type: RW - description: | - The data read or written based on the currently selected `vsiselect` value. + description: + - id: csr-vsireg6-value + normative: true + text: | + The data read or written from the register selected by the current value of `vsiselect`. reset_value: UNDEFINED_LEGAL + sw_read(): | diff --git a/arch/csr/Smcsrind/vsiselect.yaml b/arch/csr/Smcsrind/vsiselect.yaml index b65c585aae..6d712d97c4 100644 --- a/arch/csr/Smcsrind/vsiselect.yaml +++ b/arch/csr/Smcsrind/vsiselect.yaml @@ -8,31 +8,52 @@ virtual_address: 0x250 priv_mode: VS length: VSXLEN definedBy: Smcsrind -description: | - The `vsiselect` register will support the value range 0..0xFFF at a minimum. A future extension may - define a value range outside of this minimum range. Only if such an extension is implemented will - `vsiselect` be required to support larger values. +description: + - id: csr-vsiselect-range-minimum + normative: true + text: | + The `vsiselect` register will support the value range 0..0xFFF at a minimum. + A future extension may define a value range outside of this minimum range. + Only if such an extension is implemented will `vsiselect` be required to support larger values. - Requiring a range of 0-0xFFF for `vsiselect`, even though most or all of the space may be reserved - or inaccessible, permits a hypervisor to emulate indirectly accessed registers in this implemented - range, including registers that may be standardized in the future. + - id: csr-vsiselect-hypervisor-emulation + normative: true + text: | + Requiring a range of 0-0xFFF for `vsiselect`, even though most or all of the space may be reserved + or inaccessible, permits a hypervisor to emulate indirectly accessed registers in this implemented + range, including registers that may be standardized in the future. - More generally it is recommended that `vsiselect` and `siselect` be implemented with the same number - of bits. This also avoids creation of a virtualization hole due to observable differences between - `vsiselect` and `siselect` widths. + - id: csr-vsiselect-siselect-width-matching + normative: false + text: | + It is recommended that `vsiselect` and `siselect` be implemented with the same number of bits. + This avoids the creation of a virtualization hole due to observable differences between their widths. - Values of `vsiselect` with the most-significant bit set (bit XLEN - 1 = 1) are designated only for - custom use, presumably for accessing custom registers through the alias CSRs. Values of `vsiselect` - with the most-significant bit clear are designated only for standard use and are reserved until - allocated to a standard architecture extension. If XLEN is changed, the most-significant bit of - `vsiselect` moves to the new position, retaining its value from before. + - id: csr-vsiselect-msb-custom-vs-standard + normative: true + text: | + Values of `vsiselect` with the most-significant bit set (bit XLEN - 1 = 1) are designated only for + custom use, presumably for accessing custom registers through the alias CSRs. + Values with the most-significant bit clear are designated only for standard use and are reserved + until allocated to a standard architecture extension. + + - id: csr-vsiselect-msb-behavior-xlen-change + normative: true + text: | + If XLEN is changed, the most-significant bit of `vsiselect` moves to the new position, + retaining its value from before. fields: VALUE: + long_name: Indirect Register Select Value location_rv32: 31-0 location_rv64: 63-0 type: RW - description: | - The index value selecting the register accessed through the `vsireg*` alias registers. + description: + - id: csr-vsiselect-value-indirect-access + normative: true + text: | + The index value selecting the register accessed through the `vsireg*` alias registers. reset_value: UNDEFINED_LEGAL + sw_read(): | From 76fc8b1eec5d5b65b59604ba65cfd1362cc348ff Mon Sep 17 00:00:00 2001 From: syedowaisalishah Date: Mon, 5 May 2025 11:45:13 +0000 Subject: [PATCH 24/29] docs(smcsrind): update smcsrind CSR YAML files: mireg[1-6] --- arch/csr/Smcsrind/mireg.yaml | 16 +++++++++++++++- arch/csr/Smcsrind/mireg2.yaml | 15 +++++++++++++++ arch/csr/Smcsrind/mireg3.yaml | 15 +++++++++++++++ arch/csr/Smcsrind/mireg4.yaml | 15 +++++++++++++++ arch/csr/Smcsrind/mireg5.yaml | 15 +++++++++++++++ arch/csr/Smcsrind/mireg6.yaml | 15 +++++++++++++++ 6 files changed, 90 insertions(+), 1 deletion(-) diff --git a/arch/csr/Smcsrind/mireg.yaml b/arch/csr/Smcsrind/mireg.yaml index 3420ff3303..001a4c792b 100644 --- a/arch/csr/Smcsrind/mireg.yaml +++ b/arch/csr/Smcsrind/mireg.yaml @@ -53,5 +53,19 @@ fields: normative: true text: Register state of the CSR selected by the current `miselect` value reset_value: UNDEFINED_LEGAL - + sw_write(csr_value): | + Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 1); + if (!handle.valid) { + unimplemented_csr($encoding); + } + if (!handle.writable) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + csr_sw_write(handle, csr_value.VALUE); + return csr_hw_read(handle); sw_read(): | + Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 1); + if (!handle.valid) { + unimplemented_csr($encoding); + } + return csr_sw_read(handle); diff --git a/arch/csr/Smcsrind/mireg2.yaml b/arch/csr/Smcsrind/mireg2.yaml index 7eef57ad56..48dccc3014 100644 --- a/arch/csr/Smcsrind/mireg2.yaml +++ b/arch/csr/Smcsrind/mireg2.yaml @@ -59,4 +59,19 @@ fields: normative: true text: Register state of the CSR selected by the current `miselect` value reset_value: UNDEFINED_LEGAL + sw_write(csr_value): | + Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 2); + if (!handle.valid) { + unimplemented_csr($encoding); + } + if (!handle.writable) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + csr_sw_write(handle, csr_value.VALUE); + return csr_hw_read(handle); sw_read(): | + Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 2); + if (!handle.valid) { + unimplemented_csr($encoding); + } + return csr_sw_read(handle); diff --git a/arch/csr/Smcsrind/mireg3.yaml b/arch/csr/Smcsrind/mireg3.yaml index 4e4de85355..8e6854ec90 100644 --- a/arch/csr/Smcsrind/mireg3.yaml +++ b/arch/csr/Smcsrind/mireg3.yaml @@ -59,4 +59,19 @@ fields: normative: true text: Register state of the CSR selected by the current `miselect` value reset_value: UNDEFINED_LEGAL + sw_write(csr_value): | + Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 3); + if (!handle.valid) { + unimplemented_csr($encoding); + } + if (!handle.writable) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + csr_sw_write(handle, csr_value.VALUE); + return csr_hw_read(handle); sw_read(): | + Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 3); + if (!handle.valid) { + unimplemented_csr($encoding); + } + return csr_sw_read(handle); diff --git a/arch/csr/Smcsrind/mireg4.yaml b/arch/csr/Smcsrind/mireg4.yaml index f64d6cc6f5..ed1b6dbed7 100644 --- a/arch/csr/Smcsrind/mireg4.yaml +++ b/arch/csr/Smcsrind/mireg4.yaml @@ -59,4 +59,19 @@ fields: normative: true text: Register state of the CSR selected by the current `miselect` value reset_value: UNDEFINED_LEGAL + sw_write(csr_value): | + Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 4); + if (!handle.valid) { + unimplemented_csr($encoding); + } + if (!handle.writable) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + csr_sw_write(handle, csr_value.VALUE); + return csr_hw_read(handle); sw_read(): | + Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 4); + if (!handle.valid) { + unimplemented_csr($encoding); + } + return csr_sw_read(handle); diff --git a/arch/csr/Smcsrind/mireg5.yaml b/arch/csr/Smcsrind/mireg5.yaml index 0880d900cf..211001f028 100644 --- a/arch/csr/Smcsrind/mireg5.yaml +++ b/arch/csr/Smcsrind/mireg5.yaml @@ -59,4 +59,19 @@ fields: normative: true text: Register state of the CSR selected by the current `miselect` value reset_value: UNDEFINED_LEGAL + sw_write(csr_value): | + Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 5); + if (!handle.valid) { + unimplemented_csr($encoding); + } + if (!handle.writable) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + csr_sw_write(handle, csr_value.VALUE); + return csr_hw_read(handle); sw_read(): | + Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 5); + if (!handle.valid) { + unimplemented_csr($encoding); + } + return csr_sw_read(handle); diff --git a/arch/csr/Smcsrind/mireg6.yaml b/arch/csr/Smcsrind/mireg6.yaml index 4f1c3a2181..2ca76a21b1 100644 --- a/arch/csr/Smcsrind/mireg6.yaml +++ b/arch/csr/Smcsrind/mireg6.yaml @@ -59,4 +59,19 @@ fields: normative: true text: Register state of the CSR selected by the current `miselect` value reset_value: UNDEFINED_LEGAL + sw_write(csr_value): | + Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 6); + if (!handle.valid) { + unimplemented_csr($encoding); + } + if (!handle.writable) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + csr_sw_write(handle, csr_value.VALUE); + return csr_hw_read(handle); sw_read(): | + Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 6); + if (!handle.valid) { + unimplemented_csr($encoding); + } + return csr_sw_read(handle); From 31d2cfe6c42851d4c5160a1ce8d4af672ab13371 Mon Sep 17 00:00:00 2001 From: syedowaisalishah Date: Mon, 5 May 2025 11:47:03 +0000 Subject: [PATCH 25/29] docs(smcsrind): update smcsrind CSR YAML files: sireg[1-6] --- arch/csr/Smcsrind/sireg.yaml | 15 +++++++++++++++ arch/csr/Smcsrind/sireg2.yaml | 15 +++++++++++++++ arch/csr/Smcsrind/sireg3.yaml | 15 +++++++++++++++ arch/csr/Smcsrind/sireg4.yaml | 15 +++++++++++++++ arch/csr/Smcsrind/sireg5.yaml | 15 +++++++++++++++ arch/csr/Smcsrind/sireg6.yaml | 15 +++++++++++++++ 6 files changed, 90 insertions(+) diff --git a/arch/csr/Smcsrind/sireg.yaml b/arch/csr/Smcsrind/sireg.yaml index b59f824511..49d6b0ff16 100644 --- a/arch/csr/Smcsrind/sireg.yaml +++ b/arch/csr/Smcsrind/sireg.yaml @@ -59,4 +59,19 @@ fields: normative: true text: The data read from or written to the register selected by the current `siselect` value. reset_value: UNDEFINED_LEGAL + sw_write(csr_value): | + Csr handle = indirect_csr_lookup(CSR[siselect].VALUE, 1); + if (!handle.valid) { + unimplemented_csr($encoding); + } + if (!handle.writable) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + csr_sw_write(handle, csr_value.VALUE); + return csr_hw_read(handle); sw_read(): | + Csr handle = indirect_csr_lookup(CSR[siselect].VALUE, 1); + if (!handle.valid) { + unimplemented_csr($encoding); + } + return csr_sw_read(handle); diff --git a/arch/csr/Smcsrind/sireg2.yaml b/arch/csr/Smcsrind/sireg2.yaml index 921ea21f49..86e7c1e827 100644 --- a/arch/csr/Smcsrind/sireg2.yaml +++ b/arch/csr/Smcsrind/sireg2.yaml @@ -59,4 +59,19 @@ fields: normative: true text: The data read from or written to the register selected by the current `siselect` value. reset_value: UNDEFINED_LEGAL + sw_write(csr_value): | + Csr handle = indirect_csr_lookup(CSR[siselect].VALUE, 2); + if (!handle.valid) { + unimplemented_csr($encoding); + } + if (!handle.writable) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + csr_sw_write(handle, csr_value.VALUE); + return csr_hw_read(handle); sw_read(): | + Csr handle = indirect_csr_lookup(CSR[siselect].VALUE, 2); + if (!handle.valid) { + unimplemented_csr($encoding); + } + return csr_sw_read(handle); diff --git a/arch/csr/Smcsrind/sireg3.yaml b/arch/csr/Smcsrind/sireg3.yaml index fedecd88bb..5fafd84fdb 100644 --- a/arch/csr/Smcsrind/sireg3.yaml +++ b/arch/csr/Smcsrind/sireg3.yaml @@ -59,4 +59,19 @@ fields: normative: true text: The data read from or written to the register selected by the current `siselect` value. reset_value: UNDEFINED_LEGAL + sw_write(csr_value): | + Csr handle = indirect_csr_lookup(CSR[siselect].VALUE, 3); + if (!handle.valid) { + unimplemented_csr($encoding); + } + if (!handle.writable) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + csr_sw_write(handle, csr_value.VALUE); + return csr_hw_read(handle); sw_read(): | + Csr handle = indirect_csr_lookup(CSR[siselect].VALUE, 3); + if (!handle.valid) { + unimplemented_csr($encoding); + } + return csr_sw_read(handle); diff --git a/arch/csr/Smcsrind/sireg4.yaml b/arch/csr/Smcsrind/sireg4.yaml index d42c130968..6dec2acd32 100644 --- a/arch/csr/Smcsrind/sireg4.yaml +++ b/arch/csr/Smcsrind/sireg4.yaml @@ -59,4 +59,19 @@ fields: normative: true text: The data read from or written to the register selected by the current `siselect` value. reset_value: UNDEFINED_LEGAL + sw_write(csr_value): | + Csr handle = indirect_csr_lookup(CSR[siselect].VALUE, 4); + if (!handle.valid) { + unimplemented_csr($encoding); + } + if (!handle.writable) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + csr_sw_write(handle, csr_value.VALUE); + return csr_hw_read(handle); sw_read(): | + Csr handle = indirect_csr_lookup(CSR[siselect].VALUE, 4); + if (!handle.valid) { + unimplemented_csr($encoding); + } + return csr_sw_read(handle); diff --git a/arch/csr/Smcsrind/sireg5.yaml b/arch/csr/Smcsrind/sireg5.yaml index 55a7170825..a5c4c8759b 100644 --- a/arch/csr/Smcsrind/sireg5.yaml +++ b/arch/csr/Smcsrind/sireg5.yaml @@ -59,4 +59,19 @@ fields: normative: true text: The data read from or written to the register selected by the current `siselect` value. reset_value: UNDEFINED_LEGAL + sw_write(csr_value): | + Csr handle = indirect_csr_lookup(CSR[siselect].VALUE, 5); + if (!handle.valid) { + unimplemented_csr($encoding); + } + if (!handle.writable) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + csr_sw_write(handle, csr_value.VALUE); + return csr_hw_read(handle); sw_read(): | + Csr handle = indirect_csr_lookup(CSR[siselect].VALUE, 5); + if (!handle.valid) { + unimplemented_csr($encoding); + } + return csr_sw_read(handle); diff --git a/arch/csr/Smcsrind/sireg6.yaml b/arch/csr/Smcsrind/sireg6.yaml index d9c5874836..9265193b3d 100644 --- a/arch/csr/Smcsrind/sireg6.yaml +++ b/arch/csr/Smcsrind/sireg6.yaml @@ -59,4 +59,19 @@ fields: normative: true text: The data read from or written to the register selected by the current `siselect` value. reset_value: UNDEFINED_LEGAL + sw_write(csr_value): | + Csr handle = indirect_csr_lookup(CSR[siselect].VALUE, 6); + if (!handle.valid) { + unimplemented_csr($encoding); + } + if (!handle.writable) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + csr_sw_write(handle, csr_value.VALUE); + return csr_hw_read(handle); sw_read(): | + Csr handle = indirect_csr_lookup(CSR[siselect].VALUE, 6); + if (!handle.valid) { + unimplemented_csr($encoding); + } + return csr_sw_read(handle); From 4036f19dedf685d3ed574ffca95a45bd95394c9f Mon Sep 17 00:00:00 2001 From: syedowaisalishah Date: Mon, 5 May 2025 11:49:16 +0000 Subject: [PATCH 26/29] docs(smcsrind): update smcsrind CSR YAML files: vsireg[1-6] --- arch/csr/Smcsrind/vsireg.yaml | 16 +++++++++++++++- arch/csr/Smcsrind/vsireg2.yaml | 16 +++++++++++++++- arch/csr/Smcsrind/vsireg3.yaml | 16 +++++++++++++++- arch/csr/Smcsrind/vsireg4.yaml | 16 +++++++++++++++- arch/csr/Smcsrind/vsireg5.yaml | 16 +++++++++++++++- arch/csr/Smcsrind/vsireg6.yaml | 16 +++++++++++++++- 6 files changed, 90 insertions(+), 6 deletions(-) diff --git a/arch/csr/Smcsrind/vsireg.yaml b/arch/csr/Smcsrind/vsireg.yaml index c64981f7e1..ba73b47899 100644 --- a/arch/csr/Smcsrind/vsireg.yaml +++ b/arch/csr/Smcsrind/vsireg.yaml @@ -63,5 +63,19 @@ fields: The data read from or written to the register selected by the current value of the `vsiselect` CSR. reset_value: UNDEFINED_LEGAL - + sw_write(csr_value): | + Csr handle = indirect_csr_lookup(CSR[vsiselect].VALUE, 1); + if (!handle.valid) { + unimplemented_csr($encoding); + } + if (!handle.writable) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + csr_sw_write(handle, csr_value.VALUE); + return csr_hw_read(handle); sw_read(): | + Csr handle = indirect_csr_lookup(CSR[vsiselect].VALUE, 1); + if (!handle.valid) { + unimplemented_csr($encoding); + } + return csr_sw_read(handle); diff --git a/arch/csr/Smcsrind/vsireg2.yaml b/arch/csr/Smcsrind/vsireg2.yaml index 31fad2da46..7f605d08c4 100644 --- a/arch/csr/Smcsrind/vsireg2.yaml +++ b/arch/csr/Smcsrind/vsireg2.yaml @@ -62,5 +62,19 @@ fields: text: | Data read or written based on the currently selected `vsiselect` value. reset_value: UNDEFINED_LEGAL - + sw_write(csr_value): | + Csr handle = indirect_csr_lookup(CSR[vsiselect].VALUE, 2); + if (!handle.valid) { + unimplemented_csr($encoding); + } + if (!handle.writable) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + csr_sw_write(handle, csr_value.VALUE); + return csr_hw_read(handle); sw_read(): | + Csr handle = indirect_csr_lookup(CSR[vsiselect].VALUE, 2); + if (!handle.valid) { + unimplemented_csr($encoding); + } + return csr_sw_read(handle); diff --git a/arch/csr/Smcsrind/vsireg3.yaml b/arch/csr/Smcsrind/vsireg3.yaml index 86ccb349ab..fd80cdbd25 100644 --- a/arch/csr/Smcsrind/vsireg3.yaml +++ b/arch/csr/Smcsrind/vsireg3.yaml @@ -62,5 +62,19 @@ fields: text: | The data read or written based on the currently selected `vsiselect` value. reset_value: UNDEFINED_LEGAL - + sw_write(csr_value): | + Csr handle = indirect_csr_lookup(CSR[vsiselect].VALUE, 3); + if (!handle.valid) { + unimplemented_csr($encoding); + } + if (!handle.writable) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + csr_sw_write(handle, csr_value.VALUE); + return csr_hw_read(handle); sw_read(): | + Csr handle = indirect_csr_lookup(CSR[vsiselect].VALUE, 3); + if (!handle.valid) { + unimplemented_csr($encoding); + } + return csr_sw_read(handle); diff --git a/arch/csr/Smcsrind/vsireg4.yaml b/arch/csr/Smcsrind/vsireg4.yaml index e5f8f56a8c..252a50db66 100644 --- a/arch/csr/Smcsrind/vsireg4.yaml +++ b/arch/csr/Smcsrind/vsireg4.yaml @@ -62,5 +62,19 @@ fields: text: | The data read or written based on the currently selected `vsiselect` value. reset_value: UNDEFINED_LEGAL - + sw_write(csr_value): | + Csr handle = indirect_csr_lookup(CSR[vsiselect].VALUE, 4); + if (!handle.valid) { + unimplemented_csr($encoding); + } + if (!handle.writable) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + csr_sw_write(handle, csr_value.VALUE); + return csr_hw_read(handle); sw_read(): | + Csr handle = indirect_csr_lookup(CSR[vsiselect].VALUE, 4); + if (!handle.valid) { + unimplemented_csr($encoding); + } + return csr_sw_read(handle); diff --git a/arch/csr/Smcsrind/vsireg5.yaml b/arch/csr/Smcsrind/vsireg5.yaml index bbd4b19ead..c870fece41 100644 --- a/arch/csr/Smcsrind/vsireg5.yaml +++ b/arch/csr/Smcsrind/vsireg5.yaml @@ -62,5 +62,19 @@ fields: text: | The data read or written from the register selected by the value in `vsiselect`. reset_value: UNDEFINED_LEGAL - + sw_write(csr_value): | + Csr handle = indirect_csr_lookup(CSR[vsiselect].VALUE, 5); + if (!handle.valid) { + unimplemented_csr($encoding); + } + if (!handle.writable) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + csr_sw_write(handle, csr_value.VALUE); + return csr_hw_read(handle); sw_read(): | + Csr handle = indirect_csr_lookup(CSR[vsiselect].VALUE, 5); + if (!handle.valid) { + unimplemented_csr($encoding); + } + return csr_sw_read(handle); diff --git a/arch/csr/Smcsrind/vsireg6.yaml b/arch/csr/Smcsrind/vsireg6.yaml index 0bd5b4ea75..9613a99845 100644 --- a/arch/csr/Smcsrind/vsireg6.yaml +++ b/arch/csr/Smcsrind/vsireg6.yaml @@ -62,5 +62,19 @@ fields: text: | The data read or written from the register selected by the current value of `vsiselect`. reset_value: UNDEFINED_LEGAL - + sw_write(csr_value): | + Csr handle = indirect_csr_lookup(CSR[vsiselect].VALUE, 6); + if (!handle.valid) { + unimplemented_csr($encoding); + } + if (!handle.writable) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + csr_sw_write(handle, csr_value.VALUE); + return csr_hw_read(handle); sw_read(): | + Csr handle = indirect_csr_lookup(CSR[vsiselect].VALUE, 6); + if (!handle.valid) { + unimplemented_csr($encoding); + } + return csr_sw_read(handle); From 05b85a5b5d754036f1d7029f7b43bb408649e70d Mon Sep 17 00:00:00 2001 From: syedowaisalishah Date: Mon, 5 May 2025 15:29:54 +0000 Subject: [PATCH 27/29] docs(smcsrind): update smcsrind CSR YAML files: mireg[1-6] --- arch/csr/Smcsrind/mireg.yaml | 4 ++-- arch/csr/Smcsrind/mireg2.yaml | 4 ++-- arch/csr/Smcsrind/mireg3.yaml | 4 ++-- arch/csr/Smcsrind/mireg4.yaml | 4 ++-- arch/csr/Smcsrind/mireg5.yaml | 4 ++-- arch/csr/Smcsrind/mireg6.yaml | 4 ++-- 6 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/csr/Smcsrind/mireg.yaml b/arch/csr/Smcsrind/mireg.yaml index 001a4c792b..692247778c 100644 --- a/arch/csr/Smcsrind/mireg.yaml +++ b/arch/csr/Smcsrind/mireg.yaml @@ -56,10 +56,10 @@ fields: sw_write(csr_value): | Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 1); if (!handle.valid) { - unimplemented_csr($encoding); + unimplemented_csr($encoding); } if (!handle.writable) { - raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); } csr_sw_write(handle, csr_value.VALUE); return csr_hw_read(handle); diff --git a/arch/csr/Smcsrind/mireg2.yaml b/arch/csr/Smcsrind/mireg2.yaml index 48dccc3014..9a44d5516f 100644 --- a/arch/csr/Smcsrind/mireg2.yaml +++ b/arch/csr/Smcsrind/mireg2.yaml @@ -62,10 +62,10 @@ fields: sw_write(csr_value): | Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 2); if (!handle.valid) { - unimplemented_csr($encoding); + unimplemented_csr($encoding); } if (!handle.writable) { - raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); } csr_sw_write(handle, csr_value.VALUE); return csr_hw_read(handle); diff --git a/arch/csr/Smcsrind/mireg3.yaml b/arch/csr/Smcsrind/mireg3.yaml index 8e6854ec90..dc0caf73b7 100644 --- a/arch/csr/Smcsrind/mireg3.yaml +++ b/arch/csr/Smcsrind/mireg3.yaml @@ -62,10 +62,10 @@ fields: sw_write(csr_value): | Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 3); if (!handle.valid) { - unimplemented_csr($encoding); + unimplemented_csr($encoding); } if (!handle.writable) { - raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); } csr_sw_write(handle, csr_value.VALUE); return csr_hw_read(handle); diff --git a/arch/csr/Smcsrind/mireg4.yaml b/arch/csr/Smcsrind/mireg4.yaml index ed1b6dbed7..1065dea5a9 100644 --- a/arch/csr/Smcsrind/mireg4.yaml +++ b/arch/csr/Smcsrind/mireg4.yaml @@ -62,10 +62,10 @@ fields: sw_write(csr_value): | Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 4); if (!handle.valid) { - unimplemented_csr($encoding); + unimplemented_csr($encoding); } if (!handle.writable) { - raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); } csr_sw_write(handle, csr_value.VALUE); return csr_hw_read(handle); diff --git a/arch/csr/Smcsrind/mireg5.yaml b/arch/csr/Smcsrind/mireg5.yaml index 211001f028..68971e7d89 100644 --- a/arch/csr/Smcsrind/mireg5.yaml +++ b/arch/csr/Smcsrind/mireg5.yaml @@ -62,10 +62,10 @@ fields: sw_write(csr_value): | Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 5); if (!handle.valid) { - unimplemented_csr($encoding); + unimplemented_csr($encoding); } if (!handle.writable) { - raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); } csr_sw_write(handle, csr_value.VALUE); return csr_hw_read(handle); diff --git a/arch/csr/Smcsrind/mireg6.yaml b/arch/csr/Smcsrind/mireg6.yaml index 2ca76a21b1..7a5b74e258 100644 --- a/arch/csr/Smcsrind/mireg6.yaml +++ b/arch/csr/Smcsrind/mireg6.yaml @@ -62,10 +62,10 @@ fields: sw_write(csr_value): | Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 6); if (!handle.valid) { - unimplemented_csr($encoding); + unimplemented_csr($encoding); } if (!handle.writable) { - raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); } csr_sw_write(handle, csr_value.VALUE); return csr_hw_read(handle); From 1a2225a29d2fc8bfeaa7b0d03d2b0cd5a8363de8 Mon Sep 17 00:00:00 2001 From: syedowaisalishah Date: Mon, 5 May 2025 15:31:52 +0000 Subject: [PATCH 28/29] docs(smcsrind): update smcsrind CSR YAML files: sireg[1-6] --- arch/csr/Smcsrind/sireg.yaml | 4 ++-- arch/csr/Smcsrind/sireg2.yaml | 4 ++-- arch/csr/Smcsrind/sireg3.yaml | 4 ++-- arch/csr/Smcsrind/sireg4.yaml | 4 ++-- arch/csr/Smcsrind/sireg5.yaml | 4 ++-- arch/csr/Smcsrind/sireg6.yaml | 4 ++-- 6 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/csr/Smcsrind/sireg.yaml b/arch/csr/Smcsrind/sireg.yaml index 49d6b0ff16..30e75063f8 100644 --- a/arch/csr/Smcsrind/sireg.yaml +++ b/arch/csr/Smcsrind/sireg.yaml @@ -62,10 +62,10 @@ fields: sw_write(csr_value): | Csr handle = indirect_csr_lookup(CSR[siselect].VALUE, 1); if (!handle.valid) { - unimplemented_csr($encoding); + unimplemented_csr($encoding); } if (!handle.writable) { - raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); } csr_sw_write(handle, csr_value.VALUE); return csr_hw_read(handle); diff --git a/arch/csr/Smcsrind/sireg2.yaml b/arch/csr/Smcsrind/sireg2.yaml index 86e7c1e827..7ae9e042ec 100644 --- a/arch/csr/Smcsrind/sireg2.yaml +++ b/arch/csr/Smcsrind/sireg2.yaml @@ -62,10 +62,10 @@ fields: sw_write(csr_value): | Csr handle = indirect_csr_lookup(CSR[siselect].VALUE, 2); if (!handle.valid) { - unimplemented_csr($encoding); + unimplemented_csr($encoding); } if (!handle.writable) { - raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); } csr_sw_write(handle, csr_value.VALUE); return csr_hw_read(handle); diff --git a/arch/csr/Smcsrind/sireg3.yaml b/arch/csr/Smcsrind/sireg3.yaml index 5fafd84fdb..bee9ce84bb 100644 --- a/arch/csr/Smcsrind/sireg3.yaml +++ b/arch/csr/Smcsrind/sireg3.yaml @@ -62,10 +62,10 @@ fields: sw_write(csr_value): | Csr handle = indirect_csr_lookup(CSR[siselect].VALUE, 3); if (!handle.valid) { - unimplemented_csr($encoding); + unimplemented_csr($encoding); } if (!handle.writable) { - raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); } csr_sw_write(handle, csr_value.VALUE); return csr_hw_read(handle); diff --git a/arch/csr/Smcsrind/sireg4.yaml b/arch/csr/Smcsrind/sireg4.yaml index 6dec2acd32..3dbaba4832 100644 --- a/arch/csr/Smcsrind/sireg4.yaml +++ b/arch/csr/Smcsrind/sireg4.yaml @@ -62,10 +62,10 @@ fields: sw_write(csr_value): | Csr handle = indirect_csr_lookup(CSR[siselect].VALUE, 4); if (!handle.valid) { - unimplemented_csr($encoding); + unimplemented_csr($encoding); } if (!handle.writable) { - raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); } csr_sw_write(handle, csr_value.VALUE); return csr_hw_read(handle); diff --git a/arch/csr/Smcsrind/sireg5.yaml b/arch/csr/Smcsrind/sireg5.yaml index a5c4c8759b..4a77067b6f 100644 --- a/arch/csr/Smcsrind/sireg5.yaml +++ b/arch/csr/Smcsrind/sireg5.yaml @@ -62,10 +62,10 @@ fields: sw_write(csr_value): | Csr handle = indirect_csr_lookup(CSR[siselect].VALUE, 5); if (!handle.valid) { - unimplemented_csr($encoding); + unimplemented_csr($encoding); } if (!handle.writable) { - raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); } csr_sw_write(handle, csr_value.VALUE); return csr_hw_read(handle); diff --git a/arch/csr/Smcsrind/sireg6.yaml b/arch/csr/Smcsrind/sireg6.yaml index 9265193b3d..8bf9f6678f 100644 --- a/arch/csr/Smcsrind/sireg6.yaml +++ b/arch/csr/Smcsrind/sireg6.yaml @@ -62,10 +62,10 @@ fields: sw_write(csr_value): | Csr handle = indirect_csr_lookup(CSR[siselect].VALUE, 6); if (!handle.valid) { - unimplemented_csr($encoding); + unimplemented_csr($encoding); } if (!handle.writable) { - raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); } csr_sw_write(handle, csr_value.VALUE); return csr_hw_read(handle); From d407f0ecc5bbc7aec75dcf921e0d67bd2307e871 Mon Sep 17 00:00:00 2001 From: syedowaisalishah Date: Mon, 5 May 2025 15:33:08 +0000 Subject: [PATCH 29/29] docs(smcsrind): update smcsrind CSR YAML files: vsireg[1-6] --- arch/csr/Smcsrind/vsireg.yaml | 4 ++-- arch/csr/Smcsrind/vsireg2.yaml | 4 ++-- arch/csr/Smcsrind/vsireg3.yaml | 4 ++-- arch/csr/Smcsrind/vsireg4.yaml | 4 ++-- arch/csr/Smcsrind/vsireg5.yaml | 4 ++-- arch/csr/Smcsrind/vsireg6.yaml | 4 ++-- 6 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/csr/Smcsrind/vsireg.yaml b/arch/csr/Smcsrind/vsireg.yaml index ba73b47899..099f2a94bc 100644 --- a/arch/csr/Smcsrind/vsireg.yaml +++ b/arch/csr/Smcsrind/vsireg.yaml @@ -66,10 +66,10 @@ fields: sw_write(csr_value): | Csr handle = indirect_csr_lookup(CSR[vsiselect].VALUE, 1); if (!handle.valid) { - unimplemented_csr($encoding); + unimplemented_csr($encoding); } if (!handle.writable) { - raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); } csr_sw_write(handle, csr_value.VALUE); return csr_hw_read(handle); diff --git a/arch/csr/Smcsrind/vsireg2.yaml b/arch/csr/Smcsrind/vsireg2.yaml index 7f605d08c4..1bc93a1e88 100644 --- a/arch/csr/Smcsrind/vsireg2.yaml +++ b/arch/csr/Smcsrind/vsireg2.yaml @@ -65,10 +65,10 @@ fields: sw_write(csr_value): | Csr handle = indirect_csr_lookup(CSR[vsiselect].VALUE, 2); if (!handle.valid) { - unimplemented_csr($encoding); + unimplemented_csr($encoding); } if (!handle.writable) { - raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); } csr_sw_write(handle, csr_value.VALUE); return csr_hw_read(handle); diff --git a/arch/csr/Smcsrind/vsireg3.yaml b/arch/csr/Smcsrind/vsireg3.yaml index fd80cdbd25..141bd9d76c 100644 --- a/arch/csr/Smcsrind/vsireg3.yaml +++ b/arch/csr/Smcsrind/vsireg3.yaml @@ -65,10 +65,10 @@ fields: sw_write(csr_value): | Csr handle = indirect_csr_lookup(CSR[vsiselect].VALUE, 3); if (!handle.valid) { - unimplemented_csr($encoding); + unimplemented_csr($encoding); } if (!handle.writable) { - raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); } csr_sw_write(handle, csr_value.VALUE); return csr_hw_read(handle); diff --git a/arch/csr/Smcsrind/vsireg4.yaml b/arch/csr/Smcsrind/vsireg4.yaml index 252a50db66..95f8e60985 100644 --- a/arch/csr/Smcsrind/vsireg4.yaml +++ b/arch/csr/Smcsrind/vsireg4.yaml @@ -65,10 +65,10 @@ fields: sw_write(csr_value): | Csr handle = indirect_csr_lookup(CSR[vsiselect].VALUE, 4); if (!handle.valid) { - unimplemented_csr($encoding); + unimplemented_csr($encoding); } if (!handle.writable) { - raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); } csr_sw_write(handle, csr_value.VALUE); return csr_hw_read(handle); diff --git a/arch/csr/Smcsrind/vsireg5.yaml b/arch/csr/Smcsrind/vsireg5.yaml index c870fece41..224388afcc 100644 --- a/arch/csr/Smcsrind/vsireg5.yaml +++ b/arch/csr/Smcsrind/vsireg5.yaml @@ -65,10 +65,10 @@ fields: sw_write(csr_value): | Csr handle = indirect_csr_lookup(CSR[vsiselect].VALUE, 5); if (!handle.valid) { - unimplemented_csr($encoding); + unimplemented_csr($encoding); } if (!handle.writable) { - raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); } csr_sw_write(handle, csr_value.VALUE); return csr_hw_read(handle); diff --git a/arch/csr/Smcsrind/vsireg6.yaml b/arch/csr/Smcsrind/vsireg6.yaml index 9613a99845..ed4ce451cb 100644 --- a/arch/csr/Smcsrind/vsireg6.yaml +++ b/arch/csr/Smcsrind/vsireg6.yaml @@ -65,10 +65,10 @@ fields: sw_write(csr_value): | Csr handle = indirect_csr_lookup(CSR[vsiselect].VALUE, 6); if (!handle.valid) { - unimplemented_csr($encoding); + unimplemented_csr($encoding); } if (!handle.writable) { - raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); } csr_sw_write(handle, csr_value.VALUE); return csr_hw_read(handle);