Add Smcsrind and Sscsrind CSR YAML Files

arch/csr/Smcsrind/mireg.yaml

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+---
+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+$schema: csr_schema.json#
+kind: csr
+name: mireg
+long_name: Machine Indirect Register Alias 1
+address: 0x351
+priv_mode: M
+length: MXLEN
+definedBy: Smcsrind
+description: |
+  The `mireg` CSR is the primary machine-level indirect alias register used to access
+  register state as determined by the index held in `miselect`. This CSR is typically used
+  to read or write the full 32-bit or 64-bit value of the indirectly addressed register.
+
+  For 64-bit registers in RV32 systems, `mireg` is generally used to access the lower 32 bits.
+  Combined with higher-indexed aliases (e.g., `mireg4`), this provides full access to 64-bit values
+  across multiple CSRs.
+
+  If the value in `miselect` is not implemented, access is UNSPECIFIED. Implementations
+  are encouraged to raise an illegal instruction exception in such cases.
+
+fields:
+  Count:
+    location_rv32: 31-0
+    location_rv64: 63-0
+    type: RW
+    description: Indirect register data selected by `miselect` value.
+    reset_value: UNDEFINED_LEGAL
+sw_read(): |

arch/csr/Smcsrind/mireg2.yaml

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+---
+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+$schema: csr_schema.json#
+kind: csr
+name: mireg2
+long_name: Machine Indirect Register Alias 2
+address: 0x352
+priv_mode: M
+length: MXLEN
+definedBy: Smcsrind
+description: |
+  The `mireg2` CSR is an indirect alias register used for machine-level access to register state,
+  indexed via the value in `miselect`.
+
+  Like `mireg`, this CSR enables flexible access to an array of registers without allocating
+  dedicated CSR numbers for each. It may be used independently or as part of a split-access
+  scheme for larger registers in RV32.
+
+  The behavior of `mireg2` is determined by the value of `miselect`. If `miselect` holds
+  an unsupported value, the behavior is UNSPECIFIED.
+
+fields:
+  Count:
+    location_rv32: 31-0
+    location_rv64: 63-0
+    type: RW
+    description: Indirect register data selected by `miselect` value.
+    reset_value: UNDEFINED_LEGAL
+sw_read(): |

arch/csr/Smcsrind/mireg3.yaml

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+---
+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+$schema: csr_schema.json#
+kind: csr
+name: mireg3
+long_name: Machine Indirect Register Alias 3
+address: 0x353
+priv_mode: M
+length: MXLEN
+definedBy: Smcsrind
+description: |
+  The `mireg3` CSR provides an additional machine-level alias for indirect register access via
+  the `miselect` CSR. This CSR supports cases where multiple register arrays or channels need
+  to be addressed concurrently.
+
+  In RV32, `mireg3` may be used as part of an array access pattern to read or write lower
+  segments of a register, or to support separate CSR sets.
+
+  Access behavior is defined by the selected value in `miselect`. Unsupported values result in
+  UNSPECIFIED behavior and may raise an illegal instruction exception.
+
+fields:
+  Count:
+    location_rv32: 31-0
+    location_rv64: 63-0
+    type: RW
+    description: Indirect register data selected by `miselect` value.
+    reset_value: UNDEFINED_LEGAL
+sw_read(): |

arch/csr/Smcsrind/mireg4.yaml

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+---
+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+$schema: csr_schema.json#
+kind: csr
+name: mireg4
+long_name: Machine Indirect Register Alias 4
+address: 0x355
+priv_mode: M
+length: MXLEN
+definedBy: Smcsrind
+description: |
+  The `mireg4` CSR is commonly used to access the upper 32 bits of a 64-bit machine-level
+  register in RV32 systems when used alongside `mireg`, `mireg2`, or `mireg3`.
+
+  This split-access capability allows for indirect access to full 64-bit values in 32-bit environments
+  using paired CSRs. The `miselect` value determines the exact register being accessed.
+
+  If `miselect` points to an unimplemented mapping, behavior is UNSPECIFIED. It is
+  RECOMMENDED to raise an illegal instruction exception.
+
+fields:
+  Count:
+    location_rv32: 31-0
+    location_rv64: 63-0
+    type: RW
+    description: Indirect register data selected by `miselect` value.
+    reset_value: UNDEFINED_LEGAL
+sw_read(): |

arch/csr/Smcsrind/mireg5.yaml

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+---
+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+$schema: csr_schema.json#
+kind: csr
+name: mireg5
+long_name: Machine Indirect Register Alias 5
+address: 0x356
+priv_mode: M
+length: MXLEN
+definedBy: Smcsrind
+description: |
+  The `mireg5` CSR is a machine-level alias register used primarily for accessing the upper half
+  of a 64-bit register in RV32, complementing `mireg2`.
+
+  When `miselect` is configured to point to a 64-bit register, `mireg2` may provide access
+  to the lower 32 bits while `mireg5` gives access to the upper 32 bits.
+
+  Behavior is extension-defined and depends on the current `miselect` value. Illegal
+  or unsupported values yield UNSPECIFIED behavior.
+
+fields:
+  Count:
+    location_rv32: 31-0
+    location_rv64: 63-0
+    type: RW
+    description: Indirect register data selected by `miselect` value.
+    reset_value: UNDEFINED_LEGAL
+sw_read(): |

arch/csr/Smcsrind/mireg6.yaml

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+---
+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+$schema: csr_schema.json#
+kind: csr
+name: mireg6
+long_name: Machine Indirect Register Alias 6
+address: 0x357
+priv_mode: M
+length: MXLEN
+definedBy: Smcsrind
+description: |
+  The `mireg6` CSR offers the final alias in the machine-level indirect access set, and is typically
+  used for the upper half of a 64-bit register accessed via `mireg3` in RV32 environments.
+
+  This CSR expands support for multiple register arrays, enabling extensions to define complex
+  or high-bandwidth access patterns using a compact set of CSRs.
+
+  When `miselect` holds a value not allocated or implemented by an extension, access is
+  UNSPECIFIED and may raise an exception.
+
+fields:
+  Count:
+    location_rv32: 31-0
+    location_rv64: 63-0
+    type: RW
+    description: Indirect register data selected by `miselect` value.
+    reset_value: UNDEFINED_LEGAL
+sw_read(): |

arch/csr/Smcsrind/miselect.yaml

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+---
+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+$schema: csr_schema.json#
+kind: csr
+name: miselect
+long_name: Machine Indirect Register Select
+address: 0x350
+priv_mode: M
+length: MXLEN
+definedBy: Smcsrind
+description: |
+  The `miselect` CSR is a WARL (Write-Any Read-Legal) register that selects which
+  indirect register is accessed via the `mireg*` alias CSRs. The value in `miselect`
+  acts as an index into a space of indirectly addressable machine-level registers.
+
+  Values of `miselect` are allocated by extensions implementing indirect register access.
+  The most-significant bit (bit MXLEN-1) is reserved for custom use and must be used
+  only with implementation-specific extensions. Values with this bit clear are reserved
+  for standard use.
+
+  The indirect access mechanism enabled by `miselect` reduces the need for allocating
+  large contiguous CSR address ranges by supporting register arrays accessed by index.
+
+  If `miselect` holds an unsupported value, accesses to the corresponding `mireg*`
+  alias CSR are UNSPECIFIED. Implementations are encouraged to raise an illegal instruction
+  exception to support robust error handling and software emulation.
+
+fields:
+  Select Value:
+    location_rv32: 31-0
+    location_rv64: 63-0
+    type: RW
+    description: Selects which indirect register is accessed via `mireg*`.
+    reset_value: UNDEFINED_LEGAL
+sw_read(): |

arch/csr/Smcsrind/sireg.yaml

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+---
+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+$schema: csr_schema.json#
+kind: csr
+name: sireg
+long_name: Supervisor Indirect Register Alias
+address: 0x151
+priv_mode: S
+length: SXLEN
+definedBy: Sscsrind
+description: |
+  The `sireg` CSR is a supervisor-level alias register used to access register state
+  indirectly based on the value held in the `siselect` CSR. The `sireg` CSR provides
+  access to a window of indirectly addressed registers.
+
+  The behavior of accesses to `sireg` is determined by the currently selected
+  `siselect` value, which acts as an index into an alias space defined by the extension
+  utilizing this access method. This indirect mechanism allows software to access
+  an array of CSRs without consuming large contiguous blocks of the CSR address space.
+
+  When `siselect` contains a value that is not supported, access to `sireg` is UNSPECIFIED,
+  and implementations are encouraged to raise an illegal instruction exception to aid in
+  debugging or software emulation.
+
+  The indirect access mechanism is useful for CSR arrays, such as counters or
+  performance registers, and ensures a scalable way to interact with dynamically
+  indexed register sets.
+
+fields:
+  Data:
+    location_rv32: 31-0
+    location_rv64: 63-0
+    type: RW
+    description: |
+      The data read from or written to the register selected by the current `siselect` value.
+    reset_value: UNDEFINED_LEGAL
+sw_read(): |

arch/csr/Smcsrind/sireg2.yaml

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+---
+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+$schema: csr_schema.json#
+kind: csr
+name: sireg2
+long_name: Supervisor Indirect Register Alias 2
+address: 0x152
+priv_mode: S
+length: SXLEN
+definedBy: Sscsrind
+description: |
+  The `sireg2` CSR is a supervisor-level alias register used to access register state
+  indirectly based on the value held in the `siselect` CSR. The `sireg2` CSR provides
+  access to a window of indirectly addressed registers.
+
+  The behavior of accesses to `sireg2` is determined by the currently selected
+  `siselect` value, which acts as an index into an alias space defined by the extension
+  utilizing this access method. This indirect mechanism allows software to access
+  an array of CSRs without consuming large contiguous blocks of the CSR address space.
+
+  When `siselect` contains a value that is not supported, access to `sireg2` is UNSPECIFIED,
+  and implementations are encouraged to raise an illegal instruction exception to aid in
+  debugging or software emulation.
+
+  The indirect access mechanism is useful for CSR arrays, such as counters or
+  performance registers, and ensures a scalable way to interact with dynamically
+  indexed register sets.
+
+fields:
+  Data:
+    location_rv32: 31-0
+    location_rv64: 63-0
+    type: RW
+    description: |
+      The data read from or written to the register selected by the current `siselect` value.
+    reset_value: UNDEFINED_LEGAL
+sw_read(): |

arch/csr/Smcsrind/sireg3.yaml

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+---
+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+$schema: csr_schema.json#
+kind: csr
+name: sireg3
+long_name: Supervisor Indirect Register Alias 3
+address: 0x153
+priv_mode: S
+length: SXLEN
+definedBy: Sscsrind
+description: |
+  The `sireg3` CSR is a supervisor-level alias register used to access register state
+  indirectly based on the value held in the `siselect` CSR. The `sireg3` CSR provides
+  access to a window of indirectly addressed registers.
+
+  The behavior of accesses to `sireg3` is determined by the currently selected
+  `siselect` value, which acts as an index into an alias space defined by the extension
+  utilizing this access method. This indirect mechanism allows software to access
+  an array of CSRs without consuming large contiguous blocks of the CSR address space.
+
+  When `siselect` contains a value that is not supported, access to `sireg3` is UNSPECIFIED,
+  and implementations are encouraged to raise an illegal instruction exception to aid in
+  debugging or software emulation.
+
+  The indirect access mechanism is useful for CSR arrays, such as counters or
+  performance registers, and ensures a scalable way to interact with dynamically
+  indexed register sets.
+
+fields:
+  Data:
+    location_rv32: 31-0
+    location_rv64: 63-0
+    type: RW
+    description: |
+      The data read from or written to the register selected by the current `siselect` value.
+    reset_value: UNDEFINED_LEGAL
+sw_read(): |

arch/csr/Smcsrind/sireg4.yaml

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+---
+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+$schema: csr_schema.json#
+kind: csr
+name: sireg4
+long_name: Supervisor Indirect Register Alias 4
+address: 0x155
+priv_mode: S
+length: SXLEN
+definedBy: Sscsrind
+description: |
+  The `sireg4` CSR is a supervisor-level alias register used to access register state
+  indirectly based on the value held in the `siselect` CSR. The `sireg4` CSR provides
+  access to a window of indirectly addressed registers.
+
+  The behavior of accesses to `sireg4` is determined by the currently selected
+  `siselect` value, which acts as an index into an alias space defined by the extension
+  utilizing this access method. This indirect mechanism allows software to access
+  an array of CSRs without consuming large contiguous blocks of the CSR address space.
+
+  When `siselect` contains a value that is not supported, access to `sireg4` is UNSPECIFIED,
+  and implementations are encouraged to raise an illegal instruction exception to aid in
+  debugging or software emulation.
+
+  The indirect access mechanism is useful for CSR arrays, such as counters or
+  performance registers, and ensures a scalable way to interact with dynamically
+  indexed register sets.
+
+fields:
+  Data:
+    location_rv32: 31-0
+    location_rv64: 63-0
+    type: RW
+    description: |
+      The data read from or written to the register selected by the current `siselect` value.
+    reset_value: UNDEFINED_LEGAL
+sw_read(): |