From bb6a2f846fcea07fbb220d2a44e01c0764368509 Mon Sep 17 00:00:00 2001 From: Derek Hower Date: Fri, 4 Apr 2025 10:41:53 -0700 Subject: [PATCH 01/15] test(idl): test:idl task takes config from enviornment This lets us test idl for any config from the command line: ./do test:idl qc_iu --- Rakefile | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/Rakefile b/Rakefile index ccda666883..d4a873a887 100755 --- a/Rakefile +++ b/Rakefile @@ -238,18 +238,15 @@ namespace :test do puts "All files validate against their schema" end - task idl: ["#{$root}/.stamps/resolve-rv32.stamp", "#{$root}/.stamps/resolve-rv64.stamp"] do - print "Parsing IDL code for RV32..." - cfg_arch32 = cfg_arch_for("rv32") - puts "done" - - cfg_arch32.type_check + task :idl do + cfg = ENV["CFG"] + raise "Missing CFG enviornment variable" if cfg.nil? - print "Parsing IDL code for RV64..." - cfg_arch64 = cfg_arch_for("rv64") + print "Parsing IDL code for #{cfg}..." + cfg_arch = cfg_arch_for(cfg) puts "done" - cfg_arch64.type_check + cfg_arch.type_check puts "All IDL passed type checking" end @@ -410,6 +407,11 @@ namespace :test do Rake::Task["test:idl_compiler"].invoke Rake::Task["test:lib"].invoke Rake::Task["test:schema"].invoke + ENV["CFG"] = "rv32" + Rake::Task["test:idl"].invoke + ENV["CFG"] = "rv64" + Rake::Task["test:idl"].invoke + ENV["CFG"] = "qc_iu" Rake::Task["test:idl"].invoke Rake::Task["test:inst_encodings"].invoke end From f8a7b59e7e24b572b8b6c64c861553169b00e6d8 Mon Sep 17 00:00:00 2001 From: Derek Hower Date: Fri, 4 Apr 2025 10:44:27 -0700 Subject: [PATCH 02/15] idl: add indirect csr access; do direct csr access with functions This does three things: * Remove `CSR[expression]` syntax for direct CSR reads ** `CSR[csr_name]` still works * Adds `direct_csr_lookup`/`csr_{hw,sw}_{read,write}` functions to access a CSR with a direct address * Adds `indirect_csr_lookup` to access an indirect CSR with an indirect address --- arch/csr/Zihpm/hpmcounter10h.yaml | 1 - arch/csr/Zihpm/hpmcounter11h.yaml | 1 - arch/csr/Zihpm/hpmcounter12h.yaml | 1 - arch/csr/Zihpm/hpmcounter13h.yaml | 1 - arch/csr/Zihpm/hpmcounter14h.yaml | 1 - arch/csr/Zihpm/hpmcounter15h.yaml | 1 - arch/csr/Zihpm/hpmcounter16h.yaml | 1 - arch/csr/Zihpm/hpmcounter17h.yaml | 1 - arch/csr/Zihpm/hpmcounter18h.yaml | 1 - arch/csr/Zihpm/hpmcounter19h.yaml | 1 - arch/csr/Zihpm/hpmcounter20h.yaml | 1 - arch/csr/Zihpm/hpmcounter21h.yaml | 1 - arch/csr/Zihpm/hpmcounter22h.yaml | 1 - arch/csr/Zihpm/hpmcounter23h.yaml | 1 - arch/csr/Zihpm/hpmcounter24h.yaml | 1 - arch/csr/Zihpm/hpmcounter25h.yaml | 1 - arch/csr/Zihpm/hpmcounter26h.yaml | 1 - arch/csr/Zihpm/hpmcounter27h.yaml | 1 - arch/csr/Zihpm/hpmcounter28h.yaml | 1 - arch/csr/Zihpm/hpmcounter29h.yaml | 1 - arch/csr/Zihpm/hpmcounter30h.yaml | 1 - arch/csr/Zihpm/hpmcounter31h.yaml | 1 - arch/csr/Zihpm/hpmcounter3h.yaml | 1 - arch/csr/Zihpm/hpmcounter4h.yaml | 1 - arch/csr/Zihpm/hpmcounter5h.yaml | 1 - arch/csr/Zihpm/hpmcounter6h.yaml | 1 - arch/csr/Zihpm/hpmcounter7h.yaml | 1 - arch/csr/Zihpm/hpmcounter8h.yaml | 1 - arch/csr/Zihpm/hpmcounter9h.yaml | 1 - arch/inst/Zicsr/csrrc.yaml | 16 +- arch/inst/Zicsr/csrrci.yaml | 18 ++- arch/inst/Zicsr/csrrs.yaml | 16 +- arch/inst/Zicsr/csrrsi.yaml | 16 +- arch/inst/Zicsr/csrrw.yaml | 15 +- arch/inst/Zicsr/csrrwi.yaml | 15 +- arch/isa/builtin_functions.idl | 69 +++++++++ arch/isa/globals.isa | 140 +++++++----------- arch_overlay/qc_iu/inst/Xqci/qc.c.clrint.yaml | 4 +- arch_overlay/qc_iu/inst/Xqci/qc.c.setint.yaml | 4 +- arch_overlay/qc_iu/inst/Xqci/qc.clrinti.yaml | 4 +- arch_overlay/qc_iu/inst/Xqci/qc.csrrwr.yaml | 7 +- arch_overlay/qc_iu/inst/Xqci/qc.csrrwri.yaml | 10 +- arch_overlay/qc_iu/inst/Xqci/qc.setinti.yaml | 4 +- backends/cpp_hart_gen/cpp/include/udb/csr.hpp | 6 + backends/cpp_hart_gen/lib/gen_cpp.rb | 11 +- backends/cpp_hart_gen/templates/csrs.hxx.erb | 2 + backends/cpp_hart_gen/templates/hart.hxx.erb | 71 +++++++++ .../cpp_hart_gen/templates/hart_impl.hxx.erb | 3 + lib/arch_obj_models/csr.rb | 4 + lib/arch_obj_models/instruction.rb | 4 +- lib/cfg_arch.rb | 13 +- lib/idl/ast.rb | 102 +++++-------- lib/idl/idl.treetop | 4 +- lib/idl/passes/gen_adoc.rb | 18 +-- lib/idl/symbol_table.rb | 1 + lib/idl/type.rb | 7 +- 56 files changed, 363 insertions(+), 250 deletions(-) diff --git a/arch/csr/Zihpm/hpmcounter10h.yaml b/arch/csr/Zihpm/hpmcounter10h.yaml index 81f80156af..b903ef0217 100644 --- a/arch/csr/Zihpm/hpmcounter10h.yaml +++ b/arch/csr/Zihpm/hpmcounter10h.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter10h long_name: User-mode Hardware Performance Counter 7, high half address: 0xC8A -base: 32 description: | Alias for M-mode CSR `mhpmcounter10h`. diff --git a/arch/csr/Zihpm/hpmcounter11h.yaml b/arch/csr/Zihpm/hpmcounter11h.yaml index 5eefd08e03..24c3187660 100644 --- a/arch/csr/Zihpm/hpmcounter11h.yaml +++ b/arch/csr/Zihpm/hpmcounter11h.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter11h long_name: User-mode Hardware Performance Counter 8, high half address: 0xC8B -base: 32 description: | Alias for M-mode CSR `mhpmcounter11h`. diff --git a/arch/csr/Zihpm/hpmcounter12h.yaml b/arch/csr/Zihpm/hpmcounter12h.yaml index 9007c8f506..c0c468c19d 100644 --- a/arch/csr/Zihpm/hpmcounter12h.yaml +++ b/arch/csr/Zihpm/hpmcounter12h.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter12h long_name: User-mode Hardware Performance Counter 9, high half address: 0xC8C -base: 32 description: | Alias for M-mode CSR `mhpmcounter12h`. diff --git a/arch/csr/Zihpm/hpmcounter13h.yaml b/arch/csr/Zihpm/hpmcounter13h.yaml index fb684749df..cd055f9404 100644 --- a/arch/csr/Zihpm/hpmcounter13h.yaml +++ b/arch/csr/Zihpm/hpmcounter13h.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter13h long_name: User-mode Hardware Performance Counter 10, high half address: 0xC8D -base: 32 description: | Alias for M-mode CSR `mhpmcounter13h`. diff --git a/arch/csr/Zihpm/hpmcounter14h.yaml b/arch/csr/Zihpm/hpmcounter14h.yaml index 9e38f55a14..1a4290b354 100644 --- a/arch/csr/Zihpm/hpmcounter14h.yaml +++ b/arch/csr/Zihpm/hpmcounter14h.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter14h long_name: User-mode Hardware Performance Counter 11, high half address: 0xC8E -base: 32 description: | Alias for M-mode CSR `mhpmcounter14h`. diff --git a/arch/csr/Zihpm/hpmcounter15h.yaml b/arch/csr/Zihpm/hpmcounter15h.yaml index 745a8d284e..8f7a0fb94e 100644 --- a/arch/csr/Zihpm/hpmcounter15h.yaml +++ b/arch/csr/Zihpm/hpmcounter15h.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter15h long_name: User-mode Hardware Performance Counter 12, high half address: 0xC8F -base: 32 description: | Alias for M-mode CSR `mhpmcounter15h`. diff --git a/arch/csr/Zihpm/hpmcounter16h.yaml b/arch/csr/Zihpm/hpmcounter16h.yaml index 39f9043123..b3d05236b9 100644 --- a/arch/csr/Zihpm/hpmcounter16h.yaml +++ b/arch/csr/Zihpm/hpmcounter16h.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter16h long_name: User-mode Hardware Performance Counter 13, high half address: 0xC90 -base: 32 description: | Alias for M-mode CSR `mhpmcounter16h`. diff --git a/arch/csr/Zihpm/hpmcounter17h.yaml b/arch/csr/Zihpm/hpmcounter17h.yaml index 6a55a4e1ec..0cd5f864e3 100644 --- a/arch/csr/Zihpm/hpmcounter17h.yaml +++ b/arch/csr/Zihpm/hpmcounter17h.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter17h long_name: User-mode Hardware Performance Counter 14, high half address: 0xC91 -base: 32 description: | Alias for M-mode CSR `mhpmcounter17h`. diff --git a/arch/csr/Zihpm/hpmcounter18h.yaml b/arch/csr/Zihpm/hpmcounter18h.yaml index 4427ba61d7..d45aa624b9 100644 --- a/arch/csr/Zihpm/hpmcounter18h.yaml +++ b/arch/csr/Zihpm/hpmcounter18h.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter18h long_name: User-mode Hardware Performance Counter 15, high half address: 0xC92 -base: 32 description: | Alias for M-mode CSR `mhpmcounter18h`. diff --git a/arch/csr/Zihpm/hpmcounter19h.yaml b/arch/csr/Zihpm/hpmcounter19h.yaml index bc4872908c..f5bff3f22d 100644 --- a/arch/csr/Zihpm/hpmcounter19h.yaml +++ b/arch/csr/Zihpm/hpmcounter19h.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter19h long_name: User-mode Hardware Performance Counter 16, high half address: 0xC93 -base: 32 description: | Alias for M-mode CSR `mhpmcounter19h`. diff --git a/arch/csr/Zihpm/hpmcounter20h.yaml b/arch/csr/Zihpm/hpmcounter20h.yaml index 6b75ff97e6..6734e2d79b 100644 --- a/arch/csr/Zihpm/hpmcounter20h.yaml +++ b/arch/csr/Zihpm/hpmcounter20h.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter20h long_name: User-mode Hardware Performance Counter 17, high half address: 0xC94 -base: 32 description: | Alias for M-mode CSR `mhpmcounter20h`. diff --git a/arch/csr/Zihpm/hpmcounter21h.yaml b/arch/csr/Zihpm/hpmcounter21h.yaml index d644bf0ca9..12012a7bca 100644 --- a/arch/csr/Zihpm/hpmcounter21h.yaml +++ b/arch/csr/Zihpm/hpmcounter21h.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter21h long_name: User-mode Hardware Performance Counter 18, high half address: 0xC95 -base: 32 description: | Alias for M-mode CSR `mhpmcounter21h`. diff --git a/arch/csr/Zihpm/hpmcounter22h.yaml b/arch/csr/Zihpm/hpmcounter22h.yaml index ab3836ad4a..994240044e 100644 --- a/arch/csr/Zihpm/hpmcounter22h.yaml +++ b/arch/csr/Zihpm/hpmcounter22h.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter22h long_name: User-mode Hardware Performance Counter 19, high half address: 0xC96 -base: 32 description: | Alias for M-mode CSR `mhpmcounter22h`. diff --git a/arch/csr/Zihpm/hpmcounter23h.yaml b/arch/csr/Zihpm/hpmcounter23h.yaml index 11c69f5e77..ecb16e6844 100644 --- a/arch/csr/Zihpm/hpmcounter23h.yaml +++ b/arch/csr/Zihpm/hpmcounter23h.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter23h long_name: User-mode Hardware Performance Counter 20, high half address: 0xC97 -base: 32 description: | Alias for M-mode CSR `mhpmcounter23h`. diff --git a/arch/csr/Zihpm/hpmcounter24h.yaml b/arch/csr/Zihpm/hpmcounter24h.yaml index d1223f183b..ffe667a456 100644 --- a/arch/csr/Zihpm/hpmcounter24h.yaml +++ b/arch/csr/Zihpm/hpmcounter24h.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter24h long_name: User-mode Hardware Performance Counter 21, high half address: 0xC98 -base: 32 description: | Alias for M-mode CSR `mhpmcounter24h`. diff --git a/arch/csr/Zihpm/hpmcounter25h.yaml b/arch/csr/Zihpm/hpmcounter25h.yaml index 891956a29d..f4b3286a4f 100644 --- a/arch/csr/Zihpm/hpmcounter25h.yaml +++ b/arch/csr/Zihpm/hpmcounter25h.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter25h long_name: User-mode Hardware Performance Counter 22, high half address: 0xC99 -base: 32 description: | Alias for M-mode CSR `mhpmcounter25h`. diff --git a/arch/csr/Zihpm/hpmcounter26h.yaml b/arch/csr/Zihpm/hpmcounter26h.yaml index 267827d2ac..995483b4fe 100644 --- a/arch/csr/Zihpm/hpmcounter26h.yaml +++ b/arch/csr/Zihpm/hpmcounter26h.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter26h long_name: User-mode Hardware Performance Counter 23, high half address: 0xC9A -base: 32 description: | Alias for M-mode CSR `mhpmcounter26h`. diff --git a/arch/csr/Zihpm/hpmcounter27h.yaml b/arch/csr/Zihpm/hpmcounter27h.yaml index ecc4f89d37..8e17ad1758 100644 --- a/arch/csr/Zihpm/hpmcounter27h.yaml +++ b/arch/csr/Zihpm/hpmcounter27h.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter27h long_name: User-mode Hardware Performance Counter 24, high half address: 0xC9B -base: 32 description: | Alias for M-mode CSR `mhpmcounter27h`. diff --git a/arch/csr/Zihpm/hpmcounter28h.yaml b/arch/csr/Zihpm/hpmcounter28h.yaml index ee3b013e17..9a1e7714f3 100644 --- a/arch/csr/Zihpm/hpmcounter28h.yaml +++ b/arch/csr/Zihpm/hpmcounter28h.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter28h long_name: User-mode Hardware Performance Counter 25, high half address: 0xC9C -base: 32 description: | Alias for M-mode CSR `mhpmcounter28h`. diff --git a/arch/csr/Zihpm/hpmcounter29h.yaml b/arch/csr/Zihpm/hpmcounter29h.yaml index f903b631f4..e3fd8e6a2f 100644 --- a/arch/csr/Zihpm/hpmcounter29h.yaml +++ b/arch/csr/Zihpm/hpmcounter29h.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter29h long_name: User-mode Hardware Performance Counter 26, high half address: 0xC9D -base: 32 description: | Alias for M-mode CSR `mhpmcounter29h`. diff --git a/arch/csr/Zihpm/hpmcounter30h.yaml b/arch/csr/Zihpm/hpmcounter30h.yaml index 4c370ead95..08bc8149a7 100644 --- a/arch/csr/Zihpm/hpmcounter30h.yaml +++ b/arch/csr/Zihpm/hpmcounter30h.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter30h long_name: User-mode Hardware Performance Counter 27, high half address: 0xC9E -base: 32 description: | Alias for M-mode CSR `mhpmcounter30h`. diff --git a/arch/csr/Zihpm/hpmcounter31h.yaml b/arch/csr/Zihpm/hpmcounter31h.yaml index 397143b275..02f8f77b23 100644 --- a/arch/csr/Zihpm/hpmcounter31h.yaml +++ b/arch/csr/Zihpm/hpmcounter31h.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter31h long_name: User-mode Hardware Performance Counter 28, high half address: 0xC9F -base: 32 description: | Alias for M-mode CSR `mhpmcounter31h`. diff --git a/arch/csr/Zihpm/hpmcounter3h.yaml b/arch/csr/Zihpm/hpmcounter3h.yaml index 6eb41a9e0f..2c49c0fe4c 100644 --- a/arch/csr/Zihpm/hpmcounter3h.yaml +++ b/arch/csr/Zihpm/hpmcounter3h.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter3h long_name: User-mode Hardware Performance Counter 0, high half address: 0xC83 -base: 32 description: | Alias for M-mode CSR `mhpmcounter3h`. diff --git a/arch/csr/Zihpm/hpmcounter4h.yaml b/arch/csr/Zihpm/hpmcounter4h.yaml index 9faab3c5c0..ac6a575ccc 100644 --- a/arch/csr/Zihpm/hpmcounter4h.yaml +++ b/arch/csr/Zihpm/hpmcounter4h.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter4h long_name: User-mode Hardware Performance Counter 1, high half address: 0xC84 -base: 32 description: | Alias for M-mode CSR `mhpmcounter4h`. diff --git a/arch/csr/Zihpm/hpmcounter5h.yaml b/arch/csr/Zihpm/hpmcounter5h.yaml index 662458fdab..1529a2f8a2 100644 --- a/arch/csr/Zihpm/hpmcounter5h.yaml +++ b/arch/csr/Zihpm/hpmcounter5h.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter5h long_name: User-mode Hardware Performance Counter 2, high half address: 0xC85 -base: 32 description: | Alias for M-mode CSR `mhpmcounter5h`. diff --git a/arch/csr/Zihpm/hpmcounter6h.yaml b/arch/csr/Zihpm/hpmcounter6h.yaml index e481365550..9995fc0eee 100644 --- a/arch/csr/Zihpm/hpmcounter6h.yaml +++ b/arch/csr/Zihpm/hpmcounter6h.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter6h long_name: User-mode Hardware Performance Counter 3, high half address: 0xC86 -base: 32 description: | Alias for M-mode CSR `mhpmcounter6h`. diff --git a/arch/csr/Zihpm/hpmcounter7h.yaml b/arch/csr/Zihpm/hpmcounter7h.yaml index 4b1e69a34d..416f912193 100644 --- a/arch/csr/Zihpm/hpmcounter7h.yaml +++ b/arch/csr/Zihpm/hpmcounter7h.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter7h long_name: User-mode Hardware Performance Counter 4, high half address: 0xC87 -base: 32 description: | Alias for M-mode CSR `mhpmcounter7h`. diff --git a/arch/csr/Zihpm/hpmcounter8h.yaml b/arch/csr/Zihpm/hpmcounter8h.yaml index a71d48687a..11a341b4bb 100644 --- a/arch/csr/Zihpm/hpmcounter8h.yaml +++ b/arch/csr/Zihpm/hpmcounter8h.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter8h long_name: User-mode Hardware Performance Counter 5, high half address: 0xC88 -base: 32 description: | Alias for M-mode CSR `mhpmcounter8h`. diff --git a/arch/csr/Zihpm/hpmcounter9h.yaml b/arch/csr/Zihpm/hpmcounter9h.yaml index 9a751b36c8..f3fcfdc25b 100644 --- a/arch/csr/Zihpm/hpmcounter9h.yaml +++ b/arch/csr/Zihpm/hpmcounter9h.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter9h long_name: User-mode Hardware Performance Counter 6, high half address: 0xC89 -base: 32 description: | Alias for M-mode CSR `mhpmcounter9h`. diff --git a/arch/inst/Zicsr/csrrc.yaml b/arch/inst/Zicsr/csrrc.yaml index 3ab6aaf2b3..8606d5648f 100644 --- a/arch/inst/Zicsr/csrrc.yaml +++ b/arch/inst/Zicsr/csrrc.yaml @@ -24,16 +24,26 @@ access: vu: always data_independent_timing: false operation(): | + Csr csr_handle = direct_csr_lookup(csr); + Boolean will_write = xs1 != 0; - check_csr(csr, will_write, $encoding); - XReg initial_csr_value = CSR[csr].sw_read(); + # permission checks + if (csr_handle.valid == false) { + unimplemented_csr($encoding); + } else if (!compatible_mode?(csr_handle.mode, mode())) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } else if (will_write && csr_handle.writable == false) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg initial_csr_value = csr_sw_read(csr_handle); if (xs1 != 0) { # clear bits using the mask # performing any WARL transformations first XReg mask = X[xs1]; - CSR[csr].sw_write(initial_csr_value & ~mask); + csr_sw_write(csr_handle, initial_csr_value & ~mask); } X[xd] = initial_csr_value; diff --git a/arch/inst/Zicsr/csrrci.yaml b/arch/inst/Zicsr/csrrci.yaml index d45728539c..2917e9cc6e 100644 --- a/arch/inst/Zicsr/csrrci.yaml +++ b/arch/inst/Zicsr/csrrci.yaml @@ -25,15 +25,25 @@ access: data_independent_timing: false operation(): | Boolean will_write = uimm != 0; - check_csr(csr, will_write, $encoding); - XReg initial_csr_value = CSR[csr].sw_read(); + Csr csr_handle = direct_csr_lookup(csr); - if (uimm != 0) { + # permission checks + if (csr_handle.valid == false) { + unimplemented_csr($encoding); + } else if (!compatible_mode?(csr_handle.mode, mode())) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } else if (will_write && csr_handle.writable == false) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg initial_csr_value = csr_sw_read(csr_handle); + + if (will_write) { # set bits using the mask # performing any WARL transformations first XReg mask = uimm; - CSR[csr].sw_write(initial_csr_value & ~mask); + csr_sw_write(csr_handle, initial_csr_value & ~mask); } X[xd] = initial_csr_value; diff --git a/arch/inst/Zicsr/csrrs.yaml b/arch/inst/Zicsr/csrrs.yaml index e5171f141e..9919ca5caf 100644 --- a/arch/inst/Zicsr/csrrs.yaml +++ b/arch/inst/Zicsr/csrrs.yaml @@ -31,15 +31,25 @@ access: vu: always operation(): | Boolean will_write = rs1 != 0; - check_csr(csr, will_write, $encoding); - XReg initial_csr_value = CSR[csr].sw_read(); + Csr csr_handle = direct_csr_lookup(csr); + + # permission checks + if (csr_handle.valid == false) { + unimplemented_csr($encoding); + } else if (!compatible_mode?(csr_handle.mode, mode())) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } else if (will_write && csr_handle.writable == false) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg initial_csr_value = csr_sw_read(csr_handle); if (will_write) { # set bits using the mask # performing any WARL transformations first XReg mask = X[rs1]; - CSR[csr].sw_write(initial_csr_value | mask); + csr_sw_write(csr_handle, initial_csr_value | mask); } X[rd] = initial_csr_value; diff --git a/arch/inst/Zicsr/csrrsi.yaml b/arch/inst/Zicsr/csrrsi.yaml index 5543777132..e175c9398f 100644 --- a/arch/inst/Zicsr/csrrsi.yaml +++ b/arch/inst/Zicsr/csrrsi.yaml @@ -25,15 +25,25 @@ access: data_independent_timing: false operation(): | Boolean will_write = uimm != 0; - check_csr(csr, will_write, $encoding); - XReg initial_csr_value = CSR[csr].sw_read(); + Csr csr_handle = direct_csr_lookup(csr); + + # permission checks + if (csr_handle.valid == false) { + unimplemented_csr($encoding); + } else if (!compatible_mode?(csr_handle.mode, mode())) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } else if (will_write && csr_handle.writable == false) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg initial_csr_value = csr_sw_read(csr_handle); if (will_write) { # set bits using the mask # performing any WARL transformations first XReg mask = uimm; - CSR[csr].sw_write(initial_csr_value | mask); + csr_sw_write(csr_handle, initial_csr_value | mask); } X[xd] = initial_csr_value; diff --git a/arch/inst/Zicsr/csrrw.yaml b/arch/inst/Zicsr/csrrw.yaml index c379a802a8..0ddf85fc9c 100644 --- a/arch/inst/Zicsr/csrrw.yaml +++ b/arch/inst/Zicsr/csrrw.yaml @@ -29,17 +29,26 @@ access: vs: always vu: always operation(): | - check_csr(csr, true, $encoding); + Csr csr_handle = direct_csr_lookup(csr); Bits initial_value = X[xs1]; + # permission checks + if (csr_handle.valid == false) { + unimplemented_csr($encoding); + } else if (!compatible_mode?(csr_handle.mode, mode())) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } else if (csr_handle.writable == false) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + if (xd != 0) { - X[xd] = CSR[csr].sw_read(); + X[xd] = csr_sw_read(csr_handle); } # writes the value in X[xs1] to the CSR, # performing any WARL transformations first - CSR[csr].sw_write(initial_value); + csr_sw_write(csr_handle, initial_value); # SPDX-SnippetBegin # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model diff --git a/arch/inst/Zicsr/csrrwi.yaml b/arch/inst/Zicsr/csrrwi.yaml index f3290fd3c0..dca3605e55 100644 --- a/arch/inst/Zicsr/csrrwi.yaml +++ b/arch/inst/Zicsr/csrrwi.yaml @@ -29,15 +29,24 @@ access: vs: always vu: always operation(): | - check_csr(csr, true, $encoding); + Csr csr_handle = direct_csr_lookup(csr); + + # permission checks + if (csr_handle.valid == false) { + unimplemented_csr($encoding); + } else if (!compatible_mode?(csr_handle.mode, mode())) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } else if (csr_handle.writable == false) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } if (rd != 0) { - X[rd] = CSR[csr].sw_read(); + X[rd] = csr_sw_read(csr_handle); } # writes the zero-extended immediate to the CSR, # performing any WARL transformations first - CSR[csr].sw_write({{XLEN-5{1'b0}}, imm}); + csr_sw_write(csr_handle, {{XLEN-5{1'b0}}, imm}); # SPDX-SnippetBegin # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model diff --git a/arch/isa/builtin_functions.idl b/arch/isa/builtin_functions.idl index 6a11479338..aee4dc2fe7 100644 --- a/arch/isa/builtin_functions.idl +++ b/arch/isa/builtin_functions.idl @@ -24,6 +24,75 @@ generated function implemented_csr? { } } +enum CsrAddressType { + Direct # accessible with csrrw, etc. + Indirect # only accessible with csrind +} + +struct Csr { + Boolean valid; + String name; + CsrAddressType addr_type; + Bits<64> address; + PrivilegeMode mode; + Boolean writable; +} + +# implementation is generated from CSR YAML defintions +generated function direct_csr_lookup { + returns Csr + arguments + Bits<12> csr_addr + description { + Return CSR info for a CSR with direct address +csr_addr+. + + If no CSR exists, .valid == false + } +} + +# implementation is generated from CSR YAML defintions +generated function indirect_csr_lookup { + returns Csr + arguments + Bits csr_addr + description { + Return CSR info for a CSR with indirect address +csr_addr+. + + If no CSR exists, .valid == false + } +} + +generated function csr_hw_read { + returns Bits<64> # even in rv32, there are 64-bit CSRs + arguments + Csr csr + description { + Returns the raw value of csr + } +} + +# implementation is generated from CSR YAML defintions +generated function csr_sw_read { + returns Bits<64> # even in rv32, there are 64-bit CSRs + arguments + Csr csr + description { + Returns the result of CSR[csr].sw_read(); i.e., the software view of the register + } +} + +# implementation is generated from CSR YAML defintions +generated function csr_sw_write { + arguments + Csr csr, + Bits value + description { + Writes +value+ to +csr+, applying an WARL transformations first. + + Uses the sw_write(...) functions of CSR field definitions. + } +} + builtin function unpredictable { arguments String why description { diff --git a/arch/isa/globals.isa b/arch/isa/globals.isa index c208dedec7..66dd9a0375 100644 --- a/arch/isa/globals.isa +++ b/arch/isa/globals.isa @@ -267,6 +267,41 @@ function set_mode { } } +function compatible_mode? { + returns Boolean + arguments + PrivilegeMode target_mode, + PrivilegeMode actual_mode + description { + Returns true if +target_mode+ is more privileged than +actual_mode+. + } + body { + if (target_mode == PrivilegeMode::M) { + return actual_mode == PrivilegeMode::M; + } else if (target_mode == PrivilegeMode::S) { + return + (actual_mode == PrivilegeMode::M) || + (actual_mode == PrivilegeMode::S); + } else if (target_mode == PrivilegeMode::U) { + return + (actual_mode == PrivilegeMode::M) || + (actual_mode == PrivilegeMode::S) || + (actual_mode == PrivilegeMode::U); + } else if (target_mode == PrivilegeMode::VS) { + return + (actual_mode == PrivilegeMode::M) || + (actual_mode == PrivilegeMode::S) || + (actual_mode == PrivilegeMode::VS); + } else if (target_mode == PrivilegeMode::VU) { + return + (actual_mode == PrivilegeMode::M) || + (actual_mode == PrivilegeMode::S) || + (actual_mode == PrivilegeMode::VS) || + (actual_mode == PrivilegeMode::VU); + } + } +} + function exception_handling_mode { returns PrivilegeMode arguments ExceptionCode exception_code @@ -515,79 +550,6 @@ function stval_for { } } -function csr? { - returns Boolean - arguments Bits<12> csr_addr - description { - Returns true if csr_addr is an implemented csr, and the defining extension is not disabled - } - body { - if (!implemented_csr?(csr_addr)) { - return false; - } - - if (implemented?(ExtensionName::S) - && !CSR[csr_addr].implemented_without?(ExtensionName::S)) { - - return CSR[misa].S == 1'b1; - - } else if (implemented?(ExtensionName::U) - && !CSR[csr_addr].implemented_without?(ExtensionName::U)) { - - return CSR[misa].U == 1'b1; - - } else if (implemented?(ExtensionName::H) - && !CSR[csr_addr].implemented_without?(ExtensionName::H)) { - - return CSR[misa].H == 1'b1; - } - - return true; - } -} - -function check_csr { - arguments Bits<12> csr_addr, Boolean for_write, Bits encoding - description { - Checks if 'csr_addr' is a valid address, can be read in the current mode, - and, if for_write is true, can be written in the current mode. - - If the check fails, will either raise IllegalInsruction or cause - unpredictable behavior, depending on TRAP_ON_UNIMPLEMENTED_CSR - } - body { - if (!csr?(csr_addr)) { - if (TRAP_ON_UNIMPLEMENTED_CSR) { - raise(ExceptionCode::IllegalInstruction, mode(), encoding); - } else { - unpredictable("Attempt to read unimplemented CSR"); - } - } - PrivilegeMode priv_mode; - if (csr_addr[9:8] == 2'b00) { - priv_mode = PrivilegeMode::M; - } else if (csr_addr[9:8] == 2'b01 || csr_addr[9:8] == 2'b10) { - priv_mode = PrivilegeMode::S; - } else { - priv_mode = PrivilegeMode::U; - } - if (priv_mode == PrivilegeMode::M) { - if (mode() != PrivilegeMode::M) { - raise(ExceptionCode::IllegalInstruction, mode(), encoding); - } - } else if (priv_mode == PrivilegeMode::S) { - if (mode() == PrivilegeMode::U || mode() == PrivilegeMode::VU) { - raise(ExceptionCode::IllegalInstruction, mode(), encoding); - } - } - - if (for_write && csr_addr[11:10] == 2'b11) { - # write to read-only CSR - raise(ExceptionCode::IllegalInstruction, mode(), encoding); - } - } -} - function vstval_for { returns XReg arguments ExceptionCode exception_code, XReg tval @@ -1024,8 +986,13 @@ function pmp_match_64 { # get the registers for this PMP entry Bits<12> pmpcfg_idx = pmpcfg0_addr + (i/8)*2; Bits<6> shamt = (i % 8)*8; - PmpCfg cfg = ($bits(CSR[pmpcfg0_addr]) >> shamt)[7:0]; + + Csr pmpcfg_csr = direct_csr_lookup(pmpcfg_idx); + PmpCfg cfg = (csr_hw_read(pmpcfg_csr) >> shamt)[7:0]; + Bits<12> pmpaddr_idx = pmpaddr0_addr + i; + Csr pmpaddr_csr = direct_csr_lookup(pmpaddr_idx); + Bits<64> pmpaddr_csr_value = csr_sw_read(pmpaddr_csr); # set up the default range limits, which will result in NoMatch when # compared to the access @@ -1038,9 +1005,10 @@ function pmp_match_64 { range_lo = 0; } else { # otherwise, it's the address in the next lowest pmpaddr register - range_lo = ($bits(CSR[pmpaddr_idx - 1]) << 2)[PHYS_ADDR_WIDTH-1:0]; + Csr tor_pmpaddr_csr = direct_csr_lookup(pmpaddr_idx - 1); + range_lo = (csr_sw_read(tor_pmpaddr_csr) << 2)[PHYS_ADDR_WIDTH-1:0]; } - range_hi = ($bits(CSR[pmpaddr_idx]) << 2)[PHYS_ADDR_WIDTH-1:0]; + range_hi = (pmpaddr_csr_value << 2)[PHYS_ADDR_WIDTH-1:0]; } else if (cfg.A == $bits(PmpCfg_A::NAPOT)) { # Example pmpaddr: 0b00010101111 @@ -1049,14 +1017,14 @@ function pmp_match_64 { # mask: 0b00000011111 # ~mask: 0b11111100000 # len = mask + 1: 0b00000100000 - Bits pmpaddr_value = CSR[pmpaddr_idx].sw_read()[PHYS_ADDR_WIDTH-3:0]; + Bits pmpaddr_value = pmpaddr_csr_value[PHYS_ADDR_WIDTH-3:0]; Bits mask = pmpaddr_value ^ (pmpaddr_value + 1); range_lo = (pmpaddr_value & ~mask) << 2; Bits len = mask + 1; range_hi = ((pmpaddr_value & ~mask) + len) << 2; } else if (cfg.A == $bits(PmpCfg_A::NA4)) { - range_lo = ($bits(CSR[pmpaddr_idx]) << 2)[PHYS_ADDR_WIDTH-1:0]; + range_lo = (pmpaddr_csr_value << 2)[PHYS_ADDR_WIDTH-1:0]; range_hi = range_lo + 4; } @@ -1091,8 +1059,13 @@ function pmp_match_32 { # get the registers for this PMP entry Bits<12> pmpcfg_idx = pmpcfg0_addr + (i/4); Bits<6> shamt = (i % 4)*8; - PmpCfg cfg = ($bits(CSR[pmpcfg0_addr]) >> shamt)[7:0]; + + Csr pmpcfg_csr = direct_csr_lookup(pmpcfg_idx); + PmpCfg cfg = (csr_hw_read(pmpcfg_csr) >> shamt)[7:0]; + Bits<12> pmpaddr_idx = pmpaddr0_addr + i; + Csr pmpaddr_csr = direct_csr_lookup(pmpaddr_idx); + Bits<32> pmpaddr_csr_value = csr_sw_read(pmpaddr_csr); # set up the default range limits, which will result in NoMatch when # compared to the access @@ -1105,9 +1078,10 @@ function pmp_match_32 { range_lo = 0; } else { # otherwise, it's the address in the next lowest pmpaddr register - range_lo = ($bits(CSR[pmpaddr_idx - 1]) << 2)[PHYS_ADDR_WIDTH-1:0]; + Csr tor_pmpaddr_csr = direct_csr_lookup(pmpaddr_idx - 1); + range_lo = (csr_sw_read(tor_pmpaddr_csr) << 2)[PHYS_ADDR_WIDTH-1:0]; } - range_hi = ($bits(CSR[pmpaddr_idx]) << 2)[PHYS_ADDR_WIDTH-1:0]; + range_hi = (pmpaddr_csr_value << 2)[PHYS_ADDR_WIDTH-1:0]; } else if (cfg.A == $bits(PmpCfg_A::NAPOT)) { # Example pmpaddr: 0b00010101111 @@ -1116,14 +1090,14 @@ function pmp_match_32 { # mask: 0b00000011111 # ~mask: 0b11111100000 # len = mask + 1: 0b00000100000 - Bits pmpaddr_value = CSR[pmpaddr_idx].sw_read()[PHYS_ADDR_WIDTH-3:0]; + Bits pmpaddr_value = pmpaddr_csr_value[PHYS_ADDR_WIDTH-3:0]; Bits mask = pmpaddr_value ^ (pmpaddr_value + 1); range_lo = (pmpaddr_value & ~mask) << 2; Bits len = mask + 1; range_hi = ((pmpaddr_value & ~mask) + len) << 2; } else if (cfg.A == $bits(PmpCfg_A::NA4)) { - range_lo = ($bits(CSR[pmpaddr_idx]) << 2)[PHYS_ADDR_WIDTH-1:0]; + range_lo = (pmpaddr_csr_value << 2)[PHYS_ADDR_WIDTH-1:0]; range_hi = range_lo + 4; } diff --git a/arch_overlay/qc_iu/inst/Xqci/qc.c.clrint.yaml b/arch_overlay/qc_iu/inst/Xqci/qc.c.clrint.yaml index 3be38f2786..cdd1b645e4 100644 --- a/arch_overlay/qc_iu/inst/Xqci/qc.c.clrint.yaml +++ b/arch_overlay/qc_iu/inst/Xqci/qc.c.clrint.yaml @@ -29,5 +29,5 @@ operation(): | XReg idx = rs1 / 32; XReg bit = rs1 % 32; - XReg pre_csr = CSR[MCLICIP0_ADDR + idx].sw_read(); - CSR[MCLICIP0_ADDR + idx].sw_write(pre_csr & ~(1 << bit)); + Csr pre_csr = direct_csr_lookup(MCLICIP0_ADDR + idx); + csr_sw_write(pre_csr, csr_sw_read(pre_csr) & ~(1 << bit)); diff --git a/arch_overlay/qc_iu/inst/Xqci/qc.c.setint.yaml b/arch_overlay/qc_iu/inst/Xqci/qc.c.setint.yaml index 074157bbc3..9f7b5e5e69 100644 --- a/arch_overlay/qc_iu/inst/Xqci/qc.c.setint.yaml +++ b/arch_overlay/qc_iu/inst/Xqci/qc.c.setint.yaml @@ -29,5 +29,5 @@ operation(): | XReg idx = rs1 / 32; XReg bit = rs1 % 32; - XReg pre_csr = CSR[MCLICIP0_ADDR + idx].sw_read(); - CSR[MCLICIP0_ADDR + idx].sw_write(pre_csr | (1 << bit)); + Csr pre_csr = direct_csr_lookup(MCLICIP0_ADDR + idx); + csr_sw_write(pre_csr, csr_sw_read(pre_csr) | (1 << bit)); diff --git a/arch_overlay/qc_iu/inst/Xqci/qc.clrinti.yaml b/arch_overlay/qc_iu/inst/Xqci/qc.clrinti.yaml index 86be3a762d..81e9b42c53 100644 --- a/arch_overlay/qc_iu/inst/Xqci/qc.clrinti.yaml +++ b/arch_overlay/qc_iu/inst/Xqci/qc.clrinti.yaml @@ -28,5 +28,5 @@ operation(): | XReg idx = imm / 32; XReg bit = imm % 32; - XReg pre_csr = CSR[MCLICIP0_ADDR + idx].sw_read(); - CSR[MCLICIP0_ADDR + idx].sw_write(pre_csr & ~(1 << bit)); + Csr pre_csr = direct_csr_lookup(MCLICIP0_ADDR + idx); + csr_sw_write(pre_csr, csr_sw_read(pre_csr) & ~(1 << bit)); diff --git a/arch_overlay/qc_iu/inst/Xqci/qc.csrrwr.yaml b/arch_overlay/qc_iu/inst/Xqci/qc.csrrwr.yaml index 47c7a9a49f..4edaa962e4 100644 --- a/arch_overlay/qc_iu/inst/Xqci/qc.csrrwr.yaml +++ b/arch_overlay/qc_iu/inst/Xqci/qc.csrrwr.yaml @@ -35,10 +35,11 @@ access: vs: always vu: always operation(): | - XReg csr = X[rs2]; + XReg csr_addr = X[rs2]; + Csr csr = direct_csr_lookup(csr_addr); if (rd != 0) { - X[rd] = CSR[csr].sw_read(); + X[rd] = csr_sw_read(csr); } # writes the value in X[rs1] to the CSR, # performing any WARL transformations first - CSR[csr].sw_write(X[rs1]); + csr_sw_write(csr, X[rs1]); diff --git a/arch_overlay/qc_iu/inst/Xqci/qc.csrrwri.yaml b/arch_overlay/qc_iu/inst/Xqci/qc.csrrwri.yaml index 94c7df3741..f7c9d74985 100644 --- a/arch_overlay/qc_iu/inst/Xqci/qc.csrrwri.yaml +++ b/arch_overlay/qc_iu/inst/Xqci/qc.csrrwri.yaml @@ -35,10 +35,12 @@ access: vs: always vu: always operation(): | - XReg csr = X[rs2]; + XReg csr_addr = X[rs2]; + Csr csr = direct_csr_lookup(csr_addr); if (rd != 0) { - X[rd] = CSR[csr].sw_read(); + X[rd] = csr_sw_read(csr_addr); } # writes the zero-extended immediate to the CSR, - # performing any WARL transformations first - CSR[csr].sw_write({{XLEN-5{1'b0}}, imm}); + # performing any WARL transformations + # first + csr_sw_write(csr, {{XLEN-5{1'b0}}, imm}); diff --git a/arch_overlay/qc_iu/inst/Xqci/qc.setinti.yaml b/arch_overlay/qc_iu/inst/Xqci/qc.setinti.yaml index 537c311bde..9255bb8ac0 100644 --- a/arch_overlay/qc_iu/inst/Xqci/qc.setinti.yaml +++ b/arch_overlay/qc_iu/inst/Xqci/qc.setinti.yaml @@ -28,5 +28,5 @@ operation(): | XReg idx = imm / 32; XReg bit = imm % 32; - XReg pre_csr = CSR[MCLICIP0_ADDR + idx].sw_read(); - CSR[MCLICIP0_ADDR + idx].sw_write(pre_csr | (1 << bit)); + Csr pre_csr = direct_csr_lookup(MCLICIP0_ADDR + idx); + csr_sw_write(pre_csr, csr_sw_read(pre_csr) | (1 << bit)); diff --git a/backends/cpp_hart_gen/cpp/include/udb/csr.hpp b/backends/cpp_hart_gen/cpp/include/udb/csr.hpp index 668d582cbe..1399680674 100644 --- a/backends/cpp_hart_gen/cpp/include/udb/csr.hpp +++ b/backends/cpp_hart_gen/cpp/include/udb/csr.hpp @@ -84,6 +84,12 @@ namespace udb { virtual void reset() = 0; + // the most privileged mode that has access to this csr + virtual PrivilegeMode mode() const = 0; + + // false if the CSR is read only + virtual bool writable() const = 0; + // read the raw bits of a CSR value // // some CSRs are shorter than XLEN bits, but none are longer diff --git a/backends/cpp_hart_gen/lib/gen_cpp.rb b/backends/cpp_hart_gen/lib/gen_cpp.rb index 56b305eb5c..87f4590422 100644 --- a/backends/cpp_hart_gen/lib/gen_cpp.rb +++ b/backends/cpp_hart_gen/lib/gen_cpp.rb @@ -757,15 +757,10 @@ def gen_cpp(symtab, indent = 0, indent_spaces: 2) class CsrReadExpressionAst def gen_cpp(symtab, indent = 0, indent_spaces: 2) csr = csr_def(symtab) - if csr.nil? - # csr isn't known at runtime... - "#{' '*indent}__UDB_CSR_BY_ADDR(#{idx_expr.gen_cpp(symtab, 0, indent_spaces:)}).hw_read(__UDB_XLEN)" + if symtab.cfg_arch.multi_xlen? && csr.format_changes_with_xlen? + "#{' '*indent}__UDB_CSR_BY_NAME(#{csr.name})._hw_read(__UDB_XLEN)" else - if symtab.cfg_arch.multi_xlen? && csr.format_changes_with_xlen? - "#{' '*indent}__UDB_CSR_BY_NAME(#{csr.name})._hw_read(__UDB_XLEN)" - else - "#{' '*indent}__UDB_CSR_BY_NAME(#{csr.name})._hw_read()" - end + "#{' '*indent}__UDB_CSR_BY_NAME(#{csr.name})._hw_read()" end end end diff --git a/backends/cpp_hart_gen/templates/csrs.hxx.erb b/backends/cpp_hart_gen/templates/csrs.hxx.erb index 7bae01031f..2ecd720643 100644 --- a/backends/cpp_hart_gen/templates/csrs.hxx.erb +++ b/backends/cpp_hart_gen/templates/csrs.hxx.erb @@ -220,6 +220,8 @@ namespace udb { unsigned address() const override { return <%= csr.address %>; } static constexpr unsigned _address() { return <%= csr.address %>; } const std::string name() const override { return "<%= csr.name %>"; } + PrivilegeMode mode() const override { return PrivilegeMode::<%= csr.priv_mode %>; } + bool writable() const override { return <%= csr.writable %>; } void reset() override { <%- fields_for_xlen.each do |field| -%> diff --git a/backends/cpp_hart_gen/templates/hart.hxx.erb b/backends/cpp_hart_gen/templates/hart.hxx.erb index c9452a580c..52c12d3faf 100644 --- a/backends/cpp_hart_gen/templates/hart.hxx.erb +++ b/backends/cpp_hart_gen/templates/hart.hxx.erb @@ -225,7 +225,77 @@ namespace udb { return m_csr_addr_map.count(csr_addr) == 1; } + <%= name_of(:struct, "Csr", cfg_arch) %> direct_csr_lookup(const Bits<12>& csr_addr) { + <%= name_of(:struct, "Csr", cfg_arch) %> csr_handle; + + auto csr = m_csr_addr_map.find(csr_addr); + if (csr == m_csr_addr_map.end()) { + csr_handle.valid = false; + return csr_handle; + } else { + csr_handle.valid = true; + csr_handle.name = csr->name(); + csr_handle.addr_type = CsrAddressType::Direct; + csr_handle.address = csr_addr; + csr_handle.mode = csr->mode(); + csr_handle.writable = csr->writable(); + return csr_handle; + } + } + <%= name_of(:struct, "Csr", cfg_arch) %> indirect_csr_lookup(const Bits<64>& csr_indirect_addr) { + <%= name_of(:struct, "Csr", cfg_arch) %> csr_handle; + + auto csr = m_csr_indirect_addr_map.find(csr_addr); + if (csr == m_csr_indirect_addr_map.end()) { + csr_handle.valid = false; + return csr_handle; + } else { + csr_handle.valid = true; + csr_handle.name = csr->name(); + csr_handle.addr_type = CsrAddressType::Indirect; + csr_handle.address = csr_addr; + csr_handle.mode = csr->mode(); + csr_handle.writable = csr->writable(); + return csr_handle; + } + } + + PossiblyUnknownBits<64> csr_hw_read(const <%= name_of(:struct, "Csr", cfg_arch) %>& csr_handle) { + if (csr_handle.addr_type == CsrAddressType::Direct) { + auto csr = m_csr_addr_map.find(csr_handle.address); + udb_assert(csr != m_csr_addr_map.end(), "CSR not found"); + return csr.hw_read(xlen()); + } else { + auto csr = m_csr_indirect_addr_map.find(csr_handle.address); + udb_assert(csr != m_csr_indirect_addr_map.end(), "CSR not found"); + return csr.hw_read(xlen()); + } + } + + PossiblyUnknownBits<64> csr_sw_read(const <%= name_of(:struct, "Csr", cfg_arch) %>& csr_handle) { + if (csr_handle.addr_type == CsrAddressType::Direct) { + auto csr = m_csr_addr_map.find(csr_handle.address); + udb_assert(csr != m_csr_addr_map.end(), "CSR not found"); + return csr.sw_read(xlen()); + } else { + auto csr = m_csr_indirect_addr_map.find(csr_handle.address); + udb_assert(csr != m_csr_indirect_addr_map.end(), "CSR not found"); + return csr.sw_read(xlen()); + } + } + + void csr_sw_write(const <%= name_of(:struct, "Csr", cfg_arch) %>& csr_handle, const Bits<<%= cfg_arch.mxlen %>>& value) { + if (csr_handle.addr_type == CsrAddressType::Direct) { + auto csr = m_csr_addr_map.find(csr_handle.address); + udb_assert(csr != m_csr_addr_map.end(), "CSR not found"); + return csr.sw_write(value, xlen()); + } else { + auto csr = m_csr_indirect_addr_map.find(csr_handle.address); + udb_assert(csr != m_csr_indirect_addr_map.end(), "CSR not found"); + return csr.sw_write(value, xlen()); + } + } void set_pc(uint64_t new_pc) override { m_pc = new_pc; @@ -379,6 +449,7 @@ namespace udb { <%= name_of(:params, cfg_arch) %> m_params; <%= name_of(:csr_container, cfg_arch) %> m_csrs; std::unordered_map, CsrBase*> m_csr_addr_map; + std::unordered_map, CsrBase*> m_csr_indirect_addr_map; std::map m_csr_name_map; std::array m_run_one_inst_storage; diff --git a/backends/cpp_hart_gen/templates/hart_impl.hxx.erb b/backends/cpp_hart_gen/templates/hart_impl.hxx.erb index 72207eb8dc..153ad656af 100644 --- a/backends/cpp_hart_gen/templates/hart_impl.hxx.erb +++ b/backends/cpp_hart_gen/templates/hart_impl.hxx.erb @@ -43,6 +43,9 @@ namespace udb { <%- unless csr.address.nil? -%> m_csr_addr_map[<%= csr.address %>] = &m_csrs.<%= csr.name %>; <%- end -%> + <%- unless csr.indirect_address.nil? -%> + m_csr_indirect_addr_map[<%= csr.indirect_address %>] = &m_csrs.<%= csr.name %>; + <%_ end -%> m_csr_name_map["<%= csr.name %>"] = &m_csrs.<%= csr.name %>; <%- end -%> } diff --git a/lib/arch_obj_models/csr.rb b/lib/arch_obj_models/csr.rb index ff1639856b..b0e7f15de1 100644 --- a/lib/arch_obj_models/csr.rb +++ b/lib/arch_obj_models/csr.rb @@ -33,6 +33,10 @@ def virtual_address @data["virtual_address"] end + def writable + @data["writeable"] + end + # @return [Integer] 32 or 64, the XLEN this CSR is exclusively defined in # @return [nil] if this CSR is defined in all bases def base = @data["base"] diff --git a/lib/arch_obj_models/instruction.rb b/lib/arch_obj_models/instruction.rb index 738e73cc34..d056342052 100644 --- a/lib/arch_obj_models/instruction.rb +++ b/lib/arch_obj_models/instruction.rb @@ -158,10 +158,10 @@ def reachable_functions(effective_xlen) else # RubyProf.start ast = type_checked_operation_ast(effective_xlen) - print "Determining reachable funcs from #{name} (#{effective_xlen})..." + # print "Determining reachable funcs from #{name} (#{effective_xlen})..." symtab = fill_symtab(effective_xlen, ast) fns = ast.reachable_functions(symtab) - puts "done" + # puts "done" # result = RubyProf.stop # RubyProf::FlatPrinter.new(result).print($stdout) # exit diff --git a/lib/cfg_arch.rb b/lib/cfg_arch.rb index 05d4531912..47fb388454 100644 --- a/lib/cfg_arch.rb +++ b/lib/cfg_arch.rb @@ -215,10 +215,10 @@ def type_check(show_progress: true, io: $stdout) io.puts "Type checking IDL code for #{@config.name}..." progressbar = if show_progress - ProgressBar.create(title: "Instructions", total: instructions.size) + ProgressBar.create(title: "Instructions", total: possible_instructions.size) end - instructions.each do |inst| + possible_instructions.each do |inst| progressbar.increment if show_progress if @mxlen == 32 inst.type_checked_operation_ast(32) if inst.rv32? @@ -230,10 +230,10 @@ def type_check(show_progress: true, io: $stdout) progressbar = if show_progress - ProgressBar.create(title: "CSRs", total: csrs.size) + ProgressBar.create(title: "CSRs", total: possible_csrs.size) end - csrs.each do |csr| + possible_csrs.each do |csr| progressbar.increment if show_progress if csr.has_custom_sw_read? if (possible_xlens.include?(32) && csr.defined_in_base32?) @@ -265,11 +265,12 @@ def type_check(show_progress: true, io: $stdout) end end + func_list = reachable_functions progressbar = if show_progress - ProgressBar.create(title: "Functions", total: functions.size) + ProgressBar.create(title: "Functions", total: func_list.size) end - functions.each do |func| + func_list.each do |func| progressbar.increment if show_progress func.type_check(@symtab) end diff --git a/lib/idl/ast.rb b/lib/idl/ast.rb index 23ac6dd49a..17a135423f 100644 --- a/lib/idl/ast.rb +++ b/lib/idl/ast.rb @@ -2377,7 +2377,9 @@ def type_check(symtab, add_sym = true) value_else(value_result) do # if this is a fully configured ConfiguredArchitecture, this is an error because all constants are supposed to be known if symtab.cfg_arch.fully_configured? - type_error "Array size (#{ary_size.text_value}) must be known at compile time" + unless ary_size.type(symtab).template_var? + type_error "Array size (#{ary_size.text_value}) must be known at compile time" + end else # otherwise, it's ok that we don't know the value yet, as long as the value is a const type_error "Array size (#{ary_size.text_value}) must be a constant" unless ary_size.type(symtab).const? @@ -4367,7 +4369,11 @@ def type_check(symtab) end end value_else(value_result) do - type_error "Bit width must be known at compile time" if symtab.cfg_arch.fully_configured? + unless bits_expression.type(symtab).template_var? + if symtab.cfg_arch.fully_configured? + type_error "Bit width (#{bits_expression.text_value}) must be known at compile time" + end + end end end unless ["Bits", "String", "XReg", "Boolean", "U32", "U64"].include?(@type_name) @@ -4906,6 +4912,16 @@ def value(symtab) value_error "maybe_cache_translation is not compile-time-knowable" elsif name == "invalidate_translations" value_error "invalidate_translations is not compile-time-knowable" + elsif name == "direct_csr_lookup" + value_error "direct_csr_lookup is not compile-time-knowable" + elsif name == "indirect_csr_lookup" + value_error "indirect_csr_lookup is not compile-time-knowable" + elsif name == "csr_hw_read" + value_error "csr_hw_read is not compile-time-knowable" + elsif name == "csr_sw_read" + value_error "csr_sw_read is not compile-time-knowable" + elsif name == "csr_sw_write" + value_error "csr_sw_write is not compile-time-knowable" else internal_error "Unimplemented generated: '#{name}'" end @@ -5352,7 +5368,7 @@ def type_check(symtab) symtab = symtab.deep_clone symtab.push(self) template_names.each_with_index do |tname, index| - symtab.add(tname, Var.new(tname, template_types(symtab)[index])) + symtab.add(tname, Var.new(tname, template_types(symtab)[index], template_index: index)) end type_check_return(symtab) @@ -5399,6 +5415,7 @@ def template_types(symtab) ttype = a.type(symtab) ttype = ttype.ref_type if ttype.kind == :enum ttypes << ttype.clone.make_const + ttypes.last.qualify(:template_var) end ttypes end @@ -6109,7 +6126,7 @@ def calc_value(symtab) class CsrReadExpressionSyntaxNode < Treetop::Runtime::SyntaxNode def to_ast - CsrReadExpressionAst.new(input, interval, idx.text_value) + CsrReadExpressionAst.new(input, interval, csr_name.text_value) end end @@ -6122,13 +6139,12 @@ def to_ast class CsrReadExpressionAst < AstNode include Rvalue - attr_reader :idx_text - attr_reader :idx_expr + attr_reader :csr_name - def initialize(input, interval, idx) + def initialize(input, interval, csr_name) super(input, interval, []) - @idx_text = idx + @csr_name = csr_name end def freeze_tree(symtab) @@ -6136,73 +6152,25 @@ def freeze_tree(symtab) @cfg_arch = symtab.cfg_arch # remember cfg_arch, used by gen_adoc pass - if symtab.cfg_arch.csr(@idx_text).nil? - parser = symtab.cfg_arch.idl_compiler.parser - expr = parser.parse(@idx_text, root: :expression) + type_error "CSR '#{@csr_name}' is not defined" if symtab.cfg_arch.csr(@csr_name).nil? + @csr_obj = symtab.cfg_arch.csr(@csr_name) - type_error "#{@idx_text} is not a CSR; it must be an expression" if expr.nil? - - @idx_expr = expr.to_ast - @children << @idx_expr - else - @csr_obj = symtab.cfg_arch.csr(@idx_text) - end + @type = CsrType.new(@csr_obj, symtab.cfg_arch) @children.each { |child| child.freeze_tree(symtab) } freeze end # @!macro type - def type(symtab) - cfg_arch = symtab.cfg_arch - - cd = csr_def(symtab) - if cd.nil? - # we don't know anything about this index, so we can only - # treat this as a generic - CsrType.new(:unknown, cfg_arch) - else - CsrType.new(cd, cfg_arch) - end - end + def type(symtab) = @type # @!macro type_check def type_check(symtab) - cfg_arch = symtab.cfg_arch - - if !@csr_obj.nil? - # this is a known csr name - # nothing else to check - - else - # this is an expression - @idx_expr.type_check(symtab) - type_error "Csr index must be integral" unless @idx_expr.type(symtab).integral? - - value_try do - idx_value = @idx_expr.value(symtab) - csr_index = cfg_arch.csrs.index { |csr| csr.address == idx_value } - type_error "No csr number '#{idx_value}' was found" if csr_index.nil? - :ok - end - # OK, index doesn't have to be known - end + type_error "CSR '#{@csr_name}' is not defined" if symtab.cfg_arch.csr(@csr_name).nil? end def csr_def(symtab) - cfg_arch = symtab.cfg_arch - if !@csr_obj.nil? - # this is a known csr name - @csr_obj - else - # this is an expression - value_try do - idx_value = @idx_expr.value(symtab) - return cfg_arch.csrs.find { |csr| csr.address == idx_value } - end - # || we don't know at compile time which CSR this is... - nil - end + @csr_obj end def csr_known?(symtab) @@ -6217,20 +6185,18 @@ def csr_name(symtab) # @!macro value def value(symtab) - cd = csr_def(symtab) - value_error "CSR number not knowable" if cd.nil? if symtab.cfg_arch.fully_configured? - value_error "CSR is not implemented" unless symtab.cfg_arch.transitive_implemented_csrs.any? { |icsr| icsr.name == cd.name } + value_error "CSR is not implemented" unless symtab.cfg_arch.transitive_implemented_csrs.any? { |icsr| icsr.name == @csr_obj.name } else - value_error "CSR is not defined" unless symtab.cfg_arch.csrs.any? { |icsr| icsr.name == cd.name } + value_error "CSR is not defined" unless symtab.cfg_arch.csrs.any? { |icsr| icsr.name == @csr_obj.name } end - cd.fields.each { |f| value_error "#{csr_name(symtab)}.#{f.name} not RO" unless f.type(symtab) == "RO" } + @csr_obj.fields.each { |f| value_error "#{csr_name(symtab)}.#{f.name} not RO" unless f.type(symtab) == "RO" } csr_def(symtab).fields.reduce(0) { |val, f| val | (f.value << f.location.begin) } end # @!macro to_idl - def to_idl = "CSR[#{@idx.to_idl}]" + def to_idl = "CSR[#{@csr_name}]" end class CsrSoftwareWriteSyntaxNode < Treetop::Runtime::SyntaxNode diff --git a/lib/idl/idl.treetop b/lib/idl/idl.treetop index 9cead8a2b2..c30be56d24 100644 --- a/lib/idl/idl.treetop +++ b/lib/idl/idl.treetop @@ -275,7 +275,7 @@ grammar Idl rule csr_register_access_expression # CSR register access - 'CSR' space* '[' space* idx:(expression / csr_name) space* ']' + 'CSR' space* '[' space* csr_name space* ']' end rule field_access_eligible_expression @@ -652,7 +652,7 @@ grammar Idl end rule var_write - 'CSR' space* '[' space* idx:(csr_name / int) space* ']' + 'CSR' space* '[' space* csr_name space* ']' / id end diff --git a/lib/idl/passes/gen_adoc.rb b/lib/idl/passes/gen_adoc.rb index 5dde948cd6..355596e1d9 100644 --- a/lib/idl/passes/gen_adoc.rb +++ b/lib/idl/passes/gen_adoc.rb @@ -299,24 +299,8 @@ def gen_adoc(indent = 0, indent_spaces: 2) class CsrReadExpressionAst def gen_adoc(indent = 0, indent_spaces: 2) - idx = - if @idx_expr.nil? - @idx_text - else - @idx_expr.gen_adoc(0) - end - csr_text = "CSR[#{idx}]" - if idx_text =~ /[0-9]+/ - # we don't have the symtab to map this to a csr name - "#{' '*indent}#{csr_text}" - else - if @cfg_arch.csr(csr_text).nil? - "#{' '*indent}#{csr_text}" - else - "#{' '*indent}%%LINK%csr;#{idx};#{csr_text}%%" - end - end + "#{' '*indent}%%LINK%csr;#{csr_name};#{csr_text}%%" end end diff --git a/lib/idl/symbol_table.rb b/lib/idl/symbol_table.rb index d59ee0422f..24f0fa44e1 100644 --- a/lib/idl/symbol_table.rb +++ b/lib/idl/symbol_table.rb @@ -14,6 +14,7 @@ def initialize(name, type, value = nil, decode_var: false, template_index: nil, raise ArgumentError, "Expecting a Type, got #{type.class.name}" unless type.is_a?(Type) @type = type + @type.qualify(:template_var) @type.freeze @value = value raise "unexpected" unless decode_var.is_a?(TrueClass) || decode_var.is_a?(FalseClass) diff --git a/lib/idl/type.rb b/lib/idl/type.rb index 0b582e4584..1ae0bc6fc8 100644 --- a/lib/idl/type.rb +++ b/lib/idl/type.rb @@ -22,7 +22,8 @@ class Type QUALIFIERS = [ :const, :signed, - :global + :global, + :template_var ].freeze # true for any type that can generally be treated as a scalar integer @@ -394,6 +395,10 @@ def global? @qualifiers.include?(:global) end + def template_var? + @qualifiers.include?(:template_var) + end + def make_signed @qualifiers.append(:signed).uniq! self From 54b5f3a5d1a49f2d72858afea5391629d139f22f Mon Sep 17 00:00:00 2001 From: Derek Hower Date: Fri, 4 Apr 2025 11:02:09 -0700 Subject: [PATCH 03/15] schema(csr): add writeable field This adds a boolean writeable field to the CSR schema. We need this for two reasons: * Indirect CSRs that have no address convention * CSRs like mscontext that don't follow the direct address convention --- arch/csr/F/fcsr.yaml | 1 + arch/csr/H/hcounteren.yaml | 1 + arch/csr/H/henvcfg.yaml | 1 + arch/csr/H/henvcfgh.yaml | 1 + arch/csr/H/hgatp.yaml | 1 + arch/csr/H/htimedelta.yaml | 1 + arch/csr/H/htimedeltah.yaml | 1 + arch/csr/H/htinst.yaml | 1 + arch/csr/H/htval.yaml | 1 + arch/csr/H/mtinst.yaml | 1 + arch/csr/H/mtval2.yaml | 1 + arch/csr/H/vsatp.yaml | 1 + arch/csr/I/mcounteren.yaml | 1 + arch/csr/I/pmpaddr0.yaml | 1 + arch/csr/I/pmpaddr1.yaml | 1 + arch/csr/I/pmpaddr10.yaml | 1 + arch/csr/I/pmpaddr11.yaml | 1 + arch/csr/I/pmpaddr12.yaml | 1 + arch/csr/I/pmpaddr13.yaml | 1 + arch/csr/I/pmpaddr14.yaml | 1 + arch/csr/I/pmpaddr15.yaml | 1 + arch/csr/I/pmpaddr16.yaml | 1 + arch/csr/I/pmpaddr17.yaml | 1 + arch/csr/I/pmpaddr18.yaml | 1 + arch/csr/I/pmpaddr19.yaml | 1 + arch/csr/I/pmpaddr2.yaml | 1 + arch/csr/I/pmpaddr20.yaml | 1 + arch/csr/I/pmpaddr21.yaml | 1 + arch/csr/I/pmpaddr22.yaml | 1 + arch/csr/I/pmpaddr23.yaml | 1 + arch/csr/I/pmpaddr24.yaml | 1 + arch/csr/I/pmpaddr25.yaml | 1 + arch/csr/I/pmpaddr26.yaml | 1 + arch/csr/I/pmpaddr27.yaml | 1 + arch/csr/I/pmpaddr28.yaml | 1 + arch/csr/I/pmpaddr29.yaml | 1 + arch/csr/I/pmpaddr3.yaml | 1 + arch/csr/I/pmpaddr30.yaml | 1 + arch/csr/I/pmpaddr31.yaml | 1 + arch/csr/I/pmpaddr32.yaml | 1 + arch/csr/I/pmpaddr33.yaml | 1 + arch/csr/I/pmpaddr34.yaml | 1 + arch/csr/I/pmpaddr35.yaml | 1 + arch/csr/I/pmpaddr36.yaml | 1 + arch/csr/I/pmpaddr37.yaml | 1 + arch/csr/I/pmpaddr38.yaml | 1 + arch/csr/I/pmpaddr39.yaml | 1 + arch/csr/I/pmpaddr4.yaml | 1 + arch/csr/I/pmpaddr40.yaml | 1 + arch/csr/I/pmpaddr41.yaml | 1 + arch/csr/I/pmpaddr42.yaml | 1 + arch/csr/I/pmpaddr43.yaml | 1 + arch/csr/I/pmpaddr44.yaml | 1 + arch/csr/I/pmpaddr45.yaml | 1 + arch/csr/I/pmpaddr46.yaml | 1 + arch/csr/I/pmpaddr47.yaml | 1 + arch/csr/I/pmpaddr48.yaml | 1 + arch/csr/I/pmpaddr49.yaml | 1 + arch/csr/I/pmpaddr5.yaml | 1 + arch/csr/I/pmpaddr50.yaml | 1 + arch/csr/I/pmpaddr51.yaml | 1 + arch/csr/I/pmpaddr52.yaml | 1 + arch/csr/I/pmpaddr53.yaml | 1 + arch/csr/I/pmpaddr54.yaml | 1 + arch/csr/I/pmpaddr55.yaml | 1 + arch/csr/I/pmpaddr56.yaml | 1 + arch/csr/I/pmpaddr57.yaml | 1 + arch/csr/I/pmpaddr58.yaml | 1 + arch/csr/I/pmpaddr59.yaml | 1 + arch/csr/I/pmpaddr6.yaml | 1 + arch/csr/I/pmpaddr60.yaml | 1 + arch/csr/I/pmpaddr61.yaml | 1 + arch/csr/I/pmpaddr62.yaml | 1 + arch/csr/I/pmpaddr63.yaml | 1 + arch/csr/I/pmpaddr7.yaml | 1 + arch/csr/I/pmpaddr8.yaml | 1 + arch/csr/I/pmpaddr9.yaml | 1 + arch/csr/I/pmpcfg0.yaml | 1 + arch/csr/I/pmpcfg1.yaml | 1 + arch/csr/I/pmpcfg10.yaml | 1 + arch/csr/I/pmpcfg11.yaml | 1 + arch/csr/I/pmpcfg12.yaml | 1 + arch/csr/I/pmpcfg13.yaml | 1 + arch/csr/I/pmpcfg14.yaml | 1 + arch/csr/I/pmpcfg15.yaml | 1 + arch/csr/I/pmpcfg2.yaml | 1 + arch/csr/I/pmpcfg3.yaml | 1 + arch/csr/I/pmpcfg4.yaml | 1 + arch/csr/I/pmpcfg5.yaml | 1 + arch/csr/I/pmpcfg6.yaml | 1 + arch/csr/I/pmpcfg7.yaml | 1 + arch/csr/I/pmpcfg8.yaml | 1 + arch/csr/I/pmpcfg9.yaml | 1 + arch/csr/S/scounteren.yaml | 1 + arch/csr/Smrnmi/mncause.yaml | 1 + arch/csr/Smrnmi/mnepc.yaml | 1 + arch/csr/Smrnmi/mnscratch.yaml | 5 ++++- arch/csr/Smrnmi/mnstatus.yaml | 5 ++++- arch/csr/Zicntr/mcountinhibit.yaml | 1 + arch/csr/Zihpm/hpmcounter10.yaml | 1 + arch/csr/Zihpm/hpmcounter10h.yaml | 1 + arch/csr/Zihpm/hpmcounter11.yaml | 1 + arch/csr/Zihpm/hpmcounter11h.yaml | 1 + arch/csr/Zihpm/hpmcounter12.yaml | 1 + arch/csr/Zihpm/hpmcounter12h.yaml | 1 + arch/csr/Zihpm/hpmcounter13.yaml | 1 + arch/csr/Zihpm/hpmcounter13h.yaml | 1 + arch/csr/Zihpm/hpmcounter14.yaml | 1 + arch/csr/Zihpm/hpmcounter14h.yaml | 1 + arch/csr/Zihpm/hpmcounter15.yaml | 1 + arch/csr/Zihpm/hpmcounter15h.yaml | 1 + arch/csr/Zihpm/hpmcounter16.yaml | 1 + arch/csr/Zihpm/hpmcounter16h.yaml | 1 + arch/csr/Zihpm/hpmcounter17.yaml | 1 + arch/csr/Zihpm/hpmcounter17h.yaml | 1 + arch/csr/Zihpm/hpmcounter18.yaml | 1 + arch/csr/Zihpm/hpmcounter18h.yaml | 1 + arch/csr/Zihpm/hpmcounter19.yaml | 1 + arch/csr/Zihpm/hpmcounter19h.yaml | 1 + arch/csr/Zihpm/hpmcounter20.yaml | 1 + arch/csr/Zihpm/hpmcounter20h.yaml | 1 + arch/csr/Zihpm/hpmcounter21.yaml | 1 + arch/csr/Zihpm/hpmcounter21h.yaml | 1 + arch/csr/Zihpm/hpmcounter22.yaml | 1 + arch/csr/Zihpm/hpmcounter22h.yaml | 1 + arch/csr/Zihpm/hpmcounter23.yaml | 1 + arch/csr/Zihpm/hpmcounter23h.yaml | 1 + arch/csr/Zihpm/hpmcounter24.yaml | 1 + arch/csr/Zihpm/hpmcounter24h.yaml | 1 + arch/csr/Zihpm/hpmcounter25.yaml | 1 + arch/csr/Zihpm/hpmcounter25h.yaml | 1 + arch/csr/Zihpm/hpmcounter26.yaml | 1 + arch/csr/Zihpm/hpmcounter26h.yaml | 1 + arch/csr/Zihpm/hpmcounter27.yaml | 1 + arch/csr/Zihpm/hpmcounter27h.yaml | 1 + arch/csr/Zihpm/hpmcounter28.yaml | 1 + arch/csr/Zihpm/hpmcounter28h.yaml | 1 + arch/csr/Zihpm/hpmcounter29.yaml | 1 + arch/csr/Zihpm/hpmcounter29h.yaml | 1 + arch/csr/Zihpm/hpmcounter3.yaml | 1 + arch/csr/Zihpm/hpmcounter30.yaml | 1 + arch/csr/Zihpm/hpmcounter30h.yaml | 1 + arch/csr/Zihpm/hpmcounter31.yaml | 1 + arch/csr/Zihpm/hpmcounter31h.yaml | 1 + arch/csr/Zihpm/hpmcounter3h.yaml | 1 + arch/csr/Zihpm/hpmcounter4.yaml | 1 + arch/csr/Zihpm/hpmcounter4h.yaml | 1 + arch/csr/Zihpm/hpmcounter5.yaml | 1 + arch/csr/Zihpm/hpmcounter5h.yaml | 1 + arch/csr/Zihpm/hpmcounter6.yaml | 1 + arch/csr/Zihpm/hpmcounter6h.yaml | 1 + arch/csr/Zihpm/hpmcounter7.yaml | 1 + arch/csr/Zihpm/hpmcounter7h.yaml | 1 + arch/csr/Zihpm/hpmcounter8.yaml | 1 + arch/csr/Zihpm/hpmcounter8h.yaml | 1 + arch/csr/Zihpm/hpmcounter9.yaml | 1 + arch/csr/Zihpm/hpmcounter9h.yaml | 1 + arch/csr/Zihpm/mhpmcounter10.yaml | 1 + arch/csr/Zihpm/mhpmcounter10h.yaml | 1 + arch/csr/Zihpm/mhpmcounter11.yaml | 1 + arch/csr/Zihpm/mhpmcounter11h.yaml | 1 + arch/csr/Zihpm/mhpmcounter12.yaml | 1 + arch/csr/Zihpm/mhpmcounter12h.yaml | 1 + arch/csr/Zihpm/mhpmcounter13.yaml | 1 + arch/csr/Zihpm/mhpmcounter13h.yaml | 1 + arch/csr/Zihpm/mhpmcounter14.yaml | 1 + arch/csr/Zihpm/mhpmcounter14h.yaml | 1 + arch/csr/Zihpm/mhpmcounter15.yaml | 1 + arch/csr/Zihpm/mhpmcounter15h.yaml | 1 + arch/csr/Zihpm/mhpmcounter16.yaml | 1 + arch/csr/Zihpm/mhpmcounter16h.yaml | 1 + arch/csr/Zihpm/mhpmcounter17.yaml | 1 + arch/csr/Zihpm/mhpmcounter17h.yaml | 1 + arch/csr/Zihpm/mhpmcounter18.yaml | 1 + arch/csr/Zihpm/mhpmcounter18h.yaml | 1 + arch/csr/Zihpm/mhpmcounter19.yaml | 1 + arch/csr/Zihpm/mhpmcounter19h.yaml | 1 + arch/csr/Zihpm/mhpmcounter20.yaml | 1 + arch/csr/Zihpm/mhpmcounter20h.yaml | 1 + arch/csr/Zihpm/mhpmcounter21.yaml | 1 + arch/csr/Zihpm/mhpmcounter21h.yaml | 1 + arch/csr/Zihpm/mhpmcounter22.yaml | 1 + arch/csr/Zihpm/mhpmcounter22h.yaml | 1 + arch/csr/Zihpm/mhpmcounter23.yaml | 1 + arch/csr/Zihpm/mhpmcounter23h.yaml | 1 + arch/csr/Zihpm/mhpmcounter24.yaml | 1 + arch/csr/Zihpm/mhpmcounter24h.yaml | 1 + arch/csr/Zihpm/mhpmcounter25.yaml | 1 + arch/csr/Zihpm/mhpmcounter25h.yaml | 1 + arch/csr/Zihpm/mhpmcounter26.yaml | 1 + arch/csr/Zihpm/mhpmcounter26h.yaml | 1 + arch/csr/Zihpm/mhpmcounter27.yaml | 1 + arch/csr/Zihpm/mhpmcounter27h.yaml | 1 + arch/csr/Zihpm/mhpmcounter28.yaml | 1 + arch/csr/Zihpm/mhpmcounter28h.yaml | 1 + arch/csr/Zihpm/mhpmcounter29.yaml | 1 + arch/csr/Zihpm/mhpmcounter29h.yaml | 1 + arch/csr/Zihpm/mhpmcounter3.yaml | 1 + arch/csr/Zihpm/mhpmcounter30.yaml | 1 + arch/csr/Zihpm/mhpmcounter30h.yaml | 1 + arch/csr/Zihpm/mhpmcounter31.yaml | 1 + arch/csr/Zihpm/mhpmcounter31h.yaml | 1 + arch/csr/Zihpm/mhpmcounter3h.yaml | 1 + arch/csr/Zihpm/mhpmcounter4.yaml | 1 + arch/csr/Zihpm/mhpmcounter4h.yaml | 1 + arch/csr/Zihpm/mhpmcounter5.yaml | 1 + arch/csr/Zihpm/mhpmcounter5h.yaml | 1 + arch/csr/Zihpm/mhpmcounter6.yaml | 1 + arch/csr/Zihpm/mhpmcounter6h.yaml | 1 + arch/csr/Zihpm/mhpmcounter7.yaml | 1 + arch/csr/Zihpm/mhpmcounter7h.yaml | 1 + arch/csr/Zihpm/mhpmcounter8.yaml | 1 + arch/csr/Zihpm/mhpmcounter8h.yaml | 1 + arch/csr/Zihpm/mhpmcounter9.yaml | 1 + arch/csr/Zihpm/mhpmcounter9h.yaml | 1 + arch/csr/Zihpm/mhpmevent10.yaml | 21 ++++++++++++++++----- arch/csr/Zihpm/mhpmevent10h.yaml | 1 + arch/csr/Zihpm/mhpmevent11.yaml | 21 ++++++++++++++++----- arch/csr/Zihpm/mhpmevent11h.yaml | 1 + arch/csr/Zihpm/mhpmevent12.yaml | 21 ++++++++++++++++----- arch/csr/Zihpm/mhpmevent12h.yaml | 1 + arch/csr/Zihpm/mhpmevent13.yaml | 21 ++++++++++++++++----- arch/csr/Zihpm/mhpmevent13h.yaml | 1 + arch/csr/Zihpm/mhpmevent14.yaml | 21 ++++++++++++++++----- arch/csr/Zihpm/mhpmevent14h.yaml | 1 + arch/csr/Zihpm/mhpmevent15.yaml | 21 ++++++++++++++++----- arch/csr/Zihpm/mhpmevent15h.yaml | 1 + arch/csr/Zihpm/mhpmevent16.yaml | 21 ++++++++++++++++----- arch/csr/Zihpm/mhpmevent16h.yaml | 1 + arch/csr/Zihpm/mhpmevent17.yaml | 21 ++++++++++++++++----- arch/csr/Zihpm/mhpmevent17h.yaml | 1 + arch/csr/Zihpm/mhpmevent18.yaml | 21 ++++++++++++++++----- arch/csr/Zihpm/mhpmevent18h.yaml | 1 + arch/csr/Zihpm/mhpmevent19.yaml | 21 ++++++++++++++++----- arch/csr/Zihpm/mhpmevent19h.yaml | 1 + arch/csr/Zihpm/mhpmevent20.yaml | 21 ++++++++++++++++----- arch/csr/Zihpm/mhpmevent20h.yaml | 1 + arch/csr/Zihpm/mhpmevent21.yaml | 21 ++++++++++++++++----- arch/csr/Zihpm/mhpmevent21h.yaml | 1 + arch/csr/Zihpm/mhpmevent22.yaml | 21 ++++++++++++++++----- arch/csr/Zihpm/mhpmevent22h.yaml | 1 + arch/csr/Zihpm/mhpmevent23.yaml | 21 ++++++++++++++++----- arch/csr/Zihpm/mhpmevent23h.yaml | 1 + arch/csr/Zihpm/mhpmevent24.yaml | 21 ++++++++++++++++----- arch/csr/Zihpm/mhpmevent24h.yaml | 1 + arch/csr/Zihpm/mhpmevent25.yaml | 21 ++++++++++++++++----- arch/csr/Zihpm/mhpmevent25h.yaml | 1 + arch/csr/Zihpm/mhpmevent26.yaml | 21 ++++++++++++++++----- arch/csr/Zihpm/mhpmevent26h.yaml | 1 + arch/csr/Zihpm/mhpmevent27.yaml | 21 ++++++++++++++++----- arch/csr/Zihpm/mhpmevent27h.yaml | 1 + arch/csr/Zihpm/mhpmevent28.yaml | 21 ++++++++++++++++----- arch/csr/Zihpm/mhpmevent28h.yaml | 1 + arch/csr/Zihpm/mhpmevent29.yaml | 21 ++++++++++++++++----- arch/csr/Zihpm/mhpmevent29h.yaml | 1 + arch/csr/Zihpm/mhpmevent3.yaml | 21 ++++++++++++++++----- arch/csr/Zihpm/mhpmevent30.yaml | 21 ++++++++++++++++----- arch/csr/Zihpm/mhpmevent30h.yaml | 1 + arch/csr/Zihpm/mhpmevent31.yaml | 21 ++++++++++++++++----- arch/csr/Zihpm/mhpmevent31h.yaml | 1 + arch/csr/Zihpm/mhpmevent3h.yaml | 1 + arch/csr/Zihpm/mhpmevent4.yaml | 21 ++++++++++++++++----- arch/csr/Zihpm/mhpmevent4h.yaml | 1 + arch/csr/Zihpm/mhpmevent5.yaml | 21 ++++++++++++++++----- arch/csr/Zihpm/mhpmevent5h.yaml | 1 + arch/csr/Zihpm/mhpmevent6.yaml | 21 ++++++++++++++++----- arch/csr/Zihpm/mhpmevent6h.yaml | 1 + arch/csr/Zihpm/mhpmevent7.yaml | 21 ++++++++++++++++----- arch/csr/Zihpm/mhpmevent7h.yaml | 1 + arch/csr/Zihpm/mhpmevent8.yaml | 21 ++++++++++++++++----- arch/csr/Zihpm/mhpmevent8h.yaml | 1 + arch/csr/Zihpm/mhpmevent9.yaml | 21 ++++++++++++++++----- arch/csr/Zihpm/mhpmevent9h.yaml | 1 + arch/csr/cycle.yaml | 1 + arch/csr/cycleh.yaml | 1 + arch/csr/hedeleg.yaml | 1 + arch/csr/hedelegh.yaml | 1 + arch/csr/hstatus.yaml | 1 + arch/csr/instret.yaml | 1 + arch/csr/instreth.yaml | 1 + arch/csr/marchid.yaml | 1 + arch/csr/mcause.yaml | 1 + arch/csr/mconfigptr.yaml | 5 ++++- arch/csr/mcycle.yaml | 1 + arch/csr/mcycleh.yaml | 1 + arch/csr/medeleg.yaml | 1 + arch/csr/medelegh.yaml | 1 + arch/csr/menvcfg.yaml | 1 + arch/csr/menvcfgh.yaml | 1 + arch/csr/mepc.yaml | 1 + arch/csr/mhartid.yaml | 1 + arch/csr/mideleg.yaml | 1 + arch/csr/mie.yaml | 1 + arch/csr/mimpid.yaml | 1 + arch/csr/minstret.yaml | 1 + arch/csr/minstreth.yaml | 1 + arch/csr/mip.yaml | 1 + arch/csr/misa.yaml | 1 + arch/csr/mscratch.yaml | 1 + arch/csr/mseccfg.yaml | 1 + arch/csr/mseccfgh.yaml | 1 + arch/csr/mstatus.yaml | 5 ++++- arch/csr/mstatush.yaml | 5 ++++- arch/csr/mtval.yaml | 1 + arch/csr/mtvec.yaml | 1 + arch/csr/mvendorid.yaml | 1 + arch/csr/satp.yaml | 5 ++++- arch/csr/scause.yaml | 1 + arch/csr/senvcfg.yaml | 1 + arch/csr/sepc.yaml | 1 + arch/csr/sip.yaml | 1 + arch/csr/sscratch.yaml | 1 + arch/csr/sstatus.yaml | 1 + arch/csr/stval.yaml | 1 + arch/csr/stvec.yaml | 1 + arch/csr/time.yaml | 1 + arch/csr/timeh.yaml | 1 + arch/csr/vscause.yaml | 1 + arch/csr/vsepc.yaml | 1 + arch/csr/vsstatus.yaml | 1 + arch/csr/vstval.yaml | 1 + arch/csr/vstvec.yaml | 1 + schemas/csr_schema.json | 5 ++--- 323 files changed, 777 insertions(+), 154 deletions(-) diff --git a/arch/csr/F/fcsr.yaml b/arch/csr/F/fcsr.yaml index a44a5b39c7..d1cd315e8d 100644 --- a/arch/csr/F/fcsr.yaml +++ b/arch/csr/F/fcsr.yaml @@ -5,6 +5,7 @@ kind: csr name: fcsr long_name: Floating-point control and status register (`frm` + `fflags`) address: 0x003 +writeable: true description: | The floating-point control and status register, `fcsr`, is a RISC-V control and status register (CSR). It is a 32-bit read/write register diff --git a/arch/csr/H/hcounteren.yaml b/arch/csr/H/hcounteren.yaml index 45a80cfa49..1f0cacb970 100644 --- a/arch/csr/H/hcounteren.yaml +++ b/arch/csr/H/hcounteren.yaml @@ -6,6 +6,7 @@ kind: csr name: hcounteren long_name: Hypervisor Counter Enable address: 0x606 +writeable: true priv_mode: S length: 32 description: | diff --git a/arch/csr/H/henvcfg.yaml b/arch/csr/H/henvcfg.yaml index 462bc0f138..719a45345d 100644 --- a/arch/csr/H/henvcfg.yaml +++ b/arch/csr/H/henvcfg.yaml @@ -4,6 +4,7 @@ $schema: "csr_schema.json#" kind: csr name: henvcfg address: 0x60A +writeable: true long_name: Hypervisor Environment Configuration description: | The henvcfg CSR is a 64-bit read/write register that controls certain characteristics of the diff --git a/arch/csr/H/henvcfgh.yaml b/arch/csr/H/henvcfgh.yaml index 4f136fce3f..1b423c783e 100644 --- a/arch/csr/H/henvcfgh.yaml +++ b/arch/csr/H/henvcfgh.yaml @@ -4,6 +4,7 @@ $schema: "csr_schema.json#" kind: csr name: henvcfgh address: 0x61A +writeable: true base: 32 long_name: most-significant 32 bits of Hypervisor Environment Configuration description: | diff --git a/arch/csr/H/hgatp.yaml b/arch/csr/H/hgatp.yaml index 034b1d0178..b890bdc7cd 100644 --- a/arch/csr/H/hgatp.yaml +++ b/arch/csr/H/hgatp.yaml @@ -102,6 +102,7 @@ description: | HFENCE.GVMA instruction (see <>) before or after writing `hgatp`. address: 0x680 +writeable: true priv_mode: S definedBy: H length: SXLEN diff --git a/arch/csr/H/htimedelta.yaml b/arch/csr/H/htimedelta.yaml index 48de13f532..be9572cfa6 100644 --- a/arch/csr/H/htimedelta.yaml +++ b/arch/csr/H/htimedelta.yaml @@ -15,6 +15,7 @@ description: | `htimedelta` may be used to represent negative time offsets. address: 0x605 +writeable: true priv_mode: S definedBy: H length: 64 diff --git a/arch/csr/H/htimedeltah.yaml b/arch/csr/H/htimedeltah.yaml index 9aad2147e5..663b3e61be 100644 --- a/arch/csr/H/htimedeltah.yaml +++ b/arch/csr/H/htimedeltah.yaml @@ -8,6 +8,7 @@ description: | Upper half of the `htimedelta` CSR. address: 0x615 +writeable: true priv_mode: S definedBy: H length: 32 diff --git a/arch/csr/H/htinst.yaml b/arch/csr/H/htinst.yaml index f4a9df9e4a..6c1edf713b 100644 --- a/arch/csr/H/htinst.yaml +++ b/arch/csr/H/htinst.yaml @@ -4,6 +4,7 @@ $schema: "csr_schema.json#" kind: csr name: htinst address: 0x64a +writeable: true long_name: Hypervisor Trap Instruction Register description: | When a trap is taken into HS-mode, mtinst is written with a value that, if nonzero, diff --git a/arch/csr/H/htval.yaml b/arch/csr/H/htval.yaml index 39631dcfc2..2f3498e01d 100644 --- a/arch/csr/H/htval.yaml +++ b/arch/csr/H/htval.yaml @@ -4,6 +4,7 @@ $schema: "csr_schema.json#" kind: csr name: htval address: 0x643 +writeable: true long_name: Hypervisor Trap Value Register description: | When a trap is taken into HS-mode, htval is written with additional exception-specific information, alongside stval, to assist software in handling the trap. diff --git a/arch/csr/H/mtinst.yaml b/arch/csr/H/mtinst.yaml index bbfff0cd32..a145cb4124 100644 --- a/arch/csr/H/mtinst.yaml +++ b/arch/csr/H/mtinst.yaml @@ -4,6 +4,7 @@ $schema: "csr_schema.json#" kind: csr name: mtinst address: 0x34a +writeable: true long_name: Machine Trap Instruction Register description: | When a trap is taken into M-mode, mtinst is written with a value that, if nonzero, diff --git a/arch/csr/H/mtval2.yaml b/arch/csr/H/mtval2.yaml index 03d5db862f..fce637d5c1 100644 --- a/arch/csr/H/mtval2.yaml +++ b/arch/csr/H/mtval2.yaml @@ -4,6 +4,7 @@ $schema: "csr_schema.json#" kind: csr name: mtval2 address: 0x34b +writeable: true long_name: Machine Second Trap Value Register description: | When a trap is taken into M-mode from a virtual mode, mtval2 is written with additional exception-specific information, diff --git a/arch/csr/H/vsatp.yaml b/arch/csr/H/vsatp.yaml index fef44032c4..21d5489a5f 100644 --- a/arch/csr/H/vsatp.yaml +++ b/arch/csr/H/vsatp.yaml @@ -4,6 +4,7 @@ $schema: "csr_schema.json#" kind: csr name: vsatp address: 0x280 +writeable: true virtual_address: 0x180 long_name: Virtual Supervisor Address Translation and Protection description: | diff --git a/arch/csr/I/mcounteren.yaml b/arch/csr/I/mcounteren.yaml index 7d2e0dbac2..4b463a6c71 100644 --- a/arch/csr/I/mcounteren.yaml +++ b/arch/csr/I/mcounteren.yaml @@ -6,6 +6,7 @@ kind: csr name: mcounteren long_name: Machine Counter Enable address: 0x306 +writeable: true priv_mode: M length: 32 description: | diff --git a/arch/csr/I/pmpaddr0.yaml b/arch/csr/I/pmpaddr0.yaml index 250d438c06..260044ac66 100644 --- a/arch/csr/I/pmpaddr0.yaml +++ b/arch/csr/I/pmpaddr0.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr0 long_name: PMP Address 0 address: 0x3B0 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr1.yaml b/arch/csr/I/pmpaddr1.yaml index 5e24bf677c..3bd35c72f1 100644 --- a/arch/csr/I/pmpaddr1.yaml +++ b/arch/csr/I/pmpaddr1.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr1 long_name: PMP Address 1 address: 0x3B1 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr10.yaml b/arch/csr/I/pmpaddr10.yaml index a7da04a4b6..060fdf466a 100644 --- a/arch/csr/I/pmpaddr10.yaml +++ b/arch/csr/I/pmpaddr10.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr10 long_name: PMP Address 10 address: 0x3BA +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr11.yaml b/arch/csr/I/pmpaddr11.yaml index a8ccd0b6bc..3dd73dd011 100644 --- a/arch/csr/I/pmpaddr11.yaml +++ b/arch/csr/I/pmpaddr11.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr11 long_name: PMP Address 11 address: 0x3BB +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr12.yaml b/arch/csr/I/pmpaddr12.yaml index 10f1f2efe5..c5ab762ef5 100644 --- a/arch/csr/I/pmpaddr12.yaml +++ b/arch/csr/I/pmpaddr12.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr12 long_name: PMP Address 12 address: 0x3BC +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr13.yaml b/arch/csr/I/pmpaddr13.yaml index 99d40a0936..8bff40b843 100644 --- a/arch/csr/I/pmpaddr13.yaml +++ b/arch/csr/I/pmpaddr13.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr13 long_name: PMP Address 13 address: 0x3BD +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr14.yaml b/arch/csr/I/pmpaddr14.yaml index cda0e1265e..8caa138a42 100644 --- a/arch/csr/I/pmpaddr14.yaml +++ b/arch/csr/I/pmpaddr14.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr14 long_name: PMP Address 14 address: 0x3BE +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr15.yaml b/arch/csr/I/pmpaddr15.yaml index 1cb1232715..183d441a60 100644 --- a/arch/csr/I/pmpaddr15.yaml +++ b/arch/csr/I/pmpaddr15.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr15 long_name: PMP Address 15 address: 0x3BF +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr16.yaml b/arch/csr/I/pmpaddr16.yaml index d766d82fa5..60849d9dbf 100644 --- a/arch/csr/I/pmpaddr16.yaml +++ b/arch/csr/I/pmpaddr16.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr16 long_name: PMP Address 16 address: 0x3C0 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr17.yaml b/arch/csr/I/pmpaddr17.yaml index 94b5b47b47..326781d8a9 100644 --- a/arch/csr/I/pmpaddr17.yaml +++ b/arch/csr/I/pmpaddr17.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr17 long_name: PMP Address 17 address: 0x3C1 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr18.yaml b/arch/csr/I/pmpaddr18.yaml index 1006a07df5..6d725a7e64 100644 --- a/arch/csr/I/pmpaddr18.yaml +++ b/arch/csr/I/pmpaddr18.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr18 long_name: PMP Address 18 address: 0x3C2 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr19.yaml b/arch/csr/I/pmpaddr19.yaml index 7caa8cfbed..a1380146b3 100644 --- a/arch/csr/I/pmpaddr19.yaml +++ b/arch/csr/I/pmpaddr19.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr19 long_name: PMP Address 19 address: 0x3C3 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr2.yaml b/arch/csr/I/pmpaddr2.yaml index 8805ecdafe..37ca3e5c54 100644 --- a/arch/csr/I/pmpaddr2.yaml +++ b/arch/csr/I/pmpaddr2.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr2 long_name: PMP Address 2 address: 0x3B2 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr20.yaml b/arch/csr/I/pmpaddr20.yaml index 2479fbb520..f5bc7eed7f 100644 --- a/arch/csr/I/pmpaddr20.yaml +++ b/arch/csr/I/pmpaddr20.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr20 long_name: PMP Address 20 address: 0x3C4 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr21.yaml b/arch/csr/I/pmpaddr21.yaml index 27f99fec38..66b16eb7c7 100644 --- a/arch/csr/I/pmpaddr21.yaml +++ b/arch/csr/I/pmpaddr21.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr21 long_name: PMP Address 21 address: 0x3C5 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr22.yaml b/arch/csr/I/pmpaddr22.yaml index e738359032..173311eeec 100644 --- a/arch/csr/I/pmpaddr22.yaml +++ b/arch/csr/I/pmpaddr22.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr22 long_name: PMP Address 22 address: 0x3C6 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr23.yaml b/arch/csr/I/pmpaddr23.yaml index b23078e01e..9d9cf29811 100644 --- a/arch/csr/I/pmpaddr23.yaml +++ b/arch/csr/I/pmpaddr23.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr23 long_name: PMP Address 23 address: 0x3C7 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr24.yaml b/arch/csr/I/pmpaddr24.yaml index f07a22f661..987f8e7540 100644 --- a/arch/csr/I/pmpaddr24.yaml +++ b/arch/csr/I/pmpaddr24.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr24 long_name: PMP Address 24 address: 0x3C8 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr25.yaml b/arch/csr/I/pmpaddr25.yaml index c3a791b223..d2e53d83eb 100644 --- a/arch/csr/I/pmpaddr25.yaml +++ b/arch/csr/I/pmpaddr25.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr25 long_name: PMP Address 25 address: 0x3C9 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr26.yaml b/arch/csr/I/pmpaddr26.yaml index ad2d1cb063..9c1a92dd02 100644 --- a/arch/csr/I/pmpaddr26.yaml +++ b/arch/csr/I/pmpaddr26.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr26 long_name: PMP Address 26 address: 0x3CA +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr27.yaml b/arch/csr/I/pmpaddr27.yaml index ef27d3bf9c..f8df97afdc 100644 --- a/arch/csr/I/pmpaddr27.yaml +++ b/arch/csr/I/pmpaddr27.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr27 long_name: PMP Address 27 address: 0x3CB +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr28.yaml b/arch/csr/I/pmpaddr28.yaml index b7f1bf4278..c2ba979815 100644 --- a/arch/csr/I/pmpaddr28.yaml +++ b/arch/csr/I/pmpaddr28.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr28 long_name: PMP Address 28 address: 0x3CC +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr29.yaml b/arch/csr/I/pmpaddr29.yaml index 7a0a971ad6..ebd9902dcb 100644 --- a/arch/csr/I/pmpaddr29.yaml +++ b/arch/csr/I/pmpaddr29.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr29 long_name: PMP Address 29 address: 0x3CD +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr3.yaml b/arch/csr/I/pmpaddr3.yaml index 7d79c0b926..3e96214a57 100644 --- a/arch/csr/I/pmpaddr3.yaml +++ b/arch/csr/I/pmpaddr3.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr3 long_name: PMP Address 3 address: 0x3B3 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr30.yaml b/arch/csr/I/pmpaddr30.yaml index 0b8481e85d..84aa312fcc 100644 --- a/arch/csr/I/pmpaddr30.yaml +++ b/arch/csr/I/pmpaddr30.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr30 long_name: PMP Address 30 address: 0x3CE +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr31.yaml b/arch/csr/I/pmpaddr31.yaml index cb6889d511..74a63dd8a2 100644 --- a/arch/csr/I/pmpaddr31.yaml +++ b/arch/csr/I/pmpaddr31.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr31 long_name: PMP Address 31 address: 0x3CF +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr32.yaml b/arch/csr/I/pmpaddr32.yaml index ef38ca7aab..9cb24997c4 100644 --- a/arch/csr/I/pmpaddr32.yaml +++ b/arch/csr/I/pmpaddr32.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr32 long_name: PMP Address 32 address: 0x3D0 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr33.yaml b/arch/csr/I/pmpaddr33.yaml index 8bac474921..f8d6c238e7 100644 --- a/arch/csr/I/pmpaddr33.yaml +++ b/arch/csr/I/pmpaddr33.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr33 long_name: PMP Address 33 address: 0x3D1 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr34.yaml b/arch/csr/I/pmpaddr34.yaml index 8c06828a18..602d4e1b60 100644 --- a/arch/csr/I/pmpaddr34.yaml +++ b/arch/csr/I/pmpaddr34.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr34 long_name: PMP Address 34 address: 0x3D2 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr35.yaml b/arch/csr/I/pmpaddr35.yaml index 8cc63fde59..1d4e0abba2 100644 --- a/arch/csr/I/pmpaddr35.yaml +++ b/arch/csr/I/pmpaddr35.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr35 long_name: PMP Address 35 address: 0x3D3 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr36.yaml b/arch/csr/I/pmpaddr36.yaml index 4b22831126..9e3e93c6c8 100644 --- a/arch/csr/I/pmpaddr36.yaml +++ b/arch/csr/I/pmpaddr36.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr36 long_name: PMP Address 36 address: 0x3D4 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr37.yaml b/arch/csr/I/pmpaddr37.yaml index 957132029e..611ee8428a 100644 --- a/arch/csr/I/pmpaddr37.yaml +++ b/arch/csr/I/pmpaddr37.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr37 long_name: PMP Address 37 address: 0x3D5 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr38.yaml b/arch/csr/I/pmpaddr38.yaml index 4979a53a5e..c953bccb70 100644 --- a/arch/csr/I/pmpaddr38.yaml +++ b/arch/csr/I/pmpaddr38.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr38 long_name: PMP Address 38 address: 0x3D6 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr39.yaml b/arch/csr/I/pmpaddr39.yaml index 41340b4953..c78b253a14 100644 --- a/arch/csr/I/pmpaddr39.yaml +++ b/arch/csr/I/pmpaddr39.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr39 long_name: PMP Address 39 address: 0x3D7 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr4.yaml b/arch/csr/I/pmpaddr4.yaml index 0a5d45b7ab..25e407f2d5 100644 --- a/arch/csr/I/pmpaddr4.yaml +++ b/arch/csr/I/pmpaddr4.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr4 long_name: PMP Address 4 address: 0x3B4 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr40.yaml b/arch/csr/I/pmpaddr40.yaml index 21b3cf11fe..359f0ce625 100644 --- a/arch/csr/I/pmpaddr40.yaml +++ b/arch/csr/I/pmpaddr40.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr40 long_name: PMP Address 40 address: 0x3D8 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr41.yaml b/arch/csr/I/pmpaddr41.yaml index 6bb1bafc97..cc856c92a5 100644 --- a/arch/csr/I/pmpaddr41.yaml +++ b/arch/csr/I/pmpaddr41.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr41 long_name: PMP Address 41 address: 0x3D9 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr42.yaml b/arch/csr/I/pmpaddr42.yaml index bdab7845a1..561eabf1b1 100644 --- a/arch/csr/I/pmpaddr42.yaml +++ b/arch/csr/I/pmpaddr42.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr42 long_name: PMP Address 42 address: 0x3DA +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr43.yaml b/arch/csr/I/pmpaddr43.yaml index 91b1812bcf..ce6e03f271 100644 --- a/arch/csr/I/pmpaddr43.yaml +++ b/arch/csr/I/pmpaddr43.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr43 long_name: PMP Address 43 address: 0x3DB +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr44.yaml b/arch/csr/I/pmpaddr44.yaml index 5d0cdfca6f..f5a4f2c419 100644 --- a/arch/csr/I/pmpaddr44.yaml +++ b/arch/csr/I/pmpaddr44.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr44 long_name: PMP Address 44 address: 0x3DC +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr45.yaml b/arch/csr/I/pmpaddr45.yaml index 18e02b28cd..5cda5b7e88 100644 --- a/arch/csr/I/pmpaddr45.yaml +++ b/arch/csr/I/pmpaddr45.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr45 long_name: PMP Address 45 address: 0x3DD +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr46.yaml b/arch/csr/I/pmpaddr46.yaml index 950b7b2b89..78d9edd254 100644 --- a/arch/csr/I/pmpaddr46.yaml +++ b/arch/csr/I/pmpaddr46.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr46 long_name: PMP Address 46 address: 0x3DE +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr47.yaml b/arch/csr/I/pmpaddr47.yaml index fb6a5f4222..4251f90446 100644 --- a/arch/csr/I/pmpaddr47.yaml +++ b/arch/csr/I/pmpaddr47.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr47 long_name: PMP Address 47 address: 0x3DF +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr48.yaml b/arch/csr/I/pmpaddr48.yaml index 9eba2608ad..61fa755574 100644 --- a/arch/csr/I/pmpaddr48.yaml +++ b/arch/csr/I/pmpaddr48.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr48 long_name: PMP Address 48 address: 0x3E0 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr49.yaml b/arch/csr/I/pmpaddr49.yaml index 26cb239966..1685f45198 100644 --- a/arch/csr/I/pmpaddr49.yaml +++ b/arch/csr/I/pmpaddr49.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr49 long_name: PMP Address 49 address: 0x3E1 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr5.yaml b/arch/csr/I/pmpaddr5.yaml index 8a73ce45e6..df64c18ba2 100644 --- a/arch/csr/I/pmpaddr5.yaml +++ b/arch/csr/I/pmpaddr5.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr5 long_name: PMP Address 5 address: 0x3B5 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr50.yaml b/arch/csr/I/pmpaddr50.yaml index 69aff1deca..88d4193b8b 100644 --- a/arch/csr/I/pmpaddr50.yaml +++ b/arch/csr/I/pmpaddr50.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr50 long_name: PMP Address 50 address: 0x3E2 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr51.yaml b/arch/csr/I/pmpaddr51.yaml index d5d6464f49..17c496f698 100644 --- a/arch/csr/I/pmpaddr51.yaml +++ b/arch/csr/I/pmpaddr51.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr51 long_name: PMP Address 51 address: 0x3E3 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr52.yaml b/arch/csr/I/pmpaddr52.yaml index 49ace51ac0..51571410ea 100644 --- a/arch/csr/I/pmpaddr52.yaml +++ b/arch/csr/I/pmpaddr52.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr52 long_name: PMP Address 52 address: 0x3E4 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr53.yaml b/arch/csr/I/pmpaddr53.yaml index 222efed3b3..95bf8b6856 100644 --- a/arch/csr/I/pmpaddr53.yaml +++ b/arch/csr/I/pmpaddr53.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr53 long_name: PMP Address 53 address: 0x3E5 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr54.yaml b/arch/csr/I/pmpaddr54.yaml index 6f7e7677d5..4fd59184b8 100644 --- a/arch/csr/I/pmpaddr54.yaml +++ b/arch/csr/I/pmpaddr54.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr54 long_name: PMP Address 54 address: 0x3E6 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr55.yaml b/arch/csr/I/pmpaddr55.yaml index 0f9d5a5063..02d42b187b 100644 --- a/arch/csr/I/pmpaddr55.yaml +++ b/arch/csr/I/pmpaddr55.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr55 long_name: PMP Address 55 address: 0x3E7 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr56.yaml b/arch/csr/I/pmpaddr56.yaml index 4ca1bd3e55..61a7d79c37 100644 --- a/arch/csr/I/pmpaddr56.yaml +++ b/arch/csr/I/pmpaddr56.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr56 long_name: PMP Address 56 address: 0x3E8 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr57.yaml b/arch/csr/I/pmpaddr57.yaml index bde0f738bf..3161a4f60f 100644 --- a/arch/csr/I/pmpaddr57.yaml +++ b/arch/csr/I/pmpaddr57.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr57 long_name: PMP Address 57 address: 0x3E9 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr58.yaml b/arch/csr/I/pmpaddr58.yaml index 6fa1aa32e5..f7809698e9 100644 --- a/arch/csr/I/pmpaddr58.yaml +++ b/arch/csr/I/pmpaddr58.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr58 long_name: PMP Address 58 address: 0x3EA +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr59.yaml b/arch/csr/I/pmpaddr59.yaml index 794787cfd1..1392abc21d 100644 --- a/arch/csr/I/pmpaddr59.yaml +++ b/arch/csr/I/pmpaddr59.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr59 long_name: PMP Address 59 address: 0x3EB +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr6.yaml b/arch/csr/I/pmpaddr6.yaml index 28733415e1..ed81dba357 100644 --- a/arch/csr/I/pmpaddr6.yaml +++ b/arch/csr/I/pmpaddr6.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr6 long_name: PMP Address 6 address: 0x3B6 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr60.yaml b/arch/csr/I/pmpaddr60.yaml index 2932496683..021bd23a7d 100644 --- a/arch/csr/I/pmpaddr60.yaml +++ b/arch/csr/I/pmpaddr60.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr60 long_name: PMP Address 60 address: 0x3EC +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr61.yaml b/arch/csr/I/pmpaddr61.yaml index 9570264235..ca3ed5cabf 100644 --- a/arch/csr/I/pmpaddr61.yaml +++ b/arch/csr/I/pmpaddr61.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr61 long_name: PMP Address 61 address: 0x3ED +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr62.yaml b/arch/csr/I/pmpaddr62.yaml index 0ae068f5d1..961bd3ad06 100644 --- a/arch/csr/I/pmpaddr62.yaml +++ b/arch/csr/I/pmpaddr62.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr62 long_name: PMP Address 62 address: 0x3EE +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr63.yaml b/arch/csr/I/pmpaddr63.yaml index d448de1db1..8837c0af8c 100644 --- a/arch/csr/I/pmpaddr63.yaml +++ b/arch/csr/I/pmpaddr63.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr63 long_name: PMP Address 63 address: 0x3EF +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr7.yaml b/arch/csr/I/pmpaddr7.yaml index 710c597570..c9774eba35 100644 --- a/arch/csr/I/pmpaddr7.yaml +++ b/arch/csr/I/pmpaddr7.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr7 long_name: PMP Address 7 address: 0x3B7 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr8.yaml b/arch/csr/I/pmpaddr8.yaml index e6807b1669..c589f7cfdc 100644 --- a/arch/csr/I/pmpaddr8.yaml +++ b/arch/csr/I/pmpaddr8.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr8 long_name: PMP Address 8 address: 0x3B8 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr9.yaml b/arch/csr/I/pmpaddr9.yaml index 5cefea0afd..0510c298be 100644 --- a/arch/csr/I/pmpaddr9.yaml +++ b/arch/csr/I/pmpaddr9.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr9 long_name: PMP Address 9 address: 0x3B9 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpcfg0.yaml b/arch/csr/I/pmpcfg0.yaml index 2630c3ba38..4d94e07d16 100644 --- a/arch/csr/I/pmpcfg0.yaml +++ b/arch/csr/I/pmpcfg0.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpcfg0 long_name: PMP Configuration Register 0 address: 0x3A0 +writeable: true priv_mode: M length: MXLEN description: PMP entry configuration diff --git a/arch/csr/I/pmpcfg1.yaml b/arch/csr/I/pmpcfg1.yaml index 317183e198..1a19e04104 100644 --- a/arch/csr/I/pmpcfg1.yaml +++ b/arch/csr/I/pmpcfg1.yaml @@ -8,6 +8,7 @@ name: pmpcfg1 base: 32 # odd numbered pmpcfg registers do not exist in RV64 long_name: PMP Configuration Register 1 address: 0x3A1 +writeable: true priv_mode: M length: MXLEN description: PMP entry configuration diff --git a/arch/csr/I/pmpcfg10.yaml b/arch/csr/I/pmpcfg10.yaml index b0a9f613ff..0731ecf874 100644 --- a/arch/csr/I/pmpcfg10.yaml +++ b/arch/csr/I/pmpcfg10.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpcfg10 long_name: PMP Configuration Register 10 address: 0x3AA +writeable: true priv_mode: M length: MXLEN description: PMP entry configuration diff --git a/arch/csr/I/pmpcfg11.yaml b/arch/csr/I/pmpcfg11.yaml index c865e0d5e6..422208ef11 100644 --- a/arch/csr/I/pmpcfg11.yaml +++ b/arch/csr/I/pmpcfg11.yaml @@ -8,6 +8,7 @@ name: pmpcfg11 base: 32 # odd numbered pmpcfg registers do not exist in RV64 long_name: PMP Configuration Register 11 address: 0x3AB +writeable: true priv_mode: M length: MXLEN description: PMP entry configuration diff --git a/arch/csr/I/pmpcfg12.yaml b/arch/csr/I/pmpcfg12.yaml index 7943b623ab..407a3573e5 100644 --- a/arch/csr/I/pmpcfg12.yaml +++ b/arch/csr/I/pmpcfg12.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpcfg12 long_name: PMP Configuration Register 12 address: 0x3AC +writeable: true priv_mode: M length: MXLEN description: PMP entry configuration diff --git a/arch/csr/I/pmpcfg13.yaml b/arch/csr/I/pmpcfg13.yaml index 770fa37e19..f000e9258a 100644 --- a/arch/csr/I/pmpcfg13.yaml +++ b/arch/csr/I/pmpcfg13.yaml @@ -8,6 +8,7 @@ name: pmpcfg13 base: 32 # odd numbered pmpcfg registers do not exist in RV64 long_name: PMP Configuration Register 13 address: 0x3AD +writeable: true priv_mode: M length: MXLEN description: PMP entry configuration diff --git a/arch/csr/I/pmpcfg14.yaml b/arch/csr/I/pmpcfg14.yaml index 062513daa8..30242a1c27 100644 --- a/arch/csr/I/pmpcfg14.yaml +++ b/arch/csr/I/pmpcfg14.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpcfg14 long_name: PMP Configuration Register 14 address: 0x3AE +writeable: true priv_mode: M length: MXLEN description: PMP entry configuration diff --git a/arch/csr/I/pmpcfg15.yaml b/arch/csr/I/pmpcfg15.yaml index 942828b3a1..2f8b457738 100644 --- a/arch/csr/I/pmpcfg15.yaml +++ b/arch/csr/I/pmpcfg15.yaml @@ -8,6 +8,7 @@ name: pmpcfg15 base: 32 # odd numbered pmpcfg registers do not exist in RV64 long_name: PMP Configuration Register 15 address: 0x3AF +writeable: true priv_mode: M length: MXLEN description: PMP entry configuration diff --git a/arch/csr/I/pmpcfg2.yaml b/arch/csr/I/pmpcfg2.yaml index 771dceccbe..9256cb542b 100644 --- a/arch/csr/I/pmpcfg2.yaml +++ b/arch/csr/I/pmpcfg2.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpcfg2 long_name: PMP Configuration Register 2 address: 0x3A2 +writeable: true priv_mode: M length: MXLEN description: PMP entry configuration diff --git a/arch/csr/I/pmpcfg3.yaml b/arch/csr/I/pmpcfg3.yaml index 7c2ab8989f..1faafdbdb6 100644 --- a/arch/csr/I/pmpcfg3.yaml +++ b/arch/csr/I/pmpcfg3.yaml @@ -8,6 +8,7 @@ name: pmpcfg3 base: 32 # odd numbered pmpcfg registers do not exist in RV64 long_name: PMP Configuration Register 3 address: 0x3A3 +writeable: true priv_mode: M length: MXLEN description: PMP entry configuration diff --git a/arch/csr/I/pmpcfg4.yaml b/arch/csr/I/pmpcfg4.yaml index 7079c73d6d..c27eccf91c 100644 --- a/arch/csr/I/pmpcfg4.yaml +++ b/arch/csr/I/pmpcfg4.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpcfg4 long_name: PMP Configuration Register 4 address: 0x3A4 +writeable: true priv_mode: M length: MXLEN description: PMP entry configuration diff --git a/arch/csr/I/pmpcfg5.yaml b/arch/csr/I/pmpcfg5.yaml index abd86000c7..4695225a77 100644 --- a/arch/csr/I/pmpcfg5.yaml +++ b/arch/csr/I/pmpcfg5.yaml @@ -8,6 +8,7 @@ name: pmpcfg5 base: 32 # odd numbered pmpcfg registers do not exist in RV64 long_name: PMP Configuration Register 5 address: 0x3A5 +writeable: true priv_mode: M length: MXLEN description: PMP entry configuration diff --git a/arch/csr/I/pmpcfg6.yaml b/arch/csr/I/pmpcfg6.yaml index 74690b12cf..d252e01490 100644 --- a/arch/csr/I/pmpcfg6.yaml +++ b/arch/csr/I/pmpcfg6.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpcfg6 long_name: PMP Configuration Register 6 address: 0x3A6 +writeable: true priv_mode: M length: MXLEN description: PMP entry configuration diff --git a/arch/csr/I/pmpcfg7.yaml b/arch/csr/I/pmpcfg7.yaml index fcfbd78e37..9c7fa84349 100644 --- a/arch/csr/I/pmpcfg7.yaml +++ b/arch/csr/I/pmpcfg7.yaml @@ -8,6 +8,7 @@ name: pmpcfg7 base: 32 # odd numbered pmpcfg registers do not exist in RV64 long_name: PMP Configuration Register 7 address: 0x3A7 +writeable: true priv_mode: M length: MXLEN description: PMP entry configuration diff --git a/arch/csr/I/pmpcfg8.yaml b/arch/csr/I/pmpcfg8.yaml index 79b006f5e9..c35ed68b9b 100644 --- a/arch/csr/I/pmpcfg8.yaml +++ b/arch/csr/I/pmpcfg8.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpcfg8 long_name: PMP Configuration Register 8 address: 0x3A8 +writeable: true priv_mode: M length: MXLEN description: PMP entry configuration diff --git a/arch/csr/I/pmpcfg9.yaml b/arch/csr/I/pmpcfg9.yaml index ec8211763d..902d358ba9 100644 --- a/arch/csr/I/pmpcfg9.yaml +++ b/arch/csr/I/pmpcfg9.yaml @@ -8,6 +8,7 @@ name: pmpcfg9 base: 32 # odd numbered pmpcfg registers do not exist in RV64 long_name: PMP Configuration Register 9 address: 0x3A9 +writeable: true priv_mode: M length: MXLEN description: PMP entry configuration diff --git a/arch/csr/S/scounteren.yaml b/arch/csr/S/scounteren.yaml index 1079620219..7548c61d15 100644 --- a/arch/csr/S/scounteren.yaml +++ b/arch/csr/S/scounteren.yaml @@ -6,6 +6,7 @@ kind: csr name: scounteren long_name: Supervisor Counter Enable address: 0x106 +writeable: true priv_mode: S length: 32 description: | diff --git a/arch/csr/Smrnmi/mncause.yaml b/arch/csr/Smrnmi/mncause.yaml index fa0ad9cd63..d944135118 100644 --- a/arch/csr/Smrnmi/mncause.yaml +++ b/arch/csr/Smrnmi/mncause.yaml @@ -5,6 +5,7 @@ kind: csr name: mncause long_name: Resumable NMI cause address: 0x742 +writeable: true priv_mode: M length: MXLEN definedBy: Smrnmi diff --git a/arch/csr/Smrnmi/mnepc.yaml b/arch/csr/Smrnmi/mnepc.yaml index e249aa441b..5fefa12361 100644 --- a/arch/csr/Smrnmi/mnepc.yaml +++ b/arch/csr/Smrnmi/mnepc.yaml @@ -5,6 +5,7 @@ kind: csr name: mnepc long_name: Machine Exception Program Counter address: 0x741 +writeable: true priv_mode: M length: MXLEN description: | diff --git a/arch/csr/Smrnmi/mnscratch.yaml b/arch/csr/Smrnmi/mnscratch.yaml index b3d89c52b2..1cceddef16 100644 --- a/arch/csr/Smrnmi/mnscratch.yaml +++ b/arch/csr/Smrnmi/mnscratch.yaml @@ -5,9 +5,12 @@ kind: csr name: mnscratch long_name: Machine Scratch Register address: 0x740 +writeable: true priv_mode: M length: MXLEN -description: Scratch register for software use in NMI / double trap. Bits are not interpreted by hardware. +description: + Scratch register for software use in NMI / double trap. Bits are not + interpreted by hardware. definedBy: Smrnmi fields: SCRATCH: diff --git a/arch/csr/Smrnmi/mnstatus.yaml b/arch/csr/Smrnmi/mnstatus.yaml index 1ab64b3967..b79a2ec298 100644 --- a/arch/csr/Smrnmi/mnstatus.yaml +++ b/arch/csr/Smrnmi/mnstatus.yaml @@ -5,11 +5,14 @@ kind: csr name: mnstatus long_name: Machine NMI Status address: 0x744 +writeable: true priv_mode: M # length is MXLEN-bit length: MXLEN -description: The mnstatus register tracks and controls the hart's current NMI operating state. +description: + The mnstatus register tracks and controls the hart's current NMI operating + state. definedBy: Smrnmi fields: MNPP: diff --git a/arch/csr/Zicntr/mcountinhibit.yaml b/arch/csr/Zicntr/mcountinhibit.yaml index 1a06640b7e..591396f95f 100644 --- a/arch/csr/Zicntr/mcountinhibit.yaml +++ b/arch/csr/Zicntr/mcountinhibit.yaml @@ -6,6 +6,7 @@ kind: csr name: mcountinhibit long_name: Machine Counter Inhibit address: 0x320 +writeable: true priv_mode: M length: 32 description: | diff --git a/arch/csr/Zihpm/hpmcounter10.yaml b/arch/csr/Zihpm/hpmcounter10.yaml index 40b6fbdbcc..37d084dd35 100644 --- a/arch/csr/Zihpm/hpmcounter10.yaml +++ b/arch/csr/Zihpm/hpmcounter10.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter10 long_name: User-mode Hardware Performance Counter 7 address: 0xC0A +writeable: false description: | Alias for M-mode CSR `mhpmcounter10`. diff --git a/arch/csr/Zihpm/hpmcounter10h.yaml b/arch/csr/Zihpm/hpmcounter10h.yaml index b903ef0217..623ee258aa 100644 --- a/arch/csr/Zihpm/hpmcounter10h.yaml +++ b/arch/csr/Zihpm/hpmcounter10h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter10h long_name: User-mode Hardware Performance Counter 7, high half address: 0xC8A +writeable: false description: | Alias for M-mode CSR `mhpmcounter10h`. diff --git a/arch/csr/Zihpm/hpmcounter11.yaml b/arch/csr/Zihpm/hpmcounter11.yaml index 1217cc8161..d3242a03ff 100644 --- a/arch/csr/Zihpm/hpmcounter11.yaml +++ b/arch/csr/Zihpm/hpmcounter11.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter11 long_name: User-mode Hardware Performance Counter 8 address: 0xC0B +writeable: false description: | Alias for M-mode CSR `mhpmcounter11`. diff --git a/arch/csr/Zihpm/hpmcounter11h.yaml b/arch/csr/Zihpm/hpmcounter11h.yaml index 24c3187660..40b24be791 100644 --- a/arch/csr/Zihpm/hpmcounter11h.yaml +++ b/arch/csr/Zihpm/hpmcounter11h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter11h long_name: User-mode Hardware Performance Counter 8, high half address: 0xC8B +writeable: false description: | Alias for M-mode CSR `mhpmcounter11h`. diff --git a/arch/csr/Zihpm/hpmcounter12.yaml b/arch/csr/Zihpm/hpmcounter12.yaml index f8f296a581..29c1cc3d60 100644 --- a/arch/csr/Zihpm/hpmcounter12.yaml +++ b/arch/csr/Zihpm/hpmcounter12.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter12 long_name: User-mode Hardware Performance Counter 9 address: 0xC0C +writeable: false description: | Alias for M-mode CSR `mhpmcounter12`. diff --git a/arch/csr/Zihpm/hpmcounter12h.yaml b/arch/csr/Zihpm/hpmcounter12h.yaml index c0c468c19d..ea0b6465ef 100644 --- a/arch/csr/Zihpm/hpmcounter12h.yaml +++ b/arch/csr/Zihpm/hpmcounter12h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter12h long_name: User-mode Hardware Performance Counter 9, high half address: 0xC8C +writeable: false description: | Alias for M-mode CSR `mhpmcounter12h`. diff --git a/arch/csr/Zihpm/hpmcounter13.yaml b/arch/csr/Zihpm/hpmcounter13.yaml index 8713f1e88b..62fb683501 100644 --- a/arch/csr/Zihpm/hpmcounter13.yaml +++ b/arch/csr/Zihpm/hpmcounter13.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter13 long_name: User-mode Hardware Performance Counter 10 address: 0xC0D +writeable: false description: | Alias for M-mode CSR `mhpmcounter13`. diff --git a/arch/csr/Zihpm/hpmcounter13h.yaml b/arch/csr/Zihpm/hpmcounter13h.yaml index cd055f9404..5eafe2b6df 100644 --- a/arch/csr/Zihpm/hpmcounter13h.yaml +++ b/arch/csr/Zihpm/hpmcounter13h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter13h long_name: User-mode Hardware Performance Counter 10, high half address: 0xC8D +writeable: false description: | Alias for M-mode CSR `mhpmcounter13h`. diff --git a/arch/csr/Zihpm/hpmcounter14.yaml b/arch/csr/Zihpm/hpmcounter14.yaml index 47303cbb4e..ebc3e0b49f 100644 --- a/arch/csr/Zihpm/hpmcounter14.yaml +++ b/arch/csr/Zihpm/hpmcounter14.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter14 long_name: User-mode Hardware Performance Counter 11 address: 0xC0E +writeable: false description: | Alias for M-mode CSR `mhpmcounter14`. diff --git a/arch/csr/Zihpm/hpmcounter14h.yaml b/arch/csr/Zihpm/hpmcounter14h.yaml index 1a4290b354..ce24e878da 100644 --- a/arch/csr/Zihpm/hpmcounter14h.yaml +++ b/arch/csr/Zihpm/hpmcounter14h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter14h long_name: User-mode Hardware Performance Counter 11, high half address: 0xC8E +writeable: false description: | Alias for M-mode CSR `mhpmcounter14h`. diff --git a/arch/csr/Zihpm/hpmcounter15.yaml b/arch/csr/Zihpm/hpmcounter15.yaml index a18732b248..13bcd9b8e1 100644 --- a/arch/csr/Zihpm/hpmcounter15.yaml +++ b/arch/csr/Zihpm/hpmcounter15.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter15 long_name: User-mode Hardware Performance Counter 12 address: 0xC0F +writeable: false description: | Alias for M-mode CSR `mhpmcounter15`. diff --git a/arch/csr/Zihpm/hpmcounter15h.yaml b/arch/csr/Zihpm/hpmcounter15h.yaml index 8f7a0fb94e..34220b9a98 100644 --- a/arch/csr/Zihpm/hpmcounter15h.yaml +++ b/arch/csr/Zihpm/hpmcounter15h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter15h long_name: User-mode Hardware Performance Counter 12, high half address: 0xC8F +writeable: false description: | Alias for M-mode CSR `mhpmcounter15h`. diff --git a/arch/csr/Zihpm/hpmcounter16.yaml b/arch/csr/Zihpm/hpmcounter16.yaml index 61e454230c..748b70a0b1 100644 --- a/arch/csr/Zihpm/hpmcounter16.yaml +++ b/arch/csr/Zihpm/hpmcounter16.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter16 long_name: User-mode Hardware Performance Counter 13 address: 0xC10 +writeable: false description: | Alias for M-mode CSR `mhpmcounter16`. diff --git a/arch/csr/Zihpm/hpmcounter16h.yaml b/arch/csr/Zihpm/hpmcounter16h.yaml index b3d05236b9..6f996123f1 100644 --- a/arch/csr/Zihpm/hpmcounter16h.yaml +++ b/arch/csr/Zihpm/hpmcounter16h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter16h long_name: User-mode Hardware Performance Counter 13, high half address: 0xC90 +writeable: false description: | Alias for M-mode CSR `mhpmcounter16h`. diff --git a/arch/csr/Zihpm/hpmcounter17.yaml b/arch/csr/Zihpm/hpmcounter17.yaml index 2d130ca5d2..3cffcea98f 100644 --- a/arch/csr/Zihpm/hpmcounter17.yaml +++ b/arch/csr/Zihpm/hpmcounter17.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter17 long_name: User-mode Hardware Performance Counter 14 address: 0xC11 +writeable: false description: | Alias for M-mode CSR `mhpmcounter17`. diff --git a/arch/csr/Zihpm/hpmcounter17h.yaml b/arch/csr/Zihpm/hpmcounter17h.yaml index 0cd5f864e3..5faf5fb30f 100644 --- a/arch/csr/Zihpm/hpmcounter17h.yaml +++ b/arch/csr/Zihpm/hpmcounter17h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter17h long_name: User-mode Hardware Performance Counter 14, high half address: 0xC91 +writeable: false description: | Alias for M-mode CSR `mhpmcounter17h`. diff --git a/arch/csr/Zihpm/hpmcounter18.yaml b/arch/csr/Zihpm/hpmcounter18.yaml index b115107009..f1928ae231 100644 --- a/arch/csr/Zihpm/hpmcounter18.yaml +++ b/arch/csr/Zihpm/hpmcounter18.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter18 long_name: User-mode Hardware Performance Counter 15 address: 0xC12 +writeable: false description: | Alias for M-mode CSR `mhpmcounter18`. diff --git a/arch/csr/Zihpm/hpmcounter18h.yaml b/arch/csr/Zihpm/hpmcounter18h.yaml index d45aa624b9..ea1721f4c4 100644 --- a/arch/csr/Zihpm/hpmcounter18h.yaml +++ b/arch/csr/Zihpm/hpmcounter18h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter18h long_name: User-mode Hardware Performance Counter 15, high half address: 0xC92 +writeable: false description: | Alias for M-mode CSR `mhpmcounter18h`. diff --git a/arch/csr/Zihpm/hpmcounter19.yaml b/arch/csr/Zihpm/hpmcounter19.yaml index 12a99ea82e..86858b8aa6 100644 --- a/arch/csr/Zihpm/hpmcounter19.yaml +++ b/arch/csr/Zihpm/hpmcounter19.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter19 long_name: User-mode Hardware Performance Counter 16 address: 0xC13 +writeable: false description: | Alias for M-mode CSR `mhpmcounter19`. diff --git a/arch/csr/Zihpm/hpmcounter19h.yaml b/arch/csr/Zihpm/hpmcounter19h.yaml index f5bff3f22d..8a23619f57 100644 --- a/arch/csr/Zihpm/hpmcounter19h.yaml +++ b/arch/csr/Zihpm/hpmcounter19h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter19h long_name: User-mode Hardware Performance Counter 16, high half address: 0xC93 +writeable: false description: | Alias for M-mode CSR `mhpmcounter19h`. diff --git a/arch/csr/Zihpm/hpmcounter20.yaml b/arch/csr/Zihpm/hpmcounter20.yaml index a8a406d7b1..b3b588d6ed 100644 --- a/arch/csr/Zihpm/hpmcounter20.yaml +++ b/arch/csr/Zihpm/hpmcounter20.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter20 long_name: User-mode Hardware Performance Counter 17 address: 0xC14 +writeable: false description: | Alias for M-mode CSR `mhpmcounter20`. diff --git a/arch/csr/Zihpm/hpmcounter20h.yaml b/arch/csr/Zihpm/hpmcounter20h.yaml index 6734e2d79b..db45f652a6 100644 --- a/arch/csr/Zihpm/hpmcounter20h.yaml +++ b/arch/csr/Zihpm/hpmcounter20h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter20h long_name: User-mode Hardware Performance Counter 17, high half address: 0xC94 +writeable: false description: | Alias for M-mode CSR `mhpmcounter20h`. diff --git a/arch/csr/Zihpm/hpmcounter21.yaml b/arch/csr/Zihpm/hpmcounter21.yaml index 3ce7cb84a2..9c29fd1fd2 100644 --- a/arch/csr/Zihpm/hpmcounter21.yaml +++ b/arch/csr/Zihpm/hpmcounter21.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter21 long_name: User-mode Hardware Performance Counter 18 address: 0xC15 +writeable: false description: | Alias for M-mode CSR `mhpmcounter21`. diff --git a/arch/csr/Zihpm/hpmcounter21h.yaml b/arch/csr/Zihpm/hpmcounter21h.yaml index 12012a7bca..bc30fbf87d 100644 --- a/arch/csr/Zihpm/hpmcounter21h.yaml +++ b/arch/csr/Zihpm/hpmcounter21h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter21h long_name: User-mode Hardware Performance Counter 18, high half address: 0xC95 +writeable: false description: | Alias for M-mode CSR `mhpmcounter21h`. diff --git a/arch/csr/Zihpm/hpmcounter22.yaml b/arch/csr/Zihpm/hpmcounter22.yaml index 7943981fdd..e8021fee46 100644 --- a/arch/csr/Zihpm/hpmcounter22.yaml +++ b/arch/csr/Zihpm/hpmcounter22.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter22 long_name: User-mode Hardware Performance Counter 19 address: 0xC16 +writeable: false description: | Alias for M-mode CSR `mhpmcounter22`. diff --git a/arch/csr/Zihpm/hpmcounter22h.yaml b/arch/csr/Zihpm/hpmcounter22h.yaml index 994240044e..1a0757e946 100644 --- a/arch/csr/Zihpm/hpmcounter22h.yaml +++ b/arch/csr/Zihpm/hpmcounter22h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter22h long_name: User-mode Hardware Performance Counter 19, high half address: 0xC96 +writeable: false description: | Alias for M-mode CSR `mhpmcounter22h`. diff --git a/arch/csr/Zihpm/hpmcounter23.yaml b/arch/csr/Zihpm/hpmcounter23.yaml index fc22bd72a5..c6718ff464 100644 --- a/arch/csr/Zihpm/hpmcounter23.yaml +++ b/arch/csr/Zihpm/hpmcounter23.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter23 long_name: User-mode Hardware Performance Counter 20 address: 0xC17 +writeable: false description: | Alias for M-mode CSR `mhpmcounter23`. diff --git a/arch/csr/Zihpm/hpmcounter23h.yaml b/arch/csr/Zihpm/hpmcounter23h.yaml index ecb16e6844..9744f72931 100644 --- a/arch/csr/Zihpm/hpmcounter23h.yaml +++ b/arch/csr/Zihpm/hpmcounter23h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter23h long_name: User-mode Hardware Performance Counter 20, high half address: 0xC97 +writeable: false description: | Alias for M-mode CSR `mhpmcounter23h`. diff --git a/arch/csr/Zihpm/hpmcounter24.yaml b/arch/csr/Zihpm/hpmcounter24.yaml index 4f392aaa5e..414f4e11d5 100644 --- a/arch/csr/Zihpm/hpmcounter24.yaml +++ b/arch/csr/Zihpm/hpmcounter24.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter24 long_name: User-mode Hardware Performance Counter 21 address: 0xC18 +writeable: false description: | Alias for M-mode CSR `mhpmcounter24`. diff --git a/arch/csr/Zihpm/hpmcounter24h.yaml b/arch/csr/Zihpm/hpmcounter24h.yaml index ffe667a456..e3e55a9dc5 100644 --- a/arch/csr/Zihpm/hpmcounter24h.yaml +++ b/arch/csr/Zihpm/hpmcounter24h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter24h long_name: User-mode Hardware Performance Counter 21, high half address: 0xC98 +writeable: false description: | Alias for M-mode CSR `mhpmcounter24h`. diff --git a/arch/csr/Zihpm/hpmcounter25.yaml b/arch/csr/Zihpm/hpmcounter25.yaml index 3bcedc674d..5d37bceab2 100644 --- a/arch/csr/Zihpm/hpmcounter25.yaml +++ b/arch/csr/Zihpm/hpmcounter25.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter25 long_name: User-mode Hardware Performance Counter 22 address: 0xC19 +writeable: false description: | Alias for M-mode CSR `mhpmcounter25`. diff --git a/arch/csr/Zihpm/hpmcounter25h.yaml b/arch/csr/Zihpm/hpmcounter25h.yaml index f4b3286a4f..ec7c5092d1 100644 --- a/arch/csr/Zihpm/hpmcounter25h.yaml +++ b/arch/csr/Zihpm/hpmcounter25h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter25h long_name: User-mode Hardware Performance Counter 22, high half address: 0xC99 +writeable: false description: | Alias for M-mode CSR `mhpmcounter25h`. diff --git a/arch/csr/Zihpm/hpmcounter26.yaml b/arch/csr/Zihpm/hpmcounter26.yaml index 1dee5e0c76..b6248bdb54 100644 --- a/arch/csr/Zihpm/hpmcounter26.yaml +++ b/arch/csr/Zihpm/hpmcounter26.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter26 long_name: User-mode Hardware Performance Counter 23 address: 0xC1A +writeable: false description: | Alias for M-mode CSR `mhpmcounter26`. diff --git a/arch/csr/Zihpm/hpmcounter26h.yaml b/arch/csr/Zihpm/hpmcounter26h.yaml index 995483b4fe..d17fa68f13 100644 --- a/arch/csr/Zihpm/hpmcounter26h.yaml +++ b/arch/csr/Zihpm/hpmcounter26h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter26h long_name: User-mode Hardware Performance Counter 23, high half address: 0xC9A +writeable: false description: | Alias for M-mode CSR `mhpmcounter26h`. diff --git a/arch/csr/Zihpm/hpmcounter27.yaml b/arch/csr/Zihpm/hpmcounter27.yaml index 694b4ee993..874827ee2d 100644 --- a/arch/csr/Zihpm/hpmcounter27.yaml +++ b/arch/csr/Zihpm/hpmcounter27.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter27 long_name: User-mode Hardware Performance Counter 24 address: 0xC1B +writeable: false description: | Alias for M-mode CSR `mhpmcounter27`. diff --git a/arch/csr/Zihpm/hpmcounter27h.yaml b/arch/csr/Zihpm/hpmcounter27h.yaml index 8e17ad1758..912022fec9 100644 --- a/arch/csr/Zihpm/hpmcounter27h.yaml +++ b/arch/csr/Zihpm/hpmcounter27h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter27h long_name: User-mode Hardware Performance Counter 24, high half address: 0xC9B +writeable: false description: | Alias for M-mode CSR `mhpmcounter27h`. diff --git a/arch/csr/Zihpm/hpmcounter28.yaml b/arch/csr/Zihpm/hpmcounter28.yaml index be77b1867d..904ed48f58 100644 --- a/arch/csr/Zihpm/hpmcounter28.yaml +++ b/arch/csr/Zihpm/hpmcounter28.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter28 long_name: User-mode Hardware Performance Counter 25 address: 0xC1C +writeable: false description: | Alias for M-mode CSR `mhpmcounter28`. diff --git a/arch/csr/Zihpm/hpmcounter28h.yaml b/arch/csr/Zihpm/hpmcounter28h.yaml index 9a1e7714f3..a0e2b375ac 100644 --- a/arch/csr/Zihpm/hpmcounter28h.yaml +++ b/arch/csr/Zihpm/hpmcounter28h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter28h long_name: User-mode Hardware Performance Counter 25, high half address: 0xC9C +writeable: false description: | Alias for M-mode CSR `mhpmcounter28h`. diff --git a/arch/csr/Zihpm/hpmcounter29.yaml b/arch/csr/Zihpm/hpmcounter29.yaml index df27482266..d8aa7c1e61 100644 --- a/arch/csr/Zihpm/hpmcounter29.yaml +++ b/arch/csr/Zihpm/hpmcounter29.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter29 long_name: User-mode Hardware Performance Counter 26 address: 0xC1D +writeable: false description: | Alias for M-mode CSR `mhpmcounter29`. diff --git a/arch/csr/Zihpm/hpmcounter29h.yaml b/arch/csr/Zihpm/hpmcounter29h.yaml index e3fd8e6a2f..67b6530152 100644 --- a/arch/csr/Zihpm/hpmcounter29h.yaml +++ b/arch/csr/Zihpm/hpmcounter29h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter29h long_name: User-mode Hardware Performance Counter 26, high half address: 0xC9D +writeable: false description: | Alias for M-mode CSR `mhpmcounter29h`. diff --git a/arch/csr/Zihpm/hpmcounter3.yaml b/arch/csr/Zihpm/hpmcounter3.yaml index 92c2bea3d8..ad81f77396 100644 --- a/arch/csr/Zihpm/hpmcounter3.yaml +++ b/arch/csr/Zihpm/hpmcounter3.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter3 long_name: User-mode Hardware Performance Counter 0 address: 0xC03 +writeable: false description: | Alias for M-mode CSR `mhpmcounter3`. diff --git a/arch/csr/Zihpm/hpmcounter30.yaml b/arch/csr/Zihpm/hpmcounter30.yaml index 7428dbb693..14e0f7c176 100644 --- a/arch/csr/Zihpm/hpmcounter30.yaml +++ b/arch/csr/Zihpm/hpmcounter30.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter30 long_name: User-mode Hardware Performance Counter 27 address: 0xC1E +writeable: false description: | Alias for M-mode CSR `mhpmcounter30`. diff --git a/arch/csr/Zihpm/hpmcounter30h.yaml b/arch/csr/Zihpm/hpmcounter30h.yaml index 08bc8149a7..76e3c0b4a8 100644 --- a/arch/csr/Zihpm/hpmcounter30h.yaml +++ b/arch/csr/Zihpm/hpmcounter30h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter30h long_name: User-mode Hardware Performance Counter 27, high half address: 0xC9E +writeable: false description: | Alias for M-mode CSR `mhpmcounter30h`. diff --git a/arch/csr/Zihpm/hpmcounter31.yaml b/arch/csr/Zihpm/hpmcounter31.yaml index 77f88b79f1..442ab2eaec 100644 --- a/arch/csr/Zihpm/hpmcounter31.yaml +++ b/arch/csr/Zihpm/hpmcounter31.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter31 long_name: User-mode Hardware Performance Counter 28 address: 0xC1F +writeable: false description: | Alias for M-mode CSR `mhpmcounter31`. diff --git a/arch/csr/Zihpm/hpmcounter31h.yaml b/arch/csr/Zihpm/hpmcounter31h.yaml index 02f8f77b23..e581c66448 100644 --- a/arch/csr/Zihpm/hpmcounter31h.yaml +++ b/arch/csr/Zihpm/hpmcounter31h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter31h long_name: User-mode Hardware Performance Counter 28, high half address: 0xC9F +writeable: false description: | Alias for M-mode CSR `mhpmcounter31h`. diff --git a/arch/csr/Zihpm/hpmcounter3h.yaml b/arch/csr/Zihpm/hpmcounter3h.yaml index 2c49c0fe4c..f66931bd2e 100644 --- a/arch/csr/Zihpm/hpmcounter3h.yaml +++ b/arch/csr/Zihpm/hpmcounter3h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter3h long_name: User-mode Hardware Performance Counter 0, high half address: 0xC83 +writeable: false description: | Alias for M-mode CSR `mhpmcounter3h`. diff --git a/arch/csr/Zihpm/hpmcounter4.yaml b/arch/csr/Zihpm/hpmcounter4.yaml index e453b1739b..6d60345a48 100644 --- a/arch/csr/Zihpm/hpmcounter4.yaml +++ b/arch/csr/Zihpm/hpmcounter4.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter4 long_name: User-mode Hardware Performance Counter 1 address: 0xC04 +writeable: false description: | Alias for M-mode CSR `mhpmcounter4`. diff --git a/arch/csr/Zihpm/hpmcounter4h.yaml b/arch/csr/Zihpm/hpmcounter4h.yaml index ac6a575ccc..e922e73588 100644 --- a/arch/csr/Zihpm/hpmcounter4h.yaml +++ b/arch/csr/Zihpm/hpmcounter4h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter4h long_name: User-mode Hardware Performance Counter 1, high half address: 0xC84 +writeable: false description: | Alias for M-mode CSR `mhpmcounter4h`. diff --git a/arch/csr/Zihpm/hpmcounter5.yaml b/arch/csr/Zihpm/hpmcounter5.yaml index 6e9e0c801a..ad06be019d 100644 --- a/arch/csr/Zihpm/hpmcounter5.yaml +++ b/arch/csr/Zihpm/hpmcounter5.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter5 long_name: User-mode Hardware Performance Counter 2 address: 0xC05 +writeable: false description: | Alias for M-mode CSR `mhpmcounter5`. diff --git a/arch/csr/Zihpm/hpmcounter5h.yaml b/arch/csr/Zihpm/hpmcounter5h.yaml index 1529a2f8a2..505805a41f 100644 --- a/arch/csr/Zihpm/hpmcounter5h.yaml +++ b/arch/csr/Zihpm/hpmcounter5h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter5h long_name: User-mode Hardware Performance Counter 2, high half address: 0xC85 +writeable: false description: | Alias for M-mode CSR `mhpmcounter5h`. diff --git a/arch/csr/Zihpm/hpmcounter6.yaml b/arch/csr/Zihpm/hpmcounter6.yaml index 128202fdb3..cf0470bcdc 100644 --- a/arch/csr/Zihpm/hpmcounter6.yaml +++ b/arch/csr/Zihpm/hpmcounter6.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter6 long_name: User-mode Hardware Performance Counter 3 address: 0xC06 +writeable: false description: | Alias for M-mode CSR `mhpmcounter6`. diff --git a/arch/csr/Zihpm/hpmcounter6h.yaml b/arch/csr/Zihpm/hpmcounter6h.yaml index 9995fc0eee..cbd7bd150c 100644 --- a/arch/csr/Zihpm/hpmcounter6h.yaml +++ b/arch/csr/Zihpm/hpmcounter6h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter6h long_name: User-mode Hardware Performance Counter 3, high half address: 0xC86 +writeable: false description: | Alias for M-mode CSR `mhpmcounter6h`. diff --git a/arch/csr/Zihpm/hpmcounter7.yaml b/arch/csr/Zihpm/hpmcounter7.yaml index c471a1df47..98f87d5e70 100644 --- a/arch/csr/Zihpm/hpmcounter7.yaml +++ b/arch/csr/Zihpm/hpmcounter7.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter7 long_name: User-mode Hardware Performance Counter 4 address: 0xC07 +writeable: false description: | Alias for M-mode CSR `mhpmcounter7`. diff --git a/arch/csr/Zihpm/hpmcounter7h.yaml b/arch/csr/Zihpm/hpmcounter7h.yaml index 416f912193..c0607c51cb 100644 --- a/arch/csr/Zihpm/hpmcounter7h.yaml +++ b/arch/csr/Zihpm/hpmcounter7h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter7h long_name: User-mode Hardware Performance Counter 4, high half address: 0xC87 +writeable: false description: | Alias for M-mode CSR `mhpmcounter7h`. diff --git a/arch/csr/Zihpm/hpmcounter8.yaml b/arch/csr/Zihpm/hpmcounter8.yaml index a7c22a495c..f91910331a 100644 --- a/arch/csr/Zihpm/hpmcounter8.yaml +++ b/arch/csr/Zihpm/hpmcounter8.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter8 long_name: User-mode Hardware Performance Counter 5 address: 0xC08 +writeable: false description: | Alias for M-mode CSR `mhpmcounter8`. diff --git a/arch/csr/Zihpm/hpmcounter8h.yaml b/arch/csr/Zihpm/hpmcounter8h.yaml index 11a341b4bb..fda4a1ffc6 100644 --- a/arch/csr/Zihpm/hpmcounter8h.yaml +++ b/arch/csr/Zihpm/hpmcounter8h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter8h long_name: User-mode Hardware Performance Counter 5, high half address: 0xC88 +writeable: false description: | Alias for M-mode CSR `mhpmcounter8h`. diff --git a/arch/csr/Zihpm/hpmcounter9.yaml b/arch/csr/Zihpm/hpmcounter9.yaml index 09770fa7a6..522740b419 100644 --- a/arch/csr/Zihpm/hpmcounter9.yaml +++ b/arch/csr/Zihpm/hpmcounter9.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter9 long_name: User-mode Hardware Performance Counter 6 address: 0xC09 +writeable: false description: | Alias for M-mode CSR `mhpmcounter9`. diff --git a/arch/csr/Zihpm/hpmcounter9h.yaml b/arch/csr/Zihpm/hpmcounter9h.yaml index f3fcfdc25b..c8061f67d1 100644 --- a/arch/csr/Zihpm/hpmcounter9h.yaml +++ b/arch/csr/Zihpm/hpmcounter9h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter9h long_name: User-mode Hardware Performance Counter 6, high half address: 0xC89 +writeable: false description: | Alias for M-mode CSR `mhpmcounter9h`. diff --git a/arch/csr/Zihpm/mhpmcounter10.yaml b/arch/csr/Zihpm/mhpmcounter10.yaml index 8bbc5e1d9d..2cc562c1aa 100644 --- a/arch/csr/Zihpm/mhpmcounter10.yaml +++ b/arch/csr/Zihpm/mhpmcounter10.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter10 long_name: Machine Hardware Performance Counter 10 address: 0xB0A +writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter10h.yaml b/arch/csr/Zihpm/mhpmcounter10h.yaml index 3bfbeb11e9..fb91bf2cfb 100644 --- a/arch/csr/Zihpm/mhpmcounter10h.yaml +++ b/arch/csr/Zihpm/mhpmcounter10h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter10h long_name: Machine Hardware Performance Counter 10, Upper half address: 0xB8A +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter11.yaml b/arch/csr/Zihpm/mhpmcounter11.yaml index 0501702a38..ff6fe28b99 100644 --- a/arch/csr/Zihpm/mhpmcounter11.yaml +++ b/arch/csr/Zihpm/mhpmcounter11.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter11 long_name: Machine Hardware Performance Counter 11 address: 0xB0B +writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter11h.yaml b/arch/csr/Zihpm/mhpmcounter11h.yaml index 53d1e8d13b..1850848841 100644 --- a/arch/csr/Zihpm/mhpmcounter11h.yaml +++ b/arch/csr/Zihpm/mhpmcounter11h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter11h long_name: Machine Hardware Performance Counter 11, Upper half address: 0xB8B +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter12.yaml b/arch/csr/Zihpm/mhpmcounter12.yaml index f0aceebd18..00498cebf8 100644 --- a/arch/csr/Zihpm/mhpmcounter12.yaml +++ b/arch/csr/Zihpm/mhpmcounter12.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter12 long_name: Machine Hardware Performance Counter 12 address: 0xB0C +writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter12h.yaml b/arch/csr/Zihpm/mhpmcounter12h.yaml index 0b94cfb176..2807ab87ef 100644 --- a/arch/csr/Zihpm/mhpmcounter12h.yaml +++ b/arch/csr/Zihpm/mhpmcounter12h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter12h long_name: Machine Hardware Performance Counter 12, Upper half address: 0xB8C +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter13.yaml b/arch/csr/Zihpm/mhpmcounter13.yaml index 10fc117dfd..a5f9e6bebd 100644 --- a/arch/csr/Zihpm/mhpmcounter13.yaml +++ b/arch/csr/Zihpm/mhpmcounter13.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter13 long_name: Machine Hardware Performance Counter 13 address: 0xB0D +writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter13h.yaml b/arch/csr/Zihpm/mhpmcounter13h.yaml index 754fb34492..c8b566b9c1 100644 --- a/arch/csr/Zihpm/mhpmcounter13h.yaml +++ b/arch/csr/Zihpm/mhpmcounter13h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter13h long_name: Machine Hardware Performance Counter 13, Upper half address: 0xB8D +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter14.yaml b/arch/csr/Zihpm/mhpmcounter14.yaml index 2285c2cca4..2d22b686b4 100644 --- a/arch/csr/Zihpm/mhpmcounter14.yaml +++ b/arch/csr/Zihpm/mhpmcounter14.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter14 long_name: Machine Hardware Performance Counter 14 address: 0xB0E +writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter14h.yaml b/arch/csr/Zihpm/mhpmcounter14h.yaml index 5f32a7c7bf..2e05420c2d 100644 --- a/arch/csr/Zihpm/mhpmcounter14h.yaml +++ b/arch/csr/Zihpm/mhpmcounter14h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter14h long_name: Machine Hardware Performance Counter 14, Upper half address: 0xB8E +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter15.yaml b/arch/csr/Zihpm/mhpmcounter15.yaml index a487e21c5b..fd0a9edc4e 100644 --- a/arch/csr/Zihpm/mhpmcounter15.yaml +++ b/arch/csr/Zihpm/mhpmcounter15.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter15 long_name: Machine Hardware Performance Counter 15 address: 0xB0F +writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter15h.yaml b/arch/csr/Zihpm/mhpmcounter15h.yaml index 21184c4cc9..19215effe6 100644 --- a/arch/csr/Zihpm/mhpmcounter15h.yaml +++ b/arch/csr/Zihpm/mhpmcounter15h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter15h long_name: Machine Hardware Performance Counter 15, Upper half address: 0xB8F +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter16.yaml b/arch/csr/Zihpm/mhpmcounter16.yaml index 9ff6a82635..61c7aa24d6 100644 --- a/arch/csr/Zihpm/mhpmcounter16.yaml +++ b/arch/csr/Zihpm/mhpmcounter16.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter16 long_name: Machine Hardware Performance Counter 16 address: 0xB10 +writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter16h.yaml b/arch/csr/Zihpm/mhpmcounter16h.yaml index d0b7ee88a5..300d827e3a 100644 --- a/arch/csr/Zihpm/mhpmcounter16h.yaml +++ b/arch/csr/Zihpm/mhpmcounter16h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter16h long_name: Machine Hardware Performance Counter 16, Upper half address: 0xB90 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter17.yaml b/arch/csr/Zihpm/mhpmcounter17.yaml index 6c30f92d62..da262b3c3f 100644 --- a/arch/csr/Zihpm/mhpmcounter17.yaml +++ b/arch/csr/Zihpm/mhpmcounter17.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter17 long_name: Machine Hardware Performance Counter 17 address: 0xB11 +writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter17h.yaml b/arch/csr/Zihpm/mhpmcounter17h.yaml index 14d6a52195..807157626e 100644 --- a/arch/csr/Zihpm/mhpmcounter17h.yaml +++ b/arch/csr/Zihpm/mhpmcounter17h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter17h long_name: Machine Hardware Performance Counter 17, Upper half address: 0xB91 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter18.yaml b/arch/csr/Zihpm/mhpmcounter18.yaml index 02b6dcd4fc..b03d08a6f2 100644 --- a/arch/csr/Zihpm/mhpmcounter18.yaml +++ b/arch/csr/Zihpm/mhpmcounter18.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter18 long_name: Machine Hardware Performance Counter 18 address: 0xB12 +writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter18h.yaml b/arch/csr/Zihpm/mhpmcounter18h.yaml index 3fc41ad052..a50a473f2c 100644 --- a/arch/csr/Zihpm/mhpmcounter18h.yaml +++ b/arch/csr/Zihpm/mhpmcounter18h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter18h long_name: Machine Hardware Performance Counter 18, Upper half address: 0xB92 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter19.yaml b/arch/csr/Zihpm/mhpmcounter19.yaml index 0e45c395c8..84d1292f21 100644 --- a/arch/csr/Zihpm/mhpmcounter19.yaml +++ b/arch/csr/Zihpm/mhpmcounter19.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter19 long_name: Machine Hardware Performance Counter 19 address: 0xB13 +writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter19h.yaml b/arch/csr/Zihpm/mhpmcounter19h.yaml index 6483d13301..78e7318c13 100644 --- a/arch/csr/Zihpm/mhpmcounter19h.yaml +++ b/arch/csr/Zihpm/mhpmcounter19h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter19h long_name: Machine Hardware Performance Counter 19, Upper half address: 0xB93 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter20.yaml b/arch/csr/Zihpm/mhpmcounter20.yaml index 6f7d6d1e85..12cc843582 100644 --- a/arch/csr/Zihpm/mhpmcounter20.yaml +++ b/arch/csr/Zihpm/mhpmcounter20.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter20 long_name: Machine Hardware Performance Counter 20 address: 0xB14 +writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter20h.yaml b/arch/csr/Zihpm/mhpmcounter20h.yaml index 73db882e51..a168876173 100644 --- a/arch/csr/Zihpm/mhpmcounter20h.yaml +++ b/arch/csr/Zihpm/mhpmcounter20h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter20h long_name: Machine Hardware Performance Counter 20, Upper half address: 0xB94 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter21.yaml b/arch/csr/Zihpm/mhpmcounter21.yaml index b5cfa7a02d..cfc330fdc0 100644 --- a/arch/csr/Zihpm/mhpmcounter21.yaml +++ b/arch/csr/Zihpm/mhpmcounter21.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter21 long_name: Machine Hardware Performance Counter 21 address: 0xB15 +writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter21h.yaml b/arch/csr/Zihpm/mhpmcounter21h.yaml index f3d81870f8..5138852e39 100644 --- a/arch/csr/Zihpm/mhpmcounter21h.yaml +++ b/arch/csr/Zihpm/mhpmcounter21h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter21h long_name: Machine Hardware Performance Counter 21, Upper half address: 0xB95 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter22.yaml b/arch/csr/Zihpm/mhpmcounter22.yaml index d35d8671dc..881ad56ae9 100644 --- a/arch/csr/Zihpm/mhpmcounter22.yaml +++ b/arch/csr/Zihpm/mhpmcounter22.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter22 long_name: Machine Hardware Performance Counter 22 address: 0xB16 +writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter22h.yaml b/arch/csr/Zihpm/mhpmcounter22h.yaml index 6617b98232..982784d08f 100644 --- a/arch/csr/Zihpm/mhpmcounter22h.yaml +++ b/arch/csr/Zihpm/mhpmcounter22h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter22h long_name: Machine Hardware Performance Counter 22, Upper half address: 0xB96 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter23.yaml b/arch/csr/Zihpm/mhpmcounter23.yaml index 380c27d78d..f1de6bf132 100644 --- a/arch/csr/Zihpm/mhpmcounter23.yaml +++ b/arch/csr/Zihpm/mhpmcounter23.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter23 long_name: Machine Hardware Performance Counter 23 address: 0xB17 +writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter23h.yaml b/arch/csr/Zihpm/mhpmcounter23h.yaml index 36117b668b..099ee3089f 100644 --- a/arch/csr/Zihpm/mhpmcounter23h.yaml +++ b/arch/csr/Zihpm/mhpmcounter23h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter23h long_name: Machine Hardware Performance Counter 23, Upper half address: 0xB97 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter24.yaml b/arch/csr/Zihpm/mhpmcounter24.yaml index 4f66699999..096bc2e7a5 100644 --- a/arch/csr/Zihpm/mhpmcounter24.yaml +++ b/arch/csr/Zihpm/mhpmcounter24.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter24 long_name: Machine Hardware Performance Counter 24 address: 0xB18 +writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter24h.yaml b/arch/csr/Zihpm/mhpmcounter24h.yaml index d7f37ec8b9..3d8fa5546c 100644 --- a/arch/csr/Zihpm/mhpmcounter24h.yaml +++ b/arch/csr/Zihpm/mhpmcounter24h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter24h long_name: Machine Hardware Performance Counter 24, Upper half address: 0xB98 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter25.yaml b/arch/csr/Zihpm/mhpmcounter25.yaml index ca1ea51987..b5503ae861 100644 --- a/arch/csr/Zihpm/mhpmcounter25.yaml +++ b/arch/csr/Zihpm/mhpmcounter25.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter25 long_name: Machine Hardware Performance Counter 25 address: 0xB19 +writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter25h.yaml b/arch/csr/Zihpm/mhpmcounter25h.yaml index a8d2fa086d..cf7300e514 100644 --- a/arch/csr/Zihpm/mhpmcounter25h.yaml +++ b/arch/csr/Zihpm/mhpmcounter25h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter25h long_name: Machine Hardware Performance Counter 25, Upper half address: 0xB99 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter26.yaml b/arch/csr/Zihpm/mhpmcounter26.yaml index 9175778c05..dfcc27e637 100644 --- a/arch/csr/Zihpm/mhpmcounter26.yaml +++ b/arch/csr/Zihpm/mhpmcounter26.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter26 long_name: Machine Hardware Performance Counter 26 address: 0xB1A +writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter26h.yaml b/arch/csr/Zihpm/mhpmcounter26h.yaml index 2074cf504d..2925dddcab 100644 --- a/arch/csr/Zihpm/mhpmcounter26h.yaml +++ b/arch/csr/Zihpm/mhpmcounter26h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter26h long_name: Machine Hardware Performance Counter 26, Upper half address: 0xB9A +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter27.yaml b/arch/csr/Zihpm/mhpmcounter27.yaml index 0cc6b33f94..9db94ead49 100644 --- a/arch/csr/Zihpm/mhpmcounter27.yaml +++ b/arch/csr/Zihpm/mhpmcounter27.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter27 long_name: Machine Hardware Performance Counter 27 address: 0xB1B +writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter27h.yaml b/arch/csr/Zihpm/mhpmcounter27h.yaml index cfd7308bdf..fdcaea9186 100644 --- a/arch/csr/Zihpm/mhpmcounter27h.yaml +++ b/arch/csr/Zihpm/mhpmcounter27h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter27h long_name: Machine Hardware Performance Counter 27, Upper half address: 0xB9B +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter28.yaml b/arch/csr/Zihpm/mhpmcounter28.yaml index f214594745..211c2ba183 100644 --- a/arch/csr/Zihpm/mhpmcounter28.yaml +++ b/arch/csr/Zihpm/mhpmcounter28.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter28 long_name: Machine Hardware Performance Counter 28 address: 0xB1C +writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter28h.yaml b/arch/csr/Zihpm/mhpmcounter28h.yaml index 5b89a5cdcd..e820f81481 100644 --- a/arch/csr/Zihpm/mhpmcounter28h.yaml +++ b/arch/csr/Zihpm/mhpmcounter28h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter28h long_name: Machine Hardware Performance Counter 28, Upper half address: 0xB9C +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter29.yaml b/arch/csr/Zihpm/mhpmcounter29.yaml index 367de7cfec..1f6ffc1617 100644 --- a/arch/csr/Zihpm/mhpmcounter29.yaml +++ b/arch/csr/Zihpm/mhpmcounter29.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter29 long_name: Machine Hardware Performance Counter 29 address: 0xB1D +writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter29h.yaml b/arch/csr/Zihpm/mhpmcounter29h.yaml index 8bbcd8a105..7a8bcd8450 100644 --- a/arch/csr/Zihpm/mhpmcounter29h.yaml +++ b/arch/csr/Zihpm/mhpmcounter29h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter29h long_name: Machine Hardware Performance Counter 29, Upper half address: 0xB9D +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter3.yaml b/arch/csr/Zihpm/mhpmcounter3.yaml index 5c8dd1c6e1..e566163369 100644 --- a/arch/csr/Zihpm/mhpmcounter3.yaml +++ b/arch/csr/Zihpm/mhpmcounter3.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter3 long_name: Machine Hardware Performance Counter 3 address: 0xB03 +writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter30.yaml b/arch/csr/Zihpm/mhpmcounter30.yaml index 441eaab905..229c38d8f3 100644 --- a/arch/csr/Zihpm/mhpmcounter30.yaml +++ b/arch/csr/Zihpm/mhpmcounter30.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter30 long_name: Machine Hardware Performance Counter 30 address: 0xB1E +writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter30h.yaml b/arch/csr/Zihpm/mhpmcounter30h.yaml index b24609c6f1..5efef1f511 100644 --- a/arch/csr/Zihpm/mhpmcounter30h.yaml +++ b/arch/csr/Zihpm/mhpmcounter30h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter30h long_name: Machine Hardware Performance Counter 30, Upper half address: 0xB9E +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter31.yaml b/arch/csr/Zihpm/mhpmcounter31.yaml index 917c8d533b..321b4891a8 100644 --- a/arch/csr/Zihpm/mhpmcounter31.yaml +++ b/arch/csr/Zihpm/mhpmcounter31.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter31 long_name: Machine Hardware Performance Counter 31 address: 0xB1F +writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter31h.yaml b/arch/csr/Zihpm/mhpmcounter31h.yaml index 219f540d9f..f2eeeaae9b 100644 --- a/arch/csr/Zihpm/mhpmcounter31h.yaml +++ b/arch/csr/Zihpm/mhpmcounter31h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter31h long_name: Machine Hardware Performance Counter 31, Upper half address: 0xB9F +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter3h.yaml b/arch/csr/Zihpm/mhpmcounter3h.yaml index b1d00039fa..cae7c2793f 100644 --- a/arch/csr/Zihpm/mhpmcounter3h.yaml +++ b/arch/csr/Zihpm/mhpmcounter3h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter3h long_name: Machine Hardware Performance Counter 3, Upper half address: 0xB83 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter4.yaml b/arch/csr/Zihpm/mhpmcounter4.yaml index 9fc827b0bf..9cbd076432 100644 --- a/arch/csr/Zihpm/mhpmcounter4.yaml +++ b/arch/csr/Zihpm/mhpmcounter4.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter4 long_name: Machine Hardware Performance Counter 4 address: 0xB04 +writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter4h.yaml b/arch/csr/Zihpm/mhpmcounter4h.yaml index b810844ab8..774a29590f 100644 --- a/arch/csr/Zihpm/mhpmcounter4h.yaml +++ b/arch/csr/Zihpm/mhpmcounter4h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter4h long_name: Machine Hardware Performance Counter 4, Upper half address: 0xB84 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter5.yaml b/arch/csr/Zihpm/mhpmcounter5.yaml index b4c035e04f..1a0b723f1c 100644 --- a/arch/csr/Zihpm/mhpmcounter5.yaml +++ b/arch/csr/Zihpm/mhpmcounter5.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter5 long_name: Machine Hardware Performance Counter 5 address: 0xB05 +writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter5h.yaml b/arch/csr/Zihpm/mhpmcounter5h.yaml index f8296cf5a8..d76cd03bec 100644 --- a/arch/csr/Zihpm/mhpmcounter5h.yaml +++ b/arch/csr/Zihpm/mhpmcounter5h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter5h long_name: Machine Hardware Performance Counter 5, Upper half address: 0xB85 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter6.yaml b/arch/csr/Zihpm/mhpmcounter6.yaml index 187e00a28b..1e1afb0bb7 100644 --- a/arch/csr/Zihpm/mhpmcounter6.yaml +++ b/arch/csr/Zihpm/mhpmcounter6.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter6 long_name: Machine Hardware Performance Counter 6 address: 0xB06 +writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter6h.yaml b/arch/csr/Zihpm/mhpmcounter6h.yaml index 3305497de4..726df5825a 100644 --- a/arch/csr/Zihpm/mhpmcounter6h.yaml +++ b/arch/csr/Zihpm/mhpmcounter6h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter6h long_name: Machine Hardware Performance Counter 6, Upper half address: 0xB86 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter7.yaml b/arch/csr/Zihpm/mhpmcounter7.yaml index 7d56e48d5a..3e6bdc9d6d 100644 --- a/arch/csr/Zihpm/mhpmcounter7.yaml +++ b/arch/csr/Zihpm/mhpmcounter7.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter7 long_name: Machine Hardware Performance Counter 7 address: 0xB07 +writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter7h.yaml b/arch/csr/Zihpm/mhpmcounter7h.yaml index 05fc92d3c0..72f940d1f3 100644 --- a/arch/csr/Zihpm/mhpmcounter7h.yaml +++ b/arch/csr/Zihpm/mhpmcounter7h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter7h long_name: Machine Hardware Performance Counter 7, Upper half address: 0xB87 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter8.yaml b/arch/csr/Zihpm/mhpmcounter8.yaml index a29a653bcc..10e30a6349 100644 --- a/arch/csr/Zihpm/mhpmcounter8.yaml +++ b/arch/csr/Zihpm/mhpmcounter8.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter8 long_name: Machine Hardware Performance Counter 8 address: 0xB08 +writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter8h.yaml b/arch/csr/Zihpm/mhpmcounter8h.yaml index 02b097678b..2dc2d52c65 100644 --- a/arch/csr/Zihpm/mhpmcounter8h.yaml +++ b/arch/csr/Zihpm/mhpmcounter8h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter8h long_name: Machine Hardware Performance Counter 8, Upper half address: 0xB88 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter9.yaml b/arch/csr/Zihpm/mhpmcounter9.yaml index 729999ee53..a7f659d0b7 100644 --- a/arch/csr/Zihpm/mhpmcounter9.yaml +++ b/arch/csr/Zihpm/mhpmcounter9.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter9 long_name: Machine Hardware Performance Counter 9 address: 0xB09 +writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter9h.yaml b/arch/csr/Zihpm/mhpmcounter9h.yaml index 277f425300..05b360ffb9 100644 --- a/arch/csr/Zihpm/mhpmcounter9h.yaml +++ b/arch/csr/Zihpm/mhpmcounter9h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter9h long_name: Machine Hardware Performance Counter 9, Upper half address: 0xB89 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent10.yaml b/arch/csr/Zihpm/mhpmevent10.yaml index d5e3511e5d..ecb0134747 100644 --- a/arch/csr/Zihpm/mhpmevent10.yaml +++ b/arch/csr/Zihpm/mhpmevent10.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent10 long_name: Machine Hardware Performance Counter 10 Control address: 0x32A +writeable: true priv_mode: M length: 64 description: | @@ -42,7 +43,9 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: When set, mhpmcounter10 does not increment while the hart in operating in M-mode. + description: + When set, mhpmcounter10 does not increment while the hart in operating + in M-mode. type(): | if (HPM_COUNTER_EN[10]) { return CsrFieldType::RW; @@ -58,7 +61,9 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: When set, mhpmcounter10 does not increment while the hart in operating in (H)S-mode. + description: + When set, mhpmcounter10 does not increment while the hart in operating + in (H)S-mode. type(): | if (HPM_COUNTER_EN[10] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -74,7 +79,9 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: When set, mhpmcounter10 does not increment while the hart in operating in U-mode. + description: + When set, mhpmcounter10 does not increment while the hart in operating + in U-mode. type(): | if (HPM_COUNTER_EN[10] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -90,7 +97,9 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: When set, mhpmcounter10 does not increment while the hart in operating in VS-mode. + description: + When set, mhpmcounter10 does not increment while the hart in operating + in VS-mode. type(): | if ((HPM_COUNTER_EN[10]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -106,7 +115,9 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: When set, mhpmcounter10 does not increment while the hart in operating in VU-mode. + description: + When set, mhpmcounter10 does not increment while the hart in operating + in VU-mode. type(): | if (HPM_COUNTER_EN[10] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent10h.yaml b/arch/csr/Zihpm/mhpmevent10h.yaml index ddc90479cd..7fd5b12239 100644 --- a/arch/csr/Zihpm/mhpmevent10h.yaml +++ b/arch/csr/Zihpm/mhpmevent10h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent10h long_name: Machine Hardware Performance Counter 10 Control, High half address: 0x72A +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent11.yaml b/arch/csr/Zihpm/mhpmevent11.yaml index 25acd4e788..f2f4bb4ef2 100644 --- a/arch/csr/Zihpm/mhpmevent11.yaml +++ b/arch/csr/Zihpm/mhpmevent11.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent11 long_name: Machine Hardware Performance Counter 11 Control address: 0x32B +writeable: true priv_mode: M length: 64 description: | @@ -42,7 +43,9 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: When set, mhpmcounter11 does not increment while the hart in operating in M-mode. + description: + When set, mhpmcounter11 does not increment while the hart in operating + in M-mode. type(): | if (HPM_COUNTER_EN[11]) { return CsrFieldType::RW; @@ -58,7 +61,9 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: When set, mhpmcounter11 does not increment while the hart in operating in (H)S-mode. + description: + When set, mhpmcounter11 does not increment while the hart in operating + in (H)S-mode. type(): | if (HPM_COUNTER_EN[11] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -74,7 +79,9 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: When set, mhpmcounter11 does not increment while the hart in operating in U-mode. + description: + When set, mhpmcounter11 does not increment while the hart in operating + in U-mode. type(): | if (HPM_COUNTER_EN[11] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -90,7 +97,9 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: When set, mhpmcounter11 does not increment while the hart in operating in VS-mode. + description: + When set, mhpmcounter11 does not increment while the hart in operating + in VS-mode. type(): | if ((HPM_COUNTER_EN[11]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -106,7 +115,9 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: When set, mhpmcounter11 does not increment while the hart in operating in VU-mode. + description: + When set, mhpmcounter11 does not increment while the hart in operating + in VU-mode. type(): | if (HPM_COUNTER_EN[11] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent11h.yaml b/arch/csr/Zihpm/mhpmevent11h.yaml index 10a4d69ab0..71ad1eb900 100644 --- a/arch/csr/Zihpm/mhpmevent11h.yaml +++ b/arch/csr/Zihpm/mhpmevent11h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent11h long_name: Machine Hardware Performance Counter 11 Control, High half address: 0x72B +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent12.yaml b/arch/csr/Zihpm/mhpmevent12.yaml index 3277d79920..44ec92451a 100644 --- a/arch/csr/Zihpm/mhpmevent12.yaml +++ b/arch/csr/Zihpm/mhpmevent12.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent12 long_name: Machine Hardware Performance Counter 12 Control address: 0x32C +writeable: true priv_mode: M length: 64 description: | @@ -42,7 +43,9 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: When set, mhpmcounter12 does not increment while the hart in operating in M-mode. + description: + When set, mhpmcounter12 does not increment while the hart in operating + in M-mode. type(): | if (HPM_COUNTER_EN[12]) { return CsrFieldType::RW; @@ -58,7 +61,9 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: When set, mhpmcounter12 does not increment while the hart in operating in (H)S-mode. + description: + When set, mhpmcounter12 does not increment while the hart in operating + in (H)S-mode. type(): | if (HPM_COUNTER_EN[12] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -74,7 +79,9 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: When set, mhpmcounter12 does not increment while the hart in operating in U-mode. + description: + When set, mhpmcounter12 does not increment while the hart in operating + in U-mode. type(): | if (HPM_COUNTER_EN[12] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -90,7 +97,9 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: When set, mhpmcounter12 does not increment while the hart in operating in VS-mode. + description: + When set, mhpmcounter12 does not increment while the hart in operating + in VS-mode. type(): | if ((HPM_COUNTER_EN[12]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -106,7 +115,9 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: When set, mhpmcounter12 does not increment while the hart in operating in VU-mode. + description: + When set, mhpmcounter12 does not increment while the hart in operating + in VU-mode. type(): | if (HPM_COUNTER_EN[12] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent12h.yaml b/arch/csr/Zihpm/mhpmevent12h.yaml index 1561213e0b..e760126e39 100644 --- a/arch/csr/Zihpm/mhpmevent12h.yaml +++ b/arch/csr/Zihpm/mhpmevent12h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent12h long_name: Machine Hardware Performance Counter 12 Control, High half address: 0x72C +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent13.yaml b/arch/csr/Zihpm/mhpmevent13.yaml index 8fe055a95f..089da9360c 100644 --- a/arch/csr/Zihpm/mhpmevent13.yaml +++ b/arch/csr/Zihpm/mhpmevent13.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent13 long_name: Machine Hardware Performance Counter 13 Control address: 0x32D +writeable: true priv_mode: M length: 64 description: | @@ -42,7 +43,9 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: When set, mhpmcounter13 does not increment while the hart in operating in M-mode. + description: + When set, mhpmcounter13 does not increment while the hart in operating + in M-mode. type(): | if (HPM_COUNTER_EN[13]) { return CsrFieldType::RW; @@ -58,7 +61,9 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: When set, mhpmcounter13 does not increment while the hart in operating in (H)S-mode. + description: + When set, mhpmcounter13 does not increment while the hart in operating + in (H)S-mode. type(): | if (HPM_COUNTER_EN[13] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -74,7 +79,9 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: When set, mhpmcounter13 does not increment while the hart in operating in U-mode. + description: + When set, mhpmcounter13 does not increment while the hart in operating + in U-mode. type(): | if (HPM_COUNTER_EN[13] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -90,7 +97,9 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: When set, mhpmcounter13 does not increment while the hart in operating in VS-mode. + description: + When set, mhpmcounter13 does not increment while the hart in operating + in VS-mode. type(): | if ((HPM_COUNTER_EN[13]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -106,7 +115,9 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: When set, mhpmcounter13 does not increment while the hart in operating in VU-mode. + description: + When set, mhpmcounter13 does not increment while the hart in operating + in VU-mode. type(): | if (HPM_COUNTER_EN[13] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent13h.yaml b/arch/csr/Zihpm/mhpmevent13h.yaml index 9d6a4c4f48..b335a5472d 100644 --- a/arch/csr/Zihpm/mhpmevent13h.yaml +++ b/arch/csr/Zihpm/mhpmevent13h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent13h long_name: Machine Hardware Performance Counter 13 Control, High half address: 0x72D +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent14.yaml b/arch/csr/Zihpm/mhpmevent14.yaml index c4f64bcd0e..9480a5315a 100644 --- a/arch/csr/Zihpm/mhpmevent14.yaml +++ b/arch/csr/Zihpm/mhpmevent14.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent14 long_name: Machine Hardware Performance Counter 14 Control address: 0x32E +writeable: true priv_mode: M length: 64 description: | @@ -42,7 +43,9 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: When set, mhpmcounter14 does not increment while the hart in operating in M-mode. + description: + When set, mhpmcounter14 does not increment while the hart in operating + in M-mode. type(): | if (HPM_COUNTER_EN[14]) { return CsrFieldType::RW; @@ -58,7 +61,9 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: When set, mhpmcounter14 does not increment while the hart in operating in (H)S-mode. + description: + When set, mhpmcounter14 does not increment while the hart in operating + in (H)S-mode. type(): | if (HPM_COUNTER_EN[14] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -74,7 +79,9 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: When set, mhpmcounter14 does not increment while the hart in operating in U-mode. + description: + When set, mhpmcounter14 does not increment while the hart in operating + in U-mode. type(): | if (HPM_COUNTER_EN[14] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -90,7 +97,9 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: When set, mhpmcounter14 does not increment while the hart in operating in VS-mode. + description: + When set, mhpmcounter14 does not increment while the hart in operating + in VS-mode. type(): | if ((HPM_COUNTER_EN[14]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -106,7 +115,9 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: When set, mhpmcounter14 does not increment while the hart in operating in VU-mode. + description: + When set, mhpmcounter14 does not increment while the hart in operating + in VU-mode. type(): | if (HPM_COUNTER_EN[14] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent14h.yaml b/arch/csr/Zihpm/mhpmevent14h.yaml index 53e1db9431..3b723c6fa5 100644 --- a/arch/csr/Zihpm/mhpmevent14h.yaml +++ b/arch/csr/Zihpm/mhpmevent14h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent14h long_name: Machine Hardware Performance Counter 14 Control, High half address: 0x72E +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent15.yaml b/arch/csr/Zihpm/mhpmevent15.yaml index bf73956a62..8295fd4b53 100644 --- a/arch/csr/Zihpm/mhpmevent15.yaml +++ b/arch/csr/Zihpm/mhpmevent15.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent15 long_name: Machine Hardware Performance Counter 15 Control address: 0x32F +writeable: true priv_mode: M length: 64 description: | @@ -42,7 +43,9 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: When set, mhpmcounter15 does not increment while the hart in operating in M-mode. + description: + When set, mhpmcounter15 does not increment while the hart in operating + in M-mode. type(): | if (HPM_COUNTER_EN[15]) { return CsrFieldType::RW; @@ -58,7 +61,9 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: When set, mhpmcounter15 does not increment while the hart in operating in (H)S-mode. + description: + When set, mhpmcounter15 does not increment while the hart in operating + in (H)S-mode. type(): | if (HPM_COUNTER_EN[15] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -74,7 +79,9 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: When set, mhpmcounter15 does not increment while the hart in operating in U-mode. + description: + When set, mhpmcounter15 does not increment while the hart in operating + in U-mode. type(): | if (HPM_COUNTER_EN[15] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -90,7 +97,9 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: When set, mhpmcounter15 does not increment while the hart in operating in VS-mode. + description: + When set, mhpmcounter15 does not increment while the hart in operating + in VS-mode. type(): | if ((HPM_COUNTER_EN[15]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -106,7 +115,9 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: When set, mhpmcounter15 does not increment while the hart in operating in VU-mode. + description: + When set, mhpmcounter15 does not increment while the hart in operating + in VU-mode. type(): | if (HPM_COUNTER_EN[15] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent15h.yaml b/arch/csr/Zihpm/mhpmevent15h.yaml index a8298f5a03..d3dd4d15be 100644 --- a/arch/csr/Zihpm/mhpmevent15h.yaml +++ b/arch/csr/Zihpm/mhpmevent15h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent15h long_name: Machine Hardware Performance Counter 15 Control, High half address: 0x72F +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent16.yaml b/arch/csr/Zihpm/mhpmevent16.yaml index 0f39bfbc94..2f5e596db5 100644 --- a/arch/csr/Zihpm/mhpmevent16.yaml +++ b/arch/csr/Zihpm/mhpmevent16.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent16 long_name: Machine Hardware Performance Counter 16 Control address: 0x330 +writeable: true priv_mode: M length: 64 description: | @@ -42,7 +43,9 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: When set, mhpmcounter16 does not increment while the hart in operating in M-mode. + description: + When set, mhpmcounter16 does not increment while the hart in operating + in M-mode. type(): | if (HPM_COUNTER_EN[16]) { return CsrFieldType::RW; @@ -58,7 +61,9 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: When set, mhpmcounter16 does not increment while the hart in operating in (H)S-mode. + description: + When set, mhpmcounter16 does not increment while the hart in operating + in (H)S-mode. type(): | if (HPM_COUNTER_EN[16] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -74,7 +79,9 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: When set, mhpmcounter16 does not increment while the hart in operating in U-mode. + description: + When set, mhpmcounter16 does not increment while the hart in operating + in U-mode. type(): | if (HPM_COUNTER_EN[16] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -90,7 +97,9 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: When set, mhpmcounter16 does not increment while the hart in operating in VS-mode. + description: + When set, mhpmcounter16 does not increment while the hart in operating + in VS-mode. type(): | if ((HPM_COUNTER_EN[16]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -106,7 +115,9 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: When set, mhpmcounter16 does not increment while the hart in operating in VU-mode. + description: + When set, mhpmcounter16 does not increment while the hart in operating + in VU-mode. type(): | if (HPM_COUNTER_EN[16] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent16h.yaml b/arch/csr/Zihpm/mhpmevent16h.yaml index 7257f46c5f..3052f0ef14 100644 --- a/arch/csr/Zihpm/mhpmevent16h.yaml +++ b/arch/csr/Zihpm/mhpmevent16h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent16h long_name: Machine Hardware Performance Counter 16 Control, High half address: 0x730 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent17.yaml b/arch/csr/Zihpm/mhpmevent17.yaml index b442d54fb2..1be002bc2a 100644 --- a/arch/csr/Zihpm/mhpmevent17.yaml +++ b/arch/csr/Zihpm/mhpmevent17.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent17 long_name: Machine Hardware Performance Counter 17 Control address: 0x331 +writeable: true priv_mode: M length: 64 description: | @@ -42,7 +43,9 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: When set, mhpmcounter17 does not increment while the hart in operating in M-mode. + description: + When set, mhpmcounter17 does not increment while the hart in operating + in M-mode. type(): | if (HPM_COUNTER_EN[17]) { return CsrFieldType::RW; @@ -58,7 +61,9 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: When set, mhpmcounter17 does not increment while the hart in operating in (H)S-mode. + description: + When set, mhpmcounter17 does not increment while the hart in operating + in (H)S-mode. type(): | if (HPM_COUNTER_EN[17] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -74,7 +79,9 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: When set, mhpmcounter17 does not increment while the hart in operating in U-mode. + description: + When set, mhpmcounter17 does not increment while the hart in operating + in U-mode. type(): | if (HPM_COUNTER_EN[17] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -90,7 +97,9 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: When set, mhpmcounter17 does not increment while the hart in operating in VS-mode. + description: + When set, mhpmcounter17 does not increment while the hart in operating + in VS-mode. type(): | if ((HPM_COUNTER_EN[17]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -106,7 +115,9 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: When set, mhpmcounter17 does not increment while the hart in operating in VU-mode. + description: + When set, mhpmcounter17 does not increment while the hart in operating + in VU-mode. type(): | if (HPM_COUNTER_EN[17] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent17h.yaml b/arch/csr/Zihpm/mhpmevent17h.yaml index 70e07cc5b5..a47dfea651 100644 --- a/arch/csr/Zihpm/mhpmevent17h.yaml +++ b/arch/csr/Zihpm/mhpmevent17h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent17h long_name: Machine Hardware Performance Counter 17 Control, High half address: 0x731 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent18.yaml b/arch/csr/Zihpm/mhpmevent18.yaml index 95f43e4428..19911621eb 100644 --- a/arch/csr/Zihpm/mhpmevent18.yaml +++ b/arch/csr/Zihpm/mhpmevent18.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent18 long_name: Machine Hardware Performance Counter 18 Control address: 0x332 +writeable: true priv_mode: M length: 64 description: | @@ -42,7 +43,9 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: When set, mhpmcounter18 does not increment while the hart in operating in M-mode. + description: + When set, mhpmcounter18 does not increment while the hart in operating + in M-mode. type(): | if (HPM_COUNTER_EN[18]) { return CsrFieldType::RW; @@ -58,7 +61,9 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: When set, mhpmcounter18 does not increment while the hart in operating in (H)S-mode. + description: + When set, mhpmcounter18 does not increment while the hart in operating + in (H)S-mode. type(): | if (HPM_COUNTER_EN[18] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -74,7 +79,9 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: When set, mhpmcounter18 does not increment while the hart in operating in U-mode. + description: + When set, mhpmcounter18 does not increment while the hart in operating + in U-mode. type(): | if (HPM_COUNTER_EN[18] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -90,7 +97,9 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: When set, mhpmcounter18 does not increment while the hart in operating in VS-mode. + description: + When set, mhpmcounter18 does not increment while the hart in operating + in VS-mode. type(): | if ((HPM_COUNTER_EN[18]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -106,7 +115,9 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: When set, mhpmcounter18 does not increment while the hart in operating in VU-mode. + description: + When set, mhpmcounter18 does not increment while the hart in operating + in VU-mode. type(): | if (HPM_COUNTER_EN[18] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent18h.yaml b/arch/csr/Zihpm/mhpmevent18h.yaml index 4cd34aaafa..23d83aa836 100644 --- a/arch/csr/Zihpm/mhpmevent18h.yaml +++ b/arch/csr/Zihpm/mhpmevent18h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent18h long_name: Machine Hardware Performance Counter 18 Control, High half address: 0x732 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent19.yaml b/arch/csr/Zihpm/mhpmevent19.yaml index 1a1ced791e..9f9d441605 100644 --- a/arch/csr/Zihpm/mhpmevent19.yaml +++ b/arch/csr/Zihpm/mhpmevent19.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent19 long_name: Machine Hardware Performance Counter 19 Control address: 0x333 +writeable: true priv_mode: M length: 64 description: | @@ -42,7 +43,9 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: When set, mhpmcounter19 does not increment while the hart in operating in M-mode. + description: + When set, mhpmcounter19 does not increment while the hart in operating + in M-mode. type(): | if (HPM_COUNTER_EN[19]) { return CsrFieldType::RW; @@ -58,7 +61,9 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: When set, mhpmcounter19 does not increment while the hart in operating in (H)S-mode. + description: + When set, mhpmcounter19 does not increment while the hart in operating + in (H)S-mode. type(): | if (HPM_COUNTER_EN[19] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -74,7 +79,9 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: When set, mhpmcounter19 does not increment while the hart in operating in U-mode. + description: + When set, mhpmcounter19 does not increment while the hart in operating + in U-mode. type(): | if (HPM_COUNTER_EN[19] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -90,7 +97,9 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: When set, mhpmcounter19 does not increment while the hart in operating in VS-mode. + description: + When set, mhpmcounter19 does not increment while the hart in operating + in VS-mode. type(): | if ((HPM_COUNTER_EN[19]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -106,7 +115,9 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: When set, mhpmcounter19 does not increment while the hart in operating in VU-mode. + description: + When set, mhpmcounter19 does not increment while the hart in operating + in VU-mode. type(): | if (HPM_COUNTER_EN[19] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent19h.yaml b/arch/csr/Zihpm/mhpmevent19h.yaml index 2d67a0db2e..4afb967263 100644 --- a/arch/csr/Zihpm/mhpmevent19h.yaml +++ b/arch/csr/Zihpm/mhpmevent19h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent19h long_name: Machine Hardware Performance Counter 19 Control, High half address: 0x733 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent20.yaml b/arch/csr/Zihpm/mhpmevent20.yaml index 5ec2c960b9..b603174dc4 100644 --- a/arch/csr/Zihpm/mhpmevent20.yaml +++ b/arch/csr/Zihpm/mhpmevent20.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent20 long_name: Machine Hardware Performance Counter 20 Control address: 0x334 +writeable: true priv_mode: M length: 64 description: | @@ -42,7 +43,9 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: When set, mhpmcounter20 does not increment while the hart in operating in M-mode. + description: + When set, mhpmcounter20 does not increment while the hart in operating + in M-mode. type(): | if (HPM_COUNTER_EN[20]) { return CsrFieldType::RW; @@ -58,7 +61,9 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: When set, mhpmcounter20 does not increment while the hart in operating in (H)S-mode. + description: + When set, mhpmcounter20 does not increment while the hart in operating + in (H)S-mode. type(): | if (HPM_COUNTER_EN[20] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -74,7 +79,9 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: When set, mhpmcounter20 does not increment while the hart in operating in U-mode. + description: + When set, mhpmcounter20 does not increment while the hart in operating + in U-mode. type(): | if (HPM_COUNTER_EN[20] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -90,7 +97,9 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: When set, mhpmcounter20 does not increment while the hart in operating in VS-mode. + description: + When set, mhpmcounter20 does not increment while the hart in operating + in VS-mode. type(): | if ((HPM_COUNTER_EN[20]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -106,7 +115,9 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: When set, mhpmcounter20 does not increment while the hart in operating in VU-mode. + description: + When set, mhpmcounter20 does not increment while the hart in operating + in VU-mode. type(): | if (HPM_COUNTER_EN[20] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent20h.yaml b/arch/csr/Zihpm/mhpmevent20h.yaml index 32f9027ac7..eb60d57b1d 100644 --- a/arch/csr/Zihpm/mhpmevent20h.yaml +++ b/arch/csr/Zihpm/mhpmevent20h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent20h long_name: Machine Hardware Performance Counter 20 Control, High half address: 0x734 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent21.yaml b/arch/csr/Zihpm/mhpmevent21.yaml index 166aa50f66..064ad0a591 100644 --- a/arch/csr/Zihpm/mhpmevent21.yaml +++ b/arch/csr/Zihpm/mhpmevent21.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent21 long_name: Machine Hardware Performance Counter 21 Control address: 0x335 +writeable: true priv_mode: M length: 64 description: | @@ -42,7 +43,9 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: When set, mhpmcounter21 does not increment while the hart in operating in M-mode. + description: + When set, mhpmcounter21 does not increment while the hart in operating + in M-mode. type(): | if (HPM_COUNTER_EN[21]) { return CsrFieldType::RW; @@ -58,7 +61,9 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: When set, mhpmcounter21 does not increment while the hart in operating in (H)S-mode. + description: + When set, mhpmcounter21 does not increment while the hart in operating + in (H)S-mode. type(): | if (HPM_COUNTER_EN[21] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -74,7 +79,9 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: When set, mhpmcounter21 does not increment while the hart in operating in U-mode. + description: + When set, mhpmcounter21 does not increment while the hart in operating + in U-mode. type(): | if (HPM_COUNTER_EN[21] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -90,7 +97,9 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: When set, mhpmcounter21 does not increment while the hart in operating in VS-mode. + description: + When set, mhpmcounter21 does not increment while the hart in operating + in VS-mode. type(): | if ((HPM_COUNTER_EN[21]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -106,7 +115,9 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: When set, mhpmcounter21 does not increment while the hart in operating in VU-mode. + description: + When set, mhpmcounter21 does not increment while the hart in operating + in VU-mode. type(): | if (HPM_COUNTER_EN[21] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent21h.yaml b/arch/csr/Zihpm/mhpmevent21h.yaml index f5fa3dfe28..a44c4f4f53 100644 --- a/arch/csr/Zihpm/mhpmevent21h.yaml +++ b/arch/csr/Zihpm/mhpmevent21h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent21h long_name: Machine Hardware Performance Counter 21 Control, High half address: 0x735 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent22.yaml b/arch/csr/Zihpm/mhpmevent22.yaml index 21f1a3c4bb..b8697f2433 100644 --- a/arch/csr/Zihpm/mhpmevent22.yaml +++ b/arch/csr/Zihpm/mhpmevent22.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent22 long_name: Machine Hardware Performance Counter 22 Control address: 0x336 +writeable: true priv_mode: M length: 64 description: | @@ -42,7 +43,9 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: When set, mhpmcounter22 does not increment while the hart in operating in M-mode. + description: + When set, mhpmcounter22 does not increment while the hart in operating + in M-mode. type(): | if (HPM_COUNTER_EN[22]) { return CsrFieldType::RW; @@ -58,7 +61,9 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: When set, mhpmcounter22 does not increment while the hart in operating in (H)S-mode. + description: + When set, mhpmcounter22 does not increment while the hart in operating + in (H)S-mode. type(): | if (HPM_COUNTER_EN[22] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -74,7 +79,9 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: When set, mhpmcounter22 does not increment while the hart in operating in U-mode. + description: + When set, mhpmcounter22 does not increment while the hart in operating + in U-mode. type(): | if (HPM_COUNTER_EN[22] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -90,7 +97,9 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: When set, mhpmcounter22 does not increment while the hart in operating in VS-mode. + description: + When set, mhpmcounter22 does not increment while the hart in operating + in VS-mode. type(): | if ((HPM_COUNTER_EN[22]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -106,7 +115,9 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: When set, mhpmcounter22 does not increment while the hart in operating in VU-mode. + description: + When set, mhpmcounter22 does not increment while the hart in operating + in VU-mode. type(): | if (HPM_COUNTER_EN[22] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent22h.yaml b/arch/csr/Zihpm/mhpmevent22h.yaml index a8adbe8a1e..317a5516b5 100644 --- a/arch/csr/Zihpm/mhpmevent22h.yaml +++ b/arch/csr/Zihpm/mhpmevent22h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent22h long_name: Machine Hardware Performance Counter 22 Control, High half address: 0x736 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent23.yaml b/arch/csr/Zihpm/mhpmevent23.yaml index 4e6b623c04..fed6373eb6 100644 --- a/arch/csr/Zihpm/mhpmevent23.yaml +++ b/arch/csr/Zihpm/mhpmevent23.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent23 long_name: Machine Hardware Performance Counter 23 Control address: 0x337 +writeable: true priv_mode: M length: 64 description: | @@ -42,7 +43,9 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: When set, mhpmcounter23 does not increment while the hart in operating in M-mode. + description: + When set, mhpmcounter23 does not increment while the hart in operating + in M-mode. type(): | if (HPM_COUNTER_EN[23]) { return CsrFieldType::RW; @@ -58,7 +61,9 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: When set, mhpmcounter23 does not increment while the hart in operating in (H)S-mode. + description: + When set, mhpmcounter23 does not increment while the hart in operating + in (H)S-mode. type(): | if (HPM_COUNTER_EN[23] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -74,7 +79,9 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: When set, mhpmcounter23 does not increment while the hart in operating in U-mode. + description: + When set, mhpmcounter23 does not increment while the hart in operating + in U-mode. type(): | if (HPM_COUNTER_EN[23] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -90,7 +97,9 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: When set, mhpmcounter23 does not increment while the hart in operating in VS-mode. + description: + When set, mhpmcounter23 does not increment while the hart in operating + in VS-mode. type(): | if ((HPM_COUNTER_EN[23]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -106,7 +115,9 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: When set, mhpmcounter23 does not increment while the hart in operating in VU-mode. + description: + When set, mhpmcounter23 does not increment while the hart in operating + in VU-mode. type(): | if (HPM_COUNTER_EN[23] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent23h.yaml b/arch/csr/Zihpm/mhpmevent23h.yaml index ba1566e3d1..2b04776472 100644 --- a/arch/csr/Zihpm/mhpmevent23h.yaml +++ b/arch/csr/Zihpm/mhpmevent23h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent23h long_name: Machine Hardware Performance Counter 23 Control, High half address: 0x737 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent24.yaml b/arch/csr/Zihpm/mhpmevent24.yaml index 89cd20f66e..f9ad03c43e 100644 --- a/arch/csr/Zihpm/mhpmevent24.yaml +++ b/arch/csr/Zihpm/mhpmevent24.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent24 long_name: Machine Hardware Performance Counter 24 Control address: 0x338 +writeable: true priv_mode: M length: 64 description: | @@ -42,7 +43,9 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: When set, mhpmcounter24 does not increment while the hart in operating in M-mode. + description: + When set, mhpmcounter24 does not increment while the hart in operating + in M-mode. type(): | if (HPM_COUNTER_EN[24]) { return CsrFieldType::RW; @@ -58,7 +61,9 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: When set, mhpmcounter24 does not increment while the hart in operating in (H)S-mode. + description: + When set, mhpmcounter24 does not increment while the hart in operating + in (H)S-mode. type(): | if (HPM_COUNTER_EN[24] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -74,7 +79,9 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: When set, mhpmcounter24 does not increment while the hart in operating in U-mode. + description: + When set, mhpmcounter24 does not increment while the hart in operating + in U-mode. type(): | if (HPM_COUNTER_EN[24] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -90,7 +97,9 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: When set, mhpmcounter24 does not increment while the hart in operating in VS-mode. + description: + When set, mhpmcounter24 does not increment while the hart in operating + in VS-mode. type(): | if ((HPM_COUNTER_EN[24]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -106,7 +115,9 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: When set, mhpmcounter24 does not increment while the hart in operating in VU-mode. + description: + When set, mhpmcounter24 does not increment while the hart in operating + in VU-mode. type(): | if (HPM_COUNTER_EN[24] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent24h.yaml b/arch/csr/Zihpm/mhpmevent24h.yaml index 69adfe7536..540580e16a 100644 --- a/arch/csr/Zihpm/mhpmevent24h.yaml +++ b/arch/csr/Zihpm/mhpmevent24h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent24h long_name: Machine Hardware Performance Counter 24 Control, High half address: 0x738 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent25.yaml b/arch/csr/Zihpm/mhpmevent25.yaml index 4b291b985f..6b743c3a8e 100644 --- a/arch/csr/Zihpm/mhpmevent25.yaml +++ b/arch/csr/Zihpm/mhpmevent25.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent25 long_name: Machine Hardware Performance Counter 25 Control address: 0x339 +writeable: true priv_mode: M length: 64 description: | @@ -42,7 +43,9 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: When set, mhpmcounter25 does not increment while the hart in operating in M-mode. + description: + When set, mhpmcounter25 does not increment while the hart in operating + in M-mode. type(): | if (HPM_COUNTER_EN[25]) { return CsrFieldType::RW; @@ -58,7 +61,9 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: When set, mhpmcounter25 does not increment while the hart in operating in (H)S-mode. + description: + When set, mhpmcounter25 does not increment while the hart in operating + in (H)S-mode. type(): | if (HPM_COUNTER_EN[25] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -74,7 +79,9 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: When set, mhpmcounter25 does not increment while the hart in operating in U-mode. + description: + When set, mhpmcounter25 does not increment while the hart in operating + in U-mode. type(): | if (HPM_COUNTER_EN[25] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -90,7 +97,9 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: When set, mhpmcounter25 does not increment while the hart in operating in VS-mode. + description: + When set, mhpmcounter25 does not increment while the hart in operating + in VS-mode. type(): | if ((HPM_COUNTER_EN[25]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -106,7 +115,9 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: When set, mhpmcounter25 does not increment while the hart in operating in VU-mode. + description: + When set, mhpmcounter25 does not increment while the hart in operating + in VU-mode. type(): | if (HPM_COUNTER_EN[25] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent25h.yaml b/arch/csr/Zihpm/mhpmevent25h.yaml index 411ba06a52..c8e75371a9 100644 --- a/arch/csr/Zihpm/mhpmevent25h.yaml +++ b/arch/csr/Zihpm/mhpmevent25h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent25h long_name: Machine Hardware Performance Counter 25 Control, High half address: 0x739 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent26.yaml b/arch/csr/Zihpm/mhpmevent26.yaml index 0ca5a2c6fe..2ef1de995d 100644 --- a/arch/csr/Zihpm/mhpmevent26.yaml +++ b/arch/csr/Zihpm/mhpmevent26.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent26 long_name: Machine Hardware Performance Counter 26 Control address: 0x33A +writeable: true priv_mode: M length: 64 description: | @@ -42,7 +43,9 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: When set, mhpmcounter26 does not increment while the hart in operating in M-mode. + description: + When set, mhpmcounter26 does not increment while the hart in operating + in M-mode. type(): | if (HPM_COUNTER_EN[26]) { return CsrFieldType::RW; @@ -58,7 +61,9 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: When set, mhpmcounter26 does not increment while the hart in operating in (H)S-mode. + description: + When set, mhpmcounter26 does not increment while the hart in operating + in (H)S-mode. type(): | if (HPM_COUNTER_EN[26] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -74,7 +79,9 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: When set, mhpmcounter26 does not increment while the hart in operating in U-mode. + description: + When set, mhpmcounter26 does not increment while the hart in operating + in U-mode. type(): | if (HPM_COUNTER_EN[26] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -90,7 +97,9 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: When set, mhpmcounter26 does not increment while the hart in operating in VS-mode. + description: + When set, mhpmcounter26 does not increment while the hart in operating + in VS-mode. type(): | if ((HPM_COUNTER_EN[26]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -106,7 +115,9 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: When set, mhpmcounter26 does not increment while the hart in operating in VU-mode. + description: + When set, mhpmcounter26 does not increment while the hart in operating + in VU-mode. type(): | if (HPM_COUNTER_EN[26] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent26h.yaml b/arch/csr/Zihpm/mhpmevent26h.yaml index 276bf866fa..473246d7d6 100644 --- a/arch/csr/Zihpm/mhpmevent26h.yaml +++ b/arch/csr/Zihpm/mhpmevent26h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent26h long_name: Machine Hardware Performance Counter 26 Control, High half address: 0x73A +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent27.yaml b/arch/csr/Zihpm/mhpmevent27.yaml index b8e7ba1d1b..17cf19420b 100644 --- a/arch/csr/Zihpm/mhpmevent27.yaml +++ b/arch/csr/Zihpm/mhpmevent27.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent27 long_name: Machine Hardware Performance Counter 27 Control address: 0x33B +writeable: true priv_mode: M length: 64 description: | @@ -42,7 +43,9 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: When set, mhpmcounter27 does not increment while the hart in operating in M-mode. + description: + When set, mhpmcounter27 does not increment while the hart in operating + in M-mode. type(): | if (HPM_COUNTER_EN[27]) { return CsrFieldType::RW; @@ -58,7 +61,9 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: When set, mhpmcounter27 does not increment while the hart in operating in (H)S-mode. + description: + When set, mhpmcounter27 does not increment while the hart in operating + in (H)S-mode. type(): | if (HPM_COUNTER_EN[27] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -74,7 +79,9 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: When set, mhpmcounter27 does not increment while the hart in operating in U-mode. + description: + When set, mhpmcounter27 does not increment while the hart in operating + in U-mode. type(): | if (HPM_COUNTER_EN[27] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -90,7 +97,9 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: When set, mhpmcounter27 does not increment while the hart in operating in VS-mode. + description: + When set, mhpmcounter27 does not increment while the hart in operating + in VS-mode. type(): | if ((HPM_COUNTER_EN[27]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -106,7 +115,9 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: When set, mhpmcounter27 does not increment while the hart in operating in VU-mode. + description: + When set, mhpmcounter27 does not increment while the hart in operating + in VU-mode. type(): | if (HPM_COUNTER_EN[27] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent27h.yaml b/arch/csr/Zihpm/mhpmevent27h.yaml index f5136e8ec1..a2b4fe543f 100644 --- a/arch/csr/Zihpm/mhpmevent27h.yaml +++ b/arch/csr/Zihpm/mhpmevent27h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent27h long_name: Machine Hardware Performance Counter 27 Control, High half address: 0x73B +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent28.yaml b/arch/csr/Zihpm/mhpmevent28.yaml index f9485190e1..dbd7c64764 100644 --- a/arch/csr/Zihpm/mhpmevent28.yaml +++ b/arch/csr/Zihpm/mhpmevent28.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent28 long_name: Machine Hardware Performance Counter 28 Control address: 0x33C +writeable: true priv_mode: M length: 64 description: | @@ -42,7 +43,9 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: When set, mhpmcounter28 does not increment while the hart in operating in M-mode. + description: + When set, mhpmcounter28 does not increment while the hart in operating + in M-mode. type(): | if (HPM_COUNTER_EN[28]) { return CsrFieldType::RW; @@ -58,7 +61,9 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: When set, mhpmcounter28 does not increment while the hart in operating in (H)S-mode. + description: + When set, mhpmcounter28 does not increment while the hart in operating + in (H)S-mode. type(): | if (HPM_COUNTER_EN[28] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -74,7 +79,9 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: When set, mhpmcounter28 does not increment while the hart in operating in U-mode. + description: + When set, mhpmcounter28 does not increment while the hart in operating + in U-mode. type(): | if (HPM_COUNTER_EN[28] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -90,7 +97,9 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: When set, mhpmcounter28 does not increment while the hart in operating in VS-mode. + description: + When set, mhpmcounter28 does not increment while the hart in operating + in VS-mode. type(): | if ((HPM_COUNTER_EN[28]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -106,7 +115,9 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: When set, mhpmcounter28 does not increment while the hart in operating in VU-mode. + description: + When set, mhpmcounter28 does not increment while the hart in operating + in VU-mode. type(): | if (HPM_COUNTER_EN[28] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent28h.yaml b/arch/csr/Zihpm/mhpmevent28h.yaml index 6f5b083ed0..fd6c54518f 100644 --- a/arch/csr/Zihpm/mhpmevent28h.yaml +++ b/arch/csr/Zihpm/mhpmevent28h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent28h long_name: Machine Hardware Performance Counter 28 Control, High half address: 0x73C +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent29.yaml b/arch/csr/Zihpm/mhpmevent29.yaml index 007d149878..4dc6b80504 100644 --- a/arch/csr/Zihpm/mhpmevent29.yaml +++ b/arch/csr/Zihpm/mhpmevent29.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent29 long_name: Machine Hardware Performance Counter 29 Control address: 0x33D +writeable: true priv_mode: M length: 64 description: | @@ -42,7 +43,9 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: When set, mhpmcounter29 does not increment while the hart in operating in M-mode. + description: + When set, mhpmcounter29 does not increment while the hart in operating + in M-mode. type(): | if (HPM_COUNTER_EN[29]) { return CsrFieldType::RW; @@ -58,7 +61,9 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: When set, mhpmcounter29 does not increment while the hart in operating in (H)S-mode. + description: + When set, mhpmcounter29 does not increment while the hart in operating + in (H)S-mode. type(): | if (HPM_COUNTER_EN[29] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -74,7 +79,9 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: When set, mhpmcounter29 does not increment while the hart in operating in U-mode. + description: + When set, mhpmcounter29 does not increment while the hart in operating + in U-mode. type(): | if (HPM_COUNTER_EN[29] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -90,7 +97,9 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: When set, mhpmcounter29 does not increment while the hart in operating in VS-mode. + description: + When set, mhpmcounter29 does not increment while the hart in operating + in VS-mode. type(): | if ((HPM_COUNTER_EN[29]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -106,7 +115,9 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: When set, mhpmcounter29 does not increment while the hart in operating in VU-mode. + description: + When set, mhpmcounter29 does not increment while the hart in operating + in VU-mode. type(): | if (HPM_COUNTER_EN[29] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent29h.yaml b/arch/csr/Zihpm/mhpmevent29h.yaml index 11c6f67d7f..7b122a09b8 100644 --- a/arch/csr/Zihpm/mhpmevent29h.yaml +++ b/arch/csr/Zihpm/mhpmevent29h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent29h long_name: Machine Hardware Performance Counter 29 Control, High half address: 0x73D +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent3.yaml b/arch/csr/Zihpm/mhpmevent3.yaml index bf6237f551..4ce4fd0c75 100644 --- a/arch/csr/Zihpm/mhpmevent3.yaml +++ b/arch/csr/Zihpm/mhpmevent3.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent3 long_name: Machine Hardware Performance Counter 3 Control address: 0x323 +writeable: true priv_mode: M length: 64 description: | @@ -42,7 +43,9 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: When set, mhpmcounter3 does not increment while the hart in operating in M-mode. + description: + When set, mhpmcounter3 does not increment while the hart in operating + in M-mode. type(): | if (HPM_COUNTER_EN[3]) { return CsrFieldType::RW; @@ -58,7 +61,9 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: When set, mhpmcounter3 does not increment while the hart in operating in (H)S-mode. + description: + When set, mhpmcounter3 does not increment while the hart in operating + in (H)S-mode. type(): | if (HPM_COUNTER_EN[3] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -74,7 +79,9 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: When set, mhpmcounter3 does not increment while the hart in operating in U-mode. + description: + When set, mhpmcounter3 does not increment while the hart in operating + in U-mode. type(): | if (HPM_COUNTER_EN[3] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -90,7 +97,9 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: When set, mhpmcounter3 does not increment while the hart in operating in VS-mode. + description: + When set, mhpmcounter3 does not increment while the hart in operating + in VS-mode. type(): | if ((HPM_COUNTER_EN[3]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -106,7 +115,9 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: When set, mhpmcounter3 does not increment while the hart in operating in VU-mode. + description: + When set, mhpmcounter3 does not increment while the hart in operating + in VU-mode. type(): | if (HPM_COUNTER_EN[3] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent30.yaml b/arch/csr/Zihpm/mhpmevent30.yaml index 6d59261234..f1f3ed0824 100644 --- a/arch/csr/Zihpm/mhpmevent30.yaml +++ b/arch/csr/Zihpm/mhpmevent30.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent30 long_name: Machine Hardware Performance Counter 30 Control address: 0x33E +writeable: true priv_mode: M length: 64 description: | @@ -42,7 +43,9 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: When set, mhpmcounter30 does not increment while the hart in operating in M-mode. + description: + When set, mhpmcounter30 does not increment while the hart in operating + in M-mode. type(): | if (HPM_COUNTER_EN[30]) { return CsrFieldType::RW; @@ -58,7 +61,9 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: When set, mhpmcounter30 does not increment while the hart in operating in (H)S-mode. + description: + When set, mhpmcounter30 does not increment while the hart in operating + in (H)S-mode. type(): | if (HPM_COUNTER_EN[30] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -74,7 +79,9 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: When set, mhpmcounter30 does not increment while the hart in operating in U-mode. + description: + When set, mhpmcounter30 does not increment while the hart in operating + in U-mode. type(): | if (HPM_COUNTER_EN[30] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -90,7 +97,9 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: When set, mhpmcounter30 does not increment while the hart in operating in VS-mode. + description: + When set, mhpmcounter30 does not increment while the hart in operating + in VS-mode. type(): | if ((HPM_COUNTER_EN[30]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -106,7 +115,9 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: When set, mhpmcounter30 does not increment while the hart in operating in VU-mode. + description: + When set, mhpmcounter30 does not increment while the hart in operating + in VU-mode. type(): | if (HPM_COUNTER_EN[30] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent30h.yaml b/arch/csr/Zihpm/mhpmevent30h.yaml index 27b55926c8..8b277b4a47 100644 --- a/arch/csr/Zihpm/mhpmevent30h.yaml +++ b/arch/csr/Zihpm/mhpmevent30h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent30h long_name: Machine Hardware Performance Counter 30 Control, High half address: 0x73E +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent31.yaml b/arch/csr/Zihpm/mhpmevent31.yaml index 37b8593076..e0ac7f2dc3 100644 --- a/arch/csr/Zihpm/mhpmevent31.yaml +++ b/arch/csr/Zihpm/mhpmevent31.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent31 long_name: Machine Hardware Performance Counter 31 Control address: 0x33F +writeable: true priv_mode: M length: 64 description: | @@ -42,7 +43,9 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: When set, mhpmcounter31 does not increment while the hart in operating in M-mode. + description: + When set, mhpmcounter31 does not increment while the hart in operating + in M-mode. type(): | if (HPM_COUNTER_EN[31]) { return CsrFieldType::RW; @@ -58,7 +61,9 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: When set, mhpmcounter31 does not increment while the hart in operating in (H)S-mode. + description: + When set, mhpmcounter31 does not increment while the hart in operating + in (H)S-mode. type(): | if (HPM_COUNTER_EN[31] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -74,7 +79,9 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: When set, mhpmcounter31 does not increment while the hart in operating in U-mode. + description: + When set, mhpmcounter31 does not increment while the hart in operating + in U-mode. type(): | if (HPM_COUNTER_EN[31] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -90,7 +97,9 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: When set, mhpmcounter31 does not increment while the hart in operating in VS-mode. + description: + When set, mhpmcounter31 does not increment while the hart in operating + in VS-mode. type(): | if ((HPM_COUNTER_EN[31]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -106,7 +115,9 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: When set, mhpmcounter31 does not increment while the hart in operating in VU-mode. + description: + When set, mhpmcounter31 does not increment while the hart in operating + in VU-mode. type(): | if (HPM_COUNTER_EN[31] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent31h.yaml b/arch/csr/Zihpm/mhpmevent31h.yaml index 0dca0fbe7f..c39151a2ea 100644 --- a/arch/csr/Zihpm/mhpmevent31h.yaml +++ b/arch/csr/Zihpm/mhpmevent31h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent31h long_name: Machine Hardware Performance Counter 31 Control, High half address: 0x73F +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent3h.yaml b/arch/csr/Zihpm/mhpmevent3h.yaml index b92a0a8e0c..a5f437fe81 100644 --- a/arch/csr/Zihpm/mhpmevent3h.yaml +++ b/arch/csr/Zihpm/mhpmevent3h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent3h long_name: Machine Hardware Performance Counter 3 Control, High half address: 0x723 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent4.yaml b/arch/csr/Zihpm/mhpmevent4.yaml index 1291ed96f6..12421c0936 100644 --- a/arch/csr/Zihpm/mhpmevent4.yaml +++ b/arch/csr/Zihpm/mhpmevent4.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent4 long_name: Machine Hardware Performance Counter 4 Control address: 0x324 +writeable: true priv_mode: M length: 64 description: | @@ -42,7 +43,9 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: When set, mhpmcounter4 does not increment while the hart in operating in M-mode. + description: + When set, mhpmcounter4 does not increment while the hart in operating + in M-mode. type(): | if (HPM_COUNTER_EN[4]) { return CsrFieldType::RW; @@ -58,7 +61,9 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: When set, mhpmcounter4 does not increment while the hart in operating in (H)S-mode. + description: + When set, mhpmcounter4 does not increment while the hart in operating + in (H)S-mode. type(): | if (HPM_COUNTER_EN[4] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -74,7 +79,9 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: When set, mhpmcounter4 does not increment while the hart in operating in U-mode. + description: + When set, mhpmcounter4 does not increment while the hart in operating + in U-mode. type(): | if (HPM_COUNTER_EN[4] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -90,7 +97,9 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: When set, mhpmcounter4 does not increment while the hart in operating in VS-mode. + description: + When set, mhpmcounter4 does not increment while the hart in operating + in VS-mode. type(): | if ((HPM_COUNTER_EN[4]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -106,7 +115,9 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: When set, mhpmcounter4 does not increment while the hart in operating in VU-mode. + description: + When set, mhpmcounter4 does not increment while the hart in operating + in VU-mode. type(): | if (HPM_COUNTER_EN[4] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent4h.yaml b/arch/csr/Zihpm/mhpmevent4h.yaml index e70ed1280d..74e0bc4ac1 100644 --- a/arch/csr/Zihpm/mhpmevent4h.yaml +++ b/arch/csr/Zihpm/mhpmevent4h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent4h long_name: Machine Hardware Performance Counter 4 Control, High half address: 0x724 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent5.yaml b/arch/csr/Zihpm/mhpmevent5.yaml index bbe2824f5c..bf0ffe5775 100644 --- a/arch/csr/Zihpm/mhpmevent5.yaml +++ b/arch/csr/Zihpm/mhpmevent5.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent5 long_name: Machine Hardware Performance Counter 5 Control address: 0x325 +writeable: true priv_mode: M length: 64 description: | @@ -42,7 +43,9 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: When set, mhpmcounter5 does not increment while the hart in operating in M-mode. + description: + When set, mhpmcounter5 does not increment while the hart in operating + in M-mode. type(): | if (HPM_COUNTER_EN[5]) { return CsrFieldType::RW; @@ -58,7 +61,9 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: When set, mhpmcounter5 does not increment while the hart in operating in (H)S-mode. + description: + When set, mhpmcounter5 does not increment while the hart in operating + in (H)S-mode. type(): | if (HPM_COUNTER_EN[5] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -74,7 +79,9 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: When set, mhpmcounter5 does not increment while the hart in operating in U-mode. + description: + When set, mhpmcounter5 does not increment while the hart in operating + in U-mode. type(): | if (HPM_COUNTER_EN[5] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -90,7 +97,9 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: When set, mhpmcounter5 does not increment while the hart in operating in VS-mode. + description: + When set, mhpmcounter5 does not increment while the hart in operating + in VS-mode. type(): | if ((HPM_COUNTER_EN[5]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -106,7 +115,9 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: When set, mhpmcounter5 does not increment while the hart in operating in VU-mode. + description: + When set, mhpmcounter5 does not increment while the hart in operating + in VU-mode. type(): | if (HPM_COUNTER_EN[5] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent5h.yaml b/arch/csr/Zihpm/mhpmevent5h.yaml index b8db07f6f7..f8347cf95f 100644 --- a/arch/csr/Zihpm/mhpmevent5h.yaml +++ b/arch/csr/Zihpm/mhpmevent5h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent5h long_name: Machine Hardware Performance Counter 5 Control, High half address: 0x725 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent6.yaml b/arch/csr/Zihpm/mhpmevent6.yaml index f4e0b15cb9..2e6240c7aa 100644 --- a/arch/csr/Zihpm/mhpmevent6.yaml +++ b/arch/csr/Zihpm/mhpmevent6.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent6 long_name: Machine Hardware Performance Counter 6 Control address: 0x326 +writeable: true priv_mode: M length: 64 description: | @@ -42,7 +43,9 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: When set, mhpmcounter6 does not increment while the hart in operating in M-mode. + description: + When set, mhpmcounter6 does not increment while the hart in operating + in M-mode. type(): | if (HPM_COUNTER_EN[6]) { return CsrFieldType::RW; @@ -58,7 +61,9 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: When set, mhpmcounter6 does not increment while the hart in operating in (H)S-mode. + description: + When set, mhpmcounter6 does not increment while the hart in operating + in (H)S-mode. type(): | if (HPM_COUNTER_EN[6] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -74,7 +79,9 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: When set, mhpmcounter6 does not increment while the hart in operating in U-mode. + description: + When set, mhpmcounter6 does not increment while the hart in operating + in U-mode. type(): | if (HPM_COUNTER_EN[6] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -90,7 +97,9 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: When set, mhpmcounter6 does not increment while the hart in operating in VS-mode. + description: + When set, mhpmcounter6 does not increment while the hart in operating + in VS-mode. type(): | if ((HPM_COUNTER_EN[6]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -106,7 +115,9 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: When set, mhpmcounter6 does not increment while the hart in operating in VU-mode. + description: + When set, mhpmcounter6 does not increment while the hart in operating + in VU-mode. type(): | if (HPM_COUNTER_EN[6] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent6h.yaml b/arch/csr/Zihpm/mhpmevent6h.yaml index d6e9003aa5..1708de0339 100644 --- a/arch/csr/Zihpm/mhpmevent6h.yaml +++ b/arch/csr/Zihpm/mhpmevent6h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent6h long_name: Machine Hardware Performance Counter 6 Control, High half address: 0x726 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent7.yaml b/arch/csr/Zihpm/mhpmevent7.yaml index c4586b60bd..e4d4b06fcd 100644 --- a/arch/csr/Zihpm/mhpmevent7.yaml +++ b/arch/csr/Zihpm/mhpmevent7.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent7 long_name: Machine Hardware Performance Counter 7 Control address: 0x327 +writeable: true priv_mode: M length: 64 description: | @@ -42,7 +43,9 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: When set, mhpmcounter7 does not increment while the hart in operating in M-mode. + description: + When set, mhpmcounter7 does not increment while the hart in operating + in M-mode. type(): | if (HPM_COUNTER_EN[7]) { return CsrFieldType::RW; @@ -58,7 +61,9 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: When set, mhpmcounter7 does not increment while the hart in operating in (H)S-mode. + description: + When set, mhpmcounter7 does not increment while the hart in operating + in (H)S-mode. type(): | if (HPM_COUNTER_EN[7] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -74,7 +79,9 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: When set, mhpmcounter7 does not increment while the hart in operating in U-mode. + description: + When set, mhpmcounter7 does not increment while the hart in operating + in U-mode. type(): | if (HPM_COUNTER_EN[7] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -90,7 +97,9 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: When set, mhpmcounter7 does not increment while the hart in operating in VS-mode. + description: + When set, mhpmcounter7 does not increment while the hart in operating + in VS-mode. type(): | if ((HPM_COUNTER_EN[7]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -106,7 +115,9 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: When set, mhpmcounter7 does not increment while the hart in operating in VU-mode. + description: + When set, mhpmcounter7 does not increment while the hart in operating + in VU-mode. type(): | if (HPM_COUNTER_EN[7] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent7h.yaml b/arch/csr/Zihpm/mhpmevent7h.yaml index f04327a66b..03a01a2d3a 100644 --- a/arch/csr/Zihpm/mhpmevent7h.yaml +++ b/arch/csr/Zihpm/mhpmevent7h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent7h long_name: Machine Hardware Performance Counter 7 Control, High half address: 0x727 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent8.yaml b/arch/csr/Zihpm/mhpmevent8.yaml index 349fc9ca30..a3dc41f854 100644 --- a/arch/csr/Zihpm/mhpmevent8.yaml +++ b/arch/csr/Zihpm/mhpmevent8.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent8 long_name: Machine Hardware Performance Counter 8 Control address: 0x328 +writeable: true priv_mode: M length: 64 description: | @@ -42,7 +43,9 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: When set, mhpmcounter8 does not increment while the hart in operating in M-mode. + description: + When set, mhpmcounter8 does not increment while the hart in operating + in M-mode. type(): | if (HPM_COUNTER_EN[8]) { return CsrFieldType::RW; @@ -58,7 +61,9 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: When set, mhpmcounter8 does not increment while the hart in operating in (H)S-mode. + description: + When set, mhpmcounter8 does not increment while the hart in operating + in (H)S-mode. type(): | if (HPM_COUNTER_EN[8] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -74,7 +79,9 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: When set, mhpmcounter8 does not increment while the hart in operating in U-mode. + description: + When set, mhpmcounter8 does not increment while the hart in operating + in U-mode. type(): | if (HPM_COUNTER_EN[8] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -90,7 +97,9 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: When set, mhpmcounter8 does not increment while the hart in operating in VS-mode. + description: + When set, mhpmcounter8 does not increment while the hart in operating + in VS-mode. type(): | if ((HPM_COUNTER_EN[8]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -106,7 +115,9 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: When set, mhpmcounter8 does not increment while the hart in operating in VU-mode. + description: + When set, mhpmcounter8 does not increment while the hart in operating + in VU-mode. type(): | if (HPM_COUNTER_EN[8] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent8h.yaml b/arch/csr/Zihpm/mhpmevent8h.yaml index 0370dc3186..44b58d6c41 100644 --- a/arch/csr/Zihpm/mhpmevent8h.yaml +++ b/arch/csr/Zihpm/mhpmevent8h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent8h long_name: Machine Hardware Performance Counter 8 Control, High half address: 0x728 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent9.yaml b/arch/csr/Zihpm/mhpmevent9.yaml index fc947e3e2d..1d2a7a1ccc 100644 --- a/arch/csr/Zihpm/mhpmevent9.yaml +++ b/arch/csr/Zihpm/mhpmevent9.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent9 long_name: Machine Hardware Performance Counter 9 Control address: 0x329 +writeable: true priv_mode: M length: 64 description: | @@ -42,7 +43,9 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: When set, mhpmcounter9 does not increment while the hart in operating in M-mode. + description: + When set, mhpmcounter9 does not increment while the hart in operating + in M-mode. type(): | if (HPM_COUNTER_EN[9]) { return CsrFieldType::RW; @@ -58,7 +61,9 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: When set, mhpmcounter9 does not increment while the hart in operating in (H)S-mode. + description: + When set, mhpmcounter9 does not increment while the hart in operating + in (H)S-mode. type(): | if (HPM_COUNTER_EN[9] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -74,7 +79,9 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: When set, mhpmcounter9 does not increment while the hart in operating in U-mode. + description: + When set, mhpmcounter9 does not increment while the hart in operating + in U-mode. type(): | if (HPM_COUNTER_EN[9] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -90,7 +97,9 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: When set, mhpmcounter9 does not increment while the hart in operating in VS-mode. + description: + When set, mhpmcounter9 does not increment while the hart in operating + in VS-mode. type(): | if ((HPM_COUNTER_EN[9]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -106,7 +115,9 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: When set, mhpmcounter9 does not increment while the hart in operating in VU-mode. + description: + When set, mhpmcounter9 does not increment while the hart in operating + in VU-mode. type(): | if (HPM_COUNTER_EN[9] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent9h.yaml b/arch/csr/Zihpm/mhpmevent9h.yaml index 946464b3b0..7383b28c30 100644 --- a/arch/csr/Zihpm/mhpmevent9h.yaml +++ b/arch/csr/Zihpm/mhpmevent9h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent9h long_name: Machine Hardware Performance Counter 9 Control, High half address: 0x729 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/cycle.yaml b/arch/csr/cycle.yaml index 0d7d975cf5..7d2b493245 100644 --- a/arch/csr/cycle.yaml +++ b/arch/csr/cycle.yaml @@ -5,6 +5,7 @@ kind: csr name: cycle long_name: Cycle counter for RDCYCLE Instruction address: 0xC00 +writeable: false description: | Alias for M-mode CSR `mcycle`. diff --git a/arch/csr/cycleh.yaml b/arch/csr/cycleh.yaml index 75ed1b438d..770a46e1b2 100644 --- a/arch/csr/cycleh.yaml +++ b/arch/csr/cycleh.yaml @@ -5,6 +5,7 @@ kind: csr name: cycleh long_name: High-half cycle counter for RDCYCLE Instruction address: 0xC80 +writeable: false base: 32 description: | Alias for M-mode CSR `mcycleh`. diff --git a/arch/csr/hedeleg.yaml b/arch/csr/hedeleg.yaml index f0eb50f396..e50da89a4e 100644 --- a/arch/csr/hedeleg.yaml +++ b/arch/csr/hedeleg.yaml @@ -5,6 +5,7 @@ kind: csr name: hedeleg long_name: Hypervisor Exception Delegation address: 0x602 +writeable: true priv_mode: S length: 64 description: | diff --git a/arch/csr/hedelegh.yaml b/arch/csr/hedelegh.yaml index fc1ad672eb..abe635b742 100644 --- a/arch/csr/hedelegh.yaml +++ b/arch/csr/hedelegh.yaml @@ -5,6 +5,7 @@ kind: csr name: hedelegh long_name: Hypervisor Exception Delegation High address: 0x612 +writeable: true base: 32 priv_mode: S length: 32 diff --git a/arch/csr/hstatus.yaml b/arch/csr/hstatus.yaml index a19aa4bc8f..5f80128965 100644 --- a/arch/csr/hstatus.yaml +++ b/arch/csr/hstatus.yaml @@ -5,6 +5,7 @@ kind: csr name: hstatus long_name: Hypervisor Status address: 0x600 +writeable: true priv_mode: S length: SXLEN description: | diff --git a/arch/csr/instret.yaml b/arch/csr/instret.yaml index b54fedf8d9..2e2be9a645 100644 --- a/arch/csr/instret.yaml +++ b/arch/csr/instret.yaml @@ -5,6 +5,7 @@ kind: csr name: instret long_name: Instructions retired counter for RDINSTRET Instruction address: 0xC02 +writeable: false description: | Alias for M-mode CSR `minstret`. diff --git a/arch/csr/instreth.yaml b/arch/csr/instreth.yaml index bb4df78053..0283bbc389 100644 --- a/arch/csr/instreth.yaml +++ b/arch/csr/instreth.yaml @@ -5,6 +5,7 @@ kind: csr name: instreth long_name: Instructions retired counter, high bits address: 0xC82 +writeable: false base: 32 description: | Alias for high bits of M-mode CSR `minstret`[63:32]. diff --git a/arch/csr/marchid.yaml b/arch/csr/marchid.yaml index fc7e8d8dd1..88e9f5ec1a 100644 --- a/arch/csr/marchid.yaml +++ b/arch/csr/marchid.yaml @@ -5,6 +5,7 @@ kind: csr name: marchid long_name: Machine Architecture ID address: 0xf12 +writeable: false priv_mode: M length: MXLEN description: | diff --git a/arch/csr/mcause.yaml b/arch/csr/mcause.yaml index 11b8b07d58..0f7666d662 100644 --- a/arch/csr/mcause.yaml +++ b/arch/csr/mcause.yaml @@ -5,6 +5,7 @@ kind: csr name: mcause long_name: Machine Cause address: 0x342 +writeable: true priv_mode: M length: MXLEN description: Reports the cause of the latest exception. diff --git a/arch/csr/mconfigptr.yaml b/arch/csr/mconfigptr.yaml index 96ef26a416..14ab0d3d6b 100644 --- a/arch/csr/mconfigptr.yaml +++ b/arch/csr/mconfigptr.yaml @@ -5,6 +5,7 @@ kind: csr name: mconfigptr long_name: Machine Configuration Pointer address: 0xF15 +writeable: false description: | Holds a physical address pointer to the unified discovery data structure in Memory. @@ -45,7 +46,9 @@ fields: ADDRESS: location_rv32: 31-0 location_rv64: 63-0 - description: Pointer to physical address of the Unified Discovery configuration data structure. + description: + Pointer to physical address of the Unified Discovery configuration + data structure. type: RO reset_value(): | return CONFIG_PTR_ADDRESS; diff --git a/arch/csr/mcycle.yaml b/arch/csr/mcycle.yaml index 8fb8102f8b..c36433fcf4 100644 --- a/arch/csr/mcycle.yaml +++ b/arch/csr/mcycle.yaml @@ -6,6 +6,7 @@ name: mcycle long_name: Machine Cycle Counter definedBy: Zicntr address: 0xB00 +writeable: true description: | Counts the number of clock cycles executed by the processor core on which the hart is running. diff --git a/arch/csr/mcycleh.yaml b/arch/csr/mcycleh.yaml index fb1798174f..0de21583c1 100644 --- a/arch/csr/mcycleh.yaml +++ b/arch/csr/mcycleh.yaml @@ -6,6 +6,7 @@ name: mcycleh long_name: High-half machine Cycle Counter definedBy: Zicntr address: 0xB80 +writeable: true description: | High-half alias of `mcycle`. priv_mode: M diff --git a/arch/csr/medeleg.yaml b/arch/csr/medeleg.yaml index 94b6981d04..134ba8baaa 100644 --- a/arch/csr/medeleg.yaml +++ b/arch/csr/medeleg.yaml @@ -5,6 +5,7 @@ kind: csr name: medeleg long_name: Machine Exception Delegation address: 0x302 +writeable: true priv_mode: M length: 64 description: | diff --git a/arch/csr/medelegh.yaml b/arch/csr/medelegh.yaml index bff63b2b0f..e481d906af 100644 --- a/arch/csr/medelegh.yaml +++ b/arch/csr/medelegh.yaml @@ -5,6 +5,7 @@ kind: csr name: medelegh long_name: Machine Exception Delegation, High bits address: 0x312 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/menvcfg.yaml b/arch/csr/menvcfg.yaml index 8feafff958..f2ea62adea 100644 --- a/arch/csr/menvcfg.yaml +++ b/arch/csr/menvcfg.yaml @@ -4,6 +4,7 @@ $schema: "csr_schema.json#" kind: csr name: menvcfg address: 0x30A +writeable: true long_name: Machine Environment Configuration description: | Contains fields that control certain characteristics of the execution environment diff --git a/arch/csr/menvcfgh.yaml b/arch/csr/menvcfgh.yaml index 3543f9ea6f..541ff71339 100644 --- a/arch/csr/menvcfgh.yaml +++ b/arch/csr/menvcfgh.yaml @@ -4,6 +4,7 @@ $schema: "csr_schema.json#" kind: csr name: menvcfgh address: 0x31A +writeable: true base: 32 long_name: Machine Environment Configuration description: Contains bits to enable/disable extensions diff --git a/arch/csr/mepc.yaml b/arch/csr/mepc.yaml index 3118fee37a..92ca5c9314 100644 --- a/arch/csr/mepc.yaml +++ b/arch/csr/mepc.yaml @@ -5,6 +5,7 @@ kind: csr name: mepc long_name: Machine Exception Program Counter address: 0x341 +writeable: true priv_mode: M length: MXLEN description: | diff --git a/arch/csr/mhartid.yaml b/arch/csr/mhartid.yaml index 8b5e50793d..6fb026ff41 100644 --- a/arch/csr/mhartid.yaml +++ b/arch/csr/mhartid.yaml @@ -5,6 +5,7 @@ kind: csr name: mhartid long_name: Machine Hart ID address: 0xf14 +writeable: false priv_mode: M length: MXLEN description: Reports the unique hart-specific ID in the system. diff --git a/arch/csr/mideleg.yaml b/arch/csr/mideleg.yaml index af53608a13..a6b0abf963 100644 --- a/arch/csr/mideleg.yaml +++ b/arch/csr/mideleg.yaml @@ -5,6 +5,7 @@ kind: csr name: mideleg long_name: Machine Interrupt Delegation address: 0x303 +writeable: true priv_mode: M length: MXLEN definedBy: diff --git a/arch/csr/mie.yaml b/arch/csr/mie.yaml index 927ed583c8..d65abf2476 100644 --- a/arch/csr/mie.yaml +++ b/arch/csr/mie.yaml @@ -5,6 +5,7 @@ kind: csr name: mie long_name: Machine Interrupt Enable address: 0x304 +writeable: true priv_mode: M length: MXLEN definedBy: Sm diff --git a/arch/csr/mimpid.yaml b/arch/csr/mimpid.yaml index 4d35e45c79..1c9bd58844 100644 --- a/arch/csr/mimpid.yaml +++ b/arch/csr/mimpid.yaml @@ -5,6 +5,7 @@ kind: csr name: mimpid long_name: Machine Implementation ID address: 0xf13 +writeable: false priv_mode: M length: MXLEN description: | diff --git a/arch/csr/minstret.yaml b/arch/csr/minstret.yaml index 9d4344a1c2..2c28fddf30 100644 --- a/arch/csr/minstret.yaml +++ b/arch/csr/minstret.yaml @@ -5,6 +5,7 @@ kind: csr name: minstret long_name: Machine Instructions Retired Counter address: 0xB02 +writeable: true description: | Counts the number of instructions retired by this hart from some arbitrary start point in the past. diff --git a/arch/csr/minstreth.yaml b/arch/csr/minstreth.yaml index 0df4282594..97cb2f6a27 100644 --- a/arch/csr/minstreth.yaml +++ b/arch/csr/minstreth.yaml @@ -5,6 +5,7 @@ kind: csr name: minstreth long_name: Machine Instructions Retired Counter address: 0xB82 +writeable: true description: | Upper half of 64-bit instructions retired counters. diff --git a/arch/csr/mip.yaml b/arch/csr/mip.yaml index 4d831856b4..954f27ff55 100644 --- a/arch/csr/mip.yaml +++ b/arch/csr/mip.yaml @@ -5,6 +5,7 @@ kind: csr name: mip long_name: Machine Interrupt Pending address: 0x344 +writeable: true priv_mode: M # Description is shared with mie CSR (it copies it from here). diff --git a/arch/csr/misa.yaml b/arch/csr/misa.yaml index 4c554b6b06..a7c6cc8626 100644 --- a/arch/csr/misa.yaml +++ b/arch/csr/misa.yaml @@ -5,6 +5,7 @@ kind: csr name: misa long_name: Machine ISA Control address: 0x301 +writeable: true priv_mode: M length: MXLEN description: Reports the XLEN and "major" extensions supported by the ISA. diff --git a/arch/csr/mscratch.yaml b/arch/csr/mscratch.yaml index 544b6bce0c..9f126e1f0b 100644 --- a/arch/csr/mscratch.yaml +++ b/arch/csr/mscratch.yaml @@ -5,6 +5,7 @@ kind: csr name: mscratch long_name: Machine Scratch Register address: 0x340 +writeable: true priv_mode: M length: MXLEN description: Scratch register for software use. Bits are not interpreted by hardware. diff --git a/arch/csr/mseccfg.yaml b/arch/csr/mseccfg.yaml index bc76cd8864..209daa1047 100644 --- a/arch/csr/mseccfg.yaml +++ b/arch/csr/mseccfg.yaml @@ -5,6 +5,7 @@ kind: csr name: mseccfg long_name: Machine Security Configuration address: 0x747 +writeable: true priv_mode: M length: 64 description: Machine Security Configuration diff --git a/arch/csr/mseccfgh.yaml b/arch/csr/mseccfgh.yaml index 3f2330a5c7..b8f894eb05 100644 --- a/arch/csr/mseccfgh.yaml +++ b/arch/csr/mseccfgh.yaml @@ -6,6 +6,7 @@ name: mseccfgh long_name: Most significant 32 bits of Machine Security Configuration base: 32 address: 0x757 +writeable: true priv_mode: M length: 32 description: Machine Security Configuration diff --git a/arch/csr/mstatus.yaml b/arch/csr/mstatus.yaml index 84cd5695ac..23cac80778 100644 --- a/arch/csr/mstatus.yaml +++ b/arch/csr/mstatus.yaml @@ -5,6 +5,7 @@ kind: csr name: mstatus long_name: Machine Status address: 0x300 +writeable: true priv_mode: M # length is MXLEN-bit @@ -12,7 +13,9 @@ priv_mode: M # MXLEN cannot change dynamically, so this will be converted to an integer # in the generated, configuration-dependent spec length: MXLEN -description: The mstatus register tracks and controls the hart's current operating state. +description: + The mstatus register tracks and controls the hart's current operating + state. definedBy: Sm fields: SD: diff --git a/arch/csr/mstatush.yaml b/arch/csr/mstatush.yaml index 1b44ad800c..038a392a90 100644 --- a/arch/csr/mstatush.yaml +++ b/arch/csr/mstatush.yaml @@ -5,10 +5,13 @@ kind: csr name: mstatush long_name: Machine Status High address: 0x310 +writeable: true priv_mode: M base: 32 length: 32 -description: The mstatus register tracks and controls the hart's current operating state. +description: + The mstatus register tracks and controls the hart's current operating + state. definedBy: name: Sm version: ">= 1.12" diff --git a/arch/csr/mtval.yaml b/arch/csr/mtval.yaml index 71b0b9f1e2..cec0138e65 100644 --- a/arch/csr/mtval.yaml +++ b/arch/csr/mtval.yaml @@ -5,6 +5,7 @@ kind: csr name: mtval long_name: Machine Trap Value address: 0x343 +writeable: true description: Holds trap-specific information priv_mode: M length: MXLEN diff --git a/arch/csr/mtvec.yaml b/arch/csr/mtvec.yaml index 265f39fd3e..bf850afc1a 100644 --- a/arch/csr/mtvec.yaml +++ b/arch/csr/mtvec.yaml @@ -5,6 +5,7 @@ kind: csr name: mtvec long_name: Machine Trap Vector Control address: 0x305 +writeable: true priv_mode: M length: MXLEN description: Controls where traps jump. diff --git a/arch/csr/mvendorid.yaml b/arch/csr/mvendorid.yaml index a752ece2da..afd5144f07 100644 --- a/arch/csr/mvendorid.yaml +++ b/arch/csr/mvendorid.yaml @@ -5,6 +5,7 @@ kind: csr name: mvendorid long_name: Machine Vendor ID address: 0xf11 +writeable: false priv_mode: M length: 32 description: Reports the JEDEC manufacturer ID of the core. diff --git a/arch/csr/satp.yaml b/arch/csr/satp.yaml index b4d4a0d3a1..b5f4cf3dd6 100644 --- a/arch/csr/satp.yaml +++ b/arch/csr/satp.yaml @@ -4,8 +4,11 @@ $schema: "csr_schema.json#" kind: csr name: satp address: 0x180 +writeable: true long_name: Supervisor Address Translation and Protection -description: Controls the translation mode in (H)S-mode and U-mode, and holds the current ASID and page table base pointer. +description: + Controls the translation mode in (H)S-mode and U-mode, and holds the + current ASID and page table base pointer. priv_mode: S length: SXLEN definedBy: S diff --git a/arch/csr/scause.yaml b/arch/csr/scause.yaml index c206cd60de..9d25a7906a 100644 --- a/arch/csr/scause.yaml +++ b/arch/csr/scause.yaml @@ -5,6 +5,7 @@ kind: csr name: scause long_name: Supervisor Cause address: 0x142 +writeable: true priv_mode: S length: SXLEN description: Reports the cause of the latest exception. diff --git a/arch/csr/senvcfg.yaml b/arch/csr/senvcfg.yaml index 6feb151349..a142d371ce 100644 --- a/arch/csr/senvcfg.yaml +++ b/arch/csr/senvcfg.yaml @@ -4,6 +4,7 @@ $schema: "csr_schema.json#" kind: csr name: senvcfg address: 0x10A +writeable: true long_name: Supervisor Environment Configuration description: | Contains fields that control certain characteristics of the U-mode execution environment. diff --git a/arch/csr/sepc.yaml b/arch/csr/sepc.yaml index 82fae3a4b3..861f8747f3 100644 --- a/arch/csr/sepc.yaml +++ b/arch/csr/sepc.yaml @@ -5,6 +5,7 @@ kind: csr name: sepc long_name: Supervisor Exception Program Counter address: 0x141 +writeable: true priv_mode: S length: 64 description: | diff --git a/arch/csr/sip.yaml b/arch/csr/sip.yaml index 6de22310d6..f307cc34c5 100644 --- a/arch/csr/sip.yaml +++ b/arch/csr/sip.yaml @@ -5,6 +5,7 @@ kind: csr name: sip long_name: Supervisor Interrupt Pending address: 0x144 +writeable: true priv_mode: S description: | A restricted view of the interrupt pending bits in `mip`. diff --git a/arch/csr/sscratch.yaml b/arch/csr/sscratch.yaml index dceaf14863..4a3c6d405b 100644 --- a/arch/csr/sscratch.yaml +++ b/arch/csr/sscratch.yaml @@ -5,6 +5,7 @@ kind: csr name: sscratch long_name: Supervisor Scratch Register address: 0x140 +writeable: true priv_mode: S length: 64 description: Scratch register for software use. Bits are not interpreted by hardware. diff --git a/arch/csr/sstatus.yaml b/arch/csr/sstatus.yaml index c9ae22e33c..34d644689f 100644 --- a/arch/csr/sstatus.yaml +++ b/arch/csr/sstatus.yaml @@ -5,6 +5,7 @@ kind: csr name: sstatus long_name: Supervisor Status address: 0x100 +writeable: true priv_mode: S length: SXLEN description: | diff --git a/arch/csr/stval.yaml b/arch/csr/stval.yaml index fb447e5059..dddff978c9 100644 --- a/arch/csr/stval.yaml +++ b/arch/csr/stval.yaml @@ -5,6 +5,7 @@ kind: csr name: stval long_name: Supervisor Trap Value address: 0x143 +writeable: true description: Holds trap-specific information priv_mode: S length: 64 diff --git a/arch/csr/stvec.yaml b/arch/csr/stvec.yaml index 3432f8a89a..a77ace47c0 100644 --- a/arch/csr/stvec.yaml +++ b/arch/csr/stvec.yaml @@ -5,6 +5,7 @@ kind: csr name: stvec long_name: Supervisor Trap Vector address: 0x105 +writeable: true priv_mode: S length: 64 description: Controls where traps jump. diff --git a/arch/csr/time.yaml b/arch/csr/time.yaml index 5ebccad92d..2e64103e43 100644 --- a/arch/csr/time.yaml +++ b/arch/csr/time.yaml @@ -5,6 +5,7 @@ kind: csr name: time long_name: Timer for RDTIME Instruction address: 0xC01 +writeable: false description: | [when,"TIME_CSR_IMPLEMENTED == false"] This CSR does not exist, and access will cause an IllegalInstruction exception. diff --git a/arch/csr/timeh.yaml b/arch/csr/timeh.yaml index cdf1ff35be..26a2671597 100644 --- a/arch/csr/timeh.yaml +++ b/arch/csr/timeh.yaml @@ -5,6 +5,7 @@ kind: csr name: timeh long_name: High-half timer for RDTIME Instruction address: 0xC81 +writeable: false base: 32 description: | [when,"TIME_CSR_IMPLEMENTED == false"] diff --git a/arch/csr/vscause.yaml b/arch/csr/vscause.yaml index cfaf02d1dd..6d4c26472e 100644 --- a/arch/csr/vscause.yaml +++ b/arch/csr/vscause.yaml @@ -5,6 +5,7 @@ kind: csr name: vscause long_name: Virtual Supervisor Cause address: 0x242 +writeable: true virtual_address: 0x142 priv_mode: VS length: VSXLEN diff --git a/arch/csr/vsepc.yaml b/arch/csr/vsepc.yaml index 68c7e77d6a..49ff1bbd3e 100644 --- a/arch/csr/vsepc.yaml +++ b/arch/csr/vsepc.yaml @@ -5,6 +5,7 @@ kind: csr name: vsepc long_name: Virtual Supervisor Exception Program Counter address: 0x241 +writeable: true virtual_address: 0x141 priv_mode: VS length: 64 diff --git a/arch/csr/vsstatus.yaml b/arch/csr/vsstatus.yaml index 08287caa26..d1bebff3b4 100644 --- a/arch/csr/vsstatus.yaml +++ b/arch/csr/vsstatus.yaml @@ -5,6 +5,7 @@ kind: csr name: vsstatus long_name: Virtual Supervisor Status address: 0x200 +writeable: true virtual_address: 0x100 priv_mode: VS length: VSXLEN diff --git a/arch/csr/vstval.yaml b/arch/csr/vstval.yaml index 7baa9e8b16..131116cc5e 100644 --- a/arch/csr/vstval.yaml +++ b/arch/csr/vstval.yaml @@ -5,6 +5,7 @@ kind: csr name: vstval long_name: Virtual supervisor Trap Value address: 0x243 +writeable: true virtual_address: 0x143 description: Holds trap-specific information priv_mode: S diff --git a/arch/csr/vstvec.yaml b/arch/csr/vstvec.yaml index 4357ac5894..2405b748a8 100644 --- a/arch/csr/vstvec.yaml +++ b/arch/csr/vstvec.yaml @@ -5,6 +5,7 @@ kind: csr name: vstvec long_name: Supervisor Trap Vector address: 0x205 +writeable: true virtual_address: 0x105 priv_mode: S length: 64 diff --git a/schemas/csr_schema.json b/schemas/csr_schema.json index 6ef1790a77..a3f8100ec9 100644 --- a/schemas/csr_schema.json +++ b/schemas/csr_schema.json @@ -234,10 +234,9 @@ "type": "integer", "description": "Indirect address of the CSR, as given to the indirect CSRs of the `Smcsrind`/`Sscdrind` extensions" }, - "indirect": { + "writeable": { "type": "boolean", - "default": false, - "description": "Whether or not the CSR is accessible via an indirect address" + "description": "Whether or not the CSR can be written by software (i.e., is read-write)" }, "virtual_address": true, "$comment": "Conditionally required; see below", From bffee3f3601a18678900d4d59b95bf0107d9a8f4 Mon Sep 17 00:00:00 2001 From: Derek Hower Date: Fri, 4 Apr 2025 11:12:15 -0700 Subject: [PATCH 04/15] fix(ruby): corrects adoc generation for CSR read expressions --- backends/cpp_hart_gen/lib/gen_cpp.rb | 4 ++-- lib/idl/ast.rb | 34 +++++++++------------------- lib/idl/passes/gen_adoc.rb | 2 +- 3 files changed, 14 insertions(+), 26 deletions(-) diff --git a/backends/cpp_hart_gen/lib/gen_cpp.rb b/backends/cpp_hart_gen/lib/gen_cpp.rb index 87f4590422..d634551795 100644 --- a/backends/cpp_hart_gen/lib/gen_cpp.rb +++ b/backends/cpp_hart_gen/lib/gen_cpp.rb @@ -313,9 +313,9 @@ def gen_cpp(symtab, indent, indent_spaces: 2) field = csr_field.field_def(symtab) if symtab.cfg_arch.multi_xlen? && field.dynamic_location? - "#{' '*indent}__UDB_CSR_BY_NAME(#{csr_field.csr_name(symtab)}).#{field.name}()._hw_write(#{write_value.gen_cpp(symtab, 0, indent_spaces:)}, __UDB_XLEN)" + "#{' '*indent}__UDB_CSR_BY_NAME(#{csr_field.csr_name}).#{field.name}()._hw_write(#{write_value.gen_cpp(symtab, 0, indent_spaces:)}, __UDB_XLEN)" else - "#{' '*indent}__UDB_CSR_BY_NAME(#{csr_field.csr_name(symtab)}).#{field.name}()._hw_write(#{write_value.gen_cpp(symtab, 0, indent_spaces:)})" + "#{' '*indent}__UDB_CSR_BY_NAME(#{csr_field.csr_name}).#{field.name}()._hw_write(#{write_value.gen_cpp(symtab, 0, indent_spaces:)})" end end end diff --git a/lib/idl/ast.rb b/lib/idl/ast.rb index 17a135423f..db311061ac 100644 --- a/lib/idl/ast.rb +++ b/lib/idl/ast.rb @@ -6050,18 +6050,16 @@ def freeze_tree(symtab) def type_check(symtab) @csr.type_check(symtab) - type_error "CSR[#{csr_name(symtab)}] has no field named #{@field_name}" if field_def(symtab).nil? - type_error "CSR[#{csr_name(symtab)}].#{@field_name} is not defined in RV32" if symtab.cfg_arch.mxlen == 32 && !field_def(symtab).defined_in_base32? - type_error "CSR[#{csr_name(symtab)}].#{@field_name} is not defined in RV64" if symtab.cfg_arch.mxlen == 64 && !field_def(symtab).defined_in_base64? + type_error "CSR[#{csr_name}] has no field named #{@field_name}" if field_def(symtab).nil? + type_error "CSR[#{csr_name}].#{@field_name} is not defined in RV32" if symtab.cfg_arch.mxlen == 32 && !field_def(symtab).defined_in_base32? + type_error "CSR[#{csr_name}].#{@field_name} is not defined in RV64" if symtab.cfg_arch.mxlen == 64 && !field_def(symtab).defined_in_base64? end def csr_def(symtab) @csr_obj end - def csr_name(symtab) - csr_def(symtab).name - end + def csr_name = @csr.csr_name def field_def(symtab) @csr_obj.fields.find { |f| f.name == @field_name } @@ -6103,7 +6101,7 @@ def calc_type(symtab) # @!macro value def value(symtab) if @value.nil? - value_error "'#{csr_name(symtab)}.#{field_name(symtab)}' is not RO" + value_error "'#{csr_name}.#{field_name(symtab)}' is not RO" else @value end @@ -6115,7 +6113,7 @@ def calc_value(symtab) symtab.cfg_arch.possible_xlens.each do |effective_xlen| unless field_def(symtab).type(effective_xlen) == "RO" - value_error "'#{csr_name(symtab)}.#{field_name(symtab)}' is not RO" + value_error "'#{csr_name}.#{field_name(symtab)}' is not RO" end end @@ -6177,12 +6175,6 @@ def csr_known?(symtab) !csr_def(symtab).nil? end - def csr_name(symtab) - internal_error "No CSR" unless csr_known?(symtab) - - csr_def(symtab).name - end - # @!macro value def value(symtab) if symtab.cfg_arch.fully_configured? @@ -6190,7 +6182,7 @@ def value(symtab) else value_error "CSR is not defined" unless symtab.cfg_arch.csrs.any? { |icsr| icsr.name == @csr_obj.name } end - @csr_obj.fields.each { |f| value_error "#{csr_name(symtab)}.#{f.name} not RO" unless f.type(symtab) == "RO" } + @csr_obj.fields.each { |f| value_error "#{csr_name}.#{f.name} not RO" unless f.type(symtab) == "RO" } csr_def(symtab).fields.reduce(0) { |val, f| val | (f.value << f.location.begin) } end @@ -6231,9 +6223,7 @@ def csr_known?(symtab) csr.csr_known?(symtab) end - def csr_name(symtab) - csr.csr_name(symtab) - end + def csr_name = csr.csr_name # @!macro value def value(_symtab) @@ -6299,7 +6289,7 @@ def type(symtab) case function_name when "sw_read" if csr_known?(symtab) - l = cfg_arch.csr(csr.csr_name(symtab)).length + l = cfg_arch.csr(csr.csr_name).length Type.new(:bits, width: (l.nil? ? :unknown : l)) else Type.new(:bits, width: symtab.mxlen.nil? ? :unknown : symtab.mxlen) @@ -6317,9 +6307,7 @@ def csr_known?(symtab) csr.csr_known?(symtab) end - def csr_name(symtab) - csr.csr_name(symtab) - end + def csr_name = csr.csr_name def csr_def(symtab) csr.csr_def(symtab) @@ -6331,7 +6319,7 @@ def value(symtab) when "sw_read" value_error "CSR not knowable" unless csr_known?(symtab) cd = csr_def(symtab) - cd.fields.each { |f| value_error "#{csr_name(symtab)}.#{f.name} not RO" unless f.type(symtab) == "RO" } + cd.fields.each { |f| value_error "#{csr_name}.#{f.name} not RO" unless f.type(symtab) == "RO" } value_error "TODO: CSRs with sw_read function" when "address" diff --git a/lib/idl/passes/gen_adoc.rb b/lib/idl/passes/gen_adoc.rb index 355596e1d9..6b6fa43f00 100644 --- a/lib/idl/passes/gen_adoc.rb +++ b/lib/idl/passes/gen_adoc.rb @@ -299,7 +299,7 @@ def gen_adoc(indent = 0, indent_spaces: 2) class CsrReadExpressionAst def gen_adoc(indent = 0, indent_spaces: 2) - csr_text = "CSR[#{idx}]" + csr_text = "CSR[#{csr_name}]" "#{' '*indent}%%LINK%csr;#{csr_name};#{csr_text}%%" end end From 60addff300f7cffa958b8d260776caf54e3e3cf4 Mon Sep 17 00:00:00 2001 From: Derek Hower Date: Fri, 4 Apr 2025 10:41:53 -0700 Subject: [PATCH 05/15] test(idl): test:idl task takes config from enviornment This lets us test idl for any config from the command line: ./do test:idl qc_iu --- Rakefile | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/Rakefile b/Rakefile index 46a4361fd2..b33baa393f 100755 --- a/Rakefile +++ b/Rakefile @@ -238,18 +238,15 @@ namespace :test do puts "All files validate against their schema" end - task idl: ["#{$root}/.stamps/resolve-rv32.stamp", "#{$root}/.stamps/resolve-rv64.stamp"] do - print "Parsing IDL code for RV32..." - cfg_arch32 = cfg_arch_for("rv32") - puts "done" - - cfg_arch32.type_check + task :idl do + cfg = ENV["CFG"] + raise "Missing CFG enviornment variable" if cfg.nil? - print "Parsing IDL code for RV64..." - cfg_arch64 = cfg_arch_for("rv64") + print "Parsing IDL code for #{cfg}..." + cfg_arch = cfg_arch_for(cfg) puts "done" - cfg_arch64.type_check + cfg_arch.type_check puts "All IDL passed type checking" end @@ -410,6 +407,11 @@ namespace :test do Rake::Task["test:idl_compiler"].invoke Rake::Task["test:lib"].invoke Rake::Task["test:schema"].invoke + ENV["CFG"] = "rv32" + Rake::Task["test:idl"].invoke + ENV["CFG"] = "rv64" + Rake::Task["test:idl"].invoke + ENV["CFG"] = "qc_iu" Rake::Task["test:idl"].invoke Rake::Task["test:inst_encodings"].invoke end From 716b515cbbefbd61e179f5f941d87f2a6fdc0ee2 Mon Sep 17 00:00:00 2001 From: Derek Hower Date: Fri, 4 Apr 2025 10:44:27 -0700 Subject: [PATCH 06/15] idl: add indirect csr access; do direct csr access with functions This does three things: * Remove `CSR[expression]` syntax for direct CSR reads ** `CSR[csr_name]` still works * Adds `direct_csr_lookup`/`csr_{hw,sw}_{read,write}` functions to access a CSR with a direct address * Adds `indirect_csr_lookup` to access an indirect CSR with an indirect address --- arch/csr/Zihpm/hpmcounter10h.yaml | 1 - arch/csr/Zihpm/hpmcounter11h.yaml | 1 - arch/csr/Zihpm/hpmcounter12h.yaml | 1 - arch/csr/Zihpm/hpmcounter13h.yaml | 1 - arch/csr/Zihpm/hpmcounter14h.yaml | 1 - arch/csr/Zihpm/hpmcounter15h.yaml | 1 - arch/csr/Zihpm/hpmcounter16h.yaml | 1 - arch/csr/Zihpm/hpmcounter17h.yaml | 1 - arch/csr/Zihpm/hpmcounter18h.yaml | 1 - arch/csr/Zihpm/hpmcounter19h.yaml | 1 - arch/csr/Zihpm/hpmcounter20h.yaml | 1 - arch/csr/Zihpm/hpmcounter21h.yaml | 1 - arch/csr/Zihpm/hpmcounter22h.yaml | 1 - arch/csr/Zihpm/hpmcounter23h.yaml | 1 - arch/csr/Zihpm/hpmcounter24h.yaml | 1 - arch/csr/Zihpm/hpmcounter25h.yaml | 1 - arch/csr/Zihpm/hpmcounter26h.yaml | 1 - arch/csr/Zihpm/hpmcounter27h.yaml | 1 - arch/csr/Zihpm/hpmcounter28h.yaml | 1 - arch/csr/Zihpm/hpmcounter29h.yaml | 1 - arch/csr/Zihpm/hpmcounter30h.yaml | 1 - arch/csr/Zihpm/hpmcounter31h.yaml | 1 - arch/csr/Zihpm/hpmcounter3h.yaml | 1 - arch/csr/Zihpm/hpmcounter4h.yaml | 1 - arch/csr/Zihpm/hpmcounter5h.yaml | 1 - arch/csr/Zihpm/hpmcounter6h.yaml | 1 - arch/csr/Zihpm/hpmcounter7h.yaml | 1 - arch/csr/Zihpm/hpmcounter8h.yaml | 1 - arch/csr/Zihpm/hpmcounter9h.yaml | 1 - arch/inst/Zicsr/csrrc.yaml | 16 +- arch/inst/Zicsr/csrrci.yaml | 18 ++- arch/inst/Zicsr/csrrs.yaml | 16 +- arch/inst/Zicsr/csrrsi.yaml | 16 +- arch/inst/Zicsr/csrrw.yaml | 15 +- arch/inst/Zicsr/csrrwi.yaml | 15 +- arch/isa/builtin_functions.idl | 69 +++++++++ arch/isa/globals.isa | 140 +++++++----------- arch_overlay/qc_iu/inst/Xqci/qc.c.clrint.yaml | 4 +- arch_overlay/qc_iu/inst/Xqci/qc.c.setint.yaml | 4 +- arch_overlay/qc_iu/inst/Xqci/qc.clrinti.yaml | 4 +- arch_overlay/qc_iu/inst/Xqci/qc.csrrwr.yaml | 7 +- arch_overlay/qc_iu/inst/Xqci/qc.csrrwri.yaml | 10 +- arch_overlay/qc_iu/inst/Xqci/qc.setinti.yaml | 4 +- backends/cpp_hart_gen/cpp/include/udb/csr.hpp | 6 + backends/cpp_hart_gen/lib/gen_cpp.rb | 11 +- backends/cpp_hart_gen/templates/csrs.hxx.erb | 2 + backends/cpp_hart_gen/templates/hart.hxx.erb | 71 +++++++++ .../cpp_hart_gen/templates/hart_impl.hxx.erb | 3 + lib/arch_obj_models/csr.rb | 4 + lib/arch_obj_models/instruction.rb | 4 +- lib/cfg_arch.rb | 13 +- lib/idl/ast.rb | 102 +++++-------- lib/idl/idl.treetop | 4 +- lib/idl/passes/gen_adoc.rb | 18 +-- lib/idl/symbol_table.rb | 1 + lib/idl/type.rb | 7 +- 56 files changed, 363 insertions(+), 250 deletions(-) diff --git a/arch/csr/Zihpm/hpmcounter10h.yaml b/arch/csr/Zihpm/hpmcounter10h.yaml index 81f80156af..b903ef0217 100644 --- a/arch/csr/Zihpm/hpmcounter10h.yaml +++ b/arch/csr/Zihpm/hpmcounter10h.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter10h long_name: User-mode Hardware Performance Counter 7, high half address: 0xC8A -base: 32 description: | Alias for M-mode CSR `mhpmcounter10h`. diff --git a/arch/csr/Zihpm/hpmcounter11h.yaml b/arch/csr/Zihpm/hpmcounter11h.yaml index 5eefd08e03..24c3187660 100644 --- a/arch/csr/Zihpm/hpmcounter11h.yaml +++ b/arch/csr/Zihpm/hpmcounter11h.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter11h long_name: User-mode Hardware Performance Counter 8, high half address: 0xC8B -base: 32 description: | Alias for M-mode CSR `mhpmcounter11h`. diff --git a/arch/csr/Zihpm/hpmcounter12h.yaml b/arch/csr/Zihpm/hpmcounter12h.yaml index 9007c8f506..c0c468c19d 100644 --- a/arch/csr/Zihpm/hpmcounter12h.yaml +++ b/arch/csr/Zihpm/hpmcounter12h.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter12h long_name: User-mode Hardware Performance Counter 9, high half address: 0xC8C -base: 32 description: | Alias for M-mode CSR `mhpmcounter12h`. diff --git a/arch/csr/Zihpm/hpmcounter13h.yaml b/arch/csr/Zihpm/hpmcounter13h.yaml index fb684749df..cd055f9404 100644 --- a/arch/csr/Zihpm/hpmcounter13h.yaml +++ b/arch/csr/Zihpm/hpmcounter13h.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter13h long_name: User-mode Hardware Performance Counter 10, high half address: 0xC8D -base: 32 description: | Alias for M-mode CSR `mhpmcounter13h`. diff --git a/arch/csr/Zihpm/hpmcounter14h.yaml b/arch/csr/Zihpm/hpmcounter14h.yaml index 9e38f55a14..1a4290b354 100644 --- a/arch/csr/Zihpm/hpmcounter14h.yaml +++ b/arch/csr/Zihpm/hpmcounter14h.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter14h long_name: User-mode Hardware Performance Counter 11, high half address: 0xC8E -base: 32 description: | Alias for M-mode CSR `mhpmcounter14h`. diff --git a/arch/csr/Zihpm/hpmcounter15h.yaml b/arch/csr/Zihpm/hpmcounter15h.yaml index 745a8d284e..8f7a0fb94e 100644 --- a/arch/csr/Zihpm/hpmcounter15h.yaml +++ b/arch/csr/Zihpm/hpmcounter15h.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter15h long_name: User-mode Hardware Performance Counter 12, high half address: 0xC8F -base: 32 description: | Alias for M-mode CSR `mhpmcounter15h`. diff --git a/arch/csr/Zihpm/hpmcounter16h.yaml b/arch/csr/Zihpm/hpmcounter16h.yaml index 39f9043123..b3d05236b9 100644 --- a/arch/csr/Zihpm/hpmcounter16h.yaml +++ b/arch/csr/Zihpm/hpmcounter16h.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter16h long_name: User-mode Hardware Performance Counter 13, high half address: 0xC90 -base: 32 description: | Alias for M-mode CSR `mhpmcounter16h`. diff --git a/arch/csr/Zihpm/hpmcounter17h.yaml b/arch/csr/Zihpm/hpmcounter17h.yaml index 6a55a4e1ec..0cd5f864e3 100644 --- a/arch/csr/Zihpm/hpmcounter17h.yaml +++ b/arch/csr/Zihpm/hpmcounter17h.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter17h long_name: User-mode Hardware Performance Counter 14, high half address: 0xC91 -base: 32 description: | Alias for M-mode CSR `mhpmcounter17h`. diff --git a/arch/csr/Zihpm/hpmcounter18h.yaml b/arch/csr/Zihpm/hpmcounter18h.yaml index 4427ba61d7..d45aa624b9 100644 --- a/arch/csr/Zihpm/hpmcounter18h.yaml +++ b/arch/csr/Zihpm/hpmcounter18h.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter18h long_name: User-mode Hardware Performance Counter 15, high half address: 0xC92 -base: 32 description: | Alias for M-mode CSR `mhpmcounter18h`. diff --git a/arch/csr/Zihpm/hpmcounter19h.yaml b/arch/csr/Zihpm/hpmcounter19h.yaml index bc4872908c..f5bff3f22d 100644 --- a/arch/csr/Zihpm/hpmcounter19h.yaml +++ b/arch/csr/Zihpm/hpmcounter19h.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter19h long_name: User-mode Hardware Performance Counter 16, high half address: 0xC93 -base: 32 description: | Alias for M-mode CSR `mhpmcounter19h`. diff --git a/arch/csr/Zihpm/hpmcounter20h.yaml b/arch/csr/Zihpm/hpmcounter20h.yaml index 6b75ff97e6..6734e2d79b 100644 --- a/arch/csr/Zihpm/hpmcounter20h.yaml +++ b/arch/csr/Zihpm/hpmcounter20h.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter20h long_name: User-mode Hardware Performance Counter 17, high half address: 0xC94 -base: 32 description: | Alias for M-mode CSR `mhpmcounter20h`. diff --git a/arch/csr/Zihpm/hpmcounter21h.yaml b/arch/csr/Zihpm/hpmcounter21h.yaml index d644bf0ca9..12012a7bca 100644 --- a/arch/csr/Zihpm/hpmcounter21h.yaml +++ b/arch/csr/Zihpm/hpmcounter21h.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter21h long_name: User-mode Hardware Performance Counter 18, high half address: 0xC95 -base: 32 description: | Alias for M-mode CSR `mhpmcounter21h`. diff --git a/arch/csr/Zihpm/hpmcounter22h.yaml b/arch/csr/Zihpm/hpmcounter22h.yaml index ab3836ad4a..994240044e 100644 --- a/arch/csr/Zihpm/hpmcounter22h.yaml +++ b/arch/csr/Zihpm/hpmcounter22h.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter22h long_name: User-mode Hardware Performance Counter 19, high half address: 0xC96 -base: 32 description: | Alias for M-mode CSR `mhpmcounter22h`. diff --git a/arch/csr/Zihpm/hpmcounter23h.yaml b/arch/csr/Zihpm/hpmcounter23h.yaml index 11c69f5e77..ecb16e6844 100644 --- a/arch/csr/Zihpm/hpmcounter23h.yaml +++ b/arch/csr/Zihpm/hpmcounter23h.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter23h long_name: User-mode Hardware Performance Counter 20, high half address: 0xC97 -base: 32 description: | Alias for M-mode CSR `mhpmcounter23h`. diff --git a/arch/csr/Zihpm/hpmcounter24h.yaml b/arch/csr/Zihpm/hpmcounter24h.yaml index d1223f183b..ffe667a456 100644 --- a/arch/csr/Zihpm/hpmcounter24h.yaml +++ b/arch/csr/Zihpm/hpmcounter24h.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter24h long_name: User-mode Hardware Performance Counter 21, high half address: 0xC98 -base: 32 description: | Alias for M-mode CSR `mhpmcounter24h`. diff --git a/arch/csr/Zihpm/hpmcounter25h.yaml b/arch/csr/Zihpm/hpmcounter25h.yaml index 891956a29d..f4b3286a4f 100644 --- a/arch/csr/Zihpm/hpmcounter25h.yaml +++ b/arch/csr/Zihpm/hpmcounter25h.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter25h long_name: User-mode Hardware Performance Counter 22, high half address: 0xC99 -base: 32 description: | Alias for M-mode CSR `mhpmcounter25h`. diff --git a/arch/csr/Zihpm/hpmcounter26h.yaml b/arch/csr/Zihpm/hpmcounter26h.yaml index 267827d2ac..995483b4fe 100644 --- a/arch/csr/Zihpm/hpmcounter26h.yaml +++ b/arch/csr/Zihpm/hpmcounter26h.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter26h long_name: User-mode Hardware Performance Counter 23, high half address: 0xC9A -base: 32 description: | Alias for M-mode CSR `mhpmcounter26h`. diff --git a/arch/csr/Zihpm/hpmcounter27h.yaml b/arch/csr/Zihpm/hpmcounter27h.yaml index ecc4f89d37..8e17ad1758 100644 --- a/arch/csr/Zihpm/hpmcounter27h.yaml +++ b/arch/csr/Zihpm/hpmcounter27h.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter27h long_name: User-mode Hardware Performance Counter 24, high half address: 0xC9B -base: 32 description: | Alias for M-mode CSR `mhpmcounter27h`. diff --git a/arch/csr/Zihpm/hpmcounter28h.yaml b/arch/csr/Zihpm/hpmcounter28h.yaml index ee3b013e17..9a1e7714f3 100644 --- a/arch/csr/Zihpm/hpmcounter28h.yaml +++ b/arch/csr/Zihpm/hpmcounter28h.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter28h long_name: User-mode Hardware Performance Counter 25, high half address: 0xC9C -base: 32 description: | Alias for M-mode CSR `mhpmcounter28h`. diff --git a/arch/csr/Zihpm/hpmcounter29h.yaml b/arch/csr/Zihpm/hpmcounter29h.yaml index f903b631f4..e3fd8e6a2f 100644 --- a/arch/csr/Zihpm/hpmcounter29h.yaml +++ b/arch/csr/Zihpm/hpmcounter29h.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter29h long_name: User-mode Hardware Performance Counter 26, high half address: 0xC9D -base: 32 description: | Alias for M-mode CSR `mhpmcounter29h`. diff --git a/arch/csr/Zihpm/hpmcounter30h.yaml b/arch/csr/Zihpm/hpmcounter30h.yaml index 4c370ead95..08bc8149a7 100644 --- a/arch/csr/Zihpm/hpmcounter30h.yaml +++ b/arch/csr/Zihpm/hpmcounter30h.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter30h long_name: User-mode Hardware Performance Counter 27, high half address: 0xC9E -base: 32 description: | Alias for M-mode CSR `mhpmcounter30h`. diff --git a/arch/csr/Zihpm/hpmcounter31h.yaml b/arch/csr/Zihpm/hpmcounter31h.yaml index 397143b275..02f8f77b23 100644 --- a/arch/csr/Zihpm/hpmcounter31h.yaml +++ b/arch/csr/Zihpm/hpmcounter31h.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter31h long_name: User-mode Hardware Performance Counter 28, high half address: 0xC9F -base: 32 description: | Alias for M-mode CSR `mhpmcounter31h`. diff --git a/arch/csr/Zihpm/hpmcounter3h.yaml b/arch/csr/Zihpm/hpmcounter3h.yaml index 6eb41a9e0f..2c49c0fe4c 100644 --- a/arch/csr/Zihpm/hpmcounter3h.yaml +++ b/arch/csr/Zihpm/hpmcounter3h.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter3h long_name: User-mode Hardware Performance Counter 0, high half address: 0xC83 -base: 32 description: | Alias for M-mode CSR `mhpmcounter3h`. diff --git a/arch/csr/Zihpm/hpmcounter4h.yaml b/arch/csr/Zihpm/hpmcounter4h.yaml index 9faab3c5c0..ac6a575ccc 100644 --- a/arch/csr/Zihpm/hpmcounter4h.yaml +++ b/arch/csr/Zihpm/hpmcounter4h.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter4h long_name: User-mode Hardware Performance Counter 1, high half address: 0xC84 -base: 32 description: | Alias for M-mode CSR `mhpmcounter4h`. diff --git a/arch/csr/Zihpm/hpmcounter5h.yaml b/arch/csr/Zihpm/hpmcounter5h.yaml index 662458fdab..1529a2f8a2 100644 --- a/arch/csr/Zihpm/hpmcounter5h.yaml +++ b/arch/csr/Zihpm/hpmcounter5h.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter5h long_name: User-mode Hardware Performance Counter 2, high half address: 0xC85 -base: 32 description: | Alias for M-mode CSR `mhpmcounter5h`. diff --git a/arch/csr/Zihpm/hpmcounter6h.yaml b/arch/csr/Zihpm/hpmcounter6h.yaml index e481365550..9995fc0eee 100644 --- a/arch/csr/Zihpm/hpmcounter6h.yaml +++ b/arch/csr/Zihpm/hpmcounter6h.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter6h long_name: User-mode Hardware Performance Counter 3, high half address: 0xC86 -base: 32 description: | Alias for M-mode CSR `mhpmcounter6h`. diff --git a/arch/csr/Zihpm/hpmcounter7h.yaml b/arch/csr/Zihpm/hpmcounter7h.yaml index 4b1e69a34d..416f912193 100644 --- a/arch/csr/Zihpm/hpmcounter7h.yaml +++ b/arch/csr/Zihpm/hpmcounter7h.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter7h long_name: User-mode Hardware Performance Counter 4, high half address: 0xC87 -base: 32 description: | Alias for M-mode CSR `mhpmcounter7h`. diff --git a/arch/csr/Zihpm/hpmcounter8h.yaml b/arch/csr/Zihpm/hpmcounter8h.yaml index a71d48687a..11a341b4bb 100644 --- a/arch/csr/Zihpm/hpmcounter8h.yaml +++ b/arch/csr/Zihpm/hpmcounter8h.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter8h long_name: User-mode Hardware Performance Counter 5, high half address: 0xC88 -base: 32 description: | Alias for M-mode CSR `mhpmcounter8h`. diff --git a/arch/csr/Zihpm/hpmcounter9h.yaml b/arch/csr/Zihpm/hpmcounter9h.yaml index 9a751b36c8..f3fcfdc25b 100644 --- a/arch/csr/Zihpm/hpmcounter9h.yaml +++ b/arch/csr/Zihpm/hpmcounter9h.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter9h long_name: User-mode Hardware Performance Counter 6, high half address: 0xC89 -base: 32 description: | Alias for M-mode CSR `mhpmcounter9h`. diff --git a/arch/inst/Zicsr/csrrc.yaml b/arch/inst/Zicsr/csrrc.yaml index 3ab6aaf2b3..8606d5648f 100644 --- a/arch/inst/Zicsr/csrrc.yaml +++ b/arch/inst/Zicsr/csrrc.yaml @@ -24,16 +24,26 @@ access: vu: always data_independent_timing: false operation(): | + Csr csr_handle = direct_csr_lookup(csr); + Boolean will_write = xs1 != 0; - check_csr(csr, will_write, $encoding); - XReg initial_csr_value = CSR[csr].sw_read(); + # permission checks + if (csr_handle.valid == false) { + unimplemented_csr($encoding); + } else if (!compatible_mode?(csr_handle.mode, mode())) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } else if (will_write && csr_handle.writable == false) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg initial_csr_value = csr_sw_read(csr_handle); if (xs1 != 0) { # clear bits using the mask # performing any WARL transformations first XReg mask = X[xs1]; - CSR[csr].sw_write(initial_csr_value & ~mask); + csr_sw_write(csr_handle, initial_csr_value & ~mask); } X[xd] = initial_csr_value; diff --git a/arch/inst/Zicsr/csrrci.yaml b/arch/inst/Zicsr/csrrci.yaml index d45728539c..2917e9cc6e 100644 --- a/arch/inst/Zicsr/csrrci.yaml +++ b/arch/inst/Zicsr/csrrci.yaml @@ -25,15 +25,25 @@ access: data_independent_timing: false operation(): | Boolean will_write = uimm != 0; - check_csr(csr, will_write, $encoding); - XReg initial_csr_value = CSR[csr].sw_read(); + Csr csr_handle = direct_csr_lookup(csr); - if (uimm != 0) { + # permission checks + if (csr_handle.valid == false) { + unimplemented_csr($encoding); + } else if (!compatible_mode?(csr_handle.mode, mode())) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } else if (will_write && csr_handle.writable == false) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg initial_csr_value = csr_sw_read(csr_handle); + + if (will_write) { # set bits using the mask # performing any WARL transformations first XReg mask = uimm; - CSR[csr].sw_write(initial_csr_value & ~mask); + csr_sw_write(csr_handle, initial_csr_value & ~mask); } X[xd] = initial_csr_value; diff --git a/arch/inst/Zicsr/csrrs.yaml b/arch/inst/Zicsr/csrrs.yaml index e5171f141e..9919ca5caf 100644 --- a/arch/inst/Zicsr/csrrs.yaml +++ b/arch/inst/Zicsr/csrrs.yaml @@ -31,15 +31,25 @@ access: vu: always operation(): | Boolean will_write = rs1 != 0; - check_csr(csr, will_write, $encoding); - XReg initial_csr_value = CSR[csr].sw_read(); + Csr csr_handle = direct_csr_lookup(csr); + + # permission checks + if (csr_handle.valid == false) { + unimplemented_csr($encoding); + } else if (!compatible_mode?(csr_handle.mode, mode())) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } else if (will_write && csr_handle.writable == false) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg initial_csr_value = csr_sw_read(csr_handle); if (will_write) { # set bits using the mask # performing any WARL transformations first XReg mask = X[rs1]; - CSR[csr].sw_write(initial_csr_value | mask); + csr_sw_write(csr_handle, initial_csr_value | mask); } X[rd] = initial_csr_value; diff --git a/arch/inst/Zicsr/csrrsi.yaml b/arch/inst/Zicsr/csrrsi.yaml index 5543777132..e175c9398f 100644 --- a/arch/inst/Zicsr/csrrsi.yaml +++ b/arch/inst/Zicsr/csrrsi.yaml @@ -25,15 +25,25 @@ access: data_independent_timing: false operation(): | Boolean will_write = uimm != 0; - check_csr(csr, will_write, $encoding); - XReg initial_csr_value = CSR[csr].sw_read(); + Csr csr_handle = direct_csr_lookup(csr); + + # permission checks + if (csr_handle.valid == false) { + unimplemented_csr($encoding); + } else if (!compatible_mode?(csr_handle.mode, mode())) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } else if (will_write && csr_handle.writable == false) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg initial_csr_value = csr_sw_read(csr_handle); if (will_write) { # set bits using the mask # performing any WARL transformations first XReg mask = uimm; - CSR[csr].sw_write(initial_csr_value | mask); + csr_sw_write(csr_handle, initial_csr_value | mask); } X[xd] = initial_csr_value; diff --git a/arch/inst/Zicsr/csrrw.yaml b/arch/inst/Zicsr/csrrw.yaml index c379a802a8..0ddf85fc9c 100644 --- a/arch/inst/Zicsr/csrrw.yaml +++ b/arch/inst/Zicsr/csrrw.yaml @@ -29,17 +29,26 @@ access: vs: always vu: always operation(): | - check_csr(csr, true, $encoding); + Csr csr_handle = direct_csr_lookup(csr); Bits initial_value = X[xs1]; + # permission checks + if (csr_handle.valid == false) { + unimplemented_csr($encoding); + } else if (!compatible_mode?(csr_handle.mode, mode())) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } else if (csr_handle.writable == false) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + if (xd != 0) { - X[xd] = CSR[csr].sw_read(); + X[xd] = csr_sw_read(csr_handle); } # writes the value in X[xs1] to the CSR, # performing any WARL transformations first - CSR[csr].sw_write(initial_value); + csr_sw_write(csr_handle, initial_value); # SPDX-SnippetBegin # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model diff --git a/arch/inst/Zicsr/csrrwi.yaml b/arch/inst/Zicsr/csrrwi.yaml index f3290fd3c0..dca3605e55 100644 --- a/arch/inst/Zicsr/csrrwi.yaml +++ b/arch/inst/Zicsr/csrrwi.yaml @@ -29,15 +29,24 @@ access: vs: always vu: always operation(): | - check_csr(csr, true, $encoding); + Csr csr_handle = direct_csr_lookup(csr); + + # permission checks + if (csr_handle.valid == false) { + unimplemented_csr($encoding); + } else if (!compatible_mode?(csr_handle.mode, mode())) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } else if (csr_handle.writable == false) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } if (rd != 0) { - X[rd] = CSR[csr].sw_read(); + X[rd] = csr_sw_read(csr_handle); } # writes the zero-extended immediate to the CSR, # performing any WARL transformations first - CSR[csr].sw_write({{XLEN-5{1'b0}}, imm}); + csr_sw_write(csr_handle, {{XLEN-5{1'b0}}, imm}); # SPDX-SnippetBegin # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model diff --git a/arch/isa/builtin_functions.idl b/arch/isa/builtin_functions.idl index 6a11479338..aee4dc2fe7 100644 --- a/arch/isa/builtin_functions.idl +++ b/arch/isa/builtin_functions.idl @@ -24,6 +24,75 @@ generated function implemented_csr? { } } +enum CsrAddressType { + Direct # accessible with csrrw, etc. + Indirect # only accessible with csrind +} + +struct Csr { + Boolean valid; + String name; + CsrAddressType addr_type; + Bits<64> address; + PrivilegeMode mode; + Boolean writable; +} + +# implementation is generated from CSR YAML defintions +generated function direct_csr_lookup { + returns Csr + arguments + Bits<12> csr_addr + description { + Return CSR info for a CSR with direct address +csr_addr+. + + If no CSR exists, .valid == false + } +} + +# implementation is generated from CSR YAML defintions +generated function indirect_csr_lookup { + returns Csr + arguments + Bits csr_addr + description { + Return CSR info for a CSR with indirect address +csr_addr+. + + If no CSR exists, .valid == false + } +} + +generated function csr_hw_read { + returns Bits<64> # even in rv32, there are 64-bit CSRs + arguments + Csr csr + description { + Returns the raw value of csr + } +} + +# implementation is generated from CSR YAML defintions +generated function csr_sw_read { + returns Bits<64> # even in rv32, there are 64-bit CSRs + arguments + Csr csr + description { + Returns the result of CSR[csr].sw_read(); i.e., the software view of the register + } +} + +# implementation is generated from CSR YAML defintions +generated function csr_sw_write { + arguments + Csr csr, + Bits value + description { + Writes +value+ to +csr+, applying an WARL transformations first. + + Uses the sw_write(...) functions of CSR field definitions. + } +} + builtin function unpredictable { arguments String why description { diff --git a/arch/isa/globals.isa b/arch/isa/globals.isa index c208dedec7..66dd9a0375 100644 --- a/arch/isa/globals.isa +++ b/arch/isa/globals.isa @@ -267,6 +267,41 @@ function set_mode { } } +function compatible_mode? { + returns Boolean + arguments + PrivilegeMode target_mode, + PrivilegeMode actual_mode + description { + Returns true if +target_mode+ is more privileged than +actual_mode+. + } + body { + if (target_mode == PrivilegeMode::M) { + return actual_mode == PrivilegeMode::M; + } else if (target_mode == PrivilegeMode::S) { + return + (actual_mode == PrivilegeMode::M) || + (actual_mode == PrivilegeMode::S); + } else if (target_mode == PrivilegeMode::U) { + return + (actual_mode == PrivilegeMode::M) || + (actual_mode == PrivilegeMode::S) || + (actual_mode == PrivilegeMode::U); + } else if (target_mode == PrivilegeMode::VS) { + return + (actual_mode == PrivilegeMode::M) || + (actual_mode == PrivilegeMode::S) || + (actual_mode == PrivilegeMode::VS); + } else if (target_mode == PrivilegeMode::VU) { + return + (actual_mode == PrivilegeMode::M) || + (actual_mode == PrivilegeMode::S) || + (actual_mode == PrivilegeMode::VS) || + (actual_mode == PrivilegeMode::VU); + } + } +} + function exception_handling_mode { returns PrivilegeMode arguments ExceptionCode exception_code @@ -515,79 +550,6 @@ function stval_for { } } -function csr? { - returns Boolean - arguments Bits<12> csr_addr - description { - Returns true if csr_addr is an implemented csr, and the defining extension is not disabled - } - body { - if (!implemented_csr?(csr_addr)) { - return false; - } - - if (implemented?(ExtensionName::S) - && !CSR[csr_addr].implemented_without?(ExtensionName::S)) { - - return CSR[misa].S == 1'b1; - - } else if (implemented?(ExtensionName::U) - && !CSR[csr_addr].implemented_without?(ExtensionName::U)) { - - return CSR[misa].U == 1'b1; - - } else if (implemented?(ExtensionName::H) - && !CSR[csr_addr].implemented_without?(ExtensionName::H)) { - - return CSR[misa].H == 1'b1; - } - - return true; - } -} - -function check_csr { - arguments Bits<12> csr_addr, Boolean for_write, Bits encoding - description { - Checks if 'csr_addr' is a valid address, can be read in the current mode, - and, if for_write is true, can be written in the current mode. - - If the check fails, will either raise IllegalInsruction or cause - unpredictable behavior, depending on TRAP_ON_UNIMPLEMENTED_CSR - } - body { - if (!csr?(csr_addr)) { - if (TRAP_ON_UNIMPLEMENTED_CSR) { - raise(ExceptionCode::IllegalInstruction, mode(), encoding); - } else { - unpredictable("Attempt to read unimplemented CSR"); - } - } - PrivilegeMode priv_mode; - if (csr_addr[9:8] == 2'b00) { - priv_mode = PrivilegeMode::M; - } else if (csr_addr[9:8] == 2'b01 || csr_addr[9:8] == 2'b10) { - priv_mode = PrivilegeMode::S; - } else { - priv_mode = PrivilegeMode::U; - } - if (priv_mode == PrivilegeMode::M) { - if (mode() != PrivilegeMode::M) { - raise(ExceptionCode::IllegalInstruction, mode(), encoding); - } - } else if (priv_mode == PrivilegeMode::S) { - if (mode() == PrivilegeMode::U || mode() == PrivilegeMode::VU) { - raise(ExceptionCode::IllegalInstruction, mode(), encoding); - } - } - - if (for_write && csr_addr[11:10] == 2'b11) { - # write to read-only CSR - raise(ExceptionCode::IllegalInstruction, mode(), encoding); - } - } -} - function vstval_for { returns XReg arguments ExceptionCode exception_code, XReg tval @@ -1024,8 +986,13 @@ function pmp_match_64 { # get the registers for this PMP entry Bits<12> pmpcfg_idx = pmpcfg0_addr + (i/8)*2; Bits<6> shamt = (i % 8)*8; - PmpCfg cfg = ($bits(CSR[pmpcfg0_addr]) >> shamt)[7:0]; + + Csr pmpcfg_csr = direct_csr_lookup(pmpcfg_idx); + PmpCfg cfg = (csr_hw_read(pmpcfg_csr) >> shamt)[7:0]; + Bits<12> pmpaddr_idx = pmpaddr0_addr + i; + Csr pmpaddr_csr = direct_csr_lookup(pmpaddr_idx); + Bits<64> pmpaddr_csr_value = csr_sw_read(pmpaddr_csr); # set up the default range limits, which will result in NoMatch when # compared to the access @@ -1038,9 +1005,10 @@ function pmp_match_64 { range_lo = 0; } else { # otherwise, it's the address in the next lowest pmpaddr register - range_lo = ($bits(CSR[pmpaddr_idx - 1]) << 2)[PHYS_ADDR_WIDTH-1:0]; + Csr tor_pmpaddr_csr = direct_csr_lookup(pmpaddr_idx - 1); + range_lo = (csr_sw_read(tor_pmpaddr_csr) << 2)[PHYS_ADDR_WIDTH-1:0]; } - range_hi = ($bits(CSR[pmpaddr_idx]) << 2)[PHYS_ADDR_WIDTH-1:0]; + range_hi = (pmpaddr_csr_value << 2)[PHYS_ADDR_WIDTH-1:0]; } else if (cfg.A == $bits(PmpCfg_A::NAPOT)) { # Example pmpaddr: 0b00010101111 @@ -1049,14 +1017,14 @@ function pmp_match_64 { # mask: 0b00000011111 # ~mask: 0b11111100000 # len = mask + 1: 0b00000100000 - Bits pmpaddr_value = CSR[pmpaddr_idx].sw_read()[PHYS_ADDR_WIDTH-3:0]; + Bits pmpaddr_value = pmpaddr_csr_value[PHYS_ADDR_WIDTH-3:0]; Bits mask = pmpaddr_value ^ (pmpaddr_value + 1); range_lo = (pmpaddr_value & ~mask) << 2; Bits len = mask + 1; range_hi = ((pmpaddr_value & ~mask) + len) << 2; } else if (cfg.A == $bits(PmpCfg_A::NA4)) { - range_lo = ($bits(CSR[pmpaddr_idx]) << 2)[PHYS_ADDR_WIDTH-1:0]; + range_lo = (pmpaddr_csr_value << 2)[PHYS_ADDR_WIDTH-1:0]; range_hi = range_lo + 4; } @@ -1091,8 +1059,13 @@ function pmp_match_32 { # get the registers for this PMP entry Bits<12> pmpcfg_idx = pmpcfg0_addr + (i/4); Bits<6> shamt = (i % 4)*8; - PmpCfg cfg = ($bits(CSR[pmpcfg0_addr]) >> shamt)[7:0]; + + Csr pmpcfg_csr = direct_csr_lookup(pmpcfg_idx); + PmpCfg cfg = (csr_hw_read(pmpcfg_csr) >> shamt)[7:0]; + Bits<12> pmpaddr_idx = pmpaddr0_addr + i; + Csr pmpaddr_csr = direct_csr_lookup(pmpaddr_idx); + Bits<32> pmpaddr_csr_value = csr_sw_read(pmpaddr_csr); # set up the default range limits, which will result in NoMatch when # compared to the access @@ -1105,9 +1078,10 @@ function pmp_match_32 { range_lo = 0; } else { # otherwise, it's the address in the next lowest pmpaddr register - range_lo = ($bits(CSR[pmpaddr_idx - 1]) << 2)[PHYS_ADDR_WIDTH-1:0]; + Csr tor_pmpaddr_csr = direct_csr_lookup(pmpaddr_idx - 1); + range_lo = (csr_sw_read(tor_pmpaddr_csr) << 2)[PHYS_ADDR_WIDTH-1:0]; } - range_hi = ($bits(CSR[pmpaddr_idx]) << 2)[PHYS_ADDR_WIDTH-1:0]; + range_hi = (pmpaddr_csr_value << 2)[PHYS_ADDR_WIDTH-1:0]; } else if (cfg.A == $bits(PmpCfg_A::NAPOT)) { # Example pmpaddr: 0b00010101111 @@ -1116,14 +1090,14 @@ function pmp_match_32 { # mask: 0b00000011111 # ~mask: 0b11111100000 # len = mask + 1: 0b00000100000 - Bits pmpaddr_value = CSR[pmpaddr_idx].sw_read()[PHYS_ADDR_WIDTH-3:0]; + Bits pmpaddr_value = pmpaddr_csr_value[PHYS_ADDR_WIDTH-3:0]; Bits mask = pmpaddr_value ^ (pmpaddr_value + 1); range_lo = (pmpaddr_value & ~mask) << 2; Bits len = mask + 1; range_hi = ((pmpaddr_value & ~mask) + len) << 2; } else if (cfg.A == $bits(PmpCfg_A::NA4)) { - range_lo = ($bits(CSR[pmpaddr_idx]) << 2)[PHYS_ADDR_WIDTH-1:0]; + range_lo = (pmpaddr_csr_value << 2)[PHYS_ADDR_WIDTH-1:0]; range_hi = range_lo + 4; } diff --git a/arch_overlay/qc_iu/inst/Xqci/qc.c.clrint.yaml b/arch_overlay/qc_iu/inst/Xqci/qc.c.clrint.yaml index 3be38f2786..cdd1b645e4 100644 --- a/arch_overlay/qc_iu/inst/Xqci/qc.c.clrint.yaml +++ b/arch_overlay/qc_iu/inst/Xqci/qc.c.clrint.yaml @@ -29,5 +29,5 @@ operation(): | XReg idx = rs1 / 32; XReg bit = rs1 % 32; - XReg pre_csr = CSR[MCLICIP0_ADDR + idx].sw_read(); - CSR[MCLICIP0_ADDR + idx].sw_write(pre_csr & ~(1 << bit)); + Csr pre_csr = direct_csr_lookup(MCLICIP0_ADDR + idx); + csr_sw_write(pre_csr, csr_sw_read(pre_csr) & ~(1 << bit)); diff --git a/arch_overlay/qc_iu/inst/Xqci/qc.c.setint.yaml b/arch_overlay/qc_iu/inst/Xqci/qc.c.setint.yaml index 074157bbc3..9f7b5e5e69 100644 --- a/arch_overlay/qc_iu/inst/Xqci/qc.c.setint.yaml +++ b/arch_overlay/qc_iu/inst/Xqci/qc.c.setint.yaml @@ -29,5 +29,5 @@ operation(): | XReg idx = rs1 / 32; XReg bit = rs1 % 32; - XReg pre_csr = CSR[MCLICIP0_ADDR + idx].sw_read(); - CSR[MCLICIP0_ADDR + idx].sw_write(pre_csr | (1 << bit)); + Csr pre_csr = direct_csr_lookup(MCLICIP0_ADDR + idx); + csr_sw_write(pre_csr, csr_sw_read(pre_csr) | (1 << bit)); diff --git a/arch_overlay/qc_iu/inst/Xqci/qc.clrinti.yaml b/arch_overlay/qc_iu/inst/Xqci/qc.clrinti.yaml index 86be3a762d..81e9b42c53 100644 --- a/arch_overlay/qc_iu/inst/Xqci/qc.clrinti.yaml +++ b/arch_overlay/qc_iu/inst/Xqci/qc.clrinti.yaml @@ -28,5 +28,5 @@ operation(): | XReg idx = imm / 32; XReg bit = imm % 32; - XReg pre_csr = CSR[MCLICIP0_ADDR + idx].sw_read(); - CSR[MCLICIP0_ADDR + idx].sw_write(pre_csr & ~(1 << bit)); + Csr pre_csr = direct_csr_lookup(MCLICIP0_ADDR + idx); + csr_sw_write(pre_csr, csr_sw_read(pre_csr) & ~(1 << bit)); diff --git a/arch_overlay/qc_iu/inst/Xqci/qc.csrrwr.yaml b/arch_overlay/qc_iu/inst/Xqci/qc.csrrwr.yaml index 47c7a9a49f..4edaa962e4 100644 --- a/arch_overlay/qc_iu/inst/Xqci/qc.csrrwr.yaml +++ b/arch_overlay/qc_iu/inst/Xqci/qc.csrrwr.yaml @@ -35,10 +35,11 @@ access: vs: always vu: always operation(): | - XReg csr = X[rs2]; + XReg csr_addr = X[rs2]; + Csr csr = direct_csr_lookup(csr_addr); if (rd != 0) { - X[rd] = CSR[csr].sw_read(); + X[rd] = csr_sw_read(csr); } # writes the value in X[rs1] to the CSR, # performing any WARL transformations first - CSR[csr].sw_write(X[rs1]); + csr_sw_write(csr, X[rs1]); diff --git a/arch_overlay/qc_iu/inst/Xqci/qc.csrrwri.yaml b/arch_overlay/qc_iu/inst/Xqci/qc.csrrwri.yaml index 94c7df3741..f7c9d74985 100644 --- a/arch_overlay/qc_iu/inst/Xqci/qc.csrrwri.yaml +++ b/arch_overlay/qc_iu/inst/Xqci/qc.csrrwri.yaml @@ -35,10 +35,12 @@ access: vs: always vu: always operation(): | - XReg csr = X[rs2]; + XReg csr_addr = X[rs2]; + Csr csr = direct_csr_lookup(csr_addr); if (rd != 0) { - X[rd] = CSR[csr].sw_read(); + X[rd] = csr_sw_read(csr_addr); } # writes the zero-extended immediate to the CSR, - # performing any WARL transformations first - CSR[csr].sw_write({{XLEN-5{1'b0}}, imm}); + # performing any WARL transformations + # first + csr_sw_write(csr, {{XLEN-5{1'b0}}, imm}); diff --git a/arch_overlay/qc_iu/inst/Xqci/qc.setinti.yaml b/arch_overlay/qc_iu/inst/Xqci/qc.setinti.yaml index 537c311bde..9255bb8ac0 100644 --- a/arch_overlay/qc_iu/inst/Xqci/qc.setinti.yaml +++ b/arch_overlay/qc_iu/inst/Xqci/qc.setinti.yaml @@ -28,5 +28,5 @@ operation(): | XReg idx = imm / 32; XReg bit = imm % 32; - XReg pre_csr = CSR[MCLICIP0_ADDR + idx].sw_read(); - CSR[MCLICIP0_ADDR + idx].sw_write(pre_csr | (1 << bit)); + Csr pre_csr = direct_csr_lookup(MCLICIP0_ADDR + idx); + csr_sw_write(pre_csr, csr_sw_read(pre_csr) | (1 << bit)); diff --git a/backends/cpp_hart_gen/cpp/include/udb/csr.hpp b/backends/cpp_hart_gen/cpp/include/udb/csr.hpp index 668d582cbe..1399680674 100644 --- a/backends/cpp_hart_gen/cpp/include/udb/csr.hpp +++ b/backends/cpp_hart_gen/cpp/include/udb/csr.hpp @@ -84,6 +84,12 @@ namespace udb { virtual void reset() = 0; + // the most privileged mode that has access to this csr + virtual PrivilegeMode mode() const = 0; + + // false if the CSR is read only + virtual bool writable() const = 0; + // read the raw bits of a CSR value // // some CSRs are shorter than XLEN bits, but none are longer diff --git a/backends/cpp_hart_gen/lib/gen_cpp.rb b/backends/cpp_hart_gen/lib/gen_cpp.rb index 56b305eb5c..87f4590422 100644 --- a/backends/cpp_hart_gen/lib/gen_cpp.rb +++ b/backends/cpp_hart_gen/lib/gen_cpp.rb @@ -757,15 +757,10 @@ def gen_cpp(symtab, indent = 0, indent_spaces: 2) class CsrReadExpressionAst def gen_cpp(symtab, indent = 0, indent_spaces: 2) csr = csr_def(symtab) - if csr.nil? - # csr isn't known at runtime... - "#{' '*indent}__UDB_CSR_BY_ADDR(#{idx_expr.gen_cpp(symtab, 0, indent_spaces:)}).hw_read(__UDB_XLEN)" + if symtab.cfg_arch.multi_xlen? && csr.format_changes_with_xlen? + "#{' '*indent}__UDB_CSR_BY_NAME(#{csr.name})._hw_read(__UDB_XLEN)" else - if symtab.cfg_arch.multi_xlen? && csr.format_changes_with_xlen? - "#{' '*indent}__UDB_CSR_BY_NAME(#{csr.name})._hw_read(__UDB_XLEN)" - else - "#{' '*indent}__UDB_CSR_BY_NAME(#{csr.name})._hw_read()" - end + "#{' '*indent}__UDB_CSR_BY_NAME(#{csr.name})._hw_read()" end end end diff --git a/backends/cpp_hart_gen/templates/csrs.hxx.erb b/backends/cpp_hart_gen/templates/csrs.hxx.erb index 7bae01031f..2ecd720643 100644 --- a/backends/cpp_hart_gen/templates/csrs.hxx.erb +++ b/backends/cpp_hart_gen/templates/csrs.hxx.erb @@ -220,6 +220,8 @@ namespace udb { unsigned address() const override { return <%= csr.address %>; } static constexpr unsigned _address() { return <%= csr.address %>; } const std::string name() const override { return "<%= csr.name %>"; } + PrivilegeMode mode() const override { return PrivilegeMode::<%= csr.priv_mode %>; } + bool writable() const override { return <%= csr.writable %>; } void reset() override { <%- fields_for_xlen.each do |field| -%> diff --git a/backends/cpp_hart_gen/templates/hart.hxx.erb b/backends/cpp_hart_gen/templates/hart.hxx.erb index c9452a580c..52c12d3faf 100644 --- a/backends/cpp_hart_gen/templates/hart.hxx.erb +++ b/backends/cpp_hart_gen/templates/hart.hxx.erb @@ -225,7 +225,77 @@ namespace udb { return m_csr_addr_map.count(csr_addr) == 1; } + <%= name_of(:struct, "Csr", cfg_arch) %> direct_csr_lookup(const Bits<12>& csr_addr) { + <%= name_of(:struct, "Csr", cfg_arch) %> csr_handle; + + auto csr = m_csr_addr_map.find(csr_addr); + if (csr == m_csr_addr_map.end()) { + csr_handle.valid = false; + return csr_handle; + } else { + csr_handle.valid = true; + csr_handle.name = csr->name(); + csr_handle.addr_type = CsrAddressType::Direct; + csr_handle.address = csr_addr; + csr_handle.mode = csr->mode(); + csr_handle.writable = csr->writable(); + return csr_handle; + } + } + <%= name_of(:struct, "Csr", cfg_arch) %> indirect_csr_lookup(const Bits<64>& csr_indirect_addr) { + <%= name_of(:struct, "Csr", cfg_arch) %> csr_handle; + + auto csr = m_csr_indirect_addr_map.find(csr_addr); + if (csr == m_csr_indirect_addr_map.end()) { + csr_handle.valid = false; + return csr_handle; + } else { + csr_handle.valid = true; + csr_handle.name = csr->name(); + csr_handle.addr_type = CsrAddressType::Indirect; + csr_handle.address = csr_addr; + csr_handle.mode = csr->mode(); + csr_handle.writable = csr->writable(); + return csr_handle; + } + } + + PossiblyUnknownBits<64> csr_hw_read(const <%= name_of(:struct, "Csr", cfg_arch) %>& csr_handle) { + if (csr_handle.addr_type == CsrAddressType::Direct) { + auto csr = m_csr_addr_map.find(csr_handle.address); + udb_assert(csr != m_csr_addr_map.end(), "CSR not found"); + return csr.hw_read(xlen()); + } else { + auto csr = m_csr_indirect_addr_map.find(csr_handle.address); + udb_assert(csr != m_csr_indirect_addr_map.end(), "CSR not found"); + return csr.hw_read(xlen()); + } + } + + PossiblyUnknownBits<64> csr_sw_read(const <%= name_of(:struct, "Csr", cfg_arch) %>& csr_handle) { + if (csr_handle.addr_type == CsrAddressType::Direct) { + auto csr = m_csr_addr_map.find(csr_handle.address); + udb_assert(csr != m_csr_addr_map.end(), "CSR not found"); + return csr.sw_read(xlen()); + } else { + auto csr = m_csr_indirect_addr_map.find(csr_handle.address); + udb_assert(csr != m_csr_indirect_addr_map.end(), "CSR not found"); + return csr.sw_read(xlen()); + } + } + + void csr_sw_write(const <%= name_of(:struct, "Csr", cfg_arch) %>& csr_handle, const Bits<<%= cfg_arch.mxlen %>>& value) { + if (csr_handle.addr_type == CsrAddressType::Direct) { + auto csr = m_csr_addr_map.find(csr_handle.address); + udb_assert(csr != m_csr_addr_map.end(), "CSR not found"); + return csr.sw_write(value, xlen()); + } else { + auto csr = m_csr_indirect_addr_map.find(csr_handle.address); + udb_assert(csr != m_csr_indirect_addr_map.end(), "CSR not found"); + return csr.sw_write(value, xlen()); + } + } void set_pc(uint64_t new_pc) override { m_pc = new_pc; @@ -379,6 +449,7 @@ namespace udb { <%= name_of(:params, cfg_arch) %> m_params; <%= name_of(:csr_container, cfg_arch) %> m_csrs; std::unordered_map, CsrBase*> m_csr_addr_map; + std::unordered_map, CsrBase*> m_csr_indirect_addr_map; std::map m_csr_name_map; std::array m_run_one_inst_storage; diff --git a/backends/cpp_hart_gen/templates/hart_impl.hxx.erb b/backends/cpp_hart_gen/templates/hart_impl.hxx.erb index 72207eb8dc..153ad656af 100644 --- a/backends/cpp_hart_gen/templates/hart_impl.hxx.erb +++ b/backends/cpp_hart_gen/templates/hart_impl.hxx.erb @@ -43,6 +43,9 @@ namespace udb { <%- unless csr.address.nil? -%> m_csr_addr_map[<%= csr.address %>] = &m_csrs.<%= csr.name %>; <%- end -%> + <%- unless csr.indirect_address.nil? -%> + m_csr_indirect_addr_map[<%= csr.indirect_address %>] = &m_csrs.<%= csr.name %>; + <%_ end -%> m_csr_name_map["<%= csr.name %>"] = &m_csrs.<%= csr.name %>; <%- end -%> } diff --git a/lib/arch_obj_models/csr.rb b/lib/arch_obj_models/csr.rb index ff1639856b..b0e7f15de1 100644 --- a/lib/arch_obj_models/csr.rb +++ b/lib/arch_obj_models/csr.rb @@ -33,6 +33,10 @@ def virtual_address @data["virtual_address"] end + def writable + @data["writeable"] + end + # @return [Integer] 32 or 64, the XLEN this CSR is exclusively defined in # @return [nil] if this CSR is defined in all bases def base = @data["base"] diff --git a/lib/arch_obj_models/instruction.rb b/lib/arch_obj_models/instruction.rb index 738e73cc34..d056342052 100644 --- a/lib/arch_obj_models/instruction.rb +++ b/lib/arch_obj_models/instruction.rb @@ -158,10 +158,10 @@ def reachable_functions(effective_xlen) else # RubyProf.start ast = type_checked_operation_ast(effective_xlen) - print "Determining reachable funcs from #{name} (#{effective_xlen})..." + # print "Determining reachable funcs from #{name} (#{effective_xlen})..." symtab = fill_symtab(effective_xlen, ast) fns = ast.reachable_functions(symtab) - puts "done" + # puts "done" # result = RubyProf.stop # RubyProf::FlatPrinter.new(result).print($stdout) # exit diff --git a/lib/cfg_arch.rb b/lib/cfg_arch.rb index 05d4531912..47fb388454 100644 --- a/lib/cfg_arch.rb +++ b/lib/cfg_arch.rb @@ -215,10 +215,10 @@ def type_check(show_progress: true, io: $stdout) io.puts "Type checking IDL code for #{@config.name}..." progressbar = if show_progress - ProgressBar.create(title: "Instructions", total: instructions.size) + ProgressBar.create(title: "Instructions", total: possible_instructions.size) end - instructions.each do |inst| + possible_instructions.each do |inst| progressbar.increment if show_progress if @mxlen == 32 inst.type_checked_operation_ast(32) if inst.rv32? @@ -230,10 +230,10 @@ def type_check(show_progress: true, io: $stdout) progressbar = if show_progress - ProgressBar.create(title: "CSRs", total: csrs.size) + ProgressBar.create(title: "CSRs", total: possible_csrs.size) end - csrs.each do |csr| + possible_csrs.each do |csr| progressbar.increment if show_progress if csr.has_custom_sw_read? if (possible_xlens.include?(32) && csr.defined_in_base32?) @@ -265,11 +265,12 @@ def type_check(show_progress: true, io: $stdout) end end + func_list = reachable_functions progressbar = if show_progress - ProgressBar.create(title: "Functions", total: functions.size) + ProgressBar.create(title: "Functions", total: func_list.size) end - functions.each do |func| + func_list.each do |func| progressbar.increment if show_progress func.type_check(@symtab) end diff --git a/lib/idl/ast.rb b/lib/idl/ast.rb index 23ac6dd49a..17a135423f 100644 --- a/lib/idl/ast.rb +++ b/lib/idl/ast.rb @@ -2377,7 +2377,9 @@ def type_check(symtab, add_sym = true) value_else(value_result) do # if this is a fully configured ConfiguredArchitecture, this is an error because all constants are supposed to be known if symtab.cfg_arch.fully_configured? - type_error "Array size (#{ary_size.text_value}) must be known at compile time" + unless ary_size.type(symtab).template_var? + type_error "Array size (#{ary_size.text_value}) must be known at compile time" + end else # otherwise, it's ok that we don't know the value yet, as long as the value is a const type_error "Array size (#{ary_size.text_value}) must be a constant" unless ary_size.type(symtab).const? @@ -4367,7 +4369,11 @@ def type_check(symtab) end end value_else(value_result) do - type_error "Bit width must be known at compile time" if symtab.cfg_arch.fully_configured? + unless bits_expression.type(symtab).template_var? + if symtab.cfg_arch.fully_configured? + type_error "Bit width (#{bits_expression.text_value}) must be known at compile time" + end + end end end unless ["Bits", "String", "XReg", "Boolean", "U32", "U64"].include?(@type_name) @@ -4906,6 +4912,16 @@ def value(symtab) value_error "maybe_cache_translation is not compile-time-knowable" elsif name == "invalidate_translations" value_error "invalidate_translations is not compile-time-knowable" + elsif name == "direct_csr_lookup" + value_error "direct_csr_lookup is not compile-time-knowable" + elsif name == "indirect_csr_lookup" + value_error "indirect_csr_lookup is not compile-time-knowable" + elsif name == "csr_hw_read" + value_error "csr_hw_read is not compile-time-knowable" + elsif name == "csr_sw_read" + value_error "csr_sw_read is not compile-time-knowable" + elsif name == "csr_sw_write" + value_error "csr_sw_write is not compile-time-knowable" else internal_error "Unimplemented generated: '#{name}'" end @@ -5352,7 +5368,7 @@ def type_check(symtab) symtab = symtab.deep_clone symtab.push(self) template_names.each_with_index do |tname, index| - symtab.add(tname, Var.new(tname, template_types(symtab)[index])) + symtab.add(tname, Var.new(tname, template_types(symtab)[index], template_index: index)) end type_check_return(symtab) @@ -5399,6 +5415,7 @@ def template_types(symtab) ttype = a.type(symtab) ttype = ttype.ref_type if ttype.kind == :enum ttypes << ttype.clone.make_const + ttypes.last.qualify(:template_var) end ttypes end @@ -6109,7 +6126,7 @@ def calc_value(symtab) class CsrReadExpressionSyntaxNode < Treetop::Runtime::SyntaxNode def to_ast - CsrReadExpressionAst.new(input, interval, idx.text_value) + CsrReadExpressionAst.new(input, interval, csr_name.text_value) end end @@ -6122,13 +6139,12 @@ def to_ast class CsrReadExpressionAst < AstNode include Rvalue - attr_reader :idx_text - attr_reader :idx_expr + attr_reader :csr_name - def initialize(input, interval, idx) + def initialize(input, interval, csr_name) super(input, interval, []) - @idx_text = idx + @csr_name = csr_name end def freeze_tree(symtab) @@ -6136,73 +6152,25 @@ def freeze_tree(symtab) @cfg_arch = symtab.cfg_arch # remember cfg_arch, used by gen_adoc pass - if symtab.cfg_arch.csr(@idx_text).nil? - parser = symtab.cfg_arch.idl_compiler.parser - expr = parser.parse(@idx_text, root: :expression) + type_error "CSR '#{@csr_name}' is not defined" if symtab.cfg_arch.csr(@csr_name).nil? + @csr_obj = symtab.cfg_arch.csr(@csr_name) - type_error "#{@idx_text} is not a CSR; it must be an expression" if expr.nil? - - @idx_expr = expr.to_ast - @children << @idx_expr - else - @csr_obj = symtab.cfg_arch.csr(@idx_text) - end + @type = CsrType.new(@csr_obj, symtab.cfg_arch) @children.each { |child| child.freeze_tree(symtab) } freeze end # @!macro type - def type(symtab) - cfg_arch = symtab.cfg_arch - - cd = csr_def(symtab) - if cd.nil? - # we don't know anything about this index, so we can only - # treat this as a generic - CsrType.new(:unknown, cfg_arch) - else - CsrType.new(cd, cfg_arch) - end - end + def type(symtab) = @type # @!macro type_check def type_check(symtab) - cfg_arch = symtab.cfg_arch - - if !@csr_obj.nil? - # this is a known csr name - # nothing else to check - - else - # this is an expression - @idx_expr.type_check(symtab) - type_error "Csr index must be integral" unless @idx_expr.type(symtab).integral? - - value_try do - idx_value = @idx_expr.value(symtab) - csr_index = cfg_arch.csrs.index { |csr| csr.address == idx_value } - type_error "No csr number '#{idx_value}' was found" if csr_index.nil? - :ok - end - # OK, index doesn't have to be known - end + type_error "CSR '#{@csr_name}' is not defined" if symtab.cfg_arch.csr(@csr_name).nil? end def csr_def(symtab) - cfg_arch = symtab.cfg_arch - if !@csr_obj.nil? - # this is a known csr name - @csr_obj - else - # this is an expression - value_try do - idx_value = @idx_expr.value(symtab) - return cfg_arch.csrs.find { |csr| csr.address == idx_value } - end - # || we don't know at compile time which CSR this is... - nil - end + @csr_obj end def csr_known?(symtab) @@ -6217,20 +6185,18 @@ def csr_name(symtab) # @!macro value def value(symtab) - cd = csr_def(symtab) - value_error "CSR number not knowable" if cd.nil? if symtab.cfg_arch.fully_configured? - value_error "CSR is not implemented" unless symtab.cfg_arch.transitive_implemented_csrs.any? { |icsr| icsr.name == cd.name } + value_error "CSR is not implemented" unless symtab.cfg_arch.transitive_implemented_csrs.any? { |icsr| icsr.name == @csr_obj.name } else - value_error "CSR is not defined" unless symtab.cfg_arch.csrs.any? { |icsr| icsr.name == cd.name } + value_error "CSR is not defined" unless symtab.cfg_arch.csrs.any? { |icsr| icsr.name == @csr_obj.name } end - cd.fields.each { |f| value_error "#{csr_name(symtab)}.#{f.name} not RO" unless f.type(symtab) == "RO" } + @csr_obj.fields.each { |f| value_error "#{csr_name(symtab)}.#{f.name} not RO" unless f.type(symtab) == "RO" } csr_def(symtab).fields.reduce(0) { |val, f| val | (f.value << f.location.begin) } end # @!macro to_idl - def to_idl = "CSR[#{@idx.to_idl}]" + def to_idl = "CSR[#{@csr_name}]" end class CsrSoftwareWriteSyntaxNode < Treetop::Runtime::SyntaxNode diff --git a/lib/idl/idl.treetop b/lib/idl/idl.treetop index 9cead8a2b2..c30be56d24 100644 --- a/lib/idl/idl.treetop +++ b/lib/idl/idl.treetop @@ -275,7 +275,7 @@ grammar Idl rule csr_register_access_expression # CSR register access - 'CSR' space* '[' space* idx:(expression / csr_name) space* ']' + 'CSR' space* '[' space* csr_name space* ']' end rule field_access_eligible_expression @@ -652,7 +652,7 @@ grammar Idl end rule var_write - 'CSR' space* '[' space* idx:(csr_name / int) space* ']' + 'CSR' space* '[' space* csr_name space* ']' / id end diff --git a/lib/idl/passes/gen_adoc.rb b/lib/idl/passes/gen_adoc.rb index 5dde948cd6..355596e1d9 100644 --- a/lib/idl/passes/gen_adoc.rb +++ b/lib/idl/passes/gen_adoc.rb @@ -299,24 +299,8 @@ def gen_adoc(indent = 0, indent_spaces: 2) class CsrReadExpressionAst def gen_adoc(indent = 0, indent_spaces: 2) - idx = - if @idx_expr.nil? - @idx_text - else - @idx_expr.gen_adoc(0) - end - csr_text = "CSR[#{idx}]" - if idx_text =~ /[0-9]+/ - # we don't have the symtab to map this to a csr name - "#{' '*indent}#{csr_text}" - else - if @cfg_arch.csr(csr_text).nil? - "#{' '*indent}#{csr_text}" - else - "#{' '*indent}%%LINK%csr;#{idx};#{csr_text}%%" - end - end + "#{' '*indent}%%LINK%csr;#{csr_name};#{csr_text}%%" end end diff --git a/lib/idl/symbol_table.rb b/lib/idl/symbol_table.rb index d59ee0422f..24f0fa44e1 100644 --- a/lib/idl/symbol_table.rb +++ b/lib/idl/symbol_table.rb @@ -14,6 +14,7 @@ def initialize(name, type, value = nil, decode_var: false, template_index: nil, raise ArgumentError, "Expecting a Type, got #{type.class.name}" unless type.is_a?(Type) @type = type + @type.qualify(:template_var) @type.freeze @value = value raise "unexpected" unless decode_var.is_a?(TrueClass) || decode_var.is_a?(FalseClass) diff --git a/lib/idl/type.rb b/lib/idl/type.rb index 0b582e4584..1ae0bc6fc8 100644 --- a/lib/idl/type.rb +++ b/lib/idl/type.rb @@ -22,7 +22,8 @@ class Type QUALIFIERS = [ :const, :signed, - :global + :global, + :template_var ].freeze # true for any type that can generally be treated as a scalar integer @@ -394,6 +395,10 @@ def global? @qualifiers.include?(:global) end + def template_var? + @qualifiers.include?(:template_var) + end + def make_signed @qualifiers.append(:signed).uniq! self From fe3dc19054cf730735396651327d8a1998fcfdab Mon Sep 17 00:00:00 2001 From: Derek Hower Date: Fri, 4 Apr 2025 11:02:09 -0700 Subject: [PATCH 07/15] schema(csr): add writeable field This adds a boolean writeable field to the CSR schema. We need this for two reasons: * Indirect CSRs that have no address convention * CSRs like mscontext that don't follow the direct address convention --- arch/csr/F/fcsr.yaml | 1 + arch/csr/H/hcounteren.yaml | 1 + arch/csr/H/henvcfg.yaml | 1 + arch/csr/H/henvcfgh.yaml | 1 + arch/csr/H/hgatp.yaml | 1 + arch/csr/H/htimedelta.yaml | 1 + arch/csr/H/htimedeltah.yaml | 1 + arch/csr/H/htinst.yaml | 1 + arch/csr/H/htval.yaml | 1 + arch/csr/H/mtinst.yaml | 1 + arch/csr/H/mtval2.yaml | 1 + arch/csr/H/vsatp.yaml | 1 + arch/csr/I/mcounteren.yaml | 1 + arch/csr/I/pmpaddr0.yaml | 1 + arch/csr/I/pmpaddr1.yaml | 1 + arch/csr/I/pmpaddr10.yaml | 1 + arch/csr/I/pmpaddr11.yaml | 1 + arch/csr/I/pmpaddr12.yaml | 1 + arch/csr/I/pmpaddr13.yaml | 1 + arch/csr/I/pmpaddr14.yaml | 1 + arch/csr/I/pmpaddr15.yaml | 1 + arch/csr/I/pmpaddr16.yaml | 1 + arch/csr/I/pmpaddr17.yaml | 1 + arch/csr/I/pmpaddr18.yaml | 1 + arch/csr/I/pmpaddr19.yaml | 1 + arch/csr/I/pmpaddr2.yaml | 1 + arch/csr/I/pmpaddr20.yaml | 1 + arch/csr/I/pmpaddr21.yaml | 1 + arch/csr/I/pmpaddr22.yaml | 1 + arch/csr/I/pmpaddr23.yaml | 1 + arch/csr/I/pmpaddr24.yaml | 1 + arch/csr/I/pmpaddr25.yaml | 1 + arch/csr/I/pmpaddr26.yaml | 1 + arch/csr/I/pmpaddr27.yaml | 1 + arch/csr/I/pmpaddr28.yaml | 1 + arch/csr/I/pmpaddr29.yaml | 1 + arch/csr/I/pmpaddr3.yaml | 1 + arch/csr/I/pmpaddr30.yaml | 1 + arch/csr/I/pmpaddr31.yaml | 1 + arch/csr/I/pmpaddr32.yaml | 1 + arch/csr/I/pmpaddr33.yaml | 1 + arch/csr/I/pmpaddr34.yaml | 1 + arch/csr/I/pmpaddr35.yaml | 1 + arch/csr/I/pmpaddr36.yaml | 1 + arch/csr/I/pmpaddr37.yaml | 1 + arch/csr/I/pmpaddr38.yaml | 1 + arch/csr/I/pmpaddr39.yaml | 1 + arch/csr/I/pmpaddr4.yaml | 1 + arch/csr/I/pmpaddr40.yaml | 1 + arch/csr/I/pmpaddr41.yaml | 1 + arch/csr/I/pmpaddr42.yaml | 1 + arch/csr/I/pmpaddr43.yaml | 1 + arch/csr/I/pmpaddr44.yaml | 1 + arch/csr/I/pmpaddr45.yaml | 1 + arch/csr/I/pmpaddr46.yaml | 1 + arch/csr/I/pmpaddr47.yaml | 1 + arch/csr/I/pmpaddr48.yaml | 1 + arch/csr/I/pmpaddr49.yaml | 1 + arch/csr/I/pmpaddr5.yaml | 1 + arch/csr/I/pmpaddr50.yaml | 1 + arch/csr/I/pmpaddr51.yaml | 1 + arch/csr/I/pmpaddr52.yaml | 1 + arch/csr/I/pmpaddr53.yaml | 1 + arch/csr/I/pmpaddr54.yaml | 1 + arch/csr/I/pmpaddr55.yaml | 1 + arch/csr/I/pmpaddr56.yaml | 1 + arch/csr/I/pmpaddr57.yaml | 1 + arch/csr/I/pmpaddr58.yaml | 1 + arch/csr/I/pmpaddr59.yaml | 1 + arch/csr/I/pmpaddr6.yaml | 1 + arch/csr/I/pmpaddr60.yaml | 1 + arch/csr/I/pmpaddr61.yaml | 1 + arch/csr/I/pmpaddr62.yaml | 1 + arch/csr/I/pmpaddr63.yaml | 1 + arch/csr/I/pmpaddr7.yaml | 1 + arch/csr/I/pmpaddr8.yaml | 1 + arch/csr/I/pmpaddr9.yaml | 1 + arch/csr/I/pmpcfg0.yaml | 1 + arch/csr/I/pmpcfg1.yaml | 1 + arch/csr/I/pmpcfg10.yaml | 1 + arch/csr/I/pmpcfg11.yaml | 1 + arch/csr/I/pmpcfg12.yaml | 1 + arch/csr/I/pmpcfg13.yaml | 1 + arch/csr/I/pmpcfg14.yaml | 1 + arch/csr/I/pmpcfg15.yaml | 1 + arch/csr/I/pmpcfg2.yaml | 1 + arch/csr/I/pmpcfg3.yaml | 1 + arch/csr/I/pmpcfg4.yaml | 1 + arch/csr/I/pmpcfg5.yaml | 1 + arch/csr/I/pmpcfg6.yaml | 1 + arch/csr/I/pmpcfg7.yaml | 1 + arch/csr/I/pmpcfg8.yaml | 1 + arch/csr/I/pmpcfg9.yaml | 1 + arch/csr/S/scounteren.yaml | 1 + arch/csr/Smrnmi/mncause.yaml | 1 + arch/csr/Smrnmi/mnepc.yaml | 1 + arch/csr/Smrnmi/mnscratch.yaml | 5 ++++- arch/csr/Smrnmi/mnstatus.yaml | 5 ++++- arch/csr/Zicntr/mcountinhibit.yaml | 1 + arch/csr/Zihpm/hpmcounter10.yaml | 1 + arch/csr/Zihpm/hpmcounter10h.yaml | 1 + arch/csr/Zihpm/hpmcounter11.yaml | 1 + arch/csr/Zihpm/hpmcounter11h.yaml | 1 + arch/csr/Zihpm/hpmcounter12.yaml | 1 + arch/csr/Zihpm/hpmcounter12h.yaml | 1 + arch/csr/Zihpm/hpmcounter13.yaml | 1 + arch/csr/Zihpm/hpmcounter13h.yaml | 1 + arch/csr/Zihpm/hpmcounter14.yaml | 1 + arch/csr/Zihpm/hpmcounter14h.yaml | 1 + arch/csr/Zihpm/hpmcounter15.yaml | 1 + arch/csr/Zihpm/hpmcounter15h.yaml | 1 + arch/csr/Zihpm/hpmcounter16.yaml | 1 + arch/csr/Zihpm/hpmcounter16h.yaml | 1 + arch/csr/Zihpm/hpmcounter17.yaml | 1 + arch/csr/Zihpm/hpmcounter17h.yaml | 1 + arch/csr/Zihpm/hpmcounter18.yaml | 1 + arch/csr/Zihpm/hpmcounter18h.yaml | 1 + arch/csr/Zihpm/hpmcounter19.yaml | 1 + arch/csr/Zihpm/hpmcounter19h.yaml | 1 + arch/csr/Zihpm/hpmcounter20.yaml | 1 + arch/csr/Zihpm/hpmcounter20h.yaml | 1 + arch/csr/Zihpm/hpmcounter21.yaml | 1 + arch/csr/Zihpm/hpmcounter21h.yaml | 1 + arch/csr/Zihpm/hpmcounter22.yaml | 1 + arch/csr/Zihpm/hpmcounter22h.yaml | 1 + arch/csr/Zihpm/hpmcounter23.yaml | 1 + arch/csr/Zihpm/hpmcounter23h.yaml | 1 + arch/csr/Zihpm/hpmcounter24.yaml | 1 + arch/csr/Zihpm/hpmcounter24h.yaml | 1 + arch/csr/Zihpm/hpmcounter25.yaml | 1 + arch/csr/Zihpm/hpmcounter25h.yaml | 1 + arch/csr/Zihpm/hpmcounter26.yaml | 1 + arch/csr/Zihpm/hpmcounter26h.yaml | 1 + arch/csr/Zihpm/hpmcounter27.yaml | 1 + arch/csr/Zihpm/hpmcounter27h.yaml | 1 + arch/csr/Zihpm/hpmcounter28.yaml | 1 + arch/csr/Zihpm/hpmcounter28h.yaml | 1 + arch/csr/Zihpm/hpmcounter29.yaml | 1 + arch/csr/Zihpm/hpmcounter29h.yaml | 1 + arch/csr/Zihpm/hpmcounter3.yaml | 1 + arch/csr/Zihpm/hpmcounter30.yaml | 1 + arch/csr/Zihpm/hpmcounter30h.yaml | 1 + arch/csr/Zihpm/hpmcounter31.yaml | 1 + arch/csr/Zihpm/hpmcounter31h.yaml | 1 + arch/csr/Zihpm/hpmcounter3h.yaml | 1 + arch/csr/Zihpm/hpmcounter4.yaml | 1 + arch/csr/Zihpm/hpmcounter4h.yaml | 1 + arch/csr/Zihpm/hpmcounter5.yaml | 1 + arch/csr/Zihpm/hpmcounter5h.yaml | 1 + arch/csr/Zihpm/hpmcounter6.yaml | 1 + arch/csr/Zihpm/hpmcounter6h.yaml | 1 + arch/csr/Zihpm/hpmcounter7.yaml | 1 + arch/csr/Zihpm/hpmcounter7h.yaml | 1 + arch/csr/Zihpm/hpmcounter8.yaml | 1 + arch/csr/Zihpm/hpmcounter8h.yaml | 1 + arch/csr/Zihpm/hpmcounter9.yaml | 1 + arch/csr/Zihpm/hpmcounter9h.yaml | 1 + arch/csr/Zihpm/mhpmcounter10.yaml | 1 + arch/csr/Zihpm/mhpmcounter10h.yaml | 1 + arch/csr/Zihpm/mhpmcounter11.yaml | 1 + arch/csr/Zihpm/mhpmcounter11h.yaml | 1 + arch/csr/Zihpm/mhpmcounter12.yaml | 1 + arch/csr/Zihpm/mhpmcounter12h.yaml | 1 + arch/csr/Zihpm/mhpmcounter13.yaml | 1 + arch/csr/Zihpm/mhpmcounter13h.yaml | 1 + arch/csr/Zihpm/mhpmcounter14.yaml | 1 + arch/csr/Zihpm/mhpmcounter14h.yaml | 1 + arch/csr/Zihpm/mhpmcounter15.yaml | 1 + arch/csr/Zihpm/mhpmcounter15h.yaml | 1 + arch/csr/Zihpm/mhpmcounter16.yaml | 1 + arch/csr/Zihpm/mhpmcounter16h.yaml | 1 + arch/csr/Zihpm/mhpmcounter17.yaml | 1 + arch/csr/Zihpm/mhpmcounter17h.yaml | 1 + arch/csr/Zihpm/mhpmcounter18.yaml | 1 + arch/csr/Zihpm/mhpmcounter18h.yaml | 1 + arch/csr/Zihpm/mhpmcounter19.yaml | 1 + arch/csr/Zihpm/mhpmcounter19h.yaml | 1 + arch/csr/Zihpm/mhpmcounter20.yaml | 1 + arch/csr/Zihpm/mhpmcounter20h.yaml | 1 + arch/csr/Zihpm/mhpmcounter21.yaml | 1 + arch/csr/Zihpm/mhpmcounter21h.yaml | 1 + arch/csr/Zihpm/mhpmcounter22.yaml | 1 + arch/csr/Zihpm/mhpmcounter22h.yaml | 1 + arch/csr/Zihpm/mhpmcounter23.yaml | 1 + arch/csr/Zihpm/mhpmcounter23h.yaml | 1 + arch/csr/Zihpm/mhpmcounter24.yaml | 1 + arch/csr/Zihpm/mhpmcounter24h.yaml | 1 + arch/csr/Zihpm/mhpmcounter25.yaml | 1 + arch/csr/Zihpm/mhpmcounter25h.yaml | 1 + arch/csr/Zihpm/mhpmcounter26.yaml | 1 + arch/csr/Zihpm/mhpmcounter26h.yaml | 1 + arch/csr/Zihpm/mhpmcounter27.yaml | 1 + arch/csr/Zihpm/mhpmcounter27h.yaml | 1 + arch/csr/Zihpm/mhpmcounter28.yaml | 1 + arch/csr/Zihpm/mhpmcounter28h.yaml | 1 + arch/csr/Zihpm/mhpmcounter29.yaml | 1 + arch/csr/Zihpm/mhpmcounter29h.yaml | 1 + arch/csr/Zihpm/mhpmcounter3.yaml | 1 + arch/csr/Zihpm/mhpmcounter30.yaml | 1 + arch/csr/Zihpm/mhpmcounter30h.yaml | 1 + arch/csr/Zihpm/mhpmcounter31.yaml | 1 + arch/csr/Zihpm/mhpmcounter31h.yaml | 1 + arch/csr/Zihpm/mhpmcounter3h.yaml | 1 + arch/csr/Zihpm/mhpmcounter4.yaml | 1 + arch/csr/Zihpm/mhpmcounter4h.yaml | 1 + arch/csr/Zihpm/mhpmcounter5.yaml | 1 + arch/csr/Zihpm/mhpmcounter5h.yaml | 1 + arch/csr/Zihpm/mhpmcounter6.yaml | 1 + arch/csr/Zihpm/mhpmcounter6h.yaml | 1 + arch/csr/Zihpm/mhpmcounter7.yaml | 1 + arch/csr/Zihpm/mhpmcounter7h.yaml | 1 + arch/csr/Zihpm/mhpmcounter8.yaml | 1 + arch/csr/Zihpm/mhpmcounter8h.yaml | 1 + arch/csr/Zihpm/mhpmcounter9.yaml | 1 + arch/csr/Zihpm/mhpmcounter9h.yaml | 1 + arch/csr/Zihpm/mhpmevent10.yaml | 21 ++++++++++++++++----- arch/csr/Zihpm/mhpmevent10h.yaml | 1 + arch/csr/Zihpm/mhpmevent11.yaml | 21 ++++++++++++++++----- arch/csr/Zihpm/mhpmevent11h.yaml | 1 + arch/csr/Zihpm/mhpmevent12.yaml | 21 ++++++++++++++++----- arch/csr/Zihpm/mhpmevent12h.yaml | 1 + arch/csr/Zihpm/mhpmevent13.yaml | 21 ++++++++++++++++----- arch/csr/Zihpm/mhpmevent13h.yaml | 1 + arch/csr/Zihpm/mhpmevent14.yaml | 21 ++++++++++++++++----- arch/csr/Zihpm/mhpmevent14h.yaml | 1 + arch/csr/Zihpm/mhpmevent15.yaml | 21 ++++++++++++++++----- arch/csr/Zihpm/mhpmevent15h.yaml | 1 + arch/csr/Zihpm/mhpmevent16.yaml | 21 ++++++++++++++++----- arch/csr/Zihpm/mhpmevent16h.yaml | 1 + arch/csr/Zihpm/mhpmevent17.yaml | 21 ++++++++++++++++----- arch/csr/Zihpm/mhpmevent17h.yaml | 1 + arch/csr/Zihpm/mhpmevent18.yaml | 21 ++++++++++++++++----- arch/csr/Zihpm/mhpmevent18h.yaml | 1 + arch/csr/Zihpm/mhpmevent19.yaml | 21 ++++++++++++++++----- arch/csr/Zihpm/mhpmevent19h.yaml | 1 + arch/csr/Zihpm/mhpmevent20.yaml | 21 ++++++++++++++++----- arch/csr/Zihpm/mhpmevent20h.yaml | 1 + arch/csr/Zihpm/mhpmevent21.yaml | 21 ++++++++++++++++----- arch/csr/Zihpm/mhpmevent21h.yaml | 1 + arch/csr/Zihpm/mhpmevent22.yaml | 21 ++++++++++++++++----- arch/csr/Zihpm/mhpmevent22h.yaml | 1 + arch/csr/Zihpm/mhpmevent23.yaml | 21 ++++++++++++++++----- arch/csr/Zihpm/mhpmevent23h.yaml | 1 + arch/csr/Zihpm/mhpmevent24.yaml | 21 ++++++++++++++++----- arch/csr/Zihpm/mhpmevent24h.yaml | 1 + arch/csr/Zihpm/mhpmevent25.yaml | 21 ++++++++++++++++----- arch/csr/Zihpm/mhpmevent25h.yaml | 1 + arch/csr/Zihpm/mhpmevent26.yaml | 21 ++++++++++++++++----- arch/csr/Zihpm/mhpmevent26h.yaml | 1 + arch/csr/Zihpm/mhpmevent27.yaml | 21 ++++++++++++++++----- arch/csr/Zihpm/mhpmevent27h.yaml | 1 + arch/csr/Zihpm/mhpmevent28.yaml | 21 ++++++++++++++++----- arch/csr/Zihpm/mhpmevent28h.yaml | 1 + arch/csr/Zihpm/mhpmevent29.yaml | 21 ++++++++++++++++----- arch/csr/Zihpm/mhpmevent29h.yaml | 1 + arch/csr/Zihpm/mhpmevent3.yaml | 21 ++++++++++++++++----- arch/csr/Zihpm/mhpmevent30.yaml | 21 ++++++++++++++++----- arch/csr/Zihpm/mhpmevent30h.yaml | 1 + arch/csr/Zihpm/mhpmevent31.yaml | 21 ++++++++++++++++----- arch/csr/Zihpm/mhpmevent31h.yaml | 1 + arch/csr/Zihpm/mhpmevent3h.yaml | 1 + arch/csr/Zihpm/mhpmevent4.yaml | 21 ++++++++++++++++----- arch/csr/Zihpm/mhpmevent4h.yaml | 1 + arch/csr/Zihpm/mhpmevent5.yaml | 21 ++++++++++++++++----- arch/csr/Zihpm/mhpmevent5h.yaml | 1 + arch/csr/Zihpm/mhpmevent6.yaml | 21 ++++++++++++++++----- arch/csr/Zihpm/mhpmevent6h.yaml | 1 + arch/csr/Zihpm/mhpmevent7.yaml | 21 ++++++++++++++++----- arch/csr/Zihpm/mhpmevent7h.yaml | 1 + arch/csr/Zihpm/mhpmevent8.yaml | 21 ++++++++++++++++----- arch/csr/Zihpm/mhpmevent8h.yaml | 1 + arch/csr/Zihpm/mhpmevent9.yaml | 21 ++++++++++++++++----- arch/csr/Zihpm/mhpmevent9h.yaml | 1 + arch/csr/cycle.yaml | 1 + arch/csr/cycleh.yaml | 1 + arch/csr/hedeleg.yaml | 1 + arch/csr/hedelegh.yaml | 1 + arch/csr/hstatus.yaml | 1 + arch/csr/instret.yaml | 1 + arch/csr/instreth.yaml | 1 + arch/csr/marchid.yaml | 1 + arch/csr/mcause.yaml | 1 + arch/csr/mconfigptr.yaml | 5 ++++- arch/csr/mcycle.yaml | 1 + arch/csr/mcycleh.yaml | 1 + arch/csr/medeleg.yaml | 1 + arch/csr/medelegh.yaml | 1 + arch/csr/menvcfg.yaml | 1 + arch/csr/menvcfgh.yaml | 1 + arch/csr/mepc.yaml | 1 + arch/csr/mhartid.yaml | 1 + arch/csr/mideleg.yaml | 1 + arch/csr/mie.yaml | 1 + arch/csr/mimpid.yaml | 1 + arch/csr/minstret.yaml | 1 + arch/csr/minstreth.yaml | 1 + arch/csr/mip.yaml | 1 + arch/csr/misa.yaml | 1 + arch/csr/mscratch.yaml | 1 + arch/csr/mseccfg.yaml | 1 + arch/csr/mseccfgh.yaml | 1 + arch/csr/mstatus.yaml | 5 ++++- arch/csr/mstatush.yaml | 5 ++++- arch/csr/mtval.yaml | 1 + arch/csr/mtvec.yaml | 1 + arch/csr/mvendorid.yaml | 1 + arch/csr/satp.yaml | 5 ++++- arch/csr/scause.yaml | 1 + arch/csr/senvcfg.yaml | 1 + arch/csr/sepc.yaml | 1 + arch/csr/sip.yaml | 1 + arch/csr/sscratch.yaml | 1 + arch/csr/sstatus.yaml | 1 + arch/csr/stval.yaml | 1 + arch/csr/stvec.yaml | 1 + arch/csr/time.yaml | 1 + arch/csr/timeh.yaml | 1 + arch/csr/vscause.yaml | 1 + arch/csr/vsepc.yaml | 1 + arch/csr/vsstatus.yaml | 1 + arch/csr/vstval.yaml | 1 + arch/csr/vstvec.yaml | 1 + schemas/csr_schema.json | 5 ++--- 323 files changed, 777 insertions(+), 154 deletions(-) diff --git a/arch/csr/F/fcsr.yaml b/arch/csr/F/fcsr.yaml index a44a5b39c7..d1cd315e8d 100644 --- a/arch/csr/F/fcsr.yaml +++ b/arch/csr/F/fcsr.yaml @@ -5,6 +5,7 @@ kind: csr name: fcsr long_name: Floating-point control and status register (`frm` + `fflags`) address: 0x003 +writeable: true description: | The floating-point control and status register, `fcsr`, is a RISC-V control and status register (CSR). It is a 32-bit read/write register diff --git a/arch/csr/H/hcounteren.yaml b/arch/csr/H/hcounteren.yaml index 45a80cfa49..1f0cacb970 100644 --- a/arch/csr/H/hcounteren.yaml +++ b/arch/csr/H/hcounteren.yaml @@ -6,6 +6,7 @@ kind: csr name: hcounteren long_name: Hypervisor Counter Enable address: 0x606 +writeable: true priv_mode: S length: 32 description: | diff --git a/arch/csr/H/henvcfg.yaml b/arch/csr/H/henvcfg.yaml index 462bc0f138..719a45345d 100644 --- a/arch/csr/H/henvcfg.yaml +++ b/arch/csr/H/henvcfg.yaml @@ -4,6 +4,7 @@ $schema: "csr_schema.json#" kind: csr name: henvcfg address: 0x60A +writeable: true long_name: Hypervisor Environment Configuration description: | The henvcfg CSR is a 64-bit read/write register that controls certain characteristics of the diff --git a/arch/csr/H/henvcfgh.yaml b/arch/csr/H/henvcfgh.yaml index 4f136fce3f..1b423c783e 100644 --- a/arch/csr/H/henvcfgh.yaml +++ b/arch/csr/H/henvcfgh.yaml @@ -4,6 +4,7 @@ $schema: "csr_schema.json#" kind: csr name: henvcfgh address: 0x61A +writeable: true base: 32 long_name: most-significant 32 bits of Hypervisor Environment Configuration description: | diff --git a/arch/csr/H/hgatp.yaml b/arch/csr/H/hgatp.yaml index 034b1d0178..b890bdc7cd 100644 --- a/arch/csr/H/hgatp.yaml +++ b/arch/csr/H/hgatp.yaml @@ -102,6 +102,7 @@ description: | HFENCE.GVMA instruction (see <>) before or after writing `hgatp`. address: 0x680 +writeable: true priv_mode: S definedBy: H length: SXLEN diff --git a/arch/csr/H/htimedelta.yaml b/arch/csr/H/htimedelta.yaml index 48de13f532..be9572cfa6 100644 --- a/arch/csr/H/htimedelta.yaml +++ b/arch/csr/H/htimedelta.yaml @@ -15,6 +15,7 @@ description: | `htimedelta` may be used to represent negative time offsets. address: 0x605 +writeable: true priv_mode: S definedBy: H length: 64 diff --git a/arch/csr/H/htimedeltah.yaml b/arch/csr/H/htimedeltah.yaml index 9aad2147e5..663b3e61be 100644 --- a/arch/csr/H/htimedeltah.yaml +++ b/arch/csr/H/htimedeltah.yaml @@ -8,6 +8,7 @@ description: | Upper half of the `htimedelta` CSR. address: 0x615 +writeable: true priv_mode: S definedBy: H length: 32 diff --git a/arch/csr/H/htinst.yaml b/arch/csr/H/htinst.yaml index f4a9df9e4a..6c1edf713b 100644 --- a/arch/csr/H/htinst.yaml +++ b/arch/csr/H/htinst.yaml @@ -4,6 +4,7 @@ $schema: "csr_schema.json#" kind: csr name: htinst address: 0x64a +writeable: true long_name: Hypervisor Trap Instruction Register description: | When a trap is taken into HS-mode, mtinst is written with a value that, if nonzero, diff --git a/arch/csr/H/htval.yaml b/arch/csr/H/htval.yaml index 39631dcfc2..2f3498e01d 100644 --- a/arch/csr/H/htval.yaml +++ b/arch/csr/H/htval.yaml @@ -4,6 +4,7 @@ $schema: "csr_schema.json#" kind: csr name: htval address: 0x643 +writeable: true long_name: Hypervisor Trap Value Register description: | When a trap is taken into HS-mode, htval is written with additional exception-specific information, alongside stval, to assist software in handling the trap. diff --git a/arch/csr/H/mtinst.yaml b/arch/csr/H/mtinst.yaml index bbfff0cd32..a145cb4124 100644 --- a/arch/csr/H/mtinst.yaml +++ b/arch/csr/H/mtinst.yaml @@ -4,6 +4,7 @@ $schema: "csr_schema.json#" kind: csr name: mtinst address: 0x34a +writeable: true long_name: Machine Trap Instruction Register description: | When a trap is taken into M-mode, mtinst is written with a value that, if nonzero, diff --git a/arch/csr/H/mtval2.yaml b/arch/csr/H/mtval2.yaml index 03d5db862f..fce637d5c1 100644 --- a/arch/csr/H/mtval2.yaml +++ b/arch/csr/H/mtval2.yaml @@ -4,6 +4,7 @@ $schema: "csr_schema.json#" kind: csr name: mtval2 address: 0x34b +writeable: true long_name: Machine Second Trap Value Register description: | When a trap is taken into M-mode from a virtual mode, mtval2 is written with additional exception-specific information, diff --git a/arch/csr/H/vsatp.yaml b/arch/csr/H/vsatp.yaml index fef44032c4..21d5489a5f 100644 --- a/arch/csr/H/vsatp.yaml +++ b/arch/csr/H/vsatp.yaml @@ -4,6 +4,7 @@ $schema: "csr_schema.json#" kind: csr name: vsatp address: 0x280 +writeable: true virtual_address: 0x180 long_name: Virtual Supervisor Address Translation and Protection description: | diff --git a/arch/csr/I/mcounteren.yaml b/arch/csr/I/mcounteren.yaml index 7d2e0dbac2..4b463a6c71 100644 --- a/arch/csr/I/mcounteren.yaml +++ b/arch/csr/I/mcounteren.yaml @@ -6,6 +6,7 @@ kind: csr name: mcounteren long_name: Machine Counter Enable address: 0x306 +writeable: true priv_mode: M length: 32 description: | diff --git a/arch/csr/I/pmpaddr0.yaml b/arch/csr/I/pmpaddr0.yaml index 250d438c06..260044ac66 100644 --- a/arch/csr/I/pmpaddr0.yaml +++ b/arch/csr/I/pmpaddr0.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr0 long_name: PMP Address 0 address: 0x3B0 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr1.yaml b/arch/csr/I/pmpaddr1.yaml index 5e24bf677c..3bd35c72f1 100644 --- a/arch/csr/I/pmpaddr1.yaml +++ b/arch/csr/I/pmpaddr1.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr1 long_name: PMP Address 1 address: 0x3B1 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr10.yaml b/arch/csr/I/pmpaddr10.yaml index a7da04a4b6..060fdf466a 100644 --- a/arch/csr/I/pmpaddr10.yaml +++ b/arch/csr/I/pmpaddr10.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr10 long_name: PMP Address 10 address: 0x3BA +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr11.yaml b/arch/csr/I/pmpaddr11.yaml index a8ccd0b6bc..3dd73dd011 100644 --- a/arch/csr/I/pmpaddr11.yaml +++ b/arch/csr/I/pmpaddr11.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr11 long_name: PMP Address 11 address: 0x3BB +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr12.yaml b/arch/csr/I/pmpaddr12.yaml index 10f1f2efe5..c5ab762ef5 100644 --- a/arch/csr/I/pmpaddr12.yaml +++ b/arch/csr/I/pmpaddr12.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr12 long_name: PMP Address 12 address: 0x3BC +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr13.yaml b/arch/csr/I/pmpaddr13.yaml index 99d40a0936..8bff40b843 100644 --- a/arch/csr/I/pmpaddr13.yaml +++ b/arch/csr/I/pmpaddr13.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr13 long_name: PMP Address 13 address: 0x3BD +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr14.yaml b/arch/csr/I/pmpaddr14.yaml index cda0e1265e..8caa138a42 100644 --- a/arch/csr/I/pmpaddr14.yaml +++ b/arch/csr/I/pmpaddr14.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr14 long_name: PMP Address 14 address: 0x3BE +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr15.yaml b/arch/csr/I/pmpaddr15.yaml index 1cb1232715..183d441a60 100644 --- a/arch/csr/I/pmpaddr15.yaml +++ b/arch/csr/I/pmpaddr15.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr15 long_name: PMP Address 15 address: 0x3BF +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr16.yaml b/arch/csr/I/pmpaddr16.yaml index d766d82fa5..60849d9dbf 100644 --- a/arch/csr/I/pmpaddr16.yaml +++ b/arch/csr/I/pmpaddr16.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr16 long_name: PMP Address 16 address: 0x3C0 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr17.yaml b/arch/csr/I/pmpaddr17.yaml index 94b5b47b47..326781d8a9 100644 --- a/arch/csr/I/pmpaddr17.yaml +++ b/arch/csr/I/pmpaddr17.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr17 long_name: PMP Address 17 address: 0x3C1 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr18.yaml b/arch/csr/I/pmpaddr18.yaml index 1006a07df5..6d725a7e64 100644 --- a/arch/csr/I/pmpaddr18.yaml +++ b/arch/csr/I/pmpaddr18.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr18 long_name: PMP Address 18 address: 0x3C2 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr19.yaml b/arch/csr/I/pmpaddr19.yaml index 7caa8cfbed..a1380146b3 100644 --- a/arch/csr/I/pmpaddr19.yaml +++ b/arch/csr/I/pmpaddr19.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr19 long_name: PMP Address 19 address: 0x3C3 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr2.yaml b/arch/csr/I/pmpaddr2.yaml index 8805ecdafe..37ca3e5c54 100644 --- a/arch/csr/I/pmpaddr2.yaml +++ b/arch/csr/I/pmpaddr2.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr2 long_name: PMP Address 2 address: 0x3B2 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr20.yaml b/arch/csr/I/pmpaddr20.yaml index 2479fbb520..f5bc7eed7f 100644 --- a/arch/csr/I/pmpaddr20.yaml +++ b/arch/csr/I/pmpaddr20.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr20 long_name: PMP Address 20 address: 0x3C4 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr21.yaml b/arch/csr/I/pmpaddr21.yaml index 27f99fec38..66b16eb7c7 100644 --- a/arch/csr/I/pmpaddr21.yaml +++ b/arch/csr/I/pmpaddr21.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr21 long_name: PMP Address 21 address: 0x3C5 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr22.yaml b/arch/csr/I/pmpaddr22.yaml index e738359032..173311eeec 100644 --- a/arch/csr/I/pmpaddr22.yaml +++ b/arch/csr/I/pmpaddr22.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr22 long_name: PMP Address 22 address: 0x3C6 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr23.yaml b/arch/csr/I/pmpaddr23.yaml index b23078e01e..9d9cf29811 100644 --- a/arch/csr/I/pmpaddr23.yaml +++ b/arch/csr/I/pmpaddr23.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr23 long_name: PMP Address 23 address: 0x3C7 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr24.yaml b/arch/csr/I/pmpaddr24.yaml index f07a22f661..987f8e7540 100644 --- a/arch/csr/I/pmpaddr24.yaml +++ b/arch/csr/I/pmpaddr24.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr24 long_name: PMP Address 24 address: 0x3C8 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr25.yaml b/arch/csr/I/pmpaddr25.yaml index c3a791b223..d2e53d83eb 100644 --- a/arch/csr/I/pmpaddr25.yaml +++ b/arch/csr/I/pmpaddr25.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr25 long_name: PMP Address 25 address: 0x3C9 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr26.yaml b/arch/csr/I/pmpaddr26.yaml index ad2d1cb063..9c1a92dd02 100644 --- a/arch/csr/I/pmpaddr26.yaml +++ b/arch/csr/I/pmpaddr26.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr26 long_name: PMP Address 26 address: 0x3CA +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr27.yaml b/arch/csr/I/pmpaddr27.yaml index ef27d3bf9c..f8df97afdc 100644 --- a/arch/csr/I/pmpaddr27.yaml +++ b/arch/csr/I/pmpaddr27.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr27 long_name: PMP Address 27 address: 0x3CB +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr28.yaml b/arch/csr/I/pmpaddr28.yaml index b7f1bf4278..c2ba979815 100644 --- a/arch/csr/I/pmpaddr28.yaml +++ b/arch/csr/I/pmpaddr28.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr28 long_name: PMP Address 28 address: 0x3CC +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr29.yaml b/arch/csr/I/pmpaddr29.yaml index 7a0a971ad6..ebd9902dcb 100644 --- a/arch/csr/I/pmpaddr29.yaml +++ b/arch/csr/I/pmpaddr29.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr29 long_name: PMP Address 29 address: 0x3CD +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr3.yaml b/arch/csr/I/pmpaddr3.yaml index 7d79c0b926..3e96214a57 100644 --- a/arch/csr/I/pmpaddr3.yaml +++ b/arch/csr/I/pmpaddr3.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr3 long_name: PMP Address 3 address: 0x3B3 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr30.yaml b/arch/csr/I/pmpaddr30.yaml index 0b8481e85d..84aa312fcc 100644 --- a/arch/csr/I/pmpaddr30.yaml +++ b/arch/csr/I/pmpaddr30.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr30 long_name: PMP Address 30 address: 0x3CE +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr31.yaml b/arch/csr/I/pmpaddr31.yaml index cb6889d511..74a63dd8a2 100644 --- a/arch/csr/I/pmpaddr31.yaml +++ b/arch/csr/I/pmpaddr31.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr31 long_name: PMP Address 31 address: 0x3CF +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr32.yaml b/arch/csr/I/pmpaddr32.yaml index ef38ca7aab..9cb24997c4 100644 --- a/arch/csr/I/pmpaddr32.yaml +++ b/arch/csr/I/pmpaddr32.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr32 long_name: PMP Address 32 address: 0x3D0 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr33.yaml b/arch/csr/I/pmpaddr33.yaml index 8bac474921..f8d6c238e7 100644 --- a/arch/csr/I/pmpaddr33.yaml +++ b/arch/csr/I/pmpaddr33.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr33 long_name: PMP Address 33 address: 0x3D1 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr34.yaml b/arch/csr/I/pmpaddr34.yaml index 8c06828a18..602d4e1b60 100644 --- a/arch/csr/I/pmpaddr34.yaml +++ b/arch/csr/I/pmpaddr34.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr34 long_name: PMP Address 34 address: 0x3D2 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr35.yaml b/arch/csr/I/pmpaddr35.yaml index 8cc63fde59..1d4e0abba2 100644 --- a/arch/csr/I/pmpaddr35.yaml +++ b/arch/csr/I/pmpaddr35.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr35 long_name: PMP Address 35 address: 0x3D3 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr36.yaml b/arch/csr/I/pmpaddr36.yaml index 4b22831126..9e3e93c6c8 100644 --- a/arch/csr/I/pmpaddr36.yaml +++ b/arch/csr/I/pmpaddr36.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr36 long_name: PMP Address 36 address: 0x3D4 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr37.yaml b/arch/csr/I/pmpaddr37.yaml index 957132029e..611ee8428a 100644 --- a/arch/csr/I/pmpaddr37.yaml +++ b/arch/csr/I/pmpaddr37.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr37 long_name: PMP Address 37 address: 0x3D5 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr38.yaml b/arch/csr/I/pmpaddr38.yaml index 4979a53a5e..c953bccb70 100644 --- a/arch/csr/I/pmpaddr38.yaml +++ b/arch/csr/I/pmpaddr38.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr38 long_name: PMP Address 38 address: 0x3D6 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr39.yaml b/arch/csr/I/pmpaddr39.yaml index 41340b4953..c78b253a14 100644 --- a/arch/csr/I/pmpaddr39.yaml +++ b/arch/csr/I/pmpaddr39.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr39 long_name: PMP Address 39 address: 0x3D7 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr4.yaml b/arch/csr/I/pmpaddr4.yaml index 0a5d45b7ab..25e407f2d5 100644 --- a/arch/csr/I/pmpaddr4.yaml +++ b/arch/csr/I/pmpaddr4.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr4 long_name: PMP Address 4 address: 0x3B4 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr40.yaml b/arch/csr/I/pmpaddr40.yaml index 21b3cf11fe..359f0ce625 100644 --- a/arch/csr/I/pmpaddr40.yaml +++ b/arch/csr/I/pmpaddr40.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr40 long_name: PMP Address 40 address: 0x3D8 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr41.yaml b/arch/csr/I/pmpaddr41.yaml index 6bb1bafc97..cc856c92a5 100644 --- a/arch/csr/I/pmpaddr41.yaml +++ b/arch/csr/I/pmpaddr41.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr41 long_name: PMP Address 41 address: 0x3D9 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr42.yaml b/arch/csr/I/pmpaddr42.yaml index bdab7845a1..561eabf1b1 100644 --- a/arch/csr/I/pmpaddr42.yaml +++ b/arch/csr/I/pmpaddr42.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr42 long_name: PMP Address 42 address: 0x3DA +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr43.yaml b/arch/csr/I/pmpaddr43.yaml index 91b1812bcf..ce6e03f271 100644 --- a/arch/csr/I/pmpaddr43.yaml +++ b/arch/csr/I/pmpaddr43.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr43 long_name: PMP Address 43 address: 0x3DB +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr44.yaml b/arch/csr/I/pmpaddr44.yaml index 5d0cdfca6f..f5a4f2c419 100644 --- a/arch/csr/I/pmpaddr44.yaml +++ b/arch/csr/I/pmpaddr44.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr44 long_name: PMP Address 44 address: 0x3DC +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr45.yaml b/arch/csr/I/pmpaddr45.yaml index 18e02b28cd..5cda5b7e88 100644 --- a/arch/csr/I/pmpaddr45.yaml +++ b/arch/csr/I/pmpaddr45.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr45 long_name: PMP Address 45 address: 0x3DD +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr46.yaml b/arch/csr/I/pmpaddr46.yaml index 950b7b2b89..78d9edd254 100644 --- a/arch/csr/I/pmpaddr46.yaml +++ b/arch/csr/I/pmpaddr46.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr46 long_name: PMP Address 46 address: 0x3DE +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr47.yaml b/arch/csr/I/pmpaddr47.yaml index fb6a5f4222..4251f90446 100644 --- a/arch/csr/I/pmpaddr47.yaml +++ b/arch/csr/I/pmpaddr47.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr47 long_name: PMP Address 47 address: 0x3DF +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr48.yaml b/arch/csr/I/pmpaddr48.yaml index 9eba2608ad..61fa755574 100644 --- a/arch/csr/I/pmpaddr48.yaml +++ b/arch/csr/I/pmpaddr48.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr48 long_name: PMP Address 48 address: 0x3E0 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr49.yaml b/arch/csr/I/pmpaddr49.yaml index 26cb239966..1685f45198 100644 --- a/arch/csr/I/pmpaddr49.yaml +++ b/arch/csr/I/pmpaddr49.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr49 long_name: PMP Address 49 address: 0x3E1 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr5.yaml b/arch/csr/I/pmpaddr5.yaml index 8a73ce45e6..df64c18ba2 100644 --- a/arch/csr/I/pmpaddr5.yaml +++ b/arch/csr/I/pmpaddr5.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr5 long_name: PMP Address 5 address: 0x3B5 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr50.yaml b/arch/csr/I/pmpaddr50.yaml index 69aff1deca..88d4193b8b 100644 --- a/arch/csr/I/pmpaddr50.yaml +++ b/arch/csr/I/pmpaddr50.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr50 long_name: PMP Address 50 address: 0x3E2 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr51.yaml b/arch/csr/I/pmpaddr51.yaml index d5d6464f49..17c496f698 100644 --- a/arch/csr/I/pmpaddr51.yaml +++ b/arch/csr/I/pmpaddr51.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr51 long_name: PMP Address 51 address: 0x3E3 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr52.yaml b/arch/csr/I/pmpaddr52.yaml index 49ace51ac0..51571410ea 100644 --- a/arch/csr/I/pmpaddr52.yaml +++ b/arch/csr/I/pmpaddr52.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr52 long_name: PMP Address 52 address: 0x3E4 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr53.yaml b/arch/csr/I/pmpaddr53.yaml index 222efed3b3..95bf8b6856 100644 --- a/arch/csr/I/pmpaddr53.yaml +++ b/arch/csr/I/pmpaddr53.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr53 long_name: PMP Address 53 address: 0x3E5 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr54.yaml b/arch/csr/I/pmpaddr54.yaml index 6f7e7677d5..4fd59184b8 100644 --- a/arch/csr/I/pmpaddr54.yaml +++ b/arch/csr/I/pmpaddr54.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr54 long_name: PMP Address 54 address: 0x3E6 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr55.yaml b/arch/csr/I/pmpaddr55.yaml index 0f9d5a5063..02d42b187b 100644 --- a/arch/csr/I/pmpaddr55.yaml +++ b/arch/csr/I/pmpaddr55.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr55 long_name: PMP Address 55 address: 0x3E7 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr56.yaml b/arch/csr/I/pmpaddr56.yaml index 4ca1bd3e55..61a7d79c37 100644 --- a/arch/csr/I/pmpaddr56.yaml +++ b/arch/csr/I/pmpaddr56.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr56 long_name: PMP Address 56 address: 0x3E8 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr57.yaml b/arch/csr/I/pmpaddr57.yaml index bde0f738bf..3161a4f60f 100644 --- a/arch/csr/I/pmpaddr57.yaml +++ b/arch/csr/I/pmpaddr57.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr57 long_name: PMP Address 57 address: 0x3E9 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr58.yaml b/arch/csr/I/pmpaddr58.yaml index 6fa1aa32e5..f7809698e9 100644 --- a/arch/csr/I/pmpaddr58.yaml +++ b/arch/csr/I/pmpaddr58.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr58 long_name: PMP Address 58 address: 0x3EA +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr59.yaml b/arch/csr/I/pmpaddr59.yaml index 794787cfd1..1392abc21d 100644 --- a/arch/csr/I/pmpaddr59.yaml +++ b/arch/csr/I/pmpaddr59.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr59 long_name: PMP Address 59 address: 0x3EB +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr6.yaml b/arch/csr/I/pmpaddr6.yaml index 28733415e1..ed81dba357 100644 --- a/arch/csr/I/pmpaddr6.yaml +++ b/arch/csr/I/pmpaddr6.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr6 long_name: PMP Address 6 address: 0x3B6 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr60.yaml b/arch/csr/I/pmpaddr60.yaml index 2932496683..021bd23a7d 100644 --- a/arch/csr/I/pmpaddr60.yaml +++ b/arch/csr/I/pmpaddr60.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr60 long_name: PMP Address 60 address: 0x3EC +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr61.yaml b/arch/csr/I/pmpaddr61.yaml index 9570264235..ca3ed5cabf 100644 --- a/arch/csr/I/pmpaddr61.yaml +++ b/arch/csr/I/pmpaddr61.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr61 long_name: PMP Address 61 address: 0x3ED +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr62.yaml b/arch/csr/I/pmpaddr62.yaml index 0ae068f5d1..961bd3ad06 100644 --- a/arch/csr/I/pmpaddr62.yaml +++ b/arch/csr/I/pmpaddr62.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr62 long_name: PMP Address 62 address: 0x3EE +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr63.yaml b/arch/csr/I/pmpaddr63.yaml index d448de1db1..8837c0af8c 100644 --- a/arch/csr/I/pmpaddr63.yaml +++ b/arch/csr/I/pmpaddr63.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr63 long_name: PMP Address 63 address: 0x3EF +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr7.yaml b/arch/csr/I/pmpaddr7.yaml index 710c597570..c9774eba35 100644 --- a/arch/csr/I/pmpaddr7.yaml +++ b/arch/csr/I/pmpaddr7.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr7 long_name: PMP Address 7 address: 0x3B7 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr8.yaml b/arch/csr/I/pmpaddr8.yaml index e6807b1669..c589f7cfdc 100644 --- a/arch/csr/I/pmpaddr8.yaml +++ b/arch/csr/I/pmpaddr8.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr8 long_name: PMP Address 8 address: 0x3B8 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr9.yaml b/arch/csr/I/pmpaddr9.yaml index 5cefea0afd..0510c298be 100644 --- a/arch/csr/I/pmpaddr9.yaml +++ b/arch/csr/I/pmpaddr9.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpaddr9 long_name: PMP Address 9 address: 0x3B9 +writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpcfg0.yaml b/arch/csr/I/pmpcfg0.yaml index 2630c3ba38..4d94e07d16 100644 --- a/arch/csr/I/pmpcfg0.yaml +++ b/arch/csr/I/pmpcfg0.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpcfg0 long_name: PMP Configuration Register 0 address: 0x3A0 +writeable: true priv_mode: M length: MXLEN description: PMP entry configuration diff --git a/arch/csr/I/pmpcfg1.yaml b/arch/csr/I/pmpcfg1.yaml index 317183e198..1a19e04104 100644 --- a/arch/csr/I/pmpcfg1.yaml +++ b/arch/csr/I/pmpcfg1.yaml @@ -8,6 +8,7 @@ name: pmpcfg1 base: 32 # odd numbered pmpcfg registers do not exist in RV64 long_name: PMP Configuration Register 1 address: 0x3A1 +writeable: true priv_mode: M length: MXLEN description: PMP entry configuration diff --git a/arch/csr/I/pmpcfg10.yaml b/arch/csr/I/pmpcfg10.yaml index b0a9f613ff..0731ecf874 100644 --- a/arch/csr/I/pmpcfg10.yaml +++ b/arch/csr/I/pmpcfg10.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpcfg10 long_name: PMP Configuration Register 10 address: 0x3AA +writeable: true priv_mode: M length: MXLEN description: PMP entry configuration diff --git a/arch/csr/I/pmpcfg11.yaml b/arch/csr/I/pmpcfg11.yaml index c865e0d5e6..422208ef11 100644 --- a/arch/csr/I/pmpcfg11.yaml +++ b/arch/csr/I/pmpcfg11.yaml @@ -8,6 +8,7 @@ name: pmpcfg11 base: 32 # odd numbered pmpcfg registers do not exist in RV64 long_name: PMP Configuration Register 11 address: 0x3AB +writeable: true priv_mode: M length: MXLEN description: PMP entry configuration diff --git a/arch/csr/I/pmpcfg12.yaml b/arch/csr/I/pmpcfg12.yaml index 7943b623ab..407a3573e5 100644 --- a/arch/csr/I/pmpcfg12.yaml +++ b/arch/csr/I/pmpcfg12.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpcfg12 long_name: PMP Configuration Register 12 address: 0x3AC +writeable: true priv_mode: M length: MXLEN description: PMP entry configuration diff --git a/arch/csr/I/pmpcfg13.yaml b/arch/csr/I/pmpcfg13.yaml index 770fa37e19..f000e9258a 100644 --- a/arch/csr/I/pmpcfg13.yaml +++ b/arch/csr/I/pmpcfg13.yaml @@ -8,6 +8,7 @@ name: pmpcfg13 base: 32 # odd numbered pmpcfg registers do not exist in RV64 long_name: PMP Configuration Register 13 address: 0x3AD +writeable: true priv_mode: M length: MXLEN description: PMP entry configuration diff --git a/arch/csr/I/pmpcfg14.yaml b/arch/csr/I/pmpcfg14.yaml index 062513daa8..30242a1c27 100644 --- a/arch/csr/I/pmpcfg14.yaml +++ b/arch/csr/I/pmpcfg14.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpcfg14 long_name: PMP Configuration Register 14 address: 0x3AE +writeable: true priv_mode: M length: MXLEN description: PMP entry configuration diff --git a/arch/csr/I/pmpcfg15.yaml b/arch/csr/I/pmpcfg15.yaml index 942828b3a1..2f8b457738 100644 --- a/arch/csr/I/pmpcfg15.yaml +++ b/arch/csr/I/pmpcfg15.yaml @@ -8,6 +8,7 @@ name: pmpcfg15 base: 32 # odd numbered pmpcfg registers do not exist in RV64 long_name: PMP Configuration Register 15 address: 0x3AF +writeable: true priv_mode: M length: MXLEN description: PMP entry configuration diff --git a/arch/csr/I/pmpcfg2.yaml b/arch/csr/I/pmpcfg2.yaml index 771dceccbe..9256cb542b 100644 --- a/arch/csr/I/pmpcfg2.yaml +++ b/arch/csr/I/pmpcfg2.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpcfg2 long_name: PMP Configuration Register 2 address: 0x3A2 +writeable: true priv_mode: M length: MXLEN description: PMP entry configuration diff --git a/arch/csr/I/pmpcfg3.yaml b/arch/csr/I/pmpcfg3.yaml index 7c2ab8989f..1faafdbdb6 100644 --- a/arch/csr/I/pmpcfg3.yaml +++ b/arch/csr/I/pmpcfg3.yaml @@ -8,6 +8,7 @@ name: pmpcfg3 base: 32 # odd numbered pmpcfg registers do not exist in RV64 long_name: PMP Configuration Register 3 address: 0x3A3 +writeable: true priv_mode: M length: MXLEN description: PMP entry configuration diff --git a/arch/csr/I/pmpcfg4.yaml b/arch/csr/I/pmpcfg4.yaml index 7079c73d6d..c27eccf91c 100644 --- a/arch/csr/I/pmpcfg4.yaml +++ b/arch/csr/I/pmpcfg4.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpcfg4 long_name: PMP Configuration Register 4 address: 0x3A4 +writeable: true priv_mode: M length: MXLEN description: PMP entry configuration diff --git a/arch/csr/I/pmpcfg5.yaml b/arch/csr/I/pmpcfg5.yaml index abd86000c7..4695225a77 100644 --- a/arch/csr/I/pmpcfg5.yaml +++ b/arch/csr/I/pmpcfg5.yaml @@ -8,6 +8,7 @@ name: pmpcfg5 base: 32 # odd numbered pmpcfg registers do not exist in RV64 long_name: PMP Configuration Register 5 address: 0x3A5 +writeable: true priv_mode: M length: MXLEN description: PMP entry configuration diff --git a/arch/csr/I/pmpcfg6.yaml b/arch/csr/I/pmpcfg6.yaml index 74690b12cf..d252e01490 100644 --- a/arch/csr/I/pmpcfg6.yaml +++ b/arch/csr/I/pmpcfg6.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpcfg6 long_name: PMP Configuration Register 6 address: 0x3A6 +writeable: true priv_mode: M length: MXLEN description: PMP entry configuration diff --git a/arch/csr/I/pmpcfg7.yaml b/arch/csr/I/pmpcfg7.yaml index fcfbd78e37..9c7fa84349 100644 --- a/arch/csr/I/pmpcfg7.yaml +++ b/arch/csr/I/pmpcfg7.yaml @@ -8,6 +8,7 @@ name: pmpcfg7 base: 32 # odd numbered pmpcfg registers do not exist in RV64 long_name: PMP Configuration Register 7 address: 0x3A7 +writeable: true priv_mode: M length: MXLEN description: PMP entry configuration diff --git a/arch/csr/I/pmpcfg8.yaml b/arch/csr/I/pmpcfg8.yaml index 79b006f5e9..c35ed68b9b 100644 --- a/arch/csr/I/pmpcfg8.yaml +++ b/arch/csr/I/pmpcfg8.yaml @@ -7,6 +7,7 @@ kind: csr name: pmpcfg8 long_name: PMP Configuration Register 8 address: 0x3A8 +writeable: true priv_mode: M length: MXLEN description: PMP entry configuration diff --git a/arch/csr/I/pmpcfg9.yaml b/arch/csr/I/pmpcfg9.yaml index ec8211763d..902d358ba9 100644 --- a/arch/csr/I/pmpcfg9.yaml +++ b/arch/csr/I/pmpcfg9.yaml @@ -8,6 +8,7 @@ name: pmpcfg9 base: 32 # odd numbered pmpcfg registers do not exist in RV64 long_name: PMP Configuration Register 9 address: 0x3A9 +writeable: true priv_mode: M length: MXLEN description: PMP entry configuration diff --git a/arch/csr/S/scounteren.yaml b/arch/csr/S/scounteren.yaml index 1079620219..7548c61d15 100644 --- a/arch/csr/S/scounteren.yaml +++ b/arch/csr/S/scounteren.yaml @@ -6,6 +6,7 @@ kind: csr name: scounteren long_name: Supervisor Counter Enable address: 0x106 +writeable: true priv_mode: S length: 32 description: | diff --git a/arch/csr/Smrnmi/mncause.yaml b/arch/csr/Smrnmi/mncause.yaml index fa0ad9cd63..d944135118 100644 --- a/arch/csr/Smrnmi/mncause.yaml +++ b/arch/csr/Smrnmi/mncause.yaml @@ -5,6 +5,7 @@ kind: csr name: mncause long_name: Resumable NMI cause address: 0x742 +writeable: true priv_mode: M length: MXLEN definedBy: Smrnmi diff --git a/arch/csr/Smrnmi/mnepc.yaml b/arch/csr/Smrnmi/mnepc.yaml index e249aa441b..5fefa12361 100644 --- a/arch/csr/Smrnmi/mnepc.yaml +++ b/arch/csr/Smrnmi/mnepc.yaml @@ -5,6 +5,7 @@ kind: csr name: mnepc long_name: Machine Exception Program Counter address: 0x741 +writeable: true priv_mode: M length: MXLEN description: | diff --git a/arch/csr/Smrnmi/mnscratch.yaml b/arch/csr/Smrnmi/mnscratch.yaml index b3d89c52b2..1cceddef16 100644 --- a/arch/csr/Smrnmi/mnscratch.yaml +++ b/arch/csr/Smrnmi/mnscratch.yaml @@ -5,9 +5,12 @@ kind: csr name: mnscratch long_name: Machine Scratch Register address: 0x740 +writeable: true priv_mode: M length: MXLEN -description: Scratch register for software use in NMI / double trap. Bits are not interpreted by hardware. +description: + Scratch register for software use in NMI / double trap. Bits are not + interpreted by hardware. definedBy: Smrnmi fields: SCRATCH: diff --git a/arch/csr/Smrnmi/mnstatus.yaml b/arch/csr/Smrnmi/mnstatus.yaml index 1ab64b3967..b79a2ec298 100644 --- a/arch/csr/Smrnmi/mnstatus.yaml +++ b/arch/csr/Smrnmi/mnstatus.yaml @@ -5,11 +5,14 @@ kind: csr name: mnstatus long_name: Machine NMI Status address: 0x744 +writeable: true priv_mode: M # length is MXLEN-bit length: MXLEN -description: The mnstatus register tracks and controls the hart's current NMI operating state. +description: + The mnstatus register tracks and controls the hart's current NMI operating + state. definedBy: Smrnmi fields: MNPP: diff --git a/arch/csr/Zicntr/mcountinhibit.yaml b/arch/csr/Zicntr/mcountinhibit.yaml index 1a06640b7e..591396f95f 100644 --- a/arch/csr/Zicntr/mcountinhibit.yaml +++ b/arch/csr/Zicntr/mcountinhibit.yaml @@ -6,6 +6,7 @@ kind: csr name: mcountinhibit long_name: Machine Counter Inhibit address: 0x320 +writeable: true priv_mode: M length: 32 description: | diff --git a/arch/csr/Zihpm/hpmcounter10.yaml b/arch/csr/Zihpm/hpmcounter10.yaml index 40b6fbdbcc..37d084dd35 100644 --- a/arch/csr/Zihpm/hpmcounter10.yaml +++ b/arch/csr/Zihpm/hpmcounter10.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter10 long_name: User-mode Hardware Performance Counter 7 address: 0xC0A +writeable: false description: | Alias for M-mode CSR `mhpmcounter10`. diff --git a/arch/csr/Zihpm/hpmcounter10h.yaml b/arch/csr/Zihpm/hpmcounter10h.yaml index b903ef0217..623ee258aa 100644 --- a/arch/csr/Zihpm/hpmcounter10h.yaml +++ b/arch/csr/Zihpm/hpmcounter10h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter10h long_name: User-mode Hardware Performance Counter 7, high half address: 0xC8A +writeable: false description: | Alias for M-mode CSR `mhpmcounter10h`. diff --git a/arch/csr/Zihpm/hpmcounter11.yaml b/arch/csr/Zihpm/hpmcounter11.yaml index 1217cc8161..d3242a03ff 100644 --- a/arch/csr/Zihpm/hpmcounter11.yaml +++ b/arch/csr/Zihpm/hpmcounter11.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter11 long_name: User-mode Hardware Performance Counter 8 address: 0xC0B +writeable: false description: | Alias for M-mode CSR `mhpmcounter11`. diff --git a/arch/csr/Zihpm/hpmcounter11h.yaml b/arch/csr/Zihpm/hpmcounter11h.yaml index 24c3187660..40b24be791 100644 --- a/arch/csr/Zihpm/hpmcounter11h.yaml +++ b/arch/csr/Zihpm/hpmcounter11h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter11h long_name: User-mode Hardware Performance Counter 8, high half address: 0xC8B +writeable: false description: | Alias for M-mode CSR `mhpmcounter11h`. diff --git a/arch/csr/Zihpm/hpmcounter12.yaml b/arch/csr/Zihpm/hpmcounter12.yaml index f8f296a581..29c1cc3d60 100644 --- a/arch/csr/Zihpm/hpmcounter12.yaml +++ b/arch/csr/Zihpm/hpmcounter12.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter12 long_name: User-mode Hardware Performance Counter 9 address: 0xC0C +writeable: false description: | Alias for M-mode CSR `mhpmcounter12`. diff --git a/arch/csr/Zihpm/hpmcounter12h.yaml b/arch/csr/Zihpm/hpmcounter12h.yaml index c0c468c19d..ea0b6465ef 100644 --- a/arch/csr/Zihpm/hpmcounter12h.yaml +++ b/arch/csr/Zihpm/hpmcounter12h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter12h long_name: User-mode Hardware Performance Counter 9, high half address: 0xC8C +writeable: false description: | Alias for M-mode CSR `mhpmcounter12h`. diff --git a/arch/csr/Zihpm/hpmcounter13.yaml b/arch/csr/Zihpm/hpmcounter13.yaml index 8713f1e88b..62fb683501 100644 --- a/arch/csr/Zihpm/hpmcounter13.yaml +++ b/arch/csr/Zihpm/hpmcounter13.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter13 long_name: User-mode Hardware Performance Counter 10 address: 0xC0D +writeable: false description: | Alias for M-mode CSR `mhpmcounter13`. diff --git a/arch/csr/Zihpm/hpmcounter13h.yaml b/arch/csr/Zihpm/hpmcounter13h.yaml index cd055f9404..5eafe2b6df 100644 --- a/arch/csr/Zihpm/hpmcounter13h.yaml +++ b/arch/csr/Zihpm/hpmcounter13h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter13h long_name: User-mode Hardware Performance Counter 10, high half address: 0xC8D +writeable: false description: | Alias for M-mode CSR `mhpmcounter13h`. diff --git a/arch/csr/Zihpm/hpmcounter14.yaml b/arch/csr/Zihpm/hpmcounter14.yaml index 47303cbb4e..ebc3e0b49f 100644 --- a/arch/csr/Zihpm/hpmcounter14.yaml +++ b/arch/csr/Zihpm/hpmcounter14.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter14 long_name: User-mode Hardware Performance Counter 11 address: 0xC0E +writeable: false description: | Alias for M-mode CSR `mhpmcounter14`. diff --git a/arch/csr/Zihpm/hpmcounter14h.yaml b/arch/csr/Zihpm/hpmcounter14h.yaml index 1a4290b354..ce24e878da 100644 --- a/arch/csr/Zihpm/hpmcounter14h.yaml +++ b/arch/csr/Zihpm/hpmcounter14h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter14h long_name: User-mode Hardware Performance Counter 11, high half address: 0xC8E +writeable: false description: | Alias for M-mode CSR `mhpmcounter14h`. diff --git a/arch/csr/Zihpm/hpmcounter15.yaml b/arch/csr/Zihpm/hpmcounter15.yaml index a18732b248..13bcd9b8e1 100644 --- a/arch/csr/Zihpm/hpmcounter15.yaml +++ b/arch/csr/Zihpm/hpmcounter15.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter15 long_name: User-mode Hardware Performance Counter 12 address: 0xC0F +writeable: false description: | Alias for M-mode CSR `mhpmcounter15`. diff --git a/arch/csr/Zihpm/hpmcounter15h.yaml b/arch/csr/Zihpm/hpmcounter15h.yaml index 8f7a0fb94e..34220b9a98 100644 --- a/arch/csr/Zihpm/hpmcounter15h.yaml +++ b/arch/csr/Zihpm/hpmcounter15h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter15h long_name: User-mode Hardware Performance Counter 12, high half address: 0xC8F +writeable: false description: | Alias for M-mode CSR `mhpmcounter15h`. diff --git a/arch/csr/Zihpm/hpmcounter16.yaml b/arch/csr/Zihpm/hpmcounter16.yaml index 61e454230c..748b70a0b1 100644 --- a/arch/csr/Zihpm/hpmcounter16.yaml +++ b/arch/csr/Zihpm/hpmcounter16.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter16 long_name: User-mode Hardware Performance Counter 13 address: 0xC10 +writeable: false description: | Alias for M-mode CSR `mhpmcounter16`. diff --git a/arch/csr/Zihpm/hpmcounter16h.yaml b/arch/csr/Zihpm/hpmcounter16h.yaml index b3d05236b9..6f996123f1 100644 --- a/arch/csr/Zihpm/hpmcounter16h.yaml +++ b/arch/csr/Zihpm/hpmcounter16h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter16h long_name: User-mode Hardware Performance Counter 13, high half address: 0xC90 +writeable: false description: | Alias for M-mode CSR `mhpmcounter16h`. diff --git a/arch/csr/Zihpm/hpmcounter17.yaml b/arch/csr/Zihpm/hpmcounter17.yaml index 2d130ca5d2..3cffcea98f 100644 --- a/arch/csr/Zihpm/hpmcounter17.yaml +++ b/arch/csr/Zihpm/hpmcounter17.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter17 long_name: User-mode Hardware Performance Counter 14 address: 0xC11 +writeable: false description: | Alias for M-mode CSR `mhpmcounter17`. diff --git a/arch/csr/Zihpm/hpmcounter17h.yaml b/arch/csr/Zihpm/hpmcounter17h.yaml index 0cd5f864e3..5faf5fb30f 100644 --- a/arch/csr/Zihpm/hpmcounter17h.yaml +++ b/arch/csr/Zihpm/hpmcounter17h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter17h long_name: User-mode Hardware Performance Counter 14, high half address: 0xC91 +writeable: false description: | Alias for M-mode CSR `mhpmcounter17h`. diff --git a/arch/csr/Zihpm/hpmcounter18.yaml b/arch/csr/Zihpm/hpmcounter18.yaml index b115107009..f1928ae231 100644 --- a/arch/csr/Zihpm/hpmcounter18.yaml +++ b/arch/csr/Zihpm/hpmcounter18.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter18 long_name: User-mode Hardware Performance Counter 15 address: 0xC12 +writeable: false description: | Alias for M-mode CSR `mhpmcounter18`. diff --git a/arch/csr/Zihpm/hpmcounter18h.yaml b/arch/csr/Zihpm/hpmcounter18h.yaml index d45aa624b9..ea1721f4c4 100644 --- a/arch/csr/Zihpm/hpmcounter18h.yaml +++ b/arch/csr/Zihpm/hpmcounter18h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter18h long_name: User-mode Hardware Performance Counter 15, high half address: 0xC92 +writeable: false description: | Alias for M-mode CSR `mhpmcounter18h`. diff --git a/arch/csr/Zihpm/hpmcounter19.yaml b/arch/csr/Zihpm/hpmcounter19.yaml index 12a99ea82e..86858b8aa6 100644 --- a/arch/csr/Zihpm/hpmcounter19.yaml +++ b/arch/csr/Zihpm/hpmcounter19.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter19 long_name: User-mode Hardware Performance Counter 16 address: 0xC13 +writeable: false description: | Alias for M-mode CSR `mhpmcounter19`. diff --git a/arch/csr/Zihpm/hpmcounter19h.yaml b/arch/csr/Zihpm/hpmcounter19h.yaml index f5bff3f22d..8a23619f57 100644 --- a/arch/csr/Zihpm/hpmcounter19h.yaml +++ b/arch/csr/Zihpm/hpmcounter19h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter19h long_name: User-mode Hardware Performance Counter 16, high half address: 0xC93 +writeable: false description: | Alias for M-mode CSR `mhpmcounter19h`. diff --git a/arch/csr/Zihpm/hpmcounter20.yaml b/arch/csr/Zihpm/hpmcounter20.yaml index a8a406d7b1..b3b588d6ed 100644 --- a/arch/csr/Zihpm/hpmcounter20.yaml +++ b/arch/csr/Zihpm/hpmcounter20.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter20 long_name: User-mode Hardware Performance Counter 17 address: 0xC14 +writeable: false description: | Alias for M-mode CSR `mhpmcounter20`. diff --git a/arch/csr/Zihpm/hpmcounter20h.yaml b/arch/csr/Zihpm/hpmcounter20h.yaml index 6734e2d79b..db45f652a6 100644 --- a/arch/csr/Zihpm/hpmcounter20h.yaml +++ b/arch/csr/Zihpm/hpmcounter20h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter20h long_name: User-mode Hardware Performance Counter 17, high half address: 0xC94 +writeable: false description: | Alias for M-mode CSR `mhpmcounter20h`. diff --git a/arch/csr/Zihpm/hpmcounter21.yaml b/arch/csr/Zihpm/hpmcounter21.yaml index 3ce7cb84a2..9c29fd1fd2 100644 --- a/arch/csr/Zihpm/hpmcounter21.yaml +++ b/arch/csr/Zihpm/hpmcounter21.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter21 long_name: User-mode Hardware Performance Counter 18 address: 0xC15 +writeable: false description: | Alias for M-mode CSR `mhpmcounter21`. diff --git a/arch/csr/Zihpm/hpmcounter21h.yaml b/arch/csr/Zihpm/hpmcounter21h.yaml index 12012a7bca..bc30fbf87d 100644 --- a/arch/csr/Zihpm/hpmcounter21h.yaml +++ b/arch/csr/Zihpm/hpmcounter21h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter21h long_name: User-mode Hardware Performance Counter 18, high half address: 0xC95 +writeable: false description: | Alias for M-mode CSR `mhpmcounter21h`. diff --git a/arch/csr/Zihpm/hpmcounter22.yaml b/arch/csr/Zihpm/hpmcounter22.yaml index 7943981fdd..e8021fee46 100644 --- a/arch/csr/Zihpm/hpmcounter22.yaml +++ b/arch/csr/Zihpm/hpmcounter22.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter22 long_name: User-mode Hardware Performance Counter 19 address: 0xC16 +writeable: false description: | Alias for M-mode CSR `mhpmcounter22`. diff --git a/arch/csr/Zihpm/hpmcounter22h.yaml b/arch/csr/Zihpm/hpmcounter22h.yaml index 994240044e..1a0757e946 100644 --- a/arch/csr/Zihpm/hpmcounter22h.yaml +++ b/arch/csr/Zihpm/hpmcounter22h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter22h long_name: User-mode Hardware Performance Counter 19, high half address: 0xC96 +writeable: false description: | Alias for M-mode CSR `mhpmcounter22h`. diff --git a/arch/csr/Zihpm/hpmcounter23.yaml b/arch/csr/Zihpm/hpmcounter23.yaml index fc22bd72a5..c6718ff464 100644 --- a/arch/csr/Zihpm/hpmcounter23.yaml +++ b/arch/csr/Zihpm/hpmcounter23.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter23 long_name: User-mode Hardware Performance Counter 20 address: 0xC17 +writeable: false description: | Alias for M-mode CSR `mhpmcounter23`. diff --git a/arch/csr/Zihpm/hpmcounter23h.yaml b/arch/csr/Zihpm/hpmcounter23h.yaml index ecb16e6844..9744f72931 100644 --- a/arch/csr/Zihpm/hpmcounter23h.yaml +++ b/arch/csr/Zihpm/hpmcounter23h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter23h long_name: User-mode Hardware Performance Counter 20, high half address: 0xC97 +writeable: false description: | Alias for M-mode CSR `mhpmcounter23h`. diff --git a/arch/csr/Zihpm/hpmcounter24.yaml b/arch/csr/Zihpm/hpmcounter24.yaml index 4f392aaa5e..414f4e11d5 100644 --- a/arch/csr/Zihpm/hpmcounter24.yaml +++ b/arch/csr/Zihpm/hpmcounter24.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter24 long_name: User-mode Hardware Performance Counter 21 address: 0xC18 +writeable: false description: | Alias for M-mode CSR `mhpmcounter24`. diff --git a/arch/csr/Zihpm/hpmcounter24h.yaml b/arch/csr/Zihpm/hpmcounter24h.yaml index ffe667a456..e3e55a9dc5 100644 --- a/arch/csr/Zihpm/hpmcounter24h.yaml +++ b/arch/csr/Zihpm/hpmcounter24h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter24h long_name: User-mode Hardware Performance Counter 21, high half address: 0xC98 +writeable: false description: | Alias for M-mode CSR `mhpmcounter24h`. diff --git a/arch/csr/Zihpm/hpmcounter25.yaml b/arch/csr/Zihpm/hpmcounter25.yaml index 3bcedc674d..5d37bceab2 100644 --- a/arch/csr/Zihpm/hpmcounter25.yaml +++ b/arch/csr/Zihpm/hpmcounter25.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter25 long_name: User-mode Hardware Performance Counter 22 address: 0xC19 +writeable: false description: | Alias for M-mode CSR `mhpmcounter25`. diff --git a/arch/csr/Zihpm/hpmcounter25h.yaml b/arch/csr/Zihpm/hpmcounter25h.yaml index f4b3286a4f..ec7c5092d1 100644 --- a/arch/csr/Zihpm/hpmcounter25h.yaml +++ b/arch/csr/Zihpm/hpmcounter25h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter25h long_name: User-mode Hardware Performance Counter 22, high half address: 0xC99 +writeable: false description: | Alias for M-mode CSR `mhpmcounter25h`. diff --git a/arch/csr/Zihpm/hpmcounter26.yaml b/arch/csr/Zihpm/hpmcounter26.yaml index 1dee5e0c76..b6248bdb54 100644 --- a/arch/csr/Zihpm/hpmcounter26.yaml +++ b/arch/csr/Zihpm/hpmcounter26.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter26 long_name: User-mode Hardware Performance Counter 23 address: 0xC1A +writeable: false description: | Alias for M-mode CSR `mhpmcounter26`. diff --git a/arch/csr/Zihpm/hpmcounter26h.yaml b/arch/csr/Zihpm/hpmcounter26h.yaml index 995483b4fe..d17fa68f13 100644 --- a/arch/csr/Zihpm/hpmcounter26h.yaml +++ b/arch/csr/Zihpm/hpmcounter26h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter26h long_name: User-mode Hardware Performance Counter 23, high half address: 0xC9A +writeable: false description: | Alias for M-mode CSR `mhpmcounter26h`. diff --git a/arch/csr/Zihpm/hpmcounter27.yaml b/arch/csr/Zihpm/hpmcounter27.yaml index 694b4ee993..874827ee2d 100644 --- a/arch/csr/Zihpm/hpmcounter27.yaml +++ b/arch/csr/Zihpm/hpmcounter27.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter27 long_name: User-mode Hardware Performance Counter 24 address: 0xC1B +writeable: false description: | Alias for M-mode CSR `mhpmcounter27`. diff --git a/arch/csr/Zihpm/hpmcounter27h.yaml b/arch/csr/Zihpm/hpmcounter27h.yaml index 8e17ad1758..912022fec9 100644 --- a/arch/csr/Zihpm/hpmcounter27h.yaml +++ b/arch/csr/Zihpm/hpmcounter27h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter27h long_name: User-mode Hardware Performance Counter 24, high half address: 0xC9B +writeable: false description: | Alias for M-mode CSR `mhpmcounter27h`. diff --git a/arch/csr/Zihpm/hpmcounter28.yaml b/arch/csr/Zihpm/hpmcounter28.yaml index be77b1867d..904ed48f58 100644 --- a/arch/csr/Zihpm/hpmcounter28.yaml +++ b/arch/csr/Zihpm/hpmcounter28.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter28 long_name: User-mode Hardware Performance Counter 25 address: 0xC1C +writeable: false description: | Alias for M-mode CSR `mhpmcounter28`. diff --git a/arch/csr/Zihpm/hpmcounter28h.yaml b/arch/csr/Zihpm/hpmcounter28h.yaml index 9a1e7714f3..a0e2b375ac 100644 --- a/arch/csr/Zihpm/hpmcounter28h.yaml +++ b/arch/csr/Zihpm/hpmcounter28h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter28h long_name: User-mode Hardware Performance Counter 25, high half address: 0xC9C +writeable: false description: | Alias for M-mode CSR `mhpmcounter28h`. diff --git a/arch/csr/Zihpm/hpmcounter29.yaml b/arch/csr/Zihpm/hpmcounter29.yaml index df27482266..d8aa7c1e61 100644 --- a/arch/csr/Zihpm/hpmcounter29.yaml +++ b/arch/csr/Zihpm/hpmcounter29.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter29 long_name: User-mode Hardware Performance Counter 26 address: 0xC1D +writeable: false description: | Alias for M-mode CSR `mhpmcounter29`. diff --git a/arch/csr/Zihpm/hpmcounter29h.yaml b/arch/csr/Zihpm/hpmcounter29h.yaml index e3fd8e6a2f..67b6530152 100644 --- a/arch/csr/Zihpm/hpmcounter29h.yaml +++ b/arch/csr/Zihpm/hpmcounter29h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter29h long_name: User-mode Hardware Performance Counter 26, high half address: 0xC9D +writeable: false description: | Alias for M-mode CSR `mhpmcounter29h`. diff --git a/arch/csr/Zihpm/hpmcounter3.yaml b/arch/csr/Zihpm/hpmcounter3.yaml index 92c2bea3d8..ad81f77396 100644 --- a/arch/csr/Zihpm/hpmcounter3.yaml +++ b/arch/csr/Zihpm/hpmcounter3.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter3 long_name: User-mode Hardware Performance Counter 0 address: 0xC03 +writeable: false description: | Alias for M-mode CSR `mhpmcounter3`. diff --git a/arch/csr/Zihpm/hpmcounter30.yaml b/arch/csr/Zihpm/hpmcounter30.yaml index 7428dbb693..14e0f7c176 100644 --- a/arch/csr/Zihpm/hpmcounter30.yaml +++ b/arch/csr/Zihpm/hpmcounter30.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter30 long_name: User-mode Hardware Performance Counter 27 address: 0xC1E +writeable: false description: | Alias for M-mode CSR `mhpmcounter30`. diff --git a/arch/csr/Zihpm/hpmcounter30h.yaml b/arch/csr/Zihpm/hpmcounter30h.yaml index 08bc8149a7..76e3c0b4a8 100644 --- a/arch/csr/Zihpm/hpmcounter30h.yaml +++ b/arch/csr/Zihpm/hpmcounter30h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter30h long_name: User-mode Hardware Performance Counter 27, high half address: 0xC9E +writeable: false description: | Alias for M-mode CSR `mhpmcounter30h`. diff --git a/arch/csr/Zihpm/hpmcounter31.yaml b/arch/csr/Zihpm/hpmcounter31.yaml index 77f88b79f1..442ab2eaec 100644 --- a/arch/csr/Zihpm/hpmcounter31.yaml +++ b/arch/csr/Zihpm/hpmcounter31.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter31 long_name: User-mode Hardware Performance Counter 28 address: 0xC1F +writeable: false description: | Alias for M-mode CSR `mhpmcounter31`. diff --git a/arch/csr/Zihpm/hpmcounter31h.yaml b/arch/csr/Zihpm/hpmcounter31h.yaml index 02f8f77b23..e581c66448 100644 --- a/arch/csr/Zihpm/hpmcounter31h.yaml +++ b/arch/csr/Zihpm/hpmcounter31h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter31h long_name: User-mode Hardware Performance Counter 28, high half address: 0xC9F +writeable: false description: | Alias for M-mode CSR `mhpmcounter31h`. diff --git a/arch/csr/Zihpm/hpmcounter3h.yaml b/arch/csr/Zihpm/hpmcounter3h.yaml index 2c49c0fe4c..f66931bd2e 100644 --- a/arch/csr/Zihpm/hpmcounter3h.yaml +++ b/arch/csr/Zihpm/hpmcounter3h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter3h long_name: User-mode Hardware Performance Counter 0, high half address: 0xC83 +writeable: false description: | Alias for M-mode CSR `mhpmcounter3h`. diff --git a/arch/csr/Zihpm/hpmcounter4.yaml b/arch/csr/Zihpm/hpmcounter4.yaml index e453b1739b..6d60345a48 100644 --- a/arch/csr/Zihpm/hpmcounter4.yaml +++ b/arch/csr/Zihpm/hpmcounter4.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter4 long_name: User-mode Hardware Performance Counter 1 address: 0xC04 +writeable: false description: | Alias for M-mode CSR `mhpmcounter4`. diff --git a/arch/csr/Zihpm/hpmcounter4h.yaml b/arch/csr/Zihpm/hpmcounter4h.yaml index ac6a575ccc..e922e73588 100644 --- a/arch/csr/Zihpm/hpmcounter4h.yaml +++ b/arch/csr/Zihpm/hpmcounter4h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter4h long_name: User-mode Hardware Performance Counter 1, high half address: 0xC84 +writeable: false description: | Alias for M-mode CSR `mhpmcounter4h`. diff --git a/arch/csr/Zihpm/hpmcounter5.yaml b/arch/csr/Zihpm/hpmcounter5.yaml index 6e9e0c801a..ad06be019d 100644 --- a/arch/csr/Zihpm/hpmcounter5.yaml +++ b/arch/csr/Zihpm/hpmcounter5.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter5 long_name: User-mode Hardware Performance Counter 2 address: 0xC05 +writeable: false description: | Alias for M-mode CSR `mhpmcounter5`. diff --git a/arch/csr/Zihpm/hpmcounter5h.yaml b/arch/csr/Zihpm/hpmcounter5h.yaml index 1529a2f8a2..505805a41f 100644 --- a/arch/csr/Zihpm/hpmcounter5h.yaml +++ b/arch/csr/Zihpm/hpmcounter5h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter5h long_name: User-mode Hardware Performance Counter 2, high half address: 0xC85 +writeable: false description: | Alias for M-mode CSR `mhpmcounter5h`. diff --git a/arch/csr/Zihpm/hpmcounter6.yaml b/arch/csr/Zihpm/hpmcounter6.yaml index 128202fdb3..cf0470bcdc 100644 --- a/arch/csr/Zihpm/hpmcounter6.yaml +++ b/arch/csr/Zihpm/hpmcounter6.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter6 long_name: User-mode Hardware Performance Counter 3 address: 0xC06 +writeable: false description: | Alias for M-mode CSR `mhpmcounter6`. diff --git a/arch/csr/Zihpm/hpmcounter6h.yaml b/arch/csr/Zihpm/hpmcounter6h.yaml index 9995fc0eee..cbd7bd150c 100644 --- a/arch/csr/Zihpm/hpmcounter6h.yaml +++ b/arch/csr/Zihpm/hpmcounter6h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter6h long_name: User-mode Hardware Performance Counter 3, high half address: 0xC86 +writeable: false description: | Alias for M-mode CSR `mhpmcounter6h`. diff --git a/arch/csr/Zihpm/hpmcounter7.yaml b/arch/csr/Zihpm/hpmcounter7.yaml index c471a1df47..98f87d5e70 100644 --- a/arch/csr/Zihpm/hpmcounter7.yaml +++ b/arch/csr/Zihpm/hpmcounter7.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter7 long_name: User-mode Hardware Performance Counter 4 address: 0xC07 +writeable: false description: | Alias for M-mode CSR `mhpmcounter7`. diff --git a/arch/csr/Zihpm/hpmcounter7h.yaml b/arch/csr/Zihpm/hpmcounter7h.yaml index 416f912193..c0607c51cb 100644 --- a/arch/csr/Zihpm/hpmcounter7h.yaml +++ b/arch/csr/Zihpm/hpmcounter7h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter7h long_name: User-mode Hardware Performance Counter 4, high half address: 0xC87 +writeable: false description: | Alias for M-mode CSR `mhpmcounter7h`. diff --git a/arch/csr/Zihpm/hpmcounter8.yaml b/arch/csr/Zihpm/hpmcounter8.yaml index a7c22a495c..f91910331a 100644 --- a/arch/csr/Zihpm/hpmcounter8.yaml +++ b/arch/csr/Zihpm/hpmcounter8.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter8 long_name: User-mode Hardware Performance Counter 5 address: 0xC08 +writeable: false description: | Alias for M-mode CSR `mhpmcounter8`. diff --git a/arch/csr/Zihpm/hpmcounter8h.yaml b/arch/csr/Zihpm/hpmcounter8h.yaml index 11a341b4bb..fda4a1ffc6 100644 --- a/arch/csr/Zihpm/hpmcounter8h.yaml +++ b/arch/csr/Zihpm/hpmcounter8h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter8h long_name: User-mode Hardware Performance Counter 5, high half address: 0xC88 +writeable: false description: | Alias for M-mode CSR `mhpmcounter8h`. diff --git a/arch/csr/Zihpm/hpmcounter9.yaml b/arch/csr/Zihpm/hpmcounter9.yaml index 09770fa7a6..522740b419 100644 --- a/arch/csr/Zihpm/hpmcounter9.yaml +++ b/arch/csr/Zihpm/hpmcounter9.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter9 long_name: User-mode Hardware Performance Counter 6 address: 0xC09 +writeable: false description: | Alias for M-mode CSR `mhpmcounter9`. diff --git a/arch/csr/Zihpm/hpmcounter9h.yaml b/arch/csr/Zihpm/hpmcounter9h.yaml index f3fcfdc25b..c8061f67d1 100644 --- a/arch/csr/Zihpm/hpmcounter9h.yaml +++ b/arch/csr/Zihpm/hpmcounter9h.yaml @@ -7,6 +7,7 @@ kind: csr name: hpmcounter9h long_name: User-mode Hardware Performance Counter 6, high half address: 0xC89 +writeable: false description: | Alias for M-mode CSR `mhpmcounter9h`. diff --git a/arch/csr/Zihpm/mhpmcounter10.yaml b/arch/csr/Zihpm/mhpmcounter10.yaml index 8bbc5e1d9d..2cc562c1aa 100644 --- a/arch/csr/Zihpm/mhpmcounter10.yaml +++ b/arch/csr/Zihpm/mhpmcounter10.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter10 long_name: Machine Hardware Performance Counter 10 address: 0xB0A +writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter10h.yaml b/arch/csr/Zihpm/mhpmcounter10h.yaml index 3bfbeb11e9..fb91bf2cfb 100644 --- a/arch/csr/Zihpm/mhpmcounter10h.yaml +++ b/arch/csr/Zihpm/mhpmcounter10h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter10h long_name: Machine Hardware Performance Counter 10, Upper half address: 0xB8A +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter11.yaml b/arch/csr/Zihpm/mhpmcounter11.yaml index 0501702a38..ff6fe28b99 100644 --- a/arch/csr/Zihpm/mhpmcounter11.yaml +++ b/arch/csr/Zihpm/mhpmcounter11.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter11 long_name: Machine Hardware Performance Counter 11 address: 0xB0B +writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter11h.yaml b/arch/csr/Zihpm/mhpmcounter11h.yaml index 53d1e8d13b..1850848841 100644 --- a/arch/csr/Zihpm/mhpmcounter11h.yaml +++ b/arch/csr/Zihpm/mhpmcounter11h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter11h long_name: Machine Hardware Performance Counter 11, Upper half address: 0xB8B +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter12.yaml b/arch/csr/Zihpm/mhpmcounter12.yaml index f0aceebd18..00498cebf8 100644 --- a/arch/csr/Zihpm/mhpmcounter12.yaml +++ b/arch/csr/Zihpm/mhpmcounter12.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter12 long_name: Machine Hardware Performance Counter 12 address: 0xB0C +writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter12h.yaml b/arch/csr/Zihpm/mhpmcounter12h.yaml index 0b94cfb176..2807ab87ef 100644 --- a/arch/csr/Zihpm/mhpmcounter12h.yaml +++ b/arch/csr/Zihpm/mhpmcounter12h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter12h long_name: Machine Hardware Performance Counter 12, Upper half address: 0xB8C +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter13.yaml b/arch/csr/Zihpm/mhpmcounter13.yaml index 10fc117dfd..a5f9e6bebd 100644 --- a/arch/csr/Zihpm/mhpmcounter13.yaml +++ b/arch/csr/Zihpm/mhpmcounter13.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter13 long_name: Machine Hardware Performance Counter 13 address: 0xB0D +writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter13h.yaml b/arch/csr/Zihpm/mhpmcounter13h.yaml index 754fb34492..c8b566b9c1 100644 --- a/arch/csr/Zihpm/mhpmcounter13h.yaml +++ b/arch/csr/Zihpm/mhpmcounter13h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter13h long_name: Machine Hardware Performance Counter 13, Upper half address: 0xB8D +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter14.yaml b/arch/csr/Zihpm/mhpmcounter14.yaml index 2285c2cca4..2d22b686b4 100644 --- a/arch/csr/Zihpm/mhpmcounter14.yaml +++ b/arch/csr/Zihpm/mhpmcounter14.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter14 long_name: Machine Hardware Performance Counter 14 address: 0xB0E +writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter14h.yaml b/arch/csr/Zihpm/mhpmcounter14h.yaml index 5f32a7c7bf..2e05420c2d 100644 --- a/arch/csr/Zihpm/mhpmcounter14h.yaml +++ b/arch/csr/Zihpm/mhpmcounter14h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter14h long_name: Machine Hardware Performance Counter 14, Upper half address: 0xB8E +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter15.yaml b/arch/csr/Zihpm/mhpmcounter15.yaml index a487e21c5b..fd0a9edc4e 100644 --- a/arch/csr/Zihpm/mhpmcounter15.yaml +++ b/arch/csr/Zihpm/mhpmcounter15.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter15 long_name: Machine Hardware Performance Counter 15 address: 0xB0F +writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter15h.yaml b/arch/csr/Zihpm/mhpmcounter15h.yaml index 21184c4cc9..19215effe6 100644 --- a/arch/csr/Zihpm/mhpmcounter15h.yaml +++ b/arch/csr/Zihpm/mhpmcounter15h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter15h long_name: Machine Hardware Performance Counter 15, Upper half address: 0xB8F +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter16.yaml b/arch/csr/Zihpm/mhpmcounter16.yaml index 9ff6a82635..61c7aa24d6 100644 --- a/arch/csr/Zihpm/mhpmcounter16.yaml +++ b/arch/csr/Zihpm/mhpmcounter16.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter16 long_name: Machine Hardware Performance Counter 16 address: 0xB10 +writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter16h.yaml b/arch/csr/Zihpm/mhpmcounter16h.yaml index d0b7ee88a5..300d827e3a 100644 --- a/arch/csr/Zihpm/mhpmcounter16h.yaml +++ b/arch/csr/Zihpm/mhpmcounter16h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter16h long_name: Machine Hardware Performance Counter 16, Upper half address: 0xB90 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter17.yaml b/arch/csr/Zihpm/mhpmcounter17.yaml index 6c30f92d62..da262b3c3f 100644 --- a/arch/csr/Zihpm/mhpmcounter17.yaml +++ b/arch/csr/Zihpm/mhpmcounter17.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter17 long_name: Machine Hardware Performance Counter 17 address: 0xB11 +writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter17h.yaml b/arch/csr/Zihpm/mhpmcounter17h.yaml index 14d6a52195..807157626e 100644 --- a/arch/csr/Zihpm/mhpmcounter17h.yaml +++ b/arch/csr/Zihpm/mhpmcounter17h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter17h long_name: Machine Hardware Performance Counter 17, Upper half address: 0xB91 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter18.yaml b/arch/csr/Zihpm/mhpmcounter18.yaml index 02b6dcd4fc..b03d08a6f2 100644 --- a/arch/csr/Zihpm/mhpmcounter18.yaml +++ b/arch/csr/Zihpm/mhpmcounter18.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter18 long_name: Machine Hardware Performance Counter 18 address: 0xB12 +writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter18h.yaml b/arch/csr/Zihpm/mhpmcounter18h.yaml index 3fc41ad052..a50a473f2c 100644 --- a/arch/csr/Zihpm/mhpmcounter18h.yaml +++ b/arch/csr/Zihpm/mhpmcounter18h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter18h long_name: Machine Hardware Performance Counter 18, Upper half address: 0xB92 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter19.yaml b/arch/csr/Zihpm/mhpmcounter19.yaml index 0e45c395c8..84d1292f21 100644 --- a/arch/csr/Zihpm/mhpmcounter19.yaml +++ b/arch/csr/Zihpm/mhpmcounter19.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter19 long_name: Machine Hardware Performance Counter 19 address: 0xB13 +writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter19h.yaml b/arch/csr/Zihpm/mhpmcounter19h.yaml index 6483d13301..78e7318c13 100644 --- a/arch/csr/Zihpm/mhpmcounter19h.yaml +++ b/arch/csr/Zihpm/mhpmcounter19h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter19h long_name: Machine Hardware Performance Counter 19, Upper half address: 0xB93 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter20.yaml b/arch/csr/Zihpm/mhpmcounter20.yaml index 6f7d6d1e85..12cc843582 100644 --- a/arch/csr/Zihpm/mhpmcounter20.yaml +++ b/arch/csr/Zihpm/mhpmcounter20.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter20 long_name: Machine Hardware Performance Counter 20 address: 0xB14 +writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter20h.yaml b/arch/csr/Zihpm/mhpmcounter20h.yaml index 73db882e51..a168876173 100644 --- a/arch/csr/Zihpm/mhpmcounter20h.yaml +++ b/arch/csr/Zihpm/mhpmcounter20h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter20h long_name: Machine Hardware Performance Counter 20, Upper half address: 0xB94 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter21.yaml b/arch/csr/Zihpm/mhpmcounter21.yaml index b5cfa7a02d..cfc330fdc0 100644 --- a/arch/csr/Zihpm/mhpmcounter21.yaml +++ b/arch/csr/Zihpm/mhpmcounter21.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter21 long_name: Machine Hardware Performance Counter 21 address: 0xB15 +writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter21h.yaml b/arch/csr/Zihpm/mhpmcounter21h.yaml index f3d81870f8..5138852e39 100644 --- a/arch/csr/Zihpm/mhpmcounter21h.yaml +++ b/arch/csr/Zihpm/mhpmcounter21h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter21h long_name: Machine Hardware Performance Counter 21, Upper half address: 0xB95 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter22.yaml b/arch/csr/Zihpm/mhpmcounter22.yaml index d35d8671dc..881ad56ae9 100644 --- a/arch/csr/Zihpm/mhpmcounter22.yaml +++ b/arch/csr/Zihpm/mhpmcounter22.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter22 long_name: Machine Hardware Performance Counter 22 address: 0xB16 +writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter22h.yaml b/arch/csr/Zihpm/mhpmcounter22h.yaml index 6617b98232..982784d08f 100644 --- a/arch/csr/Zihpm/mhpmcounter22h.yaml +++ b/arch/csr/Zihpm/mhpmcounter22h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter22h long_name: Machine Hardware Performance Counter 22, Upper half address: 0xB96 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter23.yaml b/arch/csr/Zihpm/mhpmcounter23.yaml index 380c27d78d..f1de6bf132 100644 --- a/arch/csr/Zihpm/mhpmcounter23.yaml +++ b/arch/csr/Zihpm/mhpmcounter23.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter23 long_name: Machine Hardware Performance Counter 23 address: 0xB17 +writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter23h.yaml b/arch/csr/Zihpm/mhpmcounter23h.yaml index 36117b668b..099ee3089f 100644 --- a/arch/csr/Zihpm/mhpmcounter23h.yaml +++ b/arch/csr/Zihpm/mhpmcounter23h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter23h long_name: Machine Hardware Performance Counter 23, Upper half address: 0xB97 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter24.yaml b/arch/csr/Zihpm/mhpmcounter24.yaml index 4f66699999..096bc2e7a5 100644 --- a/arch/csr/Zihpm/mhpmcounter24.yaml +++ b/arch/csr/Zihpm/mhpmcounter24.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter24 long_name: Machine Hardware Performance Counter 24 address: 0xB18 +writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter24h.yaml b/arch/csr/Zihpm/mhpmcounter24h.yaml index d7f37ec8b9..3d8fa5546c 100644 --- a/arch/csr/Zihpm/mhpmcounter24h.yaml +++ b/arch/csr/Zihpm/mhpmcounter24h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter24h long_name: Machine Hardware Performance Counter 24, Upper half address: 0xB98 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter25.yaml b/arch/csr/Zihpm/mhpmcounter25.yaml index ca1ea51987..b5503ae861 100644 --- a/arch/csr/Zihpm/mhpmcounter25.yaml +++ b/arch/csr/Zihpm/mhpmcounter25.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter25 long_name: Machine Hardware Performance Counter 25 address: 0xB19 +writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter25h.yaml b/arch/csr/Zihpm/mhpmcounter25h.yaml index a8d2fa086d..cf7300e514 100644 --- a/arch/csr/Zihpm/mhpmcounter25h.yaml +++ b/arch/csr/Zihpm/mhpmcounter25h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter25h long_name: Machine Hardware Performance Counter 25, Upper half address: 0xB99 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter26.yaml b/arch/csr/Zihpm/mhpmcounter26.yaml index 9175778c05..dfcc27e637 100644 --- a/arch/csr/Zihpm/mhpmcounter26.yaml +++ b/arch/csr/Zihpm/mhpmcounter26.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter26 long_name: Machine Hardware Performance Counter 26 address: 0xB1A +writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter26h.yaml b/arch/csr/Zihpm/mhpmcounter26h.yaml index 2074cf504d..2925dddcab 100644 --- a/arch/csr/Zihpm/mhpmcounter26h.yaml +++ b/arch/csr/Zihpm/mhpmcounter26h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter26h long_name: Machine Hardware Performance Counter 26, Upper half address: 0xB9A +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter27.yaml b/arch/csr/Zihpm/mhpmcounter27.yaml index 0cc6b33f94..9db94ead49 100644 --- a/arch/csr/Zihpm/mhpmcounter27.yaml +++ b/arch/csr/Zihpm/mhpmcounter27.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter27 long_name: Machine Hardware Performance Counter 27 address: 0xB1B +writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter27h.yaml b/arch/csr/Zihpm/mhpmcounter27h.yaml index cfd7308bdf..fdcaea9186 100644 --- a/arch/csr/Zihpm/mhpmcounter27h.yaml +++ b/arch/csr/Zihpm/mhpmcounter27h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter27h long_name: Machine Hardware Performance Counter 27, Upper half address: 0xB9B +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter28.yaml b/arch/csr/Zihpm/mhpmcounter28.yaml index f214594745..211c2ba183 100644 --- a/arch/csr/Zihpm/mhpmcounter28.yaml +++ b/arch/csr/Zihpm/mhpmcounter28.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter28 long_name: Machine Hardware Performance Counter 28 address: 0xB1C +writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter28h.yaml b/arch/csr/Zihpm/mhpmcounter28h.yaml index 5b89a5cdcd..e820f81481 100644 --- a/arch/csr/Zihpm/mhpmcounter28h.yaml +++ b/arch/csr/Zihpm/mhpmcounter28h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter28h long_name: Machine Hardware Performance Counter 28, Upper half address: 0xB9C +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter29.yaml b/arch/csr/Zihpm/mhpmcounter29.yaml index 367de7cfec..1f6ffc1617 100644 --- a/arch/csr/Zihpm/mhpmcounter29.yaml +++ b/arch/csr/Zihpm/mhpmcounter29.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter29 long_name: Machine Hardware Performance Counter 29 address: 0xB1D +writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter29h.yaml b/arch/csr/Zihpm/mhpmcounter29h.yaml index 8bbcd8a105..7a8bcd8450 100644 --- a/arch/csr/Zihpm/mhpmcounter29h.yaml +++ b/arch/csr/Zihpm/mhpmcounter29h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter29h long_name: Machine Hardware Performance Counter 29, Upper half address: 0xB9D +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter3.yaml b/arch/csr/Zihpm/mhpmcounter3.yaml index 5c8dd1c6e1..e566163369 100644 --- a/arch/csr/Zihpm/mhpmcounter3.yaml +++ b/arch/csr/Zihpm/mhpmcounter3.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter3 long_name: Machine Hardware Performance Counter 3 address: 0xB03 +writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter30.yaml b/arch/csr/Zihpm/mhpmcounter30.yaml index 441eaab905..229c38d8f3 100644 --- a/arch/csr/Zihpm/mhpmcounter30.yaml +++ b/arch/csr/Zihpm/mhpmcounter30.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter30 long_name: Machine Hardware Performance Counter 30 address: 0xB1E +writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter30h.yaml b/arch/csr/Zihpm/mhpmcounter30h.yaml index b24609c6f1..5efef1f511 100644 --- a/arch/csr/Zihpm/mhpmcounter30h.yaml +++ b/arch/csr/Zihpm/mhpmcounter30h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter30h long_name: Machine Hardware Performance Counter 30, Upper half address: 0xB9E +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter31.yaml b/arch/csr/Zihpm/mhpmcounter31.yaml index 917c8d533b..321b4891a8 100644 --- a/arch/csr/Zihpm/mhpmcounter31.yaml +++ b/arch/csr/Zihpm/mhpmcounter31.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter31 long_name: Machine Hardware Performance Counter 31 address: 0xB1F +writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter31h.yaml b/arch/csr/Zihpm/mhpmcounter31h.yaml index 219f540d9f..f2eeeaae9b 100644 --- a/arch/csr/Zihpm/mhpmcounter31h.yaml +++ b/arch/csr/Zihpm/mhpmcounter31h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter31h long_name: Machine Hardware Performance Counter 31, Upper half address: 0xB9F +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter3h.yaml b/arch/csr/Zihpm/mhpmcounter3h.yaml index b1d00039fa..cae7c2793f 100644 --- a/arch/csr/Zihpm/mhpmcounter3h.yaml +++ b/arch/csr/Zihpm/mhpmcounter3h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter3h long_name: Machine Hardware Performance Counter 3, Upper half address: 0xB83 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter4.yaml b/arch/csr/Zihpm/mhpmcounter4.yaml index 9fc827b0bf..9cbd076432 100644 --- a/arch/csr/Zihpm/mhpmcounter4.yaml +++ b/arch/csr/Zihpm/mhpmcounter4.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter4 long_name: Machine Hardware Performance Counter 4 address: 0xB04 +writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter4h.yaml b/arch/csr/Zihpm/mhpmcounter4h.yaml index b810844ab8..774a29590f 100644 --- a/arch/csr/Zihpm/mhpmcounter4h.yaml +++ b/arch/csr/Zihpm/mhpmcounter4h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter4h long_name: Machine Hardware Performance Counter 4, Upper half address: 0xB84 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter5.yaml b/arch/csr/Zihpm/mhpmcounter5.yaml index b4c035e04f..1a0b723f1c 100644 --- a/arch/csr/Zihpm/mhpmcounter5.yaml +++ b/arch/csr/Zihpm/mhpmcounter5.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter5 long_name: Machine Hardware Performance Counter 5 address: 0xB05 +writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter5h.yaml b/arch/csr/Zihpm/mhpmcounter5h.yaml index f8296cf5a8..d76cd03bec 100644 --- a/arch/csr/Zihpm/mhpmcounter5h.yaml +++ b/arch/csr/Zihpm/mhpmcounter5h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter5h long_name: Machine Hardware Performance Counter 5, Upper half address: 0xB85 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter6.yaml b/arch/csr/Zihpm/mhpmcounter6.yaml index 187e00a28b..1e1afb0bb7 100644 --- a/arch/csr/Zihpm/mhpmcounter6.yaml +++ b/arch/csr/Zihpm/mhpmcounter6.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter6 long_name: Machine Hardware Performance Counter 6 address: 0xB06 +writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter6h.yaml b/arch/csr/Zihpm/mhpmcounter6h.yaml index 3305497de4..726df5825a 100644 --- a/arch/csr/Zihpm/mhpmcounter6h.yaml +++ b/arch/csr/Zihpm/mhpmcounter6h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter6h long_name: Machine Hardware Performance Counter 6, Upper half address: 0xB86 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter7.yaml b/arch/csr/Zihpm/mhpmcounter7.yaml index 7d56e48d5a..3e6bdc9d6d 100644 --- a/arch/csr/Zihpm/mhpmcounter7.yaml +++ b/arch/csr/Zihpm/mhpmcounter7.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter7 long_name: Machine Hardware Performance Counter 7 address: 0xB07 +writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter7h.yaml b/arch/csr/Zihpm/mhpmcounter7h.yaml index 05fc92d3c0..72f940d1f3 100644 --- a/arch/csr/Zihpm/mhpmcounter7h.yaml +++ b/arch/csr/Zihpm/mhpmcounter7h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter7h long_name: Machine Hardware Performance Counter 7, Upper half address: 0xB87 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter8.yaml b/arch/csr/Zihpm/mhpmcounter8.yaml index a29a653bcc..10e30a6349 100644 --- a/arch/csr/Zihpm/mhpmcounter8.yaml +++ b/arch/csr/Zihpm/mhpmcounter8.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter8 long_name: Machine Hardware Performance Counter 8 address: 0xB08 +writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter8h.yaml b/arch/csr/Zihpm/mhpmcounter8h.yaml index 02b097678b..2dc2d52c65 100644 --- a/arch/csr/Zihpm/mhpmcounter8h.yaml +++ b/arch/csr/Zihpm/mhpmcounter8h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter8h long_name: Machine Hardware Performance Counter 8, Upper half address: 0xB88 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter9.yaml b/arch/csr/Zihpm/mhpmcounter9.yaml index 729999ee53..a7f659d0b7 100644 --- a/arch/csr/Zihpm/mhpmcounter9.yaml +++ b/arch/csr/Zihpm/mhpmcounter9.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter9 long_name: Machine Hardware Performance Counter 9 address: 0xB09 +writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter9h.yaml b/arch/csr/Zihpm/mhpmcounter9h.yaml index 277f425300..05b360ffb9 100644 --- a/arch/csr/Zihpm/mhpmcounter9h.yaml +++ b/arch/csr/Zihpm/mhpmcounter9h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmcounter9h long_name: Machine Hardware Performance Counter 9, Upper half address: 0xB89 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent10.yaml b/arch/csr/Zihpm/mhpmevent10.yaml index d5e3511e5d..ecb0134747 100644 --- a/arch/csr/Zihpm/mhpmevent10.yaml +++ b/arch/csr/Zihpm/mhpmevent10.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent10 long_name: Machine Hardware Performance Counter 10 Control address: 0x32A +writeable: true priv_mode: M length: 64 description: | @@ -42,7 +43,9 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: When set, mhpmcounter10 does not increment while the hart in operating in M-mode. + description: + When set, mhpmcounter10 does not increment while the hart in operating + in M-mode. type(): | if (HPM_COUNTER_EN[10]) { return CsrFieldType::RW; @@ -58,7 +61,9 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: When set, mhpmcounter10 does not increment while the hart in operating in (H)S-mode. + description: + When set, mhpmcounter10 does not increment while the hart in operating + in (H)S-mode. type(): | if (HPM_COUNTER_EN[10] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -74,7 +79,9 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: When set, mhpmcounter10 does not increment while the hart in operating in U-mode. + description: + When set, mhpmcounter10 does not increment while the hart in operating + in U-mode. type(): | if (HPM_COUNTER_EN[10] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -90,7 +97,9 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: When set, mhpmcounter10 does not increment while the hart in operating in VS-mode. + description: + When set, mhpmcounter10 does not increment while the hart in operating + in VS-mode. type(): | if ((HPM_COUNTER_EN[10]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -106,7 +115,9 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: When set, mhpmcounter10 does not increment while the hart in operating in VU-mode. + description: + When set, mhpmcounter10 does not increment while the hart in operating + in VU-mode. type(): | if (HPM_COUNTER_EN[10] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent10h.yaml b/arch/csr/Zihpm/mhpmevent10h.yaml index ddc90479cd..7fd5b12239 100644 --- a/arch/csr/Zihpm/mhpmevent10h.yaml +++ b/arch/csr/Zihpm/mhpmevent10h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent10h long_name: Machine Hardware Performance Counter 10 Control, High half address: 0x72A +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent11.yaml b/arch/csr/Zihpm/mhpmevent11.yaml index 25acd4e788..f2f4bb4ef2 100644 --- a/arch/csr/Zihpm/mhpmevent11.yaml +++ b/arch/csr/Zihpm/mhpmevent11.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent11 long_name: Machine Hardware Performance Counter 11 Control address: 0x32B +writeable: true priv_mode: M length: 64 description: | @@ -42,7 +43,9 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: When set, mhpmcounter11 does not increment while the hart in operating in M-mode. + description: + When set, mhpmcounter11 does not increment while the hart in operating + in M-mode. type(): | if (HPM_COUNTER_EN[11]) { return CsrFieldType::RW; @@ -58,7 +61,9 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: When set, mhpmcounter11 does not increment while the hart in operating in (H)S-mode. + description: + When set, mhpmcounter11 does not increment while the hart in operating + in (H)S-mode. type(): | if (HPM_COUNTER_EN[11] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -74,7 +79,9 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: When set, mhpmcounter11 does not increment while the hart in operating in U-mode. + description: + When set, mhpmcounter11 does not increment while the hart in operating + in U-mode. type(): | if (HPM_COUNTER_EN[11] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -90,7 +97,9 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: When set, mhpmcounter11 does not increment while the hart in operating in VS-mode. + description: + When set, mhpmcounter11 does not increment while the hart in operating + in VS-mode. type(): | if ((HPM_COUNTER_EN[11]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -106,7 +115,9 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: When set, mhpmcounter11 does not increment while the hart in operating in VU-mode. + description: + When set, mhpmcounter11 does not increment while the hart in operating + in VU-mode. type(): | if (HPM_COUNTER_EN[11] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent11h.yaml b/arch/csr/Zihpm/mhpmevent11h.yaml index 10a4d69ab0..71ad1eb900 100644 --- a/arch/csr/Zihpm/mhpmevent11h.yaml +++ b/arch/csr/Zihpm/mhpmevent11h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent11h long_name: Machine Hardware Performance Counter 11 Control, High half address: 0x72B +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent12.yaml b/arch/csr/Zihpm/mhpmevent12.yaml index 3277d79920..44ec92451a 100644 --- a/arch/csr/Zihpm/mhpmevent12.yaml +++ b/arch/csr/Zihpm/mhpmevent12.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent12 long_name: Machine Hardware Performance Counter 12 Control address: 0x32C +writeable: true priv_mode: M length: 64 description: | @@ -42,7 +43,9 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: When set, mhpmcounter12 does not increment while the hart in operating in M-mode. + description: + When set, mhpmcounter12 does not increment while the hart in operating + in M-mode. type(): | if (HPM_COUNTER_EN[12]) { return CsrFieldType::RW; @@ -58,7 +61,9 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: When set, mhpmcounter12 does not increment while the hart in operating in (H)S-mode. + description: + When set, mhpmcounter12 does not increment while the hart in operating + in (H)S-mode. type(): | if (HPM_COUNTER_EN[12] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -74,7 +79,9 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: When set, mhpmcounter12 does not increment while the hart in operating in U-mode. + description: + When set, mhpmcounter12 does not increment while the hart in operating + in U-mode. type(): | if (HPM_COUNTER_EN[12] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -90,7 +97,9 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: When set, mhpmcounter12 does not increment while the hart in operating in VS-mode. + description: + When set, mhpmcounter12 does not increment while the hart in operating + in VS-mode. type(): | if ((HPM_COUNTER_EN[12]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -106,7 +115,9 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: When set, mhpmcounter12 does not increment while the hart in operating in VU-mode. + description: + When set, mhpmcounter12 does not increment while the hart in operating + in VU-mode. type(): | if (HPM_COUNTER_EN[12] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent12h.yaml b/arch/csr/Zihpm/mhpmevent12h.yaml index 1561213e0b..e760126e39 100644 --- a/arch/csr/Zihpm/mhpmevent12h.yaml +++ b/arch/csr/Zihpm/mhpmevent12h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent12h long_name: Machine Hardware Performance Counter 12 Control, High half address: 0x72C +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent13.yaml b/arch/csr/Zihpm/mhpmevent13.yaml index 8fe055a95f..089da9360c 100644 --- a/arch/csr/Zihpm/mhpmevent13.yaml +++ b/arch/csr/Zihpm/mhpmevent13.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent13 long_name: Machine Hardware Performance Counter 13 Control address: 0x32D +writeable: true priv_mode: M length: 64 description: | @@ -42,7 +43,9 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: When set, mhpmcounter13 does not increment while the hart in operating in M-mode. + description: + When set, mhpmcounter13 does not increment while the hart in operating + in M-mode. type(): | if (HPM_COUNTER_EN[13]) { return CsrFieldType::RW; @@ -58,7 +61,9 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: When set, mhpmcounter13 does not increment while the hart in operating in (H)S-mode. + description: + When set, mhpmcounter13 does not increment while the hart in operating + in (H)S-mode. type(): | if (HPM_COUNTER_EN[13] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -74,7 +79,9 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: When set, mhpmcounter13 does not increment while the hart in operating in U-mode. + description: + When set, mhpmcounter13 does not increment while the hart in operating + in U-mode. type(): | if (HPM_COUNTER_EN[13] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -90,7 +97,9 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: When set, mhpmcounter13 does not increment while the hart in operating in VS-mode. + description: + When set, mhpmcounter13 does not increment while the hart in operating + in VS-mode. type(): | if ((HPM_COUNTER_EN[13]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -106,7 +115,9 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: When set, mhpmcounter13 does not increment while the hart in operating in VU-mode. + description: + When set, mhpmcounter13 does not increment while the hart in operating + in VU-mode. type(): | if (HPM_COUNTER_EN[13] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent13h.yaml b/arch/csr/Zihpm/mhpmevent13h.yaml index 9d6a4c4f48..b335a5472d 100644 --- a/arch/csr/Zihpm/mhpmevent13h.yaml +++ b/arch/csr/Zihpm/mhpmevent13h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent13h long_name: Machine Hardware Performance Counter 13 Control, High half address: 0x72D +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent14.yaml b/arch/csr/Zihpm/mhpmevent14.yaml index c4f64bcd0e..9480a5315a 100644 --- a/arch/csr/Zihpm/mhpmevent14.yaml +++ b/arch/csr/Zihpm/mhpmevent14.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent14 long_name: Machine Hardware Performance Counter 14 Control address: 0x32E +writeable: true priv_mode: M length: 64 description: | @@ -42,7 +43,9 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: When set, mhpmcounter14 does not increment while the hart in operating in M-mode. + description: + When set, mhpmcounter14 does not increment while the hart in operating + in M-mode. type(): | if (HPM_COUNTER_EN[14]) { return CsrFieldType::RW; @@ -58,7 +61,9 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: When set, mhpmcounter14 does not increment while the hart in operating in (H)S-mode. + description: + When set, mhpmcounter14 does not increment while the hart in operating + in (H)S-mode. type(): | if (HPM_COUNTER_EN[14] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -74,7 +79,9 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: When set, mhpmcounter14 does not increment while the hart in operating in U-mode. + description: + When set, mhpmcounter14 does not increment while the hart in operating + in U-mode. type(): | if (HPM_COUNTER_EN[14] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -90,7 +97,9 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: When set, mhpmcounter14 does not increment while the hart in operating in VS-mode. + description: + When set, mhpmcounter14 does not increment while the hart in operating + in VS-mode. type(): | if ((HPM_COUNTER_EN[14]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -106,7 +115,9 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: When set, mhpmcounter14 does not increment while the hart in operating in VU-mode. + description: + When set, mhpmcounter14 does not increment while the hart in operating + in VU-mode. type(): | if (HPM_COUNTER_EN[14] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent14h.yaml b/arch/csr/Zihpm/mhpmevent14h.yaml index 53e1db9431..3b723c6fa5 100644 --- a/arch/csr/Zihpm/mhpmevent14h.yaml +++ b/arch/csr/Zihpm/mhpmevent14h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent14h long_name: Machine Hardware Performance Counter 14 Control, High half address: 0x72E +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent15.yaml b/arch/csr/Zihpm/mhpmevent15.yaml index bf73956a62..8295fd4b53 100644 --- a/arch/csr/Zihpm/mhpmevent15.yaml +++ b/arch/csr/Zihpm/mhpmevent15.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent15 long_name: Machine Hardware Performance Counter 15 Control address: 0x32F +writeable: true priv_mode: M length: 64 description: | @@ -42,7 +43,9 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: When set, mhpmcounter15 does not increment while the hart in operating in M-mode. + description: + When set, mhpmcounter15 does not increment while the hart in operating + in M-mode. type(): | if (HPM_COUNTER_EN[15]) { return CsrFieldType::RW; @@ -58,7 +61,9 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: When set, mhpmcounter15 does not increment while the hart in operating in (H)S-mode. + description: + When set, mhpmcounter15 does not increment while the hart in operating + in (H)S-mode. type(): | if (HPM_COUNTER_EN[15] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -74,7 +79,9 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: When set, mhpmcounter15 does not increment while the hart in operating in U-mode. + description: + When set, mhpmcounter15 does not increment while the hart in operating + in U-mode. type(): | if (HPM_COUNTER_EN[15] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -90,7 +97,9 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: When set, mhpmcounter15 does not increment while the hart in operating in VS-mode. + description: + When set, mhpmcounter15 does not increment while the hart in operating + in VS-mode. type(): | if ((HPM_COUNTER_EN[15]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -106,7 +115,9 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: When set, mhpmcounter15 does not increment while the hart in operating in VU-mode. + description: + When set, mhpmcounter15 does not increment while the hart in operating + in VU-mode. type(): | if (HPM_COUNTER_EN[15] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent15h.yaml b/arch/csr/Zihpm/mhpmevent15h.yaml index a8298f5a03..d3dd4d15be 100644 --- a/arch/csr/Zihpm/mhpmevent15h.yaml +++ b/arch/csr/Zihpm/mhpmevent15h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent15h long_name: Machine Hardware Performance Counter 15 Control, High half address: 0x72F +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent16.yaml b/arch/csr/Zihpm/mhpmevent16.yaml index 0f39bfbc94..2f5e596db5 100644 --- a/arch/csr/Zihpm/mhpmevent16.yaml +++ b/arch/csr/Zihpm/mhpmevent16.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent16 long_name: Machine Hardware Performance Counter 16 Control address: 0x330 +writeable: true priv_mode: M length: 64 description: | @@ -42,7 +43,9 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: When set, mhpmcounter16 does not increment while the hart in operating in M-mode. + description: + When set, mhpmcounter16 does not increment while the hart in operating + in M-mode. type(): | if (HPM_COUNTER_EN[16]) { return CsrFieldType::RW; @@ -58,7 +61,9 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: When set, mhpmcounter16 does not increment while the hart in operating in (H)S-mode. + description: + When set, mhpmcounter16 does not increment while the hart in operating + in (H)S-mode. type(): | if (HPM_COUNTER_EN[16] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -74,7 +79,9 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: When set, mhpmcounter16 does not increment while the hart in operating in U-mode. + description: + When set, mhpmcounter16 does not increment while the hart in operating + in U-mode. type(): | if (HPM_COUNTER_EN[16] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -90,7 +97,9 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: When set, mhpmcounter16 does not increment while the hart in operating in VS-mode. + description: + When set, mhpmcounter16 does not increment while the hart in operating + in VS-mode. type(): | if ((HPM_COUNTER_EN[16]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -106,7 +115,9 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: When set, mhpmcounter16 does not increment while the hart in operating in VU-mode. + description: + When set, mhpmcounter16 does not increment while the hart in operating + in VU-mode. type(): | if (HPM_COUNTER_EN[16] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent16h.yaml b/arch/csr/Zihpm/mhpmevent16h.yaml index 7257f46c5f..3052f0ef14 100644 --- a/arch/csr/Zihpm/mhpmevent16h.yaml +++ b/arch/csr/Zihpm/mhpmevent16h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent16h long_name: Machine Hardware Performance Counter 16 Control, High half address: 0x730 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent17.yaml b/arch/csr/Zihpm/mhpmevent17.yaml index b442d54fb2..1be002bc2a 100644 --- a/arch/csr/Zihpm/mhpmevent17.yaml +++ b/arch/csr/Zihpm/mhpmevent17.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent17 long_name: Machine Hardware Performance Counter 17 Control address: 0x331 +writeable: true priv_mode: M length: 64 description: | @@ -42,7 +43,9 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: When set, mhpmcounter17 does not increment while the hart in operating in M-mode. + description: + When set, mhpmcounter17 does not increment while the hart in operating + in M-mode. type(): | if (HPM_COUNTER_EN[17]) { return CsrFieldType::RW; @@ -58,7 +61,9 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: When set, mhpmcounter17 does not increment while the hart in operating in (H)S-mode. + description: + When set, mhpmcounter17 does not increment while the hart in operating + in (H)S-mode. type(): | if (HPM_COUNTER_EN[17] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -74,7 +79,9 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: When set, mhpmcounter17 does not increment while the hart in operating in U-mode. + description: + When set, mhpmcounter17 does not increment while the hart in operating + in U-mode. type(): | if (HPM_COUNTER_EN[17] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -90,7 +97,9 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: When set, mhpmcounter17 does not increment while the hart in operating in VS-mode. + description: + When set, mhpmcounter17 does not increment while the hart in operating + in VS-mode. type(): | if ((HPM_COUNTER_EN[17]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -106,7 +115,9 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: When set, mhpmcounter17 does not increment while the hart in operating in VU-mode. + description: + When set, mhpmcounter17 does not increment while the hart in operating + in VU-mode. type(): | if (HPM_COUNTER_EN[17] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent17h.yaml b/arch/csr/Zihpm/mhpmevent17h.yaml index 70e07cc5b5..a47dfea651 100644 --- a/arch/csr/Zihpm/mhpmevent17h.yaml +++ b/arch/csr/Zihpm/mhpmevent17h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent17h long_name: Machine Hardware Performance Counter 17 Control, High half address: 0x731 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent18.yaml b/arch/csr/Zihpm/mhpmevent18.yaml index 95f43e4428..19911621eb 100644 --- a/arch/csr/Zihpm/mhpmevent18.yaml +++ b/arch/csr/Zihpm/mhpmevent18.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent18 long_name: Machine Hardware Performance Counter 18 Control address: 0x332 +writeable: true priv_mode: M length: 64 description: | @@ -42,7 +43,9 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: When set, mhpmcounter18 does not increment while the hart in operating in M-mode. + description: + When set, mhpmcounter18 does not increment while the hart in operating + in M-mode. type(): | if (HPM_COUNTER_EN[18]) { return CsrFieldType::RW; @@ -58,7 +61,9 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: When set, mhpmcounter18 does not increment while the hart in operating in (H)S-mode. + description: + When set, mhpmcounter18 does not increment while the hart in operating + in (H)S-mode. type(): | if (HPM_COUNTER_EN[18] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -74,7 +79,9 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: When set, mhpmcounter18 does not increment while the hart in operating in U-mode. + description: + When set, mhpmcounter18 does not increment while the hart in operating + in U-mode. type(): | if (HPM_COUNTER_EN[18] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -90,7 +97,9 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: When set, mhpmcounter18 does not increment while the hart in operating in VS-mode. + description: + When set, mhpmcounter18 does not increment while the hart in operating + in VS-mode. type(): | if ((HPM_COUNTER_EN[18]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -106,7 +115,9 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: When set, mhpmcounter18 does not increment while the hart in operating in VU-mode. + description: + When set, mhpmcounter18 does not increment while the hart in operating + in VU-mode. type(): | if (HPM_COUNTER_EN[18] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent18h.yaml b/arch/csr/Zihpm/mhpmevent18h.yaml index 4cd34aaafa..23d83aa836 100644 --- a/arch/csr/Zihpm/mhpmevent18h.yaml +++ b/arch/csr/Zihpm/mhpmevent18h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent18h long_name: Machine Hardware Performance Counter 18 Control, High half address: 0x732 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent19.yaml b/arch/csr/Zihpm/mhpmevent19.yaml index 1a1ced791e..9f9d441605 100644 --- a/arch/csr/Zihpm/mhpmevent19.yaml +++ b/arch/csr/Zihpm/mhpmevent19.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent19 long_name: Machine Hardware Performance Counter 19 Control address: 0x333 +writeable: true priv_mode: M length: 64 description: | @@ -42,7 +43,9 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: When set, mhpmcounter19 does not increment while the hart in operating in M-mode. + description: + When set, mhpmcounter19 does not increment while the hart in operating + in M-mode. type(): | if (HPM_COUNTER_EN[19]) { return CsrFieldType::RW; @@ -58,7 +61,9 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: When set, mhpmcounter19 does not increment while the hart in operating in (H)S-mode. + description: + When set, mhpmcounter19 does not increment while the hart in operating + in (H)S-mode. type(): | if (HPM_COUNTER_EN[19] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -74,7 +79,9 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: When set, mhpmcounter19 does not increment while the hart in operating in U-mode. + description: + When set, mhpmcounter19 does not increment while the hart in operating + in U-mode. type(): | if (HPM_COUNTER_EN[19] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -90,7 +97,9 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: When set, mhpmcounter19 does not increment while the hart in operating in VS-mode. + description: + When set, mhpmcounter19 does not increment while the hart in operating + in VS-mode. type(): | if ((HPM_COUNTER_EN[19]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -106,7 +115,9 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: When set, mhpmcounter19 does not increment while the hart in operating in VU-mode. + description: + When set, mhpmcounter19 does not increment while the hart in operating + in VU-mode. type(): | if (HPM_COUNTER_EN[19] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent19h.yaml b/arch/csr/Zihpm/mhpmevent19h.yaml index 2d67a0db2e..4afb967263 100644 --- a/arch/csr/Zihpm/mhpmevent19h.yaml +++ b/arch/csr/Zihpm/mhpmevent19h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent19h long_name: Machine Hardware Performance Counter 19 Control, High half address: 0x733 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent20.yaml b/arch/csr/Zihpm/mhpmevent20.yaml index 5ec2c960b9..b603174dc4 100644 --- a/arch/csr/Zihpm/mhpmevent20.yaml +++ b/arch/csr/Zihpm/mhpmevent20.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent20 long_name: Machine Hardware Performance Counter 20 Control address: 0x334 +writeable: true priv_mode: M length: 64 description: | @@ -42,7 +43,9 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: When set, mhpmcounter20 does not increment while the hart in operating in M-mode. + description: + When set, mhpmcounter20 does not increment while the hart in operating + in M-mode. type(): | if (HPM_COUNTER_EN[20]) { return CsrFieldType::RW; @@ -58,7 +61,9 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: When set, mhpmcounter20 does not increment while the hart in operating in (H)S-mode. + description: + When set, mhpmcounter20 does not increment while the hart in operating + in (H)S-mode. type(): | if (HPM_COUNTER_EN[20] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -74,7 +79,9 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: When set, mhpmcounter20 does not increment while the hart in operating in U-mode. + description: + When set, mhpmcounter20 does not increment while the hart in operating + in U-mode. type(): | if (HPM_COUNTER_EN[20] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -90,7 +97,9 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: When set, mhpmcounter20 does not increment while the hart in operating in VS-mode. + description: + When set, mhpmcounter20 does not increment while the hart in operating + in VS-mode. type(): | if ((HPM_COUNTER_EN[20]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -106,7 +115,9 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: When set, mhpmcounter20 does not increment while the hart in operating in VU-mode. + description: + When set, mhpmcounter20 does not increment while the hart in operating + in VU-mode. type(): | if (HPM_COUNTER_EN[20] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent20h.yaml b/arch/csr/Zihpm/mhpmevent20h.yaml index 32f9027ac7..eb60d57b1d 100644 --- a/arch/csr/Zihpm/mhpmevent20h.yaml +++ b/arch/csr/Zihpm/mhpmevent20h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent20h long_name: Machine Hardware Performance Counter 20 Control, High half address: 0x734 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent21.yaml b/arch/csr/Zihpm/mhpmevent21.yaml index 166aa50f66..064ad0a591 100644 --- a/arch/csr/Zihpm/mhpmevent21.yaml +++ b/arch/csr/Zihpm/mhpmevent21.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent21 long_name: Machine Hardware Performance Counter 21 Control address: 0x335 +writeable: true priv_mode: M length: 64 description: | @@ -42,7 +43,9 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: When set, mhpmcounter21 does not increment while the hart in operating in M-mode. + description: + When set, mhpmcounter21 does not increment while the hart in operating + in M-mode. type(): | if (HPM_COUNTER_EN[21]) { return CsrFieldType::RW; @@ -58,7 +61,9 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: When set, mhpmcounter21 does not increment while the hart in operating in (H)S-mode. + description: + When set, mhpmcounter21 does not increment while the hart in operating + in (H)S-mode. type(): | if (HPM_COUNTER_EN[21] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -74,7 +79,9 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: When set, mhpmcounter21 does not increment while the hart in operating in U-mode. + description: + When set, mhpmcounter21 does not increment while the hart in operating + in U-mode. type(): | if (HPM_COUNTER_EN[21] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -90,7 +97,9 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: When set, mhpmcounter21 does not increment while the hart in operating in VS-mode. + description: + When set, mhpmcounter21 does not increment while the hart in operating + in VS-mode. type(): | if ((HPM_COUNTER_EN[21]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -106,7 +115,9 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: When set, mhpmcounter21 does not increment while the hart in operating in VU-mode. + description: + When set, mhpmcounter21 does not increment while the hart in operating + in VU-mode. type(): | if (HPM_COUNTER_EN[21] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent21h.yaml b/arch/csr/Zihpm/mhpmevent21h.yaml index f5fa3dfe28..a44c4f4f53 100644 --- a/arch/csr/Zihpm/mhpmevent21h.yaml +++ b/arch/csr/Zihpm/mhpmevent21h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent21h long_name: Machine Hardware Performance Counter 21 Control, High half address: 0x735 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent22.yaml b/arch/csr/Zihpm/mhpmevent22.yaml index 21f1a3c4bb..b8697f2433 100644 --- a/arch/csr/Zihpm/mhpmevent22.yaml +++ b/arch/csr/Zihpm/mhpmevent22.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent22 long_name: Machine Hardware Performance Counter 22 Control address: 0x336 +writeable: true priv_mode: M length: 64 description: | @@ -42,7 +43,9 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: When set, mhpmcounter22 does not increment while the hart in operating in M-mode. + description: + When set, mhpmcounter22 does not increment while the hart in operating + in M-mode. type(): | if (HPM_COUNTER_EN[22]) { return CsrFieldType::RW; @@ -58,7 +61,9 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: When set, mhpmcounter22 does not increment while the hart in operating in (H)S-mode. + description: + When set, mhpmcounter22 does not increment while the hart in operating + in (H)S-mode. type(): | if (HPM_COUNTER_EN[22] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -74,7 +79,9 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: When set, mhpmcounter22 does not increment while the hart in operating in U-mode. + description: + When set, mhpmcounter22 does not increment while the hart in operating + in U-mode. type(): | if (HPM_COUNTER_EN[22] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -90,7 +97,9 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: When set, mhpmcounter22 does not increment while the hart in operating in VS-mode. + description: + When set, mhpmcounter22 does not increment while the hart in operating + in VS-mode. type(): | if ((HPM_COUNTER_EN[22]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -106,7 +115,9 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: When set, mhpmcounter22 does not increment while the hart in operating in VU-mode. + description: + When set, mhpmcounter22 does not increment while the hart in operating + in VU-mode. type(): | if (HPM_COUNTER_EN[22] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent22h.yaml b/arch/csr/Zihpm/mhpmevent22h.yaml index a8adbe8a1e..317a5516b5 100644 --- a/arch/csr/Zihpm/mhpmevent22h.yaml +++ b/arch/csr/Zihpm/mhpmevent22h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent22h long_name: Machine Hardware Performance Counter 22 Control, High half address: 0x736 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent23.yaml b/arch/csr/Zihpm/mhpmevent23.yaml index 4e6b623c04..fed6373eb6 100644 --- a/arch/csr/Zihpm/mhpmevent23.yaml +++ b/arch/csr/Zihpm/mhpmevent23.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent23 long_name: Machine Hardware Performance Counter 23 Control address: 0x337 +writeable: true priv_mode: M length: 64 description: | @@ -42,7 +43,9 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: When set, mhpmcounter23 does not increment while the hart in operating in M-mode. + description: + When set, mhpmcounter23 does not increment while the hart in operating + in M-mode. type(): | if (HPM_COUNTER_EN[23]) { return CsrFieldType::RW; @@ -58,7 +61,9 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: When set, mhpmcounter23 does not increment while the hart in operating in (H)S-mode. + description: + When set, mhpmcounter23 does not increment while the hart in operating + in (H)S-mode. type(): | if (HPM_COUNTER_EN[23] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -74,7 +79,9 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: When set, mhpmcounter23 does not increment while the hart in operating in U-mode. + description: + When set, mhpmcounter23 does not increment while the hart in operating + in U-mode. type(): | if (HPM_COUNTER_EN[23] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -90,7 +97,9 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: When set, mhpmcounter23 does not increment while the hart in operating in VS-mode. + description: + When set, mhpmcounter23 does not increment while the hart in operating + in VS-mode. type(): | if ((HPM_COUNTER_EN[23]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -106,7 +115,9 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: When set, mhpmcounter23 does not increment while the hart in operating in VU-mode. + description: + When set, mhpmcounter23 does not increment while the hart in operating + in VU-mode. type(): | if (HPM_COUNTER_EN[23] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent23h.yaml b/arch/csr/Zihpm/mhpmevent23h.yaml index ba1566e3d1..2b04776472 100644 --- a/arch/csr/Zihpm/mhpmevent23h.yaml +++ b/arch/csr/Zihpm/mhpmevent23h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent23h long_name: Machine Hardware Performance Counter 23 Control, High half address: 0x737 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent24.yaml b/arch/csr/Zihpm/mhpmevent24.yaml index 89cd20f66e..f9ad03c43e 100644 --- a/arch/csr/Zihpm/mhpmevent24.yaml +++ b/arch/csr/Zihpm/mhpmevent24.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent24 long_name: Machine Hardware Performance Counter 24 Control address: 0x338 +writeable: true priv_mode: M length: 64 description: | @@ -42,7 +43,9 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: When set, mhpmcounter24 does not increment while the hart in operating in M-mode. + description: + When set, mhpmcounter24 does not increment while the hart in operating + in M-mode. type(): | if (HPM_COUNTER_EN[24]) { return CsrFieldType::RW; @@ -58,7 +61,9 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: When set, mhpmcounter24 does not increment while the hart in operating in (H)S-mode. + description: + When set, mhpmcounter24 does not increment while the hart in operating + in (H)S-mode. type(): | if (HPM_COUNTER_EN[24] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -74,7 +79,9 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: When set, mhpmcounter24 does not increment while the hart in operating in U-mode. + description: + When set, mhpmcounter24 does not increment while the hart in operating + in U-mode. type(): | if (HPM_COUNTER_EN[24] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -90,7 +97,9 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: When set, mhpmcounter24 does not increment while the hart in operating in VS-mode. + description: + When set, mhpmcounter24 does not increment while the hart in operating + in VS-mode. type(): | if ((HPM_COUNTER_EN[24]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -106,7 +115,9 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: When set, mhpmcounter24 does not increment while the hart in operating in VU-mode. + description: + When set, mhpmcounter24 does not increment while the hart in operating + in VU-mode. type(): | if (HPM_COUNTER_EN[24] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent24h.yaml b/arch/csr/Zihpm/mhpmevent24h.yaml index 69adfe7536..540580e16a 100644 --- a/arch/csr/Zihpm/mhpmevent24h.yaml +++ b/arch/csr/Zihpm/mhpmevent24h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent24h long_name: Machine Hardware Performance Counter 24 Control, High half address: 0x738 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent25.yaml b/arch/csr/Zihpm/mhpmevent25.yaml index 4b291b985f..6b743c3a8e 100644 --- a/arch/csr/Zihpm/mhpmevent25.yaml +++ b/arch/csr/Zihpm/mhpmevent25.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent25 long_name: Machine Hardware Performance Counter 25 Control address: 0x339 +writeable: true priv_mode: M length: 64 description: | @@ -42,7 +43,9 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: When set, mhpmcounter25 does not increment while the hart in operating in M-mode. + description: + When set, mhpmcounter25 does not increment while the hart in operating + in M-mode. type(): | if (HPM_COUNTER_EN[25]) { return CsrFieldType::RW; @@ -58,7 +61,9 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: When set, mhpmcounter25 does not increment while the hart in operating in (H)S-mode. + description: + When set, mhpmcounter25 does not increment while the hart in operating + in (H)S-mode. type(): | if (HPM_COUNTER_EN[25] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -74,7 +79,9 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: When set, mhpmcounter25 does not increment while the hart in operating in U-mode. + description: + When set, mhpmcounter25 does not increment while the hart in operating + in U-mode. type(): | if (HPM_COUNTER_EN[25] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -90,7 +97,9 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: When set, mhpmcounter25 does not increment while the hart in operating in VS-mode. + description: + When set, mhpmcounter25 does not increment while the hart in operating + in VS-mode. type(): | if ((HPM_COUNTER_EN[25]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -106,7 +115,9 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: When set, mhpmcounter25 does not increment while the hart in operating in VU-mode. + description: + When set, mhpmcounter25 does not increment while the hart in operating + in VU-mode. type(): | if (HPM_COUNTER_EN[25] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent25h.yaml b/arch/csr/Zihpm/mhpmevent25h.yaml index 411ba06a52..c8e75371a9 100644 --- a/arch/csr/Zihpm/mhpmevent25h.yaml +++ b/arch/csr/Zihpm/mhpmevent25h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent25h long_name: Machine Hardware Performance Counter 25 Control, High half address: 0x739 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent26.yaml b/arch/csr/Zihpm/mhpmevent26.yaml index 0ca5a2c6fe..2ef1de995d 100644 --- a/arch/csr/Zihpm/mhpmevent26.yaml +++ b/arch/csr/Zihpm/mhpmevent26.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent26 long_name: Machine Hardware Performance Counter 26 Control address: 0x33A +writeable: true priv_mode: M length: 64 description: | @@ -42,7 +43,9 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: When set, mhpmcounter26 does not increment while the hart in operating in M-mode. + description: + When set, mhpmcounter26 does not increment while the hart in operating + in M-mode. type(): | if (HPM_COUNTER_EN[26]) { return CsrFieldType::RW; @@ -58,7 +61,9 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: When set, mhpmcounter26 does not increment while the hart in operating in (H)S-mode. + description: + When set, mhpmcounter26 does not increment while the hart in operating + in (H)S-mode. type(): | if (HPM_COUNTER_EN[26] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -74,7 +79,9 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: When set, mhpmcounter26 does not increment while the hart in operating in U-mode. + description: + When set, mhpmcounter26 does not increment while the hart in operating + in U-mode. type(): | if (HPM_COUNTER_EN[26] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -90,7 +97,9 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: When set, mhpmcounter26 does not increment while the hart in operating in VS-mode. + description: + When set, mhpmcounter26 does not increment while the hart in operating + in VS-mode. type(): | if ((HPM_COUNTER_EN[26]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -106,7 +115,9 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: When set, mhpmcounter26 does not increment while the hart in operating in VU-mode. + description: + When set, mhpmcounter26 does not increment while the hart in operating + in VU-mode. type(): | if (HPM_COUNTER_EN[26] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent26h.yaml b/arch/csr/Zihpm/mhpmevent26h.yaml index 276bf866fa..473246d7d6 100644 --- a/arch/csr/Zihpm/mhpmevent26h.yaml +++ b/arch/csr/Zihpm/mhpmevent26h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent26h long_name: Machine Hardware Performance Counter 26 Control, High half address: 0x73A +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent27.yaml b/arch/csr/Zihpm/mhpmevent27.yaml index b8e7ba1d1b..17cf19420b 100644 --- a/arch/csr/Zihpm/mhpmevent27.yaml +++ b/arch/csr/Zihpm/mhpmevent27.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent27 long_name: Machine Hardware Performance Counter 27 Control address: 0x33B +writeable: true priv_mode: M length: 64 description: | @@ -42,7 +43,9 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: When set, mhpmcounter27 does not increment while the hart in operating in M-mode. + description: + When set, mhpmcounter27 does not increment while the hart in operating + in M-mode. type(): | if (HPM_COUNTER_EN[27]) { return CsrFieldType::RW; @@ -58,7 +61,9 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: When set, mhpmcounter27 does not increment while the hart in operating in (H)S-mode. + description: + When set, mhpmcounter27 does not increment while the hart in operating + in (H)S-mode. type(): | if (HPM_COUNTER_EN[27] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -74,7 +79,9 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: When set, mhpmcounter27 does not increment while the hart in operating in U-mode. + description: + When set, mhpmcounter27 does not increment while the hart in operating + in U-mode. type(): | if (HPM_COUNTER_EN[27] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -90,7 +97,9 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: When set, mhpmcounter27 does not increment while the hart in operating in VS-mode. + description: + When set, mhpmcounter27 does not increment while the hart in operating + in VS-mode. type(): | if ((HPM_COUNTER_EN[27]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -106,7 +115,9 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: When set, mhpmcounter27 does not increment while the hart in operating in VU-mode. + description: + When set, mhpmcounter27 does not increment while the hart in operating + in VU-mode. type(): | if (HPM_COUNTER_EN[27] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent27h.yaml b/arch/csr/Zihpm/mhpmevent27h.yaml index f5136e8ec1..a2b4fe543f 100644 --- a/arch/csr/Zihpm/mhpmevent27h.yaml +++ b/arch/csr/Zihpm/mhpmevent27h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent27h long_name: Machine Hardware Performance Counter 27 Control, High half address: 0x73B +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent28.yaml b/arch/csr/Zihpm/mhpmevent28.yaml index f9485190e1..dbd7c64764 100644 --- a/arch/csr/Zihpm/mhpmevent28.yaml +++ b/arch/csr/Zihpm/mhpmevent28.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent28 long_name: Machine Hardware Performance Counter 28 Control address: 0x33C +writeable: true priv_mode: M length: 64 description: | @@ -42,7 +43,9 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: When set, mhpmcounter28 does not increment while the hart in operating in M-mode. + description: + When set, mhpmcounter28 does not increment while the hart in operating + in M-mode. type(): | if (HPM_COUNTER_EN[28]) { return CsrFieldType::RW; @@ -58,7 +61,9 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: When set, mhpmcounter28 does not increment while the hart in operating in (H)S-mode. + description: + When set, mhpmcounter28 does not increment while the hart in operating + in (H)S-mode. type(): | if (HPM_COUNTER_EN[28] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -74,7 +79,9 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: When set, mhpmcounter28 does not increment while the hart in operating in U-mode. + description: + When set, mhpmcounter28 does not increment while the hart in operating + in U-mode. type(): | if (HPM_COUNTER_EN[28] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -90,7 +97,9 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: When set, mhpmcounter28 does not increment while the hart in operating in VS-mode. + description: + When set, mhpmcounter28 does not increment while the hart in operating + in VS-mode. type(): | if ((HPM_COUNTER_EN[28]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -106,7 +115,9 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: When set, mhpmcounter28 does not increment while the hart in operating in VU-mode. + description: + When set, mhpmcounter28 does not increment while the hart in operating + in VU-mode. type(): | if (HPM_COUNTER_EN[28] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent28h.yaml b/arch/csr/Zihpm/mhpmevent28h.yaml index 6f5b083ed0..fd6c54518f 100644 --- a/arch/csr/Zihpm/mhpmevent28h.yaml +++ b/arch/csr/Zihpm/mhpmevent28h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent28h long_name: Machine Hardware Performance Counter 28 Control, High half address: 0x73C +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent29.yaml b/arch/csr/Zihpm/mhpmevent29.yaml index 007d149878..4dc6b80504 100644 --- a/arch/csr/Zihpm/mhpmevent29.yaml +++ b/arch/csr/Zihpm/mhpmevent29.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent29 long_name: Machine Hardware Performance Counter 29 Control address: 0x33D +writeable: true priv_mode: M length: 64 description: | @@ -42,7 +43,9 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: When set, mhpmcounter29 does not increment while the hart in operating in M-mode. + description: + When set, mhpmcounter29 does not increment while the hart in operating + in M-mode. type(): | if (HPM_COUNTER_EN[29]) { return CsrFieldType::RW; @@ -58,7 +61,9 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: When set, mhpmcounter29 does not increment while the hart in operating in (H)S-mode. + description: + When set, mhpmcounter29 does not increment while the hart in operating + in (H)S-mode. type(): | if (HPM_COUNTER_EN[29] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -74,7 +79,9 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: When set, mhpmcounter29 does not increment while the hart in operating in U-mode. + description: + When set, mhpmcounter29 does not increment while the hart in operating + in U-mode. type(): | if (HPM_COUNTER_EN[29] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -90,7 +97,9 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: When set, mhpmcounter29 does not increment while the hart in operating in VS-mode. + description: + When set, mhpmcounter29 does not increment while the hart in operating + in VS-mode. type(): | if ((HPM_COUNTER_EN[29]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -106,7 +115,9 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: When set, mhpmcounter29 does not increment while the hart in operating in VU-mode. + description: + When set, mhpmcounter29 does not increment while the hart in operating + in VU-mode. type(): | if (HPM_COUNTER_EN[29] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent29h.yaml b/arch/csr/Zihpm/mhpmevent29h.yaml index 11c6f67d7f..7b122a09b8 100644 --- a/arch/csr/Zihpm/mhpmevent29h.yaml +++ b/arch/csr/Zihpm/mhpmevent29h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent29h long_name: Machine Hardware Performance Counter 29 Control, High half address: 0x73D +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent3.yaml b/arch/csr/Zihpm/mhpmevent3.yaml index bf6237f551..4ce4fd0c75 100644 --- a/arch/csr/Zihpm/mhpmevent3.yaml +++ b/arch/csr/Zihpm/mhpmevent3.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent3 long_name: Machine Hardware Performance Counter 3 Control address: 0x323 +writeable: true priv_mode: M length: 64 description: | @@ -42,7 +43,9 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: When set, mhpmcounter3 does not increment while the hart in operating in M-mode. + description: + When set, mhpmcounter3 does not increment while the hart in operating + in M-mode. type(): | if (HPM_COUNTER_EN[3]) { return CsrFieldType::RW; @@ -58,7 +61,9 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: When set, mhpmcounter3 does not increment while the hart in operating in (H)S-mode. + description: + When set, mhpmcounter3 does not increment while the hart in operating + in (H)S-mode. type(): | if (HPM_COUNTER_EN[3] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -74,7 +79,9 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: When set, mhpmcounter3 does not increment while the hart in operating in U-mode. + description: + When set, mhpmcounter3 does not increment while the hart in operating + in U-mode. type(): | if (HPM_COUNTER_EN[3] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -90,7 +97,9 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: When set, mhpmcounter3 does not increment while the hart in operating in VS-mode. + description: + When set, mhpmcounter3 does not increment while the hart in operating + in VS-mode. type(): | if ((HPM_COUNTER_EN[3]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -106,7 +115,9 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: When set, mhpmcounter3 does not increment while the hart in operating in VU-mode. + description: + When set, mhpmcounter3 does not increment while the hart in operating + in VU-mode. type(): | if (HPM_COUNTER_EN[3] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent30.yaml b/arch/csr/Zihpm/mhpmevent30.yaml index 6d59261234..f1f3ed0824 100644 --- a/arch/csr/Zihpm/mhpmevent30.yaml +++ b/arch/csr/Zihpm/mhpmevent30.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent30 long_name: Machine Hardware Performance Counter 30 Control address: 0x33E +writeable: true priv_mode: M length: 64 description: | @@ -42,7 +43,9 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: When set, mhpmcounter30 does not increment while the hart in operating in M-mode. + description: + When set, mhpmcounter30 does not increment while the hart in operating + in M-mode. type(): | if (HPM_COUNTER_EN[30]) { return CsrFieldType::RW; @@ -58,7 +61,9 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: When set, mhpmcounter30 does not increment while the hart in operating in (H)S-mode. + description: + When set, mhpmcounter30 does not increment while the hart in operating + in (H)S-mode. type(): | if (HPM_COUNTER_EN[30] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -74,7 +79,9 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: When set, mhpmcounter30 does not increment while the hart in operating in U-mode. + description: + When set, mhpmcounter30 does not increment while the hart in operating + in U-mode. type(): | if (HPM_COUNTER_EN[30] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -90,7 +97,9 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: When set, mhpmcounter30 does not increment while the hart in operating in VS-mode. + description: + When set, mhpmcounter30 does not increment while the hart in operating + in VS-mode. type(): | if ((HPM_COUNTER_EN[30]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -106,7 +115,9 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: When set, mhpmcounter30 does not increment while the hart in operating in VU-mode. + description: + When set, mhpmcounter30 does not increment while the hart in operating + in VU-mode. type(): | if (HPM_COUNTER_EN[30] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent30h.yaml b/arch/csr/Zihpm/mhpmevent30h.yaml index 27b55926c8..8b277b4a47 100644 --- a/arch/csr/Zihpm/mhpmevent30h.yaml +++ b/arch/csr/Zihpm/mhpmevent30h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent30h long_name: Machine Hardware Performance Counter 30 Control, High half address: 0x73E +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent31.yaml b/arch/csr/Zihpm/mhpmevent31.yaml index 37b8593076..e0ac7f2dc3 100644 --- a/arch/csr/Zihpm/mhpmevent31.yaml +++ b/arch/csr/Zihpm/mhpmevent31.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent31 long_name: Machine Hardware Performance Counter 31 Control address: 0x33F +writeable: true priv_mode: M length: 64 description: | @@ -42,7 +43,9 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: When set, mhpmcounter31 does not increment while the hart in operating in M-mode. + description: + When set, mhpmcounter31 does not increment while the hart in operating + in M-mode. type(): | if (HPM_COUNTER_EN[31]) { return CsrFieldType::RW; @@ -58,7 +61,9 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: When set, mhpmcounter31 does not increment while the hart in operating in (H)S-mode. + description: + When set, mhpmcounter31 does not increment while the hart in operating + in (H)S-mode. type(): | if (HPM_COUNTER_EN[31] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -74,7 +79,9 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: When set, mhpmcounter31 does not increment while the hart in operating in U-mode. + description: + When set, mhpmcounter31 does not increment while the hart in operating + in U-mode. type(): | if (HPM_COUNTER_EN[31] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -90,7 +97,9 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: When set, mhpmcounter31 does not increment while the hart in operating in VS-mode. + description: + When set, mhpmcounter31 does not increment while the hart in operating + in VS-mode. type(): | if ((HPM_COUNTER_EN[31]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -106,7 +115,9 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: When set, mhpmcounter31 does not increment while the hart in operating in VU-mode. + description: + When set, mhpmcounter31 does not increment while the hart in operating + in VU-mode. type(): | if (HPM_COUNTER_EN[31] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent31h.yaml b/arch/csr/Zihpm/mhpmevent31h.yaml index 0dca0fbe7f..c39151a2ea 100644 --- a/arch/csr/Zihpm/mhpmevent31h.yaml +++ b/arch/csr/Zihpm/mhpmevent31h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent31h long_name: Machine Hardware Performance Counter 31 Control, High half address: 0x73F +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent3h.yaml b/arch/csr/Zihpm/mhpmevent3h.yaml index b92a0a8e0c..a5f437fe81 100644 --- a/arch/csr/Zihpm/mhpmevent3h.yaml +++ b/arch/csr/Zihpm/mhpmevent3h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent3h long_name: Machine Hardware Performance Counter 3 Control, High half address: 0x723 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent4.yaml b/arch/csr/Zihpm/mhpmevent4.yaml index 1291ed96f6..12421c0936 100644 --- a/arch/csr/Zihpm/mhpmevent4.yaml +++ b/arch/csr/Zihpm/mhpmevent4.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent4 long_name: Machine Hardware Performance Counter 4 Control address: 0x324 +writeable: true priv_mode: M length: 64 description: | @@ -42,7 +43,9 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: When set, mhpmcounter4 does not increment while the hart in operating in M-mode. + description: + When set, mhpmcounter4 does not increment while the hart in operating + in M-mode. type(): | if (HPM_COUNTER_EN[4]) { return CsrFieldType::RW; @@ -58,7 +61,9 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: When set, mhpmcounter4 does not increment while the hart in operating in (H)S-mode. + description: + When set, mhpmcounter4 does not increment while the hart in operating + in (H)S-mode. type(): | if (HPM_COUNTER_EN[4] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -74,7 +79,9 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: When set, mhpmcounter4 does not increment while the hart in operating in U-mode. + description: + When set, mhpmcounter4 does not increment while the hart in operating + in U-mode. type(): | if (HPM_COUNTER_EN[4] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -90,7 +97,9 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: When set, mhpmcounter4 does not increment while the hart in operating in VS-mode. + description: + When set, mhpmcounter4 does not increment while the hart in operating + in VS-mode. type(): | if ((HPM_COUNTER_EN[4]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -106,7 +115,9 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: When set, mhpmcounter4 does not increment while the hart in operating in VU-mode. + description: + When set, mhpmcounter4 does not increment while the hart in operating + in VU-mode. type(): | if (HPM_COUNTER_EN[4] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent4h.yaml b/arch/csr/Zihpm/mhpmevent4h.yaml index e70ed1280d..74e0bc4ac1 100644 --- a/arch/csr/Zihpm/mhpmevent4h.yaml +++ b/arch/csr/Zihpm/mhpmevent4h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent4h long_name: Machine Hardware Performance Counter 4 Control, High half address: 0x724 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent5.yaml b/arch/csr/Zihpm/mhpmevent5.yaml index bbe2824f5c..bf0ffe5775 100644 --- a/arch/csr/Zihpm/mhpmevent5.yaml +++ b/arch/csr/Zihpm/mhpmevent5.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent5 long_name: Machine Hardware Performance Counter 5 Control address: 0x325 +writeable: true priv_mode: M length: 64 description: | @@ -42,7 +43,9 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: When set, mhpmcounter5 does not increment while the hart in operating in M-mode. + description: + When set, mhpmcounter5 does not increment while the hart in operating + in M-mode. type(): | if (HPM_COUNTER_EN[5]) { return CsrFieldType::RW; @@ -58,7 +61,9 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: When set, mhpmcounter5 does not increment while the hart in operating in (H)S-mode. + description: + When set, mhpmcounter5 does not increment while the hart in operating + in (H)S-mode. type(): | if (HPM_COUNTER_EN[5] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -74,7 +79,9 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: When set, mhpmcounter5 does not increment while the hart in operating in U-mode. + description: + When set, mhpmcounter5 does not increment while the hart in operating + in U-mode. type(): | if (HPM_COUNTER_EN[5] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -90,7 +97,9 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: When set, mhpmcounter5 does not increment while the hart in operating in VS-mode. + description: + When set, mhpmcounter5 does not increment while the hart in operating + in VS-mode. type(): | if ((HPM_COUNTER_EN[5]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -106,7 +115,9 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: When set, mhpmcounter5 does not increment while the hart in operating in VU-mode. + description: + When set, mhpmcounter5 does not increment while the hart in operating + in VU-mode. type(): | if (HPM_COUNTER_EN[5] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent5h.yaml b/arch/csr/Zihpm/mhpmevent5h.yaml index b8db07f6f7..f8347cf95f 100644 --- a/arch/csr/Zihpm/mhpmevent5h.yaml +++ b/arch/csr/Zihpm/mhpmevent5h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent5h long_name: Machine Hardware Performance Counter 5 Control, High half address: 0x725 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent6.yaml b/arch/csr/Zihpm/mhpmevent6.yaml index f4e0b15cb9..2e6240c7aa 100644 --- a/arch/csr/Zihpm/mhpmevent6.yaml +++ b/arch/csr/Zihpm/mhpmevent6.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent6 long_name: Machine Hardware Performance Counter 6 Control address: 0x326 +writeable: true priv_mode: M length: 64 description: | @@ -42,7 +43,9 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: When set, mhpmcounter6 does not increment while the hart in operating in M-mode. + description: + When set, mhpmcounter6 does not increment while the hart in operating + in M-mode. type(): | if (HPM_COUNTER_EN[6]) { return CsrFieldType::RW; @@ -58,7 +61,9 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: When set, mhpmcounter6 does not increment while the hart in operating in (H)S-mode. + description: + When set, mhpmcounter6 does not increment while the hart in operating + in (H)S-mode. type(): | if (HPM_COUNTER_EN[6] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -74,7 +79,9 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: When set, mhpmcounter6 does not increment while the hart in operating in U-mode. + description: + When set, mhpmcounter6 does not increment while the hart in operating + in U-mode. type(): | if (HPM_COUNTER_EN[6] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -90,7 +97,9 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: When set, mhpmcounter6 does not increment while the hart in operating in VS-mode. + description: + When set, mhpmcounter6 does not increment while the hart in operating + in VS-mode. type(): | if ((HPM_COUNTER_EN[6]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -106,7 +115,9 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: When set, mhpmcounter6 does not increment while the hart in operating in VU-mode. + description: + When set, mhpmcounter6 does not increment while the hart in operating + in VU-mode. type(): | if (HPM_COUNTER_EN[6] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent6h.yaml b/arch/csr/Zihpm/mhpmevent6h.yaml index d6e9003aa5..1708de0339 100644 --- a/arch/csr/Zihpm/mhpmevent6h.yaml +++ b/arch/csr/Zihpm/mhpmevent6h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent6h long_name: Machine Hardware Performance Counter 6 Control, High half address: 0x726 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent7.yaml b/arch/csr/Zihpm/mhpmevent7.yaml index c4586b60bd..e4d4b06fcd 100644 --- a/arch/csr/Zihpm/mhpmevent7.yaml +++ b/arch/csr/Zihpm/mhpmevent7.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent7 long_name: Machine Hardware Performance Counter 7 Control address: 0x327 +writeable: true priv_mode: M length: 64 description: | @@ -42,7 +43,9 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: When set, mhpmcounter7 does not increment while the hart in operating in M-mode. + description: + When set, mhpmcounter7 does not increment while the hart in operating + in M-mode. type(): | if (HPM_COUNTER_EN[7]) { return CsrFieldType::RW; @@ -58,7 +61,9 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: When set, mhpmcounter7 does not increment while the hart in operating in (H)S-mode. + description: + When set, mhpmcounter7 does not increment while the hart in operating + in (H)S-mode. type(): | if (HPM_COUNTER_EN[7] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -74,7 +79,9 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: When set, mhpmcounter7 does not increment while the hart in operating in U-mode. + description: + When set, mhpmcounter7 does not increment while the hart in operating + in U-mode. type(): | if (HPM_COUNTER_EN[7] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -90,7 +97,9 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: When set, mhpmcounter7 does not increment while the hart in operating in VS-mode. + description: + When set, mhpmcounter7 does not increment while the hart in operating + in VS-mode. type(): | if ((HPM_COUNTER_EN[7]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -106,7 +115,9 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: When set, mhpmcounter7 does not increment while the hart in operating in VU-mode. + description: + When set, mhpmcounter7 does not increment while the hart in operating + in VU-mode. type(): | if (HPM_COUNTER_EN[7] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent7h.yaml b/arch/csr/Zihpm/mhpmevent7h.yaml index f04327a66b..03a01a2d3a 100644 --- a/arch/csr/Zihpm/mhpmevent7h.yaml +++ b/arch/csr/Zihpm/mhpmevent7h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent7h long_name: Machine Hardware Performance Counter 7 Control, High half address: 0x727 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent8.yaml b/arch/csr/Zihpm/mhpmevent8.yaml index 349fc9ca30..a3dc41f854 100644 --- a/arch/csr/Zihpm/mhpmevent8.yaml +++ b/arch/csr/Zihpm/mhpmevent8.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent8 long_name: Machine Hardware Performance Counter 8 Control address: 0x328 +writeable: true priv_mode: M length: 64 description: | @@ -42,7 +43,9 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: When set, mhpmcounter8 does not increment while the hart in operating in M-mode. + description: + When set, mhpmcounter8 does not increment while the hart in operating + in M-mode. type(): | if (HPM_COUNTER_EN[8]) { return CsrFieldType::RW; @@ -58,7 +61,9 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: When set, mhpmcounter8 does not increment while the hart in operating in (H)S-mode. + description: + When set, mhpmcounter8 does not increment while the hart in operating + in (H)S-mode. type(): | if (HPM_COUNTER_EN[8] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -74,7 +79,9 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: When set, mhpmcounter8 does not increment while the hart in operating in U-mode. + description: + When set, mhpmcounter8 does not increment while the hart in operating + in U-mode. type(): | if (HPM_COUNTER_EN[8] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -90,7 +97,9 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: When set, mhpmcounter8 does not increment while the hart in operating in VS-mode. + description: + When set, mhpmcounter8 does not increment while the hart in operating + in VS-mode. type(): | if ((HPM_COUNTER_EN[8]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -106,7 +115,9 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: When set, mhpmcounter8 does not increment while the hart in operating in VU-mode. + description: + When set, mhpmcounter8 does not increment while the hart in operating + in VU-mode. type(): | if (HPM_COUNTER_EN[8] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent8h.yaml b/arch/csr/Zihpm/mhpmevent8h.yaml index 0370dc3186..44b58d6c41 100644 --- a/arch/csr/Zihpm/mhpmevent8h.yaml +++ b/arch/csr/Zihpm/mhpmevent8h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent8h long_name: Machine Hardware Performance Counter 8 Control, High half address: 0x728 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent9.yaml b/arch/csr/Zihpm/mhpmevent9.yaml index fc947e3e2d..1d2a7a1ccc 100644 --- a/arch/csr/Zihpm/mhpmevent9.yaml +++ b/arch/csr/Zihpm/mhpmevent9.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent9 long_name: Machine Hardware Performance Counter 9 Control address: 0x329 +writeable: true priv_mode: M length: 64 description: | @@ -42,7 +43,9 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: When set, mhpmcounter9 does not increment while the hart in operating in M-mode. + description: + When set, mhpmcounter9 does not increment while the hart in operating + in M-mode. type(): | if (HPM_COUNTER_EN[9]) { return CsrFieldType::RW; @@ -58,7 +61,9 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: When set, mhpmcounter9 does not increment while the hart in operating in (H)S-mode. + description: + When set, mhpmcounter9 does not increment while the hart in operating + in (H)S-mode. type(): | if (HPM_COUNTER_EN[9] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -74,7 +79,9 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: When set, mhpmcounter9 does not increment while the hart in operating in U-mode. + description: + When set, mhpmcounter9 does not increment while the hart in operating + in U-mode. type(): | if (HPM_COUNTER_EN[9] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -90,7 +97,9 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: When set, mhpmcounter9 does not increment while the hart in operating in VS-mode. + description: + When set, mhpmcounter9 does not increment while the hart in operating + in VS-mode. type(): | if ((HPM_COUNTER_EN[9]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -106,7 +115,9 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: When set, mhpmcounter9 does not increment while the hart in operating in VU-mode. + description: + When set, mhpmcounter9 does not increment while the hart in operating + in VU-mode. type(): | if (HPM_COUNTER_EN[9] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent9h.yaml b/arch/csr/Zihpm/mhpmevent9h.yaml index 946464b3b0..7383b28c30 100644 --- a/arch/csr/Zihpm/mhpmevent9h.yaml +++ b/arch/csr/Zihpm/mhpmevent9h.yaml @@ -7,6 +7,7 @@ kind: csr name: mhpmevent9h long_name: Machine Hardware Performance Counter 9 Control, High half address: 0x729 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/cycle.yaml b/arch/csr/cycle.yaml index 0d7d975cf5..7d2b493245 100644 --- a/arch/csr/cycle.yaml +++ b/arch/csr/cycle.yaml @@ -5,6 +5,7 @@ kind: csr name: cycle long_name: Cycle counter for RDCYCLE Instruction address: 0xC00 +writeable: false description: | Alias for M-mode CSR `mcycle`. diff --git a/arch/csr/cycleh.yaml b/arch/csr/cycleh.yaml index 75ed1b438d..770a46e1b2 100644 --- a/arch/csr/cycleh.yaml +++ b/arch/csr/cycleh.yaml @@ -5,6 +5,7 @@ kind: csr name: cycleh long_name: High-half cycle counter for RDCYCLE Instruction address: 0xC80 +writeable: false base: 32 description: | Alias for M-mode CSR `mcycleh`. diff --git a/arch/csr/hedeleg.yaml b/arch/csr/hedeleg.yaml index f0eb50f396..e50da89a4e 100644 --- a/arch/csr/hedeleg.yaml +++ b/arch/csr/hedeleg.yaml @@ -5,6 +5,7 @@ kind: csr name: hedeleg long_name: Hypervisor Exception Delegation address: 0x602 +writeable: true priv_mode: S length: 64 description: | diff --git a/arch/csr/hedelegh.yaml b/arch/csr/hedelegh.yaml index fc1ad672eb..abe635b742 100644 --- a/arch/csr/hedelegh.yaml +++ b/arch/csr/hedelegh.yaml @@ -5,6 +5,7 @@ kind: csr name: hedelegh long_name: Hypervisor Exception Delegation High address: 0x612 +writeable: true base: 32 priv_mode: S length: 32 diff --git a/arch/csr/hstatus.yaml b/arch/csr/hstatus.yaml index a19aa4bc8f..5f80128965 100644 --- a/arch/csr/hstatus.yaml +++ b/arch/csr/hstatus.yaml @@ -5,6 +5,7 @@ kind: csr name: hstatus long_name: Hypervisor Status address: 0x600 +writeable: true priv_mode: S length: SXLEN description: | diff --git a/arch/csr/instret.yaml b/arch/csr/instret.yaml index b54fedf8d9..2e2be9a645 100644 --- a/arch/csr/instret.yaml +++ b/arch/csr/instret.yaml @@ -5,6 +5,7 @@ kind: csr name: instret long_name: Instructions retired counter for RDINSTRET Instruction address: 0xC02 +writeable: false description: | Alias for M-mode CSR `minstret`. diff --git a/arch/csr/instreth.yaml b/arch/csr/instreth.yaml index bb4df78053..0283bbc389 100644 --- a/arch/csr/instreth.yaml +++ b/arch/csr/instreth.yaml @@ -5,6 +5,7 @@ kind: csr name: instreth long_name: Instructions retired counter, high bits address: 0xC82 +writeable: false base: 32 description: | Alias for high bits of M-mode CSR `minstret`[63:32]. diff --git a/arch/csr/marchid.yaml b/arch/csr/marchid.yaml index fc7e8d8dd1..88e9f5ec1a 100644 --- a/arch/csr/marchid.yaml +++ b/arch/csr/marchid.yaml @@ -5,6 +5,7 @@ kind: csr name: marchid long_name: Machine Architecture ID address: 0xf12 +writeable: false priv_mode: M length: MXLEN description: | diff --git a/arch/csr/mcause.yaml b/arch/csr/mcause.yaml index 11b8b07d58..0f7666d662 100644 --- a/arch/csr/mcause.yaml +++ b/arch/csr/mcause.yaml @@ -5,6 +5,7 @@ kind: csr name: mcause long_name: Machine Cause address: 0x342 +writeable: true priv_mode: M length: MXLEN description: Reports the cause of the latest exception. diff --git a/arch/csr/mconfigptr.yaml b/arch/csr/mconfigptr.yaml index 96ef26a416..14ab0d3d6b 100644 --- a/arch/csr/mconfigptr.yaml +++ b/arch/csr/mconfigptr.yaml @@ -5,6 +5,7 @@ kind: csr name: mconfigptr long_name: Machine Configuration Pointer address: 0xF15 +writeable: false description: | Holds a physical address pointer to the unified discovery data structure in Memory. @@ -45,7 +46,9 @@ fields: ADDRESS: location_rv32: 31-0 location_rv64: 63-0 - description: Pointer to physical address of the Unified Discovery configuration data structure. + description: + Pointer to physical address of the Unified Discovery configuration + data structure. type: RO reset_value(): | return CONFIG_PTR_ADDRESS; diff --git a/arch/csr/mcycle.yaml b/arch/csr/mcycle.yaml index 8fb8102f8b..c36433fcf4 100644 --- a/arch/csr/mcycle.yaml +++ b/arch/csr/mcycle.yaml @@ -6,6 +6,7 @@ name: mcycle long_name: Machine Cycle Counter definedBy: Zicntr address: 0xB00 +writeable: true description: | Counts the number of clock cycles executed by the processor core on which the hart is running. diff --git a/arch/csr/mcycleh.yaml b/arch/csr/mcycleh.yaml index fb1798174f..0de21583c1 100644 --- a/arch/csr/mcycleh.yaml +++ b/arch/csr/mcycleh.yaml @@ -6,6 +6,7 @@ name: mcycleh long_name: High-half machine Cycle Counter definedBy: Zicntr address: 0xB80 +writeable: true description: | High-half alias of `mcycle`. priv_mode: M diff --git a/arch/csr/medeleg.yaml b/arch/csr/medeleg.yaml index 94b6981d04..134ba8baaa 100644 --- a/arch/csr/medeleg.yaml +++ b/arch/csr/medeleg.yaml @@ -5,6 +5,7 @@ kind: csr name: medeleg long_name: Machine Exception Delegation address: 0x302 +writeable: true priv_mode: M length: 64 description: | diff --git a/arch/csr/medelegh.yaml b/arch/csr/medelegh.yaml index bff63b2b0f..e481d906af 100644 --- a/arch/csr/medelegh.yaml +++ b/arch/csr/medelegh.yaml @@ -5,6 +5,7 @@ kind: csr name: medelegh long_name: Machine Exception Delegation, High bits address: 0x312 +writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/menvcfg.yaml b/arch/csr/menvcfg.yaml index 8feafff958..f2ea62adea 100644 --- a/arch/csr/menvcfg.yaml +++ b/arch/csr/menvcfg.yaml @@ -4,6 +4,7 @@ $schema: "csr_schema.json#" kind: csr name: menvcfg address: 0x30A +writeable: true long_name: Machine Environment Configuration description: | Contains fields that control certain characteristics of the execution environment diff --git a/arch/csr/menvcfgh.yaml b/arch/csr/menvcfgh.yaml index 3543f9ea6f..541ff71339 100644 --- a/arch/csr/menvcfgh.yaml +++ b/arch/csr/menvcfgh.yaml @@ -4,6 +4,7 @@ $schema: "csr_schema.json#" kind: csr name: menvcfgh address: 0x31A +writeable: true base: 32 long_name: Machine Environment Configuration description: Contains bits to enable/disable extensions diff --git a/arch/csr/mepc.yaml b/arch/csr/mepc.yaml index 3118fee37a..92ca5c9314 100644 --- a/arch/csr/mepc.yaml +++ b/arch/csr/mepc.yaml @@ -5,6 +5,7 @@ kind: csr name: mepc long_name: Machine Exception Program Counter address: 0x341 +writeable: true priv_mode: M length: MXLEN description: | diff --git a/arch/csr/mhartid.yaml b/arch/csr/mhartid.yaml index 8b5e50793d..6fb026ff41 100644 --- a/arch/csr/mhartid.yaml +++ b/arch/csr/mhartid.yaml @@ -5,6 +5,7 @@ kind: csr name: mhartid long_name: Machine Hart ID address: 0xf14 +writeable: false priv_mode: M length: MXLEN description: Reports the unique hart-specific ID in the system. diff --git a/arch/csr/mideleg.yaml b/arch/csr/mideleg.yaml index af53608a13..a6b0abf963 100644 --- a/arch/csr/mideleg.yaml +++ b/arch/csr/mideleg.yaml @@ -5,6 +5,7 @@ kind: csr name: mideleg long_name: Machine Interrupt Delegation address: 0x303 +writeable: true priv_mode: M length: MXLEN definedBy: diff --git a/arch/csr/mie.yaml b/arch/csr/mie.yaml index 927ed583c8..d65abf2476 100644 --- a/arch/csr/mie.yaml +++ b/arch/csr/mie.yaml @@ -5,6 +5,7 @@ kind: csr name: mie long_name: Machine Interrupt Enable address: 0x304 +writeable: true priv_mode: M length: MXLEN definedBy: Sm diff --git a/arch/csr/mimpid.yaml b/arch/csr/mimpid.yaml index 4d35e45c79..1c9bd58844 100644 --- a/arch/csr/mimpid.yaml +++ b/arch/csr/mimpid.yaml @@ -5,6 +5,7 @@ kind: csr name: mimpid long_name: Machine Implementation ID address: 0xf13 +writeable: false priv_mode: M length: MXLEN description: | diff --git a/arch/csr/minstret.yaml b/arch/csr/minstret.yaml index 9d4344a1c2..2c28fddf30 100644 --- a/arch/csr/minstret.yaml +++ b/arch/csr/minstret.yaml @@ -5,6 +5,7 @@ kind: csr name: minstret long_name: Machine Instructions Retired Counter address: 0xB02 +writeable: true description: | Counts the number of instructions retired by this hart from some arbitrary start point in the past. diff --git a/arch/csr/minstreth.yaml b/arch/csr/minstreth.yaml index 0df4282594..97cb2f6a27 100644 --- a/arch/csr/minstreth.yaml +++ b/arch/csr/minstreth.yaml @@ -5,6 +5,7 @@ kind: csr name: minstreth long_name: Machine Instructions Retired Counter address: 0xB82 +writeable: true description: | Upper half of 64-bit instructions retired counters. diff --git a/arch/csr/mip.yaml b/arch/csr/mip.yaml index 4d831856b4..954f27ff55 100644 --- a/arch/csr/mip.yaml +++ b/arch/csr/mip.yaml @@ -5,6 +5,7 @@ kind: csr name: mip long_name: Machine Interrupt Pending address: 0x344 +writeable: true priv_mode: M # Description is shared with mie CSR (it copies it from here). diff --git a/arch/csr/misa.yaml b/arch/csr/misa.yaml index 4c554b6b06..a7c6cc8626 100644 --- a/arch/csr/misa.yaml +++ b/arch/csr/misa.yaml @@ -5,6 +5,7 @@ kind: csr name: misa long_name: Machine ISA Control address: 0x301 +writeable: true priv_mode: M length: MXLEN description: Reports the XLEN and "major" extensions supported by the ISA. diff --git a/arch/csr/mscratch.yaml b/arch/csr/mscratch.yaml index 544b6bce0c..9f126e1f0b 100644 --- a/arch/csr/mscratch.yaml +++ b/arch/csr/mscratch.yaml @@ -5,6 +5,7 @@ kind: csr name: mscratch long_name: Machine Scratch Register address: 0x340 +writeable: true priv_mode: M length: MXLEN description: Scratch register for software use. Bits are not interpreted by hardware. diff --git a/arch/csr/mseccfg.yaml b/arch/csr/mseccfg.yaml index bc76cd8864..209daa1047 100644 --- a/arch/csr/mseccfg.yaml +++ b/arch/csr/mseccfg.yaml @@ -5,6 +5,7 @@ kind: csr name: mseccfg long_name: Machine Security Configuration address: 0x747 +writeable: true priv_mode: M length: 64 description: Machine Security Configuration diff --git a/arch/csr/mseccfgh.yaml b/arch/csr/mseccfgh.yaml index 3f2330a5c7..b8f894eb05 100644 --- a/arch/csr/mseccfgh.yaml +++ b/arch/csr/mseccfgh.yaml @@ -6,6 +6,7 @@ name: mseccfgh long_name: Most significant 32 bits of Machine Security Configuration base: 32 address: 0x757 +writeable: true priv_mode: M length: 32 description: Machine Security Configuration diff --git a/arch/csr/mstatus.yaml b/arch/csr/mstatus.yaml index 84cd5695ac..23cac80778 100644 --- a/arch/csr/mstatus.yaml +++ b/arch/csr/mstatus.yaml @@ -5,6 +5,7 @@ kind: csr name: mstatus long_name: Machine Status address: 0x300 +writeable: true priv_mode: M # length is MXLEN-bit @@ -12,7 +13,9 @@ priv_mode: M # MXLEN cannot change dynamically, so this will be converted to an integer # in the generated, configuration-dependent spec length: MXLEN -description: The mstatus register tracks and controls the hart's current operating state. +description: + The mstatus register tracks and controls the hart's current operating + state. definedBy: Sm fields: SD: diff --git a/arch/csr/mstatush.yaml b/arch/csr/mstatush.yaml index 1b44ad800c..038a392a90 100644 --- a/arch/csr/mstatush.yaml +++ b/arch/csr/mstatush.yaml @@ -5,10 +5,13 @@ kind: csr name: mstatush long_name: Machine Status High address: 0x310 +writeable: true priv_mode: M base: 32 length: 32 -description: The mstatus register tracks and controls the hart's current operating state. +description: + The mstatus register tracks and controls the hart's current operating + state. definedBy: name: Sm version: ">= 1.12" diff --git a/arch/csr/mtval.yaml b/arch/csr/mtval.yaml index 71b0b9f1e2..cec0138e65 100644 --- a/arch/csr/mtval.yaml +++ b/arch/csr/mtval.yaml @@ -5,6 +5,7 @@ kind: csr name: mtval long_name: Machine Trap Value address: 0x343 +writeable: true description: Holds trap-specific information priv_mode: M length: MXLEN diff --git a/arch/csr/mtvec.yaml b/arch/csr/mtvec.yaml index 265f39fd3e..bf850afc1a 100644 --- a/arch/csr/mtvec.yaml +++ b/arch/csr/mtvec.yaml @@ -5,6 +5,7 @@ kind: csr name: mtvec long_name: Machine Trap Vector Control address: 0x305 +writeable: true priv_mode: M length: MXLEN description: Controls where traps jump. diff --git a/arch/csr/mvendorid.yaml b/arch/csr/mvendorid.yaml index a752ece2da..afd5144f07 100644 --- a/arch/csr/mvendorid.yaml +++ b/arch/csr/mvendorid.yaml @@ -5,6 +5,7 @@ kind: csr name: mvendorid long_name: Machine Vendor ID address: 0xf11 +writeable: false priv_mode: M length: 32 description: Reports the JEDEC manufacturer ID of the core. diff --git a/arch/csr/satp.yaml b/arch/csr/satp.yaml index b4d4a0d3a1..b5f4cf3dd6 100644 --- a/arch/csr/satp.yaml +++ b/arch/csr/satp.yaml @@ -4,8 +4,11 @@ $schema: "csr_schema.json#" kind: csr name: satp address: 0x180 +writeable: true long_name: Supervisor Address Translation and Protection -description: Controls the translation mode in (H)S-mode and U-mode, and holds the current ASID and page table base pointer. +description: + Controls the translation mode in (H)S-mode and U-mode, and holds the + current ASID and page table base pointer. priv_mode: S length: SXLEN definedBy: S diff --git a/arch/csr/scause.yaml b/arch/csr/scause.yaml index c206cd60de..9d25a7906a 100644 --- a/arch/csr/scause.yaml +++ b/arch/csr/scause.yaml @@ -5,6 +5,7 @@ kind: csr name: scause long_name: Supervisor Cause address: 0x142 +writeable: true priv_mode: S length: SXLEN description: Reports the cause of the latest exception. diff --git a/arch/csr/senvcfg.yaml b/arch/csr/senvcfg.yaml index 6feb151349..a142d371ce 100644 --- a/arch/csr/senvcfg.yaml +++ b/arch/csr/senvcfg.yaml @@ -4,6 +4,7 @@ $schema: "csr_schema.json#" kind: csr name: senvcfg address: 0x10A +writeable: true long_name: Supervisor Environment Configuration description: | Contains fields that control certain characteristics of the U-mode execution environment. diff --git a/arch/csr/sepc.yaml b/arch/csr/sepc.yaml index 82fae3a4b3..861f8747f3 100644 --- a/arch/csr/sepc.yaml +++ b/arch/csr/sepc.yaml @@ -5,6 +5,7 @@ kind: csr name: sepc long_name: Supervisor Exception Program Counter address: 0x141 +writeable: true priv_mode: S length: 64 description: | diff --git a/arch/csr/sip.yaml b/arch/csr/sip.yaml index 6de22310d6..f307cc34c5 100644 --- a/arch/csr/sip.yaml +++ b/arch/csr/sip.yaml @@ -5,6 +5,7 @@ kind: csr name: sip long_name: Supervisor Interrupt Pending address: 0x144 +writeable: true priv_mode: S description: | A restricted view of the interrupt pending bits in `mip`. diff --git a/arch/csr/sscratch.yaml b/arch/csr/sscratch.yaml index dceaf14863..4a3c6d405b 100644 --- a/arch/csr/sscratch.yaml +++ b/arch/csr/sscratch.yaml @@ -5,6 +5,7 @@ kind: csr name: sscratch long_name: Supervisor Scratch Register address: 0x140 +writeable: true priv_mode: S length: 64 description: Scratch register for software use. Bits are not interpreted by hardware. diff --git a/arch/csr/sstatus.yaml b/arch/csr/sstatus.yaml index c9ae22e33c..34d644689f 100644 --- a/arch/csr/sstatus.yaml +++ b/arch/csr/sstatus.yaml @@ -5,6 +5,7 @@ kind: csr name: sstatus long_name: Supervisor Status address: 0x100 +writeable: true priv_mode: S length: SXLEN description: | diff --git a/arch/csr/stval.yaml b/arch/csr/stval.yaml index fb447e5059..dddff978c9 100644 --- a/arch/csr/stval.yaml +++ b/arch/csr/stval.yaml @@ -5,6 +5,7 @@ kind: csr name: stval long_name: Supervisor Trap Value address: 0x143 +writeable: true description: Holds trap-specific information priv_mode: S length: 64 diff --git a/arch/csr/stvec.yaml b/arch/csr/stvec.yaml index 3432f8a89a..a77ace47c0 100644 --- a/arch/csr/stvec.yaml +++ b/arch/csr/stvec.yaml @@ -5,6 +5,7 @@ kind: csr name: stvec long_name: Supervisor Trap Vector address: 0x105 +writeable: true priv_mode: S length: 64 description: Controls where traps jump. diff --git a/arch/csr/time.yaml b/arch/csr/time.yaml index 5ebccad92d..2e64103e43 100644 --- a/arch/csr/time.yaml +++ b/arch/csr/time.yaml @@ -5,6 +5,7 @@ kind: csr name: time long_name: Timer for RDTIME Instruction address: 0xC01 +writeable: false description: | [when,"TIME_CSR_IMPLEMENTED == false"] This CSR does not exist, and access will cause an IllegalInstruction exception. diff --git a/arch/csr/timeh.yaml b/arch/csr/timeh.yaml index cdf1ff35be..26a2671597 100644 --- a/arch/csr/timeh.yaml +++ b/arch/csr/timeh.yaml @@ -5,6 +5,7 @@ kind: csr name: timeh long_name: High-half timer for RDTIME Instruction address: 0xC81 +writeable: false base: 32 description: | [when,"TIME_CSR_IMPLEMENTED == false"] diff --git a/arch/csr/vscause.yaml b/arch/csr/vscause.yaml index cfaf02d1dd..6d4c26472e 100644 --- a/arch/csr/vscause.yaml +++ b/arch/csr/vscause.yaml @@ -5,6 +5,7 @@ kind: csr name: vscause long_name: Virtual Supervisor Cause address: 0x242 +writeable: true virtual_address: 0x142 priv_mode: VS length: VSXLEN diff --git a/arch/csr/vsepc.yaml b/arch/csr/vsepc.yaml index 68c7e77d6a..49ff1bbd3e 100644 --- a/arch/csr/vsepc.yaml +++ b/arch/csr/vsepc.yaml @@ -5,6 +5,7 @@ kind: csr name: vsepc long_name: Virtual Supervisor Exception Program Counter address: 0x241 +writeable: true virtual_address: 0x141 priv_mode: VS length: 64 diff --git a/arch/csr/vsstatus.yaml b/arch/csr/vsstatus.yaml index 08287caa26..d1bebff3b4 100644 --- a/arch/csr/vsstatus.yaml +++ b/arch/csr/vsstatus.yaml @@ -5,6 +5,7 @@ kind: csr name: vsstatus long_name: Virtual Supervisor Status address: 0x200 +writeable: true virtual_address: 0x100 priv_mode: VS length: VSXLEN diff --git a/arch/csr/vstval.yaml b/arch/csr/vstval.yaml index 7baa9e8b16..131116cc5e 100644 --- a/arch/csr/vstval.yaml +++ b/arch/csr/vstval.yaml @@ -5,6 +5,7 @@ kind: csr name: vstval long_name: Virtual supervisor Trap Value address: 0x243 +writeable: true virtual_address: 0x143 description: Holds trap-specific information priv_mode: S diff --git a/arch/csr/vstvec.yaml b/arch/csr/vstvec.yaml index 4357ac5894..2405b748a8 100644 --- a/arch/csr/vstvec.yaml +++ b/arch/csr/vstvec.yaml @@ -5,6 +5,7 @@ kind: csr name: vstvec long_name: Supervisor Trap Vector address: 0x205 +writeable: true virtual_address: 0x105 priv_mode: S length: 64 diff --git a/schemas/csr_schema.json b/schemas/csr_schema.json index 6ef1790a77..a3f8100ec9 100644 --- a/schemas/csr_schema.json +++ b/schemas/csr_schema.json @@ -234,10 +234,9 @@ "type": "integer", "description": "Indirect address of the CSR, as given to the indirect CSRs of the `Smcsrind`/`Sscdrind` extensions" }, - "indirect": { + "writeable": { "type": "boolean", - "default": false, - "description": "Whether or not the CSR is accessible via an indirect address" + "description": "Whether or not the CSR can be written by software (i.e., is read-write)" }, "virtual_address": true, "$comment": "Conditionally required; see below", From 7222654336e51584f2cca846b375388b39d17046 Mon Sep 17 00:00:00 2001 From: Derek Hower Date: Fri, 4 Apr 2025 11:12:15 -0700 Subject: [PATCH 08/15] fix(ruby): corrects adoc generation for CSR read expressions --- backends/cpp_hart_gen/lib/gen_cpp.rb | 4 ++-- lib/idl/ast.rb | 34 +++++++++------------------- lib/idl/passes/gen_adoc.rb | 2 +- 3 files changed, 14 insertions(+), 26 deletions(-) diff --git a/backends/cpp_hart_gen/lib/gen_cpp.rb b/backends/cpp_hart_gen/lib/gen_cpp.rb index 87f4590422..d634551795 100644 --- a/backends/cpp_hart_gen/lib/gen_cpp.rb +++ b/backends/cpp_hart_gen/lib/gen_cpp.rb @@ -313,9 +313,9 @@ def gen_cpp(symtab, indent, indent_spaces: 2) field = csr_field.field_def(symtab) if symtab.cfg_arch.multi_xlen? && field.dynamic_location? - "#{' '*indent}__UDB_CSR_BY_NAME(#{csr_field.csr_name(symtab)}).#{field.name}()._hw_write(#{write_value.gen_cpp(symtab, 0, indent_spaces:)}, __UDB_XLEN)" + "#{' '*indent}__UDB_CSR_BY_NAME(#{csr_field.csr_name}).#{field.name}()._hw_write(#{write_value.gen_cpp(symtab, 0, indent_spaces:)}, __UDB_XLEN)" else - "#{' '*indent}__UDB_CSR_BY_NAME(#{csr_field.csr_name(symtab)}).#{field.name}()._hw_write(#{write_value.gen_cpp(symtab, 0, indent_spaces:)})" + "#{' '*indent}__UDB_CSR_BY_NAME(#{csr_field.csr_name}).#{field.name}()._hw_write(#{write_value.gen_cpp(symtab, 0, indent_spaces:)})" end end end diff --git a/lib/idl/ast.rb b/lib/idl/ast.rb index 17a135423f..db311061ac 100644 --- a/lib/idl/ast.rb +++ b/lib/idl/ast.rb @@ -6050,18 +6050,16 @@ def freeze_tree(symtab) def type_check(symtab) @csr.type_check(symtab) - type_error "CSR[#{csr_name(symtab)}] has no field named #{@field_name}" if field_def(symtab).nil? - type_error "CSR[#{csr_name(symtab)}].#{@field_name} is not defined in RV32" if symtab.cfg_arch.mxlen == 32 && !field_def(symtab).defined_in_base32? - type_error "CSR[#{csr_name(symtab)}].#{@field_name} is not defined in RV64" if symtab.cfg_arch.mxlen == 64 && !field_def(symtab).defined_in_base64? + type_error "CSR[#{csr_name}] has no field named #{@field_name}" if field_def(symtab).nil? + type_error "CSR[#{csr_name}].#{@field_name} is not defined in RV32" if symtab.cfg_arch.mxlen == 32 && !field_def(symtab).defined_in_base32? + type_error "CSR[#{csr_name}].#{@field_name} is not defined in RV64" if symtab.cfg_arch.mxlen == 64 && !field_def(symtab).defined_in_base64? end def csr_def(symtab) @csr_obj end - def csr_name(symtab) - csr_def(symtab).name - end + def csr_name = @csr.csr_name def field_def(symtab) @csr_obj.fields.find { |f| f.name == @field_name } @@ -6103,7 +6101,7 @@ def calc_type(symtab) # @!macro value def value(symtab) if @value.nil? - value_error "'#{csr_name(symtab)}.#{field_name(symtab)}' is not RO" + value_error "'#{csr_name}.#{field_name(symtab)}' is not RO" else @value end @@ -6115,7 +6113,7 @@ def calc_value(symtab) symtab.cfg_arch.possible_xlens.each do |effective_xlen| unless field_def(symtab).type(effective_xlen) == "RO" - value_error "'#{csr_name(symtab)}.#{field_name(symtab)}' is not RO" + value_error "'#{csr_name}.#{field_name(symtab)}' is not RO" end end @@ -6177,12 +6175,6 @@ def csr_known?(symtab) !csr_def(symtab).nil? end - def csr_name(symtab) - internal_error "No CSR" unless csr_known?(symtab) - - csr_def(symtab).name - end - # @!macro value def value(symtab) if symtab.cfg_arch.fully_configured? @@ -6190,7 +6182,7 @@ def value(symtab) else value_error "CSR is not defined" unless symtab.cfg_arch.csrs.any? { |icsr| icsr.name == @csr_obj.name } end - @csr_obj.fields.each { |f| value_error "#{csr_name(symtab)}.#{f.name} not RO" unless f.type(symtab) == "RO" } + @csr_obj.fields.each { |f| value_error "#{csr_name}.#{f.name} not RO" unless f.type(symtab) == "RO" } csr_def(symtab).fields.reduce(0) { |val, f| val | (f.value << f.location.begin) } end @@ -6231,9 +6223,7 @@ def csr_known?(symtab) csr.csr_known?(symtab) end - def csr_name(symtab) - csr.csr_name(symtab) - end + def csr_name = csr.csr_name # @!macro value def value(_symtab) @@ -6299,7 +6289,7 @@ def type(symtab) case function_name when "sw_read" if csr_known?(symtab) - l = cfg_arch.csr(csr.csr_name(symtab)).length + l = cfg_arch.csr(csr.csr_name).length Type.new(:bits, width: (l.nil? ? :unknown : l)) else Type.new(:bits, width: symtab.mxlen.nil? ? :unknown : symtab.mxlen) @@ -6317,9 +6307,7 @@ def csr_known?(symtab) csr.csr_known?(symtab) end - def csr_name(symtab) - csr.csr_name(symtab) - end + def csr_name = csr.csr_name def csr_def(symtab) csr.csr_def(symtab) @@ -6331,7 +6319,7 @@ def value(symtab) when "sw_read" value_error "CSR not knowable" unless csr_known?(symtab) cd = csr_def(symtab) - cd.fields.each { |f| value_error "#{csr_name(symtab)}.#{f.name} not RO" unless f.type(symtab) == "RO" } + cd.fields.each { |f| value_error "#{csr_name}.#{f.name} not RO" unless f.type(symtab) == "RO" } value_error "TODO: CSRs with sw_read function" when "address" diff --git a/lib/idl/passes/gen_adoc.rb b/lib/idl/passes/gen_adoc.rb index 355596e1d9..6b6fa43f00 100644 --- a/lib/idl/passes/gen_adoc.rb +++ b/lib/idl/passes/gen_adoc.rb @@ -299,7 +299,7 @@ def gen_adoc(indent = 0, indent_spaces: 2) class CsrReadExpressionAst def gen_adoc(indent = 0, indent_spaces: 2) - csr_text = "CSR[#{idx}]" + csr_text = "CSR[#{csr_name}]" "#{' '*indent}%%LINK%csr;#{csr_name};#{csr_text}%%" end end From ca1cdd5ae173075d25297239e522ede5941347c2 Mon Sep 17 00:00:00 2001 From: Derek Hower Date: Tue, 8 Apr 2025 07:42:21 -0700 Subject: [PATCH 09/15] correct(csr): Fixes the layout file for hpmcounterXh Didn't have "base: 32" --- arch/csr/Zihpm/hpmcounter10h.yaml | 8 ++++---- arch/csr/Zihpm/hpmcounter11h.yaml | 8 ++++---- arch/csr/Zihpm/hpmcounter12h.yaml | 8 ++++---- arch/csr/Zihpm/hpmcounter13h.yaml | 8 ++++---- arch/csr/Zihpm/hpmcounter14h.yaml | 8 ++++---- arch/csr/Zihpm/hpmcounter15h.yaml | 8 ++++---- arch/csr/Zihpm/hpmcounter16h.yaml | 8 ++++---- arch/csr/Zihpm/hpmcounter17h.yaml | 8 ++++---- arch/csr/Zihpm/hpmcounter18h.yaml | 8 ++++---- arch/csr/Zihpm/hpmcounter19h.yaml | 8 ++++---- arch/csr/Zihpm/hpmcounter20h.yaml | 8 ++++---- arch/csr/Zihpm/hpmcounter21h.yaml | 8 ++++---- arch/csr/Zihpm/hpmcounter22h.yaml | 8 ++++---- arch/csr/Zihpm/hpmcounter23h.yaml | 8 ++++---- arch/csr/Zihpm/hpmcounter24h.yaml | 8 ++++---- arch/csr/Zihpm/hpmcounter25h.yaml | 8 ++++---- arch/csr/Zihpm/hpmcounter26h.yaml | 8 ++++---- arch/csr/Zihpm/hpmcounter27h.yaml | 8 ++++---- arch/csr/Zihpm/hpmcounter28h.yaml | 8 ++++---- arch/csr/Zihpm/hpmcounter29h.yaml | 8 ++++---- arch/csr/Zihpm/hpmcounter30h.yaml | 8 ++++---- arch/csr/Zihpm/hpmcounter31h.yaml | 8 ++++---- arch/csr/Zihpm/hpmcounter3h.yaml | 8 ++++---- arch/csr/Zihpm/hpmcounter4h.yaml | 8 ++++---- arch/csr/Zihpm/hpmcounter5h.yaml | 8 ++++---- arch/csr/Zihpm/hpmcounter6h.yaml | 8 ++++---- arch/csr/Zihpm/hpmcounter7h.yaml | 8 ++++---- arch/csr/Zihpm/hpmcounter8h.yaml | 8 ++++---- arch/csr/Zihpm/hpmcounter9h.yaml | 8 ++++---- arch/csr/Zihpm/hpmcounterNh.layout | 7 ++++--- schemas/csr_schema.json | 10 +++------- schemas/schema_defs.json | 5 +++++ 32 files changed, 128 insertions(+), 126 deletions(-) diff --git a/arch/csr/Zihpm/hpmcounter10h.yaml b/arch/csr/Zihpm/hpmcounter10h.yaml index 623ee258aa..c2a7eb8ec5 100644 --- a/arch/csr/Zihpm/hpmcounter10h.yaml +++ b/arch/csr/Zihpm/hpmcounter10h.yaml @@ -7,7 +7,7 @@ kind: csr name: hpmcounter10h long_name: User-mode Hardware Performance Counter 7, high half address: 0xC8A -writeable: false +base: 32 description: | Alias for M-mode CSR `mhpmcounter10h`. @@ -26,12 +26,12 @@ description: | ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U -length: 64 +length: 32 definedBy: Sscofpmf fields: COUNT: - location: 63-0 - alias: mhpmcounter10h.COUNT + location: 31-0 + alias: mhpmcounter10h description: Alias of `mhpmcounter10h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/Zihpm/hpmcounter11h.yaml b/arch/csr/Zihpm/hpmcounter11h.yaml index 40b24be791..71835d4e41 100644 --- a/arch/csr/Zihpm/hpmcounter11h.yaml +++ b/arch/csr/Zihpm/hpmcounter11h.yaml @@ -7,7 +7,7 @@ kind: csr name: hpmcounter11h long_name: User-mode Hardware Performance Counter 8, high half address: 0xC8B -writeable: false +base: 32 description: | Alias for M-mode CSR `mhpmcounter11h`. @@ -26,12 +26,12 @@ description: | ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U -length: 64 +length: 32 definedBy: Sscofpmf fields: COUNT: - location: 63-0 - alias: mhpmcounter11h.COUNT + location: 31-0 + alias: mhpmcounter11h description: Alias of `mhpmcounter11h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/Zihpm/hpmcounter12h.yaml b/arch/csr/Zihpm/hpmcounter12h.yaml index ea0b6465ef..b0aba93eb0 100644 --- a/arch/csr/Zihpm/hpmcounter12h.yaml +++ b/arch/csr/Zihpm/hpmcounter12h.yaml @@ -7,7 +7,7 @@ kind: csr name: hpmcounter12h long_name: User-mode Hardware Performance Counter 9, high half address: 0xC8C -writeable: false +base: 32 description: | Alias for M-mode CSR `mhpmcounter12h`. @@ -26,12 +26,12 @@ description: | ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U -length: 64 +length: 32 definedBy: Sscofpmf fields: COUNT: - location: 63-0 - alias: mhpmcounter12h.COUNT + location: 31-0 + alias: mhpmcounter12h description: Alias of `mhpmcounter12h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/Zihpm/hpmcounter13h.yaml b/arch/csr/Zihpm/hpmcounter13h.yaml index 5eafe2b6df..f7e1ef4b04 100644 --- a/arch/csr/Zihpm/hpmcounter13h.yaml +++ b/arch/csr/Zihpm/hpmcounter13h.yaml @@ -7,7 +7,7 @@ kind: csr name: hpmcounter13h long_name: User-mode Hardware Performance Counter 10, high half address: 0xC8D -writeable: false +base: 32 description: | Alias for M-mode CSR `mhpmcounter13h`. @@ -26,12 +26,12 @@ description: | ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U -length: 64 +length: 32 definedBy: Sscofpmf fields: COUNT: - location: 63-0 - alias: mhpmcounter13h.COUNT + location: 31-0 + alias: mhpmcounter13h description: Alias of `mhpmcounter13h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/Zihpm/hpmcounter14h.yaml b/arch/csr/Zihpm/hpmcounter14h.yaml index ce24e878da..c2b30aa679 100644 --- a/arch/csr/Zihpm/hpmcounter14h.yaml +++ b/arch/csr/Zihpm/hpmcounter14h.yaml @@ -7,7 +7,7 @@ kind: csr name: hpmcounter14h long_name: User-mode Hardware Performance Counter 11, high half address: 0xC8E -writeable: false +base: 32 description: | Alias for M-mode CSR `mhpmcounter14h`. @@ -26,12 +26,12 @@ description: | ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U -length: 64 +length: 32 definedBy: Sscofpmf fields: COUNT: - location: 63-0 - alias: mhpmcounter14h.COUNT + location: 31-0 + alias: mhpmcounter14h description: Alias of `mhpmcounter14h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/Zihpm/hpmcounter15h.yaml b/arch/csr/Zihpm/hpmcounter15h.yaml index 34220b9a98..c892a8d074 100644 --- a/arch/csr/Zihpm/hpmcounter15h.yaml +++ b/arch/csr/Zihpm/hpmcounter15h.yaml @@ -7,7 +7,7 @@ kind: csr name: hpmcounter15h long_name: User-mode Hardware Performance Counter 12, high half address: 0xC8F -writeable: false +base: 32 description: | Alias for M-mode CSR `mhpmcounter15h`. @@ -26,12 +26,12 @@ description: | ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U -length: 64 +length: 32 definedBy: Sscofpmf fields: COUNT: - location: 63-0 - alias: mhpmcounter15h.COUNT + location: 31-0 + alias: mhpmcounter15h description: Alias of `mhpmcounter15h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/Zihpm/hpmcounter16h.yaml b/arch/csr/Zihpm/hpmcounter16h.yaml index 6f996123f1..6e3ccf3e1e 100644 --- a/arch/csr/Zihpm/hpmcounter16h.yaml +++ b/arch/csr/Zihpm/hpmcounter16h.yaml @@ -7,7 +7,7 @@ kind: csr name: hpmcounter16h long_name: User-mode Hardware Performance Counter 13, high half address: 0xC90 -writeable: false +base: 32 description: | Alias for M-mode CSR `mhpmcounter16h`. @@ -26,12 +26,12 @@ description: | ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U -length: 64 +length: 32 definedBy: Sscofpmf fields: COUNT: - location: 63-0 - alias: mhpmcounter16h.COUNT + location: 31-0 + alias: mhpmcounter16h description: Alias of `mhpmcounter16h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/Zihpm/hpmcounter17h.yaml b/arch/csr/Zihpm/hpmcounter17h.yaml index 5faf5fb30f..56971958b0 100644 --- a/arch/csr/Zihpm/hpmcounter17h.yaml +++ b/arch/csr/Zihpm/hpmcounter17h.yaml @@ -7,7 +7,7 @@ kind: csr name: hpmcounter17h long_name: User-mode Hardware Performance Counter 14, high half address: 0xC91 -writeable: false +base: 32 description: | Alias for M-mode CSR `mhpmcounter17h`. @@ -26,12 +26,12 @@ description: | ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U -length: 64 +length: 32 definedBy: Sscofpmf fields: COUNT: - location: 63-0 - alias: mhpmcounter17h.COUNT + location: 31-0 + alias: mhpmcounter17h description: Alias of `mhpmcounter17h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/Zihpm/hpmcounter18h.yaml b/arch/csr/Zihpm/hpmcounter18h.yaml index ea1721f4c4..2994adb538 100644 --- a/arch/csr/Zihpm/hpmcounter18h.yaml +++ b/arch/csr/Zihpm/hpmcounter18h.yaml @@ -7,7 +7,7 @@ kind: csr name: hpmcounter18h long_name: User-mode Hardware Performance Counter 15, high half address: 0xC92 -writeable: false +base: 32 description: | Alias for M-mode CSR `mhpmcounter18h`. @@ -26,12 +26,12 @@ description: | ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U -length: 64 +length: 32 definedBy: Sscofpmf fields: COUNT: - location: 63-0 - alias: mhpmcounter18h.COUNT + location: 31-0 + alias: mhpmcounter18h description: Alias of `mhpmcounter18h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/Zihpm/hpmcounter19h.yaml b/arch/csr/Zihpm/hpmcounter19h.yaml index 8a23619f57..335f0f3da4 100644 --- a/arch/csr/Zihpm/hpmcounter19h.yaml +++ b/arch/csr/Zihpm/hpmcounter19h.yaml @@ -7,7 +7,7 @@ kind: csr name: hpmcounter19h long_name: User-mode Hardware Performance Counter 16, high half address: 0xC93 -writeable: false +base: 32 description: | Alias for M-mode CSR `mhpmcounter19h`. @@ -26,12 +26,12 @@ description: | ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U -length: 64 +length: 32 definedBy: Sscofpmf fields: COUNT: - location: 63-0 - alias: mhpmcounter19h.COUNT + location: 31-0 + alias: mhpmcounter19h description: Alias of `mhpmcounter19h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/Zihpm/hpmcounter20h.yaml b/arch/csr/Zihpm/hpmcounter20h.yaml index db45f652a6..93c8db3a3a 100644 --- a/arch/csr/Zihpm/hpmcounter20h.yaml +++ b/arch/csr/Zihpm/hpmcounter20h.yaml @@ -7,7 +7,7 @@ kind: csr name: hpmcounter20h long_name: User-mode Hardware Performance Counter 17, high half address: 0xC94 -writeable: false +base: 32 description: | Alias for M-mode CSR `mhpmcounter20h`. @@ -26,12 +26,12 @@ description: | ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U -length: 64 +length: 32 definedBy: Sscofpmf fields: COUNT: - location: 63-0 - alias: mhpmcounter20h.COUNT + location: 31-0 + alias: mhpmcounter20h description: Alias of `mhpmcounter20h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/Zihpm/hpmcounter21h.yaml b/arch/csr/Zihpm/hpmcounter21h.yaml index bc30fbf87d..daa5752c0b 100644 --- a/arch/csr/Zihpm/hpmcounter21h.yaml +++ b/arch/csr/Zihpm/hpmcounter21h.yaml @@ -7,7 +7,7 @@ kind: csr name: hpmcounter21h long_name: User-mode Hardware Performance Counter 18, high half address: 0xC95 -writeable: false +base: 32 description: | Alias for M-mode CSR `mhpmcounter21h`. @@ -26,12 +26,12 @@ description: | ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U -length: 64 +length: 32 definedBy: Sscofpmf fields: COUNT: - location: 63-0 - alias: mhpmcounter21h.COUNT + location: 31-0 + alias: mhpmcounter21h description: Alias of `mhpmcounter21h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/Zihpm/hpmcounter22h.yaml b/arch/csr/Zihpm/hpmcounter22h.yaml index 1a0757e946..dc12f8a874 100644 --- a/arch/csr/Zihpm/hpmcounter22h.yaml +++ b/arch/csr/Zihpm/hpmcounter22h.yaml @@ -7,7 +7,7 @@ kind: csr name: hpmcounter22h long_name: User-mode Hardware Performance Counter 19, high half address: 0xC96 -writeable: false +base: 32 description: | Alias for M-mode CSR `mhpmcounter22h`. @@ -26,12 +26,12 @@ description: | ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U -length: 64 +length: 32 definedBy: Sscofpmf fields: COUNT: - location: 63-0 - alias: mhpmcounter22h.COUNT + location: 31-0 + alias: mhpmcounter22h description: Alias of `mhpmcounter22h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/Zihpm/hpmcounter23h.yaml b/arch/csr/Zihpm/hpmcounter23h.yaml index 9744f72931..f830b04687 100644 --- a/arch/csr/Zihpm/hpmcounter23h.yaml +++ b/arch/csr/Zihpm/hpmcounter23h.yaml @@ -7,7 +7,7 @@ kind: csr name: hpmcounter23h long_name: User-mode Hardware Performance Counter 20, high half address: 0xC97 -writeable: false +base: 32 description: | Alias for M-mode CSR `mhpmcounter23h`. @@ -26,12 +26,12 @@ description: | ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U -length: 64 +length: 32 definedBy: Sscofpmf fields: COUNT: - location: 63-0 - alias: mhpmcounter23h.COUNT + location: 31-0 + alias: mhpmcounter23h description: Alias of `mhpmcounter23h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/Zihpm/hpmcounter24h.yaml b/arch/csr/Zihpm/hpmcounter24h.yaml index e3e55a9dc5..33db2d0341 100644 --- a/arch/csr/Zihpm/hpmcounter24h.yaml +++ b/arch/csr/Zihpm/hpmcounter24h.yaml @@ -7,7 +7,7 @@ kind: csr name: hpmcounter24h long_name: User-mode Hardware Performance Counter 21, high half address: 0xC98 -writeable: false +base: 32 description: | Alias for M-mode CSR `mhpmcounter24h`. @@ -26,12 +26,12 @@ description: | ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U -length: 64 +length: 32 definedBy: Sscofpmf fields: COUNT: - location: 63-0 - alias: mhpmcounter24h.COUNT + location: 31-0 + alias: mhpmcounter24h description: Alias of `mhpmcounter24h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/Zihpm/hpmcounter25h.yaml b/arch/csr/Zihpm/hpmcounter25h.yaml index ec7c5092d1..5030078517 100644 --- a/arch/csr/Zihpm/hpmcounter25h.yaml +++ b/arch/csr/Zihpm/hpmcounter25h.yaml @@ -7,7 +7,7 @@ kind: csr name: hpmcounter25h long_name: User-mode Hardware Performance Counter 22, high half address: 0xC99 -writeable: false +base: 32 description: | Alias for M-mode CSR `mhpmcounter25h`. @@ -26,12 +26,12 @@ description: | ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U -length: 64 +length: 32 definedBy: Sscofpmf fields: COUNT: - location: 63-0 - alias: mhpmcounter25h.COUNT + location: 31-0 + alias: mhpmcounter25h description: Alias of `mhpmcounter25h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/Zihpm/hpmcounter26h.yaml b/arch/csr/Zihpm/hpmcounter26h.yaml index d17fa68f13..150ac6e9da 100644 --- a/arch/csr/Zihpm/hpmcounter26h.yaml +++ b/arch/csr/Zihpm/hpmcounter26h.yaml @@ -7,7 +7,7 @@ kind: csr name: hpmcounter26h long_name: User-mode Hardware Performance Counter 23, high half address: 0xC9A -writeable: false +base: 32 description: | Alias for M-mode CSR `mhpmcounter26h`. @@ -26,12 +26,12 @@ description: | ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U -length: 64 +length: 32 definedBy: Sscofpmf fields: COUNT: - location: 63-0 - alias: mhpmcounter26h.COUNT + location: 31-0 + alias: mhpmcounter26h description: Alias of `mhpmcounter26h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/Zihpm/hpmcounter27h.yaml b/arch/csr/Zihpm/hpmcounter27h.yaml index 912022fec9..7bbbc505b0 100644 --- a/arch/csr/Zihpm/hpmcounter27h.yaml +++ b/arch/csr/Zihpm/hpmcounter27h.yaml @@ -7,7 +7,7 @@ kind: csr name: hpmcounter27h long_name: User-mode Hardware Performance Counter 24, high half address: 0xC9B -writeable: false +base: 32 description: | Alias for M-mode CSR `mhpmcounter27h`. @@ -26,12 +26,12 @@ description: | ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U -length: 64 +length: 32 definedBy: Sscofpmf fields: COUNT: - location: 63-0 - alias: mhpmcounter27h.COUNT + location: 31-0 + alias: mhpmcounter27h description: Alias of `mhpmcounter27h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/Zihpm/hpmcounter28h.yaml b/arch/csr/Zihpm/hpmcounter28h.yaml index a0e2b375ac..543aa152cf 100644 --- a/arch/csr/Zihpm/hpmcounter28h.yaml +++ b/arch/csr/Zihpm/hpmcounter28h.yaml @@ -7,7 +7,7 @@ kind: csr name: hpmcounter28h long_name: User-mode Hardware Performance Counter 25, high half address: 0xC9C -writeable: false +base: 32 description: | Alias for M-mode CSR `mhpmcounter28h`. @@ -26,12 +26,12 @@ description: | ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U -length: 64 +length: 32 definedBy: Sscofpmf fields: COUNT: - location: 63-0 - alias: mhpmcounter28h.COUNT + location: 31-0 + alias: mhpmcounter28h description: Alias of `mhpmcounter28h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/Zihpm/hpmcounter29h.yaml b/arch/csr/Zihpm/hpmcounter29h.yaml index 67b6530152..0a956b6fff 100644 --- a/arch/csr/Zihpm/hpmcounter29h.yaml +++ b/arch/csr/Zihpm/hpmcounter29h.yaml @@ -7,7 +7,7 @@ kind: csr name: hpmcounter29h long_name: User-mode Hardware Performance Counter 26, high half address: 0xC9D -writeable: false +base: 32 description: | Alias for M-mode CSR `mhpmcounter29h`. @@ -26,12 +26,12 @@ description: | ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U -length: 64 +length: 32 definedBy: Sscofpmf fields: COUNT: - location: 63-0 - alias: mhpmcounter29h.COUNT + location: 31-0 + alias: mhpmcounter29h description: Alias of `mhpmcounter29h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/Zihpm/hpmcounter30h.yaml b/arch/csr/Zihpm/hpmcounter30h.yaml index 76e3c0b4a8..fd3d0fe52f 100644 --- a/arch/csr/Zihpm/hpmcounter30h.yaml +++ b/arch/csr/Zihpm/hpmcounter30h.yaml @@ -7,7 +7,7 @@ kind: csr name: hpmcounter30h long_name: User-mode Hardware Performance Counter 27, high half address: 0xC9E -writeable: false +base: 32 description: | Alias for M-mode CSR `mhpmcounter30h`. @@ -26,12 +26,12 @@ description: | ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U -length: 64 +length: 32 definedBy: Sscofpmf fields: COUNT: - location: 63-0 - alias: mhpmcounter30h.COUNT + location: 31-0 + alias: mhpmcounter30h description: Alias of `mhpmcounter30h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/Zihpm/hpmcounter31h.yaml b/arch/csr/Zihpm/hpmcounter31h.yaml index e581c66448..94f1832334 100644 --- a/arch/csr/Zihpm/hpmcounter31h.yaml +++ b/arch/csr/Zihpm/hpmcounter31h.yaml @@ -7,7 +7,7 @@ kind: csr name: hpmcounter31h long_name: User-mode Hardware Performance Counter 28, high half address: 0xC9F -writeable: false +base: 32 description: | Alias for M-mode CSR `mhpmcounter31h`. @@ -26,12 +26,12 @@ description: | ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U -length: 64 +length: 32 definedBy: Sscofpmf fields: COUNT: - location: 63-0 - alias: mhpmcounter31h.COUNT + location: 31-0 + alias: mhpmcounter31h description: Alias of `mhpmcounter31h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/Zihpm/hpmcounter3h.yaml b/arch/csr/Zihpm/hpmcounter3h.yaml index f66931bd2e..a060ec9e5c 100644 --- a/arch/csr/Zihpm/hpmcounter3h.yaml +++ b/arch/csr/Zihpm/hpmcounter3h.yaml @@ -7,7 +7,7 @@ kind: csr name: hpmcounter3h long_name: User-mode Hardware Performance Counter 0, high half address: 0xC83 -writeable: false +base: 32 description: | Alias for M-mode CSR `mhpmcounter3h`. @@ -26,12 +26,12 @@ description: | ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U -length: 64 +length: 32 definedBy: Sscofpmf fields: COUNT: - location: 63-0 - alias: mhpmcounter3h.COUNT + location: 31-0 + alias: mhpmcounter3h description: Alias of `mhpmcounter3h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/Zihpm/hpmcounter4h.yaml b/arch/csr/Zihpm/hpmcounter4h.yaml index e922e73588..17c313df00 100644 --- a/arch/csr/Zihpm/hpmcounter4h.yaml +++ b/arch/csr/Zihpm/hpmcounter4h.yaml @@ -7,7 +7,7 @@ kind: csr name: hpmcounter4h long_name: User-mode Hardware Performance Counter 1, high half address: 0xC84 -writeable: false +base: 32 description: | Alias for M-mode CSR `mhpmcounter4h`. @@ -26,12 +26,12 @@ description: | ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U -length: 64 +length: 32 definedBy: Sscofpmf fields: COUNT: - location: 63-0 - alias: mhpmcounter4h.COUNT + location: 31-0 + alias: mhpmcounter4h description: Alias of `mhpmcounter4h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/Zihpm/hpmcounter5h.yaml b/arch/csr/Zihpm/hpmcounter5h.yaml index 505805a41f..df54009d10 100644 --- a/arch/csr/Zihpm/hpmcounter5h.yaml +++ b/arch/csr/Zihpm/hpmcounter5h.yaml @@ -7,7 +7,7 @@ kind: csr name: hpmcounter5h long_name: User-mode Hardware Performance Counter 2, high half address: 0xC85 -writeable: false +base: 32 description: | Alias for M-mode CSR `mhpmcounter5h`. @@ -26,12 +26,12 @@ description: | ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U -length: 64 +length: 32 definedBy: Sscofpmf fields: COUNT: - location: 63-0 - alias: mhpmcounter5h.COUNT + location: 31-0 + alias: mhpmcounter5h description: Alias of `mhpmcounter5h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/Zihpm/hpmcounter6h.yaml b/arch/csr/Zihpm/hpmcounter6h.yaml index cbd7bd150c..1b1ff5f1be 100644 --- a/arch/csr/Zihpm/hpmcounter6h.yaml +++ b/arch/csr/Zihpm/hpmcounter6h.yaml @@ -7,7 +7,7 @@ kind: csr name: hpmcounter6h long_name: User-mode Hardware Performance Counter 3, high half address: 0xC86 -writeable: false +base: 32 description: | Alias for M-mode CSR `mhpmcounter6h`. @@ -26,12 +26,12 @@ description: | ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U -length: 64 +length: 32 definedBy: Sscofpmf fields: COUNT: - location: 63-0 - alias: mhpmcounter6h.COUNT + location: 31-0 + alias: mhpmcounter6h description: Alias of `mhpmcounter6h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/Zihpm/hpmcounter7h.yaml b/arch/csr/Zihpm/hpmcounter7h.yaml index c0607c51cb..70fd0393c9 100644 --- a/arch/csr/Zihpm/hpmcounter7h.yaml +++ b/arch/csr/Zihpm/hpmcounter7h.yaml @@ -7,7 +7,7 @@ kind: csr name: hpmcounter7h long_name: User-mode Hardware Performance Counter 4, high half address: 0xC87 -writeable: false +base: 32 description: | Alias for M-mode CSR `mhpmcounter7h`. @@ -26,12 +26,12 @@ description: | ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U -length: 64 +length: 32 definedBy: Sscofpmf fields: COUNT: - location: 63-0 - alias: mhpmcounter7h.COUNT + location: 31-0 + alias: mhpmcounter7h description: Alias of `mhpmcounter7h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/Zihpm/hpmcounter8h.yaml b/arch/csr/Zihpm/hpmcounter8h.yaml index fda4a1ffc6..31e3016c33 100644 --- a/arch/csr/Zihpm/hpmcounter8h.yaml +++ b/arch/csr/Zihpm/hpmcounter8h.yaml @@ -7,7 +7,7 @@ kind: csr name: hpmcounter8h long_name: User-mode Hardware Performance Counter 5, high half address: 0xC88 -writeable: false +base: 32 description: | Alias for M-mode CSR `mhpmcounter8h`. @@ -26,12 +26,12 @@ description: | ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U -length: 64 +length: 32 definedBy: Sscofpmf fields: COUNT: - location: 63-0 - alias: mhpmcounter8h.COUNT + location: 31-0 + alias: mhpmcounter8h description: Alias of `mhpmcounter8h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/Zihpm/hpmcounter9h.yaml b/arch/csr/Zihpm/hpmcounter9h.yaml index c8061f67d1..0830af8cb1 100644 --- a/arch/csr/Zihpm/hpmcounter9h.yaml +++ b/arch/csr/Zihpm/hpmcounter9h.yaml @@ -7,7 +7,7 @@ kind: csr name: hpmcounter9h long_name: User-mode Hardware Performance Counter 6, high half address: 0xC89 -writeable: false +base: 32 description: | Alias for M-mode CSR `mhpmcounter9h`. @@ -26,12 +26,12 @@ description: | ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U -length: 64 +length: 32 definedBy: Sscofpmf fields: COUNT: - location: 63-0 - alias: mhpmcounter9h.COUNT + location: 31-0 + alias: mhpmcounter9h description: Alias of `mhpmcounter9h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/Zihpm/hpmcounterNh.layout b/arch/csr/Zihpm/hpmcounterNh.layout index 4c30ac4e5c..518202dc9a 100644 --- a/arch/csr/Zihpm/hpmcounterNh.layout +++ b/arch/csr/Zihpm/hpmcounterNh.layout @@ -7,6 +7,7 @@ kind: csr name: hpmcounter<%= hpm_num %>h long_name: User-mode Hardware Performance Counter <%= hpm_num - 3 %>, high half address: 0x<%= (0xC83 + (hpm_num - 3)).to_s(16).upcase %> +base: 32 description: | Alias for M-mode CSR `mhpmcounter<%= hpm_num %>h`. @@ -25,12 +26,12 @@ description: | ! 1 ! 1 ! 1 ! read-only ! read-only ! read-only ! read-only !=== priv_mode: U -length: 64 +length: 32 definedBy: Sscofpmf fields: COUNT: - location: 63-0 - alias: mhpmcounter<%= hpm_num %>h.COUNT + location: 31-0 + alias: mhpmcounter<%= hpm_num %>h description: Alias of `mhpmcounter<%= hpm_num %>h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/schemas/csr_schema.json b/schemas/csr_schema.json index a3f8100ec9..fd159b4fad 100644 --- a/schemas/csr_schema.json +++ b/schemas/csr_schema.json @@ -73,14 +73,12 @@ "alias": { "oneOf": [ { - "type": "string", - "pattern": "^[a-z][a-z0-9]+\\.[A-Z0-9]+(\\[[0-9]+(:[0-9]+)?\\])?$" + "$ref": "schema_defs.json#/$defs/csr_name" }, { "type": "array", "items": { - "type": "string", - "pattern": "^[a-z][a-z0-9]+\\.[A-Z0-9]+(\\[[0-9]+(:[0-9]+)?\\])?$" + "$ref": "schema_defs.json#/$defs/csr_name" } } ], @@ -188,9 +186,7 @@ "description": "Object type" }, "name": { - "type": "string", - "pattern": "^[a-z][a-z0-9_.]+$", - "description": "CSR name" + "$ref": "schema_defs.json#/$defs/csr_name" }, "base": { "type": "integer", diff --git a/schemas/schema_defs.json b/schemas/schema_defs.json index fb60ff841e..5f7ae5ac26 100644 --- a/schemas/schema_defs.json +++ b/schemas/schema_defs.json @@ -17,6 +17,11 @@ "type": "string", "pattern": "^[0-9]+(\\.[0-9]+(\\.[0-9]+(-pre)?)?)?$" }, + "csr_name": { + "type": "string", + "pattern": "^[a-z][a-z0-9_.]+$", + "description": "CSR name" + }, "field_location": { "oneOf": [ { "type": "number", "description": "Location of a single bit" }, From 409517701f9058c5acb3d92e5d7a399b5d6ca092 Mon Sep 17 00:00:00 2001 From: Derek Hower Date: Tue, 8 Apr 2025 08:00:13 -0700 Subject: [PATCH 10/15] fix: buggy last commit --- arch/csr/H/hcounteren.yaml | 1 - arch/csr/I/mcounteren.yaml | 1 - arch/csr/I/pmpaddr0.yaml | 1 - arch/csr/I/pmpaddr1.yaml | 1 - arch/csr/I/pmpaddr10.yaml | 1 - arch/csr/I/pmpaddr11.yaml | 1 - arch/csr/I/pmpaddr12.yaml | 1 - arch/csr/I/pmpaddr13.yaml | 1 - arch/csr/I/pmpaddr14.yaml | 1 - arch/csr/I/pmpaddr15.yaml | 1 - arch/csr/I/pmpaddr16.yaml | 1 - arch/csr/I/pmpaddr17.yaml | 1 - arch/csr/I/pmpaddr18.yaml | 1 - arch/csr/I/pmpaddr19.yaml | 1 - arch/csr/I/pmpaddr2.yaml | 1 - arch/csr/I/pmpaddr20.yaml | 1 - arch/csr/I/pmpaddr21.yaml | 1 - arch/csr/I/pmpaddr22.yaml | 1 - arch/csr/I/pmpaddr23.yaml | 1 - arch/csr/I/pmpaddr24.yaml | 1 - arch/csr/I/pmpaddr25.yaml | 1 - arch/csr/I/pmpaddr26.yaml | 1 - arch/csr/I/pmpaddr27.yaml | 1 - arch/csr/I/pmpaddr28.yaml | 1 - arch/csr/I/pmpaddr29.yaml | 1 - arch/csr/I/pmpaddr3.yaml | 1 - arch/csr/I/pmpaddr30.yaml | 1 - arch/csr/I/pmpaddr31.yaml | 1 - arch/csr/I/pmpaddr32.yaml | 1 - arch/csr/I/pmpaddr33.yaml | 1 - arch/csr/I/pmpaddr34.yaml | 1 - arch/csr/I/pmpaddr35.yaml | 1 - arch/csr/I/pmpaddr36.yaml | 1 - arch/csr/I/pmpaddr37.yaml | 1 - arch/csr/I/pmpaddr38.yaml | 1 - arch/csr/I/pmpaddr39.yaml | 1 - arch/csr/I/pmpaddr4.yaml | 1 - arch/csr/I/pmpaddr40.yaml | 1 - arch/csr/I/pmpaddr41.yaml | 1 - arch/csr/I/pmpaddr42.yaml | 1 - arch/csr/I/pmpaddr43.yaml | 1 - arch/csr/I/pmpaddr44.yaml | 1 - arch/csr/I/pmpaddr45.yaml | 1 - arch/csr/I/pmpaddr46.yaml | 1 - arch/csr/I/pmpaddr47.yaml | 1 - arch/csr/I/pmpaddr48.yaml | 1 - arch/csr/I/pmpaddr49.yaml | 1 - arch/csr/I/pmpaddr5.yaml | 1 - arch/csr/I/pmpaddr50.yaml | 1 - arch/csr/I/pmpaddr51.yaml | 1 - arch/csr/I/pmpaddr52.yaml | 1 - arch/csr/I/pmpaddr53.yaml | 1 - arch/csr/I/pmpaddr54.yaml | 1 - arch/csr/I/pmpaddr55.yaml | 1 - arch/csr/I/pmpaddr56.yaml | 1 - arch/csr/I/pmpaddr57.yaml | 1 - arch/csr/I/pmpaddr58.yaml | 1 - arch/csr/I/pmpaddr59.yaml | 1 - arch/csr/I/pmpaddr6.yaml | 1 - arch/csr/I/pmpaddr60.yaml | 1 - arch/csr/I/pmpaddr61.yaml | 1 - arch/csr/I/pmpaddr62.yaml | 1 - arch/csr/I/pmpaddr63.yaml | 1 - arch/csr/I/pmpaddr7.yaml | 1 - arch/csr/I/pmpaddr8.yaml | 1 - arch/csr/I/pmpaddr9.yaml | 1 - arch/csr/I/pmpcfg0.yaml | 1 - arch/csr/I/pmpcfg1.yaml | 1 - arch/csr/I/pmpcfg10.yaml | 1 - arch/csr/I/pmpcfg11.yaml | 1 - arch/csr/I/pmpcfg12.yaml | 1 - arch/csr/I/pmpcfg13.yaml | 1 - arch/csr/I/pmpcfg14.yaml | 1 - arch/csr/I/pmpcfg15.yaml | 1 - arch/csr/I/pmpcfg2.yaml | 1 - arch/csr/I/pmpcfg3.yaml | 1 - arch/csr/I/pmpcfg4.yaml | 1 - arch/csr/I/pmpcfg5.yaml | 1 - arch/csr/I/pmpcfg6.yaml | 1 - arch/csr/I/pmpcfg7.yaml | 1 - arch/csr/I/pmpcfg8.yaml | 1 - arch/csr/I/pmpcfg9.yaml | 1 - arch/csr/S/scounteren.yaml | 1 - arch/csr/Zicntr/mcountinhibit.yaml | 1 - arch/csr/Zihpm/hpmcounter10.yaml | 1 - arch/csr/Zihpm/hpmcounter10h.yaml | 4 ++-- arch/csr/Zihpm/hpmcounter11.yaml | 1 - arch/csr/Zihpm/hpmcounter11h.yaml | 4 ++-- arch/csr/Zihpm/hpmcounter12.yaml | 1 - arch/csr/Zihpm/hpmcounter12h.yaml | 4 ++-- arch/csr/Zihpm/hpmcounter13.yaml | 1 - arch/csr/Zihpm/hpmcounter13h.yaml | 4 ++-- arch/csr/Zihpm/hpmcounter14.yaml | 1 - arch/csr/Zihpm/hpmcounter14h.yaml | 4 ++-- arch/csr/Zihpm/hpmcounter15.yaml | 1 - arch/csr/Zihpm/hpmcounter15h.yaml | 4 ++-- arch/csr/Zihpm/hpmcounter16.yaml | 1 - arch/csr/Zihpm/hpmcounter16h.yaml | 4 ++-- arch/csr/Zihpm/hpmcounter17.yaml | 1 - arch/csr/Zihpm/hpmcounter17h.yaml | 4 ++-- arch/csr/Zihpm/hpmcounter18.yaml | 1 - arch/csr/Zihpm/hpmcounter18h.yaml | 4 ++-- arch/csr/Zihpm/hpmcounter19.yaml | 1 - arch/csr/Zihpm/hpmcounter19h.yaml | 4 ++-- arch/csr/Zihpm/hpmcounter20.yaml | 1 - arch/csr/Zihpm/hpmcounter20h.yaml | 4 ++-- arch/csr/Zihpm/hpmcounter21.yaml | 1 - arch/csr/Zihpm/hpmcounter21h.yaml | 4 ++-- arch/csr/Zihpm/hpmcounter22.yaml | 1 - arch/csr/Zihpm/hpmcounter22h.yaml | 4 ++-- arch/csr/Zihpm/hpmcounter23.yaml | 1 - arch/csr/Zihpm/hpmcounter23h.yaml | 4 ++-- arch/csr/Zihpm/hpmcounter24.yaml | 1 - arch/csr/Zihpm/hpmcounter24h.yaml | 4 ++-- arch/csr/Zihpm/hpmcounter25.yaml | 1 - arch/csr/Zihpm/hpmcounter25h.yaml | 4 ++-- arch/csr/Zihpm/hpmcounter26.yaml | 1 - arch/csr/Zihpm/hpmcounter26h.yaml | 4 ++-- arch/csr/Zihpm/hpmcounter27.yaml | 1 - arch/csr/Zihpm/hpmcounter27h.yaml | 4 ++-- arch/csr/Zihpm/hpmcounter28.yaml | 1 - arch/csr/Zihpm/hpmcounter28h.yaml | 4 ++-- arch/csr/Zihpm/hpmcounter29.yaml | 1 - arch/csr/Zihpm/hpmcounter29h.yaml | 4 ++-- arch/csr/Zihpm/hpmcounter3.yaml | 1 - arch/csr/Zihpm/hpmcounter30.yaml | 1 - arch/csr/Zihpm/hpmcounter30h.yaml | 4 ++-- arch/csr/Zihpm/hpmcounter31.yaml | 1 - arch/csr/Zihpm/hpmcounter31h.yaml | 4 ++-- arch/csr/Zihpm/hpmcounter3h.yaml | 4 ++-- arch/csr/Zihpm/hpmcounter4.yaml | 1 - arch/csr/Zihpm/hpmcounter4h.yaml | 4 ++-- arch/csr/Zihpm/hpmcounter5.yaml | 1 - arch/csr/Zihpm/hpmcounter5h.yaml | 4 ++-- arch/csr/Zihpm/hpmcounter6.yaml | 1 - arch/csr/Zihpm/hpmcounter6h.yaml | 4 ++-- arch/csr/Zihpm/hpmcounter7.yaml | 1 - arch/csr/Zihpm/hpmcounter7h.yaml | 4 ++-- arch/csr/Zihpm/hpmcounter8.yaml | 1 - arch/csr/Zihpm/hpmcounter8h.yaml | 4 ++-- arch/csr/Zihpm/hpmcounter9.yaml | 1 - arch/csr/Zihpm/hpmcounter9h.yaml | 4 ++-- arch/csr/Zihpm/hpmcounterNh.layout | 2 +- arch/csr/Zihpm/mhpmcounter10.yaml | 1 - arch/csr/Zihpm/mhpmcounter10h.yaml | 1 - arch/csr/Zihpm/mhpmcounter11.yaml | 1 - arch/csr/Zihpm/mhpmcounter11h.yaml | 1 - arch/csr/Zihpm/mhpmcounter12.yaml | 1 - arch/csr/Zihpm/mhpmcounter12h.yaml | 1 - arch/csr/Zihpm/mhpmcounter13.yaml | 1 - arch/csr/Zihpm/mhpmcounter13h.yaml | 1 - arch/csr/Zihpm/mhpmcounter14.yaml | 1 - arch/csr/Zihpm/mhpmcounter14h.yaml | 1 - arch/csr/Zihpm/mhpmcounter15.yaml | 1 - arch/csr/Zihpm/mhpmcounter15h.yaml | 1 - arch/csr/Zihpm/mhpmcounter16.yaml | 1 - arch/csr/Zihpm/mhpmcounter16h.yaml | 1 - arch/csr/Zihpm/mhpmcounter17.yaml | 1 - arch/csr/Zihpm/mhpmcounter17h.yaml | 1 - arch/csr/Zihpm/mhpmcounter18.yaml | 1 - arch/csr/Zihpm/mhpmcounter18h.yaml | 1 - arch/csr/Zihpm/mhpmcounter19.yaml | 1 - arch/csr/Zihpm/mhpmcounter19h.yaml | 1 - arch/csr/Zihpm/mhpmcounter20.yaml | 1 - arch/csr/Zihpm/mhpmcounter20h.yaml | 1 - arch/csr/Zihpm/mhpmcounter21.yaml | 1 - arch/csr/Zihpm/mhpmcounter21h.yaml | 1 - arch/csr/Zihpm/mhpmcounter22.yaml | 1 - arch/csr/Zihpm/mhpmcounter22h.yaml | 1 - arch/csr/Zihpm/mhpmcounter23.yaml | 1 - arch/csr/Zihpm/mhpmcounter23h.yaml | 1 - arch/csr/Zihpm/mhpmcounter24.yaml | 1 - arch/csr/Zihpm/mhpmcounter24h.yaml | 1 - arch/csr/Zihpm/mhpmcounter25.yaml | 1 - arch/csr/Zihpm/mhpmcounter25h.yaml | 1 - arch/csr/Zihpm/mhpmcounter26.yaml | 1 - arch/csr/Zihpm/mhpmcounter26h.yaml | 1 - arch/csr/Zihpm/mhpmcounter27.yaml | 1 - arch/csr/Zihpm/mhpmcounter27h.yaml | 1 - arch/csr/Zihpm/mhpmcounter28.yaml | 1 - arch/csr/Zihpm/mhpmcounter28h.yaml | 1 - arch/csr/Zihpm/mhpmcounter29.yaml | 1 - arch/csr/Zihpm/mhpmcounter29h.yaml | 1 - arch/csr/Zihpm/mhpmcounter3.yaml | 1 - arch/csr/Zihpm/mhpmcounter30.yaml | 1 - arch/csr/Zihpm/mhpmcounter30h.yaml | 1 - arch/csr/Zihpm/mhpmcounter31.yaml | 1 - arch/csr/Zihpm/mhpmcounter31h.yaml | 1 - arch/csr/Zihpm/mhpmcounter3h.yaml | 1 - arch/csr/Zihpm/mhpmcounter4.yaml | 1 - arch/csr/Zihpm/mhpmcounter4h.yaml | 1 - arch/csr/Zihpm/mhpmcounter5.yaml | 1 - arch/csr/Zihpm/mhpmcounter5h.yaml | 1 - arch/csr/Zihpm/mhpmcounter6.yaml | 1 - arch/csr/Zihpm/mhpmcounter6h.yaml | 1 - arch/csr/Zihpm/mhpmcounter7.yaml | 1 - arch/csr/Zihpm/mhpmcounter7h.yaml | 1 - arch/csr/Zihpm/mhpmcounter8.yaml | 1 - arch/csr/Zihpm/mhpmcounter8h.yaml | 1 - arch/csr/Zihpm/mhpmcounter9.yaml | 1 - arch/csr/Zihpm/mhpmcounter9h.yaml | 1 - arch/csr/Zihpm/mhpmevent10.yaml | 21 +++++---------------- arch/csr/Zihpm/mhpmevent10h.yaml | 1 - arch/csr/Zihpm/mhpmevent11.yaml | 21 +++++---------------- arch/csr/Zihpm/mhpmevent11h.yaml | 1 - arch/csr/Zihpm/mhpmevent12.yaml | 21 +++++---------------- arch/csr/Zihpm/mhpmevent12h.yaml | 1 - arch/csr/Zihpm/mhpmevent13.yaml | 21 +++++---------------- arch/csr/Zihpm/mhpmevent13h.yaml | 1 - arch/csr/Zihpm/mhpmevent14.yaml | 21 +++++---------------- arch/csr/Zihpm/mhpmevent14h.yaml | 1 - arch/csr/Zihpm/mhpmevent15.yaml | 21 +++++---------------- arch/csr/Zihpm/mhpmevent15h.yaml | 1 - arch/csr/Zihpm/mhpmevent16.yaml | 21 +++++---------------- arch/csr/Zihpm/mhpmevent16h.yaml | 1 - arch/csr/Zihpm/mhpmevent17.yaml | 21 +++++---------------- arch/csr/Zihpm/mhpmevent17h.yaml | 1 - arch/csr/Zihpm/mhpmevent18.yaml | 21 +++++---------------- arch/csr/Zihpm/mhpmevent18h.yaml | 1 - arch/csr/Zihpm/mhpmevent19.yaml | 21 +++++---------------- arch/csr/Zihpm/mhpmevent19h.yaml | 1 - arch/csr/Zihpm/mhpmevent20.yaml | 21 +++++---------------- arch/csr/Zihpm/mhpmevent20h.yaml | 1 - arch/csr/Zihpm/mhpmevent21.yaml | 21 +++++---------------- arch/csr/Zihpm/mhpmevent21h.yaml | 1 - arch/csr/Zihpm/mhpmevent22.yaml | 21 +++++---------------- arch/csr/Zihpm/mhpmevent22h.yaml | 1 - arch/csr/Zihpm/mhpmevent23.yaml | 21 +++++---------------- arch/csr/Zihpm/mhpmevent23h.yaml | 1 - arch/csr/Zihpm/mhpmevent24.yaml | 21 +++++---------------- arch/csr/Zihpm/mhpmevent24h.yaml | 1 - arch/csr/Zihpm/mhpmevent25.yaml | 21 +++++---------------- arch/csr/Zihpm/mhpmevent25h.yaml | 1 - arch/csr/Zihpm/mhpmevent26.yaml | 21 +++++---------------- arch/csr/Zihpm/mhpmevent26h.yaml | 1 - arch/csr/Zihpm/mhpmevent27.yaml | 21 +++++---------------- arch/csr/Zihpm/mhpmevent27h.yaml | 1 - arch/csr/Zihpm/mhpmevent28.yaml | 21 +++++---------------- arch/csr/Zihpm/mhpmevent28h.yaml | 1 - arch/csr/Zihpm/mhpmevent29.yaml | 21 +++++---------------- arch/csr/Zihpm/mhpmevent29h.yaml | 1 - arch/csr/Zihpm/mhpmevent3.yaml | 21 +++++---------------- arch/csr/Zihpm/mhpmevent30.yaml | 21 +++++---------------- arch/csr/Zihpm/mhpmevent30h.yaml | 1 - arch/csr/Zihpm/mhpmevent31.yaml | 21 +++++---------------- arch/csr/Zihpm/mhpmevent31h.yaml | 1 - arch/csr/Zihpm/mhpmevent3h.yaml | 1 - arch/csr/Zihpm/mhpmevent4.yaml | 21 +++++---------------- arch/csr/Zihpm/mhpmevent4h.yaml | 1 - arch/csr/Zihpm/mhpmevent5.yaml | 21 +++++---------------- arch/csr/Zihpm/mhpmevent5h.yaml | 1 - arch/csr/Zihpm/mhpmevent6.yaml | 21 +++++---------------- arch/csr/Zihpm/mhpmevent6h.yaml | 1 - arch/csr/Zihpm/mhpmevent7.yaml | 21 +++++---------------- arch/csr/Zihpm/mhpmevent7h.yaml | 1 - arch/csr/Zihpm/mhpmevent8.yaml | 21 +++++---------------- arch/csr/Zihpm/mhpmevent8h.yaml | 1 - arch/csr/Zihpm/mhpmevent9.yaml | 21 +++++---------------- arch/csr/Zihpm/mhpmevent9h.yaml | 1 - schemas/csr_schema.json | 14 ++++++++++++-- schemas/schema_defs.json | 10 ++++++++++ 261 files changed, 226 insertions(+), 725 deletions(-) diff --git a/arch/csr/H/hcounteren.yaml b/arch/csr/H/hcounteren.yaml index 1f0cacb970..45a80cfa49 100644 --- a/arch/csr/H/hcounteren.yaml +++ b/arch/csr/H/hcounteren.yaml @@ -6,7 +6,6 @@ kind: csr name: hcounteren long_name: Hypervisor Counter Enable address: 0x606 -writeable: true priv_mode: S length: 32 description: | diff --git a/arch/csr/I/mcounteren.yaml b/arch/csr/I/mcounteren.yaml index 4b463a6c71..7d2e0dbac2 100644 --- a/arch/csr/I/mcounteren.yaml +++ b/arch/csr/I/mcounteren.yaml @@ -6,7 +6,6 @@ kind: csr name: mcounteren long_name: Machine Counter Enable address: 0x306 -writeable: true priv_mode: M length: 32 description: | diff --git a/arch/csr/I/pmpaddr0.yaml b/arch/csr/I/pmpaddr0.yaml index 260044ac66..250d438c06 100644 --- a/arch/csr/I/pmpaddr0.yaml +++ b/arch/csr/I/pmpaddr0.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr0 long_name: PMP Address 0 address: 0x3B0 -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr1.yaml b/arch/csr/I/pmpaddr1.yaml index 3bd35c72f1..5e24bf677c 100644 --- a/arch/csr/I/pmpaddr1.yaml +++ b/arch/csr/I/pmpaddr1.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr1 long_name: PMP Address 1 address: 0x3B1 -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr10.yaml b/arch/csr/I/pmpaddr10.yaml index 060fdf466a..a7da04a4b6 100644 --- a/arch/csr/I/pmpaddr10.yaml +++ b/arch/csr/I/pmpaddr10.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr10 long_name: PMP Address 10 address: 0x3BA -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr11.yaml b/arch/csr/I/pmpaddr11.yaml index 3dd73dd011..a8ccd0b6bc 100644 --- a/arch/csr/I/pmpaddr11.yaml +++ b/arch/csr/I/pmpaddr11.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr11 long_name: PMP Address 11 address: 0x3BB -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr12.yaml b/arch/csr/I/pmpaddr12.yaml index c5ab762ef5..10f1f2efe5 100644 --- a/arch/csr/I/pmpaddr12.yaml +++ b/arch/csr/I/pmpaddr12.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr12 long_name: PMP Address 12 address: 0x3BC -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr13.yaml b/arch/csr/I/pmpaddr13.yaml index 8bff40b843..99d40a0936 100644 --- a/arch/csr/I/pmpaddr13.yaml +++ b/arch/csr/I/pmpaddr13.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr13 long_name: PMP Address 13 address: 0x3BD -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr14.yaml b/arch/csr/I/pmpaddr14.yaml index 8caa138a42..cda0e1265e 100644 --- a/arch/csr/I/pmpaddr14.yaml +++ b/arch/csr/I/pmpaddr14.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr14 long_name: PMP Address 14 address: 0x3BE -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr15.yaml b/arch/csr/I/pmpaddr15.yaml index 183d441a60..1cb1232715 100644 --- a/arch/csr/I/pmpaddr15.yaml +++ b/arch/csr/I/pmpaddr15.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr15 long_name: PMP Address 15 address: 0x3BF -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr16.yaml b/arch/csr/I/pmpaddr16.yaml index 60849d9dbf..d766d82fa5 100644 --- a/arch/csr/I/pmpaddr16.yaml +++ b/arch/csr/I/pmpaddr16.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr16 long_name: PMP Address 16 address: 0x3C0 -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr17.yaml b/arch/csr/I/pmpaddr17.yaml index 326781d8a9..94b5b47b47 100644 --- a/arch/csr/I/pmpaddr17.yaml +++ b/arch/csr/I/pmpaddr17.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr17 long_name: PMP Address 17 address: 0x3C1 -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr18.yaml b/arch/csr/I/pmpaddr18.yaml index 6d725a7e64..1006a07df5 100644 --- a/arch/csr/I/pmpaddr18.yaml +++ b/arch/csr/I/pmpaddr18.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr18 long_name: PMP Address 18 address: 0x3C2 -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr19.yaml b/arch/csr/I/pmpaddr19.yaml index a1380146b3..7caa8cfbed 100644 --- a/arch/csr/I/pmpaddr19.yaml +++ b/arch/csr/I/pmpaddr19.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr19 long_name: PMP Address 19 address: 0x3C3 -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr2.yaml b/arch/csr/I/pmpaddr2.yaml index 37ca3e5c54..8805ecdafe 100644 --- a/arch/csr/I/pmpaddr2.yaml +++ b/arch/csr/I/pmpaddr2.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr2 long_name: PMP Address 2 address: 0x3B2 -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr20.yaml b/arch/csr/I/pmpaddr20.yaml index f5bc7eed7f..2479fbb520 100644 --- a/arch/csr/I/pmpaddr20.yaml +++ b/arch/csr/I/pmpaddr20.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr20 long_name: PMP Address 20 address: 0x3C4 -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr21.yaml b/arch/csr/I/pmpaddr21.yaml index 66b16eb7c7..27f99fec38 100644 --- a/arch/csr/I/pmpaddr21.yaml +++ b/arch/csr/I/pmpaddr21.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr21 long_name: PMP Address 21 address: 0x3C5 -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr22.yaml b/arch/csr/I/pmpaddr22.yaml index 173311eeec..e738359032 100644 --- a/arch/csr/I/pmpaddr22.yaml +++ b/arch/csr/I/pmpaddr22.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr22 long_name: PMP Address 22 address: 0x3C6 -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr23.yaml b/arch/csr/I/pmpaddr23.yaml index 9d9cf29811..b23078e01e 100644 --- a/arch/csr/I/pmpaddr23.yaml +++ b/arch/csr/I/pmpaddr23.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr23 long_name: PMP Address 23 address: 0x3C7 -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr24.yaml b/arch/csr/I/pmpaddr24.yaml index 987f8e7540..f07a22f661 100644 --- a/arch/csr/I/pmpaddr24.yaml +++ b/arch/csr/I/pmpaddr24.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr24 long_name: PMP Address 24 address: 0x3C8 -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr25.yaml b/arch/csr/I/pmpaddr25.yaml index d2e53d83eb..c3a791b223 100644 --- a/arch/csr/I/pmpaddr25.yaml +++ b/arch/csr/I/pmpaddr25.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr25 long_name: PMP Address 25 address: 0x3C9 -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr26.yaml b/arch/csr/I/pmpaddr26.yaml index 9c1a92dd02..ad2d1cb063 100644 --- a/arch/csr/I/pmpaddr26.yaml +++ b/arch/csr/I/pmpaddr26.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr26 long_name: PMP Address 26 address: 0x3CA -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr27.yaml b/arch/csr/I/pmpaddr27.yaml index f8df97afdc..ef27d3bf9c 100644 --- a/arch/csr/I/pmpaddr27.yaml +++ b/arch/csr/I/pmpaddr27.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr27 long_name: PMP Address 27 address: 0x3CB -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr28.yaml b/arch/csr/I/pmpaddr28.yaml index c2ba979815..b7f1bf4278 100644 --- a/arch/csr/I/pmpaddr28.yaml +++ b/arch/csr/I/pmpaddr28.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr28 long_name: PMP Address 28 address: 0x3CC -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr29.yaml b/arch/csr/I/pmpaddr29.yaml index ebd9902dcb..7a0a971ad6 100644 --- a/arch/csr/I/pmpaddr29.yaml +++ b/arch/csr/I/pmpaddr29.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr29 long_name: PMP Address 29 address: 0x3CD -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr3.yaml b/arch/csr/I/pmpaddr3.yaml index 3e96214a57..7d79c0b926 100644 --- a/arch/csr/I/pmpaddr3.yaml +++ b/arch/csr/I/pmpaddr3.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr3 long_name: PMP Address 3 address: 0x3B3 -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr30.yaml b/arch/csr/I/pmpaddr30.yaml index 84aa312fcc..0b8481e85d 100644 --- a/arch/csr/I/pmpaddr30.yaml +++ b/arch/csr/I/pmpaddr30.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr30 long_name: PMP Address 30 address: 0x3CE -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr31.yaml b/arch/csr/I/pmpaddr31.yaml index 74a63dd8a2..cb6889d511 100644 --- a/arch/csr/I/pmpaddr31.yaml +++ b/arch/csr/I/pmpaddr31.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr31 long_name: PMP Address 31 address: 0x3CF -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr32.yaml b/arch/csr/I/pmpaddr32.yaml index 9cb24997c4..ef38ca7aab 100644 --- a/arch/csr/I/pmpaddr32.yaml +++ b/arch/csr/I/pmpaddr32.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr32 long_name: PMP Address 32 address: 0x3D0 -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr33.yaml b/arch/csr/I/pmpaddr33.yaml index f8d6c238e7..8bac474921 100644 --- a/arch/csr/I/pmpaddr33.yaml +++ b/arch/csr/I/pmpaddr33.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr33 long_name: PMP Address 33 address: 0x3D1 -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr34.yaml b/arch/csr/I/pmpaddr34.yaml index 602d4e1b60..8c06828a18 100644 --- a/arch/csr/I/pmpaddr34.yaml +++ b/arch/csr/I/pmpaddr34.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr34 long_name: PMP Address 34 address: 0x3D2 -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr35.yaml b/arch/csr/I/pmpaddr35.yaml index 1d4e0abba2..8cc63fde59 100644 --- a/arch/csr/I/pmpaddr35.yaml +++ b/arch/csr/I/pmpaddr35.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr35 long_name: PMP Address 35 address: 0x3D3 -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr36.yaml b/arch/csr/I/pmpaddr36.yaml index 9e3e93c6c8..4b22831126 100644 --- a/arch/csr/I/pmpaddr36.yaml +++ b/arch/csr/I/pmpaddr36.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr36 long_name: PMP Address 36 address: 0x3D4 -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr37.yaml b/arch/csr/I/pmpaddr37.yaml index 611ee8428a..957132029e 100644 --- a/arch/csr/I/pmpaddr37.yaml +++ b/arch/csr/I/pmpaddr37.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr37 long_name: PMP Address 37 address: 0x3D5 -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr38.yaml b/arch/csr/I/pmpaddr38.yaml index c953bccb70..4979a53a5e 100644 --- a/arch/csr/I/pmpaddr38.yaml +++ b/arch/csr/I/pmpaddr38.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr38 long_name: PMP Address 38 address: 0x3D6 -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr39.yaml b/arch/csr/I/pmpaddr39.yaml index c78b253a14..41340b4953 100644 --- a/arch/csr/I/pmpaddr39.yaml +++ b/arch/csr/I/pmpaddr39.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr39 long_name: PMP Address 39 address: 0x3D7 -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr4.yaml b/arch/csr/I/pmpaddr4.yaml index 25e407f2d5..0a5d45b7ab 100644 --- a/arch/csr/I/pmpaddr4.yaml +++ b/arch/csr/I/pmpaddr4.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr4 long_name: PMP Address 4 address: 0x3B4 -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr40.yaml b/arch/csr/I/pmpaddr40.yaml index 359f0ce625..21b3cf11fe 100644 --- a/arch/csr/I/pmpaddr40.yaml +++ b/arch/csr/I/pmpaddr40.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr40 long_name: PMP Address 40 address: 0x3D8 -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr41.yaml b/arch/csr/I/pmpaddr41.yaml index cc856c92a5..6bb1bafc97 100644 --- a/arch/csr/I/pmpaddr41.yaml +++ b/arch/csr/I/pmpaddr41.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr41 long_name: PMP Address 41 address: 0x3D9 -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr42.yaml b/arch/csr/I/pmpaddr42.yaml index 561eabf1b1..bdab7845a1 100644 --- a/arch/csr/I/pmpaddr42.yaml +++ b/arch/csr/I/pmpaddr42.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr42 long_name: PMP Address 42 address: 0x3DA -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr43.yaml b/arch/csr/I/pmpaddr43.yaml index ce6e03f271..91b1812bcf 100644 --- a/arch/csr/I/pmpaddr43.yaml +++ b/arch/csr/I/pmpaddr43.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr43 long_name: PMP Address 43 address: 0x3DB -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr44.yaml b/arch/csr/I/pmpaddr44.yaml index f5a4f2c419..5d0cdfca6f 100644 --- a/arch/csr/I/pmpaddr44.yaml +++ b/arch/csr/I/pmpaddr44.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr44 long_name: PMP Address 44 address: 0x3DC -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr45.yaml b/arch/csr/I/pmpaddr45.yaml index 5cda5b7e88..18e02b28cd 100644 --- a/arch/csr/I/pmpaddr45.yaml +++ b/arch/csr/I/pmpaddr45.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr45 long_name: PMP Address 45 address: 0x3DD -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr46.yaml b/arch/csr/I/pmpaddr46.yaml index 78d9edd254..950b7b2b89 100644 --- a/arch/csr/I/pmpaddr46.yaml +++ b/arch/csr/I/pmpaddr46.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr46 long_name: PMP Address 46 address: 0x3DE -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr47.yaml b/arch/csr/I/pmpaddr47.yaml index 4251f90446..fb6a5f4222 100644 --- a/arch/csr/I/pmpaddr47.yaml +++ b/arch/csr/I/pmpaddr47.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr47 long_name: PMP Address 47 address: 0x3DF -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr48.yaml b/arch/csr/I/pmpaddr48.yaml index 61fa755574..9eba2608ad 100644 --- a/arch/csr/I/pmpaddr48.yaml +++ b/arch/csr/I/pmpaddr48.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr48 long_name: PMP Address 48 address: 0x3E0 -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr49.yaml b/arch/csr/I/pmpaddr49.yaml index 1685f45198..26cb239966 100644 --- a/arch/csr/I/pmpaddr49.yaml +++ b/arch/csr/I/pmpaddr49.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr49 long_name: PMP Address 49 address: 0x3E1 -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr5.yaml b/arch/csr/I/pmpaddr5.yaml index df64c18ba2..8a73ce45e6 100644 --- a/arch/csr/I/pmpaddr5.yaml +++ b/arch/csr/I/pmpaddr5.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr5 long_name: PMP Address 5 address: 0x3B5 -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr50.yaml b/arch/csr/I/pmpaddr50.yaml index 88d4193b8b..69aff1deca 100644 --- a/arch/csr/I/pmpaddr50.yaml +++ b/arch/csr/I/pmpaddr50.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr50 long_name: PMP Address 50 address: 0x3E2 -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr51.yaml b/arch/csr/I/pmpaddr51.yaml index 17c496f698..d5d6464f49 100644 --- a/arch/csr/I/pmpaddr51.yaml +++ b/arch/csr/I/pmpaddr51.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr51 long_name: PMP Address 51 address: 0x3E3 -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr52.yaml b/arch/csr/I/pmpaddr52.yaml index 51571410ea..49ace51ac0 100644 --- a/arch/csr/I/pmpaddr52.yaml +++ b/arch/csr/I/pmpaddr52.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr52 long_name: PMP Address 52 address: 0x3E4 -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr53.yaml b/arch/csr/I/pmpaddr53.yaml index 95bf8b6856..222efed3b3 100644 --- a/arch/csr/I/pmpaddr53.yaml +++ b/arch/csr/I/pmpaddr53.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr53 long_name: PMP Address 53 address: 0x3E5 -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr54.yaml b/arch/csr/I/pmpaddr54.yaml index 4fd59184b8..6f7e7677d5 100644 --- a/arch/csr/I/pmpaddr54.yaml +++ b/arch/csr/I/pmpaddr54.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr54 long_name: PMP Address 54 address: 0x3E6 -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr55.yaml b/arch/csr/I/pmpaddr55.yaml index 02d42b187b..0f9d5a5063 100644 --- a/arch/csr/I/pmpaddr55.yaml +++ b/arch/csr/I/pmpaddr55.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr55 long_name: PMP Address 55 address: 0x3E7 -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr56.yaml b/arch/csr/I/pmpaddr56.yaml index 61a7d79c37..4ca1bd3e55 100644 --- a/arch/csr/I/pmpaddr56.yaml +++ b/arch/csr/I/pmpaddr56.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr56 long_name: PMP Address 56 address: 0x3E8 -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr57.yaml b/arch/csr/I/pmpaddr57.yaml index 3161a4f60f..bde0f738bf 100644 --- a/arch/csr/I/pmpaddr57.yaml +++ b/arch/csr/I/pmpaddr57.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr57 long_name: PMP Address 57 address: 0x3E9 -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr58.yaml b/arch/csr/I/pmpaddr58.yaml index f7809698e9..6fa1aa32e5 100644 --- a/arch/csr/I/pmpaddr58.yaml +++ b/arch/csr/I/pmpaddr58.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr58 long_name: PMP Address 58 address: 0x3EA -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr59.yaml b/arch/csr/I/pmpaddr59.yaml index 1392abc21d..794787cfd1 100644 --- a/arch/csr/I/pmpaddr59.yaml +++ b/arch/csr/I/pmpaddr59.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr59 long_name: PMP Address 59 address: 0x3EB -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr6.yaml b/arch/csr/I/pmpaddr6.yaml index ed81dba357..28733415e1 100644 --- a/arch/csr/I/pmpaddr6.yaml +++ b/arch/csr/I/pmpaddr6.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr6 long_name: PMP Address 6 address: 0x3B6 -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr60.yaml b/arch/csr/I/pmpaddr60.yaml index 021bd23a7d..2932496683 100644 --- a/arch/csr/I/pmpaddr60.yaml +++ b/arch/csr/I/pmpaddr60.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr60 long_name: PMP Address 60 address: 0x3EC -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr61.yaml b/arch/csr/I/pmpaddr61.yaml index ca3ed5cabf..9570264235 100644 --- a/arch/csr/I/pmpaddr61.yaml +++ b/arch/csr/I/pmpaddr61.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr61 long_name: PMP Address 61 address: 0x3ED -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr62.yaml b/arch/csr/I/pmpaddr62.yaml index 961bd3ad06..0ae068f5d1 100644 --- a/arch/csr/I/pmpaddr62.yaml +++ b/arch/csr/I/pmpaddr62.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr62 long_name: PMP Address 62 address: 0x3EE -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr63.yaml b/arch/csr/I/pmpaddr63.yaml index 8837c0af8c..d448de1db1 100644 --- a/arch/csr/I/pmpaddr63.yaml +++ b/arch/csr/I/pmpaddr63.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr63 long_name: PMP Address 63 address: 0x3EF -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr7.yaml b/arch/csr/I/pmpaddr7.yaml index c9774eba35..710c597570 100644 --- a/arch/csr/I/pmpaddr7.yaml +++ b/arch/csr/I/pmpaddr7.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr7 long_name: PMP Address 7 address: 0x3B7 -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr8.yaml b/arch/csr/I/pmpaddr8.yaml index c589f7cfdc..e6807b1669 100644 --- a/arch/csr/I/pmpaddr8.yaml +++ b/arch/csr/I/pmpaddr8.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr8 long_name: PMP Address 8 address: 0x3B8 -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpaddr9.yaml b/arch/csr/I/pmpaddr9.yaml index 0510c298be..5cefea0afd 100644 --- a/arch/csr/I/pmpaddr9.yaml +++ b/arch/csr/I/pmpaddr9.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpaddr9 long_name: PMP Address 9 address: 0x3B9 -writeable: true priv_mode: M length: MXLEN description: PMP entry address diff --git a/arch/csr/I/pmpcfg0.yaml b/arch/csr/I/pmpcfg0.yaml index 4d94e07d16..2630c3ba38 100644 --- a/arch/csr/I/pmpcfg0.yaml +++ b/arch/csr/I/pmpcfg0.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpcfg0 long_name: PMP Configuration Register 0 address: 0x3A0 -writeable: true priv_mode: M length: MXLEN description: PMP entry configuration diff --git a/arch/csr/I/pmpcfg1.yaml b/arch/csr/I/pmpcfg1.yaml index 1a19e04104..317183e198 100644 --- a/arch/csr/I/pmpcfg1.yaml +++ b/arch/csr/I/pmpcfg1.yaml @@ -8,7 +8,6 @@ name: pmpcfg1 base: 32 # odd numbered pmpcfg registers do not exist in RV64 long_name: PMP Configuration Register 1 address: 0x3A1 -writeable: true priv_mode: M length: MXLEN description: PMP entry configuration diff --git a/arch/csr/I/pmpcfg10.yaml b/arch/csr/I/pmpcfg10.yaml index 0731ecf874..b0a9f613ff 100644 --- a/arch/csr/I/pmpcfg10.yaml +++ b/arch/csr/I/pmpcfg10.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpcfg10 long_name: PMP Configuration Register 10 address: 0x3AA -writeable: true priv_mode: M length: MXLEN description: PMP entry configuration diff --git a/arch/csr/I/pmpcfg11.yaml b/arch/csr/I/pmpcfg11.yaml index 422208ef11..c865e0d5e6 100644 --- a/arch/csr/I/pmpcfg11.yaml +++ b/arch/csr/I/pmpcfg11.yaml @@ -8,7 +8,6 @@ name: pmpcfg11 base: 32 # odd numbered pmpcfg registers do not exist in RV64 long_name: PMP Configuration Register 11 address: 0x3AB -writeable: true priv_mode: M length: MXLEN description: PMP entry configuration diff --git a/arch/csr/I/pmpcfg12.yaml b/arch/csr/I/pmpcfg12.yaml index 407a3573e5..7943b623ab 100644 --- a/arch/csr/I/pmpcfg12.yaml +++ b/arch/csr/I/pmpcfg12.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpcfg12 long_name: PMP Configuration Register 12 address: 0x3AC -writeable: true priv_mode: M length: MXLEN description: PMP entry configuration diff --git a/arch/csr/I/pmpcfg13.yaml b/arch/csr/I/pmpcfg13.yaml index f000e9258a..770fa37e19 100644 --- a/arch/csr/I/pmpcfg13.yaml +++ b/arch/csr/I/pmpcfg13.yaml @@ -8,7 +8,6 @@ name: pmpcfg13 base: 32 # odd numbered pmpcfg registers do not exist in RV64 long_name: PMP Configuration Register 13 address: 0x3AD -writeable: true priv_mode: M length: MXLEN description: PMP entry configuration diff --git a/arch/csr/I/pmpcfg14.yaml b/arch/csr/I/pmpcfg14.yaml index 30242a1c27..062513daa8 100644 --- a/arch/csr/I/pmpcfg14.yaml +++ b/arch/csr/I/pmpcfg14.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpcfg14 long_name: PMP Configuration Register 14 address: 0x3AE -writeable: true priv_mode: M length: MXLEN description: PMP entry configuration diff --git a/arch/csr/I/pmpcfg15.yaml b/arch/csr/I/pmpcfg15.yaml index 2f8b457738..942828b3a1 100644 --- a/arch/csr/I/pmpcfg15.yaml +++ b/arch/csr/I/pmpcfg15.yaml @@ -8,7 +8,6 @@ name: pmpcfg15 base: 32 # odd numbered pmpcfg registers do not exist in RV64 long_name: PMP Configuration Register 15 address: 0x3AF -writeable: true priv_mode: M length: MXLEN description: PMP entry configuration diff --git a/arch/csr/I/pmpcfg2.yaml b/arch/csr/I/pmpcfg2.yaml index 9256cb542b..771dceccbe 100644 --- a/arch/csr/I/pmpcfg2.yaml +++ b/arch/csr/I/pmpcfg2.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpcfg2 long_name: PMP Configuration Register 2 address: 0x3A2 -writeable: true priv_mode: M length: MXLEN description: PMP entry configuration diff --git a/arch/csr/I/pmpcfg3.yaml b/arch/csr/I/pmpcfg3.yaml index 1faafdbdb6..7c2ab8989f 100644 --- a/arch/csr/I/pmpcfg3.yaml +++ b/arch/csr/I/pmpcfg3.yaml @@ -8,7 +8,6 @@ name: pmpcfg3 base: 32 # odd numbered pmpcfg registers do not exist in RV64 long_name: PMP Configuration Register 3 address: 0x3A3 -writeable: true priv_mode: M length: MXLEN description: PMP entry configuration diff --git a/arch/csr/I/pmpcfg4.yaml b/arch/csr/I/pmpcfg4.yaml index c27eccf91c..7079c73d6d 100644 --- a/arch/csr/I/pmpcfg4.yaml +++ b/arch/csr/I/pmpcfg4.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpcfg4 long_name: PMP Configuration Register 4 address: 0x3A4 -writeable: true priv_mode: M length: MXLEN description: PMP entry configuration diff --git a/arch/csr/I/pmpcfg5.yaml b/arch/csr/I/pmpcfg5.yaml index 4695225a77..abd86000c7 100644 --- a/arch/csr/I/pmpcfg5.yaml +++ b/arch/csr/I/pmpcfg5.yaml @@ -8,7 +8,6 @@ name: pmpcfg5 base: 32 # odd numbered pmpcfg registers do not exist in RV64 long_name: PMP Configuration Register 5 address: 0x3A5 -writeable: true priv_mode: M length: MXLEN description: PMP entry configuration diff --git a/arch/csr/I/pmpcfg6.yaml b/arch/csr/I/pmpcfg6.yaml index d252e01490..74690b12cf 100644 --- a/arch/csr/I/pmpcfg6.yaml +++ b/arch/csr/I/pmpcfg6.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpcfg6 long_name: PMP Configuration Register 6 address: 0x3A6 -writeable: true priv_mode: M length: MXLEN description: PMP entry configuration diff --git a/arch/csr/I/pmpcfg7.yaml b/arch/csr/I/pmpcfg7.yaml index 9c7fa84349..fcfbd78e37 100644 --- a/arch/csr/I/pmpcfg7.yaml +++ b/arch/csr/I/pmpcfg7.yaml @@ -8,7 +8,6 @@ name: pmpcfg7 base: 32 # odd numbered pmpcfg registers do not exist in RV64 long_name: PMP Configuration Register 7 address: 0x3A7 -writeable: true priv_mode: M length: MXLEN description: PMP entry configuration diff --git a/arch/csr/I/pmpcfg8.yaml b/arch/csr/I/pmpcfg8.yaml index c35ed68b9b..79b006f5e9 100644 --- a/arch/csr/I/pmpcfg8.yaml +++ b/arch/csr/I/pmpcfg8.yaml @@ -7,7 +7,6 @@ kind: csr name: pmpcfg8 long_name: PMP Configuration Register 8 address: 0x3A8 -writeable: true priv_mode: M length: MXLEN description: PMP entry configuration diff --git a/arch/csr/I/pmpcfg9.yaml b/arch/csr/I/pmpcfg9.yaml index 902d358ba9..ec8211763d 100644 --- a/arch/csr/I/pmpcfg9.yaml +++ b/arch/csr/I/pmpcfg9.yaml @@ -8,7 +8,6 @@ name: pmpcfg9 base: 32 # odd numbered pmpcfg registers do not exist in RV64 long_name: PMP Configuration Register 9 address: 0x3A9 -writeable: true priv_mode: M length: MXLEN description: PMP entry configuration diff --git a/arch/csr/S/scounteren.yaml b/arch/csr/S/scounteren.yaml index 7548c61d15..1079620219 100644 --- a/arch/csr/S/scounteren.yaml +++ b/arch/csr/S/scounteren.yaml @@ -6,7 +6,6 @@ kind: csr name: scounteren long_name: Supervisor Counter Enable address: 0x106 -writeable: true priv_mode: S length: 32 description: | diff --git a/arch/csr/Zicntr/mcountinhibit.yaml b/arch/csr/Zicntr/mcountinhibit.yaml index 591396f95f..1a06640b7e 100644 --- a/arch/csr/Zicntr/mcountinhibit.yaml +++ b/arch/csr/Zicntr/mcountinhibit.yaml @@ -6,7 +6,6 @@ kind: csr name: mcountinhibit long_name: Machine Counter Inhibit address: 0x320 -writeable: true priv_mode: M length: 32 description: | diff --git a/arch/csr/Zihpm/hpmcounter10.yaml b/arch/csr/Zihpm/hpmcounter10.yaml index 37d084dd35..40b6fbdbcc 100644 --- a/arch/csr/Zihpm/hpmcounter10.yaml +++ b/arch/csr/Zihpm/hpmcounter10.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter10 long_name: User-mode Hardware Performance Counter 7 address: 0xC0A -writeable: false description: | Alias for M-mode CSR `mhpmcounter10`. diff --git a/arch/csr/Zihpm/hpmcounter10h.yaml b/arch/csr/Zihpm/hpmcounter10h.yaml index 6aaab8acd3..8c27418868 100644 --- a/arch/csr/Zihpm/hpmcounter10h.yaml +++ b/arch/csr/Zihpm/hpmcounter10h.yaml @@ -7,7 +7,7 @@ kind: csr name: hpmcounter10h long_name: User-mode Hardware Performance Counter 7, high half address: 0xC8A -writeable: false +base: 32 description: | Alias for M-mode CSR `mhpmcounter10h`. @@ -31,7 +31,7 @@ definedBy: Sscofpmf fields: COUNT: location: 31-0 - alias: mhpmcounter10h + alias: mhpmcounter10h.COUNT[63:32] description: Alias of `mhpmcounter10h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/Zihpm/hpmcounter11.yaml b/arch/csr/Zihpm/hpmcounter11.yaml index d3242a03ff..1217cc8161 100644 --- a/arch/csr/Zihpm/hpmcounter11.yaml +++ b/arch/csr/Zihpm/hpmcounter11.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter11 long_name: User-mode Hardware Performance Counter 8 address: 0xC0B -writeable: false description: | Alias for M-mode CSR `mhpmcounter11`. diff --git a/arch/csr/Zihpm/hpmcounter11h.yaml b/arch/csr/Zihpm/hpmcounter11h.yaml index d6e69e83e6..e92df5366a 100644 --- a/arch/csr/Zihpm/hpmcounter11h.yaml +++ b/arch/csr/Zihpm/hpmcounter11h.yaml @@ -7,7 +7,7 @@ kind: csr name: hpmcounter11h long_name: User-mode Hardware Performance Counter 8, high half address: 0xC8B -writeable: false +base: 32 description: | Alias for M-mode CSR `mhpmcounter11h`. @@ -31,7 +31,7 @@ definedBy: Sscofpmf fields: COUNT: location: 31-0 - alias: mhpmcounter11h + alias: mhpmcounter11h.COUNT[63:32] description: Alias of `mhpmcounter11h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/Zihpm/hpmcounter12.yaml b/arch/csr/Zihpm/hpmcounter12.yaml index 29c1cc3d60..f8f296a581 100644 --- a/arch/csr/Zihpm/hpmcounter12.yaml +++ b/arch/csr/Zihpm/hpmcounter12.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter12 long_name: User-mode Hardware Performance Counter 9 address: 0xC0C -writeable: false description: | Alias for M-mode CSR `mhpmcounter12`. diff --git a/arch/csr/Zihpm/hpmcounter12h.yaml b/arch/csr/Zihpm/hpmcounter12h.yaml index f9eebe0b67..97aabcb585 100644 --- a/arch/csr/Zihpm/hpmcounter12h.yaml +++ b/arch/csr/Zihpm/hpmcounter12h.yaml @@ -7,7 +7,7 @@ kind: csr name: hpmcounter12h long_name: User-mode Hardware Performance Counter 9, high half address: 0xC8C -writeable: false +base: 32 description: | Alias for M-mode CSR `mhpmcounter12h`. @@ -31,7 +31,7 @@ definedBy: Sscofpmf fields: COUNT: location: 31-0 - alias: mhpmcounter12h + alias: mhpmcounter12h.COUNT[63:32] description: Alias of `mhpmcounter12h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/Zihpm/hpmcounter13.yaml b/arch/csr/Zihpm/hpmcounter13.yaml index 62fb683501..8713f1e88b 100644 --- a/arch/csr/Zihpm/hpmcounter13.yaml +++ b/arch/csr/Zihpm/hpmcounter13.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter13 long_name: User-mode Hardware Performance Counter 10 address: 0xC0D -writeable: false description: | Alias for M-mode CSR `mhpmcounter13`. diff --git a/arch/csr/Zihpm/hpmcounter13h.yaml b/arch/csr/Zihpm/hpmcounter13h.yaml index 97cd017246..f9da99fee4 100644 --- a/arch/csr/Zihpm/hpmcounter13h.yaml +++ b/arch/csr/Zihpm/hpmcounter13h.yaml @@ -7,7 +7,7 @@ kind: csr name: hpmcounter13h long_name: User-mode Hardware Performance Counter 10, high half address: 0xC8D -writeable: false +base: 32 description: | Alias for M-mode CSR `mhpmcounter13h`. @@ -31,7 +31,7 @@ definedBy: Sscofpmf fields: COUNT: location: 31-0 - alias: mhpmcounter13h + alias: mhpmcounter13h.COUNT[63:32] description: Alias of `mhpmcounter13h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/Zihpm/hpmcounter14.yaml b/arch/csr/Zihpm/hpmcounter14.yaml index ebc3e0b49f..47303cbb4e 100644 --- a/arch/csr/Zihpm/hpmcounter14.yaml +++ b/arch/csr/Zihpm/hpmcounter14.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter14 long_name: User-mode Hardware Performance Counter 11 address: 0xC0E -writeable: false description: | Alias for M-mode CSR `mhpmcounter14`. diff --git a/arch/csr/Zihpm/hpmcounter14h.yaml b/arch/csr/Zihpm/hpmcounter14h.yaml index 19c9874442..e9c98969f7 100644 --- a/arch/csr/Zihpm/hpmcounter14h.yaml +++ b/arch/csr/Zihpm/hpmcounter14h.yaml @@ -7,7 +7,7 @@ kind: csr name: hpmcounter14h long_name: User-mode Hardware Performance Counter 11, high half address: 0xC8E -writeable: false +base: 32 description: | Alias for M-mode CSR `mhpmcounter14h`. @@ -31,7 +31,7 @@ definedBy: Sscofpmf fields: COUNT: location: 31-0 - alias: mhpmcounter14h + alias: mhpmcounter14h.COUNT[63:32] description: Alias of `mhpmcounter14h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/Zihpm/hpmcounter15.yaml b/arch/csr/Zihpm/hpmcounter15.yaml index 13bcd9b8e1..a18732b248 100644 --- a/arch/csr/Zihpm/hpmcounter15.yaml +++ b/arch/csr/Zihpm/hpmcounter15.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter15 long_name: User-mode Hardware Performance Counter 12 address: 0xC0F -writeable: false description: | Alias for M-mode CSR `mhpmcounter15`. diff --git a/arch/csr/Zihpm/hpmcounter15h.yaml b/arch/csr/Zihpm/hpmcounter15h.yaml index f1fbe20d92..d584056c73 100644 --- a/arch/csr/Zihpm/hpmcounter15h.yaml +++ b/arch/csr/Zihpm/hpmcounter15h.yaml @@ -7,7 +7,7 @@ kind: csr name: hpmcounter15h long_name: User-mode Hardware Performance Counter 12, high half address: 0xC8F -writeable: false +base: 32 description: | Alias for M-mode CSR `mhpmcounter15h`. @@ -31,7 +31,7 @@ definedBy: Sscofpmf fields: COUNT: location: 31-0 - alias: mhpmcounter15h + alias: mhpmcounter15h.COUNT[63:32] description: Alias of `mhpmcounter15h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/Zihpm/hpmcounter16.yaml b/arch/csr/Zihpm/hpmcounter16.yaml index 748b70a0b1..61e454230c 100644 --- a/arch/csr/Zihpm/hpmcounter16.yaml +++ b/arch/csr/Zihpm/hpmcounter16.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter16 long_name: User-mode Hardware Performance Counter 13 address: 0xC10 -writeable: false description: | Alias for M-mode CSR `mhpmcounter16`. diff --git a/arch/csr/Zihpm/hpmcounter16h.yaml b/arch/csr/Zihpm/hpmcounter16h.yaml index 48da2da65c..ba33b09e5e 100644 --- a/arch/csr/Zihpm/hpmcounter16h.yaml +++ b/arch/csr/Zihpm/hpmcounter16h.yaml @@ -7,7 +7,7 @@ kind: csr name: hpmcounter16h long_name: User-mode Hardware Performance Counter 13, high half address: 0xC90 -writeable: false +base: 32 description: | Alias for M-mode CSR `mhpmcounter16h`. @@ -31,7 +31,7 @@ definedBy: Sscofpmf fields: COUNT: location: 31-0 - alias: mhpmcounter16h + alias: mhpmcounter16h.COUNT[63:32] description: Alias of `mhpmcounter16h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/Zihpm/hpmcounter17.yaml b/arch/csr/Zihpm/hpmcounter17.yaml index 3cffcea98f..2d130ca5d2 100644 --- a/arch/csr/Zihpm/hpmcounter17.yaml +++ b/arch/csr/Zihpm/hpmcounter17.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter17 long_name: User-mode Hardware Performance Counter 14 address: 0xC11 -writeable: false description: | Alias for M-mode CSR `mhpmcounter17`. diff --git a/arch/csr/Zihpm/hpmcounter17h.yaml b/arch/csr/Zihpm/hpmcounter17h.yaml index f0fea0a746..4d4b83f564 100644 --- a/arch/csr/Zihpm/hpmcounter17h.yaml +++ b/arch/csr/Zihpm/hpmcounter17h.yaml @@ -7,7 +7,7 @@ kind: csr name: hpmcounter17h long_name: User-mode Hardware Performance Counter 14, high half address: 0xC91 -writeable: false +base: 32 description: | Alias for M-mode CSR `mhpmcounter17h`. @@ -31,7 +31,7 @@ definedBy: Sscofpmf fields: COUNT: location: 31-0 - alias: mhpmcounter17h + alias: mhpmcounter17h.COUNT[63:32] description: Alias of `mhpmcounter17h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/Zihpm/hpmcounter18.yaml b/arch/csr/Zihpm/hpmcounter18.yaml index f1928ae231..b115107009 100644 --- a/arch/csr/Zihpm/hpmcounter18.yaml +++ b/arch/csr/Zihpm/hpmcounter18.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter18 long_name: User-mode Hardware Performance Counter 15 address: 0xC12 -writeable: false description: | Alias for M-mode CSR `mhpmcounter18`. diff --git a/arch/csr/Zihpm/hpmcounter18h.yaml b/arch/csr/Zihpm/hpmcounter18h.yaml index e654825dab..2cd6676a39 100644 --- a/arch/csr/Zihpm/hpmcounter18h.yaml +++ b/arch/csr/Zihpm/hpmcounter18h.yaml @@ -7,7 +7,7 @@ kind: csr name: hpmcounter18h long_name: User-mode Hardware Performance Counter 15, high half address: 0xC92 -writeable: false +base: 32 description: | Alias for M-mode CSR `mhpmcounter18h`. @@ -31,7 +31,7 @@ definedBy: Sscofpmf fields: COUNT: location: 31-0 - alias: mhpmcounter18h + alias: mhpmcounter18h.COUNT[63:32] description: Alias of `mhpmcounter18h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/Zihpm/hpmcounter19.yaml b/arch/csr/Zihpm/hpmcounter19.yaml index 86858b8aa6..12a99ea82e 100644 --- a/arch/csr/Zihpm/hpmcounter19.yaml +++ b/arch/csr/Zihpm/hpmcounter19.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter19 long_name: User-mode Hardware Performance Counter 16 address: 0xC13 -writeable: false description: | Alias for M-mode CSR `mhpmcounter19`. diff --git a/arch/csr/Zihpm/hpmcounter19h.yaml b/arch/csr/Zihpm/hpmcounter19h.yaml index d563ff4aae..59e0707f57 100644 --- a/arch/csr/Zihpm/hpmcounter19h.yaml +++ b/arch/csr/Zihpm/hpmcounter19h.yaml @@ -7,7 +7,7 @@ kind: csr name: hpmcounter19h long_name: User-mode Hardware Performance Counter 16, high half address: 0xC93 -writeable: false +base: 32 description: | Alias for M-mode CSR `mhpmcounter19h`. @@ -31,7 +31,7 @@ definedBy: Sscofpmf fields: COUNT: location: 31-0 - alias: mhpmcounter19h + alias: mhpmcounter19h.COUNT[63:32] description: Alias of `mhpmcounter19h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/Zihpm/hpmcounter20.yaml b/arch/csr/Zihpm/hpmcounter20.yaml index b3b588d6ed..a8a406d7b1 100644 --- a/arch/csr/Zihpm/hpmcounter20.yaml +++ b/arch/csr/Zihpm/hpmcounter20.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter20 long_name: User-mode Hardware Performance Counter 17 address: 0xC14 -writeable: false description: | Alias for M-mode CSR `mhpmcounter20`. diff --git a/arch/csr/Zihpm/hpmcounter20h.yaml b/arch/csr/Zihpm/hpmcounter20h.yaml index 6354628b61..e819e7a046 100644 --- a/arch/csr/Zihpm/hpmcounter20h.yaml +++ b/arch/csr/Zihpm/hpmcounter20h.yaml @@ -7,7 +7,7 @@ kind: csr name: hpmcounter20h long_name: User-mode Hardware Performance Counter 17, high half address: 0xC94 -writeable: false +base: 32 description: | Alias for M-mode CSR `mhpmcounter20h`. @@ -31,7 +31,7 @@ definedBy: Sscofpmf fields: COUNT: location: 31-0 - alias: mhpmcounter20h + alias: mhpmcounter20h.COUNT[63:32] description: Alias of `mhpmcounter20h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/Zihpm/hpmcounter21.yaml b/arch/csr/Zihpm/hpmcounter21.yaml index 9c29fd1fd2..3ce7cb84a2 100644 --- a/arch/csr/Zihpm/hpmcounter21.yaml +++ b/arch/csr/Zihpm/hpmcounter21.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter21 long_name: User-mode Hardware Performance Counter 18 address: 0xC15 -writeable: false description: | Alias for M-mode CSR `mhpmcounter21`. diff --git a/arch/csr/Zihpm/hpmcounter21h.yaml b/arch/csr/Zihpm/hpmcounter21h.yaml index a6c296ccb8..51dcd09706 100644 --- a/arch/csr/Zihpm/hpmcounter21h.yaml +++ b/arch/csr/Zihpm/hpmcounter21h.yaml @@ -7,7 +7,7 @@ kind: csr name: hpmcounter21h long_name: User-mode Hardware Performance Counter 18, high half address: 0xC95 -writeable: false +base: 32 description: | Alias for M-mode CSR `mhpmcounter21h`. @@ -31,7 +31,7 @@ definedBy: Sscofpmf fields: COUNT: location: 31-0 - alias: mhpmcounter21h + alias: mhpmcounter21h.COUNT[63:32] description: Alias of `mhpmcounter21h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/Zihpm/hpmcounter22.yaml b/arch/csr/Zihpm/hpmcounter22.yaml index e8021fee46..7943981fdd 100644 --- a/arch/csr/Zihpm/hpmcounter22.yaml +++ b/arch/csr/Zihpm/hpmcounter22.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter22 long_name: User-mode Hardware Performance Counter 19 address: 0xC16 -writeable: false description: | Alias for M-mode CSR `mhpmcounter22`. diff --git a/arch/csr/Zihpm/hpmcounter22h.yaml b/arch/csr/Zihpm/hpmcounter22h.yaml index b7e1d1a712..5c2c51dce3 100644 --- a/arch/csr/Zihpm/hpmcounter22h.yaml +++ b/arch/csr/Zihpm/hpmcounter22h.yaml @@ -7,7 +7,7 @@ kind: csr name: hpmcounter22h long_name: User-mode Hardware Performance Counter 19, high half address: 0xC96 -writeable: false +base: 32 description: | Alias for M-mode CSR `mhpmcounter22h`. @@ -31,7 +31,7 @@ definedBy: Sscofpmf fields: COUNT: location: 31-0 - alias: mhpmcounter22h + alias: mhpmcounter22h.COUNT[63:32] description: Alias of `mhpmcounter22h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/Zihpm/hpmcounter23.yaml b/arch/csr/Zihpm/hpmcounter23.yaml index c6718ff464..fc22bd72a5 100644 --- a/arch/csr/Zihpm/hpmcounter23.yaml +++ b/arch/csr/Zihpm/hpmcounter23.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter23 long_name: User-mode Hardware Performance Counter 20 address: 0xC17 -writeable: false description: | Alias for M-mode CSR `mhpmcounter23`. diff --git a/arch/csr/Zihpm/hpmcounter23h.yaml b/arch/csr/Zihpm/hpmcounter23h.yaml index 96916ddad7..3c791da8b5 100644 --- a/arch/csr/Zihpm/hpmcounter23h.yaml +++ b/arch/csr/Zihpm/hpmcounter23h.yaml @@ -7,7 +7,7 @@ kind: csr name: hpmcounter23h long_name: User-mode Hardware Performance Counter 20, high half address: 0xC97 -writeable: false +base: 32 description: | Alias for M-mode CSR `mhpmcounter23h`. @@ -31,7 +31,7 @@ definedBy: Sscofpmf fields: COUNT: location: 31-0 - alias: mhpmcounter23h + alias: mhpmcounter23h.COUNT[63:32] description: Alias of `mhpmcounter23h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/Zihpm/hpmcounter24.yaml b/arch/csr/Zihpm/hpmcounter24.yaml index 414f4e11d5..4f392aaa5e 100644 --- a/arch/csr/Zihpm/hpmcounter24.yaml +++ b/arch/csr/Zihpm/hpmcounter24.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter24 long_name: User-mode Hardware Performance Counter 21 address: 0xC18 -writeable: false description: | Alias for M-mode CSR `mhpmcounter24`. diff --git a/arch/csr/Zihpm/hpmcounter24h.yaml b/arch/csr/Zihpm/hpmcounter24h.yaml index 0f7e457b24..1b46ec08dd 100644 --- a/arch/csr/Zihpm/hpmcounter24h.yaml +++ b/arch/csr/Zihpm/hpmcounter24h.yaml @@ -7,7 +7,7 @@ kind: csr name: hpmcounter24h long_name: User-mode Hardware Performance Counter 21, high half address: 0xC98 -writeable: false +base: 32 description: | Alias for M-mode CSR `mhpmcounter24h`. @@ -31,7 +31,7 @@ definedBy: Sscofpmf fields: COUNT: location: 31-0 - alias: mhpmcounter24h + alias: mhpmcounter24h.COUNT[63:32] description: Alias of `mhpmcounter24h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/Zihpm/hpmcounter25.yaml b/arch/csr/Zihpm/hpmcounter25.yaml index 5d37bceab2..3bcedc674d 100644 --- a/arch/csr/Zihpm/hpmcounter25.yaml +++ b/arch/csr/Zihpm/hpmcounter25.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter25 long_name: User-mode Hardware Performance Counter 22 address: 0xC19 -writeable: false description: | Alias for M-mode CSR `mhpmcounter25`. diff --git a/arch/csr/Zihpm/hpmcounter25h.yaml b/arch/csr/Zihpm/hpmcounter25h.yaml index 4890092420..35bde4eb49 100644 --- a/arch/csr/Zihpm/hpmcounter25h.yaml +++ b/arch/csr/Zihpm/hpmcounter25h.yaml @@ -7,7 +7,7 @@ kind: csr name: hpmcounter25h long_name: User-mode Hardware Performance Counter 22, high half address: 0xC99 -writeable: false +base: 32 description: | Alias for M-mode CSR `mhpmcounter25h`. @@ -31,7 +31,7 @@ definedBy: Sscofpmf fields: COUNT: location: 31-0 - alias: mhpmcounter25h + alias: mhpmcounter25h.COUNT[63:32] description: Alias of `mhpmcounter25h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/Zihpm/hpmcounter26.yaml b/arch/csr/Zihpm/hpmcounter26.yaml index b6248bdb54..1dee5e0c76 100644 --- a/arch/csr/Zihpm/hpmcounter26.yaml +++ b/arch/csr/Zihpm/hpmcounter26.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter26 long_name: User-mode Hardware Performance Counter 23 address: 0xC1A -writeable: false description: | Alias for M-mode CSR `mhpmcounter26`. diff --git a/arch/csr/Zihpm/hpmcounter26h.yaml b/arch/csr/Zihpm/hpmcounter26h.yaml index bf1212a974..338fc2c07d 100644 --- a/arch/csr/Zihpm/hpmcounter26h.yaml +++ b/arch/csr/Zihpm/hpmcounter26h.yaml @@ -7,7 +7,7 @@ kind: csr name: hpmcounter26h long_name: User-mode Hardware Performance Counter 23, high half address: 0xC9A -writeable: false +base: 32 description: | Alias for M-mode CSR `mhpmcounter26h`. @@ -31,7 +31,7 @@ definedBy: Sscofpmf fields: COUNT: location: 31-0 - alias: mhpmcounter26h + alias: mhpmcounter26h.COUNT[63:32] description: Alias of `mhpmcounter26h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/Zihpm/hpmcounter27.yaml b/arch/csr/Zihpm/hpmcounter27.yaml index 874827ee2d..694b4ee993 100644 --- a/arch/csr/Zihpm/hpmcounter27.yaml +++ b/arch/csr/Zihpm/hpmcounter27.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter27 long_name: User-mode Hardware Performance Counter 24 address: 0xC1B -writeable: false description: | Alias for M-mode CSR `mhpmcounter27`. diff --git a/arch/csr/Zihpm/hpmcounter27h.yaml b/arch/csr/Zihpm/hpmcounter27h.yaml index 0c91e441c2..323ebb22c6 100644 --- a/arch/csr/Zihpm/hpmcounter27h.yaml +++ b/arch/csr/Zihpm/hpmcounter27h.yaml @@ -7,7 +7,7 @@ kind: csr name: hpmcounter27h long_name: User-mode Hardware Performance Counter 24, high half address: 0xC9B -writeable: false +base: 32 description: | Alias for M-mode CSR `mhpmcounter27h`. @@ -31,7 +31,7 @@ definedBy: Sscofpmf fields: COUNT: location: 31-0 - alias: mhpmcounter27h + alias: mhpmcounter27h.COUNT[63:32] description: Alias of `mhpmcounter27h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/Zihpm/hpmcounter28.yaml b/arch/csr/Zihpm/hpmcounter28.yaml index 904ed48f58..be77b1867d 100644 --- a/arch/csr/Zihpm/hpmcounter28.yaml +++ b/arch/csr/Zihpm/hpmcounter28.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter28 long_name: User-mode Hardware Performance Counter 25 address: 0xC1C -writeable: false description: | Alias for M-mode CSR `mhpmcounter28`. diff --git a/arch/csr/Zihpm/hpmcounter28h.yaml b/arch/csr/Zihpm/hpmcounter28h.yaml index d8eaa40519..e3935c1ba5 100644 --- a/arch/csr/Zihpm/hpmcounter28h.yaml +++ b/arch/csr/Zihpm/hpmcounter28h.yaml @@ -7,7 +7,7 @@ kind: csr name: hpmcounter28h long_name: User-mode Hardware Performance Counter 25, high half address: 0xC9C -writeable: false +base: 32 description: | Alias for M-mode CSR `mhpmcounter28h`. @@ -31,7 +31,7 @@ definedBy: Sscofpmf fields: COUNT: location: 31-0 - alias: mhpmcounter28h + alias: mhpmcounter28h.COUNT[63:32] description: Alias of `mhpmcounter28h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/Zihpm/hpmcounter29.yaml b/arch/csr/Zihpm/hpmcounter29.yaml index d8aa7c1e61..df27482266 100644 --- a/arch/csr/Zihpm/hpmcounter29.yaml +++ b/arch/csr/Zihpm/hpmcounter29.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter29 long_name: User-mode Hardware Performance Counter 26 address: 0xC1D -writeable: false description: | Alias for M-mode CSR `mhpmcounter29`. diff --git a/arch/csr/Zihpm/hpmcounter29h.yaml b/arch/csr/Zihpm/hpmcounter29h.yaml index ec6bc39508..de92f4ba7b 100644 --- a/arch/csr/Zihpm/hpmcounter29h.yaml +++ b/arch/csr/Zihpm/hpmcounter29h.yaml @@ -7,7 +7,7 @@ kind: csr name: hpmcounter29h long_name: User-mode Hardware Performance Counter 26, high half address: 0xC9D -writeable: false +base: 32 description: | Alias for M-mode CSR `mhpmcounter29h`. @@ -31,7 +31,7 @@ definedBy: Sscofpmf fields: COUNT: location: 31-0 - alias: mhpmcounter29h + alias: mhpmcounter29h.COUNT[63:32] description: Alias of `mhpmcounter29h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/Zihpm/hpmcounter3.yaml b/arch/csr/Zihpm/hpmcounter3.yaml index ad81f77396..92c2bea3d8 100644 --- a/arch/csr/Zihpm/hpmcounter3.yaml +++ b/arch/csr/Zihpm/hpmcounter3.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter3 long_name: User-mode Hardware Performance Counter 0 address: 0xC03 -writeable: false description: | Alias for M-mode CSR `mhpmcounter3`. diff --git a/arch/csr/Zihpm/hpmcounter30.yaml b/arch/csr/Zihpm/hpmcounter30.yaml index 14e0f7c176..7428dbb693 100644 --- a/arch/csr/Zihpm/hpmcounter30.yaml +++ b/arch/csr/Zihpm/hpmcounter30.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter30 long_name: User-mode Hardware Performance Counter 27 address: 0xC1E -writeable: false description: | Alias for M-mode CSR `mhpmcounter30`. diff --git a/arch/csr/Zihpm/hpmcounter30h.yaml b/arch/csr/Zihpm/hpmcounter30h.yaml index d4c7d7045b..39a9b53e4e 100644 --- a/arch/csr/Zihpm/hpmcounter30h.yaml +++ b/arch/csr/Zihpm/hpmcounter30h.yaml @@ -7,7 +7,7 @@ kind: csr name: hpmcounter30h long_name: User-mode Hardware Performance Counter 27, high half address: 0xC9E -writeable: false +base: 32 description: | Alias for M-mode CSR `mhpmcounter30h`. @@ -31,7 +31,7 @@ definedBy: Sscofpmf fields: COUNT: location: 31-0 - alias: mhpmcounter30h + alias: mhpmcounter30h.COUNT[63:32] description: Alias of `mhpmcounter30h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/Zihpm/hpmcounter31.yaml b/arch/csr/Zihpm/hpmcounter31.yaml index 442ab2eaec..77f88b79f1 100644 --- a/arch/csr/Zihpm/hpmcounter31.yaml +++ b/arch/csr/Zihpm/hpmcounter31.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter31 long_name: User-mode Hardware Performance Counter 28 address: 0xC1F -writeable: false description: | Alias for M-mode CSR `mhpmcounter31`. diff --git a/arch/csr/Zihpm/hpmcounter31h.yaml b/arch/csr/Zihpm/hpmcounter31h.yaml index d255f7adc9..f9cb637033 100644 --- a/arch/csr/Zihpm/hpmcounter31h.yaml +++ b/arch/csr/Zihpm/hpmcounter31h.yaml @@ -7,7 +7,7 @@ kind: csr name: hpmcounter31h long_name: User-mode Hardware Performance Counter 28, high half address: 0xC9F -writeable: false +base: 32 description: | Alias for M-mode CSR `mhpmcounter31h`. @@ -31,7 +31,7 @@ definedBy: Sscofpmf fields: COUNT: location: 31-0 - alias: mhpmcounter31h + alias: mhpmcounter31h.COUNT[63:32] description: Alias of `mhpmcounter31h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/Zihpm/hpmcounter3h.yaml b/arch/csr/Zihpm/hpmcounter3h.yaml index 62fc116248..70f68937f2 100644 --- a/arch/csr/Zihpm/hpmcounter3h.yaml +++ b/arch/csr/Zihpm/hpmcounter3h.yaml @@ -7,7 +7,7 @@ kind: csr name: hpmcounter3h long_name: User-mode Hardware Performance Counter 0, high half address: 0xC83 -writeable: false +base: 32 description: | Alias for M-mode CSR `mhpmcounter3h`. @@ -31,7 +31,7 @@ definedBy: Sscofpmf fields: COUNT: location: 31-0 - alias: mhpmcounter3h + alias: mhpmcounter3h.COUNT[63:32] description: Alias of `mhpmcounter3h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/Zihpm/hpmcounter4.yaml b/arch/csr/Zihpm/hpmcounter4.yaml index 6d60345a48..e453b1739b 100644 --- a/arch/csr/Zihpm/hpmcounter4.yaml +++ b/arch/csr/Zihpm/hpmcounter4.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter4 long_name: User-mode Hardware Performance Counter 1 address: 0xC04 -writeable: false description: | Alias for M-mode CSR `mhpmcounter4`. diff --git a/arch/csr/Zihpm/hpmcounter4h.yaml b/arch/csr/Zihpm/hpmcounter4h.yaml index 373f1b53a8..08e24d5d9f 100644 --- a/arch/csr/Zihpm/hpmcounter4h.yaml +++ b/arch/csr/Zihpm/hpmcounter4h.yaml @@ -7,7 +7,7 @@ kind: csr name: hpmcounter4h long_name: User-mode Hardware Performance Counter 1, high half address: 0xC84 -writeable: false +base: 32 description: | Alias for M-mode CSR `mhpmcounter4h`. @@ -31,7 +31,7 @@ definedBy: Sscofpmf fields: COUNT: location: 31-0 - alias: mhpmcounter4h + alias: mhpmcounter4h.COUNT[63:32] description: Alias of `mhpmcounter4h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/Zihpm/hpmcounter5.yaml b/arch/csr/Zihpm/hpmcounter5.yaml index ad06be019d..6e9e0c801a 100644 --- a/arch/csr/Zihpm/hpmcounter5.yaml +++ b/arch/csr/Zihpm/hpmcounter5.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter5 long_name: User-mode Hardware Performance Counter 2 address: 0xC05 -writeable: false description: | Alias for M-mode CSR `mhpmcounter5`. diff --git a/arch/csr/Zihpm/hpmcounter5h.yaml b/arch/csr/Zihpm/hpmcounter5h.yaml index cb6fe11560..99d51b7b25 100644 --- a/arch/csr/Zihpm/hpmcounter5h.yaml +++ b/arch/csr/Zihpm/hpmcounter5h.yaml @@ -7,7 +7,7 @@ kind: csr name: hpmcounter5h long_name: User-mode Hardware Performance Counter 2, high half address: 0xC85 -writeable: false +base: 32 description: | Alias for M-mode CSR `mhpmcounter5h`. @@ -31,7 +31,7 @@ definedBy: Sscofpmf fields: COUNT: location: 31-0 - alias: mhpmcounter5h + alias: mhpmcounter5h.COUNT[63:32] description: Alias of `mhpmcounter5h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/Zihpm/hpmcounter6.yaml b/arch/csr/Zihpm/hpmcounter6.yaml index cf0470bcdc..128202fdb3 100644 --- a/arch/csr/Zihpm/hpmcounter6.yaml +++ b/arch/csr/Zihpm/hpmcounter6.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter6 long_name: User-mode Hardware Performance Counter 3 address: 0xC06 -writeable: false description: | Alias for M-mode CSR `mhpmcounter6`. diff --git a/arch/csr/Zihpm/hpmcounter6h.yaml b/arch/csr/Zihpm/hpmcounter6h.yaml index 568463b0ba..9d17286173 100644 --- a/arch/csr/Zihpm/hpmcounter6h.yaml +++ b/arch/csr/Zihpm/hpmcounter6h.yaml @@ -7,7 +7,7 @@ kind: csr name: hpmcounter6h long_name: User-mode Hardware Performance Counter 3, high half address: 0xC86 -writeable: false +base: 32 description: | Alias for M-mode CSR `mhpmcounter6h`. @@ -31,7 +31,7 @@ definedBy: Sscofpmf fields: COUNT: location: 31-0 - alias: mhpmcounter6h + alias: mhpmcounter6h.COUNT[63:32] description: Alias of `mhpmcounter6h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/Zihpm/hpmcounter7.yaml b/arch/csr/Zihpm/hpmcounter7.yaml index 98f87d5e70..c471a1df47 100644 --- a/arch/csr/Zihpm/hpmcounter7.yaml +++ b/arch/csr/Zihpm/hpmcounter7.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter7 long_name: User-mode Hardware Performance Counter 4 address: 0xC07 -writeable: false description: | Alias for M-mode CSR `mhpmcounter7`. diff --git a/arch/csr/Zihpm/hpmcounter7h.yaml b/arch/csr/Zihpm/hpmcounter7h.yaml index 5cb50e2469..97404a5411 100644 --- a/arch/csr/Zihpm/hpmcounter7h.yaml +++ b/arch/csr/Zihpm/hpmcounter7h.yaml @@ -7,7 +7,7 @@ kind: csr name: hpmcounter7h long_name: User-mode Hardware Performance Counter 4, high half address: 0xC87 -writeable: false +base: 32 description: | Alias for M-mode CSR `mhpmcounter7h`. @@ -31,7 +31,7 @@ definedBy: Sscofpmf fields: COUNT: location: 31-0 - alias: mhpmcounter7h + alias: mhpmcounter7h.COUNT[63:32] description: Alias of `mhpmcounter7h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/Zihpm/hpmcounter8.yaml b/arch/csr/Zihpm/hpmcounter8.yaml index f91910331a..a7c22a495c 100644 --- a/arch/csr/Zihpm/hpmcounter8.yaml +++ b/arch/csr/Zihpm/hpmcounter8.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter8 long_name: User-mode Hardware Performance Counter 5 address: 0xC08 -writeable: false description: | Alias for M-mode CSR `mhpmcounter8`. diff --git a/arch/csr/Zihpm/hpmcounter8h.yaml b/arch/csr/Zihpm/hpmcounter8h.yaml index d7e495a782..75baff05ba 100644 --- a/arch/csr/Zihpm/hpmcounter8h.yaml +++ b/arch/csr/Zihpm/hpmcounter8h.yaml @@ -7,7 +7,7 @@ kind: csr name: hpmcounter8h long_name: User-mode Hardware Performance Counter 5, high half address: 0xC88 -writeable: false +base: 32 description: | Alias for M-mode CSR `mhpmcounter8h`. @@ -31,7 +31,7 @@ definedBy: Sscofpmf fields: COUNT: location: 31-0 - alias: mhpmcounter8h + alias: mhpmcounter8h.COUNT[63:32] description: Alias of `mhpmcounter8h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/Zihpm/hpmcounter9.yaml b/arch/csr/Zihpm/hpmcounter9.yaml index 522740b419..09770fa7a6 100644 --- a/arch/csr/Zihpm/hpmcounter9.yaml +++ b/arch/csr/Zihpm/hpmcounter9.yaml @@ -7,7 +7,6 @@ kind: csr name: hpmcounter9 long_name: User-mode Hardware Performance Counter 6 address: 0xC09 -writeable: false description: | Alias for M-mode CSR `mhpmcounter9`. diff --git a/arch/csr/Zihpm/hpmcounter9h.yaml b/arch/csr/Zihpm/hpmcounter9h.yaml index 1e5fa00143..c0189fd158 100644 --- a/arch/csr/Zihpm/hpmcounter9h.yaml +++ b/arch/csr/Zihpm/hpmcounter9h.yaml @@ -7,7 +7,7 @@ kind: csr name: hpmcounter9h long_name: User-mode Hardware Performance Counter 6, high half address: 0xC89 -writeable: false +base: 32 description: | Alias for M-mode CSR `mhpmcounter9h`. @@ -31,7 +31,7 @@ definedBy: Sscofpmf fields: COUNT: location: 31-0 - alias: mhpmcounter9h + alias: mhpmcounter9h.COUNT[63:32] description: Alias of `mhpmcounter9h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/Zihpm/hpmcounterNh.layout b/arch/csr/Zihpm/hpmcounterNh.layout index 518202dc9a..b124937d7a 100644 --- a/arch/csr/Zihpm/hpmcounterNh.layout +++ b/arch/csr/Zihpm/hpmcounterNh.layout @@ -31,7 +31,7 @@ definedBy: Sscofpmf fields: COUNT: location: 31-0 - alias: mhpmcounter<%= hpm_num %>h + alias: mhpmcounter<%= hpm_num %>h.COUNT[63:32] description: Alias of `mhpmcounter<%= hpm_num %>h.COUNT`. type: RO-H reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/Zihpm/mhpmcounter10.yaml b/arch/csr/Zihpm/mhpmcounter10.yaml index 2cc562c1aa..8bbc5e1d9d 100644 --- a/arch/csr/Zihpm/mhpmcounter10.yaml +++ b/arch/csr/Zihpm/mhpmcounter10.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmcounter10 long_name: Machine Hardware Performance Counter 10 address: 0xB0A -writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter10h.yaml b/arch/csr/Zihpm/mhpmcounter10h.yaml index fb91bf2cfb..3bfbeb11e9 100644 --- a/arch/csr/Zihpm/mhpmcounter10h.yaml +++ b/arch/csr/Zihpm/mhpmcounter10h.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmcounter10h long_name: Machine Hardware Performance Counter 10, Upper half address: 0xB8A -writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter11.yaml b/arch/csr/Zihpm/mhpmcounter11.yaml index ff6fe28b99..0501702a38 100644 --- a/arch/csr/Zihpm/mhpmcounter11.yaml +++ b/arch/csr/Zihpm/mhpmcounter11.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmcounter11 long_name: Machine Hardware Performance Counter 11 address: 0xB0B -writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter11h.yaml b/arch/csr/Zihpm/mhpmcounter11h.yaml index 1850848841..53d1e8d13b 100644 --- a/arch/csr/Zihpm/mhpmcounter11h.yaml +++ b/arch/csr/Zihpm/mhpmcounter11h.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmcounter11h long_name: Machine Hardware Performance Counter 11, Upper half address: 0xB8B -writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter12.yaml b/arch/csr/Zihpm/mhpmcounter12.yaml index 00498cebf8..f0aceebd18 100644 --- a/arch/csr/Zihpm/mhpmcounter12.yaml +++ b/arch/csr/Zihpm/mhpmcounter12.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmcounter12 long_name: Machine Hardware Performance Counter 12 address: 0xB0C -writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter12h.yaml b/arch/csr/Zihpm/mhpmcounter12h.yaml index 2807ab87ef..0b94cfb176 100644 --- a/arch/csr/Zihpm/mhpmcounter12h.yaml +++ b/arch/csr/Zihpm/mhpmcounter12h.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmcounter12h long_name: Machine Hardware Performance Counter 12, Upper half address: 0xB8C -writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter13.yaml b/arch/csr/Zihpm/mhpmcounter13.yaml index a5f9e6bebd..10fc117dfd 100644 --- a/arch/csr/Zihpm/mhpmcounter13.yaml +++ b/arch/csr/Zihpm/mhpmcounter13.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmcounter13 long_name: Machine Hardware Performance Counter 13 address: 0xB0D -writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter13h.yaml b/arch/csr/Zihpm/mhpmcounter13h.yaml index c8b566b9c1..754fb34492 100644 --- a/arch/csr/Zihpm/mhpmcounter13h.yaml +++ b/arch/csr/Zihpm/mhpmcounter13h.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmcounter13h long_name: Machine Hardware Performance Counter 13, Upper half address: 0xB8D -writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter14.yaml b/arch/csr/Zihpm/mhpmcounter14.yaml index 2d22b686b4..2285c2cca4 100644 --- a/arch/csr/Zihpm/mhpmcounter14.yaml +++ b/arch/csr/Zihpm/mhpmcounter14.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmcounter14 long_name: Machine Hardware Performance Counter 14 address: 0xB0E -writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter14h.yaml b/arch/csr/Zihpm/mhpmcounter14h.yaml index 2e05420c2d..5f32a7c7bf 100644 --- a/arch/csr/Zihpm/mhpmcounter14h.yaml +++ b/arch/csr/Zihpm/mhpmcounter14h.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmcounter14h long_name: Machine Hardware Performance Counter 14, Upper half address: 0xB8E -writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter15.yaml b/arch/csr/Zihpm/mhpmcounter15.yaml index fd0a9edc4e..a487e21c5b 100644 --- a/arch/csr/Zihpm/mhpmcounter15.yaml +++ b/arch/csr/Zihpm/mhpmcounter15.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmcounter15 long_name: Machine Hardware Performance Counter 15 address: 0xB0F -writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter15h.yaml b/arch/csr/Zihpm/mhpmcounter15h.yaml index 19215effe6..21184c4cc9 100644 --- a/arch/csr/Zihpm/mhpmcounter15h.yaml +++ b/arch/csr/Zihpm/mhpmcounter15h.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmcounter15h long_name: Machine Hardware Performance Counter 15, Upper half address: 0xB8F -writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter16.yaml b/arch/csr/Zihpm/mhpmcounter16.yaml index 61c7aa24d6..9ff6a82635 100644 --- a/arch/csr/Zihpm/mhpmcounter16.yaml +++ b/arch/csr/Zihpm/mhpmcounter16.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmcounter16 long_name: Machine Hardware Performance Counter 16 address: 0xB10 -writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter16h.yaml b/arch/csr/Zihpm/mhpmcounter16h.yaml index 300d827e3a..d0b7ee88a5 100644 --- a/arch/csr/Zihpm/mhpmcounter16h.yaml +++ b/arch/csr/Zihpm/mhpmcounter16h.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmcounter16h long_name: Machine Hardware Performance Counter 16, Upper half address: 0xB90 -writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter17.yaml b/arch/csr/Zihpm/mhpmcounter17.yaml index da262b3c3f..6c30f92d62 100644 --- a/arch/csr/Zihpm/mhpmcounter17.yaml +++ b/arch/csr/Zihpm/mhpmcounter17.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmcounter17 long_name: Machine Hardware Performance Counter 17 address: 0xB11 -writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter17h.yaml b/arch/csr/Zihpm/mhpmcounter17h.yaml index 807157626e..14d6a52195 100644 --- a/arch/csr/Zihpm/mhpmcounter17h.yaml +++ b/arch/csr/Zihpm/mhpmcounter17h.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmcounter17h long_name: Machine Hardware Performance Counter 17, Upper half address: 0xB91 -writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter18.yaml b/arch/csr/Zihpm/mhpmcounter18.yaml index b03d08a6f2..02b6dcd4fc 100644 --- a/arch/csr/Zihpm/mhpmcounter18.yaml +++ b/arch/csr/Zihpm/mhpmcounter18.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmcounter18 long_name: Machine Hardware Performance Counter 18 address: 0xB12 -writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter18h.yaml b/arch/csr/Zihpm/mhpmcounter18h.yaml index a50a473f2c..3fc41ad052 100644 --- a/arch/csr/Zihpm/mhpmcounter18h.yaml +++ b/arch/csr/Zihpm/mhpmcounter18h.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmcounter18h long_name: Machine Hardware Performance Counter 18, Upper half address: 0xB92 -writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter19.yaml b/arch/csr/Zihpm/mhpmcounter19.yaml index 84d1292f21..0e45c395c8 100644 --- a/arch/csr/Zihpm/mhpmcounter19.yaml +++ b/arch/csr/Zihpm/mhpmcounter19.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmcounter19 long_name: Machine Hardware Performance Counter 19 address: 0xB13 -writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter19h.yaml b/arch/csr/Zihpm/mhpmcounter19h.yaml index 78e7318c13..6483d13301 100644 --- a/arch/csr/Zihpm/mhpmcounter19h.yaml +++ b/arch/csr/Zihpm/mhpmcounter19h.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmcounter19h long_name: Machine Hardware Performance Counter 19, Upper half address: 0xB93 -writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter20.yaml b/arch/csr/Zihpm/mhpmcounter20.yaml index 12cc843582..6f7d6d1e85 100644 --- a/arch/csr/Zihpm/mhpmcounter20.yaml +++ b/arch/csr/Zihpm/mhpmcounter20.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmcounter20 long_name: Machine Hardware Performance Counter 20 address: 0xB14 -writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter20h.yaml b/arch/csr/Zihpm/mhpmcounter20h.yaml index a168876173..73db882e51 100644 --- a/arch/csr/Zihpm/mhpmcounter20h.yaml +++ b/arch/csr/Zihpm/mhpmcounter20h.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmcounter20h long_name: Machine Hardware Performance Counter 20, Upper half address: 0xB94 -writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter21.yaml b/arch/csr/Zihpm/mhpmcounter21.yaml index cfc330fdc0..b5cfa7a02d 100644 --- a/arch/csr/Zihpm/mhpmcounter21.yaml +++ b/arch/csr/Zihpm/mhpmcounter21.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmcounter21 long_name: Machine Hardware Performance Counter 21 address: 0xB15 -writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter21h.yaml b/arch/csr/Zihpm/mhpmcounter21h.yaml index 5138852e39..f3d81870f8 100644 --- a/arch/csr/Zihpm/mhpmcounter21h.yaml +++ b/arch/csr/Zihpm/mhpmcounter21h.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmcounter21h long_name: Machine Hardware Performance Counter 21, Upper half address: 0xB95 -writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter22.yaml b/arch/csr/Zihpm/mhpmcounter22.yaml index 881ad56ae9..d35d8671dc 100644 --- a/arch/csr/Zihpm/mhpmcounter22.yaml +++ b/arch/csr/Zihpm/mhpmcounter22.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmcounter22 long_name: Machine Hardware Performance Counter 22 address: 0xB16 -writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter22h.yaml b/arch/csr/Zihpm/mhpmcounter22h.yaml index 982784d08f..6617b98232 100644 --- a/arch/csr/Zihpm/mhpmcounter22h.yaml +++ b/arch/csr/Zihpm/mhpmcounter22h.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmcounter22h long_name: Machine Hardware Performance Counter 22, Upper half address: 0xB96 -writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter23.yaml b/arch/csr/Zihpm/mhpmcounter23.yaml index f1de6bf132..380c27d78d 100644 --- a/arch/csr/Zihpm/mhpmcounter23.yaml +++ b/arch/csr/Zihpm/mhpmcounter23.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmcounter23 long_name: Machine Hardware Performance Counter 23 address: 0xB17 -writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter23h.yaml b/arch/csr/Zihpm/mhpmcounter23h.yaml index 099ee3089f..36117b668b 100644 --- a/arch/csr/Zihpm/mhpmcounter23h.yaml +++ b/arch/csr/Zihpm/mhpmcounter23h.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmcounter23h long_name: Machine Hardware Performance Counter 23, Upper half address: 0xB97 -writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter24.yaml b/arch/csr/Zihpm/mhpmcounter24.yaml index 096bc2e7a5..4f66699999 100644 --- a/arch/csr/Zihpm/mhpmcounter24.yaml +++ b/arch/csr/Zihpm/mhpmcounter24.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmcounter24 long_name: Machine Hardware Performance Counter 24 address: 0xB18 -writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter24h.yaml b/arch/csr/Zihpm/mhpmcounter24h.yaml index 3d8fa5546c..d7f37ec8b9 100644 --- a/arch/csr/Zihpm/mhpmcounter24h.yaml +++ b/arch/csr/Zihpm/mhpmcounter24h.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmcounter24h long_name: Machine Hardware Performance Counter 24, Upper half address: 0xB98 -writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter25.yaml b/arch/csr/Zihpm/mhpmcounter25.yaml index b5503ae861..ca1ea51987 100644 --- a/arch/csr/Zihpm/mhpmcounter25.yaml +++ b/arch/csr/Zihpm/mhpmcounter25.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmcounter25 long_name: Machine Hardware Performance Counter 25 address: 0xB19 -writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter25h.yaml b/arch/csr/Zihpm/mhpmcounter25h.yaml index cf7300e514..a8d2fa086d 100644 --- a/arch/csr/Zihpm/mhpmcounter25h.yaml +++ b/arch/csr/Zihpm/mhpmcounter25h.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmcounter25h long_name: Machine Hardware Performance Counter 25, Upper half address: 0xB99 -writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter26.yaml b/arch/csr/Zihpm/mhpmcounter26.yaml index dfcc27e637..9175778c05 100644 --- a/arch/csr/Zihpm/mhpmcounter26.yaml +++ b/arch/csr/Zihpm/mhpmcounter26.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmcounter26 long_name: Machine Hardware Performance Counter 26 address: 0xB1A -writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter26h.yaml b/arch/csr/Zihpm/mhpmcounter26h.yaml index 2925dddcab..2074cf504d 100644 --- a/arch/csr/Zihpm/mhpmcounter26h.yaml +++ b/arch/csr/Zihpm/mhpmcounter26h.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmcounter26h long_name: Machine Hardware Performance Counter 26, Upper half address: 0xB9A -writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter27.yaml b/arch/csr/Zihpm/mhpmcounter27.yaml index 9db94ead49..0cc6b33f94 100644 --- a/arch/csr/Zihpm/mhpmcounter27.yaml +++ b/arch/csr/Zihpm/mhpmcounter27.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmcounter27 long_name: Machine Hardware Performance Counter 27 address: 0xB1B -writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter27h.yaml b/arch/csr/Zihpm/mhpmcounter27h.yaml index fdcaea9186..cfd7308bdf 100644 --- a/arch/csr/Zihpm/mhpmcounter27h.yaml +++ b/arch/csr/Zihpm/mhpmcounter27h.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmcounter27h long_name: Machine Hardware Performance Counter 27, Upper half address: 0xB9B -writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter28.yaml b/arch/csr/Zihpm/mhpmcounter28.yaml index 211c2ba183..f214594745 100644 --- a/arch/csr/Zihpm/mhpmcounter28.yaml +++ b/arch/csr/Zihpm/mhpmcounter28.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmcounter28 long_name: Machine Hardware Performance Counter 28 address: 0xB1C -writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter28h.yaml b/arch/csr/Zihpm/mhpmcounter28h.yaml index e820f81481..5b89a5cdcd 100644 --- a/arch/csr/Zihpm/mhpmcounter28h.yaml +++ b/arch/csr/Zihpm/mhpmcounter28h.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmcounter28h long_name: Machine Hardware Performance Counter 28, Upper half address: 0xB9C -writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter29.yaml b/arch/csr/Zihpm/mhpmcounter29.yaml index 1f6ffc1617..367de7cfec 100644 --- a/arch/csr/Zihpm/mhpmcounter29.yaml +++ b/arch/csr/Zihpm/mhpmcounter29.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmcounter29 long_name: Machine Hardware Performance Counter 29 address: 0xB1D -writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter29h.yaml b/arch/csr/Zihpm/mhpmcounter29h.yaml index 7a8bcd8450..8bbcd8a105 100644 --- a/arch/csr/Zihpm/mhpmcounter29h.yaml +++ b/arch/csr/Zihpm/mhpmcounter29h.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmcounter29h long_name: Machine Hardware Performance Counter 29, Upper half address: 0xB9D -writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter3.yaml b/arch/csr/Zihpm/mhpmcounter3.yaml index e566163369..5c8dd1c6e1 100644 --- a/arch/csr/Zihpm/mhpmcounter3.yaml +++ b/arch/csr/Zihpm/mhpmcounter3.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmcounter3 long_name: Machine Hardware Performance Counter 3 address: 0xB03 -writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter30.yaml b/arch/csr/Zihpm/mhpmcounter30.yaml index 229c38d8f3..441eaab905 100644 --- a/arch/csr/Zihpm/mhpmcounter30.yaml +++ b/arch/csr/Zihpm/mhpmcounter30.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmcounter30 long_name: Machine Hardware Performance Counter 30 address: 0xB1E -writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter30h.yaml b/arch/csr/Zihpm/mhpmcounter30h.yaml index 5efef1f511..b24609c6f1 100644 --- a/arch/csr/Zihpm/mhpmcounter30h.yaml +++ b/arch/csr/Zihpm/mhpmcounter30h.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmcounter30h long_name: Machine Hardware Performance Counter 30, Upper half address: 0xB9E -writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter31.yaml b/arch/csr/Zihpm/mhpmcounter31.yaml index 321b4891a8..917c8d533b 100644 --- a/arch/csr/Zihpm/mhpmcounter31.yaml +++ b/arch/csr/Zihpm/mhpmcounter31.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmcounter31 long_name: Machine Hardware Performance Counter 31 address: 0xB1F -writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter31h.yaml b/arch/csr/Zihpm/mhpmcounter31h.yaml index f2eeeaae9b..219f540d9f 100644 --- a/arch/csr/Zihpm/mhpmcounter31h.yaml +++ b/arch/csr/Zihpm/mhpmcounter31h.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmcounter31h long_name: Machine Hardware Performance Counter 31, Upper half address: 0xB9F -writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter3h.yaml b/arch/csr/Zihpm/mhpmcounter3h.yaml index cae7c2793f..b1d00039fa 100644 --- a/arch/csr/Zihpm/mhpmcounter3h.yaml +++ b/arch/csr/Zihpm/mhpmcounter3h.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmcounter3h long_name: Machine Hardware Performance Counter 3, Upper half address: 0xB83 -writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter4.yaml b/arch/csr/Zihpm/mhpmcounter4.yaml index 9cbd076432..9fc827b0bf 100644 --- a/arch/csr/Zihpm/mhpmcounter4.yaml +++ b/arch/csr/Zihpm/mhpmcounter4.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmcounter4 long_name: Machine Hardware Performance Counter 4 address: 0xB04 -writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter4h.yaml b/arch/csr/Zihpm/mhpmcounter4h.yaml index 774a29590f..b810844ab8 100644 --- a/arch/csr/Zihpm/mhpmcounter4h.yaml +++ b/arch/csr/Zihpm/mhpmcounter4h.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmcounter4h long_name: Machine Hardware Performance Counter 4, Upper half address: 0xB84 -writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter5.yaml b/arch/csr/Zihpm/mhpmcounter5.yaml index 1a0b723f1c..b4c035e04f 100644 --- a/arch/csr/Zihpm/mhpmcounter5.yaml +++ b/arch/csr/Zihpm/mhpmcounter5.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmcounter5 long_name: Machine Hardware Performance Counter 5 address: 0xB05 -writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter5h.yaml b/arch/csr/Zihpm/mhpmcounter5h.yaml index d76cd03bec..f8296cf5a8 100644 --- a/arch/csr/Zihpm/mhpmcounter5h.yaml +++ b/arch/csr/Zihpm/mhpmcounter5h.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmcounter5h long_name: Machine Hardware Performance Counter 5, Upper half address: 0xB85 -writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter6.yaml b/arch/csr/Zihpm/mhpmcounter6.yaml index 1e1afb0bb7..187e00a28b 100644 --- a/arch/csr/Zihpm/mhpmcounter6.yaml +++ b/arch/csr/Zihpm/mhpmcounter6.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmcounter6 long_name: Machine Hardware Performance Counter 6 address: 0xB06 -writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter6h.yaml b/arch/csr/Zihpm/mhpmcounter6h.yaml index 726df5825a..3305497de4 100644 --- a/arch/csr/Zihpm/mhpmcounter6h.yaml +++ b/arch/csr/Zihpm/mhpmcounter6h.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmcounter6h long_name: Machine Hardware Performance Counter 6, Upper half address: 0xB86 -writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter7.yaml b/arch/csr/Zihpm/mhpmcounter7.yaml index 3e6bdc9d6d..7d56e48d5a 100644 --- a/arch/csr/Zihpm/mhpmcounter7.yaml +++ b/arch/csr/Zihpm/mhpmcounter7.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmcounter7 long_name: Machine Hardware Performance Counter 7 address: 0xB07 -writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter7h.yaml b/arch/csr/Zihpm/mhpmcounter7h.yaml index 72f940d1f3..05fc92d3c0 100644 --- a/arch/csr/Zihpm/mhpmcounter7h.yaml +++ b/arch/csr/Zihpm/mhpmcounter7h.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmcounter7h long_name: Machine Hardware Performance Counter 7, Upper half address: 0xB87 -writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter8.yaml b/arch/csr/Zihpm/mhpmcounter8.yaml index 10e30a6349..a29a653bcc 100644 --- a/arch/csr/Zihpm/mhpmcounter8.yaml +++ b/arch/csr/Zihpm/mhpmcounter8.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmcounter8 long_name: Machine Hardware Performance Counter 8 address: 0xB08 -writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter8h.yaml b/arch/csr/Zihpm/mhpmcounter8h.yaml index 2dc2d52c65..02b097678b 100644 --- a/arch/csr/Zihpm/mhpmcounter8h.yaml +++ b/arch/csr/Zihpm/mhpmcounter8h.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmcounter8h long_name: Machine Hardware Performance Counter 8, Upper half address: 0xB88 -writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmcounter9.yaml b/arch/csr/Zihpm/mhpmcounter9.yaml index a7f659d0b7..729999ee53 100644 --- a/arch/csr/Zihpm/mhpmcounter9.yaml +++ b/arch/csr/Zihpm/mhpmcounter9.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmcounter9 long_name: Machine Hardware Performance Counter 9 address: 0xB09 -writeable: true priv_mode: M length: 64 description: Programmable hardware performance counter. diff --git a/arch/csr/Zihpm/mhpmcounter9h.yaml b/arch/csr/Zihpm/mhpmcounter9h.yaml index 05b360ffb9..277f425300 100644 --- a/arch/csr/Zihpm/mhpmcounter9h.yaml +++ b/arch/csr/Zihpm/mhpmcounter9h.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmcounter9h long_name: Machine Hardware Performance Counter 9, Upper half address: 0xB89 -writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent10.yaml b/arch/csr/Zihpm/mhpmevent10.yaml index ecb0134747..d5e3511e5d 100644 --- a/arch/csr/Zihpm/mhpmevent10.yaml +++ b/arch/csr/Zihpm/mhpmevent10.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmevent10 long_name: Machine Hardware Performance Counter 10 Control address: 0x32A -writeable: true priv_mode: M length: 64 description: | @@ -43,9 +42,7 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: - When set, mhpmcounter10 does not increment while the hart in operating - in M-mode. + description: When set, mhpmcounter10 does not increment while the hart in operating in M-mode. type(): | if (HPM_COUNTER_EN[10]) { return CsrFieldType::RW; @@ -61,9 +58,7 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: - When set, mhpmcounter10 does not increment while the hart in operating - in (H)S-mode. + description: When set, mhpmcounter10 does not increment while the hart in operating in (H)S-mode. type(): | if (HPM_COUNTER_EN[10] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -79,9 +74,7 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: - When set, mhpmcounter10 does not increment while the hart in operating - in U-mode. + description: When set, mhpmcounter10 does not increment while the hart in operating in U-mode. type(): | if (HPM_COUNTER_EN[10] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -97,9 +90,7 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: - When set, mhpmcounter10 does not increment while the hart in operating - in VS-mode. + description: When set, mhpmcounter10 does not increment while the hart in operating in VS-mode. type(): | if ((HPM_COUNTER_EN[10]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -115,9 +106,7 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: - When set, mhpmcounter10 does not increment while the hart in operating - in VU-mode. + description: When set, mhpmcounter10 does not increment while the hart in operating in VU-mode. type(): | if (HPM_COUNTER_EN[10] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent10h.yaml b/arch/csr/Zihpm/mhpmevent10h.yaml index 7fd5b12239..ddc90479cd 100644 --- a/arch/csr/Zihpm/mhpmevent10h.yaml +++ b/arch/csr/Zihpm/mhpmevent10h.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmevent10h long_name: Machine Hardware Performance Counter 10 Control, High half address: 0x72A -writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent11.yaml b/arch/csr/Zihpm/mhpmevent11.yaml index f2f4bb4ef2..25acd4e788 100644 --- a/arch/csr/Zihpm/mhpmevent11.yaml +++ b/arch/csr/Zihpm/mhpmevent11.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmevent11 long_name: Machine Hardware Performance Counter 11 Control address: 0x32B -writeable: true priv_mode: M length: 64 description: | @@ -43,9 +42,7 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: - When set, mhpmcounter11 does not increment while the hart in operating - in M-mode. + description: When set, mhpmcounter11 does not increment while the hart in operating in M-mode. type(): | if (HPM_COUNTER_EN[11]) { return CsrFieldType::RW; @@ -61,9 +58,7 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: - When set, mhpmcounter11 does not increment while the hart in operating - in (H)S-mode. + description: When set, mhpmcounter11 does not increment while the hart in operating in (H)S-mode. type(): | if (HPM_COUNTER_EN[11] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -79,9 +74,7 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: - When set, mhpmcounter11 does not increment while the hart in operating - in U-mode. + description: When set, mhpmcounter11 does not increment while the hart in operating in U-mode. type(): | if (HPM_COUNTER_EN[11] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -97,9 +90,7 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: - When set, mhpmcounter11 does not increment while the hart in operating - in VS-mode. + description: When set, mhpmcounter11 does not increment while the hart in operating in VS-mode. type(): | if ((HPM_COUNTER_EN[11]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -115,9 +106,7 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: - When set, mhpmcounter11 does not increment while the hart in operating - in VU-mode. + description: When set, mhpmcounter11 does not increment while the hart in operating in VU-mode. type(): | if (HPM_COUNTER_EN[11] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent11h.yaml b/arch/csr/Zihpm/mhpmevent11h.yaml index 71ad1eb900..10a4d69ab0 100644 --- a/arch/csr/Zihpm/mhpmevent11h.yaml +++ b/arch/csr/Zihpm/mhpmevent11h.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmevent11h long_name: Machine Hardware Performance Counter 11 Control, High half address: 0x72B -writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent12.yaml b/arch/csr/Zihpm/mhpmevent12.yaml index 44ec92451a..3277d79920 100644 --- a/arch/csr/Zihpm/mhpmevent12.yaml +++ b/arch/csr/Zihpm/mhpmevent12.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmevent12 long_name: Machine Hardware Performance Counter 12 Control address: 0x32C -writeable: true priv_mode: M length: 64 description: | @@ -43,9 +42,7 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: - When set, mhpmcounter12 does not increment while the hart in operating - in M-mode. + description: When set, mhpmcounter12 does not increment while the hart in operating in M-mode. type(): | if (HPM_COUNTER_EN[12]) { return CsrFieldType::RW; @@ -61,9 +58,7 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: - When set, mhpmcounter12 does not increment while the hart in operating - in (H)S-mode. + description: When set, mhpmcounter12 does not increment while the hart in operating in (H)S-mode. type(): | if (HPM_COUNTER_EN[12] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -79,9 +74,7 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: - When set, mhpmcounter12 does not increment while the hart in operating - in U-mode. + description: When set, mhpmcounter12 does not increment while the hart in operating in U-mode. type(): | if (HPM_COUNTER_EN[12] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -97,9 +90,7 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: - When set, mhpmcounter12 does not increment while the hart in operating - in VS-mode. + description: When set, mhpmcounter12 does not increment while the hart in operating in VS-mode. type(): | if ((HPM_COUNTER_EN[12]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -115,9 +106,7 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: - When set, mhpmcounter12 does not increment while the hart in operating - in VU-mode. + description: When set, mhpmcounter12 does not increment while the hart in operating in VU-mode. type(): | if (HPM_COUNTER_EN[12] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent12h.yaml b/arch/csr/Zihpm/mhpmevent12h.yaml index e760126e39..1561213e0b 100644 --- a/arch/csr/Zihpm/mhpmevent12h.yaml +++ b/arch/csr/Zihpm/mhpmevent12h.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmevent12h long_name: Machine Hardware Performance Counter 12 Control, High half address: 0x72C -writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent13.yaml b/arch/csr/Zihpm/mhpmevent13.yaml index 089da9360c..8fe055a95f 100644 --- a/arch/csr/Zihpm/mhpmevent13.yaml +++ b/arch/csr/Zihpm/mhpmevent13.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmevent13 long_name: Machine Hardware Performance Counter 13 Control address: 0x32D -writeable: true priv_mode: M length: 64 description: | @@ -43,9 +42,7 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: - When set, mhpmcounter13 does not increment while the hart in operating - in M-mode. + description: When set, mhpmcounter13 does not increment while the hart in operating in M-mode. type(): | if (HPM_COUNTER_EN[13]) { return CsrFieldType::RW; @@ -61,9 +58,7 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: - When set, mhpmcounter13 does not increment while the hart in operating - in (H)S-mode. + description: When set, mhpmcounter13 does not increment while the hart in operating in (H)S-mode. type(): | if (HPM_COUNTER_EN[13] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -79,9 +74,7 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: - When set, mhpmcounter13 does not increment while the hart in operating - in U-mode. + description: When set, mhpmcounter13 does not increment while the hart in operating in U-mode. type(): | if (HPM_COUNTER_EN[13] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -97,9 +90,7 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: - When set, mhpmcounter13 does not increment while the hart in operating - in VS-mode. + description: When set, mhpmcounter13 does not increment while the hart in operating in VS-mode. type(): | if ((HPM_COUNTER_EN[13]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -115,9 +106,7 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: - When set, mhpmcounter13 does not increment while the hart in operating - in VU-mode. + description: When set, mhpmcounter13 does not increment while the hart in operating in VU-mode. type(): | if (HPM_COUNTER_EN[13] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent13h.yaml b/arch/csr/Zihpm/mhpmevent13h.yaml index b335a5472d..9d6a4c4f48 100644 --- a/arch/csr/Zihpm/mhpmevent13h.yaml +++ b/arch/csr/Zihpm/mhpmevent13h.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmevent13h long_name: Machine Hardware Performance Counter 13 Control, High half address: 0x72D -writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent14.yaml b/arch/csr/Zihpm/mhpmevent14.yaml index 9480a5315a..c4f64bcd0e 100644 --- a/arch/csr/Zihpm/mhpmevent14.yaml +++ b/arch/csr/Zihpm/mhpmevent14.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmevent14 long_name: Machine Hardware Performance Counter 14 Control address: 0x32E -writeable: true priv_mode: M length: 64 description: | @@ -43,9 +42,7 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: - When set, mhpmcounter14 does not increment while the hart in operating - in M-mode. + description: When set, mhpmcounter14 does not increment while the hart in operating in M-mode. type(): | if (HPM_COUNTER_EN[14]) { return CsrFieldType::RW; @@ -61,9 +58,7 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: - When set, mhpmcounter14 does not increment while the hart in operating - in (H)S-mode. + description: When set, mhpmcounter14 does not increment while the hart in operating in (H)S-mode. type(): | if (HPM_COUNTER_EN[14] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -79,9 +74,7 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: - When set, mhpmcounter14 does not increment while the hart in operating - in U-mode. + description: When set, mhpmcounter14 does not increment while the hart in operating in U-mode. type(): | if (HPM_COUNTER_EN[14] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -97,9 +90,7 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: - When set, mhpmcounter14 does not increment while the hart in operating - in VS-mode. + description: When set, mhpmcounter14 does not increment while the hart in operating in VS-mode. type(): | if ((HPM_COUNTER_EN[14]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -115,9 +106,7 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: - When set, mhpmcounter14 does not increment while the hart in operating - in VU-mode. + description: When set, mhpmcounter14 does not increment while the hart in operating in VU-mode. type(): | if (HPM_COUNTER_EN[14] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent14h.yaml b/arch/csr/Zihpm/mhpmevent14h.yaml index 3b723c6fa5..53e1db9431 100644 --- a/arch/csr/Zihpm/mhpmevent14h.yaml +++ b/arch/csr/Zihpm/mhpmevent14h.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmevent14h long_name: Machine Hardware Performance Counter 14 Control, High half address: 0x72E -writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent15.yaml b/arch/csr/Zihpm/mhpmevent15.yaml index 8295fd4b53..bf73956a62 100644 --- a/arch/csr/Zihpm/mhpmevent15.yaml +++ b/arch/csr/Zihpm/mhpmevent15.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmevent15 long_name: Machine Hardware Performance Counter 15 Control address: 0x32F -writeable: true priv_mode: M length: 64 description: | @@ -43,9 +42,7 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: - When set, mhpmcounter15 does not increment while the hart in operating - in M-mode. + description: When set, mhpmcounter15 does not increment while the hart in operating in M-mode. type(): | if (HPM_COUNTER_EN[15]) { return CsrFieldType::RW; @@ -61,9 +58,7 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: - When set, mhpmcounter15 does not increment while the hart in operating - in (H)S-mode. + description: When set, mhpmcounter15 does not increment while the hart in operating in (H)S-mode. type(): | if (HPM_COUNTER_EN[15] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -79,9 +74,7 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: - When set, mhpmcounter15 does not increment while the hart in operating - in U-mode. + description: When set, mhpmcounter15 does not increment while the hart in operating in U-mode. type(): | if (HPM_COUNTER_EN[15] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -97,9 +90,7 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: - When set, mhpmcounter15 does not increment while the hart in operating - in VS-mode. + description: When set, mhpmcounter15 does not increment while the hart in operating in VS-mode. type(): | if ((HPM_COUNTER_EN[15]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -115,9 +106,7 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: - When set, mhpmcounter15 does not increment while the hart in operating - in VU-mode. + description: When set, mhpmcounter15 does not increment while the hart in operating in VU-mode. type(): | if (HPM_COUNTER_EN[15] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent15h.yaml b/arch/csr/Zihpm/mhpmevent15h.yaml index d3dd4d15be..a8298f5a03 100644 --- a/arch/csr/Zihpm/mhpmevent15h.yaml +++ b/arch/csr/Zihpm/mhpmevent15h.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmevent15h long_name: Machine Hardware Performance Counter 15 Control, High half address: 0x72F -writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent16.yaml b/arch/csr/Zihpm/mhpmevent16.yaml index 2f5e596db5..0f39bfbc94 100644 --- a/arch/csr/Zihpm/mhpmevent16.yaml +++ b/arch/csr/Zihpm/mhpmevent16.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmevent16 long_name: Machine Hardware Performance Counter 16 Control address: 0x330 -writeable: true priv_mode: M length: 64 description: | @@ -43,9 +42,7 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: - When set, mhpmcounter16 does not increment while the hart in operating - in M-mode. + description: When set, mhpmcounter16 does not increment while the hart in operating in M-mode. type(): | if (HPM_COUNTER_EN[16]) { return CsrFieldType::RW; @@ -61,9 +58,7 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: - When set, mhpmcounter16 does not increment while the hart in operating - in (H)S-mode. + description: When set, mhpmcounter16 does not increment while the hart in operating in (H)S-mode. type(): | if (HPM_COUNTER_EN[16] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -79,9 +74,7 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: - When set, mhpmcounter16 does not increment while the hart in operating - in U-mode. + description: When set, mhpmcounter16 does not increment while the hart in operating in U-mode. type(): | if (HPM_COUNTER_EN[16] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -97,9 +90,7 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: - When set, mhpmcounter16 does not increment while the hart in operating - in VS-mode. + description: When set, mhpmcounter16 does not increment while the hart in operating in VS-mode. type(): | if ((HPM_COUNTER_EN[16]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -115,9 +106,7 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: - When set, mhpmcounter16 does not increment while the hart in operating - in VU-mode. + description: When set, mhpmcounter16 does not increment while the hart in operating in VU-mode. type(): | if (HPM_COUNTER_EN[16] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent16h.yaml b/arch/csr/Zihpm/mhpmevent16h.yaml index 3052f0ef14..7257f46c5f 100644 --- a/arch/csr/Zihpm/mhpmevent16h.yaml +++ b/arch/csr/Zihpm/mhpmevent16h.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmevent16h long_name: Machine Hardware Performance Counter 16 Control, High half address: 0x730 -writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent17.yaml b/arch/csr/Zihpm/mhpmevent17.yaml index 1be002bc2a..b442d54fb2 100644 --- a/arch/csr/Zihpm/mhpmevent17.yaml +++ b/arch/csr/Zihpm/mhpmevent17.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmevent17 long_name: Machine Hardware Performance Counter 17 Control address: 0x331 -writeable: true priv_mode: M length: 64 description: | @@ -43,9 +42,7 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: - When set, mhpmcounter17 does not increment while the hart in operating - in M-mode. + description: When set, mhpmcounter17 does not increment while the hart in operating in M-mode. type(): | if (HPM_COUNTER_EN[17]) { return CsrFieldType::RW; @@ -61,9 +58,7 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: - When set, mhpmcounter17 does not increment while the hart in operating - in (H)S-mode. + description: When set, mhpmcounter17 does not increment while the hart in operating in (H)S-mode. type(): | if (HPM_COUNTER_EN[17] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -79,9 +74,7 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: - When set, mhpmcounter17 does not increment while the hart in operating - in U-mode. + description: When set, mhpmcounter17 does not increment while the hart in operating in U-mode. type(): | if (HPM_COUNTER_EN[17] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -97,9 +90,7 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: - When set, mhpmcounter17 does not increment while the hart in operating - in VS-mode. + description: When set, mhpmcounter17 does not increment while the hart in operating in VS-mode. type(): | if ((HPM_COUNTER_EN[17]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -115,9 +106,7 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: - When set, mhpmcounter17 does not increment while the hart in operating - in VU-mode. + description: When set, mhpmcounter17 does not increment while the hart in operating in VU-mode. type(): | if (HPM_COUNTER_EN[17] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent17h.yaml b/arch/csr/Zihpm/mhpmevent17h.yaml index a47dfea651..70e07cc5b5 100644 --- a/arch/csr/Zihpm/mhpmevent17h.yaml +++ b/arch/csr/Zihpm/mhpmevent17h.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmevent17h long_name: Machine Hardware Performance Counter 17 Control, High half address: 0x731 -writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent18.yaml b/arch/csr/Zihpm/mhpmevent18.yaml index 19911621eb..95f43e4428 100644 --- a/arch/csr/Zihpm/mhpmevent18.yaml +++ b/arch/csr/Zihpm/mhpmevent18.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmevent18 long_name: Machine Hardware Performance Counter 18 Control address: 0x332 -writeable: true priv_mode: M length: 64 description: | @@ -43,9 +42,7 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: - When set, mhpmcounter18 does not increment while the hart in operating - in M-mode. + description: When set, mhpmcounter18 does not increment while the hart in operating in M-mode. type(): | if (HPM_COUNTER_EN[18]) { return CsrFieldType::RW; @@ -61,9 +58,7 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: - When set, mhpmcounter18 does not increment while the hart in operating - in (H)S-mode. + description: When set, mhpmcounter18 does not increment while the hart in operating in (H)S-mode. type(): | if (HPM_COUNTER_EN[18] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -79,9 +74,7 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: - When set, mhpmcounter18 does not increment while the hart in operating - in U-mode. + description: When set, mhpmcounter18 does not increment while the hart in operating in U-mode. type(): | if (HPM_COUNTER_EN[18] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -97,9 +90,7 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: - When set, mhpmcounter18 does not increment while the hart in operating - in VS-mode. + description: When set, mhpmcounter18 does not increment while the hart in operating in VS-mode. type(): | if ((HPM_COUNTER_EN[18]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -115,9 +106,7 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: - When set, mhpmcounter18 does not increment while the hart in operating - in VU-mode. + description: When set, mhpmcounter18 does not increment while the hart in operating in VU-mode. type(): | if (HPM_COUNTER_EN[18] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent18h.yaml b/arch/csr/Zihpm/mhpmevent18h.yaml index 23d83aa836..4cd34aaafa 100644 --- a/arch/csr/Zihpm/mhpmevent18h.yaml +++ b/arch/csr/Zihpm/mhpmevent18h.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmevent18h long_name: Machine Hardware Performance Counter 18 Control, High half address: 0x732 -writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent19.yaml b/arch/csr/Zihpm/mhpmevent19.yaml index 9f9d441605..1a1ced791e 100644 --- a/arch/csr/Zihpm/mhpmevent19.yaml +++ b/arch/csr/Zihpm/mhpmevent19.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmevent19 long_name: Machine Hardware Performance Counter 19 Control address: 0x333 -writeable: true priv_mode: M length: 64 description: | @@ -43,9 +42,7 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: - When set, mhpmcounter19 does not increment while the hart in operating - in M-mode. + description: When set, mhpmcounter19 does not increment while the hart in operating in M-mode. type(): | if (HPM_COUNTER_EN[19]) { return CsrFieldType::RW; @@ -61,9 +58,7 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: - When set, mhpmcounter19 does not increment while the hart in operating - in (H)S-mode. + description: When set, mhpmcounter19 does not increment while the hart in operating in (H)S-mode. type(): | if (HPM_COUNTER_EN[19] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -79,9 +74,7 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: - When set, mhpmcounter19 does not increment while the hart in operating - in U-mode. + description: When set, mhpmcounter19 does not increment while the hart in operating in U-mode. type(): | if (HPM_COUNTER_EN[19] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -97,9 +90,7 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: - When set, mhpmcounter19 does not increment while the hart in operating - in VS-mode. + description: When set, mhpmcounter19 does not increment while the hart in operating in VS-mode. type(): | if ((HPM_COUNTER_EN[19]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -115,9 +106,7 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: - When set, mhpmcounter19 does not increment while the hart in operating - in VU-mode. + description: When set, mhpmcounter19 does not increment while the hart in operating in VU-mode. type(): | if (HPM_COUNTER_EN[19] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent19h.yaml b/arch/csr/Zihpm/mhpmevent19h.yaml index 4afb967263..2d67a0db2e 100644 --- a/arch/csr/Zihpm/mhpmevent19h.yaml +++ b/arch/csr/Zihpm/mhpmevent19h.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmevent19h long_name: Machine Hardware Performance Counter 19 Control, High half address: 0x733 -writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent20.yaml b/arch/csr/Zihpm/mhpmevent20.yaml index b603174dc4..5ec2c960b9 100644 --- a/arch/csr/Zihpm/mhpmevent20.yaml +++ b/arch/csr/Zihpm/mhpmevent20.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmevent20 long_name: Machine Hardware Performance Counter 20 Control address: 0x334 -writeable: true priv_mode: M length: 64 description: | @@ -43,9 +42,7 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: - When set, mhpmcounter20 does not increment while the hart in operating - in M-mode. + description: When set, mhpmcounter20 does not increment while the hart in operating in M-mode. type(): | if (HPM_COUNTER_EN[20]) { return CsrFieldType::RW; @@ -61,9 +58,7 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: - When set, mhpmcounter20 does not increment while the hart in operating - in (H)S-mode. + description: When set, mhpmcounter20 does not increment while the hart in operating in (H)S-mode. type(): | if (HPM_COUNTER_EN[20] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -79,9 +74,7 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: - When set, mhpmcounter20 does not increment while the hart in operating - in U-mode. + description: When set, mhpmcounter20 does not increment while the hart in operating in U-mode. type(): | if (HPM_COUNTER_EN[20] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -97,9 +90,7 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: - When set, mhpmcounter20 does not increment while the hart in operating - in VS-mode. + description: When set, mhpmcounter20 does not increment while the hart in operating in VS-mode. type(): | if ((HPM_COUNTER_EN[20]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -115,9 +106,7 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: - When set, mhpmcounter20 does not increment while the hart in operating - in VU-mode. + description: When set, mhpmcounter20 does not increment while the hart in operating in VU-mode. type(): | if (HPM_COUNTER_EN[20] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent20h.yaml b/arch/csr/Zihpm/mhpmevent20h.yaml index eb60d57b1d..32f9027ac7 100644 --- a/arch/csr/Zihpm/mhpmevent20h.yaml +++ b/arch/csr/Zihpm/mhpmevent20h.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmevent20h long_name: Machine Hardware Performance Counter 20 Control, High half address: 0x734 -writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent21.yaml b/arch/csr/Zihpm/mhpmevent21.yaml index 064ad0a591..166aa50f66 100644 --- a/arch/csr/Zihpm/mhpmevent21.yaml +++ b/arch/csr/Zihpm/mhpmevent21.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmevent21 long_name: Machine Hardware Performance Counter 21 Control address: 0x335 -writeable: true priv_mode: M length: 64 description: | @@ -43,9 +42,7 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: - When set, mhpmcounter21 does not increment while the hart in operating - in M-mode. + description: When set, mhpmcounter21 does not increment while the hart in operating in M-mode. type(): | if (HPM_COUNTER_EN[21]) { return CsrFieldType::RW; @@ -61,9 +58,7 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: - When set, mhpmcounter21 does not increment while the hart in operating - in (H)S-mode. + description: When set, mhpmcounter21 does not increment while the hart in operating in (H)S-mode. type(): | if (HPM_COUNTER_EN[21] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -79,9 +74,7 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: - When set, mhpmcounter21 does not increment while the hart in operating - in U-mode. + description: When set, mhpmcounter21 does not increment while the hart in operating in U-mode. type(): | if (HPM_COUNTER_EN[21] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -97,9 +90,7 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: - When set, mhpmcounter21 does not increment while the hart in operating - in VS-mode. + description: When set, mhpmcounter21 does not increment while the hart in operating in VS-mode. type(): | if ((HPM_COUNTER_EN[21]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -115,9 +106,7 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: - When set, mhpmcounter21 does not increment while the hart in operating - in VU-mode. + description: When set, mhpmcounter21 does not increment while the hart in operating in VU-mode. type(): | if (HPM_COUNTER_EN[21] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent21h.yaml b/arch/csr/Zihpm/mhpmevent21h.yaml index a44c4f4f53..f5fa3dfe28 100644 --- a/arch/csr/Zihpm/mhpmevent21h.yaml +++ b/arch/csr/Zihpm/mhpmevent21h.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmevent21h long_name: Machine Hardware Performance Counter 21 Control, High half address: 0x735 -writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent22.yaml b/arch/csr/Zihpm/mhpmevent22.yaml index b8697f2433..21f1a3c4bb 100644 --- a/arch/csr/Zihpm/mhpmevent22.yaml +++ b/arch/csr/Zihpm/mhpmevent22.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmevent22 long_name: Machine Hardware Performance Counter 22 Control address: 0x336 -writeable: true priv_mode: M length: 64 description: | @@ -43,9 +42,7 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: - When set, mhpmcounter22 does not increment while the hart in operating - in M-mode. + description: When set, mhpmcounter22 does not increment while the hart in operating in M-mode. type(): | if (HPM_COUNTER_EN[22]) { return CsrFieldType::RW; @@ -61,9 +58,7 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: - When set, mhpmcounter22 does not increment while the hart in operating - in (H)S-mode. + description: When set, mhpmcounter22 does not increment while the hart in operating in (H)S-mode. type(): | if (HPM_COUNTER_EN[22] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -79,9 +74,7 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: - When set, mhpmcounter22 does not increment while the hart in operating - in U-mode. + description: When set, mhpmcounter22 does not increment while the hart in operating in U-mode. type(): | if (HPM_COUNTER_EN[22] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -97,9 +90,7 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: - When set, mhpmcounter22 does not increment while the hart in operating - in VS-mode. + description: When set, mhpmcounter22 does not increment while the hart in operating in VS-mode. type(): | if ((HPM_COUNTER_EN[22]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -115,9 +106,7 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: - When set, mhpmcounter22 does not increment while the hart in operating - in VU-mode. + description: When set, mhpmcounter22 does not increment while the hart in operating in VU-mode. type(): | if (HPM_COUNTER_EN[22] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent22h.yaml b/arch/csr/Zihpm/mhpmevent22h.yaml index 317a5516b5..a8adbe8a1e 100644 --- a/arch/csr/Zihpm/mhpmevent22h.yaml +++ b/arch/csr/Zihpm/mhpmevent22h.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmevent22h long_name: Machine Hardware Performance Counter 22 Control, High half address: 0x736 -writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent23.yaml b/arch/csr/Zihpm/mhpmevent23.yaml index fed6373eb6..4e6b623c04 100644 --- a/arch/csr/Zihpm/mhpmevent23.yaml +++ b/arch/csr/Zihpm/mhpmevent23.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmevent23 long_name: Machine Hardware Performance Counter 23 Control address: 0x337 -writeable: true priv_mode: M length: 64 description: | @@ -43,9 +42,7 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: - When set, mhpmcounter23 does not increment while the hart in operating - in M-mode. + description: When set, mhpmcounter23 does not increment while the hart in operating in M-mode. type(): | if (HPM_COUNTER_EN[23]) { return CsrFieldType::RW; @@ -61,9 +58,7 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: - When set, mhpmcounter23 does not increment while the hart in operating - in (H)S-mode. + description: When set, mhpmcounter23 does not increment while the hart in operating in (H)S-mode. type(): | if (HPM_COUNTER_EN[23] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -79,9 +74,7 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: - When set, mhpmcounter23 does not increment while the hart in operating - in U-mode. + description: When set, mhpmcounter23 does not increment while the hart in operating in U-mode. type(): | if (HPM_COUNTER_EN[23] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -97,9 +90,7 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: - When set, mhpmcounter23 does not increment while the hart in operating - in VS-mode. + description: When set, mhpmcounter23 does not increment while the hart in operating in VS-mode. type(): | if ((HPM_COUNTER_EN[23]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -115,9 +106,7 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: - When set, mhpmcounter23 does not increment while the hart in operating - in VU-mode. + description: When set, mhpmcounter23 does not increment while the hart in operating in VU-mode. type(): | if (HPM_COUNTER_EN[23] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent23h.yaml b/arch/csr/Zihpm/mhpmevent23h.yaml index 2b04776472..ba1566e3d1 100644 --- a/arch/csr/Zihpm/mhpmevent23h.yaml +++ b/arch/csr/Zihpm/mhpmevent23h.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmevent23h long_name: Machine Hardware Performance Counter 23 Control, High half address: 0x737 -writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent24.yaml b/arch/csr/Zihpm/mhpmevent24.yaml index f9ad03c43e..89cd20f66e 100644 --- a/arch/csr/Zihpm/mhpmevent24.yaml +++ b/arch/csr/Zihpm/mhpmevent24.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmevent24 long_name: Machine Hardware Performance Counter 24 Control address: 0x338 -writeable: true priv_mode: M length: 64 description: | @@ -43,9 +42,7 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: - When set, mhpmcounter24 does not increment while the hart in operating - in M-mode. + description: When set, mhpmcounter24 does not increment while the hart in operating in M-mode. type(): | if (HPM_COUNTER_EN[24]) { return CsrFieldType::RW; @@ -61,9 +58,7 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: - When set, mhpmcounter24 does not increment while the hart in operating - in (H)S-mode. + description: When set, mhpmcounter24 does not increment while the hart in operating in (H)S-mode. type(): | if (HPM_COUNTER_EN[24] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -79,9 +74,7 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: - When set, mhpmcounter24 does not increment while the hart in operating - in U-mode. + description: When set, mhpmcounter24 does not increment while the hart in operating in U-mode. type(): | if (HPM_COUNTER_EN[24] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -97,9 +90,7 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: - When set, mhpmcounter24 does not increment while the hart in operating - in VS-mode. + description: When set, mhpmcounter24 does not increment while the hart in operating in VS-mode. type(): | if ((HPM_COUNTER_EN[24]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -115,9 +106,7 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: - When set, mhpmcounter24 does not increment while the hart in operating - in VU-mode. + description: When set, mhpmcounter24 does not increment while the hart in operating in VU-mode. type(): | if (HPM_COUNTER_EN[24] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent24h.yaml b/arch/csr/Zihpm/mhpmevent24h.yaml index 540580e16a..69adfe7536 100644 --- a/arch/csr/Zihpm/mhpmevent24h.yaml +++ b/arch/csr/Zihpm/mhpmevent24h.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmevent24h long_name: Machine Hardware Performance Counter 24 Control, High half address: 0x738 -writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent25.yaml b/arch/csr/Zihpm/mhpmevent25.yaml index 6b743c3a8e..4b291b985f 100644 --- a/arch/csr/Zihpm/mhpmevent25.yaml +++ b/arch/csr/Zihpm/mhpmevent25.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmevent25 long_name: Machine Hardware Performance Counter 25 Control address: 0x339 -writeable: true priv_mode: M length: 64 description: | @@ -43,9 +42,7 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: - When set, mhpmcounter25 does not increment while the hart in operating - in M-mode. + description: When set, mhpmcounter25 does not increment while the hart in operating in M-mode. type(): | if (HPM_COUNTER_EN[25]) { return CsrFieldType::RW; @@ -61,9 +58,7 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: - When set, mhpmcounter25 does not increment while the hart in operating - in (H)S-mode. + description: When set, mhpmcounter25 does not increment while the hart in operating in (H)S-mode. type(): | if (HPM_COUNTER_EN[25] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -79,9 +74,7 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: - When set, mhpmcounter25 does not increment while the hart in operating - in U-mode. + description: When set, mhpmcounter25 does not increment while the hart in operating in U-mode. type(): | if (HPM_COUNTER_EN[25] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -97,9 +90,7 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: - When set, mhpmcounter25 does not increment while the hart in operating - in VS-mode. + description: When set, mhpmcounter25 does not increment while the hart in operating in VS-mode. type(): | if ((HPM_COUNTER_EN[25]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -115,9 +106,7 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: - When set, mhpmcounter25 does not increment while the hart in operating - in VU-mode. + description: When set, mhpmcounter25 does not increment while the hart in operating in VU-mode. type(): | if (HPM_COUNTER_EN[25] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent25h.yaml b/arch/csr/Zihpm/mhpmevent25h.yaml index c8e75371a9..411ba06a52 100644 --- a/arch/csr/Zihpm/mhpmevent25h.yaml +++ b/arch/csr/Zihpm/mhpmevent25h.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmevent25h long_name: Machine Hardware Performance Counter 25 Control, High half address: 0x739 -writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent26.yaml b/arch/csr/Zihpm/mhpmevent26.yaml index 2ef1de995d..0ca5a2c6fe 100644 --- a/arch/csr/Zihpm/mhpmevent26.yaml +++ b/arch/csr/Zihpm/mhpmevent26.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmevent26 long_name: Machine Hardware Performance Counter 26 Control address: 0x33A -writeable: true priv_mode: M length: 64 description: | @@ -43,9 +42,7 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: - When set, mhpmcounter26 does not increment while the hart in operating - in M-mode. + description: When set, mhpmcounter26 does not increment while the hart in operating in M-mode. type(): | if (HPM_COUNTER_EN[26]) { return CsrFieldType::RW; @@ -61,9 +58,7 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: - When set, mhpmcounter26 does not increment while the hart in operating - in (H)S-mode. + description: When set, mhpmcounter26 does not increment while the hart in operating in (H)S-mode. type(): | if (HPM_COUNTER_EN[26] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -79,9 +74,7 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: - When set, mhpmcounter26 does not increment while the hart in operating - in U-mode. + description: When set, mhpmcounter26 does not increment while the hart in operating in U-mode. type(): | if (HPM_COUNTER_EN[26] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -97,9 +90,7 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: - When set, mhpmcounter26 does not increment while the hart in operating - in VS-mode. + description: When set, mhpmcounter26 does not increment while the hart in operating in VS-mode. type(): | if ((HPM_COUNTER_EN[26]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -115,9 +106,7 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: - When set, mhpmcounter26 does not increment while the hart in operating - in VU-mode. + description: When set, mhpmcounter26 does not increment while the hart in operating in VU-mode. type(): | if (HPM_COUNTER_EN[26] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent26h.yaml b/arch/csr/Zihpm/mhpmevent26h.yaml index 473246d7d6..276bf866fa 100644 --- a/arch/csr/Zihpm/mhpmevent26h.yaml +++ b/arch/csr/Zihpm/mhpmevent26h.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmevent26h long_name: Machine Hardware Performance Counter 26 Control, High half address: 0x73A -writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent27.yaml b/arch/csr/Zihpm/mhpmevent27.yaml index 17cf19420b..b8e7ba1d1b 100644 --- a/arch/csr/Zihpm/mhpmevent27.yaml +++ b/arch/csr/Zihpm/mhpmevent27.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmevent27 long_name: Machine Hardware Performance Counter 27 Control address: 0x33B -writeable: true priv_mode: M length: 64 description: | @@ -43,9 +42,7 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: - When set, mhpmcounter27 does not increment while the hart in operating - in M-mode. + description: When set, mhpmcounter27 does not increment while the hart in operating in M-mode. type(): | if (HPM_COUNTER_EN[27]) { return CsrFieldType::RW; @@ -61,9 +58,7 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: - When set, mhpmcounter27 does not increment while the hart in operating - in (H)S-mode. + description: When set, mhpmcounter27 does not increment while the hart in operating in (H)S-mode. type(): | if (HPM_COUNTER_EN[27] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -79,9 +74,7 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: - When set, mhpmcounter27 does not increment while the hart in operating - in U-mode. + description: When set, mhpmcounter27 does not increment while the hart in operating in U-mode. type(): | if (HPM_COUNTER_EN[27] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -97,9 +90,7 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: - When set, mhpmcounter27 does not increment while the hart in operating - in VS-mode. + description: When set, mhpmcounter27 does not increment while the hart in operating in VS-mode. type(): | if ((HPM_COUNTER_EN[27]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -115,9 +106,7 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: - When set, mhpmcounter27 does not increment while the hart in operating - in VU-mode. + description: When set, mhpmcounter27 does not increment while the hart in operating in VU-mode. type(): | if (HPM_COUNTER_EN[27] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent27h.yaml b/arch/csr/Zihpm/mhpmevent27h.yaml index a2b4fe543f..f5136e8ec1 100644 --- a/arch/csr/Zihpm/mhpmevent27h.yaml +++ b/arch/csr/Zihpm/mhpmevent27h.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmevent27h long_name: Machine Hardware Performance Counter 27 Control, High half address: 0x73B -writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent28.yaml b/arch/csr/Zihpm/mhpmevent28.yaml index dbd7c64764..f9485190e1 100644 --- a/arch/csr/Zihpm/mhpmevent28.yaml +++ b/arch/csr/Zihpm/mhpmevent28.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmevent28 long_name: Machine Hardware Performance Counter 28 Control address: 0x33C -writeable: true priv_mode: M length: 64 description: | @@ -43,9 +42,7 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: - When set, mhpmcounter28 does not increment while the hart in operating - in M-mode. + description: When set, mhpmcounter28 does not increment while the hart in operating in M-mode. type(): | if (HPM_COUNTER_EN[28]) { return CsrFieldType::RW; @@ -61,9 +58,7 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: - When set, mhpmcounter28 does not increment while the hart in operating - in (H)S-mode. + description: When set, mhpmcounter28 does not increment while the hart in operating in (H)S-mode. type(): | if (HPM_COUNTER_EN[28] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -79,9 +74,7 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: - When set, mhpmcounter28 does not increment while the hart in operating - in U-mode. + description: When set, mhpmcounter28 does not increment while the hart in operating in U-mode. type(): | if (HPM_COUNTER_EN[28] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -97,9 +90,7 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: - When set, mhpmcounter28 does not increment while the hart in operating - in VS-mode. + description: When set, mhpmcounter28 does not increment while the hart in operating in VS-mode. type(): | if ((HPM_COUNTER_EN[28]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -115,9 +106,7 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: - When set, mhpmcounter28 does not increment while the hart in operating - in VU-mode. + description: When set, mhpmcounter28 does not increment while the hart in operating in VU-mode. type(): | if (HPM_COUNTER_EN[28] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent28h.yaml b/arch/csr/Zihpm/mhpmevent28h.yaml index fd6c54518f..6f5b083ed0 100644 --- a/arch/csr/Zihpm/mhpmevent28h.yaml +++ b/arch/csr/Zihpm/mhpmevent28h.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmevent28h long_name: Machine Hardware Performance Counter 28 Control, High half address: 0x73C -writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent29.yaml b/arch/csr/Zihpm/mhpmevent29.yaml index 4dc6b80504..007d149878 100644 --- a/arch/csr/Zihpm/mhpmevent29.yaml +++ b/arch/csr/Zihpm/mhpmevent29.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmevent29 long_name: Machine Hardware Performance Counter 29 Control address: 0x33D -writeable: true priv_mode: M length: 64 description: | @@ -43,9 +42,7 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: - When set, mhpmcounter29 does not increment while the hart in operating - in M-mode. + description: When set, mhpmcounter29 does not increment while the hart in operating in M-mode. type(): | if (HPM_COUNTER_EN[29]) { return CsrFieldType::RW; @@ -61,9 +58,7 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: - When set, mhpmcounter29 does not increment while the hart in operating - in (H)S-mode. + description: When set, mhpmcounter29 does not increment while the hart in operating in (H)S-mode. type(): | if (HPM_COUNTER_EN[29] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -79,9 +74,7 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: - When set, mhpmcounter29 does not increment while the hart in operating - in U-mode. + description: When set, mhpmcounter29 does not increment while the hart in operating in U-mode. type(): | if (HPM_COUNTER_EN[29] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -97,9 +90,7 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: - When set, mhpmcounter29 does not increment while the hart in operating - in VS-mode. + description: When set, mhpmcounter29 does not increment while the hart in operating in VS-mode. type(): | if ((HPM_COUNTER_EN[29]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -115,9 +106,7 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: - When set, mhpmcounter29 does not increment while the hart in operating - in VU-mode. + description: When set, mhpmcounter29 does not increment while the hart in operating in VU-mode. type(): | if (HPM_COUNTER_EN[29] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent29h.yaml b/arch/csr/Zihpm/mhpmevent29h.yaml index 7b122a09b8..11c6f67d7f 100644 --- a/arch/csr/Zihpm/mhpmevent29h.yaml +++ b/arch/csr/Zihpm/mhpmevent29h.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmevent29h long_name: Machine Hardware Performance Counter 29 Control, High half address: 0x73D -writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent3.yaml b/arch/csr/Zihpm/mhpmevent3.yaml index 4ce4fd0c75..bf6237f551 100644 --- a/arch/csr/Zihpm/mhpmevent3.yaml +++ b/arch/csr/Zihpm/mhpmevent3.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmevent3 long_name: Machine Hardware Performance Counter 3 Control address: 0x323 -writeable: true priv_mode: M length: 64 description: | @@ -43,9 +42,7 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: - When set, mhpmcounter3 does not increment while the hart in operating - in M-mode. + description: When set, mhpmcounter3 does not increment while the hart in operating in M-mode. type(): | if (HPM_COUNTER_EN[3]) { return CsrFieldType::RW; @@ -61,9 +58,7 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: - When set, mhpmcounter3 does not increment while the hart in operating - in (H)S-mode. + description: When set, mhpmcounter3 does not increment while the hart in operating in (H)S-mode. type(): | if (HPM_COUNTER_EN[3] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -79,9 +74,7 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: - When set, mhpmcounter3 does not increment while the hart in operating - in U-mode. + description: When set, mhpmcounter3 does not increment while the hart in operating in U-mode. type(): | if (HPM_COUNTER_EN[3] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -97,9 +90,7 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: - When set, mhpmcounter3 does not increment while the hart in operating - in VS-mode. + description: When set, mhpmcounter3 does not increment while the hart in operating in VS-mode. type(): | if ((HPM_COUNTER_EN[3]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -115,9 +106,7 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: - When set, mhpmcounter3 does not increment while the hart in operating - in VU-mode. + description: When set, mhpmcounter3 does not increment while the hart in operating in VU-mode. type(): | if (HPM_COUNTER_EN[3] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent30.yaml b/arch/csr/Zihpm/mhpmevent30.yaml index f1f3ed0824..6d59261234 100644 --- a/arch/csr/Zihpm/mhpmevent30.yaml +++ b/arch/csr/Zihpm/mhpmevent30.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmevent30 long_name: Machine Hardware Performance Counter 30 Control address: 0x33E -writeable: true priv_mode: M length: 64 description: | @@ -43,9 +42,7 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: - When set, mhpmcounter30 does not increment while the hart in operating - in M-mode. + description: When set, mhpmcounter30 does not increment while the hart in operating in M-mode. type(): | if (HPM_COUNTER_EN[30]) { return CsrFieldType::RW; @@ -61,9 +58,7 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: - When set, mhpmcounter30 does not increment while the hart in operating - in (H)S-mode. + description: When set, mhpmcounter30 does not increment while the hart in operating in (H)S-mode. type(): | if (HPM_COUNTER_EN[30] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -79,9 +74,7 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: - When set, mhpmcounter30 does not increment while the hart in operating - in U-mode. + description: When set, mhpmcounter30 does not increment while the hart in operating in U-mode. type(): | if (HPM_COUNTER_EN[30] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -97,9 +90,7 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: - When set, mhpmcounter30 does not increment while the hart in operating - in VS-mode. + description: When set, mhpmcounter30 does not increment while the hart in operating in VS-mode. type(): | if ((HPM_COUNTER_EN[30]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -115,9 +106,7 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: - When set, mhpmcounter30 does not increment while the hart in operating - in VU-mode. + description: When set, mhpmcounter30 does not increment while the hart in operating in VU-mode. type(): | if (HPM_COUNTER_EN[30] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent30h.yaml b/arch/csr/Zihpm/mhpmevent30h.yaml index 8b277b4a47..27b55926c8 100644 --- a/arch/csr/Zihpm/mhpmevent30h.yaml +++ b/arch/csr/Zihpm/mhpmevent30h.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmevent30h long_name: Machine Hardware Performance Counter 30 Control, High half address: 0x73E -writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent31.yaml b/arch/csr/Zihpm/mhpmevent31.yaml index e0ac7f2dc3..37b8593076 100644 --- a/arch/csr/Zihpm/mhpmevent31.yaml +++ b/arch/csr/Zihpm/mhpmevent31.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmevent31 long_name: Machine Hardware Performance Counter 31 Control address: 0x33F -writeable: true priv_mode: M length: 64 description: | @@ -43,9 +42,7 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: - When set, mhpmcounter31 does not increment while the hart in operating - in M-mode. + description: When set, mhpmcounter31 does not increment while the hart in operating in M-mode. type(): | if (HPM_COUNTER_EN[31]) { return CsrFieldType::RW; @@ -61,9 +58,7 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: - When set, mhpmcounter31 does not increment while the hart in operating - in (H)S-mode. + description: When set, mhpmcounter31 does not increment while the hart in operating in (H)S-mode. type(): | if (HPM_COUNTER_EN[31] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -79,9 +74,7 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: - When set, mhpmcounter31 does not increment while the hart in operating - in U-mode. + description: When set, mhpmcounter31 does not increment while the hart in operating in U-mode. type(): | if (HPM_COUNTER_EN[31] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -97,9 +90,7 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: - When set, mhpmcounter31 does not increment while the hart in operating - in VS-mode. + description: When set, mhpmcounter31 does not increment while the hart in operating in VS-mode. type(): | if ((HPM_COUNTER_EN[31]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -115,9 +106,7 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: - When set, mhpmcounter31 does not increment while the hart in operating - in VU-mode. + description: When set, mhpmcounter31 does not increment while the hart in operating in VU-mode. type(): | if (HPM_COUNTER_EN[31] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent31h.yaml b/arch/csr/Zihpm/mhpmevent31h.yaml index c39151a2ea..0dca0fbe7f 100644 --- a/arch/csr/Zihpm/mhpmevent31h.yaml +++ b/arch/csr/Zihpm/mhpmevent31h.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmevent31h long_name: Machine Hardware Performance Counter 31 Control, High half address: 0x73F -writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent3h.yaml b/arch/csr/Zihpm/mhpmevent3h.yaml index a5f437fe81..b92a0a8e0c 100644 --- a/arch/csr/Zihpm/mhpmevent3h.yaml +++ b/arch/csr/Zihpm/mhpmevent3h.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmevent3h long_name: Machine Hardware Performance Counter 3 Control, High half address: 0x723 -writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent4.yaml b/arch/csr/Zihpm/mhpmevent4.yaml index 12421c0936..1291ed96f6 100644 --- a/arch/csr/Zihpm/mhpmevent4.yaml +++ b/arch/csr/Zihpm/mhpmevent4.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmevent4 long_name: Machine Hardware Performance Counter 4 Control address: 0x324 -writeable: true priv_mode: M length: 64 description: | @@ -43,9 +42,7 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: - When set, mhpmcounter4 does not increment while the hart in operating - in M-mode. + description: When set, mhpmcounter4 does not increment while the hart in operating in M-mode. type(): | if (HPM_COUNTER_EN[4]) { return CsrFieldType::RW; @@ -61,9 +58,7 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: - When set, mhpmcounter4 does not increment while the hart in operating - in (H)S-mode. + description: When set, mhpmcounter4 does not increment while the hart in operating in (H)S-mode. type(): | if (HPM_COUNTER_EN[4] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -79,9 +74,7 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: - When set, mhpmcounter4 does not increment while the hart in operating - in U-mode. + description: When set, mhpmcounter4 does not increment while the hart in operating in U-mode. type(): | if (HPM_COUNTER_EN[4] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -97,9 +90,7 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: - When set, mhpmcounter4 does not increment while the hart in operating - in VS-mode. + description: When set, mhpmcounter4 does not increment while the hart in operating in VS-mode. type(): | if ((HPM_COUNTER_EN[4]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -115,9 +106,7 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: - When set, mhpmcounter4 does not increment while the hart in operating - in VU-mode. + description: When set, mhpmcounter4 does not increment while the hart in operating in VU-mode. type(): | if (HPM_COUNTER_EN[4] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent4h.yaml b/arch/csr/Zihpm/mhpmevent4h.yaml index 74e0bc4ac1..e70ed1280d 100644 --- a/arch/csr/Zihpm/mhpmevent4h.yaml +++ b/arch/csr/Zihpm/mhpmevent4h.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmevent4h long_name: Machine Hardware Performance Counter 4 Control, High half address: 0x724 -writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent5.yaml b/arch/csr/Zihpm/mhpmevent5.yaml index bf0ffe5775..bbe2824f5c 100644 --- a/arch/csr/Zihpm/mhpmevent5.yaml +++ b/arch/csr/Zihpm/mhpmevent5.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmevent5 long_name: Machine Hardware Performance Counter 5 Control address: 0x325 -writeable: true priv_mode: M length: 64 description: | @@ -43,9 +42,7 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: - When set, mhpmcounter5 does not increment while the hart in operating - in M-mode. + description: When set, mhpmcounter5 does not increment while the hart in operating in M-mode. type(): | if (HPM_COUNTER_EN[5]) { return CsrFieldType::RW; @@ -61,9 +58,7 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: - When set, mhpmcounter5 does not increment while the hart in operating - in (H)S-mode. + description: When set, mhpmcounter5 does not increment while the hart in operating in (H)S-mode. type(): | if (HPM_COUNTER_EN[5] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -79,9 +74,7 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: - When set, mhpmcounter5 does not increment while the hart in operating - in U-mode. + description: When set, mhpmcounter5 does not increment while the hart in operating in U-mode. type(): | if (HPM_COUNTER_EN[5] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -97,9 +90,7 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: - When set, mhpmcounter5 does not increment while the hart in operating - in VS-mode. + description: When set, mhpmcounter5 does not increment while the hart in operating in VS-mode. type(): | if ((HPM_COUNTER_EN[5]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -115,9 +106,7 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: - When set, mhpmcounter5 does not increment while the hart in operating - in VU-mode. + description: When set, mhpmcounter5 does not increment while the hart in operating in VU-mode. type(): | if (HPM_COUNTER_EN[5] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent5h.yaml b/arch/csr/Zihpm/mhpmevent5h.yaml index f8347cf95f..b8db07f6f7 100644 --- a/arch/csr/Zihpm/mhpmevent5h.yaml +++ b/arch/csr/Zihpm/mhpmevent5h.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmevent5h long_name: Machine Hardware Performance Counter 5 Control, High half address: 0x725 -writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent6.yaml b/arch/csr/Zihpm/mhpmevent6.yaml index 2e6240c7aa..f4e0b15cb9 100644 --- a/arch/csr/Zihpm/mhpmevent6.yaml +++ b/arch/csr/Zihpm/mhpmevent6.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmevent6 long_name: Machine Hardware Performance Counter 6 Control address: 0x326 -writeable: true priv_mode: M length: 64 description: | @@ -43,9 +42,7 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: - When set, mhpmcounter6 does not increment while the hart in operating - in M-mode. + description: When set, mhpmcounter6 does not increment while the hart in operating in M-mode. type(): | if (HPM_COUNTER_EN[6]) { return CsrFieldType::RW; @@ -61,9 +58,7 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: - When set, mhpmcounter6 does not increment while the hart in operating - in (H)S-mode. + description: When set, mhpmcounter6 does not increment while the hart in operating in (H)S-mode. type(): | if (HPM_COUNTER_EN[6] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -79,9 +74,7 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: - When set, mhpmcounter6 does not increment while the hart in operating - in U-mode. + description: When set, mhpmcounter6 does not increment while the hart in operating in U-mode. type(): | if (HPM_COUNTER_EN[6] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -97,9 +90,7 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: - When set, mhpmcounter6 does not increment while the hart in operating - in VS-mode. + description: When set, mhpmcounter6 does not increment while the hart in operating in VS-mode. type(): | if ((HPM_COUNTER_EN[6]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -115,9 +106,7 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: - When set, mhpmcounter6 does not increment while the hart in operating - in VU-mode. + description: When set, mhpmcounter6 does not increment while the hart in operating in VU-mode. type(): | if (HPM_COUNTER_EN[6] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent6h.yaml b/arch/csr/Zihpm/mhpmevent6h.yaml index 1708de0339..d6e9003aa5 100644 --- a/arch/csr/Zihpm/mhpmevent6h.yaml +++ b/arch/csr/Zihpm/mhpmevent6h.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmevent6h long_name: Machine Hardware Performance Counter 6 Control, High half address: 0x726 -writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent7.yaml b/arch/csr/Zihpm/mhpmevent7.yaml index e4d4b06fcd..c4586b60bd 100644 --- a/arch/csr/Zihpm/mhpmevent7.yaml +++ b/arch/csr/Zihpm/mhpmevent7.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmevent7 long_name: Machine Hardware Performance Counter 7 Control address: 0x327 -writeable: true priv_mode: M length: 64 description: | @@ -43,9 +42,7 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: - When set, mhpmcounter7 does not increment while the hart in operating - in M-mode. + description: When set, mhpmcounter7 does not increment while the hart in operating in M-mode. type(): | if (HPM_COUNTER_EN[7]) { return CsrFieldType::RW; @@ -61,9 +58,7 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: - When set, mhpmcounter7 does not increment while the hart in operating - in (H)S-mode. + description: When set, mhpmcounter7 does not increment while the hart in operating in (H)S-mode. type(): | if (HPM_COUNTER_EN[7] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -79,9 +74,7 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: - When set, mhpmcounter7 does not increment while the hart in operating - in U-mode. + description: When set, mhpmcounter7 does not increment while the hart in operating in U-mode. type(): | if (HPM_COUNTER_EN[7] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -97,9 +90,7 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: - When set, mhpmcounter7 does not increment while the hart in operating - in VS-mode. + description: When set, mhpmcounter7 does not increment while the hart in operating in VS-mode. type(): | if ((HPM_COUNTER_EN[7]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -115,9 +106,7 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: - When set, mhpmcounter7 does not increment while the hart in operating - in VU-mode. + description: When set, mhpmcounter7 does not increment while the hart in operating in VU-mode. type(): | if (HPM_COUNTER_EN[7] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent7h.yaml b/arch/csr/Zihpm/mhpmevent7h.yaml index 03a01a2d3a..f04327a66b 100644 --- a/arch/csr/Zihpm/mhpmevent7h.yaml +++ b/arch/csr/Zihpm/mhpmevent7h.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmevent7h long_name: Machine Hardware Performance Counter 7 Control, High half address: 0x727 -writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent8.yaml b/arch/csr/Zihpm/mhpmevent8.yaml index a3dc41f854..349fc9ca30 100644 --- a/arch/csr/Zihpm/mhpmevent8.yaml +++ b/arch/csr/Zihpm/mhpmevent8.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmevent8 long_name: Machine Hardware Performance Counter 8 Control address: 0x328 -writeable: true priv_mode: M length: 64 description: | @@ -43,9 +42,7 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: - When set, mhpmcounter8 does not increment while the hart in operating - in M-mode. + description: When set, mhpmcounter8 does not increment while the hart in operating in M-mode. type(): | if (HPM_COUNTER_EN[8]) { return CsrFieldType::RW; @@ -61,9 +58,7 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: - When set, mhpmcounter8 does not increment while the hart in operating - in (H)S-mode. + description: When set, mhpmcounter8 does not increment while the hart in operating in (H)S-mode. type(): | if (HPM_COUNTER_EN[8] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -79,9 +74,7 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: - When set, mhpmcounter8 does not increment while the hart in operating - in U-mode. + description: When set, mhpmcounter8 does not increment while the hart in operating in U-mode. type(): | if (HPM_COUNTER_EN[8] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -97,9 +90,7 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: - When set, mhpmcounter8 does not increment while the hart in operating - in VS-mode. + description: When set, mhpmcounter8 does not increment while the hart in operating in VS-mode. type(): | if ((HPM_COUNTER_EN[8]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -115,9 +106,7 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: - When set, mhpmcounter8 does not increment while the hart in operating - in VU-mode. + description: When set, mhpmcounter8 does not increment while the hart in operating in VU-mode. type(): | if (HPM_COUNTER_EN[8] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent8h.yaml b/arch/csr/Zihpm/mhpmevent8h.yaml index 44b58d6c41..0370dc3186 100644 --- a/arch/csr/Zihpm/mhpmevent8h.yaml +++ b/arch/csr/Zihpm/mhpmevent8h.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmevent8h long_name: Machine Hardware Performance Counter 8 Control, High half address: 0x728 -writeable: true priv_mode: M length: 32 base: 32 diff --git a/arch/csr/Zihpm/mhpmevent9.yaml b/arch/csr/Zihpm/mhpmevent9.yaml index 1d2a7a1ccc..fc947e3e2d 100644 --- a/arch/csr/Zihpm/mhpmevent9.yaml +++ b/arch/csr/Zihpm/mhpmevent9.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmevent9 long_name: Machine Hardware Performance Counter 9 Control address: 0x329 -writeable: true priv_mode: M length: 64 description: | @@ -43,9 +42,7 @@ fields: definedBy: Sscofpmf MINH: location: 62 - description: - When set, mhpmcounter9 does not increment while the hart in operating - in M-mode. + description: When set, mhpmcounter9 does not increment while the hart in operating in M-mode. type(): | if (HPM_COUNTER_EN[9]) { return CsrFieldType::RW; @@ -61,9 +58,7 @@ fields: definedBy: Sscofpmf SINH: location: 61 - description: - When set, mhpmcounter9 does not increment while the hart in operating - in (H)S-mode. + description: When set, mhpmcounter9 does not increment while the hart in operating in (H)S-mode. type(): | if (HPM_COUNTER_EN[9] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { return CsrFieldType::RW; @@ -79,9 +74,7 @@ fields: definedBy: Sscofpmf UINH: location: 60 - description: - When set, mhpmcounter9 does not increment while the hart in operating - in U-mode. + description: When set, mhpmcounter9 does not increment while the hart in operating in U-mode. type(): | if (HPM_COUNTER_EN[9] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { return CsrFieldType::RW; @@ -97,9 +90,7 @@ fields: definedBy: Sscofpmf VSINH: location: 59 - description: - When set, mhpmcounter9 does not increment while the hart in operating - in VS-mode. + description: When set, mhpmcounter9 does not increment while the hart in operating in VS-mode. type(): | if ((HPM_COUNTER_EN[9]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; @@ -115,9 +106,7 @@ fields: definedBy: Sscofpmf VUINH: location: 58 - description: - When set, mhpmcounter9 does not increment while the hart in operating - in VU-mode. + description: When set, mhpmcounter9 does not increment while the hart in operating in VU-mode. type(): | if (HPM_COUNTER_EN[9] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { return CsrFieldType::RW; diff --git a/arch/csr/Zihpm/mhpmevent9h.yaml b/arch/csr/Zihpm/mhpmevent9h.yaml index 7383b28c30..946464b3b0 100644 --- a/arch/csr/Zihpm/mhpmevent9h.yaml +++ b/arch/csr/Zihpm/mhpmevent9h.yaml @@ -7,7 +7,6 @@ kind: csr name: mhpmevent9h long_name: Machine Hardware Performance Counter 9 Control, High half address: 0x729 -writeable: true priv_mode: M length: 32 base: 32 diff --git a/schemas/csr_schema.json b/schemas/csr_schema.json index fd159b4fad..352a8bea81 100644 --- a/schemas/csr_schema.json +++ b/schemas/csr_schema.json @@ -73,12 +73,22 @@ "alias": { "oneOf": [ { - "$ref": "schema_defs.json#/$defs/csr_name" + "$ref": "schema_defs.json#/$defs/csr_field" + }, + { + "$ref": "schema_defs.json#/$defs/csr_field_bits" }, { "type": "array", "items": { - "$ref": "schema_defs.json#/$defs/csr_name" + "oneOf": [ + { + "$ref": "schema_defs.json#/$defs/csr_field" + }, + { + "$ref": "schema_defs.json#/$defs/csr_field_bits" + } + ] } } ], diff --git a/schemas/schema_defs.json b/schemas/schema_defs.json index 5f7ae5ac26..934f79ab6f 100644 --- a/schemas/schema_defs.json +++ b/schemas/schema_defs.json @@ -22,6 +22,16 @@ "pattern": "^[a-z][a-z0-9_.]+$", "description": "CSR name" }, + "csr_field": { + "type": "string", + "pattern": "^[a-z][a-z0-9_.]+\\.[A-Z0-9]+$", + "description": "CSR field" + }, + "csr_field_bits": { + "type": "string", + "pattern": "^[a-z][a-z0-9_.]+\\.[A-Z0-9]+\\[[0-9]+(:[0-9]+)?\\]$", + "description": "CSR field" + }, "field_location": { "oneOf": [ { "type": "number", "description": "Location of a single bit" }, From f13a2227909d16bc5351a1dba4790705b384dd50 Mon Sep 17 00:00:00 2001 From: Derek Hower Date: Tue, 8 Apr 2025 08:02:12 -0700 Subject: [PATCH 11/15] refactor: small comment cleanup --- arch_overlay/qc_iu/inst/Xqci/qc.csrrwri.yaml | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch_overlay/qc_iu/inst/Xqci/qc.csrrwri.yaml b/arch_overlay/qc_iu/inst/Xqci/qc.csrrwri.yaml index f7c9d74985..51a721a182 100644 --- a/arch_overlay/qc_iu/inst/Xqci/qc.csrrwri.yaml +++ b/arch_overlay/qc_iu/inst/Xqci/qc.csrrwri.yaml @@ -41,6 +41,5 @@ operation(): | X[rd] = csr_sw_read(csr_addr); } # writes the zero-extended immediate to the CSR, - # performing any WARL transformations - # first + # performing any WARL transformations first csr_sw_write(csr, {{XLEN-5{1'b0}}, imm}); From a2a49a9d70b963b2e5552f4f8e9ec7f09be5cb16 Mon Sep 17 00:00:00 2001 From: Derek Hower Date: Tue, 15 Apr 2025 10:25:14 -0700 Subject: [PATCH 12/15] fix: make csr address at most MXLEN bits --- arch/isa/builtin_functions.idl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/isa/builtin_functions.idl b/arch/isa/builtin_functions.idl index aee4dc2fe7..b520d97685 100644 --- a/arch/isa/builtin_functions.idl +++ b/arch/isa/builtin_functions.idl @@ -33,7 +33,7 @@ struct Csr { Boolean valid; String name; CsrAddressType addr_type; - Bits<64> address; + Bits address; PrivilegeMode mode; Boolean writable; } From 6340f6aa20fe89e753e0f4335ee5302b2c128254 Mon Sep 17 00:00:00 2001 From: Derek Hower Date: Tue, 15 Apr 2025 10:54:56 -0700 Subject: [PATCH 13/15] fix: XLEN -> MXLEN in builtin_functions --- arch/isa/builtin_functions.idl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/isa/builtin_functions.idl b/arch/isa/builtin_functions.idl index aeb1a14fb4..d22ade2895 100644 --- a/arch/isa/builtin_functions.idl +++ b/arch/isa/builtin_functions.idl @@ -54,7 +54,7 @@ generated function direct_csr_lookup { generated function indirect_csr_lookup { returns Csr arguments - Bits csr_addr + Bits csr_addr description { Return CSR info for a CSR with indirect address +csr_addr+. @@ -85,7 +85,7 @@ generated function csr_sw_read { generated function csr_sw_write { arguments Csr csr, - Bits value + Bits value description { Writes +value+ to +csr+, applying an WARL transformations first. From b9e1407446b524e75e7af36a1d06d1ec08f1e9e0 Mon Sep 17 00:00:00 2001 From: Derek Hower Date: Tue, 29 Apr 2025 10:50:34 -0700 Subject: [PATCH 14/15] feat: add window slot for indirect csrs --- arch/isa/builtin_functions.idl | 8 +++++--- backends/cpp_hart_gen/templates/hart.hxx.erb | 18 +++++++++++------- 2 files changed, 16 insertions(+), 10 deletions(-) diff --git a/arch/isa/builtin_functions.idl b/arch/isa/builtin_functions.idl index d22ade2895..175fa55a42 100644 --- a/arch/isa/builtin_functions.idl +++ b/arch/isa/builtin_functions.idl @@ -33,7 +33,8 @@ struct Csr { Boolean valid; String name; CsrAddressType addr_type; - Bits address; + Bits address; # direct or indirect address + Bits<4> indirect_slot; # window slot, when addr_type == Indirect PrivilegeMode mode; Boolean writable; } @@ -54,9 +55,10 @@ generated function direct_csr_lookup { generated function indirect_csr_lookup { returns Csr arguments - Bits csr_addr + Bits csr_addr, + Bits<4> window_slot # 1-indexed "slot" in the window (corresponding to *ireg) description { - Return CSR info for a CSR with indirect address +csr_addr+. + Return CSR info for a CSR with indirect address +csr_addr+ at window slot +window_slot+. If no CSR exists, .valid == false } diff --git a/backends/cpp_hart_gen/templates/hart.hxx.erb b/backends/cpp_hart_gen/templates/hart.hxx.erb index 52c12d3faf..894f0a3295 100644 --- a/backends/cpp_hart_gen/templates/hart.hxx.erb +++ b/backends/cpp_hart_gen/templates/hart.hxx.erb @@ -237,16 +237,19 @@ namespace udb { csr_handle.name = csr->name(); csr_handle.addr_type = CsrAddressType::Direct; csr_handle.address = csr_addr; + csr_handle.window_slot = 0; csr_handle.mode = csr->mode(); csr_handle.writable = csr->writable(); return csr_handle; } } - <%= name_of(:struct, "Csr", cfg_arch) %> indirect_csr_lookup(const Bits<64>& csr_indirect_addr) { + <%= name_of(:struct, "Csr", cfg_arch) %> indirect_csr_lookup(const Bits<64>& csr_indirect_addr, const Bits<4>& window_slot) { <%= name_of(:struct, "Csr", cfg_arch) %> csr_handle; - auto csr = m_csr_indirect_addr_map.find(csr_addr); + udb_assert((window_slot > 0) && (window_slot <= 6), "Indirect slots must be between 1-6, inclusive"); + + auto csr = m_csr_indirect_addr_map.find(std::make_pair(csr_indirect_addr, window_slot)); if (csr == m_csr_indirect_addr_map.end()) { csr_handle.valid = false; return csr_handle; @@ -254,7 +257,8 @@ namespace udb { csr_handle.valid = true; csr_handle.name = csr->name(); csr_handle.addr_type = CsrAddressType::Indirect; - csr_handle.address = csr_addr; + csr_handle.address = csr_indirect_addr; + csr_handle.window_slot = window_slot; csr_handle.mode = csr->mode(); csr_handle.writable = csr->writable(); return csr_handle; @@ -267,7 +271,7 @@ namespace udb { udb_assert(csr != m_csr_addr_map.end(), "CSR not found"); return csr.hw_read(xlen()); } else { - auto csr = m_csr_indirect_addr_map.find(csr_handle.address); + auto csr = m_csr_indirect_addr_map.find(std::make_pair(csr_handle.address, csr_handle.indirect_slot)); udb_assert(csr != m_csr_indirect_addr_map.end(), "CSR not found"); return csr.hw_read(xlen()); } @@ -279,7 +283,7 @@ namespace udb { udb_assert(csr != m_csr_addr_map.end(), "CSR not found"); return csr.sw_read(xlen()); } else { - auto csr = m_csr_indirect_addr_map.find(csr_handle.address); + auto csr = m_csr_indirect_addr_map.find(std::make_pair(csr_handle.address, csr_handle.indirect_slot)); udb_assert(csr != m_csr_indirect_addr_map.end(), "CSR not found"); return csr.sw_read(xlen()); } @@ -291,7 +295,7 @@ namespace udb { udb_assert(csr != m_csr_addr_map.end(), "CSR not found"); return csr.sw_write(value, xlen()); } else { - auto csr = m_csr_indirect_addr_map.find(csr_handle.address); + auto csr = m_csr_indirect_addr_map.find(std::make_pair(csr_handle.address, csr_handle.indirect_slot)); udb_assert(csr != m_csr_indirect_addr_map.end(), "CSR not found"); return csr.sw_write(value, xlen()); } @@ -449,7 +453,7 @@ namespace udb { <%= name_of(:params, cfg_arch) %> m_params; <%= name_of(:csr_container, cfg_arch) %> m_csrs; std::unordered_map, CsrBase*> m_csr_addr_map; - std::unordered_map, CsrBase*> m_csr_indirect_addr_map; + std::unordered_map, Bits<4>>, CsrBase*> m_csr_indirect_addr_map; std::map m_csr_name_map; std::array m_run_one_inst_storage; From 99596619b5225f36e49fbc9844024b963b595e40 Mon Sep 17 00:00:00 2001 From: Derek Hower Date: Tue, 29 Apr 2025 11:26:06 -0700 Subject: [PATCH 15/15] fix: add indirect_address/slot to Csr model --- backends/cpp_hart_gen/templates/hart_impl.hxx.erb | 2 +- lib/arch_obj_models/csr.rb | 15 +++++++++++++++ 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/backends/cpp_hart_gen/templates/hart_impl.hxx.erb b/backends/cpp_hart_gen/templates/hart_impl.hxx.erb index 153ad656af..33230b50a7 100644 --- a/backends/cpp_hart_gen/templates/hart_impl.hxx.erb +++ b/backends/cpp_hart_gen/templates/hart_impl.hxx.erb @@ -44,7 +44,7 @@ namespace udb { m_csr_addr_map[<%= csr.address %>] = &m_csrs.<%= csr.name %>; <%- end -%> <%- unless csr.indirect_address.nil? -%> - m_csr_indirect_addr_map[<%= csr.indirect_address %>] = &m_csrs.<%= csr.name %>; + m_csr_indirect_addr_map[std::make_pair(<%= csr.indirect_address %>, <%= csr.indirect_slot %>)] = &m_csrs.<%= csr.name %>; <%_ end -%> m_csr_name_map["<%= csr.name %>"] = &m_csrs.<%= csr.name %>; <%- end -%> diff --git a/lib/arch_obj_models/csr.rb b/lib/arch_obj_models/csr.rb index d5dd82fb24..bd088c4ed4 100644 --- a/lib/arch_obj_models/csr.rb +++ b/lib/arch_obj_models/csr.rb @@ -22,6 +22,21 @@ def address @data["address"] end + # @return [Boolean] Whether or not the CSR can be accessed by indirect address + def indirect? + @data.key?("indirect_address") + end + + # @return [Integer] The indirect address + def indirect_address + @data["indirect_address"] + end + + # @return [Integer] The indirect window slot + def indirect_slot + @data["indirect_slot"] + end + # @return [String] Least-privileged mode that can access this CSR. One of ['m', 's', 'u', 'vs', 'vu'] def priv_mode @data["priv_mode"]