From 38e64d7542d75e912f16e649e97c38e161f78901 Mon Sep 17 00:00:00 2001
From: Katherine Hsu <2katherinehsu@gmail.com>
Date: Mon, 14 Apr 2025 17:47:11 +0000
Subject: [PATCH 01/24] add dcsr and dpc csrs

---
 arch/csr/dcsr.yaml | 218 +++++++++++++++++++++++++++++++++++++++++++++
 arch/csr/dpc.yaml  |  39 ++++++++
 2 files changed, 257 insertions(+)
 create mode 100644 arch/csr/dcsr.yaml
 create mode 100644 arch/csr/dpc.yaml

diff --git a/arch/csr/dcsr.yaml b/arch/csr/dcsr.yaml
new file mode 100644
index 0000000000..4849b369c5
--- /dev/null
+++ b/arch/csr/dcsr.yaml
@@ -0,0 +1,218 @@
+# yaml-language-server: $schema=../../schemas/csr_schema.json
+
+$schema: "csr_schema.json#"
+kind: csr
+name: dcsr
+long_name: Debug Control and Status Register
+address: 0x7B0
+priv_mode: M
+length: 32
+description: |
+  Upon entry into Debug Mode, v and prv are updated with the privilege level the hart was previously in,
+  and cause is updated with the reason for Debug Mode entry. Other than these fields and nmip, the
+  other fields of dcsr are only writable by the external debugger.
+
+  Priority of reasons for entering Debug Mode from highest to lowest is shown below.
+  5:: resethaltreq
+  6:: halt group
+  3:: haltreq
+  2:: trigger
+  1:: ebreak
+  4:: step
+
+  For compatibility with old versions of this spec, resethaltreq and
+  haltreq are allowed to be at different positions than shown as long as:
+  1. resethaltreq is higher priority than haltreq
+  2. the relative order of the other four causes is maintained
+
+  This CSR is read/write.
+
+definedBy: Sdext
+fields:
+  DEBUGVER:
+    location: 31-28
+    type: RO
+    description: |
+      0 (none):: There is no debug support.
+      4 (1.0):: Debug support exists as it is described in this document.
+      15 (custom):: There is debug support, but it does not conform to any available version of this spec.
+    reset_value: UNDEFINED_LEGAL
+  EXTCAUSE:
+    location: 26-24
+    type: RO
+    description: |
+      When cause is 7, this optional field contains the value of a more specific halt reason than "other."
+      Otherwise it contains 0.
+
+      0 (critical error):: The hart entered a critical error state, as defined in the Smdbltrp extension.
+
+      All other values are reserved for future versions of this spec, or for use by other RISC-V extensions.
+    reset_value: 0
+  CETRIG:
+    location: 19
+    type: RW
+    description: |
+      This bit is part of Smdbltrp and only exists when that extension is implemented.
+      0 (disabled):: A hart in a critical error state does not enter
+      Debug Mode but instead asserts the critical-error signal to
+      the platform.
+      1 (enabled):: A hart in a critical error state enters Debug
+      Mode instead of asserting the critical-error signal to the
+      platform. Upon such entry into Debug Mode, the cause
+      field is set to 7, and the extcause field is set to 0, indicating
+      a critical error triggered the Debug Mode entry. This cause
+      has the highest priority among all reasons for entering
+      Debug Mode. Resuming from Debug Mode following an
+      entry from the critical error state returns the hart to the
+      critical error state.
+
+      When cetrig is 1, resuming from Debug Mode following an entry due to a critical
+      error will result in an immediate re-entry into Debug Mode due to the critical error.
+      The debugger may resume with cetrig set to 0 to allow the platform defined actions on
+      critical-error signal to occur. Other possible actions include initiating a hart or platform
+      reset using the Debug Module reset control.
+    reset_value: 0
+  PELP:
+    location: 18
+    type: RW
+    description: |
+      This bit is part of Zicfilp and only exists when that extension is implemented.
+      0 (NO_LP_EXPECTED):: No landing pad instruction expected.
+      1 (LP_EXPECTED):: A landing pad instruction is expected.
+    reset_value: 0
+  EBREAKVS:
+    location: 17
+    type: RW
+    description: |
+      0 (exception):: ebreak instructions in VS-mode behave as described in the Privileged Spec.
+      1 (debug mode):: ebreak instructions in VS-mode enter Debug Mode.
+      This bit is hardwired to 0 if the hart does not support virtualization mode.
+    reset_value: 0
+  EBREAKVU:
+    location: 16
+    type: RW
+    description: |
+      0 (exception):: ebreak instructions in VU-mode behave as described in the Privileged Spec.
+      1 (debug mode):: ebreak instructions in VU-mode enter Debug Mode.
+      This bit is hardwired to 0 if the hart does not support virtualization mode.
+    reset_value: 0
+  EBREAKM:
+    location: 15
+    type: RW
+    description: |
+      0 (exception):: ebreak instructions in M-mode behave as described in the Privileged Spec.
+      1 (debug mode):: ebreak instructions in M-mode enter Debug Mode.
+    reset_value: 0
+  EBREAKS:
+    location: 13
+    type: RW
+    description: |
+      0 (exception):: ebreak instructions in S-mode behave as described in the Privileged Spec.
+      1 (debug mode):: ebreak instructions in S-mode enter Debug Mode.
+      This bit is hardwired to 0 if the hart does not support S-mode.
+    reset_value: 0
+  EBREAKU:
+    location: 12
+    type: RW
+    description: |
+      0 (exception):: ebreak instructions in U-mode behave as described in the Privileged Spec.
+      1 (debug mode):: ebreak instructions in U-mode enter Debug Mode.
+      This bit is hardwired to 0 if the hart does not support U-mode.
+    reset_value: 0
+  STEPIE:
+    location: 11
+    type: RW
+    description: |
+      0 (interrupts disabled):: Interrupts (including NMI) are disabled during single stepping with step set.
+      This value should be supported.
+      1 (interrupts enabled):: Interrupts (including NMI) are enabled during single stepping with step set.
+      Implementations may hard wire this bit to 0. In that case interrupt behavior can be emulated by the
+      debugger. The debugger must not change the value of this bit while the hart is running.
+    reset_value: 0
+  STOPCOUNT:
+    location: 10
+    type: RW
+    description: |
+      0 (normal):: Increment counters as usual.
+      1 (freeze):: Don’t increment any hart-local counters while in Debug Mode or on ebreak instructions
+      that cause entry into Debug Mode. These counters include the instret CSR. On single-hart cores cycle
+      should be stopped, but on multi-hart cores it must keep incrementing.
+      An implementation may hardwire this bit to 0 or 1.
+    reset_value: UNDEFINED_LEGAL
+  STOPTIME:
+    location: 9
+    type: RW
+    description: |
+      0 (normal):: time continues to reflect mtime.
+      1 (freeze):: time is frozen at the time that Debug Mode was entered. When leaving Debug Mode,
+      time will reflect the latest value of mtime again.
+      While all harts have stoptime=1 and are in Debug Mode, mtime is allowed to stop incrementing.
+      An implementation may hardwire this bit to 0 or 1.
+    reset_value: UNDEFINED_LEGAL
+  CAUSE:
+    location: 8-6
+    type: RO
+    description: |
+      Explains why Debug Mode was entered.
+      When there are multiple reasons to enter Debug Mode in a
+      single cycle, hardware should set cause to the cause with
+      the highest priority.
+      1 (ebreak):: An ebreak instruction was executed.
+      2 (trigger):: A Trigger Module trigger fired with action=1.
+      3 (haltreq):: The debugger requested entry to Debug Mode
+      using haltreq.
+      4 (step):: The hart single stepped because step was set.
+      5 (resethaltreq):: The hart halted directly out of reset due to
+      resethaltreq It is also acceptable to report 3 when this
+      happens.
+      6 (group):: The hart halted because it’s part of a halt group.
+      Harts may report 3 for this cause instead.
+      7 (other):: The hart halted for a reason other than the ones
+      mentioned above. extcause may contain a more specific
+      reason.
+    reset_value: 0
+  V:
+    location: 5
+    type: RW
+    description: |
+      Extends the prv field with the virtualization mode the hart was operating in
+      when Debug Mode was entered. A debugger can change this value to change the
+      hart’s virtualization mode when exiting Debug Mode. This bit is hardwired to 0 on harts
+      that do not support virtualization mode.
+    reset_value: 0
+  MPRVEN:
+    location: 4
+    type: RW
+    description: |
+      0 (disabled):: mprv in mstatus is ignored in Debug Mode.
+      1 (enabled):: mprv in mstatus takes effect in Debug Mode.
+      Implementing this bit is optional. It may be tied to either 0 or 1.
+    reset_value: UNDEFINED_LEGAL
+  NMIP:
+    location: 3
+    type: RO
+    description: |
+      When set, there is a Non-Maskable-Interrupt (NMI) pending for the hart.
+      Since an NMI can indicate a hardware error condition, reliable debugging
+      may no longer be possible once this bit becomes set. This is implementation-dependent.
+    reset_value: 0
+  STEP:
+    location: 2
+    type: RW
+    description: |
+      When set and not in Debug Mode, the hart will only execute a single instruction
+      and then enter Debug Mode.
+      The debugger must not change the value of this bit while the hart is running.
+    reset_value: 0
+  PRV:
+    location: 1-0
+    type: RW
+    description: |
+      Contains the privilege mode the hart was operating in when Debug Mode was entered.
+      A debugger can change this value to change the hart’s privilege mode when exiting
+      Debug Mode.
+
+      Not all privilege modes are supported on all harts. If the encoding written is not
+      supported or the debugger is not allowed to change to it, the hart may change to any
+      supported privilege mode.
+    reset_value: 3
diff --git a/arch/csr/dpc.yaml b/arch/csr/dpc.yaml
new file mode 100644
index 0000000000..36fea10816
--- /dev/null
+++ b/arch/csr/dpc.yaml
@@ -0,0 +1,39 @@
+# yaml-language-server: $schema=../../schemas/csr_schema.json
+
+$schema: "csr_schema.json#"
+kind: csr
+name: dpc
+long_name: Debug PC Register
+address: 0x7B1
+priv_mode: M
+length: XLEN
+description: |
+  Upon entry to debug mode, dpc is updated with the virtual address of the next instruction to be executed.
+
+  Executing the Program Buffer may cause the value of dpc to become UNSPECIFIED. If that is the case,
+  it must be possible to read/write dpc using an abstract command with postexec not set. The debugger
+  must attempt to save dpc between halting and executing a Program Buffer, and then restore dpc before
+  leaving Debug Mode.
+
+  If the Access Register abstract command supports reading dpc while the hart is running, then the
+  value read should be the address of a recently executed instruction.
+
+  If the Access Register abstract command supports writing dpc while the hart is running, then the
+  executing program should jump to the written address shortly after the write occurs.
+
+  The writability of dpc follows the same rules as mepc as defined in the Privileged Spec. In particular,
+  dpc must be able to hold all valid virtual addresses and the writability of the low bits depends on
+  IALIGN.
+
+  When resuming, the hart’s PC is updated to the virtual address stored in dpc. A debugger may write
+  dpc to change where the hart resumes.
+
+  This CSR is read/write.
+definedBy: Sdext
+fields:
+  DPC:
+    location_rv32: 31-0
+    location_rv64: 63-0
+    type: RW
+    description: DPC Value
+    reset_value: UNDEFINED_LEGAL

From 05af6871aa67753bb2fcf57bd28db8bcc0a8c588 Mon Sep 17 00:00:00 2001
From: Katherine Hsu <2katherinehsu@gmail.com>
Date: Mon, 12 May 2025 20:32:47 +0000
Subject: [PATCH 02/24] docs(debug csrs): change dcsr and dpc to D mode

---
 arch/csr/dcsr.yaml      | 2 +-
 arch/csr/dpc.yaml       | 2 +-
 arch/isa/globals.isa    | 1 +
 schemas/csr_schema.json | 2 +-
 4 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/csr/dcsr.yaml b/arch/csr/dcsr.yaml
index 4849b369c5..fed29ba637 100644
--- a/arch/csr/dcsr.yaml
+++ b/arch/csr/dcsr.yaml
@@ -5,7 +5,7 @@ kind: csr
 name: dcsr
 long_name: Debug Control and Status Register
 address: 0x7B0
-priv_mode: M
+priv_mode: D
 length: 32
 description: |
   Upon entry into Debug Mode, v and prv are updated with the privilege level the hart was previously in,
diff --git a/arch/csr/dpc.yaml b/arch/csr/dpc.yaml
index 36fea10816..8dcf7384f7 100644
--- a/arch/csr/dpc.yaml
+++ b/arch/csr/dpc.yaml
@@ -5,7 +5,7 @@ kind: csr
 name: dpc
 long_name: Debug PC Register
 address: 0x7B1
-priv_mode: M
+priv_mode: D
 length: XLEN
 description: |
   Upon entry to debug mode, dpc is updated with the virtual address of the next instruction to be executed.
diff --git a/arch/isa/globals.isa b/arch/isa/globals.isa
index 56e6d5e6ce..6cf226e87f 100644
--- a/arch/isa/globals.isa
+++ b/arch/isa/globals.isa
@@ -40,6 +40,7 @@ enum PrivilegeMode {
   U  0b000
   VS 0b101
   VU 0b100
+  D  0b1011
 }
 
 enum MemoryOperation {
diff --git a/schemas/csr_schema.json b/schemas/csr_schema.json
index ee55b58b01..5309b415de 100644
--- a/schemas/csr_schema.json
+++ b/schemas/csr_schema.json
@@ -248,7 +248,7 @@
         "virtual_address": true,
         "$comment": "Conditionally required; see below",
         "priv_mode": {
-          "enum": ["M", "S", "U", "VS"]
+          "enum": ["M", "S", "U", "VS", "D"]
         },
         "length": {
           "description": "Length, in bits, of the CSR. Can either be a 32, 64 or MXLEN, SXLEN, VSXLEN to indicate that it is dependent on the effective XLEN for a given mode. XLEN here refers to the effective XLEN in the current execution mode.",

From a5c6bab013c2fd02e8132739615205a410b0d87f Mon Sep 17 00:00:00 2001
From: Katherine Hsu <2katherinehsu@gmail.com>
Date: Tue, 13 May 2025 20:14:34 +0000
Subject: [PATCH 03/24] docs(debug csrs): add definedBy to fields

---
 arch/csr/dcsr.yaml | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/csr/dcsr.yaml b/arch/csr/dcsr.yaml
index fed29ba637..8e31fb05e9 100644
--- a/arch/csr/dcsr.yaml
+++ b/arch/csr/dcsr.yaml
@@ -51,6 +51,7 @@ fields:
   CETRIG:
     location: 19
     type: RW
+    definedBy: Smdbltrp
     description: |
       This bit is part of Smdbltrp and only exists when that extension is implemented.
       0 (disabled):: A hart in a critical error state does not enter
@@ -75,6 +76,7 @@ fields:
   PELP:
     location: 18
     type: RW
+    definedBy: Zicfilp
     description: |
       This bit is part of Zicfilp and only exists when that extension is implemented.
       0 (NO_LP_EXPECTED):: No landing pad instruction expected.
@@ -83,6 +85,7 @@ fields:
   EBREAKVS:
     location: 17
     type: RW
+    definedBy: H
     description: |
       0 (exception):: ebreak instructions in VS-mode behave as described in the Privileged Spec.
       1 (debug mode):: ebreak instructions in VS-mode enter Debug Mode.
@@ -91,6 +94,7 @@ fields:
   EBREAKVU:
     location: 16
     type: RW
+    definedBy: H
     description: |
       0 (exception):: ebreak instructions in VU-mode behave as described in the Privileged Spec.
       1 (debug mode):: ebreak instructions in VU-mode enter Debug Mode.
@@ -106,6 +110,7 @@ fields:
   EBREAKS:
     location: 13
     type: RW
+    definedBy: S
     description: |
       0 (exception):: ebreak instructions in S-mode behave as described in the Privileged Spec.
       1 (debug mode):: ebreak instructions in S-mode enter Debug Mode.
@@ -114,6 +119,7 @@ fields:
   EBREAKU:
     location: 12
     type: RW
+    definedBy: U
     description: |
       0 (exception):: ebreak instructions in U-mode behave as described in the Privileged Spec.
       1 (debug mode):: ebreak instructions in U-mode enter Debug Mode.
@@ -174,6 +180,7 @@ fields:
   V:
     location: 5
     type: RW
+    definedBy: H
     description: |
       Extends the prv field with the virtualization mode the hart was operating in
       when Debug Mode was entered. A debugger can change this value to change the

From c47a85046304683a2aaaa3ffd5da76f826906786 Mon Sep 17 00:00:00 2001
From: Katherine Hsu <2katherinehsu@gmail.com>
Date: Tue, 13 May 2025 20:19:21 +0000
Subject: [PATCH 04/24] docs(debug csrs): add DXLEN length type

---
 arch/csr/dpc.yaml       | 2 +-
 schemas/csr_schema.json | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/csr/dpc.yaml b/arch/csr/dpc.yaml
index 8dcf7384f7..b4cd257f3b 100644
--- a/arch/csr/dpc.yaml
+++ b/arch/csr/dpc.yaml
@@ -6,7 +6,7 @@ name: dpc
 long_name: Debug PC Register
 address: 0x7B1
 priv_mode: D
-length: XLEN
+length: DXLEN
 description: |
   Upon entry to debug mode, dpc is updated with the virtual address of the next instruction to be executed.
 
diff --git a/schemas/csr_schema.json b/schemas/csr_schema.json
index 5309b415de..b9588d4744 100644
--- a/schemas/csr_schema.json
+++ b/schemas/csr_schema.json
@@ -251,8 +251,8 @@
           "enum": ["M", "S", "U", "VS", "D"]
         },
         "length": {
-          "description": "Length, in bits, of the CSR. Can either be a 32, 64 or MXLEN, SXLEN, VSXLEN to indicate that it is dependent on the effective XLEN for a given mode. XLEN here refers to the effective XLEN in the current execution mode.",
-          "enum": [32, 64, "MXLEN", "SXLEN", "VSXLEN", "XLEN"]
+          "description": "Length, in bits, of the CSR. Can either be a 32, 64 or MXLEN, SXLEN, VSXLEN to indicate that it is dependent on the effective XLEN for a given mode. XLEN here refers to the effective XLEN in the current execution mode. DXLEN here refers is the Debug XLEN, which is the widest XLEN a hart supports, ignoring the current value of MXL in misa.",
+          "enum": [32, 64, "MXLEN", "SXLEN", "VSXLEN", "XLEN", "DXLEN"]
         },
         "requires": {
           "type": "string",

From 36de2864d721c4c26bb8141d32aa9e4379d8a606 Mon Sep 17 00:00:00 2001
From: Katherine Hsu <2katherinehsu@gmail.com>
Date: Tue, 13 May 2025 20:25:38 +0000
Subject: [PATCH 05/24] docs(debug csrs): fix privilege mode

---
 arch/csr/dpc.yaml    |  2 +-
 arch/isa/globals.isa | 17 ++++++++++-------
 2 files changed, 11 insertions(+), 8 deletions(-)

diff --git a/arch/csr/dpc.yaml b/arch/csr/dpc.yaml
index b4cd257f3b..051bf64ad8 100644
--- a/arch/csr/dpc.yaml
+++ b/arch/csr/dpc.yaml
@@ -35,5 +35,5 @@ fields:
     location_rv32: 31-0
     location_rv64: 63-0
     type: RW
-    description: DPC Value
+    description: Debug PC Value
     reset_value: UNDEFINED_LEGAL
diff --git a/arch/isa/globals.isa b/arch/isa/globals.isa
index 6cf226e87f..cc805f9e16 100644
--- a/arch/isa/globals.isa
+++ b/arch/isa/globals.isa
@@ -32,14 +32,17 @@ Bits<67> ILLEGAL_WLRL = 67'h40000000000000000;
 # maximum instruction encoding size
 U32 INSTR_ENC_SIZE = 32;
 
-# encoded as defined in the privilege spec
+# encoding defined by concatenation of { D, MPV, MPP }:
+# - D  : debug mode  (1b)
+# - MPV: mstatus.MPV (1b)
+# - MPP: mstatus.MPP (2b)
 enum PrivilegeMode {
-  M  0b011
-  S  0b001
-  HS 0b001 # alias for S when H extension is used
-  U  0b000
-  VS 0b101
-  VU 0b100
+  M  0b0011
+  S  0b0001
+  HS 0b0001 # alias for S when H extension is used
+  U  0b0000
+  VS 0b0101
+  VU 0b0100
   D  0b1011
 }
 

From fd39d4e6cae495381e73d786a0d921b50aee7641 Mon Sep 17 00:00:00 2001
From: Katherine Hsu <2katherinehsu@gmail.com>
Date: Thu, 15 May 2025 00:42:28 +0000
Subject: [PATCH 06/24] docs(debug csrs): add params and sw_write for checking
 MPRVEN implementation

---
 arch/csr/dcsr.yaml  | 4 ++++
 arch/ext/Sdext.yaml | 8 ++++++++
 2 files changed, 12 insertions(+)

diff --git a/arch/csr/dcsr.yaml b/arch/csr/dcsr.yaml
index 8e31fb05e9..8eb7b28829 100644
--- a/arch/csr/dcsr.yaml
+++ b/arch/csr/dcsr.yaml
@@ -195,6 +195,10 @@ fields:
       1 (enabled):: mprv in mstatus takes effect in Debug Mode.
       Implementing this bit is optional. It may be tied to either 0 or 1.
     reset_value: UNDEFINED_LEGAL
+    sw_write(csr_value): |
+      if (!MPRVEN_IMPLEMENTED) {
+        unimplemented_csr($encoding);
+      }
   NMIP:
     location: 3
     type: RO
diff --git a/arch/ext/Sdext.yaml b/arch/ext/Sdext.yaml
index 8cadccac1e..84cf822d04 100644
--- a/arch/ext/Sdext.yaml
+++ b/arch/ext/Sdext.yaml
@@ -11,3 +11,11 @@ versions:
   - version: "1.0.0"
     state: ratified
     ratification_date: null
+params:
+  MPRVEN_IMPLEMENTED:
+    description: |
+      Whether or not the MPRVEN field is implemented.
+      Implementation of the MPRVEN field in DCSR CSR is optional.
+      It may be tied to either 0 or 1.
+    schema:
+      type: boolean

From cc347680efd218e085865c0fafafbcd18272957e Mon Sep 17 00:00:00 2001
From: Katherine Hsu <2katherinehsu@gmail.com>
Date: Thu, 15 May 2025 00:45:26 +0000
Subject: [PATCH 07/24] docs(debug csrs): fix description

---
 arch/ext/Sdext.yaml | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/ext/Sdext.yaml b/arch/ext/Sdext.yaml
index 84cf822d04..254c48fbe5 100644
--- a/arch/ext/Sdext.yaml
+++ b/arch/ext/Sdext.yaml
@@ -14,8 +14,8 @@ versions:
 params:
   MPRVEN_IMPLEMENTED:
     description: |
-      Whether or not the MPRVEN field is implemented.
-      Implementation of the MPRVEN field in DCSR CSR is optional.
+      Whether or not the `MPRVEN` field is implemented.
+      Implementation of `CSR[dcsr].MPRVEN` is optional.
       It may be tied to either 0 or 1.
     schema:
       type: boolean

From ba6b5d479d88b6dfdc3980b7b17bd8963f42d1c3 Mon Sep 17 00:00:00 2001
From: Katherine Hsu <2katherinehsu@gmail.com>
Date: Fri, 23 May 2025 20:45:54 +0000
Subject: [PATCH 08/24] docs(debug csrs): fix MPRVEN param

---
 arch/csr/dcsr.yaml  |  4 ----
 arch/ext/Sdext.yaml | 14 +++++++++-----
 2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/arch/csr/dcsr.yaml b/arch/csr/dcsr.yaml
index 8eb7b28829..8e31fb05e9 100644
--- a/arch/csr/dcsr.yaml
+++ b/arch/csr/dcsr.yaml
@@ -195,10 +195,6 @@ fields:
       1 (enabled):: mprv in mstatus takes effect in Debug Mode.
       Implementing this bit is optional. It may be tied to either 0 or 1.
     reset_value: UNDEFINED_LEGAL
-    sw_write(csr_value): |
-      if (!MPRVEN_IMPLEMENTED) {
-        unimplemented_csr($encoding);
-      }
   NMIP:
     location: 3
     type: RO
diff --git a/arch/ext/Sdext.yaml b/arch/ext/Sdext.yaml
index 254c48fbe5..e14b9c9797 100644
--- a/arch/ext/Sdext.yaml
+++ b/arch/ext/Sdext.yaml
@@ -12,10 +12,14 @@ versions:
     state: ratified
     ratification_date: null
 params:
-  MPRVEN_IMPLEMENTED:
+  DCSR_MPRVEN_TYPE:
+    schema:
+      enum: [tied-to-0, tied-to-1, rw]
     description: |
-      Whether or not the `MPRVEN` field is implemented.
-      Implementation of `CSR[dcsr].MPRVEN` is optional.
+      Implementation of dcsr.MPRVEN is optional.
       It may be tied to either 0 or 1.
-    schema:
-      type: boolean
+
+      Behavior of the dcsr.MPRVEN bit:
+        * 'tied-to-0': tied to 0
+        * 'tied-to-1': tied to 1
+        * 'rw': read-write

From ee80efeba226f365efaa38ffb5cb0d1e1513e14a Mon Sep 17 00:00:00 2001
From: Katherine Hsu <2katherinehsu@gmail.com>
Date: Fri, 23 May 2025 21:13:34 +0000
Subject: [PATCH 09/24] docs(debug csrs): add type() and reset_value()

---
 arch/csr/dcsr.yaml | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/arch/csr/dcsr.yaml b/arch/csr/dcsr.yaml
index 8e31fb05e9..21f2cd189c 100644
--- a/arch/csr/dcsr.yaml
+++ b/arch/csr/dcsr.yaml
@@ -189,12 +189,24 @@ fields:
     reset_value: 0
   MPRVEN:
     location: 4
-    type: RW
     description: |
       0 (disabled):: mprv in mstatus is ignored in Debug Mode.
       1 (enabled):: mprv in mstatus takes effect in Debug Mode.
       Implementing this bit is optional. It may be tied to either 0 or 1.
-    reset_value: UNDEFINED_LEGAL
+    type(): |
+      if (DCSR_MPRVEN_TYPE == "tied-to-0" || DCSR_MPRVEN_TYPE == "tied-to-1") {
+        return CsrFieldType::R0;
+      } else if (DCSR_MPRVEN_TYPE == "rw") {
+        return CsrFieldType::RW;
+      }
+    reset_value(): |
+      if (DCSR_MPRVEN_TYPE == "tied-to-0") {
+        return 0;
+      } else if (DCSR_MPRVEN_TYPE == "tied-to-1") {
+        return 1
+      } else if (DCSR_MPRVEN_TYPE == "rw") {
+        return UNDEFINED_LEGAL;
+      }
   NMIP:
     location: 3
     type: RO

From beaeb61742845c72ca32f8b6f2601d2d73b8062c Mon Sep 17 00:00:00 2001
From: Katherine Hsu <2katherinehsu@gmail.com>
Date: Wed, 28 May 2025 05:22:28 +0000
Subject: [PATCH 10/24] docs(debug csr): add DXLEN to csr.rb

---
 lib/arch_obj_models/csr.rb | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/lib/arch_obj_models/csr.rb b/lib/arch_obj_models/csr.rb
index eb28631521..08e1f0b467 100644
--- a/lib/arch_obj_models/csr.rb
+++ b/lib/arch_obj_models/csr.rb
@@ -148,6 +148,8 @@ def dynamic_length?
       [nil, 3264].include?(cfg_arch.param_values["SXLEN"])) || \
       (cfg_arch.possible_extensions.map(&:name).include?("H") && \
       [nil, 3264].include?(cfg_arch.param_values["VSXLEN"]))
+    when "DXLEN"
+      cfg_arch.mxlen.nil?
     else
       raise "Unexpected length"
     end
@@ -157,7 +159,7 @@ def dynamic_length?
   # @return [Integer] Smallest length of the CSR in any mode
   def min_length
     case @data["length"]
-    when "MXLEN", "SXLEN", "VSXLEN", "XLEN"
+    when "MXLEN", "SXLEN", "VSXLEN", "XLEN", "DXLEN"
       @cfg_arch.possible_xlens.min
     when Integer
       @data["length"]
@@ -209,6 +211,8 @@ def length(effective_xlen = nil)
       end
     when "XLEN"
       effective_xlen
+    when "DXLEN"
+      effective_xlen
     when Integer
       @data["length"]
     else
@@ -279,6 +283,8 @@ def max_length
       else
         raise "Unexpected"
       end
+    when "DXLEN"
+      cfg_arch.mxlen || 64
     when Integer
       @data["length"]
     else
@@ -297,6 +303,8 @@ def length_cond32
       "CSR[hstatus].VSXL == 0"
     when "XLEN"
       "(priv_mode() == PrivilegeMode::M && CSR[misa].MXL == 0) || (priv_mode() == PrivilegeMode::S && CSR[mstatus].SXL == 0) || (priv_mode() == PrivilegeMode::VS && CSR[hstatus].VSXL == 0)"
+    when "DXLEN"
+      "CSR[misa].MXL == 0"
     else
       raise "Unexpected length #{@data['length']} for #{name}"
     end
@@ -313,6 +321,8 @@ def length_cond64
       "CSR[hstatus].VSXL == 1"
     when "XLEN"
       "(priv_mode() == PrivilegeMode::M && CSR[misa].MXL == 1) || (priv_mode() == PrivilegeMode::S && CSR[mstatus].SXL == 1) || (priv_mode() == PrivilegeMode::VS && CSR[hstatus].VSXL == 1)"
+    when "DXLEN"
+      "CSR[misa].MXL == 1"
     else
       raise "Unexpected length"
     end
@@ -333,6 +343,8 @@ def length_pretty(effective_xlen=nil)
           "CSR[hstatus].VSXL == %%"
         when "XLEN"
           "(priv_mode() == PrivilegeMode::M && CSR[misa].MXL == %%) || (priv_mode() == PrivilegeMode::S && CSR[mstatus].SXL == %%) || (priv_mode() == PrivilegeMode::VS && CSR[hstatus].VSXL == %%)"
+        when "DXLEN"
+          "CSR[misa].MXL == %%"
         else
           raise "Unexpected length '#{@data['length']}'"
         end

From d885542cd0655df69f9a1452754cc0e397a755a4 Mon Sep 17 00:00:00 2001
From: Katherine Hsu <2katherinehsu@gmail.com>
Date: Wed, 28 May 2025 23:29:25 +0000
Subject: [PATCH 11/24] docs(debug csrs): removed DXLEN

---
 arch/csr/dpc.yaml          |  2 +-
 lib/arch_obj_models/csr.rb | 14 +-------------
 schemas/csr_schema.json    |  4 ++--
 3 files changed, 4 insertions(+), 16 deletions(-)

diff --git a/arch/csr/dpc.yaml b/arch/csr/dpc.yaml
index 051bf64ad8..53ba7fcd7f 100644
--- a/arch/csr/dpc.yaml
+++ b/arch/csr/dpc.yaml
@@ -6,7 +6,7 @@ name: dpc
 long_name: Debug PC Register
 address: 0x7B1
 priv_mode: D
-length: DXLEN
+length: MXLEN
 description: |
   Upon entry to debug mode, dpc is updated with the virtual address of the next instruction to be executed.
 
diff --git a/lib/arch_obj_models/csr.rb b/lib/arch_obj_models/csr.rb
index 08e1f0b467..eb28631521 100644
--- a/lib/arch_obj_models/csr.rb
+++ b/lib/arch_obj_models/csr.rb
@@ -148,8 +148,6 @@ def dynamic_length?
       [nil, 3264].include?(cfg_arch.param_values["SXLEN"])) || \
       (cfg_arch.possible_extensions.map(&:name).include?("H") && \
       [nil, 3264].include?(cfg_arch.param_values["VSXLEN"]))
-    when "DXLEN"
-      cfg_arch.mxlen.nil?
     else
       raise "Unexpected length"
     end
@@ -159,7 +157,7 @@ def dynamic_length?
   # @return [Integer] Smallest length of the CSR in any mode
   def min_length
     case @data["length"]
-    when "MXLEN", "SXLEN", "VSXLEN", "XLEN", "DXLEN"
+    when "MXLEN", "SXLEN", "VSXLEN", "XLEN"
       @cfg_arch.possible_xlens.min
     when Integer
       @data["length"]
@@ -211,8 +209,6 @@ def length(effective_xlen = nil)
       end
     when "XLEN"
       effective_xlen
-    when "DXLEN"
-      effective_xlen
     when Integer
       @data["length"]
     else
@@ -283,8 +279,6 @@ def max_length
       else
         raise "Unexpected"
       end
-    when "DXLEN"
-      cfg_arch.mxlen || 64
     when Integer
       @data["length"]
     else
@@ -303,8 +297,6 @@ def length_cond32
       "CSR[hstatus].VSXL == 0"
     when "XLEN"
       "(priv_mode() == PrivilegeMode::M && CSR[misa].MXL == 0) || (priv_mode() == PrivilegeMode::S && CSR[mstatus].SXL == 0) || (priv_mode() == PrivilegeMode::VS && CSR[hstatus].VSXL == 0)"
-    when "DXLEN"
-      "CSR[misa].MXL == 0"
     else
       raise "Unexpected length #{@data['length']} for #{name}"
     end
@@ -321,8 +313,6 @@ def length_cond64
       "CSR[hstatus].VSXL == 1"
     when "XLEN"
       "(priv_mode() == PrivilegeMode::M && CSR[misa].MXL == 1) || (priv_mode() == PrivilegeMode::S && CSR[mstatus].SXL == 1) || (priv_mode() == PrivilegeMode::VS && CSR[hstatus].VSXL == 1)"
-    when "DXLEN"
-      "CSR[misa].MXL == 1"
     else
       raise "Unexpected length"
     end
@@ -343,8 +333,6 @@ def length_pretty(effective_xlen=nil)
           "CSR[hstatus].VSXL == %%"
         when "XLEN"
           "(priv_mode() == PrivilegeMode::M && CSR[misa].MXL == %%) || (priv_mode() == PrivilegeMode::S && CSR[mstatus].SXL == %%) || (priv_mode() == PrivilegeMode::VS && CSR[hstatus].VSXL == %%)"
-        when "DXLEN"
-          "CSR[misa].MXL == %%"
         else
           raise "Unexpected length '#{@data['length']}'"
         end
diff --git a/schemas/csr_schema.json b/schemas/csr_schema.json
index b9588d4744..5309b415de 100644
--- a/schemas/csr_schema.json
+++ b/schemas/csr_schema.json
@@ -251,8 +251,8 @@
           "enum": ["M", "S", "U", "VS", "D"]
         },
         "length": {
-          "description": "Length, in bits, of the CSR. Can either be a 32, 64 or MXLEN, SXLEN, VSXLEN to indicate that it is dependent on the effective XLEN for a given mode. XLEN here refers to the effective XLEN in the current execution mode. DXLEN here refers is the Debug XLEN, which is the widest XLEN a hart supports, ignoring the current value of MXL in misa.",
-          "enum": [32, 64, "MXLEN", "SXLEN", "VSXLEN", "XLEN", "DXLEN"]
+          "description": "Length, in bits, of the CSR. Can either be a 32, 64 or MXLEN, SXLEN, VSXLEN to indicate that it is dependent on the effective XLEN for a given mode. XLEN here refers to the effective XLEN in the current execution mode.",
+          "enum": [32, 64, "MXLEN", "SXLEN", "VSXLEN", "XLEN"]
         },
         "requires": {
           "type": "string",

From 0ee560a1a7c68b82e54b34f56d4a5de6f3e1d844 Mon Sep 17 00:00:00 2001
From: Katherine Hsu <2katherinehsu@gmail.com>
Date: Tue, 3 Jun 2025 02:12:07 +0000
Subject: [PATCH 12/24] docs(Sdext): fix CI failures

---
 arch/ext/Sdext.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/ext/Sdext.yaml b/arch/ext/Sdext.yaml
index e14b9c9797..5b86bca8bd 100644
--- a/arch/ext/Sdext.yaml
+++ b/arch/ext/Sdext.yaml
@@ -14,6 +14,7 @@ versions:
 params:
   DCSR_MPRVEN_TYPE:
     schema:
+      type: string
       enum: [tied-to-0, tied-to-1, rw]
     description: |
       Implementation of dcsr.MPRVEN is optional.

From 8a9525defb129b6894558ecaf1cbd9b3c56e18f0 Mon Sep 17 00:00:00 2001
From: Katherine Hsu <2katherinehsu@gmail.com>
Date: Tue, 3 Jun 2025 02:21:09 +0000
Subject: [PATCH 13/24] docs(dcsr): fix syntax error

---
 arch/csr/dcsr.yaml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/csr/dcsr.yaml b/arch/csr/dcsr.yaml
index 21f2cd189c..bbfb1923f4 100644
--- a/arch/csr/dcsr.yaml
+++ b/arch/csr/dcsr.yaml
@@ -195,7 +195,7 @@ fields:
       Implementing this bit is optional. It may be tied to either 0 or 1.
     type(): |
       if (DCSR_MPRVEN_TYPE == "tied-to-0" || DCSR_MPRVEN_TYPE == "tied-to-1") {
-        return CsrFieldType::R0;
+        return CsrFieldType::RO;
       } else if (DCSR_MPRVEN_TYPE == "rw") {
         return CsrFieldType::RW;
       }

From 51aafdef0f107270326184bcfe6e709505e32faa Mon Sep 17 00:00:00 2001
From: Katherine Hsu <2katherinehsu@gmail.com>
Date: Tue, 3 Jun 2025 02:22:03 +0000
Subject: [PATCH 14/24] docs(dcsr): fix syntax error

---
 arch/csr/dcsr.yaml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/csr/dcsr.yaml b/arch/csr/dcsr.yaml
index bbfb1923f4..45d6ce21ca 100644
--- a/arch/csr/dcsr.yaml
+++ b/arch/csr/dcsr.yaml
@@ -203,7 +203,7 @@ fields:
       if (DCSR_MPRVEN_TYPE == "tied-to-0") {
         return 0;
       } else if (DCSR_MPRVEN_TYPE == "tied-to-1") {
-        return 1
+        return 1;
       } else if (DCSR_MPRVEN_TYPE == "rw") {
         return UNDEFINED_LEGAL;
       }

From b4b3927919c943ebfda909025f02628c7142c36a Mon Sep 17 00:00:00 2001
From: Katherine Hsu <2katherinehsu@gmail.com>
Date: Tue, 3 Jun 2025 03:38:55 +0000
Subject: [PATCH 15/24] docs(debug mode): add D-mode to modes_with_access

---
 lib/arch_obj_models/csr.rb | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/lib/arch_obj_models/csr.rb b/lib/arch_obj_models/csr.rb
index eb28631521..f5341fa2be 100644
--- a/lib/arch_obj_models/csr.rb
+++ b/lib/arch_obj_models/csr.rb
@@ -361,6 +361,8 @@ def modes_with_access
       ["M", "S", "U", "VS", "VU"]
     when "VS"
       ["M", "S", "VS"]
+    when "D"
+      ["M", "D"]
     else
       raise "unexpected priv mode"
     end

From 3ec854b1698d403922c19035252026ac6a91931c Mon Sep 17 00:00:00 2001
From: Katherine Hsu <2katherinehsu@gmail.com>
Date: Tue, 3 Jun 2025 03:47:18 +0000
Subject: [PATCH 16/24] docs(debug mode): add D mode to multi_xlen_in_mode

---
 lib/cfg_arch.rb | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/lib/cfg_arch.rb b/lib/cfg_arch.rb
index f60ed1121d..b6d071d222 100644
--- a/lib/cfg_arch.rb
+++ b/lib/cfg_arch.rb
@@ -142,6 +142,8 @@ def multi_xlen_in_mode?(mode)
       else
         raise "Unexpected configuration state"
       end
+    when "D"
+      mxlen.nil?
     else
       raise ArgumentError, "Bad mode"
     end

From 871382bb552285f32e11cef7272260466766cec7 Mon Sep 17 00:00:00 2001
From: Katherine Hsu <2katherinehsu@gmail.com>
Date: Fri, 13 Jun 2025 17:00:14 +0000
Subject: [PATCH 17/24] docs(dcsr): add STEPIE, STOPCOUNT, and STOPTIME params

---
 arch/csr/dcsr.yaml  | 48 +++++++++++++++++++++++++++++++++++++++------
 arch/ext/Sdext.yaml | 38 ++++++++++++++++++++++++++++++++++-
 2 files changed, 79 insertions(+), 7 deletions(-)

diff --git a/arch/csr/dcsr.yaml b/arch/csr/dcsr.yaml
index 45d6ce21ca..c4410214d8 100644
--- a/arch/csr/dcsr.yaml
+++ b/arch/csr/dcsr.yaml
@@ -127,34 +127,70 @@ fields:
     reset_value: 0
   STEPIE:
     location: 11
-    type: RW
     description: |
       0 (interrupts disabled):: Interrupts (including NMI) are disabled during single stepping with step set.
       This value should be supported.
       1 (interrupts enabled):: Interrupts (including NMI) are enabled during single stepping with step set.
       Implementations may hard wire this bit to 0. In that case interrupt behavior can be emulated by the
       debugger. The debugger must not change the value of this bit while the hart is running.
-    reset_value: 0
+    type(): |
+      if (DCSR_STEPIE_TYPE == "tied-to-0" || DCSR_STEPIE_TYPE == "tied-to-1") {
+        return CsrFieldType::RO;
+      } else if (DCSR_STEPIE_TYPE == "rw") {
+        return CsrFieldType::RW;
+      }
+    reset_value(): |
+      if (DCSR_STEPIE_TYPE == "tied-to-0") {
+        return 0;
+      } else if (DCSR_STEPIE_TYPE == "tied-to-1") {
+        return 1;
+      } else if (DCSR_STEPIE_TYPE == "rw") {
+        return UNDEFINED_LEGAL;
+      }
   STOPCOUNT:
     location: 10
-    type: RW
     description: |
       0 (normal):: Increment counters as usual.
       1 (freeze):: Don’t increment any hart-local counters while in Debug Mode or on ebreak instructions
       that cause entry into Debug Mode. These counters include the instret CSR. On single-hart cores cycle
       should be stopped, but on multi-hart cores it must keep incrementing.
       An implementation may hardwire this bit to 0 or 1.
-    reset_value: UNDEFINED_LEGAL
+    type(): |
+      if (DCSR_STOPCOUNT_TYPE == "tied-to-0" || DCSR_STOPCOUNT_TYPE == "tied-to-1") {
+        return CsrFieldType::RO;
+      } else if (DCSR_STOPCOUNT_TYPE == "rw") {
+        return CsrFieldType::RW;
+      }
+    reset_value(): |
+      if (DCSR_STOPCOUNT_TYPE == "tied-to-0") {
+        return 0;
+      } else if (DCSR_STOPCOUNT_TYPE == "tied-to-1") {
+        return 1;
+      } else if (DCSR_STOPCOUNT_TYPE == "rw") {
+        return UNDEFINED_LEGAL;
+      }
   STOPTIME:
     location: 9
-    type: RW
     description: |
       0 (normal):: time continues to reflect mtime.
       1 (freeze):: time is frozen at the time that Debug Mode was entered. When leaving Debug Mode,
       time will reflect the latest value of mtime again.
       While all harts have stoptime=1 and are in Debug Mode, mtime is allowed to stop incrementing.
       An implementation may hardwire this bit to 0 or 1.
-    reset_value: UNDEFINED_LEGAL
+    type(): |
+      if (DCSR_STOPTIME_TYPE == "tied-to-0" || DCSR_STOPTIME_TYPE == "tied-to-1") {
+        return CsrFieldType::RO;
+      } else if (DCSR_STOPTIME_TYPE == "rw") {
+        return CsrFieldType::RW;
+      }
+    reset_value(): |
+      if (DCSR_STOPTIME_TYPE == "tied-to-0") {
+        return 0;
+      } else if (DCSR_STOPTIME_TYPE == "tied-to-1") {
+        return 1;
+      } else if (DCSR_STOPTIME_TYPE == "rw") {
+        return UNDEFINED_LEGAL;
+      }
   CAUSE:
     location: 8-6
     type: RO
diff --git a/arch/ext/Sdext.yaml b/arch/ext/Sdext.yaml
index 5b86bca8bd..6971850578 100644
--- a/arch/ext/Sdext.yaml
+++ b/arch/ext/Sdext.yaml
@@ -10,7 +10,7 @@ type: privileged
 versions:
   - version: "1.0.0"
     state: ratified
-    ratification_date: null
+    ratification_date: 2025-02
 params:
   DCSR_MPRVEN_TYPE:
     schema:
@@ -24,3 +24,39 @@ params:
         * 'tied-to-0': tied to 0
         * 'tied-to-1': tied to 1
         * 'rw': read-write
+  DCSR_STEPIE_TYPE:
+    schema:
+      type: string
+      enum: [tied-to-0, tied-to-1, rw]
+    description: |
+      Implementation of dcsr.STEPIE is optional.
+      It may be tied to either 0 or 1.
+
+      Behavior of the dcsr.STEPIE bit:
+        * 'tied-to-0': tied to 0
+        * 'tied-to-1': tied to 1
+        * 'rw': read-write
+  DCSR_STOPCOUNT_TYPE:
+    schema:
+      type: string
+      enum: [tied-to-0, tied-to-1, rw]
+    description: |
+      Implementation of dcsr.STOPCOUNT is optional.
+      It may be tied to either 0 or 1.
+
+      Behavior of the dcsr.STOPCOUNT bit:
+        * 'tied-to-0': tied to 0
+        * 'tied-to-1': tied to 1
+        * 'rw': read-write
+  DCSR_STOPTIME_TYPE:
+    schema:
+      type: string
+      enum: [tied-to-0, tied-to-1, rw]
+    description: |
+      Implementation of dcsr.STOPTIME is optional.
+      It may be tied to either 0 or 1.
+
+      Behavior of the dcsr.STOPTIME bit:
+        * 'tied-to-0': tied to 0
+        * 'tied-to-1': tied to 1
+        * 'rw': read-write

From fab9c494323584f8b6deb54186db812329b43dfe Mon Sep 17 00:00:00 2001
From: Katherine Hsu <2katherinehsu@gmail.com>
Date: Wed, 18 Jun 2025 13:54:04 +0000
Subject: [PATCH 18/24] docs(dcsr): add return statements

---
 arch/csr/dcsr.yaml | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/csr/dcsr.yaml b/arch/csr/dcsr.yaml
index c4410214d8..30004cbcae 100644
--- a/arch/csr/dcsr.yaml
+++ b/arch/csr/dcsr.yaml
@@ -139,6 +139,7 @@ fields:
       } else if (DCSR_STEPIE_TYPE == "rw") {
         return CsrFieldType::RW;
       }
+      return CsrFieldType::RW;
     reset_value(): |
       if (DCSR_STEPIE_TYPE == "tied-to-0") {
         return 0;
@@ -147,6 +148,7 @@ fields:
       } else if (DCSR_STEPIE_TYPE == "rw") {
         return UNDEFINED_LEGAL;
       }
+      return UNDEFINED_LEGAL;
   STOPCOUNT:
     location: 10
     description: |
@@ -161,6 +163,7 @@ fields:
       } else if (DCSR_STOPCOUNT_TYPE == "rw") {
         return CsrFieldType::RW;
       }
+      return CsrFieldType::RW;
     reset_value(): |
       if (DCSR_STOPCOUNT_TYPE == "tied-to-0") {
         return 0;
@@ -169,6 +172,7 @@ fields:
       } else if (DCSR_STOPCOUNT_TYPE == "rw") {
         return UNDEFINED_LEGAL;
       }
+      return UNDEFINED_LEGAL;
   STOPTIME:
     location: 9
     description: |
@@ -183,6 +187,7 @@ fields:
       } else if (DCSR_STOPTIME_TYPE == "rw") {
         return CsrFieldType::RW;
       }
+      return CsrFieldType::RW;
     reset_value(): |
       if (DCSR_STOPTIME_TYPE == "tied-to-0") {
         return 0;
@@ -191,6 +196,7 @@ fields:
       } else if (DCSR_STOPTIME_TYPE == "rw") {
         return UNDEFINED_LEGAL;
       }
+      return UNDEFINED_LEGAL;
   CAUSE:
     location: 8-6
     type: RO
@@ -235,6 +241,7 @@ fields:
       } else if (DCSR_MPRVEN_TYPE == "rw") {
         return CsrFieldType::RW;
       }
+      return CsrFieldType::RW;
     reset_value(): |
       if (DCSR_MPRVEN_TYPE == "tied-to-0") {
         return 0;
@@ -243,6 +250,7 @@ fields:
       } else if (DCSR_MPRVEN_TYPE == "rw") {
         return UNDEFINED_LEGAL;
       }
+      return UNDEFINED_LEGAL;
   NMIP:
     location: 3
     type: RO

From 1d4351b4f363360f152d8c33f0b03cfdf5a183cd Mon Sep 17 00:00:00 2001
From: Katherine Hsu <2katherinehsu@gmail.com>
Date: Thu, 19 Jun 2025 13:15:36 +0000
Subject: [PATCH 19/24] docs(dcsr): add asserts

---
 arch/csr/dcsr.yaml | 24 ++++++++----------------
 1 file changed, 8 insertions(+), 16 deletions(-)

diff --git a/arch/csr/dcsr.yaml b/arch/csr/dcsr.yaml
index 30004cbcae..834a4b3e7b 100644
--- a/arch/csr/dcsr.yaml
+++ b/arch/csr/dcsr.yaml
@@ -136,18 +136,16 @@ fields:
     type(): |
       if (DCSR_STEPIE_TYPE == "tied-to-0" || DCSR_STEPIE_TYPE == "tied-to-1") {
         return CsrFieldType::RO;
-      } else if (DCSR_STEPIE_TYPE == "rw") {
-        return CsrFieldType::RW;
       }
+      assert(DCSR_STEPIE_TYPE == "rw", "Unhandled DCSR_STEPIE_TYPE value");
       return CsrFieldType::RW;
     reset_value(): |
       if (DCSR_STEPIE_TYPE == "tied-to-0") {
         return 0;
       } else if (DCSR_STEPIE_TYPE == "tied-to-1") {
         return 1;
-      } else if (DCSR_STEPIE_TYPE == "rw") {
-        return UNDEFINED_LEGAL;
       }
+      assert(DCSR_STEPIE_TYPE == "rw", "Unhandled DCSR_STEPIE_TYPE value");
       return UNDEFINED_LEGAL;
   STOPCOUNT:
     location: 10
@@ -160,18 +158,16 @@ fields:
     type(): |
       if (DCSR_STOPCOUNT_TYPE == "tied-to-0" || DCSR_STOPCOUNT_TYPE == "tied-to-1") {
         return CsrFieldType::RO;
-      } else if (DCSR_STOPCOUNT_TYPE == "rw") {
-        return CsrFieldType::RW;
       }
+      assert(DCSR_STOPCOUNT_TYPE == "rw", "Unhandled DCSR_STOPCOUNT_TYPE value");
       return CsrFieldType::RW;
     reset_value(): |
       if (DCSR_STOPCOUNT_TYPE == "tied-to-0") {
         return 0;
       } else if (DCSR_STOPCOUNT_TYPE == "tied-to-1") {
         return 1;
-      } else if (DCSR_STOPCOUNT_TYPE == "rw") {
-        return UNDEFINED_LEGAL;
       }
+      assert(DCSR_STOPCOUNT_TYPE == "rw", "Unhandled DCSR_STOPCOUNT_TYPE value");
       return UNDEFINED_LEGAL;
   STOPTIME:
     location: 9
@@ -184,18 +180,16 @@ fields:
     type(): |
       if (DCSR_STOPTIME_TYPE == "tied-to-0" || DCSR_STOPTIME_TYPE == "tied-to-1") {
         return CsrFieldType::RO;
-      } else if (DCSR_STOPTIME_TYPE == "rw") {
-        return CsrFieldType::RW;
       }
+      assert(DCSR_STOPTIME_TYPE == "rw", "Unhandled DCSR_STOPTIME_TYPE value");
       return CsrFieldType::RW;
     reset_value(): |
       if (DCSR_STOPTIME_TYPE == "tied-to-0") {
         return 0;
       } else if (DCSR_STOPTIME_TYPE == "tied-to-1") {
         return 1;
-      } else if (DCSR_STOPTIME_TYPE == "rw") {
-        return UNDEFINED_LEGAL;
       }
+      assert(DCSR_STOPTIME_TYPE == "rw", "Unhandled DCSR_STOPTIME_TYPE value");
       return UNDEFINED_LEGAL;
   CAUSE:
     location: 8-6
@@ -238,18 +232,16 @@ fields:
     type(): |
       if (DCSR_MPRVEN_TYPE == "tied-to-0" || DCSR_MPRVEN_TYPE == "tied-to-1") {
         return CsrFieldType::RO;
-      } else if (DCSR_MPRVEN_TYPE == "rw") {
-        return CsrFieldType::RW;
       }
+      assert(DCSR_MPRVEN_TYPE == "rw", "Unhandled DCSR_MPRVEN_TYPE value");
       return CsrFieldType::RW;
     reset_value(): |
       if (DCSR_MPRVEN_TYPE == "tied-to-0") {
         return 0;
       } else if (DCSR_MPRVEN_TYPE == "tied-to-1") {
         return 1;
-      } else if (DCSR_MPRVEN_TYPE == "rw") {
-        return UNDEFINED_LEGAL;
       }
+      assert(DCSR_MPRVEN_TYPE == "rw", "Unhandled DCSR_MPRVEN_TYPE value");
       return UNDEFINED_LEGAL;
   NMIP:
     location: 3

From d360f7b454bfe37dab0a21bc3283440eb80afbe7 Mon Sep 17 00:00:00 2001
From: Katherine Hsu <2katherinehsu@gmail.com>
Date: Thu, 19 Jun 2025 13:20:10 +0000
Subject: [PATCH 20/24] docs(Sdext): change tied-to to read-only

---
 arch/csr/dcsr.yaml  | 24 ++++++++++++------------
 arch/ext/Sdext.yaml | 24 ++++++++++++------------
 2 files changed, 24 insertions(+), 24 deletions(-)

diff --git a/arch/csr/dcsr.yaml b/arch/csr/dcsr.yaml
index 834a4b3e7b..41e4010af5 100644
--- a/arch/csr/dcsr.yaml
+++ b/arch/csr/dcsr.yaml
@@ -134,15 +134,15 @@ fields:
       Implementations may hard wire this bit to 0. In that case interrupt behavior can be emulated by the
       debugger. The debugger must not change the value of this bit while the hart is running.
     type(): |
-      if (DCSR_STEPIE_TYPE == "tied-to-0" || DCSR_STEPIE_TYPE == "tied-to-1") {
+      if (DCSR_STEPIE_TYPE == "read-only-0" || DCSR_STEPIE_TYPE == "read-only-1") {
         return CsrFieldType::RO;
       }
       assert(DCSR_STEPIE_TYPE == "rw", "Unhandled DCSR_STEPIE_TYPE value");
       return CsrFieldType::RW;
     reset_value(): |
-      if (DCSR_STEPIE_TYPE == "tied-to-0") {
+      if (DCSR_STEPIE_TYPE == "read-only-0") {
         return 0;
-      } else if (DCSR_STEPIE_TYPE == "tied-to-1") {
+      } else if (DCSR_STEPIE_TYPE == "read-only-1") {
         return 1;
       }
       assert(DCSR_STEPIE_TYPE == "rw", "Unhandled DCSR_STEPIE_TYPE value");
@@ -156,15 +156,15 @@ fields:
       should be stopped, but on multi-hart cores it must keep incrementing.
       An implementation may hardwire this bit to 0 or 1.
     type(): |
-      if (DCSR_STOPCOUNT_TYPE == "tied-to-0" || DCSR_STOPCOUNT_TYPE == "tied-to-1") {
+      if (DCSR_STOPCOUNT_TYPE == "read-only-0" || DCSR_STOPCOUNT_TYPE == "read-only-1") {
         return CsrFieldType::RO;
       }
       assert(DCSR_STOPCOUNT_TYPE == "rw", "Unhandled DCSR_STOPCOUNT_TYPE value");
       return CsrFieldType::RW;
     reset_value(): |
-      if (DCSR_STOPCOUNT_TYPE == "tied-to-0") {
+      if (DCSR_STOPCOUNT_TYPE == "read-only-0") {
         return 0;
-      } else if (DCSR_STOPCOUNT_TYPE == "tied-to-1") {
+      } else if (DCSR_STOPCOUNT_TYPE == "read-only-1") {
         return 1;
       }
       assert(DCSR_STOPCOUNT_TYPE == "rw", "Unhandled DCSR_STOPCOUNT_TYPE value");
@@ -178,15 +178,15 @@ fields:
       While all harts have stoptime=1 and are in Debug Mode, mtime is allowed to stop incrementing.
       An implementation may hardwire this bit to 0 or 1.
     type(): |
-      if (DCSR_STOPTIME_TYPE == "tied-to-0" || DCSR_STOPTIME_TYPE == "tied-to-1") {
+      if (DCSR_STOPTIME_TYPE == "read-only-0" || DCSR_STOPTIME_TYPE == "read-only-1") {
         return CsrFieldType::RO;
       }
       assert(DCSR_STOPTIME_TYPE == "rw", "Unhandled DCSR_STOPTIME_TYPE value");
       return CsrFieldType::RW;
     reset_value(): |
-      if (DCSR_STOPTIME_TYPE == "tied-to-0") {
+      if (DCSR_STOPTIME_TYPE == "read-only-0") {
         return 0;
-      } else if (DCSR_STOPTIME_TYPE == "tied-to-1") {
+      } else if (DCSR_STOPTIME_TYPE == "read-only-1") {
         return 1;
       }
       assert(DCSR_STOPTIME_TYPE == "rw", "Unhandled DCSR_STOPTIME_TYPE value");
@@ -230,15 +230,15 @@ fields:
       1 (enabled):: mprv in mstatus takes effect in Debug Mode.
       Implementing this bit is optional. It may be tied to either 0 or 1.
     type(): |
-      if (DCSR_MPRVEN_TYPE == "tied-to-0" || DCSR_MPRVEN_TYPE == "tied-to-1") {
+      if (DCSR_MPRVEN_TYPE == "read-only-0" || DCSR_MPRVEN_TYPE == "read-only-1") {
         return CsrFieldType::RO;
       }
       assert(DCSR_MPRVEN_TYPE == "rw", "Unhandled DCSR_MPRVEN_TYPE value");
       return CsrFieldType::RW;
     reset_value(): |
-      if (DCSR_MPRVEN_TYPE == "tied-to-0") {
+      if (DCSR_MPRVEN_TYPE == "read-only-0") {
         return 0;
-      } else if (DCSR_MPRVEN_TYPE == "tied-to-1") {
+      } else if (DCSR_MPRVEN_TYPE == "read-only-1") {
         return 1;
       }
       assert(DCSR_MPRVEN_TYPE == "rw", "Unhandled DCSR_MPRVEN_TYPE value");
diff --git a/arch/ext/Sdext.yaml b/arch/ext/Sdext.yaml
index 6971850578..c9dafd3080 100644
--- a/arch/ext/Sdext.yaml
+++ b/arch/ext/Sdext.yaml
@@ -15,48 +15,48 @@ params:
   DCSR_MPRVEN_TYPE:
     schema:
       type: string
-      enum: [tied-to-0, tied-to-1, rw]
+      enum: [read-only-0, read-only-1, rw]
     description: |
       Implementation of dcsr.MPRVEN is optional.
       It may be tied to either 0 or 1.
 
       Behavior of the dcsr.MPRVEN bit:
-        * 'tied-to-0': tied to 0
-        * 'tied-to-1': tied to 1
+        * 'read-only-0': tied to 0
+        * 'read-only-1': tied to 1
         * 'rw': read-write
   DCSR_STEPIE_TYPE:
     schema:
       type: string
-      enum: [tied-to-0, tied-to-1, rw]
+      enum: [read-only-0, read-only-1, rw]
     description: |
       Implementation of dcsr.STEPIE is optional.
       It may be tied to either 0 or 1.
 
       Behavior of the dcsr.STEPIE bit:
-        * 'tied-to-0': tied to 0
-        * 'tied-to-1': tied to 1
+        * 'read-only-0': tied to 0
+        * 'read-only-1': tied to 1
         * 'rw': read-write
   DCSR_STOPCOUNT_TYPE:
     schema:
       type: string
-      enum: [tied-to-0, tied-to-1, rw]
+      enum: [read-only-0, read-only-1, rw]
     description: |
       Implementation of dcsr.STOPCOUNT is optional.
       It may be tied to either 0 or 1.
 
       Behavior of the dcsr.STOPCOUNT bit:
-        * 'tied-to-0': tied to 0
-        * 'tied-to-1': tied to 1
+        * 'read-only-0': tied to 0
+        * 'read-only-1': tied to 1
         * 'rw': read-write
   DCSR_STOPTIME_TYPE:
     schema:
       type: string
-      enum: [tied-to-0, tied-to-1, rw]
+      enum: [read-only-0, read-only-1, rw]
     description: |
       Implementation of dcsr.STOPTIME is optional.
       It may be tied to either 0 or 1.
 
       Behavior of the dcsr.STOPTIME bit:
-        * 'tied-to-0': tied to 0
-        * 'tied-to-1': tied to 1
+        * 'read-only-0': tied to 0
+        * 'read-only-1': tied to 1
         * 'rw': read-write

From e6b9c80e5d8f63e967a24c7c2ad445c6d06c0f64 Mon Sep 17 00:00:00 2001
From: Katherine Hsu <2katherinehsu@gmail.com>
Date: Fri, 20 Jun 2025 02:28:45 +0000
Subject: [PATCH 21/24] fix(debug csrs): file rebase

---
 {schemas => spec/schemas}/csr_schema.json                       | 0
 {arch => spec/std/isa}/csr/dcsr.yaml                            | 0
 {arch => spec/std/isa}/csr/dpc.yaml                             | 0
 {arch => spec/std/isa}/ext/Sdext.yaml                           | 0
 {arch => spec/std/isa}/isa/globals.isa                          | 0
 {lib => tools/ruby-gems/udb/lib/udb}/cfg_arch.rb                | 0
 {lib/arch_obj_models => tools/ruby-gems/udb/lib/udb/obj}/csr.rb | 0
 7 files changed, 0 insertions(+), 0 deletions(-)
 rename {schemas => spec/schemas}/csr_schema.json (100%)
 rename {arch => spec/std/isa}/csr/dcsr.yaml (100%)
 rename {arch => spec/std/isa}/csr/dpc.yaml (100%)
 rename {arch => spec/std/isa}/ext/Sdext.yaml (100%)
 rename {arch => spec/std/isa}/isa/globals.isa (100%)
 rename {lib => tools/ruby-gems/udb/lib/udb}/cfg_arch.rb (100%)
 rename {lib/arch_obj_models => tools/ruby-gems/udb/lib/udb/obj}/csr.rb (100%)

diff --git a/schemas/csr_schema.json b/spec/schemas/csr_schema.json
similarity index 100%
rename from schemas/csr_schema.json
rename to spec/schemas/csr_schema.json
diff --git a/arch/csr/dcsr.yaml b/spec/std/isa/csr/dcsr.yaml
similarity index 100%
rename from arch/csr/dcsr.yaml
rename to spec/std/isa/csr/dcsr.yaml
diff --git a/arch/csr/dpc.yaml b/spec/std/isa/csr/dpc.yaml
similarity index 100%
rename from arch/csr/dpc.yaml
rename to spec/std/isa/csr/dpc.yaml
diff --git a/arch/ext/Sdext.yaml b/spec/std/isa/ext/Sdext.yaml
similarity index 100%
rename from arch/ext/Sdext.yaml
rename to spec/std/isa/ext/Sdext.yaml
diff --git a/arch/isa/globals.isa b/spec/std/isa/isa/globals.isa
similarity index 100%
rename from arch/isa/globals.isa
rename to spec/std/isa/isa/globals.isa
diff --git a/lib/cfg_arch.rb b/tools/ruby-gems/udb/lib/udb/cfg_arch.rb
similarity index 100%
rename from lib/cfg_arch.rb
rename to tools/ruby-gems/udb/lib/udb/cfg_arch.rb
diff --git a/lib/arch_obj_models/csr.rb b/tools/ruby-gems/udb/lib/udb/obj/csr.rb
similarity index 100%
rename from lib/arch_obj_models/csr.rb
rename to tools/ruby-gems/udb/lib/udb/obj/csr.rb

From 39978d9ed2007f4830bd9ea667c1ec6f94fd4256 Mon Sep 17 00:00:00 2001
From: Katherine Hsu <67767297+neverlandiz@users.noreply.github.com>
Date: Fri, 20 Jun 2025 22:41:25 +0800
Subject: [PATCH 22/24] Update cfg_arch.rb

Signed-off-by: Katherine Hsu <67767297+neverlandiz@users.noreply.github.com>
---
 tools/ruby-gems/udb/lib/udb/cfg_arch.rb | 1 -
 1 file changed, 1 deletion(-)

diff --git a/tools/ruby-gems/udb/lib/udb/cfg_arch.rb b/tools/ruby-gems/udb/lib/udb/cfg_arch.rb
index 0c8d94aabc..809879d9c2 100644
--- a/tools/ruby-gems/udb/lib/udb/cfg_arch.rb
+++ b/tools/ruby-gems/udb/lib/udb/cfg_arch.rb
@@ -483,7 +483,6 @@ def initialize(name, config, arch_path)
         name: @name,
         csrs:
       )
-    
     overlay_path =
       if config.arch_overlay.nil?
         "/does/not/exist"

From 82fadef74ef8ea44fd0b97cb102af8b6ea8f40a2 Mon Sep 17 00:00:00 2001
From: Katherine Hsu <2katherinehsu@gmail.com>
Date: Fri, 20 Jun 2025 15:00:29 +0000
Subject: [PATCH 23/24] docs(debug csrs): add copyright and license information

---
 spec/std/isa/csr/dcsr.yaml | 3 +++
 spec/std/isa/csr/dpc.yaml  | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/spec/std/isa/csr/dcsr.yaml b/spec/std/isa/csr/dcsr.yaml
index 41e4010af5..cb734a3a42 100644
--- a/spec/std/isa/csr/dcsr.yaml
+++ b/spec/std/isa/csr/dcsr.yaml
@@ -1,3 +1,6 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
 # yaml-language-server: $schema=../../schemas/csr_schema.json
 
 $schema: "csr_schema.json#"
diff --git a/spec/std/isa/csr/dpc.yaml b/spec/std/isa/csr/dpc.yaml
index 53ba7fcd7f..75d682b3c0 100644
--- a/spec/std/isa/csr/dpc.yaml
+++ b/spec/std/isa/csr/dpc.yaml
@@ -1,3 +1,6 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
 # yaml-language-server: $schema=../../schemas/csr_schema.json
 
 $schema: "csr_schema.json#"

From 0edfaf8c94217a467b908474cac88f8cb109aa85 Mon Sep 17 00:00:00 2001
From: Katherine Hsu <2katherinehsu@gmail.com>
Date: Fri, 20 Jun 2025 15:26:24 +0000
Subject: [PATCH 24/24] fix(debug csrs): edit copyright information

---
 spec/std/isa/csr/dcsr.yaml | 2 +-
 spec/std/isa/csr/dpc.yaml  | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/spec/std/isa/csr/dcsr.yaml b/spec/std/isa/csr/dcsr.yaml
index cb734a3a42..9c38bf7fa8 100644
--- a/spec/std/isa/csr/dcsr.yaml
+++ b/spec/std/isa/csr/dcsr.yaml
@@ -1,4 +1,4 @@
-# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# Copyright (c) Katherine Hsu
 # SPDX-License-Identifier: BSD-3-Clause-Clear
 
 # yaml-language-server: $schema=../../schemas/csr_schema.json
diff --git a/spec/std/isa/csr/dpc.yaml b/spec/std/isa/csr/dpc.yaml
index 75d682b3c0..b740449253 100644
--- a/spec/std/isa/csr/dpc.yaml
+++ b/spec/std/isa/csr/dpc.yaml
@@ -1,4 +1,4 @@
-# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# Copyright (c) Katherine Hsu
 # SPDX-License-Identifier: BSD-3-Clause-Clear
 
 # yaml-language-server: $schema=../../schemas/csr_schema.json