diff --git a/arch/inst/I/addi.yaml b/arch/inst/I/addi.yaml index 877d9b2c84..daee7ec778 100644 --- a/arch/inst/I/addi.yaml +++ b/arch/inst/I/addi.yaml @@ -22,6 +22,11 @@ access: vs: always vu: always data_independent_timing: true +pseudoinstructions: + - when: (xd == 0 && xs1 == 0 && imm == 0) + to: nop + - when: imm == 0 + to: mv xd,xs1 operation(): X[xd] = X[xs1] + $signed(imm); # SPDX-SnippetBegin diff --git a/arch/inst/I/addiw.yaml b/arch/inst/I/addiw.yaml index e90d820d25..3a4cd77ee5 100644 --- a/arch/inst/I/addiw.yaml +++ b/arch/inst/I/addiw.yaml @@ -23,6 +23,9 @@ access: vs: always vu: always data_independent_timing: true +pseudoinstructions: + - when: imm == 0 + to: sext.w xd,xs1 operation(): | XReg operand = sext(X[xs1], 31); X[xd] = sext(operand + imm, 31); diff --git a/arch/inst/I/andi.yaml b/arch/inst/I/andi.yaml index 0a2ae71ca4..60d1e86d5a 100644 --- a/arch/inst/I/andi.yaml +++ b/arch/inst/I/andi.yaml @@ -22,6 +22,9 @@ access: vs: always vu: always data_independent_timing: true +pseudoinstructions: + - when: imm == 255 + to: zext.b operation(): X[xd] = X[xs1] & $signed(imm); # SPDX-SnippetBegin diff --git a/arch/inst/I/beq.yaml b/arch/inst/I/beq.yaml index b13ef7bea6..d44159906c 100644 --- a/arch/inst/I/beq.yaml +++ b/arch/inst/I/beq.yaml @@ -26,6 +26,9 @@ access: u: always vs: always vu: always +pseudoinstructions: + - when: xs2 == 0 + to: beqz xs1,imm operation(): | XReg lhs = X[xs1]; XReg rhs = X[xs2]; diff --git a/arch/inst/I/bge.yaml b/arch/inst/I/bge.yaml index dd13a84623..55c4972ce8 100644 --- a/arch/inst/I/bge.yaml +++ b/arch/inst/I/bge.yaml @@ -26,6 +26,11 @@ access: u: always vs: always vu: always +pseudoinstructions: + - when: xs1 == 0 + to: blez xs2,imm + - when: xs2 == 0 + to: blez xs1,imm operation(): | XReg lhs = X[xs1]; XReg rhs = X[xs2]; diff --git a/arch/inst/I/blt.yaml b/arch/inst/I/blt.yaml index d8558e2599..1f2419159b 100644 --- a/arch/inst/I/blt.yaml +++ b/arch/inst/I/blt.yaml @@ -26,6 +26,11 @@ access: u: always vs: always vu: always +pseudoinstructions: + - when: xs2 == 0 + to: bltz xs1,imm + - when: xs1 == 0 + to: bgtz xs2,imm operation(): | XReg lhs = X[xs1]; XReg rhs = X[xs2]; diff --git a/arch/inst/I/bne.yaml b/arch/inst/I/bne.yaml index e48ed35d7b..164e0ce601 100644 --- a/arch/inst/I/bne.yaml +++ b/arch/inst/I/bne.yaml @@ -26,6 +26,9 @@ access: u: always vs: always vu: always +pseudoinstructions: + - when: xs2 == 0 + to: bnez xs1,imm operation(): | XReg lhs = X[xs1]; XReg rhs = X[xs2]; diff --git a/arch/inst/I/fence.yaml b/arch/inst/I/fence.yaml index ec761d8829..4a0abfbabf 100644 --- a/arch/inst/I/fence.yaml +++ b/arch/inst/I/fence.yaml @@ -198,6 +198,8 @@ hints: pseudoinstructions: - when: (pred == 1) && (succ == 0) && (xd == 0) && (xs1 == 0) to: pause + - when: (pred == 4'b1111) && (succ == 4'b1111) + to: fence # fence => fence iorw,iorw # SPDX-SnippetBegin # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model diff --git a/arch/inst/I/jal.yaml b/arch/inst/I/jal.yaml index 86ce90b83d..0d503e3974 100644 --- a/arch/inst/I/jal.yaml +++ b/arch/inst/I/jal.yaml @@ -23,6 +23,11 @@ access: u: always vs: always vu: always +pseudoinstructions: + - when: imm == 0 + to: j xd + - when: xd == x1 + to: jal imm operation(): | XReg retrun_addr = $pc + 4; diff --git a/arch/inst/I/jalr.yaml b/arch/inst/I/jalr.yaml index 56a5eb2ed1..f40a3c44ea 100644 --- a/arch/inst/I/jalr.yaml +++ b/arch/inst/I/jalr.yaml @@ -25,6 +25,11 @@ access: u: always vs: always vu: always +pseudoinstructions: + - when: xd == 0 + to: jr imm(xs1) + - when: (rd == 0 && xs1 == x1 && imm == 0) + to: ret operation(): | XReg returnaddr; returnaddr = $pc + 4; diff --git a/arch/inst/I/slt.yaml b/arch/inst/I/slt.yaml index 574bc1c72a..d7dff9b699 100644 --- a/arch/inst/I/slt.yaml +++ b/arch/inst/I/slt.yaml @@ -24,6 +24,11 @@ access: vs: always vu: always data_independent_timing: true +pseudoinstructions: + - when: xs2 == 0 + to: sltz xd,xs1 + - when: xs1 == 0 + to: sgtz xd,xs2 operation(): | XReg src1 = X[xs1]; XReg src2 = X[xs2]; diff --git a/arch/inst/I/sltiu.yaml b/arch/inst/I/sltiu.yaml index bfb9fa851f..f2162219d0 100644 --- a/arch/inst/I/sltiu.yaml +++ b/arch/inst/I/sltiu.yaml @@ -28,6 +28,9 @@ access: vs: always vu: always data_independent_timing: true +pseudoinstructions: + - when: imm == 1 + to: seqz xd,xs1 operation(): | Bits sign_extend_imm = $signed(imm); X[xd] = (X[xs1] < sign_extend_imm) ? 1 : 0; diff --git a/arch/inst/I/sltu.yaml b/arch/inst/I/sltu.yaml index f054d625f5..06d9c1d7a0 100644 --- a/arch/inst/I/sltu.yaml +++ b/arch/inst/I/sltu.yaml @@ -24,6 +24,9 @@ access: vs: always vu: always data_independent_timing: true +pseudoinstructions: + - when: xs1 == 0 + to: snez xd,xs2 operation(): | X[xd] = (X[xs1] < X[xs2]) ? 1 : 0; diff --git a/arch/inst/I/sub.yaml b/arch/inst/I/sub.yaml index 27d1f977c1..d0440b6149 100644 --- a/arch/inst/I/sub.yaml +++ b/arch/inst/I/sub.yaml @@ -22,6 +22,9 @@ access: vs: always vu: always data_independent_timing: true +pseudoinstructions: + - when: xs1 == 0 + to: neg xd,xs2 operation(): | XReg t0 = X[xs1]; XReg t1 = X[xs2]; diff --git a/arch/inst/I/subw.yaml b/arch/inst/I/subw.yaml index 7e92744bd0..20b5e0d8cc 100644 --- a/arch/inst/I/subw.yaml +++ b/arch/inst/I/subw.yaml @@ -23,6 +23,9 @@ access: vs: always vu: always data_independent_timing: true +pseudoinstructions: + - when: xs1 == 0 + to: negw xd,xs2 operation(): | Bits<32> t0 = X[xs1][31:0]; Bits<32> t1 = X[xs2][31:0]; diff --git a/arch/inst/I/xori.yaml b/arch/inst/I/xori.yaml index 02e637c58d..ce231b50cf 100644 --- a/arch/inst/I/xori.yaml +++ b/arch/inst/I/xori.yaml @@ -22,6 +22,9 @@ access: vs: always vu: always data_independent_timing: true +pseudoinstructions: + - when: $signed(imm) == -1 + to: not xd,xs1 operation(): X[xd] = X[xs1] ^ $signed(imm); # SPDX-SnippetBegin diff --git a/arch/inst/Zicsr/csrrc.yaml b/arch/inst/Zicsr/csrrc.yaml index b0ee71c340..ec84a42461 100644 --- a/arch/inst/Zicsr/csrrc.yaml +++ b/arch/inst/Zicsr/csrrc.yaml @@ -23,6 +23,9 @@ access: vs: always vu: always data_independent_timing: false +pseudoinstructions: + - when: xd == 0 + to: csrc csr,xs1 operation(): | Csr csr_handle = direct_csr_lookup(csr); diff --git a/arch/inst/Zicsr/csrrci.yaml b/arch/inst/Zicsr/csrrci.yaml index d29e427d2c..16187e854d 100644 --- a/arch/inst/Zicsr/csrrci.yaml +++ b/arch/inst/Zicsr/csrrci.yaml @@ -7,7 +7,7 @@ long_name: No synopsis available description: | No description available. definedBy: Zicsr -assembly: rd, imm, rs1 +assembly: xd, csr, uimm encoding: match: -----------------111-----1110011 variables: @@ -23,6 +23,9 @@ access: vs: always vu: always data_independent_timing: false +pseudoinstructions: + - when: xd == 0 + to: csrci csr,uimm operation(): | Boolean will_write = uimm != 0; diff --git a/arch/inst/Zicsr/csrrs.yaml b/arch/inst/Zicsr/csrrs.yaml index 7c308eab56..30871b8e0b 100644 --- a/arch/inst/Zicsr/csrrs.yaml +++ b/arch/inst/Zicsr/csrrs.yaml @@ -8,9 +8,9 @@ description: | Atomically read and set bits in a CSR. Reads the value of the CSR, zero-extends the value to `XLEN` bits, - and writes it to integer register `rd`. The initial value in integer - register `rs1` is treated as a bit mask that specifies bit positions - to be set in the CSR. Any bit that is high in `rs1` will cause the + and writes it to integer register `xd`. The initial value in integer + register `xs1` is treated as a bit mask that specifies bit positions + to be set in the CSR. Any bit that is high in `xs1` will cause the corresponding bit to be set in the CSR, if that CSR bit is writable. Other bits in the CSR are not explicitly written. definedBy: Zicsr @@ -20,17 +20,22 @@ encoding: variables: - name: csr location: 31-20 - - name: rs1 + - name: xs1 location: 19-15 - - name: rd + - name: xd location: 11-7 access: s: always u: always vs: always vu: always +pseudoinstructions: + - when: xs1 == 0 + to: csrr xd,csr + - when: xd == 0 + to: csrs csr,xs1 operation(): | - Boolean will_write = rs1 != 0; + Boolean will_write = xs1 != 0; Csr csr_handle = direct_csr_lookup(csr); @@ -48,11 +53,11 @@ operation(): | if (will_write) { # set bits using the mask # performing any WARL transformations first - XReg mask = X[rs1]; + XReg mask = X[xs1]; csr_sw_write(csr_handle, initial_csr_value | mask); } - X[rd] = initial_csr_value; + X[xd] = initial_csr_value; # SPDX-SnippetBegin # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model diff --git a/arch/inst/Zicsr/csrrsi.yaml b/arch/inst/Zicsr/csrrsi.yaml index 4734fb3fd2..197783a9ce 100644 --- a/arch/inst/Zicsr/csrrsi.yaml +++ b/arch/inst/Zicsr/csrrsi.yaml @@ -7,7 +7,7 @@ long_name: No synopsis available description: | No description available. definedBy: Zicsr -assembly: rd, imm, rs1 +assembly: xd, csr, uimm encoding: match: -----------------110-----1110011 variables: @@ -23,6 +23,9 @@ access: vs: always vu: always data_independent_timing: false +pseudoinstructions: + - when: xd == 0 + to: csrsi csr,uimm operation(): | Boolean will_write = uimm != 0; diff --git a/arch/inst/Zicsr/csrrw.yaml b/arch/inst/Zicsr/csrrw.yaml index 0179397948..794b76eebe 100644 --- a/arch/inst/Zicsr/csrrw.yaml +++ b/arch/inst/Zicsr/csrrw.yaml @@ -8,9 +8,9 @@ description: | Atomically swap values in the CSRs and integer registers. Read the old value of the CSR, zero-extends the value to `XLEN` bits, - and then write it to integer register rd. - The initial value in rs1 is written to the CSR. - If `rd=x0`, then the instruction shall not read the CSR and shall not + and then write it to integer register xd. + The initial value in xs1 is written to the CSR. + If `xd=x0`, then the instruction shall not read the CSR and shall not cause any of the side effects that might occur on a CSR read. definedBy: Zicsr assembly: xd, imm, xs1 @@ -28,6 +28,9 @@ access: u: always vs: always vu: always +pseudoinstructions: + - when: xd == 0 + to: csrw csr,xs1 operation(): | Csr csr_handle = direct_csr_lookup(csr); diff --git a/arch/inst/Zicsr/csrrwi.yaml b/arch/inst/Zicsr/csrrwi.yaml index e35113f859..9f1ad8c4ae 100644 --- a/arch/inst/Zicsr/csrrwi.yaml +++ b/arch/inst/Zicsr/csrrwi.yaml @@ -5,15 +5,15 @@ kind: instruction name: csrrwi long_name: Atomic Read/Write CSR Immediate description: | - Atomically write CSR using a 5-bit immediate, and load the previous value into 'rd'. + Atomically write CSR using a 5-bit immediate, and load the previous value into 'xd'. Read the old value of the CSR, zero-extends the value to `XLEN` bits, - and then write it to integer register rd. + and then write it to integer register xd. The 5-bit uimm field is zero-extended and written to the CSR. - If `rd=x0`, then the instruction shall not read the CSR and shall not + If `xd=x0`, then the instruction shall not read the CSR and shall not cause any of the side effects that might occur on a CSR read. definedBy: Zicsr -assembly: rd, imm, rs1 +assembly: xd, imm, xs1 encoding: match: -----------------101-----1110011 variables: @@ -21,13 +21,16 @@ encoding: location: 31-20 - name: imm location: 19-15 - - name: rd + - name: xd location: 11-7 access: s: always u: always vs: always vu: always +pseudoinstructions: + - when: xd == 0 + to: csrwi csr,imm operation(): | Csr csr_handle = direct_csr_lookup(csr); @@ -40,8 +43,8 @@ operation(): | raise (ExceptionCode::IllegalInstruction, mode(), $encoding); } - if (rd != 0) { - X[rd] = csr_sw_read(csr_handle); + if (xd != 0) { + X[xd] = csr_sw_read(csr_handle); } # writes the zero-extended immediate to the CSR,