diff --git a/arch_overlay/qc_iu/ext/Xqci.yaml b/arch_overlay/qc_iu/ext/Xqci.yaml index 948ce32bad..15eda53efd 100644 --- a/arch_overlay/qc_iu/ext/Xqci.yaml +++ b/arch_overlay/qc_iu/ext/Xqci.yaml @@ -385,7 +385,7 @@ versions: - { name: Xqcili, version: "0.2.0" } - { name: Xqcilia, version: "0.2.0" } - { name: Xqcilo, version: "0.3.0" } - - { name: Xqcilsm, version: "0.6.0" } + - { name: Xqcilsm, version: "0.5.0" } - { name: Xqcisim, version: "0.2.0" } - { name: Xqcisls, version: "0.2.0" } - { name: Xqcisync, version: "0.3.0" } @@ -421,7 +421,43 @@ versions: - { name: Xqcili, version: "0.2.0" } - { name: Xqcilia, version: "0.2.0" } - { name: Xqcilo, version: "0.3.0" } - - { name: Xqcilsm, version: "0.5.0" } + - { name: Xqcilsm, version: "0.6.0" } + - { name: Xqcisim, version: "0.2.0" } + - { name: Xqcisls, version: "0.2.0" } + - { name: Xqcisync, version: "0.3.0" } + requires: + name: Zca + version: ">= 1.0.0" +- version: "0.13.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com + changes: + - Fix version history of releases v0.11.0 and v0.12.0 + - Fix description and IDL code of qc.csrrwr instruction to allow just read CSR + - Fix IDL code of qc.c.mileaveret instruction to avoid restoring from stack NMIP and EXCP bits + implies: + - { name: Xqcia, version: "0.7.0" } + - { name: Xqciac, version: "0.3.0" } + - { name: Xqcibi, version: "0.2.0" } + - { name: Xqcibm, version: "0.8.0" } + - { name: Xqcicli, version: "0.3.0" } + - { name: Xqcicm, version: "0.2.0" } + - { name: Xqcics, version: "0.2.0" } + - { name: Xqcicsr, version: "0.4.0" } + - { name: Xqciint, version: "0.10.0" } + - { name: Xqciio, version: "0.1.0" } + - { name: Xqcilb, version: "0.2.0" } + - { name: Xqcili, version: "0.2.0" } + - { name: Xqcilia, version: "0.2.0" } + - { name: Xqcilo, version: "0.3.0" } + - { name: Xqcilsm, version: "0.6.0" } - { name: Xqcisim, version: "0.2.0" } - { name: Xqcisls, version: "0.2.0" } - { name: Xqcisync, version: "0.3.0" } diff --git a/arch_overlay/qc_iu/ext/Xqcicsr.yaml b/arch_overlay/qc_iu/ext/Xqcicsr.yaml index 408922df62..4be9833878 100644 --- a/arch_overlay/qc_iu/ext/Xqcicsr.yaml +++ b/arch_overlay/qc_iu/ext/Xqcicsr.yaml @@ -40,6 +40,18 @@ versions: email: dhower@qti.qualcomm.com changes: - Remove qc.flags CSR +- version: "0.4.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com + changes: + - Fix description and IDL code of qc.csrrwr instruction to allow just read CSR description: | The Xqcicsr extension contains two instructions to read/write CSR which index is in register and not immediate. diff --git a/arch_overlay/qc_iu/ext/Xqciint.yaml b/arch_overlay/qc_iu/ext/Xqciint.yaml index a4625ded97..c7d0a1517e 100644 --- a/arch_overlay/qc_iu/ext/Xqciint.yaml +++ b/arch_overlay/qc_iu/ext/Xqciint.yaml @@ -134,6 +134,19 @@ versions: changes: - Fix desciption of qc.c.eir instruction to match IDL code and functionality requires: { name: Zca, version: ">= 1.0.0" } +- version: "0.10.0" + state: frozen + ratification_date: null + contributors: + - name: Albert Yosher + company: Qualcomm Technologies, Inc. + email: ayosher@qti.qualcomm.com + - name: Derek Hower + company: Qualcomm Technologies, Inc. + email: dhower@qti.qualcomm.com + changes: + - Fix IDL code of qc.c.mileaveret instruction to avoid restoring from stack NMIP and EXCP bits + requires: { name: Zca, version: ">= 1.0.0" } description: | The Xqciint extension includes eleven instructions to accelerate interrupt servicing by performing common actions during ISR prologue/epilogue. diff --git a/arch_overlay/qc_iu/inst/Xqci/qc.c.mileaveret.yaml b/arch_overlay/qc_iu/inst/Xqci/qc.c.mileaveret.yaml index 27f97e4a5a..789e449357 100644 --- a/arch_overlay/qc_iu/inst/Xqci/qc.c.mileaveret.yaml +++ b/arch_overlay/qc_iu/inst/Xqci/qc.c.mileaveret.yaml @@ -27,8 +27,11 @@ operation(): | XReg prev_retpc = read_memory<32>(virtual_address - 4, $encoding); XReg qc_mcause_val = read_memory<32>(virtual_address - 12, $encoding); Bits<1> nmie_val = CSR[mnstatus].NMIE; + XReg qc_mcause_prev_val = CSR[qc.mcause].sw_read(); + XReg qc_mcause_nmip_excp_mask = (32'b1 << 24) | (32'b1 << 25); + XReg qc_mcause_new_val = (qc_mcause_val & ~qc_mcause_nmip_excp_mask) | (qc_mcause_prev_val & qc_mcause_nmip_excp_mask); + CSR[qc.mcause].sw_write(qc_mcause_new_val); X[ 8] = read_memory<32>(virtual_address - 8, $encoding); - CSR[qc.mcause].sw_write(qc_mcause_val); X[ 1] = read_memory<32>(virtual_address - 16, $encoding); X[ 5] = read_memory<32>(virtual_address - 24, $encoding); X[ 6] = read_memory<32>(virtual_address - 28, $encoding); @@ -47,7 +50,7 @@ operation(): | X[31] = read_memory<32>(virtual_address - 80, $encoding); X[2] = X[2] + 96; if (nmie_val == 1'b1) { - XReg qc_mcause_val_masked = qc_mcause_val & ~(32'b1<<26) & ~(32'b1<<27) & ~(32'b1<<29) & ~(32'hFF<<12); + XReg qc_mcause_val_masked = qc_mcause_new_val & ~(32'b1<<26) & ~(32'b1<<27) & ~(32'b1<<29) & ~(32'hFF<<12); Bits<1> mpie_val = (qc_mcause_val >> 27) & 1; Bits<1> mpdt_val = (qc_mcause_val >> 29) & 1; Bits<4> mpil_val = (qc_mcause_val >> 16) & 0xF; @@ -74,7 +77,7 @@ operation(): | } $pc = CSR[mepc].sw_read(); } else { - XReg qc_mcause_val_masked = qc_mcause_val & ~(32'b1<<26) & ~(32'b1<<28) & ~(32'b1<<30) & ~(32'b1111<<12) & ~(32'b1111<<20); + XReg qc_mcause_val_masked = qc_mcause_new_val & ~(32'b1<<26) & ~(32'b1<<28) & ~(32'b1<<30) & ~(32'b1111<<12) & ~(32'b1111<<20); Bits<1> mnpie_val = (qc_mcause_val >> 28) & 1; Bits<4> mnpil_val = (qc_mcause_val >> 20) & 0xF; CSR[mstatus].MIE = mnpie_val; diff --git a/arch_overlay/qc_iu/inst/Xqci/qc.csrrwr.yaml b/arch_overlay/qc_iu/inst/Xqci/qc.csrrwr.yaml index 4edaa962e4..7be9106d25 100644 --- a/arch_overlay/qc_iu/inst/Xqci/qc.csrrwr.yaml +++ b/arch_overlay/qc_iu/inst/Xqci/qc.csrrwr.yaml @@ -12,6 +12,8 @@ description: | The initial value in `rs1` is written to the CSR. If `rd`=`x0`, then the instruction shall not read the CSR and shall not cause any of the side effects that might occur on a CSR read. + If `rs1`=`x0`, then the instruction shall not write to the CSR and shall not + cause any of the side effects that might occur on a CSR write. Instruction encoded in R instruction format. definedBy: anyOf: @@ -40,6 +42,8 @@ operation(): | if (rd != 0) { X[rd] = csr_sw_read(csr); } - # writes the value in X[rs1] to the CSR, - # performing any WARL transformations first - csr_sw_write(csr, X[rs1]); + if (rs1 != 0) { + # writes the value in X[rs1] to the CSR, + # performing any WARL transformations first + csr_sw_write(csr, X[rs1]); + }