diff --git a/antora/build-trigger.txt b/antora/build-trigger.txt index 39f1d8c7f..edb4c603f 100644 --- a/antora/build-trigger.txt +++ b/antora/build-trigger.txt @@ -2,4 +2,4 @@ This is a file you can change when all you want to do is trigger a full rebuild It's useful when you've been fixing up antora sources elsewhere and want to see your changes pulled in. -Rebuildd \ No newline at end of file +Rebuilddd \ No newline at end of file diff --git a/antora/build/docs/reference/isa/index.html b/antora/build/docs/reference/isa/index.html index e8729f4d3..9724e5cf5 100644 --- a/antora/build/docs/reference/isa/index.html +++ b/antora/build/docs/reference/isa/index.html @@ -3,9 +3,9 @@ - Untitled :: RISC-V Ratified Specifications Library - - + RISC-V Reference Library :: RISC-V Ratified Specifications Library + + + - - -
- -
+
-

See also [rnmi] for semantics added to the RNMI trap and the MNRET instruction +

See also "Smrnmi" Extension for Resumable Non-Maskable Interrupts for semantics added to the RNMI trap and the MNRET instruction when this extension is implemented.

@@ -941,8 +889,6 @@

Shadow Stack Memory Protection<

- - -
-

Control and Status Registers (CSRs)

+

Control and Status Registers (CSRs)

+

The SYSTEM major opcode is used to encode all privileged instructions in @@ -389,6 +335,8 @@

Control and Status Re

Standard CSRs do not have side effects on reads but may have side effects on writes.

+
+

CSR Address Mapping Conventions

@@ -424,7 +372,7 @@

[sec:hcauses], virtual-instruction exceptions. +Trap Cause Codes, virtual-instruction exceptions. Attempts to write a read-only register raise illegal-instruction exceptions. A read/write register might also contain some bits that are read-only, in which case writes to the read-only bits are ignored.

@@ -2592,7 +2540,7 @@

CSR Width Modulation

If the width of a CSR is changed (for example, by changing SXLEN or -UXLEN, as described in [xlen-control]), the +UXLEN, as described in Base ISA Control in mstatus Register), the values of the writable fields and bits of the new-width CSR are, unless specified otherwise, determined from the previous-width CSR as though by this algorithm:

@@ -2652,8 +2600,6 @@

Introduction Machine-Level ISA, Version 1.13 diff --git a/antora/build/docs/reference/isa/priv/priv-history.html b/antora/build/docs/reference/isa/priv/priv-history.html index 1eeff2ebd..e1ff8b33d 100644 --- a/antora/build/docs/reference/isa/priv/priv-history.html +++ b/antora/build/docs/reference/isa/priv/priv-history.html @@ -3,10 +3,10 @@ - Untitled :: RISC-V Ratified Specifications Library + History :: RISC-V Ratified Specifications Library - + + - - -
- -
+
-
-

Preface

-
+

Preface

Preface to Document Version 20250508

@@ -1768,10 +1712,8 @@

Preface

-
-

diff --git a/antora/build/docs/reference/isa/unpriv/counters.html b/antora/build/docs/reference/isa/unpriv/counters.html index a1fd4b8a4..8201c2c5c 100644 --- a/antora/build/docs/reference/isa/unpriv/counters.html +++ b/antora/build/docs/reference/isa/unpriv/counters.html @@ -3,10 +3,10 @@ - Untitled :: RISC-V Ratified Specifications Library + "Zicntr" and "Zihpm" Extensions for Counters, Version 2.0 :: RISC-V Ratified Specifications Library - + + - - -
- -
+
-
-
-

"D" Extension for Double-Precision Floating-Point, Version 2.2

+

"D" Extension for Double-Precision Floating-Point, Version 2.2

+

This chapter describes the standard double-precision floating-point @@ -374,11 +320,13 @@

D Register State

The D extension widens the 32 floating-point registers, f0-f31, to -64 bits (FLEN=64 in [fprs]. The f registers can +64 bits (FLEN=64 in F extension single-precision floating-point state. The f registers can now hold either 32-bit or 64-bit floating-point values as described below in NaN Boxing of Narrower Values.

@@ -684,8 +632,6 @@

Double-Precision Fl

-
- -
-

"F" Extension for Single-Precision Floating-Point, Version 2.2

+

"F" Extension for Single-Precision Floating-Point, Version 2.2

+

This chapter describes the standard instruction-set extension for @@ -371,6 +317,8 @@

"F" Extension f single-precision floating-point computational instructions compliant with the IEEE 754-2008 arithmetic standard cite:[ieee754-2008]. The F extension depends on the "Zicsr" extension for control and status register access.

+
+

F Register State

@@ -835,7 +783,7 @@

-

As described in [ldst], the execution environment defines whether misaligned floating-point loads and stores are handled invisibly or raise a contained or fatal trap.

+

As described in SP load and store, the execution environment defines whether misaligned floating-point loads and stores are handled invisibly or raise a contained or fatal trap.

@@ -934,17 +882,17 @@

FMADD.S multiplies the values in rs1 and rs2, adds the value in -rs3, and writes the final result to rd. FMADD.S computes (rs1 rs2)( Undefined control sequence \+ rs3).

+rs3, and writes the final result to rd. FMADD.S computes (rs1 rs2) + rs3.

FMSUB.S multiplies the values in rs1 and rs2, subtracts the value in rs3, and writes the final result to rd. FMSUB.S computes -(rs1 rs2) Undefined control sequence \- rs3.

+(rs1 rs2) - rs3.

-

FNMSUB.S multiplies the values in rs1 and rs2, negates the product, adds the value in rs3, and writes the final result to rd. FNMSUB.S computes -(rs1 rs2) Undefined control sequence \+ rs3.

+

FNMSUB.S multiplies the values in rs1 and rs2, negates the product, adds the value in rs3, and writes the final result to rd. FNMSUB.S computes (rs1 rs2)+ rs3.

-

FNMADD.S multiplies the values in rs1 and rs2, negates the product, subtracts the value in rs3, and writes the final result to rd. FNMADD.S computes -(rs1 rs2) Undefined control sequence \- rs3.

+

FNMADD.S multiplies the values in rs1 and rs2, negates the product, subtracts the value in rs3, and writes the final result to rd. FNMADD.S computes -(rs1 rs2) - rs3.

@@ -1302,8 +1250,6 @@

-

- -
-

Introduction

+

Introduction

+

RISC-V (pronounced "risk-five") is a new instruction-set architecture @@ -492,6 +438,8 @@

Introduction

+
+

RISC-V Hardware Platform Terminology

@@ -1315,8 +1263,6 @@

Preface RV32I Base Integer Instruction Set diff --git a/antora/build/docs/reference/isa/unpriv/m-st-ext.html b/antora/build/docs/reference/isa/unpriv/m-st-ext.html index cff17f99a..5e2a77f77 100644 --- a/antora/build/docs/reference/isa/unpriv/m-st-ext.html +++ b/antora/build/docs/reference/isa/unpriv/m-st-ext.html @@ -3,10 +3,10 @@ - Untitled :: RISC-V Ratified Specifications Library + "M" Extension for Integer Multiplication and Division, Version 2.0 :: RISC-V Ratified Specifications Library - + + - - -
- -
+