diff --git a/antora/build-trigger.txt b/antora/build-trigger.txt index edb4c603f..39f1d8c7f 100644 --- a/antora/build-trigger.txt +++ b/antora/build-trigger.txt @@ -2,4 +2,4 @@ This is a file you can change when all you want to do is trigger a full rebuild It's useful when you've been fixing up antora sources elsewhere and want to see your changes pulled in. -Rebuilddd \ No newline at end of file +Rebuildd \ No newline at end of file diff --git a/antora/build/docs/reference/isa/index.html b/antora/build/docs/reference/isa/index.html index 9724e5cf5..e8729f4d3 100644 --- a/antora/build/docs/reference/isa/index.html +++ b/antora/build/docs/reference/isa/index.html @@ -3,9 +3,9 @@ - RISC-V Reference Library :: RISC-V Ratified Specifications Library - - + Untitled :: RISC-V Ratified Specifications Library + + - -
+ + +
+ +
-

See also "Smrnmi" Extension for Resumable Non-Maskable Interrupts for semantics added to the RNMI trap and the MNRET instruction +

See also [rnmi] for semantics added to the RNMI trap and the MNRET instruction when this extension is implemented.

@@ -889,6 +941,8 @@

Shadow Stack Memory Protection<

+ + -

Control and Status Registers (CSRs)

-
+
+

Control and Status Registers (CSRs)

The SYSTEM major opcode is used to encode all privileged instructions in @@ -335,8 +389,6 @@

Standard CSRs do not have side effects on reads but may have side effects on writes.

-
-

CSR Address Mapping Conventions

@@ -372,7 +424,7 @@

Trap Cause Codes, virtual-instruction exceptions. +[sec:hcauses], virtual-instruction exceptions. Attempts to write a read-only register raise illegal-instruction exceptions. A read/write register might also contain some bits that are read-only, in which case writes to the read-only bits are ignored.

@@ -2540,7 +2592,7 @@

CSR Width Modulation

If the width of a CSR is changed (for example, by changing SXLEN or -UXLEN, as described in Base ISA Control in mstatus Register), the +UXLEN, as described in [xlen-control]), the values of the writable fields and bits of the new-width CSR are, unless specified otherwise, determined from the previous-width CSR as though by this algorithm:

@@ -2600,6 +2652,8 @@

Introduction Machine-Level ISA, Version 1.13 diff --git a/antora/build/docs/reference/isa/priv/priv-history.html b/antora/build/docs/reference/isa/priv/priv-history.html index e1ff8b33d..1eeff2ebd 100644 --- a/antora/build/docs/reference/isa/priv/priv-history.html +++ b/antora/build/docs/reference/isa/priv/priv-history.html @@ -3,10 +3,10 @@ - History :: RISC-V Ratified Specifications Library + Untitled :: RISC-V Ratified Specifications Library - + - -
+ + +
+ +
+

History

+

Research Funding at UC Berkeley

@@ -342,6 +398,8 @@

RISC-V Privileged Instruction Set Listings Bibliography diff --git a/antora/build/docs/reference/isa/priv/priv-index.html b/antora/build/docs/reference/isa/priv/priv-index.html index 24e98aa58..5e18d9fce 100644 --- a/antora/build/docs/reference/isa/priv/priv-index.html +++ b/antora/build/docs/reference/isa/priv/priv-index.html @@ -6,7 +6,7 @@ Untitled :: RISC-V Ratified Specifications Library - + - -
+ + +
+ +
-

"Smrnmi" Extension for Resumable Non-Maskable Interrupts, Version 1.0

-
+
+

"Smrnmi" Extension for Resumable Non-Maskable Interrupts, Version 1.0

The base machine-level architecture supports only unresumable @@ -325,8 +379,6 @@ mnstatus, and mnscratch) to hold the interrupted state, and one new instruction, MNRET, to resume from the RNMI handler.

-
-

RNMI Interrupt Signals

@@ -516,7 +568,7 @@

MNRET virtualization mode of the interrupted context. This instruction also sets mnstatus.NMIE. If MNRET changes the privilege mode to a mode less privileged than M, it also sets mstatus.MPRV to 0. If the Zicfilp extension is implemented, then if the new privileged mode -is y, MNRET sets ELP to the logical AND of yLPE (see Landing-Pad-Enabled (LPE) State) and mnstatus.MNPELP.

+is y, MNRET sets ELP to the logical AND of yLPE (see [FCFIACT]) and mnstatus.MNPELP.

@@ -557,6 +609,8 @@

RNMI Operat

+

+
-

"Smcdeleg/Ssccfg" Counter Delegation Extensions, Version 1.0

-
+
+

"Smcdeleg/Ssccfg" Counter Delegation Extensions, Version 1.0

In modern “Rich OS” environments, hardware performance monitoring @@ -350,8 +404,6 @@ supervisor-level state. For a RISC-V hardware platform, Smcdeleg and Ssccfg must always be implemented in tandem.

-
-

Counter Delegation

@@ -573,6 +625,8 @@

"Smrnmi" Extension for Resumable Non-Maskable Interrupts, Version 1.0 "Smdbltrp" Double Trap Extension, Version 1.0 diff --git a/antora/build/docs/reference/isa/priv/smcntrpmf.html b/antora/build/docs/reference/isa/priv/smcntrpmf.html index 7b406f404..90c4e5f02 100644 --- a/antora/build/docs/reference/isa/priv/smcntrpmf.html +++ b/antora/build/docs/reference/isa/priv/smcntrpmf.html @@ -3,10 +3,10 @@ - "Smcntrpmf" Cycle and Instret Privilege Mode Filtering, Version 1.0 :: RISC-V Ratified Specifications Library - + Untitled :: RISC-V Ratified Specifications Library + - + - -
+ + +
+ +
+

"Smcntrpmf" Cycle and Instret Privilege Mode Filtering, Version 1.0

+

Introduction

@@ -476,8 +532,10 @@

Counter

+
+
diff --git a/antora/build/docs/reference/isa/priv/smctr.html b/antora/build/docs/reference/isa/priv/smctr.html index ba6448195..2bc317cf4 100644 --- a/antora/build/docs/reference/isa/priv/smctr.html +++ b/antora/build/docs/reference/isa/priv/smctr.html @@ -3,10 +3,10 @@ - "Smctr" Control Transfer Records Extension, Version 1.0 :: RISC-V Ratified Specifications Library + Untitled :: RISC-V Ratified Specifications Library - + - -
+ + +
+ +

"Smdbltrp" Double Trap Extension, Version 1.0

+
+

"Smdbltrp" Double Trap Extension, Version 1.0

+
-

The Smdbltrp extension addresses a double trap (See Double Trap Control in mstatus Register) in -M-mode. When the Smrnmi extension ("Smrnmi" Extension for Resumable Non-Maskable Interrupts) is implemented, it enables +

The Smdbltrp extension addresses a double trap (See [machine-double-trap]) in +M-mode. When the Smrnmi extension ([rnmi]) is implemented, it enables invocation of the RNMI handler on a double trap in M-mode to handle the critical error. If the Smrnmi extension is not implemented or if a double trap occurs during the RNMI handler’s execution, this extension helps transition the @@ -325,7 +381,9 @@ hart is in a critical error state. See cite:[DEBUG_SPEC] for details.

-

See Double Trap Control in mstatus Register for the operational details.

+

See [machine-double-trap] for the operational details.

+
+
-

"Smstateen/Ssstateen" Extensions, Version 1.0

-
+
+

"Smstateen/Ssstateen" Extensions, Version 1.0

The implementation of optional RISC-V extensions has the potential to open @@ -355,8 +409,6 @@ threads, making them a less-than-compelling candidate for inclusion in sstatus. Hence, a new place is provided for them instead.

-
-

State Enable Extensions

@@ -739,6 +791,8 @@

Usage

+
+

-

"Sscofpmf" Extension for Count Overflow and Mode-Based Filtering, Version 1.0

-
+
+

"Sscofpmf" Extension for Count Overflow and Mode-Based Filtering, Version 1.0

The current Privileged specification defines mhpmevent CSRs to select and @@ -341,8 +395,6 @@

Note that the new count overflow interrupt will be treated as a standard local interrupt that is assigned to bit 13 in the mip/mie/sip/sie registers.

-
-

Count Overflow Control

@@ -537,6 +589,8 @@

"Sstc" Extension for Supervisor-mode Timer Interrupts, Version 1.0 "H" Extension for Hypervisor Support, Version 1.0 diff --git a/antora/build/docs/reference/isa/priv/ssdbltrp.html b/antora/build/docs/reference/isa/priv/ssdbltrp.html index f930ccbd3..64f67291d 100644 --- a/antora/build/docs/reference/isa/priv/ssdbltrp.html +++ b/antora/build/docs/reference/isa/priv/ssdbltrp.html @@ -3,10 +3,10 @@ - "Ssdbltrp" Double Trap Extension, Version 1.0 :: RISC-V Ratified Specifications Library + Untitled :: RISC-V Ratified Specifications Library - + - -
+ + +
+ +
+

"Ssdbltrp" Double Trap Extension, Version 1.0

+
-

The Ssdbltrp extension addresses a double trap (See Double Trap Control in mstatus Register) +

The Ssdbltrp extension addresses a double trap (See [machine-double-trap]) privilege modes lower than M. It enables HS-mode to invoke a critical error handler in a virtual machine on a double trap in VS-mode. It also allows M-mode to invoke a critical error handler in the OS/Hypervisor on a double trap in S/HS-mode.

-

The Ssdbltrp extension adds the menvcfg.DTE (See Machine Environment Configuration (menvcfg) Register) and the +

The Ssdbltrp extension adds the menvcfg.DTE (See [sec:menvcfg]) and the sstatus.SDT fields (See [sstatus]). If the hypervisor extension is additionally implemented, then the extension adds the henvcfg.DTE (See -Hypervisor Environment Configuration Register (henvcfg)) and the vsstatus.SDT fields (See Virtual Supervisor Status (vsstatus) Register).

+[sec:henvcfg]) and the vsstatus.SDT fields (See [vsstatus]).

-

See Double Trap Control in sstatus Register for the operational details.

+

See [supv-double-trap] for the operational details.

+
+
-

"Sstc" Extension for Supervisor-mode Timer Interrupts, Version 1.0

-
+
+

"Sstc" Extension for Supervisor-mode Timer Interrupts, Version 1.0

The current Privileged arch specification only defines a hardware mechanism for @@ -334,8 +388,6 @@ extensions, and 'tc' for timecmp). This extension adds the S-level stimecmp CSR and the VS-level vstimecmp CSR.

-
-

Machine and Supervisor Level Additions

@@ -560,6 +612,8 @@

Supervisor-Level ISA, Version 1.13 "Sscofpmf" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 diff --git a/antora/build/docs/reference/isa/priv/supervisor.html b/antora/build/docs/reference/isa/priv/supervisor.html index 603a0755e..414f2ca24 100644 --- a/antora/build/docs/reference/isa/priv/supervisor.html +++ b/antora/build/docs/reference/isa/priv/supervisor.html @@ -3,10 +3,10 @@ - Supervisor-Level ISA, Version 1.13 :: RISC-V Ratified Specifications Library + Untitled :: RISC-V Ratified Specifications Library - + - -
+ + +
+ +
+
-

"B" Extension for Bit Manipulation, Version 1.0.0

-
+
+

"B" Extension for Bit Manipulation, Version 1.0.0

The B standard extension comprises instructions provided by the Zba, Zbb, and Zbs extensions.

-
-

Zb* Overview

@@ -5516,6 +5568,8 @@

strcmp

+
+
-

"BF16" Extensions for BFloat16-precision Floating-Point, Version 1.0

+
+

"BF16" Extensions for BFloat16-precision Floating-Point, Version 1.0

+

Introduction

@@ -817,7 +873,7 @@

Zfbfmin - Sc

This extension includes six instructions: the FCVT.BF16.S and FCVT.S.BF16 instructions, defined below, and the FLH, FSH, FMV.X.H, and FMV.H.X -instructions, defined in "Zfh" and "Zfhmin" Extensions for Half-Precision Floating-Point.

+instructions, defined in [chap:zfh].

@@ -1509,6 +1565,8 @@

Bibliography754-2008 - IEEE Standard for Floating-Point Arithmetic

+ + -

"C" Extension for Compressed Instructions, Version 2.0

-
+
+

"C" Extension for Compressed Instructions, Version 2.0

This chapter describes the RISC-V standard compressed instruction-set @@ -320,8 +374,6 @@ 50%-60% of the RISC-V instructions in a program can be replaced with RVC instructions, resulting in a 25%-30% code-size reduction.

-
-

Overview

@@ -1598,7 +1650,7 @@

HINT Instructions

A portion of the RVC encoding space is reserved for microarchitectural HINTs. Like the HINTs in the RV32I base ISA (see -"Zfh" and "HINT Instructions), these instructions do not +[rv32i-hints]), these instructions do not modify any architectural state, except for advancing the pc and any applicable performance counters. HINTs are executed as no-ops on implementations that ignore them.

@@ -1848,6 +1900,8 @@

Figure 3. Instruction listing for RVC, Quadrant 2

+ + -

Calling Convention for Vector State (Not authoritative - Placeholder Only)

+
+

Appendix A: Calling Convention for Vector State (Not authoritative - Placeholder Only)

+
@@ -380,6 +436,8 @@
+

+
-

"CMO" Extensions for Base Cache Management Operation ISA, Version 1.0.0

+
+

"CMO" Extensions for Base Cache Management Operation ISA, Version 1.0.0

+

Pseudocode for instruction semantics

@@ -1970,6 +2026,8 @@

prefetc

+
+
-

Preface

+
+

Preface

+

Preface to Document Version 20250508

@@ -1712,8 +1768,10 @@
+
+

diff --git a/antora/build/docs/reference/isa/unpriv/counters.html b/antora/build/docs/reference/isa/unpriv/counters.html index 8201c2c5c..a1fd4b8a4 100644 --- a/antora/build/docs/reference/isa/unpriv/counters.html +++ b/antora/build/docs/reference/isa/unpriv/counters.html @@ -3,10 +3,10 @@ - "Zicntr" and "Zihpm" Extensions for Counters, Version 2.0 :: RISC-V Ratified Specifications Library + Untitled :: RISC-V Ratified Specifications Library - + - -
+ + +
+ +
+
-

"D" Extension for Double-Precision Floating-Point, Version 2.2

-
+
+

"D" Extension for Double-Precision Floating-Point, Version 2.2

This chapter describes the standard double-precision floating-point @@ -320,13 +374,11 @@

-
-

D Register State

The D extension widens the 32 floating-point registers, f0-f31, to -64 bits (FLEN=64 in F extension single-precision floating-point state. The f registers can +64 bits (FLEN=64 in [fprs]. The f registers can now hold either 32-bit or 64-bit floating-point values as described below in NaN Boxing of Narrower Values.

@@ -632,6 +684,8 @@

Double-Precision Fl

+ + -

"F" Extension for Single-Precision Floating-Point, Version 2.2

-
+
+

"F" Extension for Single-Precision Floating-Point, Version 2.2

This chapter describes the standard instruction-set extension for @@ -317,8 +371,6 @@ single-precision floating-point computational instructions compliant with the IEEE 754-2008 arithmetic standard cite:[ieee754-2008]. The F extension depends on the "Zicsr" extension for control and status register access.

-
-

F Register State

@@ -783,7 +835,7 @@

-

As described in SP load and store, the execution environment defines whether misaligned floating-point loads and stores are handled invisibly or raise a contained or fatal trap.

+

As described in [ldst], the execution environment defines whether misaligned floating-point loads and stores are handled invisibly or raise a contained or fatal trap.

@@ -882,17 +934,17 @@

FMADD.S multiplies the values in rs1 and rs2, adds the value in -rs3, and writes the final result to rd. FMADD.S computes (rs1 rs2) + rs3.

+rs3, and writes the final result to rd. FMADD.S computes (rs1 rs2)( Undefined control sequence \+ rs3).

FMSUB.S multiplies the values in rs1 and rs2, subtracts the value in rs3, and writes the final result to rd. FMSUB.S computes -(rs1 rs2) - rs3.

+(rs1 rs2) Undefined control sequence \- rs3.

-

FNMSUB.S multiplies the values in rs1 and rs2, negates the product, adds the value in rs3, and writes the final result to rd. FNMSUB.S computes (rs1 rs2)+ rs3.

+

FNMSUB.S multiplies the values in rs1 and rs2, negates the product, adds the value in rs3, and writes the final result to rd. FNMSUB.S computes -(rs1 rs2) Undefined control sequence \+ rs3.

-

FNMADD.S multiplies the values in rs1 and rs2, negates the product, subtracts the value in rs3, and writes the final result to rd. FNMADD.S computes -(rs1 rs2) - rs3.

+

FNMADD.S multiplies the values in rs1 and rs2, negates the product, subtracts the value in rs3, and writes the final result to rd. FNMADD.S computes -(rs1 rs2) Undefined control sequence \- rs3.

@@ -1250,6 +1302,8 @@

+

+ -

Introduction

-
+
+

Introduction

RISC-V (pronounced "risk-five") is a new instruction-set architecture @@ -438,8 +492,6 @@

-
-

RISC-V Hardware Platform Terminology

@@ -1263,6 +1315,8 @@

Preface RV32I Base Integer Instruction Set diff --git a/antora/build/docs/reference/isa/unpriv/m-st-ext.html b/antora/build/docs/reference/isa/unpriv/m-st-ext.html index 5e2a77f77..cff17f99a 100644 --- a/antora/build/docs/reference/isa/unpriv/m-st-ext.html +++ b/antora/build/docs/reference/isa/unpriv/m-st-ext.html @@ -3,10 +3,10 @@ - "M" Extension for Integer Multiplication and Division, Version 2.0 :: RISC-V Ratified Specifications Library + Untitled :: RISC-V Ratified Specifications Library - + - -
+ + +
+ +