diff --git a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_reserved_svnapot_S_mode.S b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_reserved_svnapot_S_mode.S index c715122efb..a3f20f0241 100644 --- a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_reserved_svnapot_S_mode.S +++ b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_reserved_svnapot_S_mode.S @@ -30,7 +30,7 @@ RVMODEL_BOOT RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",add_feature) + RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*S.*Zicsr.*); check ISA:=regex(^((?!Svnapot).)*$); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",add_feature) RVTEST_SIGBASE( x13,signature_x13_1) # --------------------------------------------------------------------------------------------- diff --git a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_reserved_svpbmt_S_mode.S b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_reserved_svpbmt_S_mode.S index ab5c8cde59..5fac0f1d46 100644 --- a/riscv-test-suite/rv64i_m/vm_sv39/src/vm_reserved_svpbmt_S_mode.S +++ b/riscv-test-suite/rv64i_m/vm_sv39/src/vm_reserved_svpbmt_S_mode.S @@ -55,7 +55,7 @@ starting_point: RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",add_feature) + RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*S.*Zicsr.*); check ISA:=regex(^((?!Svpbmt).)*$); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV39_MACROS",add_feature) RVTEST_SIGBASE( x13,signature_x13_1) # --------------------------------------------------------------------------------------------- diff --git a/riscv-test-suite/rv64i_m/vm_sv48/src/sv48_reserved_svnapot_S_mode.S b/riscv-test-suite/rv64i_m/vm_sv48/src/sv48_reserved_svnapot_S_mode.S index 3c3b0bc00f..11de427cf5 100644 --- a/riscv-test-suite/rv64i_m/vm_sv48/src/sv48_reserved_svnapot_S_mode.S +++ b/riscv-test-suite/rv64i_m/vm_sv48/src/sv48_reserved_svnapot_S_mode.S @@ -30,7 +30,7 @@ RVMODEL_BOOT RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True", sv48_tests) + RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*S.*Zicsr.*); check ISA:=regex(^((?!Svnapot).)*$); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True", sv48_tests) RVTEST_SIGBASE( x13,signature_x13_1) # --------------------------------------------------------------------------------------------- diff --git a/riscv-test-suite/rv64i_m/vm_sv48/src/sv48_reserved_svpbmt_S_mode.S b/riscv-test-suite/rv64i_m/vm_sv48/src/sv48_reserved_svpbmt_S_mode.S index 2638333516..c3d840f049 100644 --- a/riscv-test-suite/rv64i_m/vm_sv48/src/sv48_reserved_svpbmt_S_mode.S +++ b/riscv-test-suite/rv64i_m/vm_sv48/src/sv48_reserved_svpbmt_S_mode.S @@ -54,7 +54,7 @@ starting_point: RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True", sv48_tests) + RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*S.*Zicsr.*); check ISA:=regex(^((?!Svpbmt).)*$); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True", sv48_tests) RVTEST_SIGBASE( x13,signature_x13_1) # --------------------------------------------------------------------------------------------- diff --git a/riscv-test-suite/rv64i_m/vm_sv57/src/sv57_reserved_svnapot_S_mode.S b/riscv-test-suite/rv64i_m/vm_sv57/src/sv57_reserved_svnapot_S_mode.S index e94ea47b02..2c01020425 100644 --- a/riscv-test-suite/rv64i_m/vm_sv57/src/sv57_reserved_svnapot_S_mode.S +++ b/riscv-test-suite/rv64i_m/vm_sv57/src/sv57_reserved_svnapot_S_mode.S @@ -30,7 +30,7 @@ RVMODEL_BOOT RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True", sv57_tests) + RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*S.*Zicsr.*); check ISA:=regex(^((?!Svnapot).)*$); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True", sv57_tests) RVTEST_SIGBASE( x13,signature_x13_1) # --------------------------------------------------------------------------------------------- diff --git a/riscv-test-suite/rv64i_m/vm_sv57/src/sv57_reserved_svpbmt_S_mode.S b/riscv-test-suite/rv64i_m/vm_sv57/src/sv57_reserved_svpbmt_S_mode.S index 240b966135..1343c289d9 100644 --- a/riscv-test-suite/rv64i_m/vm_sv57/src/sv57_reserved_svpbmt_S_mode.S +++ b/riscv-test-suite/rv64i_m/vm_sv57/src/sv57_reserved_svpbmt_S_mode.S @@ -54,7 +54,7 @@ starting_point: RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*S.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True", sv57_tests) + RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*S.*Zicsr.*); check ISA:=regex(^((?!Svpbmt).)*$); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True", sv57_tests) RVTEST_SIGBASE( x13,signature_x13_1) # ---------------------------------------------------------------------------------------------