diff --git a/src/cheri/riscv-hybrid-integration.adoc b/src/cheri/riscv-hybrid-integration.adoc
index 40545493d..59a5a695e 100644
--- a/src/cheri/riscv-hybrid-integration.adoc
+++ b/src/cheri/riscv-hybrid-integration.adoc
@@ -34,8 +34,10 @@ NOTE: Instructions which are _modified_ on an {cheri_base_ext_name} architecture
 All <<rvy_insn_table>> instructions, and associated CSRs, are available in addition to RVI/RVE and all supported non-CHERI extensions.
 +
 The authorizing capability for memory access is <<ddc>> (as opposed to `rs1`).
-That is, all memory accesses, including <<PREFETCH_W_CHERI>> and <<PREFETCH_R_CHERI>>, are implicitly authorized by <<ddc>> and only the memory address is sourced from `rs1`.
-<<PREFETCH_I_CHERI>> is the exception to this rule, as <<pcc>> authorizes it.
+That is, all memory accesses, including <<PREFETCH_W_CHERI>>, <<PREFETCH_R_CHERI>> are implicitly authorized by <<ddc>> and only the memory address is sourced from `rs1`.
++
+NOTE: It is recommended to authorize the prefetched address of <<PREFETCH_I_CHERI>> against <<pcc>> instead of <<ddc>>.
+ High performance implementations may not have access to the <<pcc>> available to perform this check, as <<pcc>> bounds are not otherwise required in the load/store unit.
 +
 NOTE: <<ddc>> is also used to authorize {cheri_base_ext_name} specific memory instructions such as <<LOAD_CAP>> and <<STORE_CAP>>.
 +